Make flashload COM more reliable #25
@ -1,12 +1,10 @@
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#!/usr/bin/env python3
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from spacepackets.ecss import RequestId
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from spacepackets.ecss.defs import PusService
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from spacepackets.ecss.tm import PusTm
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import toml
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import struct
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import logging
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import argparse
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import threading
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import time
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import enum
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from tmtccmd.com.serial_base import SerialCfg
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@ -45,6 +43,7 @@ ACTION_SERVICE = 8
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RAW_MEMORY_WRITE_SUBSERVICE = 2
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BOOT_NVM_MEMORY_ID = 1
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PING_PAYLOAD_SIZE = 0
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class ActionId(enum.IntEnum):
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@ -104,6 +103,29 @@ def main() -> int:
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com_if = SerialCobsComIF(serial_cfg)
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com_if.open()
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file_path = None
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if args.ping:
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_LOGGER.info("Sending ping command")
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ping_tc = PusTc(
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apid=0x00,
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service=PusService.S17_TEST,
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subservice=1,
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seq_count=SEQ_PROVIDER.get_and_increment(),
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app_data=bytes(PING_PAYLOAD_SIZE),
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)
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verificator.add_tc(ping_tc)
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com_if.send(ping_tc.pack())
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data_available = com_if.data_available(0.4)
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if not data_available:
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_LOGGER.warning("no ping reply received")
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for reply in com_if.receive():
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result = verificator.add_tm(
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Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0))
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)
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if result is not None and result.completed:
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_LOGGER.info("received ping completion reply")
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if not args.target:
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return 0
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if args.target:
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if not args.corrupt:
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if not args.path:
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@ -113,15 +135,6 @@ def main() -> int:
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if not file_path.exists():
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_LOGGER.error("File does not exist")
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return -1
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if args.ping:
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_LOGGER.info("Sending ping command")
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ping_tc = PusTc(
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apid=0x00,
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service=PusService.S17_TEST,
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subservice=1,
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seq_count=SEQ_PROVIDER.get_and_increment(),
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)
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com_if.send(ping_tc.pack())
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if args.corrupt:
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if not args.target:
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_LOGGER.error("target for corruption command required")
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@ -254,7 +267,7 @@ def main() -> int:
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):
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done = True
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# Still keep a small delay
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time.sleep(0.01)
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# time.sleep(0.05)
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verificator.remove_completed_entries()
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if done:
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break
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@ -18,13 +18,11 @@
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#![no_main]
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#![no_std]
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use embedded_hal_nb::serial::Read;
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use once_cell::sync::OnceCell;
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use panic_rtt_target as _;
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use va416xx_hal::{clock::Clocks, edac, pac, time::Hertz, wdt::Wdt};
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const EXTCLK_FREQ: u32 = 40_000_000;
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const COBS_FRAME_SEPARATOR: u8 = 0x0;
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const MAX_TC_SIZE: usize = 1024;
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const MAX_TC_FRAME_SIZE: usize = cobs::max_encoding_length(MAX_TC_SIZE);
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@ -33,10 +31,8 @@ const MAX_TM_SIZE: usize = 128;
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const MAX_TM_FRAME_SIZE: usize = cobs::max_encoding_length(MAX_TM_SIZE);
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const UART_BAUDRATE: u32 = 115200;
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const SERIAL_RX_WIRETAPPING: bool = false;
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const COBS_RX_DEBUGGING: bool = false;
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const BOOT_NVM_MEMORY_ID: u8 = 1;
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const RX_DEBUGGING: bool = false;
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pub enum ActionId {
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CorruptImageA = 128,
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@ -62,13 +58,24 @@ use ringbuf::{
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CachingCons, StaticProd, StaticRb,
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};
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const BUF_RB_SIZE_TX: usize = 1024;
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const SIZES_RB_SIZE_TX: usize = 16;
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// Larger buffer for TC to be able to hold the possibly large memory write packets.
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const BUF_RB_SIZE_TC: usize = 2048;
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const SIZES_RB_SIZE_TC: usize = 16;
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static mut BUF_RB_TX: Lazy<StaticRb<u8, BUF_RB_SIZE_TX>> =
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Lazy::new(StaticRb::<u8, BUF_RB_SIZE_TX>::default);
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static mut SIZES_RB_TX: Lazy<StaticRb<usize, SIZES_RB_SIZE_TX>> =
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Lazy::new(StaticRb::<usize, SIZES_RB_SIZE_TX>::default);
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const BUF_RB_SIZE_TM: usize = 512;
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const SIZES_RB_SIZE_TM: usize = 16;
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// Ring buffers to handling variable sized telemetry
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static mut BUF_RB_TM: Lazy<StaticRb<u8, BUF_RB_SIZE_TM>> =
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Lazy::new(StaticRb::<u8, BUF_RB_SIZE_TM>::default);
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static mut SIZES_RB_TM: Lazy<StaticRb<usize, SIZES_RB_SIZE_TM>> =
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Lazy::new(StaticRb::<usize, SIZES_RB_SIZE_TM>::default);
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// Ring buffers to handling variable sized telecommands
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static mut BUF_RB_TC: Lazy<StaticRb<u8, BUF_RB_SIZE_TC>> =
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Lazy::new(StaticRb::<u8, BUF_RB_SIZE_TC>::default);
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static mut SIZES_RB_TC: Lazy<StaticRb<usize, SIZES_RB_SIZE_TC>> =
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Lazy::new(StaticRb::<usize, SIZES_RB_SIZE_TC>::default);
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pub struct DataProducer<const BUF_SIZE: usize, const SIZES_LEN: usize> {
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pub buf_prod: StaticProd<'static, u8, BUF_SIZE>,
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@ -91,15 +98,10 @@ pub const APP_B_END_ADDR: u32 = 0x40000;
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mod app {
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use super::*;
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use cortex_m::asm;
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use embedded_hal_nb::nb;
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use embedded_io::Write;
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use panic_rtt_target as _;
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use rtic::Mutex;
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use rtic_monotonics::systick::prelude::*;
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use rtic_sync::{
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channel::{Receiver, Sender},
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make_channel,
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};
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use rtt_target::rprintln;
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use satrs::pus::verification::VerificationReportCreator;
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use spacepackets::ecss::PusServiceId;
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@ -127,26 +129,24 @@ mod app {
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#[local]
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struct Local {
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uart_rx: uart::Rx<pac::Uart0>,
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uart_rx: uart::RxWithIrq<pac::Uart0>,
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uart_tx: uart::Tx<pac::Uart0>,
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cobs_reader_state: CobsReaderStates,
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tc_tx: TcTx,
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tc_rx: TcRx,
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rom_spi: Option<pac::Spi3>,
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tx_cons: DataConsumer<BUF_RB_SIZE_TX, SIZES_RB_SIZE_TX>,
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// We handle all TM in one task.
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tm_cons: DataConsumer<BUF_RB_SIZE_TM, SIZES_RB_SIZE_TM>,
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// We consume all TC in one task.
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tc_cons: DataConsumer<BUF_RB_SIZE_TC, SIZES_RB_SIZE_TC>,
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// We produce all TC in one task.
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tc_prod: DataProducer<BUF_RB_SIZE_TC, SIZES_RB_SIZE_TC>,
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verif_reporter: VerificationReportCreator,
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}
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#[shared]
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struct Shared {
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decode_buffer_busy: bool,
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decode_buf: [u8; MAX_TC_SIZE],
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tx_prod: DataProducer<BUF_RB_SIZE_TX, SIZES_RB_SIZE_TX>,
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// Having this shared allows multiple tasks to generate telemetry.
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tm_prod: DataProducer<BUF_RB_SIZE_TM, SIZES_RB_SIZE_TM>,
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}
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pub type TcTx = Sender<'static, usize, 2>;
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pub type TcRx = Receiver<'static, usize, 2>;
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rtic_monotonics::systick_monotonic!(Mono, 10_000);
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#[init]
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@ -176,38 +176,45 @@ mod app {
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&mut cx.device.sysconfig,
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&clocks,
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);
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let (tx, rx) = uart0.split();
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let (tc_tx, tc_rx) = make_channel!(usize, 2);
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let (tx, mut rx, _) = uart0.split_with_irq();
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let verif_reporter = VerificationReportCreator::new(0).unwrap();
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let (buf_prod, buf_cons) = unsafe { BUF_RB_TX.split_ref() };
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let (sizes_prod, sizes_cons) = unsafe { SIZES_RB_TX.split_ref() };
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let (buf_prod_tm, buf_cons_tm) = unsafe { BUF_RB_TM.split_ref() };
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let (sizes_prod_tm, sizes_cons_tm) = unsafe { SIZES_RB_TM.split_ref() };
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let (buf_prod_tc, buf_cons_tc) = unsafe { BUF_RB_TC.split_ref() };
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let (sizes_prod_tc, sizes_cons_tc) = unsafe { SIZES_RB_TC.split_ref() };
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Mono::start(cx.core.SYST, clocks.sysclk().raw());
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CLOCKS.set(clocks).unwrap();
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rx.read_fixed_len_using_irq(MAX_TC_FRAME_SIZE, true)
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.expect("initiating UART RX failed");
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pus_tc_handler::spawn().unwrap();
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uart_reader_task::spawn().unwrap();
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pus_tm_tx_handler::spawn().unwrap();
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(
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Shared {
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decode_buffer_busy: false,
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decode_buf: [0; MAX_TC_SIZE],
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tx_prod: DataProducer {
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buf_prod,
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sizes_prod,
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tm_prod: DataProducer {
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buf_prod: buf_prod_tm,
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sizes_prod: sizes_prod_tm,
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},
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},
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Local {
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uart_rx: rx,
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uart_tx: tx,
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cobs_reader_state: CobsReaderStates::default(),
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tc_tx,
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tc_rx,
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rom_spi: Some(cx.device.spi3),
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tx_cons: DataConsumer {
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buf_cons,
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sizes_cons,
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tm_cons: DataConsumer {
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buf_cons: buf_cons_tm,
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sizes_cons: sizes_cons_tm,
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},
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tc_cons: DataConsumer {
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buf_cons: buf_cons_tc,
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sizes_cons: sizes_cons_tc,
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},
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tc_prod: DataProducer {
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buf_prod: buf_prod_tc,
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sizes_prod: sizes_prod_tc,
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},
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verif_reporter,
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},
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@ -223,120 +230,62 @@ mod app {
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}
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#[task(
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priority = 4,
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binds = UART0_RX,
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local = [
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read_buf: [u8;MAX_TC_FRAME_SIZE] = [0; MAX_TC_FRAME_SIZE],
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cnt: u32 = 0,
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rx_buf: [u8; MAX_TC_FRAME_SIZE] = [0; MAX_TC_FRAME_SIZE],
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uart_rx,
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cobs_reader_state,
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tc_tx
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tc_prod
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],
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shared=[decode_buffer_busy, decode_buf]
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)]
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async fn uart_reader_task(mut cx: uart_reader_task::Context) {
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let mut current_idx = 0;
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loop {
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match cx.local.uart_rx.read() {
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Ok(byte) => {
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if SERIAL_RX_WIRETAPPING {
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log::debug!("RX Byte: 0x{:x?}", byte);
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}
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handle_single_rx_byte(&mut cx, byte, &mut current_idx)
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}
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Err(e) => {
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match e {
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nb::Error::Other(e) => {
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log::warn!("UART error: {:?}", e);
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match e {
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uart::Error::Overrun => {
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cx.local.uart_rx.clear_fifo();
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}
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uart::Error::FramingError => (),
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uart::Error::ParityError => (),
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uart::Error::BreakCondition => (),
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uart::Error::TransferPending => (),
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uart::Error::BufferTooShort => (),
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}
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}
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nb::Error::WouldBlock => {
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// Delay for a short period before polling again.
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Mono::delay(400.micros()).await;
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}
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}
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fn uart_rx_irq(cx: uart_rx_irq::Context) {
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match cx.local.uart_rx.irq_handler(cx.local.rx_buf) {
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Ok(result) => {
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if RX_DEBUGGING {
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log::debug!("RX Info: {:?}", cx.local.uart_rx.irq_info());
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log::debug!("RX Result: {:?}", result);
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}
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if result.complete() {
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// Check frame validity (must have COBS format) and decode the frame.
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// Currently, we expect a full frame or a frame received through a timeout
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// to be one COBS frame. We could parse for multiple COBS packets in one
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// frame, but the additional complexity is not necessary here..
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if cx.local.rx_buf[0] == 0 && cx.local.rx_buf[result.bytes_read - 1] == 0 {
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let decoded_size =
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cobs::decode_in_place(&mut cx.local.rx_buf[1..result.bytes_read]);
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if decoded_size.is_err() {
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log::warn!("COBS decoding failed");
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} else {
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let decoded_size = decoded_size.unwrap();
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if cx.local.tc_prod.sizes_prod.vacant_len() >= 1
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&& cx.local.tc_prod.buf_prod.vacant_len() >= decoded_size
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{
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// Should never fail, we checked there is enough space.
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cx.local.tc_prod.sizes_prod.try_push(decoded_size).unwrap();
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cx.local
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.tc_prod
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.buf_prod
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.push_slice(&cx.local.rx_buf[1..1 + decoded_size]);
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} else {
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log::warn!("COBS TC queue full");
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}
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}
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} else {
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log::warn!("COBS frame with invalid format, start and end bytes are not 0");
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}
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fn handle_single_rx_byte(
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cx: &mut uart_reader_task::Context,
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byte: u8,
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current_idx: &mut usize,
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) {
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match cx.local.cobs_reader_state {
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CobsReaderStates::WaitingForStart => {
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if byte == COBS_FRAME_SEPARATOR {
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if COBS_RX_DEBUGGING {
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log::debug!("COBS start marker detected");
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// Initiate next transfer.
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cx.local
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.uart_rx
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.read_fixed_len_using_irq(MAX_TC_FRAME_SIZE, true)
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.expect("read operation failed");
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}
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*cx.local.cobs_reader_state = CobsReaderStates::WatingForEnd;
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*current_idx = 0;
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if result.error() {
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log::warn!("UART error: {:?}", result.error());
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}
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}
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CobsReaderStates::WatingForEnd => {
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if byte == COBS_FRAME_SEPARATOR {
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if COBS_RX_DEBUGGING {
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log::debug!("COBS end marker detected");
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}
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let mut sending_failed = false;
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let mut decoding_error = false;
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let mut decode_buffer_busy = false;
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cx.shared.decode_buffer_busy.lock(|busy| {
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if *busy {
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decode_buffer_busy = true;
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} else {
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cx.shared.decode_buf.lock(|buf| {
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match cobs::decode(&cx.local.read_buf[..*current_idx], buf) {
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Ok(packet_len) => {
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if COBS_RX_DEBUGGING {
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log::debug!(
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"COBS decoded packet with length {}",
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packet_len
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);
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}
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if cx.local.tc_tx.try_send(packet_len).is_err() {
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sending_failed = true;
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}
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*busy = true;
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}
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Err(_) => {
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decoding_error = true;
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}
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}
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});
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}
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});
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if sending_failed {
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log::warn!("sending TC packet failed, queue full");
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}
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if decoding_error {
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log::warn!("decoding error");
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}
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if decode_buffer_busy {
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log::warn!("decode buffer busy. data arriving too fast");
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}
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*cx.local.cobs_reader_state = CobsReaderStates::WaitingForStart;
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} else if *current_idx >= cx.local.read_buf.len() {
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*cx.local.cobs_reader_state = CobsReaderStates::FrameOverflow;
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} else {
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cx.local.read_buf[*current_idx] = byte;
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*current_idx += 1;
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}
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}
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CobsReaderStates::FrameOverflow => {
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if byte == COBS_FRAME_SEPARATOR {
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*cx.local.cobs_reader_state = CobsReaderStates::WaitingForStart;
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*current_idx = 0;
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}
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Err(e) => {
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log::warn!("UART error: {:?}", e);
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}
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}
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}
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@ -344,30 +293,48 @@ mod app {
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#[task(
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priority = 2,
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local=[
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read_buf: [u8;MAX_TC_FRAME_SIZE] = [0; MAX_TC_FRAME_SIZE],
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tc_buf: [u8; MAX_TC_SIZE] = [0; MAX_TC_SIZE],
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src_data_buf: [u8; 16] = [0; 16],
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verif_buf: [u8; 32] = [0; 32],
|
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tc_rx,
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tc_cons,
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rom_spi,
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verif_reporter
|
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],
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shared=[decode_buffer_busy, decode_buf, tx_prod]
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shared=[tm_prod]
|
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)]
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async fn pus_tc_handler(mut cx: pus_tc_handler::Context) {
|
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loop {
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let packet_len = cx.local.tc_rx.recv().await.expect("all senders down");
|
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// Try to read a TC from the ring buffer.
|
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let packet_len = cx.local.tc_cons.sizes_cons.try_pop();
|
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if packet_len.is_none() {
|
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// Small delay, TCs might arrive very quickly.
|
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Mono::delay(20.millis()).await;
|
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continue;
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}
|
||||
let packet_len = packet_len.unwrap();
|
||||
log::info!(target: "TC Handler", "received packet with length {}", packet_len);
|
||||
// We still copy the data to a local buffer, so the exchange buffer can already be used
|
||||
// for the next packet / decode process.
|
||||
cx.shared
|
||||
.decode_buf
|
||||
.lock(|buf| cx.local.read_buf[0..buf.len()].copy_from_slice(buf));
|
||||
cx.shared.decode_buffer_busy.lock(|busy| *busy = false);
|
||||
match PusTcReader::new(cx.local.read_buf) {
|
||||
Ok((pus_tc, _)) => {
|
||||
assert_eq!(
|
||||
cx.local
|
||||
.tc_cons
|
||||
.buf_cons
|
||||
.pop_slice(&mut cx.local.tc_buf[0..packet_len]),
|
||||
packet_len
|
||||
);
|
||||
// Read a telecommand, now handle it.
|
||||
handle_valid_pus_tc(&mut cx);
|
||||
}
|
||||
}
|
||||
|
||||
fn handle_valid_pus_tc(cx: &mut pus_tc_handler::Context) {
|
||||
let pus_tc = PusTcReader::new(cx.local.tc_buf);
|
||||
if pus_tc.is_err() {
|
||||
log::warn!("PUS TC error: {}", pus_tc.unwrap_err());
|
||||
return;
|
||||
}
|
||||
let (pus_tc, _) = pus_tc.unwrap();
|
||||
let mut write_and_send = |tm: &PusTmCreator| {
|
||||
let written_size = tm.write_to_bytes(cx.local.verif_buf).unwrap();
|
||||
cx.shared.tx_prod.lock(|prod| {
|
||||
cx.shared.tm_prod.lock(|prod| {
|
||||
prod.sizes_prod.try_push(tm.len_written()).unwrap();
|
||||
prod.buf_prod
|
||||
.push_slice(&cx.local.verif_buf[0..written_size]);
|
||||
@ -421,6 +388,12 @@ mod app {
|
||||
}
|
||||
if pus_tc.service() == PusServiceId::Test as u8 && pus_tc.subservice() == 1 {
|
||||
log::info!(target: "TC Handler", "received ping TC");
|
||||
let tm = cx
|
||||
.local
|
||||
.verif_reporter
|
||||
.completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
|
||||
.expect("completion success failed");
|
||||
write_and_send(&tm);
|
||||
} else if pus_tc.service() == PusServiceId::MemoryManagement as u8 {
|
||||
let tm = cx
|
||||
.local
|
||||
@ -484,12 +457,6 @@ mod app {
|
||||
}
|
||||
}
|
||||
}
|
||||
Err(e) => {
|
||||
log::warn!("PUS TC error: {}", e);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[task(
|
||||
priority = 1,
|
||||
@ -497,16 +464,16 @@ mod app {
|
||||
read_buf: [u8;MAX_TM_SIZE] = [0; MAX_TM_SIZE],
|
||||
encoded_buf: [u8;MAX_TM_FRAME_SIZE] = [0; MAX_TM_FRAME_SIZE],
|
||||
uart_tx,
|
||||
tx_cons,
|
||||
tm_cons
|
||||
],
|
||||
shared=[]
|
||||
)]
|
||||
async fn pus_tm_tx_handler(cx: pus_tm_tx_handler::Context) {
|
||||
loop {
|
||||
while cx.local.tx_cons.sizes_cons.occupied_len() > 0 {
|
||||
let next_size = cx.local.tx_cons.sizes_cons.try_pop().unwrap();
|
||||
while cx.local.tm_cons.sizes_cons.occupied_len() > 0 {
|
||||
let next_size = cx.local.tm_cons.sizes_cons.try_pop().unwrap();
|
||||
cx.local
|
||||
.tx_cons
|
||||
.tm_cons
|
||||
.buf_cons
|
||||
.pop_slice(&mut cx.local.read_buf[0..next_size]);
|
||||
cx.local.encoded_buf[0] = 0;
|
||||
|
||||
@ -17,12 +17,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
||||
|
||||
- Added `va41620`, `va41630`, `va41628` and `va41629` device features. A device now has to be
|
||||
selected for HAL compilation to work properly
|
||||
- Adaptions for the UART IRQ feature which are now only implemented for the RX part of the UART.
|
||||
|
||||
## Fixed
|
||||
|
||||
- Small fixes and improvements for ADC drivers
|
||||
- Fixes for the SPI implementation where the clock divider values were not calculated
|
||||
correctly
|
||||
- Fixes for UART IRQ handler implementation
|
||||
|
||||
## Added
|
||||
|
||||
|
||||
@ -20,7 +20,7 @@ embedded-io = "0.6"
|
||||
num_enum = { version = "0.7", default-features = false }
|
||||
typenum = "1"
|
||||
bitflags = "2"
|
||||
bitfield = "0.15"
|
||||
bitfield = "0.17"
|
||||
defmt = { version = "0.3", optional = true }
|
||||
fugit = "0.3"
|
||||
delegate = "0.12"
|
||||
|
||||
@ -197,66 +197,36 @@ impl From<Hertz> for Config {
|
||||
// IRQ Definitions
|
||||
//==================================================================================================
|
||||
|
||||
struct IrqInfo {
|
||||
#[derive(Debug)]
|
||||
pub struct IrqInfo {
|
||||
rx_len: usize,
|
||||
rx_idx: usize,
|
||||
mode: IrqReceptionMode,
|
||||
}
|
||||
|
||||
pub enum IrqResultMask {
|
||||
Complete = 0,
|
||||
Overflow = 1,
|
||||
FramingError = 2,
|
||||
ParityError = 3,
|
||||
Break = 4,
|
||||
Timeout = 5,
|
||||
Addr9 = 6,
|
||||
/// Should not happen
|
||||
Unknown = 7,
|
||||
}
|
||||
|
||||
/// This struct is used to return the default IRQ handler result to the user
|
||||
#[derive(Debug, Default)]
|
||||
pub struct IrqResult {
|
||||
raw_res: u32,
|
||||
complete: bool,
|
||||
timeout: bool,
|
||||
pub errors: IrqUartError,
|
||||
pub bytes_read: usize,
|
||||
}
|
||||
|
||||
impl IrqResult {
|
||||
pub const fn new() -> Self {
|
||||
pub fn new() -> Self {
|
||||
IrqResult {
|
||||
raw_res: 0,
|
||||
complete: false,
|
||||
timeout: false,
|
||||
errors: IrqUartError::default(),
|
||||
bytes_read: 0,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl IrqResult {
|
||||
#[inline]
|
||||
pub fn raw_result(&self) -> u32 {
|
||||
self.raw_res
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub(crate) fn clear_result(&mut self) {
|
||||
self.raw_res = 0;
|
||||
}
|
||||
#[inline]
|
||||
pub(crate) fn set_result(&mut self, flag: IrqResultMask) {
|
||||
self.raw_res |= 1 << flag as u32;
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn complete(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::Complete as u32) & 0x01) == 0x01 {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn error(&self) -> bool {
|
||||
if self.overflow_error() || self.framing_error() || self.parity_error() {
|
||||
if self.errors.overflow || self.errors.parity || self.errors.framing {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
@ -264,34 +234,27 @@ impl IrqResult {
|
||||
|
||||
#[inline]
|
||||
pub fn overflow_error(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::Overflow as u32) & 0x01) == 0x01 {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
self.errors.overflow
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn framing_error(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::FramingError as u32) & 0x01) == 0x01 {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
self.errors.framing
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn parity_error(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::ParityError as u32) & 0x01) == 0x01 {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
self.errors.parity
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn timeout(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::Timeout as u32) & 0x01) == 0x01 {
|
||||
return true;
|
||||
self.timeout
|
||||
}
|
||||
false
|
||||
|
||||
#[inline]
|
||||
pub fn complete(&self) -> bool {
|
||||
self.complete
|
||||
}
|
||||
}
|
||||
|
||||
@ -317,41 +280,27 @@ pub struct Uart<UartInstance, Pins> {
|
||||
pins: Pins,
|
||||
}
|
||||
|
||||
/// UART using the IRQ capabilities of the peripheral. Can be created with the
|
||||
/// [`Uart::into_uart_with_irq`] function. Currently, only the RX side for IRQ based reception
|
||||
/// is implemented.
|
||||
pub struct UartWithIrq<Uart, Pins> {
|
||||
base: UartWithIrqBase<Uart>,
|
||||
pins: Pins,
|
||||
}
|
||||
/// Serial receiver
|
||||
pub struct Rx<Uart>(Uart);
|
||||
|
||||
/// Type-erased UART using the IRQ capabilities of the peripheral. Can be created with the
|
||||
/// [`UartWithIrq::downgrade`] function. Currently, only the RX side for IRQ based reception
|
||||
/// is implemented.
|
||||
pub struct UartWithIrqBase<UART> {
|
||||
pub inner: UartBase<UART>,
|
||||
// Serial receiver, using interrupts to offload reading to the hardware.
|
||||
pub struct RxWithIrq<Uart> {
|
||||
inner: Rx<Uart>,
|
||||
irq_info: IrqInfo,
|
||||
}
|
||||
|
||||
/// Serial receiver
|
||||
pub struct Rx<Uart> {
|
||||
uart: Uart,
|
||||
}
|
||||
|
||||
/// Serial transmitter
|
||||
pub struct Tx<Uart> {
|
||||
uart: Uart,
|
||||
}
|
||||
pub struct Tx<Uart>(Uart);
|
||||
|
||||
impl<Uart: Instance> Rx<Uart> {
|
||||
fn new(uart: Uart) -> Self {
|
||||
Self { uart }
|
||||
Self(uart)
|
||||
}
|
||||
}
|
||||
|
||||
impl<Uart> Tx<Uart> {
|
||||
fn new(uart: Uart) -> Self {
|
||||
Self { uart }
|
||||
Self(uart)
|
||||
}
|
||||
}
|
||||
|
||||
@ -602,20 +551,30 @@ impl<TxPinInst: TxPin<UartInstance>, RxPinInst: RxPin<UartInstance>, UartInstanc
|
||||
}
|
||||
|
||||
/// If the IRQ capabilities of the peripheral are used, the UART needs to be converted
|
||||
/// with this function
|
||||
pub fn into_uart_with_irq(self) -> UartWithIrq<UartInstance, (TxPinInst, RxPinInst)> {
|
||||
/// with this function. Currently, IRQ abstractions are only implemented for the RX part
|
||||
/// of the UART, so this function will release a TX and RX handle as well as the pin
|
||||
/// instances.
|
||||
pub fn split_with_irq(
|
||||
self,
|
||||
) -> (
|
||||
Tx<UartInstance>,
|
||||
RxWithIrq<UartInstance>,
|
||||
(TxPinInst, RxPinInst),
|
||||
) {
|
||||
let (inner, pins) = self.downgrade_internal();
|
||||
UartWithIrq {
|
||||
pins,
|
||||
base: UartWithIrqBase {
|
||||
inner,
|
||||
let (tx, rx) = inner.split();
|
||||
(
|
||||
tx,
|
||||
RxWithIrq {
|
||||
inner: rx,
|
||||
irq_info: IrqInfo {
|
||||
rx_len: 0,
|
||||
rx_idx: 0,
|
||||
mode: IrqReceptionMode::Idle,
|
||||
},
|
||||
},
|
||||
}
|
||||
pins,
|
||||
)
|
||||
}
|
||||
|
||||
delegate::delegate! {
|
||||
@ -673,11 +632,26 @@ impl<Uart: Instance> Rx<Uart> {
|
||||
///
|
||||
/// You must ensure that only registers related to the operation of the RX side are used.
|
||||
pub unsafe fn uart(&self) -> &Uart {
|
||||
&self.uart
|
||||
&self.0
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_fifo(&self) {
|
||||
self.uart.fifo_clr().write(|w| w.rxfifo().set_bit());
|
||||
self.0.fifo_clr().write(|w| w.rxfifo().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn enable(&mut self) {
|
||||
self.0.enable().modify(|_, w| w.rxenable().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn disable(&mut self) {
|
||||
self.0.enable().modify(|_, w| w.rxenable().clear_bit());
|
||||
}
|
||||
|
||||
pub fn release(self) -> Uart {
|
||||
self.0
|
||||
}
|
||||
}
|
||||
|
||||
@ -688,11 +662,22 @@ impl<Uart: Instance> Tx<Uart> {
|
||||
///
|
||||
/// You must ensure that only registers related to the operation of the TX side are used.
|
||||
pub unsafe fn uart(&self) -> &Uart {
|
||||
&self.uart
|
||||
&self.0
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_fifo(&self) {
|
||||
self.uart.fifo_clr().write(|w| w.txfifo().set_bit());
|
||||
self.0.fifo_clr().write(|w| w.txfifo().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn enable(&mut self) {
|
||||
self.0.enable().modify(|_, w| w.txenable().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn disable(&mut self) {
|
||||
self.0.enable().modify(|_, w| w.txenable().clear_bit());
|
||||
}
|
||||
}
|
||||
|
||||
@ -701,6 +686,7 @@ pub struct IrqUartError {
|
||||
overflow: bool,
|
||||
framing: bool,
|
||||
parity: bool,
|
||||
other: bool,
|
||||
}
|
||||
|
||||
impl IrqUartError {
|
||||
@ -715,7 +701,7 @@ pub enum IrqError {
|
||||
Uart(IrqUartError),
|
||||
}
|
||||
|
||||
impl<Uart: Instance> UartWithIrqBase<Uart> {
|
||||
impl<Uart: Instance> RxWithIrq<Uart> {
|
||||
/// This initializes a non-blocking read transfer using the IRQ capabilities of the UART
|
||||
/// peripheral.
|
||||
///
|
||||
@ -735,8 +721,7 @@ impl<Uart: Instance> UartWithIrqBase<Uart> {
|
||||
self.irq_info.mode = IrqReceptionMode::Pending;
|
||||
self.irq_info.rx_idx = 0;
|
||||
self.irq_info.rx_len = max_len;
|
||||
self.inner.enable_rx();
|
||||
self.inner.enable_tx();
|
||||
self.inner.enable();
|
||||
self.enable_rx_irq_sources(enb_timeout_irq);
|
||||
unsafe { enable_interrupt(Uart::IRQ_RX) };
|
||||
Ok(())
|
||||
@ -744,7 +729,7 @@ impl<Uart: Instance> UartWithIrqBase<Uart> {
|
||||
|
||||
#[inline]
|
||||
fn enable_rx_irq_sources(&mut self, timeout: bool) {
|
||||
self.inner.uart.irq_enb().modify(|_, w| {
|
||||
self.inner.0.irq_enb().modify(|_, w| {
|
||||
if timeout {
|
||||
w.irq_rx_to().set_bit();
|
||||
}
|
||||
@ -755,30 +740,24 @@ impl<Uart: Instance> UartWithIrqBase<Uart> {
|
||||
|
||||
#[inline]
|
||||
fn disable_rx_irq_sources(&mut self) {
|
||||
self.inner.uart.irq_enb().modify(|_, w| {
|
||||
self.inner.0.irq_enb().modify(|_, w| {
|
||||
w.irq_rx_to().clear_bit();
|
||||
w.irq_rx_status().clear_bit();
|
||||
w.irq_rx().clear_bit()
|
||||
});
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn enable_tx(&mut self) {
|
||||
self.inner.enable_tx()
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn disable_tx(&mut self) {
|
||||
self.inner.disable_tx()
|
||||
}
|
||||
|
||||
pub fn cancel_transfer(&mut self) {
|
||||
self.disable_rx_irq_sources();
|
||||
self.inner.clear_tx_fifo();
|
||||
self.inner.clear_fifo();
|
||||
self.irq_info.rx_idx = 0;
|
||||
self.irq_info.rx_len = 0;
|
||||
}
|
||||
|
||||
pub fn uart(&self) -> &Uart {
|
||||
&self.inner.0
|
||||
}
|
||||
|
||||
/// Default IRQ handler which can be used to read the packets arriving on the UART peripheral.
|
||||
///
|
||||
/// If passed buffer is equal to or larger than the specified maximum length, an
|
||||
@ -791,18 +770,38 @@ impl<Uart: Instance> UartWithIrqBase<Uart> {
|
||||
});
|
||||
}
|
||||
let mut res = IrqResult::default();
|
||||
let mut possible_error = IrqUartError::default();
|
||||
|
||||
let rx_status = self.inner.uart.rxstatus().read();
|
||||
res.raw_res = rx_status.bits();
|
||||
let irq_end = self.inner.uart.irq_end().read();
|
||||
let enb_status = self.inner.uart.enable().read();
|
||||
let irq_end = self.inner.0.irq_end().read();
|
||||
let enb_status = self.inner.0.enable().read();
|
||||
let rx_enabled = enb_status.rxenable().bit_is_set();
|
||||
let _tx_enabled = enb_status.txenable().bit_is_set();
|
||||
let read_handler = |res: &mut IrqResult,
|
||||
possible_error: &mut IrqUartError,
|
||||
read_res: nb::Result<u8, Error>|
|
||||
-> Option<u8> {
|
||||
|
||||
// Half-Full interrupt. We have a guaranteed amount of data we can read.
|
||||
if irq_end.irq_rx().bit_is_set() {
|
||||
// Determine the number of bytes to read, ensuring we leave 1 byte in the FIFO.
|
||||
// We use this trick/hack because the timeout feature of the peripheral relies on data
|
||||
// being in the RX FIFO. If data continues arriving, another half-full IRQ will fire.
|
||||
// If not, the last byte(s) is/are emptied by the timeout interrupt.
|
||||
let available_bytes = self.inner.0.rxfifoirqtrg().read().bits() as usize;
|
||||
|
||||
let bytes_to_read = core::cmp::min(
|
||||
available_bytes.saturating_sub(1),
|
||||
self.irq_info.rx_len - self.irq_info.rx_idx,
|
||||
);
|
||||
|
||||
// If this interrupt bit is set, the trigger level is available at the very least.
|
||||
// Read everything as fast as possible
|
||||
for _ in 0..bytes_to_read {
|
||||
buf[self.irq_info.rx_idx] = (self.inner.0.data().read().bits() & 0xff) as u8;
|
||||
self.irq_info.rx_idx += 1;
|
||||
}
|
||||
|
||||
// On high-baudrates, data might be available immediately, and we possible have to
|
||||
// read continuosly? Then again, the CPU should always be faster than that. I'd rather
|
||||
// rely on the hardware firing another IRQ. I have not tried baudrates higher than
|
||||
// 115200 so far.
|
||||
}
|
||||
let read_handler =
|
||||
|possible_error: &mut IrqUartError, read_res: nb::Result<u8, Error>| -> Option<u8> {
|
||||
match read_res {
|
||||
Ok(byte) => Some(byte),
|
||||
Err(nb::Error::WouldBlock) => None,
|
||||
@ -818,77 +817,55 @@ impl<Uart: Instance> UartWithIrqBase<Uart> {
|
||||
possible_error.parity = true;
|
||||
}
|
||||
_ => {
|
||||
res.set_result(IrqResultMask::Unknown);
|
||||
possible_error.other = true;
|
||||
}
|
||||
}
|
||||
None
|
||||
}
|
||||
}
|
||||
};
|
||||
if irq_end.irq_rx().bit_is_set() {
|
||||
// If this interrupt bit is set, the trigger level is available at the very least.
|
||||
// Read everything as fast as possible
|
||||
for _ in 0..core::cmp::min(
|
||||
self.inner.uart.rxfifoirqtrg().read().bits() as usize,
|
||||
self.irq_info.rx_len,
|
||||
) {
|
||||
buf[self.irq_info.rx_idx] = (self.inner.uart.data().read().bits() & 0xff) as u8;
|
||||
self.irq_info.rx_idx += 1;
|
||||
}
|
||||
|
||||
// Timeout, empty the FIFO completely.
|
||||
if irq_end.irq_rx_to().bit_is_set() {
|
||||
// While there is data in the FIFO, write it into the reception buffer
|
||||
loop {
|
||||
if self.irq_info.rx_idx == self.irq_info.rx_len {
|
||||
self.irq_completion_handler(&mut res);
|
||||
return Ok(res);
|
||||
break;
|
||||
}
|
||||
if let Some(byte) = read_handler(&mut res, &mut possible_error, self.inner.read()) {
|
||||
if let Some(byte) = read_handler(&mut res.errors, self.inner.read()) {
|
||||
buf[self.irq_info.rx_idx] = byte;
|
||||
self.irq_info.rx_idx += 1;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
self.irq_completion_handler(&mut res);
|
||||
return Ok(res);
|
||||
}
|
||||
|
||||
// RX transfer not complete, check for RX errors
|
||||
if (self.irq_info.rx_idx < self.irq_info.rx_len) && rx_enabled {
|
||||
// Read status register again, might have changed since reading received data
|
||||
let rx_status = self.inner.uart.rxstatus().read();
|
||||
res.raw_res = rx_status.bits();
|
||||
let rx_status = self.inner.0.rxstatus().read();
|
||||
if rx_status.rxovr().bit_is_set() {
|
||||
possible_error.overflow = true;
|
||||
res.errors.overflow = true;
|
||||
}
|
||||
if rx_status.rxfrm().bit_is_set() {
|
||||
possible_error.framing = true;
|
||||
res.errors.framing = true;
|
||||
}
|
||||
if rx_status.rxpar().bit_is_set() {
|
||||
possible_error.parity = true;
|
||||
}
|
||||
if rx_status.rxto().bit_is_set() {
|
||||
// A timeout has occured but there might be some leftover data in the FIFO,
|
||||
// so read that data as well
|
||||
while let Some(byte) =
|
||||
read_handler(&mut res, &mut possible_error, self.inner.read())
|
||||
{
|
||||
buf[self.irq_info.rx_idx] = byte;
|
||||
self.irq_info.rx_idx += 1;
|
||||
}
|
||||
self.irq_completion_handler(&mut res);
|
||||
res.set_result(IrqResultMask::Timeout);
|
||||
return Ok(res);
|
||||
res.errors.parity = true;
|
||||
}
|
||||
|
||||
// If it is not a timeout, it's an error
|
||||
if possible_error.error() {
|
||||
if res.error() {
|
||||
self.disable_rx_irq_sources();
|
||||
return Err(IrqError::Uart(possible_error));
|
||||
return Err(IrqError::Uart(res.errors));
|
||||
}
|
||||
}
|
||||
|
||||
// Clear the interrupt status bits
|
||||
self.inner
|
||||
.uart
|
||||
.0
|
||||
.irq_clr()
|
||||
.write(|w| unsafe { w.bits(irq_end.bits()) });
|
||||
Ok(res)
|
||||
@ -896,48 +873,23 @@ impl<Uart: Instance> UartWithIrqBase<Uart> {
|
||||
|
||||
fn irq_completion_handler(&mut self, res: &mut IrqResult) {
|
||||
self.disable_rx_irq_sources();
|
||||
self.inner.disable_rx();
|
||||
self.inner.disable();
|
||||
res.bytes_read = self.irq_info.rx_idx;
|
||||
res.clear_result();
|
||||
res.set_result(IrqResultMask::Complete);
|
||||
res.complete = true;
|
||||
self.irq_info.mode = IrqReceptionMode::Idle;
|
||||
self.irq_info.rx_idx = 0;
|
||||
self.irq_info.rx_len = 0;
|
||||
}
|
||||
|
||||
pub fn irq_info(&self) -> &IrqInfo {
|
||||
&self.irq_info
|
||||
}
|
||||
|
||||
pub fn release(self) -> Uart {
|
||||
self.inner.release()
|
||||
}
|
||||
}
|
||||
|
||||
impl<Uart: Instance, Pins> UartWithIrq<Uart, Pins> {
|
||||
/// See [`UartWithIrqBase::read_fixed_len_using_irq`] doc
|
||||
pub fn read_fixed_len_using_irq(
|
||||
&mut self,
|
||||
max_len: usize,
|
||||
enb_timeout_irq: bool,
|
||||
) -> Result<(), Error> {
|
||||
self.base.read_fixed_len_using_irq(max_len, enb_timeout_irq)
|
||||
}
|
||||
|
||||
pub fn cancel_transfer(&mut self) {
|
||||
self.base.cancel_transfer()
|
||||
}
|
||||
|
||||
/// See [`UartWithIrqBase::irq_handler`] doc
|
||||
pub fn irq_handler(&mut self, buf: &mut [u8]) -> Result<IrqResult, IrqError> {
|
||||
self.base.irq_handler(buf)
|
||||
}
|
||||
|
||||
pub fn release(self) -> (Uart, Pins) {
|
||||
(self.base.release(), self.pins)
|
||||
}
|
||||
|
||||
pub fn downgrade(self) -> (UartWithIrqBase<Uart>, Pins) {
|
||||
(self.base, self.pins)
|
||||
}
|
||||
}
|
||||
|
||||
impl embedded_io::Error for Error {
|
||||
fn kind(&self) -> embedded_io::ErrorKind {
|
||||
embedded_io::ErrorKind::Other
|
||||
|
||||
Loading…
Reference in New Issue
Block a user