SPI peripheral implementation #4
@ -14,7 +14,7 @@ fn main() -> ! {
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rprintln!("VA416xx HAL blinky example");
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let mut dp = pac::Peripherals::take().unwrap();
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let portg = PinsG::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.portg);
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let portg = PinsG::new(&mut dp.sysconfig, dp.portg);
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let mut led = portg.pg5.into_readable_push_pull_output();
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//let mut delay = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM0);
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loop {
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96
examples/simple/examples/spi.rs
Normal file
96
examples/simple/examples/spi.rs
Normal file
@ -0,0 +1,96 @@
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//! SPI example application.
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//!
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//! If you do not use the loopback mode, MOSI and MISO need to be tied together on the board.
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#![no_main]
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#![no_std]
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use cortex_m_rt::entry;
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use embedded_hal::spi::{Mode, SpiBus, MODE_0};
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use simple_examples::peb1;
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use va416xx_hal::spi::{Spi, TransferConfig};
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use va416xx_hal::{
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gpio::{PinsB, PinsC},
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pac,
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prelude::*,
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spi::SpiConfig,
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};
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#[derive(PartialEq, Debug)]
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pub enum ExampleSelect {
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// Enter loopback mode. It is not necessary to tie MOSI/MISO together for this
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Loopback,
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// Send a test buffer and print everything received. You need to tie together MOSI/MISO in this
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// mode.
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TestBuffer,
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}
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const EXAMPLE_SEL: ExampleSelect = ExampleSelect::Loopback;
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const SPI_SPEED_KHZ: u32 = 1000;
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const SPI_MODE: Mode = MODE_0;
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const BLOCKMODE: bool = true;
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const FILL_WORD: u8 = 0x0f;
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#[entry]
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fn main() -> ! {
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rtt_init_print!();
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rprintln!("-- VA108xx SPI example application--");
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let cp = cortex_m::Peripherals::take().unwrap();
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let mut dp = pac::Peripherals::take().unwrap();
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// Use the external clock connected to XTAL_N.
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let clocks = dp
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.clkgen
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.constrain()
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.xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ)
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.freeze(&mut dp.sysconfig)
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.unwrap();
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let mut delay_sysclk = cortex_m::delay::Delay::new(cp.SYST, clocks.apb0().raw());
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let pins_b = PinsB::new(&mut dp.sysconfig, dp.portb);
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let pins_c = PinsC::new(&mut dp.sysconfig, dp.portc);
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// Configure SPI1 pins.
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let (sck, miso, mosi) = (
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pins_b.pb15.into_funsel_1(),
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pins_c.pc0.into_funsel_1(),
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pins_c.pc1.into_funsel_1(),
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);
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let mut spi_cfg = SpiConfig::default();
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if EXAMPLE_SEL == ExampleSelect::Loopback {
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spi_cfg = spi_cfg.loopback(true)
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}
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let transfer_cfg =
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TransferConfig::new_no_hw_cs(SPI_SPEED_KHZ.kHz(), SPI_MODE, BLOCKMODE, false);
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// Create SPI peripheral.
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let mut spi0 = Spi::spi0(
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dp.spi0,
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(sck, miso, mosi),
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&clocks,
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spi_cfg,
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&mut dp.sysconfig,
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Some(&transfer_cfg.downgrade()),
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);
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spi0.set_fill_word(FILL_WORD);
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loop {
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let mut tx_buf: [u8; 3] = [1, 2, 3];
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let mut rx_buf: [u8; 3] = [0; 3];
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// Can't really verify correct reply here.
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spi0.write(&[0x42]).expect("write failed");
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// Need small delay.. otherwise we will read back the sent byte (which we don't want here).
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// The write function will return as soon as all bytes were shifted out, ignoring the
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// reply bytes.
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delay_sysclk.delay_us(50);
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// Because of the loopback mode, we should get back the fill word here.
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spi0.read(&mut rx_buf[0..1]).unwrap();
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assert_eq!(rx_buf[0], FILL_WORD);
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spi0.transfer_in_place(&mut tx_buf)
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.expect("SPI transfer_in_place failed");
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assert_eq!([1, 2, 3], tx_buf);
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spi0.transfer(&mut rx_buf, &tx_buf)
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.expect("SPI transfer failed");
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assert_eq!(rx_buf, tx_buf);
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delay_sysclk.delay_ms(500);
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}
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}
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@ -28,7 +28,7 @@ fn main() -> ! {
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.freeze(&mut dp.sysconfig)
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.unwrap();
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let gpiob = PinsG::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.portg);
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let gpiob = PinsG::new(&mut dp.sysconfig, dp.portg);
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let tx = gpiob.pg0.into_funsel_1();
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let rx = gpiob.pg1.into_funsel_1();
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@ -1,7 +1,7 @@
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use core::{convert::Infallible, marker::PhantomData, mem::transmute};
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pub use crate::clock::FilterClkSel;
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use crate::Sealed;
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use crate::typelevel::Sealed;
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use embedded_hal::digital::{ErrorType, InputPin, OutputPin, StatefulOutputPin};
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use va416xx::{Porta, Portb, Portc, Portd, Porte, Portf, Portg};
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@ -622,7 +622,6 @@ macro_rules! pins {
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paste::paste!(
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/// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB)
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pub struct $PinsName {
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iocfg: Option<va416xx::Ioconfig>,
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port: $Port,
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$(
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#[doc = "Pin " $Id]
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@ -637,7 +636,6 @@ macro_rules! pins {
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#[inline]
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pub fn new(
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syscfg: &mut va416xx::Sysconfig,
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iocfg: Option<va416xx::Ioconfig>,
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port: $Port
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) -> $PinsName {
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syscfg.peripheral_clk_enable().modify(|_, w| {
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@ -645,7 +643,6 @@ macro_rules! pins {
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w.ioconfig().set_bit()
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});
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$PinsName {
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iocfg,
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port,
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// Safe because we only create one `Pin` per `PinId`
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$(
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@ -662,8 +659,8 @@ macro_rules! pins {
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}
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/// Consumes the Pins struct and returns the port definitions
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pub fn release(self) -> (Option<va416xx::Ioconfig>, $Port) {
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(self.iocfg, self.port)
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pub fn release(self) -> $Port {
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self.port
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}
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}
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);
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@ -9,6 +9,7 @@ pub mod prelude;
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pub mod clock;
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pub mod gpio;
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pub mod spi;
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pub mod time;
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pub mod typelevel;
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pub mod uart;
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@ -41,11 +42,3 @@ impl IrqCfg {
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IrqCfg { irq, route, enable }
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}
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}
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mod private {
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/// Super trait used to mark traits with an exhaustive set of
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/// implementations
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pub trait Sealed {}
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}
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pub(crate) use private::Sealed;
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885
va416xx-hal/src/spi.rs
Normal file
885
va416xx-hal/src/spi.rs
Normal file
@ -0,0 +1,885 @@
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use core::{convert::Infallible, marker::PhantomData, ops::Deref};
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use embedded_hal::spi::Mode;
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use crate::{
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clock::PeripheralSelect,
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gpio::{
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AltFunc1, AltFunc2, AltFunc3, Pin, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PB0,
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PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PC0, PC1,
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PC10, PC11, PC7, PC8, PC9, PE10, PE11, PE12, PE13, PE14, PE15, PE5, PE6, PE7, PE8, PE9,
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PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PG2, PG3, PG4,
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},
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pac,
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time::Hertz,
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typelevel::{NoneT, Sealed},
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};
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//==================================================================================================
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// Defintions
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//==================================================================================================
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// FIFO has a depth of 16.
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const FILL_DEPTH: usize = 12;
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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pub enum HwChipSelectId {
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Id0 = 0,
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Id1 = 1,
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Id2 = 2,
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Id3 = 3,
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Id4 = 4,
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Id5 = 5,
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Id6 = 6,
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Id7 = 7,
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Invalid = 0xff,
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}
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#[derive(Debug)]
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pub enum SpiId {
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Spi0,
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Spi1,
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Spi2,
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Spi3,
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Invalid,
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}
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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pub enum WordSize {
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OneBit = 0x00,
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FourBits = 0x03,
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EightBits = 0x07,
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SixteenBits = 0x0f,
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}
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//==================================================================================================
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// Pin type definitions
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//==================================================================================================
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pub trait PinSck<SPI>: Sealed {}
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pub trait PinMosi<SPI>: Sealed {}
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pub trait PinMiso<SPI>: Sealed {}
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pub trait HwCsProvider: Sealed {
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const CS_ID: HwChipSelectId;
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const SPI_ID: SpiId;
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}
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pub trait OptionalHwCs<Spi>: HwCsProvider + Sealed {}
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macro_rules! hw_cs_pins {
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($SPIx:path, $portId: path:
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$(
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($PXx:ident, $AFx:ident, $HwCsIdent:path, $typedef:ident),
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)+
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) => {
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$(
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impl HwCsProvider for Pin<$PXx, $AFx> {
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const CS_ID: HwChipSelectId = $HwCsIdent;
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const SPI_ID: SpiId = $portId;
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}
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impl OptionalHwCs<$SPIx> for Pin<$PXx, $AFx> {}
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pub type $typedef = Pin<$PXx, $AFx>;
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)+
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};
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}
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impl HwCsProvider for NoneT {
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const CS_ID: HwChipSelectId = HwChipSelectId::Invalid;
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const SPI_ID: SpiId = SpiId::Invalid;
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}
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impl OptionalHwCs<pac::Spi0> for NoneT {}
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impl OptionalHwCs<pac::Spi1> for NoneT {}
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impl OptionalHwCs<pac::Spi2> for NoneT {}
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impl OptionalHwCs<pac::Spi3> for NoneT {}
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// SPI 0
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impl PinSck<pac::Spi0> for Pin<PB15, AltFunc1> {}
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impl PinMosi<pac::Spi0> for Pin<PC1, AltFunc1> {}
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impl PinMiso<pac::Spi0> for Pin<PC0, AltFunc1> {}
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// SPI 1
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impl PinSck<pac::Spi1> for Pin<PB8, AltFunc3> {}
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impl PinMosi<pac::Spi1> for Pin<PB10, AltFunc3> {}
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impl PinMiso<pac::Spi1> for Pin<PB9, AltFunc3> {}
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impl PinSck<pac::Spi1> for Pin<PC9, AltFunc2> {}
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impl PinMosi<pac::Spi1> for Pin<PC11, AltFunc2> {}
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impl PinMiso<pac::Spi1> for Pin<PC10, AltFunc2> {}
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impl PinSck<pac::Spi1> for Pin<PG3, AltFunc2> {}
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impl PinMiso<pac::Spi1> for Pin<PG4, AltFunc2> {}
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impl PinSck<pac::Spi1> for Pin<PE13, AltFunc2> {}
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impl PinMosi<pac::Spi1> for Pin<PE15, AltFunc2> {}
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impl PinMiso<pac::Spi1> for Pin<PE14, AltFunc2> {}
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impl PinSck<pac::Spi1> for Pin<PF3, AltFunc1> {}
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impl PinMosi<pac::Spi1> for Pin<PF5, AltFunc1> {}
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impl PinMiso<pac::Spi1> for Pin<PF4, AltFunc1> {}
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// SPI 2
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impl PinSck<pac::Spi2> for Pin<PA5, AltFunc2> {}
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impl PinMosi<pac::Spi2> for Pin<PA7, AltFunc2> {}
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impl PinMiso<pac::Spi2> for Pin<PA6, AltFunc2> {}
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impl PinSck<pac::Spi2> for Pin<PF5, AltFunc2> {}
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impl PinMosi<pac::Spi2> for Pin<PF7, AltFunc2> {}
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impl PinMiso<pac::Spi2> for Pin<PF6, AltFunc2> {}
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// SPI3 is shared with the ROM SPI pins and has its own dedicated pins.
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// SPI 0 HW CS pins
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hw_cs_pins!(
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pac::Spi0, SpiId::Spi0:
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(PB14, AltFunc1, HwChipSelectId::Id0, HwCs0Spi0),
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(PB13, AltFunc1, HwChipSelectId::Id1, HwCs1Spi0),
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(PB12, AltFunc1, HwChipSelectId::Id2, HwCs2Spi0),
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(PB11, AltFunc1, HwChipSelectId::Id3, HwCs3Spi0),
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);
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hw_cs_pins!(
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pac::Spi1, SpiId::Spi1:
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(PB7, AltFunc3, HwChipSelectId::Id0, HwCs0Spi1Pb),
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(PB6, AltFunc3, HwChipSelectId::Id1, HwCs1Spi1Pb),
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(PB5, AltFunc3, HwChipSelectId::Id2, HwCs2Spi1Pb),
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(PB4, AltFunc3, HwChipSelectId::Id3, HwCs3Spi1Pb),
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(PB3, AltFunc3, HwChipSelectId::Id4, HwCs4Spi1Pb),
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(PB2, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pb),
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(PB1, AltFunc3, HwChipSelectId::Id6, HwCs6Spi1Pb),
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(PB0, AltFunc3, HwChipSelectId::Id7, HwCs7Spi1Pb),
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(PC8, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pc),
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(PC7, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pc),
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(PE12, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pe),
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(PE11, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pe),
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(PE10, AltFunc2, HwChipSelectId::Id2, HwCs2Spi1Pe),
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(PE9, AltFunc2, HwChipSelectId::Id3, HwCs3Spi1Pe),
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(PE8, AltFunc2, HwChipSelectId::Id4, HwCs4Spi1Pe),
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(PE7, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pe),
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(PE6, AltFunc3, HwChipSelectId::Id6, HwCs6Spi1Pe),
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(PE5, AltFunc3, HwChipSelectId::Id7, HwCs7Spi1Pe),
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(PF2, AltFunc1, HwChipSelectId::Id0, HwCs0Spi1Pf),
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(PG2, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pg),
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);
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hw_cs_pins!(
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pac::Spi2, SpiId::Spi2:
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(PA4, AltFunc2, HwChipSelectId::Id0, HwCs0Spi2Pa),
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||||
(PA3, AltFunc2, HwChipSelectId::Id1, HwCs1Spi2Pa),
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(PA2, AltFunc2, HwChipSelectId::Id2, HwCs2Spi2Pa),
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(PA1, AltFunc2, HwChipSelectId::Id3, HwCs3Spi2Pa),
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(PA0, AltFunc2, HwChipSelectId::Id4, HwCs4Spi2Pa),
|
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(PA8, AltFunc2, HwChipSelectId::Id6, HwCs6Spi2Pa),
|
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(PA9, AltFunc2, HwChipSelectId::Id5, HwCs5Spi2Pa),
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(PF0, AltFunc2, HwChipSelectId::Id4, HwCs4Spi2Pf),
|
||||
(PF1, AltFunc2, HwChipSelectId::Id3, HwCs3Spi2Pf),
|
||||
(PF2, AltFunc2, HwChipSelectId::Id2, HwCs2Spi2Pf),
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(PF3, AltFunc2, HwChipSelectId::Id1, HwCs1Spi2Pf),
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(PF4, AltFunc2, HwChipSelectId::Id0, HwCs0Spi2Pf),
|
||||
);
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|
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//==================================================================================================
|
||||
// Config
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||||
//==================================================================================================
|
||||
|
||||
pub trait TransferConfigProvider {
|
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fn sod(&mut self, sod: bool);
|
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fn blockmode(&mut self, blockmode: bool);
|
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fn mode(&mut self, mode: Mode);
|
||||
fn frequency(&mut self, spi_clk: Hertz);
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fn hw_cs_id(&self) -> u8;
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}
|
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|
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/// This struct contains all configuration parameter which are transfer specific
|
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/// and might change for transfers to different SPI slaves
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#[derive(Copy, Clone)]
|
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pub struct TransferConfig<HwCs> {
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pub spi_clk: Hertz,
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pub mode: Mode,
|
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/// This only works if the Slave Output Disable (SOD) bit of the [`SpiConfig`] is set to
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/// false
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pub hw_cs: Option<HwCs>,
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pub sod: bool,
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||||
/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
|
||||
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
|
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/// duration of multiple data words
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pub blockmode: bool,
|
||||
}
|
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|
||||
/// Type erased variant of the transfer configuration. This is required to avoid generics in
|
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/// the SPI constructor.
|
||||
pub struct ErasedTransferConfig {
|
||||
pub spi_clk: Hertz,
|
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pub mode: Mode,
|
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pub sod: bool,
|
||||
/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
|
||||
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
|
||||
/// duration of multiple data words
|
||||
pub blockmode: bool,
|
||||
pub hw_cs: HwChipSelectId,
|
||||
}
|
||||
|
||||
impl TransferConfig<NoneT> {
|
||||
pub fn new_no_hw_cs(spi_clk: impl Into<Hertz>, mode: Mode, blockmode: bool, sod: bool) -> Self {
|
||||
TransferConfig {
|
||||
spi_clk: spi_clk.into(),
|
||||
mode,
|
||||
hw_cs: None,
|
||||
sod,
|
||||
blockmode,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<HwCs: HwCsProvider> TransferConfig<HwCs> {
|
||||
pub fn new(
|
||||
spi_clk: impl Into<Hertz>,
|
||||
mode: Mode,
|
||||
hw_cs: Option<HwCs>,
|
||||
blockmode: bool,
|
||||
sod: bool,
|
||||
) -> Self {
|
||||
TransferConfig {
|
||||
spi_clk: spi_clk.into(),
|
||||
mode,
|
||||
hw_cs,
|
||||
sod,
|
||||
blockmode,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn downgrade(self) -> ErasedTransferConfig {
|
||||
ErasedTransferConfig {
|
||||
spi_clk: self.spi_clk,
|
||||
mode: self.mode,
|
||||
sod: self.sod,
|
||||
blockmode: self.blockmode,
|
||||
hw_cs: HwCs::CS_ID,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<HwCs: HwCsProvider> TransferConfigProvider for TransferConfig<HwCs> {
|
||||
/// Slave Output Disable
|
||||
fn sod(&mut self, sod: bool) {
|
||||
self.sod = sod;
|
||||
}
|
||||
|
||||
fn blockmode(&mut self, blockmode: bool) {
|
||||
self.blockmode = blockmode;
|
||||
}
|
||||
|
||||
fn mode(&mut self, mode: Mode) {
|
||||
self.mode = mode;
|
||||
}
|
||||
|
||||
fn frequency(&mut self, spi_clk: Hertz) {
|
||||
self.spi_clk = spi_clk;
|
||||
}
|
||||
|
||||
fn hw_cs_id(&self) -> u8 {
|
||||
HwCs::CS_ID as u8
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Default)]
|
||||
/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
|
||||
pub struct SpiConfig {
|
||||
/// Serial clock rate divider. Together with the CLKPRESCALE register, it determines
|
||||
/// the SPI clock rate in master mode. 0 by default. Specifying a higher value
|
||||
/// limits the maximum attainable SPI speed
|
||||
pub ser_clock_rate_div: u8,
|
||||
/// By default, configure SPI for master mode (ms == false)
|
||||
ms: bool,
|
||||
/// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control
|
||||
pub slave_output_disable: bool,
|
||||
/// Loopback mode. If you use this, don't connect MISO to MOSI, they will be tied internally
|
||||
pub loopback_mode: bool,
|
||||
/// Enable Master Delayer Capture Mode. See Programmers Guide p.92 for more details
|
||||
pub master_delayer_capture: bool,
|
||||
}
|
||||
|
||||
impl SpiConfig {
|
||||
pub fn loopback(mut self, enable: bool) -> Self {
|
||||
self.loopback_mode = enable;
|
||||
self
|
||||
}
|
||||
|
||||
pub fn master_mode(mut self, master: bool) -> Self {
|
||||
self.ms = !master;
|
||||
self
|
||||
}
|
||||
|
||||
pub fn slave_output_disable(mut self, sod: bool) -> Self {
|
||||
self.slave_output_disable = sod;
|
||||
self
|
||||
}
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// Word Size
|
||||
//==================================================================================================
|
||||
|
||||
/// Configuration trait for the Word Size used by the SPI peripheral
|
||||
pub trait WordProvider: Copy + Default + Into<u32> + TryFrom<u32> + 'static {
|
||||
const MASK: u32;
|
||||
fn word_reg() -> u8;
|
||||
}
|
||||
|
||||
impl WordProvider for u8 {
|
||||
const MASK: u32 = 0xff;
|
||||
fn word_reg() -> u8 {
|
||||
0x07
|
||||
}
|
||||
}
|
||||
|
||||
impl WordProvider for u16 {
|
||||
const MASK: u32 = 0xffff;
|
||||
fn word_reg() -> u8 {
|
||||
0x0f
|
||||
}
|
||||
}
|
||||
|
||||
pub type SpiRegBlock = pac::spi0::RegisterBlock;
|
||||
|
||||
/// Common trait implemented by all PAC peripheral access structures. The register block
|
||||
/// format is the same for all SPI blocks.
|
||||
pub trait Instance: Deref<Target = SpiRegBlock> {
|
||||
const IDX: u8;
|
||||
|
||||
fn ptr() -> *const SpiRegBlock;
|
||||
}
|
||||
|
||||
impl Instance for pac::Spi0 {
|
||||
const IDX: u8 = 0;
|
||||
|
||||
fn ptr() -> *const SpiRegBlock {
|
||||
Self::ptr()
|
||||
}
|
||||
}
|
||||
|
||||
impl Instance for pac::Spi1 {
|
||||
const IDX: u8 = 1;
|
||||
|
||||
fn ptr() -> *const SpiRegBlock {
|
||||
Self::ptr()
|
||||
}
|
||||
}
|
||||
|
||||
impl Instance for pac::Spi2 {
|
||||
const IDX: u8 = 2;
|
||||
|
||||
fn ptr() -> *const SpiRegBlock {
|
||||
Self::ptr()
|
||||
}
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// Spi
|
||||
//==================================================================================================
|
||||
|
||||
pub struct SpiBase<SpiInstance, Word = u8> {
|
||||
spi: SpiInstance,
|
||||
cfg: SpiConfig,
|
||||
apb1_clk: Hertz,
|
||||
/// Fill word for read-only SPI transactions.
|
||||
pub fill_word: Word,
|
||||
blockmode: bool,
|
||||
word: PhantomData<Word>,
|
||||
}
|
||||
|
||||
pub struct Spi<SpiInstance, Pins, Word = u8> {
|
||||
inner: SpiBase<SpiInstance, Word>,
|
||||
pins: Pins,
|
||||
}
|
||||
|
||||
fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) {
|
||||
match mode {
|
||||
embedded_hal::spi::MODE_0 => (false, false),
|
||||
embedded_hal::spi::MODE_1 => (false, true),
|
||||
embedded_hal::spi::MODE_2 => (true, false),
|
||||
embedded_hal::spi::MODE_3 => (true, true),
|
||||
}
|
||||
}
|
||||
|
||||
impl<SpiInstance: Instance, Word: WordProvider> SpiBase<SpiInstance, Word>
|
||||
where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
#[inline]
|
||||
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
|
||||
let clk_prescale =
|
||||
self.apb1_clk.raw() / (spi_clk.into().raw() * (self.cfg.ser_clock_rate_div as u32 + 1));
|
||||
self.spi
|
||||
.clkprescale()
|
||||
.write(|w| unsafe { w.bits(clk_prescale) });
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_mode(&mut self, mode: Mode) {
|
||||
let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(mode);
|
||||
self.spi.ctrl0().modify(|_, w| {
|
||||
w.spo().bit(cpo_bit);
|
||||
w.sph().bit(cph_bit)
|
||||
});
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_tx_fifo(&self) {
|
||||
self.spi.fifo_clr().write(|w| w.txfifo().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_rx_fifo(&self) {
|
||||
self.spi.fifo_clr().write(|w| w.rxfifo().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn perid(&self) -> u32 {
|
||||
self.spi.perid().read().bits()
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_hw_cs(&mut self, hw_cs: HwChipSelectId) {
|
||||
if hw_cs == HwChipSelectId::Invalid {
|
||||
return;
|
||||
}
|
||||
self.spi.ctrl1().modify(|_, w| {
|
||||
w.sod().clear_bit();
|
||||
unsafe {
|
||||
w.ss().bits(hw_cs as u8);
|
||||
}
|
||||
w
|
||||
});
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_hw_cs_with_pin<HwCs: OptionalHwCs<SpiInstance>>(&mut self, _: &HwCs) {
|
||||
self.cfg_hw_cs(HwCs::CS_ID);
|
||||
}
|
||||
|
||||
pub fn cfg_hw_cs_disable(&mut self) {
|
||||
self.spi.ctrl1().modify(|_, w| {
|
||||
w.sod().set_bit();
|
||||
w
|
||||
});
|
||||
}
|
||||
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiInstance>>(
|
||||
&mut self,
|
||||
transfer_cfg: &TransferConfig<HwCs>,
|
||||
) {
|
||||
self.cfg_clock(transfer_cfg.spi_clk);
|
||||
self.cfg_mode(transfer_cfg.mode);
|
||||
self.blockmode = transfer_cfg.blockmode;
|
||||
self.spi.ctrl1().modify(|_, w| {
|
||||
if transfer_cfg.sod {
|
||||
w.sod().set_bit();
|
||||
} else if transfer_cfg.hw_cs.is_some() {
|
||||
w.sod().clear_bit();
|
||||
unsafe {
|
||||
w.ss().bits(HwCs::CS_ID as u8);
|
||||
}
|
||||
} else {
|
||||
w.sod().clear_bit();
|
||||
}
|
||||
if transfer_cfg.blockmode {
|
||||
w.blockmode().set_bit();
|
||||
} else {
|
||||
w.blockmode().clear_bit();
|
||||
}
|
||||
w
|
||||
});
|
||||
}
|
||||
|
||||
/// Sends a word to the slave
|
||||
#[inline(always)]
|
||||
fn send_blocking(&self, word: Word) {
|
||||
// TODO: Upper limit for wait cycles to avoid complete hangups?
|
||||
while self.spi.status().read().tnf().bit_is_clear() {}
|
||||
self.send(word)
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn send(&self, word: Word) {
|
||||
self.spi.data().write(|w| unsafe { w.bits(word.into()) });
|
||||
}
|
||||
|
||||
/// Read a word from the slave. Must be preceeded by a [`send`](Self::send) call
|
||||
#[inline(always)]
|
||||
fn read_blocking(&self) -> Word {
|
||||
// TODO: Upper limit for wait cycles to avoid complete hangups?
|
||||
while self.spi.status().read().rne().bit_is_clear() {}
|
||||
self.read_single_word()
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn read_single_word(&self) -> Word {
|
||||
(self.spi.data().read().bits() & Word::MASK)
|
||||
.try_into()
|
||||
.unwrap()
|
||||
}
|
||||
|
||||
fn transfer_preparation(&self, words: &[Word]) -> Result<(), Infallible> {
|
||||
if words.is_empty() {
|
||||
return Ok(());
|
||||
}
|
||||
let mut status_reg = self.spi.status().read();
|
||||
// Wait until all bytes have been transferred.
|
||||
while status_reg.tfe().bit_is_clear() {
|
||||
// Ignore all received read words.
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.clear_rx_fifo();
|
||||
}
|
||||
status_reg = self.spi.status().read();
|
||||
}
|
||||
// Ignore all received read words.
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.clear_rx_fifo();
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn initial_send_fifo_pumping(&self, words: Option<&[Word]>) -> usize {
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
||||
}
|
||||
// Fill the first half of the write FIFO
|
||||
let mut current_write_idx = 0;
|
||||
for _ in 0..core::cmp::min(FILL_DEPTH, words.map_or(0, |words| words.len())) {
|
||||
self.send_blocking(words.map_or(self.fill_word, |words| words[current_write_idx]));
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().clear_bit())
|
||||
}
|
||||
current_write_idx
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! spi_ctor {
|
||||
($spiI:ident, $PeriphSel: path) => {
|
||||
/// Create a new SPI struct
|
||||
///
|
||||
/// You can delete the pin type information by calling the
|
||||
/// [`downgrade`](Self::downgrade) function
|
||||
///
|
||||
/// ## Arguments
|
||||
/// * `spi` - SPI bus to use
|
||||
/// * `pins` - Pins to be used for SPI transactions. These pins are consumed
|
||||
/// to ensure the pins can not be used for other purposes anymore
|
||||
/// * `spi_cfg` - Configuration specific to the SPI bus
|
||||
/// * `transfer_cfg` - Optional initial transfer configuration which includes
|
||||
/// configuration which can change across individual SPI transfers like SPI mode
|
||||
/// or SPI clock. If only one device is connected, this configuration only needs
|
||||
/// to be done once.
|
||||
/// * `syscfg` - Can be passed optionally to enable the peripheral clock
|
||||
pub fn $spiI(
|
||||
spi: SpiI,
|
||||
pins: (Sck, Miso, Mosi),
|
||||
clocks: &crate::clock::Clocks,
|
||||
spi_cfg: SpiConfig,
|
||||
syscfg: &mut pac::Sysconfig,
|
||||
transfer_cfg: Option<&ErasedTransferConfig>,
|
||||
) -> Self {
|
||||
crate::clock::enable_peripheral_clock(syscfg, $PeriphSel);
|
||||
let SpiConfig {
|
||||
ser_clock_rate_div,
|
||||
ms,
|
||||
slave_output_disable,
|
||||
loopback_mode,
|
||||
master_delayer_capture,
|
||||
} = spi_cfg;
|
||||
let mut mode = embedded_hal::spi::MODE_0;
|
||||
let mut clk_prescale = 0x02;
|
||||
let mut ss = 0;
|
||||
let mut init_blockmode = false;
|
||||
let apb1_clk = clocks.apb1();
|
||||
if let Some(transfer_cfg) = transfer_cfg {
|
||||
mode = transfer_cfg.mode;
|
||||
clk_prescale =
|
||||
apb1_clk.raw() / (transfer_cfg.spi_clk.raw() * (ser_clock_rate_div as u32 + 1));
|
||||
if transfer_cfg.hw_cs != HwChipSelectId::Invalid {
|
||||
ss = transfer_cfg.hw_cs as u8;
|
||||
}
|
||||
init_blockmode = transfer_cfg.blockmode;
|
||||
}
|
||||
|
||||
let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(mode);
|
||||
spi.ctrl0().write(|w| {
|
||||
unsafe {
|
||||
w.size().bits(Word::word_reg());
|
||||
w.scrdv().bits(ser_clock_rate_div);
|
||||
// Clear clock phase and polarity. Will be set to correct value for each
|
||||
// transfer
|
||||
w.spo().bit(cpo_bit);
|
||||
w.sph().bit(cph_bit)
|
||||
}
|
||||
});
|
||||
spi.ctrl1().write(|w| {
|
||||
w.lbm().bit(loopback_mode);
|
||||
w.sod().bit(slave_output_disable);
|
||||
w.ms().bit(ms);
|
||||
w.mdlycap().bit(master_delayer_capture);
|
||||
w.blockmode().bit(init_blockmode);
|
||||
unsafe { w.ss().bits(ss) }
|
||||
});
|
||||
|
||||
spi.fifo_clr().write(|w| {
|
||||
w.rxfifo().set_bit();
|
||||
w.txfifo().set_bit()
|
||||
});
|
||||
spi.clkprescale().write(|w| unsafe { w.bits(clk_prescale) });
|
||||
// Enable the peripheral as the last step as recommended in the
|
||||
// programmers guide
|
||||
spi.ctrl1().modify(|_, w| w.enable().set_bit());
|
||||
Spi {
|
||||
inner: SpiBase {
|
||||
spi,
|
||||
cfg: spi_cfg,
|
||||
apb1_clk,
|
||||
fill_word: Default::default(),
|
||||
blockmode: init_blockmode,
|
||||
word: PhantomData,
|
||||
},
|
||||
pins,
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
impl<
|
||||
SpiI: Instance,
|
||||
Sck: PinSck<SpiI>,
|
||||
Miso: PinMiso<SpiI>,
|
||||
Mosi: PinMosi<SpiI>,
|
||||
Word: WordProvider,
|
||||
> Spi<SpiI, (Sck, Miso, Mosi), Word>
|
||||
where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
spi_ctor!(spi0, PeripheralSelect::Spi0);
|
||||
spi_ctor!(spi1, PeripheralSelect::Spi1);
|
||||
spi_ctor!(spi2, PeripheralSelect::Spi2);
|
||||
spi_ctor!(spi3, PeripheralSelect::Spi3);
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
|
||||
self.inner.cfg_clock(spi_clk);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_mode(&mut self, mode: Mode) {
|
||||
self.inner.cfg_mode(mode);
|
||||
}
|
||||
|
||||
pub fn set_fill_word(&mut self, fill_word: Word) {
|
||||
self.inner.fill_word = fill_word;
|
||||
}
|
||||
|
||||
pub fn fill_word(&self) -> Word {
|
||||
self.inner.fill_word
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn perid(&self) -> u32 {
|
||||
self.inner.perid()
|
||||
}
|
||||
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiI>>(&mut self, transfer_cfg: &TransferConfig<HwCs>) {
|
||||
self.inner.cfg_transfer(transfer_cfg);
|
||||
}
|
||||
|
||||
/// Releases the SPI peripheral and associated pins
|
||||
pub fn release(self) -> (SpiI, (Sck, Miso, Mosi), SpiConfig) {
|
||||
(self.inner.spi, self.pins, self.inner.cfg)
|
||||
}
|
||||
|
||||
pub fn downgrade(self) -> SpiBase<SpiI, Word> {
|
||||
self.inner
|
||||
}
|
||||
}
|
||||
|
||||
/// Changing the word size also requires a type conversion
|
||||
impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>>
|
||||
From<Spi<SpiI, (Sck, Miso, Mosi), u8>> for Spi<SpiI, (Sck, Miso, Mosi), u16>
|
||||
{
|
||||
fn from(old_spi: Spi<SpiI, (Sck, Miso, Mosi), u8>) -> Self {
|
||||
old_spi
|
||||
.inner
|
||||
.spi
|
||||
.ctrl0()
|
||||
.modify(|_, w| unsafe { w.size().bits(WordSize::SixteenBits as u8) });
|
||||
Spi {
|
||||
inner: SpiBase {
|
||||
spi: old_spi.inner.spi,
|
||||
cfg: old_spi.inner.cfg,
|
||||
blockmode: old_spi.inner.blockmode,
|
||||
fill_word: Default::default(),
|
||||
apb1_clk: old_spi.inner.apb1_clk,
|
||||
word: PhantomData,
|
||||
},
|
||||
pins: old_spi.pins,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Changing the word size also requires a type conversion
|
||||
impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>>
|
||||
From<Spi<SpiI, (Sck, Miso, Mosi), u16>> for Spi<SpiI, (Sck, Miso, Mosi), u8>
|
||||
{
|
||||
fn from(old_spi: Spi<SpiI, (Sck, Miso, Mosi), u16>) -> Self {
|
||||
old_spi
|
||||
.inner
|
||||
.spi
|
||||
.ctrl0()
|
||||
.modify(|_, w| unsafe { w.size().bits(WordSize::EightBits as u8) });
|
||||
Spi {
|
||||
inner: SpiBase {
|
||||
spi: old_spi.inner.spi,
|
||||
cfg: old_spi.inner.cfg,
|
||||
blockmode: old_spi.inner.blockmode,
|
||||
apb1_clk: old_spi.inner.apb1_clk,
|
||||
fill_word: Default::default(),
|
||||
word: PhantomData,
|
||||
},
|
||||
pins: old_spi.pins,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<SpiI: Instance, Word: WordProvider> embedded_hal::spi::ErrorType for SpiBase<SpiI, Word> {
|
||||
type Error = Infallible;
|
||||
}
|
||||
|
||||
impl<SpiI: Instance, Word: WordProvider> embedded_hal::spi::SpiBus<Word> for SpiBase<SpiI, Word>
|
||||
where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(None);
|
||||
loop {
|
||||
if current_write_idx < words.len() {
|
||||
self.send_blocking(self.fill_word);
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if current_read_idx < words.len() {
|
||||
words[current_read_idx] = self.read_blocking();
|
||||
current_read_idx += 1;
|
||||
}
|
||||
if current_read_idx >= words.len() && current_write_idx >= words.len() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(Some(words));
|
||||
while current_write_idx < words.len() {
|
||||
self.send_blocking(words[current_write_idx]);
|
||||
current_write_idx += 1;
|
||||
// Ignore received words.
|
||||
if self.spi.status().read().rne().bit_is_set() {
|
||||
self.clear_rx_fifo();
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(write)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(Some(write));
|
||||
while current_read_idx < read.len() || current_write_idx < write.len() {
|
||||
if current_write_idx < write.len() {
|
||||
self.send_blocking(write[current_write_idx]);
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if current_read_idx < read.len() {
|
||||
read[current_read_idx] = self.read_blocking();
|
||||
current_read_idx += 1;
|
||||
}
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(Some(words));
|
||||
|
||||
while current_read_idx < words.len() || current_write_idx < words.len() {
|
||||
if current_write_idx < words.len() {
|
||||
self.send_blocking(words[current_write_idx]);
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if current_read_idx < words.len() && current_read_idx < current_write_idx {
|
||||
words[current_read_idx] = self.read_blocking();
|
||||
current_read_idx += 1;
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
let status_reg = self.spi.status().read();
|
||||
while status_reg.tfe().bit_is_clear() || status_reg.rne().bit_is_set() {
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.read_single_word();
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl<
|
||||
SpiI: Instance,
|
||||
Word: WordProvider,
|
||||
Sck: PinSck<SpiI>,
|
||||
Miso: PinMiso<SpiI>,
|
||||
Mosi: PinMosi<SpiI>,
|
||||
> embedded_hal::spi::ErrorType for Spi<SpiI, (Sck, Miso, Mosi), Word>
|
||||
{
|
||||
type Error = Infallible;
|
||||
}
|
||||
|
||||
impl<
|
||||
SpiI: Instance,
|
||||
Word: WordProvider,
|
||||
Sck: PinSck<SpiI>,
|
||||
Miso: PinMiso<SpiI>,
|
||||
Mosi: PinMosi<SpiI>,
|
||||
> embedded_hal::spi::SpiBus<Word> for Spi<SpiI, (Sck, Miso, Mosi), Word>
|
||||
where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.inner.read(words)
|
||||
}
|
||||
|
||||
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
|
||||
self.inner.write(words)
|
||||
}
|
||||
|
||||
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
|
||||
self.inner.transfer(read, write)
|
||||
}
|
||||
|
||||
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.inner.transfer_in_place(words)
|
||||
}
|
||||
|
||||
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
self.inner.flush()
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user