#[doc = "Register `IRQ_ENB` reader"]
pub type R = crate::R<IrqEnbSpec>;
#[doc = "Register `IRQ_ENB` writer"]
pub type W = crate::W<IrqEnbSpec>;
#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"]
pub type FifoEmptyR = crate::BitReader;
#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"]
pub type FifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"]
pub type FifoFullR = crate::BitReader;
#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"]
pub type FifoFullW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"]
pub type FifoOflowR = crate::BitReader;
#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"]
pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"]
pub type FifoUflowR = crate::BitReader;
#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"]
pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC_DONE` reader - Enables the interrupt for an ADC data acquisition completion"]
pub type AdcDoneR = crate::BitReader;
#[doc = "Field `ADC_DONE` writer - Enables the interrupt for an ADC data acquisition completion"]
pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"]
pub type TrigErrorR = crate::BitReader;
#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"]
pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
pub type FifoDepthTrigR = crate::BitReader;
#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
pub type FifoDepthTrigW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
    #[inline(always)]
    pub fn fifo_empty(&self) -> FifoEmptyR {
        FifoEmptyR::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Enables the interrupt for FIFO full"]
    #[inline(always)]
    pub fn fifo_full(&self) -> FifoFullR {
        FifoFullR::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
    #[inline(always)]
    pub fn fifo_oflow(&self) -> FifoOflowR {
        FifoOflowR::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
    #[inline(always)]
    pub fn fifo_uflow(&self) -> FifoUflowR {
        FifoUflowR::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
    #[inline(always)]
    pub fn adc_done(&self) -> AdcDoneR {
        AdcDoneR::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - Enables the interrupt for a trigger error"]
    #[inline(always)]
    pub fn trig_error(&self) -> TrigErrorR {
        TrigErrorR::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
    #[inline(always)]
    pub fn fifo_depth_trig(&self) -> FifoDepthTrigR {
        FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
    #[inline(always)]
    pub fn fifo_empty(&mut self) -> FifoEmptyW<IrqEnbSpec> {
        FifoEmptyW::new(self, 0)
    }
    #[doc = "Bit 1 - Enables the interrupt for FIFO full"]
    #[inline(always)]
    pub fn fifo_full(&mut self) -> FifoFullW<IrqEnbSpec> {
        FifoFullW::new(self, 1)
    }
    #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
    #[inline(always)]
    pub fn fifo_oflow(&mut self) -> FifoOflowW<IrqEnbSpec> {
        FifoOflowW::new(self, 2)
    }
    #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
    #[inline(always)]
    pub fn fifo_uflow(&mut self) -> FifoUflowW<IrqEnbSpec> {
        FifoUflowW::new(self, 3)
    }
    #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
    #[inline(always)]
    pub fn adc_done(&mut self) -> AdcDoneW<IrqEnbSpec> {
        AdcDoneW::new(self, 4)
    }
    #[doc = "Bit 5 - Enables the interrupt for a trigger error"]
    #[inline(always)]
    pub fn trig_error(&mut self) -> TrigErrorW<IrqEnbSpec> {
        TrigErrorW::new(self, 5)
    }
    #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
    #[inline(always)]
    pub fn fifo_depth_trig(&mut self) -> FifoDepthTrigW<IrqEnbSpec> {
        FifoDepthTrigW::new(self, 6)
    }
}
#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
impl crate::Readable for IrqEnbSpec {}
#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
impl crate::Writable for IrqEnbSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IRQ_ENB to value 0"]
impl crate::Resettable for IrqEnbSpec {
    const RESET_VALUE: u32 = 0;
}