VORAGO TECHNOLOGIES SST va416xx M4 1.3 ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 100MHz VORAGO Technologies \n \n ----------------------------------------------------------------------------\n Copyright (c) 2013-2020 VORAGO Technologies\n \n BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n \n THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n CM4 r0p1 little false true 4 false system_va416xx VOR_ 8 32 0x20 read-write 0x00000000 0xFFFFFFFF CLKGEN 1.0 Clock Generation Peripheral 0x40006000 0x0 0x100 registers LoCLK 45 CTRL0 Clock Generation Module Control Register 0 0x0 0x00000030 SYS_CLK_LOST_DET_EN Enable the circuit that detects loss of SYS_CLK [31:31] PLL_RESET Writing this bit to 1 puts the PLL into reset [30:30] CLK_DIV_SEL Selects the PLL out divider to divide by 1/2/4/8 [29:28] PLL_CLKR PLL Symbol; selects the values 1-16 for the reference divider [27:24] PLL_CLKF PLL Symbol; selects the values 1-64 for the multiplication factor [23:18] PLL_CLKOD PLL Symbol; selects the values 1-16 for the post VCO divider [17:14] PLL_BWADJ PLL Symbol; selects the values 1-64 for the bandwidth divider [13:8] PLL_TEST PLL Symbol; Reference-to-counters-to-output bypass when high [7:7] PLL_BYPASS PLL Symbol; reference-to-output bypass when high [6:6] PLL_PWDN PLL Symbol; power down when high [5:5] PLL_INTFB PLL Symbol; select internal feedback path when high rather than FCLK [4:4] CLKSEL_SYS Input clock select to PLL [3:2] REF_CLK_SEL PLL Reference Clock Select [1:0] STAT Clock Generation Module Status Register 0x4 read-only 0x00000000 SYSCLKLOST Set when SYS_CLK has dropped to less than 1MHz [3:3] read-only LOCKLOST LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles [2:2] read-only RFSLIP Reference cycle slip output (CLKOUT frequency high) [1:1] read-only FBSLIP Feedback cycle slip output (CLKOUT frequency low) [0:0] read-only CTRL1 Clock Generation Module Control Register 1 0x8 read-write 0x00000000 ADC_CLK_DIV_SEL Clock divider select for ADC [6:5] XTAL_N_EN Enables XTAL_N output [4:4] XTAL_EN Enables the crystal oscillator [3:3] PLL_LOST_LOCK_DET_EN Enables the PLL lock lost detection circuit [2:2] PLL_LCK_DET_REARM Resets/Rearms the PLL lock detect circuit [1:1] SYS_CLK_LOST_DET_REARM Resets/Rearms the SYS_CLK lost detection feature [0:0] SYSCONFIG 1.0 System Configuration Peripheral 0x40010000 0x0 0x1000 registers LVD 46 EDAC_MBE 76 EDAC_SBE 77 RST_STAT System Reset Status 0x0 read-write 0x00000000 POR Power On Reset Status [0:0] EXTRST External Reset Status [1:1] SYSRSTREQ SYSRESETREQ Reset Status [2:2] LOOKUP LOOKUP Reset Status [3:3] WATCHDOG WATCHDOG Reset Status [4:4] MEMERR Memory Error Reset Status [5:5] read-only RST_CNTL_ROM ROM Reset Control 0x4 0x0000003F RST_CNTL_RAM0 RAM Reset Control 0x8 0x0000003F RST_CNTL_RAM1 RAM Reset Control 0xC 0x0000003F ROM_PROT ROM Protection Configuration 0x10 0x00000000 WREN ROM Write Enable Bit [0:0] ROM_SCRUB ROM Scrub Period Configuration 0x14 read-write 0x00000000 VALUE Counter divide value [23:0] RESET Reset Counter [31:31] write-only oneToClear RAM0_SCRUB RAM0 Scrub Period Configuration 0x18 RAM1_SCRUB RAM1 Scrub Period Configuration 0x1C IRQ_ENB Enable EDAC Error Interrupt Register 0x20 read-write 0x00000000 ROMMBE ROM Multi Bit Interrupt [0:0] ROMSBE ROM Single Bit Interrupt [1:1] RAM0MBE RAM0 Multi Bit Interrupt [2:2] RAM0SBE RAM0 Single Bit Interrupt [3:3] RAM1MBE RAM1 Multi Bit Interrupt [4:4] RAM1SBE RAM1 Single Bit Interrupt [5:5] IRQ_RAW Raw EDAC Error Interrupt Status 0x24 read-only 0x00000000 IRQ_END Enabled EDAC Error Interrupt Status 0x28 read-only 0x00000000 IRQ_CLR Clear EDAC Error Interrupt Status 0x2C write-only 0x00000000 oneToClear RAM0_SBE Count of RAM0 EDAC Single Bit Errors 0x30 0x00000000 COUNT RAM0 EDAC Single Bit Errors [15:0] RAM1_SBE Count of RAM1 EDAC Single Bit Errors 0x34 RAM0_MBE Count of RAM0 EDAC Multi Bit Errors 0x38 0x00000000 COUNT RAM0 Multi Bit Errors [15:0] RAM1_MBE Count of RAM1 EDAC Multi Bit Errors 0x3C ROM_SBE Count of ROM EDAC Single Bit Errors 0x40 ROM_MBE Count of ROM EDAC Multi Bit Errors 0x44 ROM_RETRIES ROM BOOT Retry count 0x48 read-only 0x00000000 COUNT Count of ROM block Retries [7:0] REFRESH_CONFIG_H Register Refresh Rate for TMR registers 0x4C 0x00000000 DIVCOUNT Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles [7:0] TESTMODE Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly. [31:30] TIM_RESET TIM Reset Control 0x50 0xFFFFFFFF TIM_RESET Reset of a given TIMER [23:0] TIM_CLK_ENABLE TIM Enable Control 0x54 0x00000000 TIMERS Clock enable of a given TIMER [23:0] PERIPHERAL_RESET Peripheral Reset Control 0x58 0x7F7BEFFF SPI0 Resetn of SPI0 [0:0] SPI1 Resetn of SPI1 [1:1] SPI2 Resetn of SPI2 [2:2] SPI3 Resetn of SPI3 [3:3] UART0 Resetn of UART0 [4:4] UART1 Resetn of UART1 [5:5] UART2 Resetn of UART2 [6:6] I2C0 Resetn of I2C0 [7:7] I2C1 Resetn of I2C1 [8:8] I2C2 Resetn of I2C2 [9:9] CAN0 Resetn of CAN0 [10:10] CAN1 Resetn of CAN1 [11:11] TRNG Resetn of TRNG [12:12] ADC Resetn of ADC [13:13] DAC Resetn of DAC [14:14] DMA Resetn of DMA [15:15] EBI Resetn of EBI [16:16] ETH Resetn of Ethernet [17:17] SPW Resetn of SpaceWire [18:18] CLKGEN RESETn of PLL in Clock Generation Module [19:19] IRQ Resetn of IRQ Router [20:20] IOCONFIG Resetn of IO CONFIG [21:21] UTILITY Resetn of UTILITY peripheral [22:22] WDOG Resetn of WDOG [23:23] PORTA Resetn of PORTA [24:24] PORTB Resetn of PORTB [25:25] PORTC Resetn of PORTC [26:26] PORTD Resetn of PORTD [27:27] PORTE Resetn of PORTE [28:28] PORTF Resetn of PORTF [29:29] PORTG Resetn of PORTG [30:30] PERIPHERAL_CLK_ENABLE Peripheral Enable Control 0x5C 0x00880000 SPW_M4_CTRL SPW M4 control register 0x60 0x00030000 LREN Lockup reset enable [17:17] SPW_PAD_EN SPW pad enable [16:16] REG_WR_KEY Fuse-analog register writes enabled when key = 0xfeed [15:0] PMU_CTRL PMU Control Register 0x64 0x00000000 LVL_SLCT Select the POK detect level [1:0] WAKEUP_CNT Wakeup Control 0x68 0x00000007 CNTSTRT Launch SLP mode in analog block [3:3] WKUP_CNT Used to set a time to wake up the processor after the device has been put in a low power state [2:0] EBI_CFG0 EBI Config Register 0 0x6C 0x00000000 ADDRLOW0 Lower bound address for CEN0 [7:0] ADDRHIGH0 Upper bound address for CEN0 [15:8] CFGREADCYCLE Number of cycles for a read - N plus 1 [18:16] CFGWRITECYCLE Number of cycles for a write - N plus 1 [21:19] CFGTURNAROUNDCYCLE Number of cycles for turnaround - N plus 1 [24:22] CFGSIZE 8 bit (0) or 16 bit (1) port size [25:25] EBI_CFG1 EBI Config Register 1 0x70 0x00000000 EBI_CFG2 EBI Config Register 2 0x74 0x00000000 EBI_CFG3 EBI Config Register 3 0x78 0x00000000 ANALOG_CNTL Analog Control Register 0x7C 0x00000000 TMOSC Test Mode [0:0] TMPOKDIS Test Mode [1:1] TM_ADCMUX_N Test Mode [2:2] TM_ADCMUX_P Test Mode [3:3] TMRATIO Test Mode [4:4] TMATOMUX Test Mode [6:5] ADC_STEST Number of clocks for sample time [12:9] RCLK_POS_EN Enable normal test clock [14:14] RCLK_NEG_EN Enable inverted test clock [15:15] APB2CLK_POS_EN Enable normal APB2CLK for test output [16:16] APB2CLK_NEG_EN Enable inverted APB2CLK for test output [17:17] TM_ANALOG_PD_EN Enables pull down on analog pads [18:18] JMP2BOOT Enables a skip of all delay counters and eFuse read [19:19] SKIPBOOT Enables a skip of all delay counters, eFuse read, and boot [20:20] SW_CLKDIV10 Initial SpW Clock Divider Value 0x80 read-write 0x00000009 SW_CLKDIV10 Defines the initial value for the SpW clock, defaults to divide by ten [7:0] REFRESH_CONFIG_L Register Refresh Rate for TMR registers 0x84 read-write 0x0000000F DIVCOUNT Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles [31:0] DAC0_CAL DAC0 Calibration Register 0xFD0 read-only 0x00000000 DAC0_CAL DAC0 Calibration bits [4:0] DAC1_CAL DAC1 Calibration Register 0xFD4 read-only 0x00000000 DAC1_CAL DAC1 Calibration bits [4:0] ADC_CAL ADC Calibration Register 0xFD8 read-only 0x00000000 ADC_CAL ADC Calibration bits [4:0] BG_CAL Bandgap Calibration Register 0xFDC read-only 0x00000000 BG_CAL Bandgap Calibration bits [2:0] DREG_CAL Digital LDO Regulator Calibration Register 0xFE0 read-only 0x00000000 DREG_CAL Digital LDO Regulator Calibration bits [8:0] AREG_CAL Analog LDO Regulator Calibration Register 0xFE4 read-only 0x00000000 AREG_CAL Analog LDO Regulator Calibration bits [8:0] HBO_CAL Heart Beat OSC Calibration Register 0xFE8 read-only 0x00000000 OSC_CAL 1MHz OSC Calibration bit [3:3] HBO_CAL Heart Beat OSC Calibration bits [2:0] EF_CONFIG EFuse Config Register 0xFEC read-only 0x0A800C40 ROM_SPEED Specifies the speed of ROM_SCK [1:0] ROM_SIZE Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset [5:2] ROM_NOCHECK When set to 1, the ROM check is skipped [6:6] BOOT_DELAY Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset [9:7] ROM_READ SPI ROM read instruction code [17:10] ROM_LATENCY Number of bits of latency from Address until data from the SPI ROM [22:18] ROM_ADDRESS ROM Address Mode [24:23] ROM_DLYCAP ROM SPI Delayed capture [25:25] ROM_STATUS The first data byte from the SPI ROM following an address is taken as a status byte [26:26] RM This bit controls the internal RAM read timing and must be maintained at this value [27:27] WM This bit controls the internal RAM write timing and must be maintained at this value [28:28] EF_ID0 EFuse ID0 Register 0xFF0 read-only 0x00000000 EF_ID1 EFuse ID1 Register 0xFF4 read-only 0x00000000 PROCID Processor ID Register 0xFF8 read-only 0x040057E3 PERID Peripheral ID Register 0xFFC read-only 0x028007E9 MANUFACTURER_ID MANUFACTURER_ID [11:0] read-only PERIPHERAL_ID PERIPHERAL_ID [23:16] read-only PERIPHERAL_VER PERIPHERAL_VER [31:24] read-only DMA 1.0 DMA Controller Block 0x40001000 0x0 0x1000 registers DMA_ERROR 43 DMA_ACTIVE0 174 DMA_ACTIVE1 175 DMA_ACTIVE2 176 DMA_ACTIVE3 177 DMA_DONE0 178 DMA_DONE1 179 DMA_DONE2 180 DMA_DONE3 181 STATUS DMA Status 0x0 read-only 0x00000000 TEST_STATUS Test Status Logic Included [31:28] read-write CHNLS_MINUS1 Number of Available Channels Minus 1 [20:16] STATE Current State of the control state machine [7:4] MASTER_ENABLE Enable status of the controller [0:0] CFG DMA Configuration 0x4 write-only 0x00000000 CHNL_PROT_CTRL HPROT[3:0] [7:5] MASTER_ENABLE PLL Symbol; Feedback cycle slip output (CLKOUT frequency low) [0:0] read-write CTRL_BASE_PTR Base Pointer for DMA Control Registers 0x8 0x00000000 CTRL_BASE_PTR Base Pointer for DMA Control Registers [31:7] ALT_CTRL_BASE_PTR DMA Channel alternate control data base pointer 0xC read-write 0x00000000 ALT_CTRL_BASE_PTR Base Pointer for Alternate DMA Control Register [31:0] WAITONREQ_STATUS DMA channel wait on request status 0x10 read-only 0x00000000 CH3 DMA wait on request [3:3] read-write CH2 DMA wait on request [2:2] read-write CH1 DMA wait on request [1:1] read-write CH0 DMA wait on request [0:0] read-write CHNL_SW_REQUEST DMA channel software request 0x14 write-only 0x00000000 CH3 Channel SW request [3:3] read-write CH2 Channel SW request [2:2] read-write CH1 Channel SW request [1:1] read-write CH0 Channel SW request [0:0] read-write CHNL_USEBURST_SET DMA channel useburst set 0x18 0x00000000 CH3 Channel use burst set [3:3] read-write CH2 Channel use burst set [2:2] read-write CH1 Channel use burst set [1:1] read-write CH0 Channel use burst set [0:0] read-write CHNL_USEBURST_CLR DMA channel useburst clear 0x1C 0x00000000 CH3 Channel use burst clear [3:3] read-write CH2 Channel use burst clear [2:2] read-write CH1 Channel use burst clear [1:1] read-write CH0 Channel use burst clear [0:0] read-write CHNL_REQ_MASK_SET DMA channel request mask set 0x20 0x00000000 CH3 Channel Request Mask set [3:3] read-write CH2 Channel Request Mask set [2:2] read-write CH1 Channel Request Mask set [1:1] read-write CH0 Channel Request Mask set [0:0] read-write CHNL_REQ_MASK_CLR DMA channel request mask clear 0x24 0x00000000 CH3 Channel Request Mask clear [3:3] read-write CH2 Channel Request Mask clear [2:2] read-write CH1 Channel Request Mask clear [1:1] read-write CH0 Channel Request Mask clear [0:0] read-write CHNL_ENABLE_SET DMA channel enable set 0x28 0x00000000 CH3 Channel Enable set [3:3] read-write CH2 Channel Enable set [2:2] read-write CH1 Channel Enable set [1:1] read-write CH0 Channel Enable set [0:0] read-write CHNL_ENABLE_CLR DMA channel enable clear 0x2C 0x00000000 CH3 Channel Enable clear [3:3] read-write CH2 Channel Enable clear [2:2] read-write CH1 Channel Enable clear [1:1] read-write CH0 Channel Enable clear [0:0] read-write CHNL_PRI_ALT_SET DMA channel primary alternate set 0x30 0x00000000 CH3 Channel PRI_ALT set [3:3] read-write CH2 Channel PRI_ALT set [2:2] read-write CH1 Channel PRI_ALT set [1:1] read-write CH0 Channel PRI_ALT set [0:0] read-write CHNL_PRI_ALT_CLR DMA channel primary alternate clear 0x34 0x00000000 CH3 Channel PRI_ALT clear [3:3] read-write CH2 Channel PRI_ALT clear [2:2] read-write CH1 Channel PRI_ALT clear [1:1] read-write CH0 Channel PRI_ALT clear [0:0] read-write CHNL_PRIORITY_SET DMA channel priority set 0x38 read-write 0x00000000 CH3 Channel PRIORITY set [3:3] read-write CH2 Channel PRIORITY set [2:2] read-write CH1 Channel PRIORITY set [1:1] read-write CH0 Channel PRIORITY set [0:0] read-write CHNL_PRIORITY_CLR DMA channel priority clear 0x3C write-only 0x00000000 CH3 Channel PRIORITY clear [3:3] write-only CH2 Channel PRIORITY clear [2:2] write-only CH1 Channel PRIORITY clear [1:1] write-only CH0 Channel PRIORITY clear [0:0] write-only ERR_CLR DMA bus error clear 0x4C 0x00000000 ERR_CLR Error Clear [0:0] read-write INTEGRATION_CFG DMA integration configuration 0xE00 0x00000000 INT_TEST_EN Error Clear [0:0] read-write STALL_STATUS DMA stall status 0xE08 0x00000000 STALL_STATUS DMA is stalled [0:0] read-only DMA_REQ_STATUS DMA Configuration 0xE10 0x00000000 CH3 DMA Request Status for this CH [3:3] read-write CH2 DMA Request Status for this CH [2:2] read-write CH1 DMA Request Status for this CH [1:1] read-write CH0 DMA Request Status for this CH [0:0] read-write DMA_SREQ_STATUS DMA single request status 0xE18 0x00000000 CH3 DMA SRequest Status for this CH [3:3] read-write CH2 DMA SRequest Status for this CH [2:2] read-write CH1 DMA SRequest Status for this CH [1:1] read-write CH0 DMA SRequest Status for this CH [0:0] read-write DMA_DONE_SET DMA done set 0xE20 0x00000000 CH3 DMA Done Set for this CH [3:3] read-write CH2 DMA Done Set for this CH [2:2] read-write CH1 DMA Done Set for this CH [1:1] read-write CH0 DMA Done Set for this CH [0:0] read-write DMA_DONE_CLR DMA done clear 0xE24 0x00000000 CH3 DMA Done clear for this CH [3:3] read-write CH2 DMA Done clear for this CH [2:2] read-write CH1 DMA Done clear for this CH [1:1] read-write CH0 DMA Done clear for this CH [0:0] read-write DMA_ACTIVE_SET DMA active set 0xE28 0x00000000 CH3 DMA Active Set [3:3] read-write CH2 DMA Active Set [2:2] read-write CH1 DMA Active Set [1:1] read-write CH0 DMA Active Set [0:0] read-write DMA_ACTIVE_CLR DMA active clear 0xE2C 0x00000000 CH3 DMA Active clear [3:3] read-write CH2 DMA Active clear [2:2] read-write CH1 DMA Active clear [1:1] read-write CH0 DMA Active clear [0:0] read-write ERR_SET DMA bus error set 0xE48 0x00000000 ERR_SET Set Error [0:0] read-only PERIPH_ID_4 DMA Peripheral ID 4 0xFD0 0x00000004 BLOCK_COUNT The Number of 4k Address Blocks Required [7:4] JEP106_C_CODE JEP106 [3:0] PERIPH_ID_0 DMA Peripheral ID 0 0xFE0 0x00000030 PART_NUMBER_0 Part Number [7:0] PERIPH_ID_1 DMA Peripheral ID 1 0xFE4 read-only 0x000000B2 JEP106_ID_3_0 Indentity Code [7:4] PART_NUMBER_1 Part Number 1 [3:0] PERIPH_ID_2 DMA Peripheral ID 2 0xFE8 0x000000BC REVISION Revision [7:4] JEDEC_USED JEDEC [3:3] JEP106_ID_6_4 JEP106 [2:0] PERIPH_ID_3 DMA Peripheral ID 3 0xFEC 0x00000000 MOD_NUMBER Controller Modifications [3:0] PRIMECELL_ID_0 DMA PrimeCell ID 0 0xFF0 0x0000000D PRIMECELL_ID_0 PrimeCell Identification [7:0] PRIMECELL_ID_1 DMA PrimeCell ID 1 0xFF4 0x000000F0 PRIMECELL_ID_1 PrimeCell Identification [7:0] PRIMECELL_ID_2 DMA PrimeCell ID 2 0xFF8 0x00000005 PRIMECELL_ID_2 PrimeCell Identification [7:0] PRIMECELL_ID_3 DMA PrimeCell ID 3 0xFFC 0x000000B1 PRIMECELL_ID_3 PrimeCell Identification [7:0] IOCONFIG 1.0 IO Pin Configuration Peripheral 0x40011000 0x0 0x1000 registers 16 0x4 PORTA[%s] PORTA Pin Configuration Register 0x0 0x00000000 FLTTYPE Input Filter Selectoin [2:0] SYNC Synchronize to system clock 0 DIRECT Direct input, no synchronization 1 FILTER1 Require 2 samples to have the same value 2 FILTER2 Require 3 samples to have the same value 3 FILTER3 Require 4 samples to have the same value 4 FILTER4 Require 5 samples to have the same value 5 FLTCLK Input Filter Clock Selection [5:3] INVINP Input Invert Selection [6:6] IEWO Input Enable While Output enabled [7:7] OPENDRN Output Open Drain Mode [8:8] INVOUT Output Invert Selection [9:9] PLEVEL Internal Pull up/down level [10:10] PEN Enable Internal Pull up/down [11:11] PWOA Enable Pull when output active [12:12] FUNSEL Pin Function Selection [15:13] IODIS IO Pin Disable [16:16] PORTB[%s] PORTB Pin Configuration Register 0x40 0x00000000 PORTC[%s] PORTC Pin Configuration Register 0x80 0x00000000 PORTD[%s] PORTD Pin Configuration Register 0xC0 0x00000000 PORTE[%s] PORTE Pin Configuration Register 0x100 0x00000000 PORTF[%s] PORTF Pin Configuration Register 0x140 0x00000000 8 0x4 PORTG[%s] PORTG Pin Configuration Register 0x180 0x00000000 CLKDIV0 Clock divide value. 0 will disable the clock 0x1C0 read-only 0x00000000 CLKDIV1 Clock divide value. 0 will disable the clock 0x1C4 read-write 0x00000000 CLKDIV2 Clock divide value. 0 will disable the clock 0x1C8 read-write 0x00000000 CLKDIV3 Clock divide value. 0 will disable the clock 0x1CC read-write 0x00000000 CLKDIV4 Clock divide value. 0 will disable the clock 0x1D0 read-write 0x00000000 CLKDIV5 Clock divide value. 0 will disable the clock 0x1D4 read-write 0x00000000 CLKDIV6 Clock divide value. 0 will disable the clock 0x1D8 read-write 0x00000000 CLKDIV7 Clock divide value. 0 will disable the clock 0x1DC read-write 0x00000000 PERID Peripheral ID Register 0xFFC read-only 0x028207E9 UTILITY 1.0 Utility Peripheral 0x40020000 0x0 0x1000 registers SYND_DATA Data Register 0x0 read-write 0x00000000 SYND_SYND Syndrome Data Register 0x4 read-write 0x00000000 SYND_SYND Provides bits 11:0 for syndrome, 2x6-bit [11:0] SYND_ENC_32_44 EDAC Encode 0x8 read-write 0x00000000 SYND_ENC_31_16 Computed syndrome value for bits 31-16 [11:6] SYND_ENC_7_0 Computed syndrome value for bits 15-0 [5:0] SYND_CHECK_32_44_DATA EDAC Decode Data 0xC read-only 0x00000000 SYND_CHECK_32_44_SYND EDAC Decode Syndrome 0x10 read-only 0x00000000 MBE Multiple bit error detect status [15:14] SBE Single bit error detect status [13:12] SYND_CHECK_32_44_SYND Correct syndrome value [11:0] ROM_TRAP_ADDRESS ROM EDAC Trap Address 0x14 read-write 0x00000000 ENABLE Enable Trap mode [31:31] ADDR Address bits for trap match [30:2] ROM_TRAP_SYND ROM EDAC Trap Syndrome 0x18 read-write 0x00000000 R0M_SYND_31_16 6-bit syndrome value for bits 31-16 [11:6] ROM_SYND_7_0 6-bit syndrome value for bits 15-0 [5:0] RAM_TRAP_ADDR0 RAM0 EDAC Trap Address 0x1C read-write 0x00000000 ENABLE Enable Trap mode [31:31] ADDR Address bits for trap match [30:2] RAM_TRAP_SYND0 RAM0 EDAC Trap Syndrome 0x20 read-write 0x00000000 RAM_SYND_31_16 6-bit syndrome value for bits 31-16 [11:6] RAM_SYND_7_0 6-bit syndrome value for bits 15-0 [5:0] RAM_TRAP_ADDR1 RAM1 EDAC Trap Address 0x24 read-write 0x00000000 ENABLE Enable Trap mode [31:31] ADDR Address bits for trap match [30:2] RAM_TRAP_SYND1 RAM1 EDAC Trap Syndrome 0x28 read-write 0x00000000 RAM_SYND_31_16 6-bit syndrome value for bits 31-16 [11:6] RAM_SYND_7_0 6-bit syndrome value for bits 15-0 [5:0] SYND_ENC_32_52 EDAC Encode 0x120 read-only 0x00000000 SYND_ENC_32_52 Computed syndrome value for bits 15-0 [19:0] SYND_CHECK_32_52_DATA EDAC Decode Data 0x124 read-only 0x00000000 SYND_CHECK_32_52_SYND EDAC Decode Syndrome 0x128 read-only 0x00000000 MBE Multiple bit error detect status [31:28] SBE Single bit error detect status [27:24] SYND_CHECK_32_52_SYND Corrected syndrome value [19:0] PERID Peripheral ID Register 0xFFC read-only 0x028407E9 PORTA 1.0 GPIO Peripheral GPIO GPIO 0x40012000 0x0 0x400 registers PORTA0 78 PORTA1 79 PORTA2 80 PORTA3 81 PORTA4 82 PORTA5 83 PORTA6 84 PORTA7 85 PORTA8 86 PORTA9 87 PORTA10 88 PORTA11 89 PORTA12 90 PORTA13 91 PORTA14 92 PORTA15 93 PORTB0 94 PORTB1 95 PORTB2 96 PORTB3 97 PORTB4 98 PORTB5 99 PORTB6 100 PORTB7 101 PORTB8 102 PORTB9 103 PORTB10 104 PORTB11 105 PORTB12 106 PORTB13 107 PORTB14 108 PORTB15 109 PORTC0 110 PORTC1 111 PORTC2 112 PORTC3 113 PORTC4 114 PORTC5 115 PORTC6 116 PORTC7 117 PORTC8 118 PORTC9 119 PORTC10 120 PORTC11 121 PORTC12 122 PORTC13 123 PORTC14 124 PORTC15 125 PORTD0 126 PORTD1 127 PORTD2 128 PORTD3 129 PORTD4 130 PORTD5 131 PORTD6 132 PORTD7 133 PORTD8 134 PORTD9 135 PORTD10 136 PORTD11 137 PORTD12 138 PORTD13 139 PORTD14 140 PORTD15 141 PORTE0 142 PORTE1 143 PORTE2 144 PORTE3 145 PORTE4 146 PORTE5 147 PORTE6 148 PORTE7 149 PORTE8 150 PORTE9 151 PORTE10 152 PORTE11 153 PORTE12 154 PORTE13 155 PORTE14 156 PORTE15 157 PORTF0 158 PORTF1 159 PORTF2 160 PORTF3 161 PORTF4 162 PORTF5 163 PORTF6 164 PORTF7 165 PORTF8 166 PORTF9 167 PORTF10 168 PORTF11 169 PORTF12 170 PORTF13 171 PORTF14 172 PORTF15 173 DATAIN Data In Register 0x0 read-only 0x00000000 4 0x1 DATAINBYTE[%s] Data In Register by Byte DATAIN 0x0 0x8 read-only 0x00000000 DATAINRAW Data In Raw Register 0x4 0x00000000 DATAINRAWBYTE[%s] Data In Raw Register by Byte DATAINRAW 0x4 0x00000000 DATAOUT Data Out Register 0x8 write-only 0x00000000 4 0x1 DATAOUTBYTE[%s] Data Out Register by Byte DATAOUT 0x8 0x8 write-only 0x00000000 DATAOUTRAW Data Out Register 0xC 0x00000000 DATAOUTRAWBYTE[%s] Data Out Register by Byte DATAOUTRAW 0xC 0x00000000 SETOUT Set Out Register 0x10 0x00000000 SETOUTBYTE[%s] Set Out Register by Byte SETOUT 0x10 0x00000000 CLROUT Clear Out Register 0x14 0x00000000 CLROUTBYTE[%s] Clear Out Register by Byte CLROUT 0x14 0x00000000 TOGOUT Toggle Out Register 0x18 0x00000000 TOGOUTBYTE[%s] Toggle Out Register by Byte TOGOUT 0x18 0x00000000 DATAMASK Data mask Register 0x1C 0x00000000 4 0x1 DATAMASKBYTE[%s] Data Out Register by Byte DATAMASK 0x1C 0x8 0x00000000 DIR Direction Register (1:Output, 0:Input) 0x20 0x00000000 DIRBYTE[%s] Direction Register by Byte DIR 0x20 0x00000000 PULSE Pulse Mode Register 0x24 0x00000000 PULSEBYTE[%s] Pulse Mode Register by Byte PULSE 0x24 0x00000000 PULSEBASE Pulse Base Value Register 0x28 0x00000000 PULSEBASEBYTE[%s] Pulse Base Mode Register by Byte PULSEBASE 0x28 0x00000000 DELAY1 Delay1 Register 0x2C 0x00000000 DELAY1BYTE[%s] Delay1 Register by Byte DELAY1 0x2C 0x00000000 DELAY2 Delay2 Register 0x30 0x20 read-write 0x00000000 DELAY2BYTE[%s] Delay2 Register by Byte DELAY2 0x30 0x00000000 IRQ_SEN Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive) 0x34 0x00000000 IRQ_EDGE Interrupt Both Edge Register (1:Both Edges, 0:Single Edge) 0x38 0x00000000 IRQ_EVT Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) 0x3C 0x00000000 IRQ_ENB Interrupt Enable Register 0x40 0x00000000 IRQ_RAW Raw Interrupt Status 0x44 read-only 0x00000000 IRQ_END Masked Interrupt Status 0x48 read-only 0x00000000 EDGE_STATUS Edge Status Register 0x4C read-write 0x00000000 PERID Peripheral ID Register 0x3FC 0x20 read-only 0x021007E9 PORTB 0x40012400 PORTC 0x40012800 PORTD 0x40012C00 PORTE 0x40013000 PORTF 0x40013400 PORTG 0x40013800 TIM0 1.0 Timer/Counter Peripheral Timer_Counter TIM 0x40018000 0x0 0x400 registers TIM0 48 TIM1 49 TIM2 50 TIM3 51 TIM4 52 TIM5 53 TIM6 54 TIM7 55 TIM8 56 TIM9 57 TIM10 58 TIM11 59 TIM12 60 TIM13 61 TIM14 62 TIM15 63 TIM16 64 TIM17 65 TIM18 66 TIM19 67 TIM20 68 TIM21 69 TIM22 70 TIM23 71 CTRL Control Register 0x0 read-write ENABLE Counter Enable [0:0] ACTIVE Counter Active [1:1] read-only AUTO_DISABLE Auto Disables the counter (set ENABLE to 0) when the count reaches 0 [2:2] AUTO_DEACTIVATE Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0 [3:3] IRQ_ENB Interrupt Enable [4:4] STATUS_SEL Counter Status Selection [7:5] DONE Single cycle pulse when the counter reaches 0 0 ACTIVE Returns the counter ACTIVE bit 1 TOGGLE Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output. 2 PWMA Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE 3 PWMB Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE 4 ENABLED Returns the counter ENABLED bit 5 PWMA_ACTIVE Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0 6 STATUS_INV Invert the Output Status [8:8] REQ_STOP Stop Request [9:9] RST_VALUE The value that counter start from after reaching 0. 0x4 CNT_VALUE The current value of the counter 0x8 ENABLE Alternate access to the Counter ENABLE bit in the CTRL Register 0xC ENABLE Counter Enable [0:0] CSD_CTRL The Cascade Control Register. Controls the counter external enable signals 0x10 CSDEN0 Cascade 0 Enable [0:0] CSDINV0 Cascade 0 Invert [1:1] CSDEN1 Cascade 1 Enable [2:2] CSDINV1 Cascade 1 Invert [3:3] DCASOP Dual Cascade Operation (0:AND, 1:OR) [4:4] CSDTRG0 Cascade 0 Enabled as Trigger [6:6] CSDTRG1 Cascade 1 Enabled as Trigger [7:7] CSDEN2 Cascade 2 Enable [8:8] CSDINV2 Cascade 2 Invert [9:9] CSDTRG2 Cascade 2 Trigger mode [10:10] CASCADE0 Cascade Enable Selection 0x14 CASSEL Cascade Selection [7:0] CASCADE1 Cascade Enable Selection 0x18 CASCADE2 Cascade Enable Selection 0x1C PWM_VALUE The Pulse Width Modulation Value 0x20 PWMA_VALUE The Pulse Width Modulation ValueA PWM_VALUE 0x20 PWMB_VALUE The Pulse Width Modulation ValueB 0x24 PERID Peripheral ID Register 0x3FC read-only 0x021107E9 TIM1 0x40018400 TIM2 0x40018800 TIM3 0x40018C00 TIM4 0x40019000 TIM5 0x40019400 TIM6 0x40019800 TIM7 0x40019C00 TIM8 0x4001A000 TIM9 0x4001A400 TIM10 0x4001A800 TIM11 0x4001AC00 TIM12 0x4001B000 TIM13 0x4001B400 TIM14 0x4001B800 TIM15 0x4001BC00 TIM16 0x40028000 TIM17 0x40028400 TIM18 0x40028800 TIM19 0x40028C00 TIM20 0x40029000 TIM21 0x40029400 TIM22 0x40029800 TIM23 0x40029C00 UART0 1.0 UART Peripheral UART UART 0x40024000 0x0 0x1000 registers UART0_TX 24 UART0_RX 25 UART1_TX 26 UART1_RX 27 UART2_TX 28 UART2_RX 29 DATA Data In/Out Register 0x0 0x00000000 ENABLE Enable Register 0x4 0x00000000 RXENABLE Rx Enable [0:0] TXENABLE Tx Enable [1:1] CTRL Control Register 0x8 0x00000000 PAREN Parity Enable [0:0] PAREVEN Parity Even/Odd(1/0) [1:1] PARSTK Parity Sticky [2:2] STOPBITS Stop Bits 1/2(0/1) [3:3] WORDSIZE Word Size in Bits 5/6/7/8(00/01/10/11) [5:4] LOOPBACK Loopback Enable [6:6] LOOPBACKBLK Loopback Block [7:7] AUTOCTS Enable Auto CTS mode [8:8] DEFRTS Default RTSn value [9:9] AUTORTS Enable Auto RTS mode [10:10] BAUD8 Enable BAUD8 mode [11:11] CLKSCALE Clock Scale Register 0xC 0x00000000 FRAC Fractional Divide (64ths) [5:0] INT Integer Divide [23:6] RESET Reset Baud Counter [31:31] write-only RXSTATUS Status Register 0x10 read-only 0x00000000 RDAVL Read Data Available [0:0] RDNFULL Read Fifo NOT Full [1:1] RXBUSY RX Busy Receiving [2:2] RXTO RX Receive Timeout [3:3] RXOVR Read Fifo Overflow [4:4] RXFRM RX Framing Error [5:5] RXPAR RX Parity Error [6:6] RXBRK RX Break Error [7:7] RXBUSYBRK RX Busy Receiving Break [8:8] RXADDR9 Address Match for 9 bit mode [9:9] RXRTSN RX RTSn Output Value [15:15] TXSTATUS Status Register 0x14 read-only 0x00000000 WRRDY Write Fifo NOT Full [0:0] WRBUSY Write Fifo Full [1:1] TXBUSY TX Busy Transmitting [2:2] WRLOST Write Data Lost (Fifo Overflow) [3:3] TXCTSN TX CTSn Input Value [15:15] FIFO_CLR Clear FIFO Register 0x18 write-only 0x00000000 RXFIFO Clear Rx FIFO [0:0] TXFIFO Clear Tx FIFO [1:1] TXBREAK Break Transmit Register 0x1C write-only 0x00000000 ADDR9 Address9 Register 0x20 read-write 0x00000000 ADDR9MASK Address9 Mask Register 0x24 read-write 0x00000000 IRQ_ENB IRQ Enable Register 0x28 read-write 0x00000000 IRQ_RX RX Interrupt [0:0] IRQ_RX_STATUS RX Status Interrupt [1:1] IRQ_RX_TO RX Timeout Interrupt [2:2] IRQ_TX TX Interrupt [4:4] IRQ_TX_STATUS TX Status Interrupt [5:5] IRQ_TX_EMPTY TX Empty Interrupt [6:6] IRQ_TX_CTS TX CTS Change Interrupt [7:7] IRQ_RAW IRQ Raw Status Register 0x2C read-only 0x00000000 IRQ_END IRQ Enabled Status Register 0x30 read-only 0x00000000 IRQ_CLR IRQ Clear Status Register 0x34 write-only 0x00000000 RXFIFOIRQTRG Rx FIFO IRQ Trigger Level 0x38 TXFIFOIRQTRG Tx FIFO IRQ Trigger Level 0x3C RXFIFORTSTRG Rx FIFO RTS Trigger Level 0x40 STATE Internal STATE of UART Controller 0x44 0x20 read-only PERID Peripheral ID Register 0xFFC read-only 0x021207E9 UART1 0x40025000 UART2 0x40017000 SPI0 1.0 SPI Peripheral SPI SPI 0x40015000 0x0 0x400 registers SPI0_TX 16 SPI0_RX 17 SPI1_TX 18 SPI1_RX 19 SPI2_TX 20 SPI2_RX 21 SPI3_TX 22 SPI3_RX 23 CTRL0 Control Register 0 0x0 0x00000000 SIZE Data Size(0x3=>4, 0xf=>16) [3:0] SPO SPI Clock Polarity [6:6] SPH SPI Clock Phase [7:7] SCRDV Serial Clock Rate divide+1 value [15:8] CTRL1 Control Register 1 0x4 0x00000000 LBM Loop Back [0:0] ENABLE Enable [1:1] MS Master/Slave (0:Master, 1:Slave) [2:2] SOD Slave output Disable [3:3] SS Slave Select [6:4] BLOCKMODE Block Mode Enable [7:7] BMSTART Block Mode Start Status Enable [8:8] BMSTALL Block Mode Stall Enable [9:9] MDLYCAP Master Delayed Capture Enable [10:10] MTXPAUSE Master Tx Pause Enable [11:11] DATA Data Input/Output 0x8 STATUS Status Register 0xC read-only 0x00000000 TFE Transmit FIFO empty [0:0] TNF Transmit FIFO not full [1:1] RNE Receive FIFO not empty [2:2] RFF Receive FIFO Full [3:3] BUSY Busy [4:4] RXDATAFIRST Pending Data is first Byte in BLOCKMODE [5:5] RXTRIGGER RX FIFO Above Trigger Level [6:6] TXTRIGGER TX FIFO Below Trigger Level [7:7] CLKPRESCALE Clock Pre Scale divide value 0x10 IRQ_ENB Interrupt Enable Register 0x14 read-write 0x00000000 RORIM RX Overrun [0:0] RTIM RX Timeout [1:1] RXIM RX Fifo is at least half full [2:2] TXIM TX Fifo is at least half empty [3:3] IRQ_RAW Raw Interrupt Status Register 0x18 read-only IRQ_END Enabled Interrupt Status Register 0x1C read-only IRQ_CLR Clear Interrupt Status Register 0x20 write-only oneToClear RXFIFOIRQTRG Rx FIFO IRQ Trigger Level 0x24 TXFIFOIRQTRG Tx FIFO IRQ Trigger Level 0x28 FIFO_CLR Clear FIFO Register 0x2C write-only RXFIFO Clear Rx FIFO [0:0] TXFIFO Clear Tx FIFO [1:1] STATE Internal STATE of SPI Controller 0x30 read-only PERID Peripheral ID Register 0x3FC read-only 0x021307E9 SPI1 0x40015400 SPI2 0x40015800 SPI3 0x40015C00 I2C0 1.0 I2C Peripheral I2C I2C 0x40016000 0x0 0x400 registers I2C0_MS 30 I2C0_SL 31 I2C1_MS 32 I2C1_SL 33 I2C2_MS 34 I2C2_SL 35 I2C0_MS_RX 182 I2C0_MS_TX 183 I2C0_SL_RX 184 I2C0_SL_TX 185 I2C1_MS_RX 186 I2C1_MS_TX 187 I2C1_SL_RX 188 I2C1_SL_TX 189 I2C2_MS_RX 190 I2C2_MS_TX 191 I2C2_SL_RX 192 I2C2_SL_TX 193 CTRL Control Register 0x0 0x00000000 CLKENABLED I2C CLK Enabled [0:0] ENABLED I2C Activated [1:1] ENABLE I2C Active [2:2] TXFEMD TX FIFIO Empty Mode [3:3] RXFFMD RX FIFO Full Mode [4:4] ALGFILTER Enable Input Analog Glitch Filter [5:5] DLGFILTER Enable Input Digital Glitch Filter [6:6] LOOPBACK Enable LoopBack Mode [8:8] TMCONFIGENB Enable Timing Config Register [9:9] CLKSCALE Clock Scale divide value 0x4 VALUE Enable FastMode [30:0] FASTMODE Enable FastMode [31:31] WORDS Word Count value 0x8 ADDRESS I2C Address value 0xC DATA Data Input/Output 0x10 CMD Command Register 0x14 STATUS I2C Controller Status Register 0x18 I2CIDLE I2C bus is idle [0:0] IDLE I2C controller is Idle [1:1] WAITING Controller is Waiting [2:2] STALLED Controller is Stalled [3:3] ARBLOST I2C Arbitration was lost [4:4] NACKADDR I2C Address was not Acknowledged [5:5] NACKDATA I2C Data was not Acknowledged [6:6] RXNEMPTY RX FIFO is Not Empty [8:8] RXFULL RX FIFO is Full [9:9] RXTRIGGER RX FIFO Above Trigger Level [11:11] TXEMPTY TX FIFO is Empty [12:12] TXNFULL TX FIFO is Full [13:13] TXTRIGGER TX FIFO Below Trigger Level [15:15] RAW_SDA I2C Raw SDA value [30:30] RAW_SCL I2C Raw SCL value [31:31] STATE Internal STATE of I2C Master Controller 0x1C read-only TXCOUNT TX Count Register 0x20 read-only RXCOUNT RX Count Register 0x24 read-only IRQ_ENB Interrupt Enable Register 0x28 read-write 0x00000000 I2CIDLE I2C Bus is Idle [0:0] IDLE Controller is Idle [1:1] WAITING Controller is Waiting [2:2] STALLED Controller is Stalled [3:3] ARBLOST I2C Arbitration was lost [4:4] NACKADDR I2C Address was not Acknowledged [5:5] NACKDATA I2C Data was not Acknowledged [6:6] CLKLOTO I2C Clock Low Timeout [7:7] TXOVERFLOW TX FIFO Overflowed [10:10] RXOVERFLOW TX FIFO Overflowed [11:11] TXREADY TX FIFO Ready [12:12] RXREADY RX FIFO Ready [13:13] TXEMPTY TX FIFO Empty [14:14] RXFULL RX FIFO Full [15:15] IRQ_RAW Raw Interrupt Status Register 0x2C read-only IRQ_END Enabled Interrupt Status Register 0x30 read-only IRQ_CLR Clear Interrupt Status Register 0x34 write-only oneToClear RXFIFOIRQTRG Rx FIFO IRQ Trigger Level 0x38 TXFIFOIRQTRG Tx FIFO IRQ Trigger Level 0x3C FIFO_CLR Clear FIFO Register 0x40 write-only RXFIFO Clear Rx FIFO [0:0] TXFIFO Clear Tx FIFO [1:1] TMCONFIG Timing Config Register 0x44 CLKTOLIMIT Clock Low Timeout Limit Register 0x48 S0_CTRL Slave Control Register 0x100 0x00000000 CLKENABLED I2C Enabled [0:0] ENABLED I2C Activated [1:1] ENABLE I2C Active [2:2] TXFEMD TX FIFIO Empty Mode [3:3] RXFFMD RX FIFO Full Mode [4:4] S0_MAXWORDS Slave MaxWords Register 0x104 0x00000000 MAXWORD Max Word Count [10:0] ENABLE Enables the max word count [31:31] S0_ADDRESS Slave I2C Address Value 0x108 0x00000000 A10MODE Enable 10b address mode [15:15] ADDRESS Address value [10:1] RW Read/Write value [0:0] S0_ADDRESSMASK Slave I2C Address Mask value 0x10C 0x00000000 MASK Address mask value [10:1] RWMASK Read/Write mask [0:0] S0_DATA Slave Data Input/Output 0x110 0x00000000 VALUE I2C data value [7:0] S0_LASTADDRESS Slave I2C Last Address value 0x114 read-only 0x00000000 ADDRESS Address value [10:1] DIRECTION Transaction direction 0=master send, 1=master receive [0:0] S0_STATUS Slave I2C Controller Status Register 0x118 read-only 0x00000000 COMPLETED Controller Complted a Transaction [0:0] IDLE Controller is Idle [1:1] WAITING Controller is Waiting [2:2] TXSTALLED Controller is Tx Stalled [3:3] RXSTALLED Controller is Rx Stalled [4:4] ADDRESSMATCH I2C Address Match [5:5] NACKDATA I2C Data was not Acknowledged [6:6] RXDATAFIRST Pending Data is first Byte following Address [7:7] RXNEMPTY RX FIFO is Not Empty [8:8] RXFULL RX FIFO is Full [9:9] RXTRIGGER RX FIFO Above Trigger Level [11:11] TXEMPTY TX FIFO is Empty [12:12] TXNFULL TX FIFO is Full [13:13] TXTRIGGER TX FIFO Below Trigger Level [15:15] RAW_BUSY I2C Raw Busy value [29:29] RAW_SDA I2C Raw SDA value [30:30] RAW_SCL I2C Raw SCL value [31:31] S0_STATE Internal STATE of I2C Slave Controller 0x11C read-only S0_TXCOUNT Slave TX Count Register 0x120 read-only 0x00000000 VALUE Count value [10:0] S0_RXCOUNT Slave RX Count Register 0x124 read-only 0x00000000 VALUE Count value [10:0] S0_IRQ_ENB Slave Interrupt Enable Register 0x128 read-write 0x00000000 COMPLETED Controller Complted a Transaction [0:0] IDLE Controller is Idle [1:1] WAITING Controller is Waiting [2:2] TXSTALLED Controller is Tx Stalled [3:3] RXSTALLED Controller is Rx Stalled [4:4] ADDRESSMATCH I2C Address Match [5:5] NACKDATA I2C Data was not Acknowledged [6:6] RXDATAFIRST Pending Data is first Byte following Address [7:7] I2C_START I2C Start Condition [8:8] I2C_STOP I2C Stop Condition [9:9] TXUNDERFLOW TX FIFO Underflowed [10:10] RXOVERFLOW TX FIFO Overflowed [11:11] TXREADY TX FIFO Ready [12:12] RXREADY RX FIFO Ready [13:13] TXEMPTY TX FIFO Empty [14:14] RXFULL RX FIFO Full [15:15] S0_IRQ_RAW Slave Raw Interrupt Status Register 0x12C read-only S0_IRQ_END Slave Enabled Interrupt Status Register 0x130 read-only S0_IRQ_CLR Slave Clear Interrupt Status Register 0x134 write-only oneToClear S0_RXFIFOIRQTRG Slave Rx FIFO IRQ Trigger Level 0x138 0x00000000 LEVEL Half full level for the Rx FIFO [4:0] S0_TXFIFOIRQTRG Slave Tx FIFO IRQ Trigger Level 0x13C 0x00000008 LEVEL Half full level for the Rx FIFO [4:0] S0_FIFO_CLR Slave Clear FIFO Register 0x140 write-only RXFIFO Clear Rx FIFO [0:0] TXFIFO Clear Tx FIFO [1:1] S0_ADDRESSB Slave I2C Address B Value 0x144 0x00000000 RW Read write value [0:0] ADDRESS Address value [10:1] ADDRESSBEN Enable Address B [15:15] S0_ADDRESSMASKB Slave I2C Address B Mask value 0x148 0x000007FE RWMASK Read write mask [0:0] MASK Address mask value [10:1] PERID Peripheral ID Register 0x3FC read-only 0x021407E9 I2C1 0x40016400 I2C2 0x40016800 CAN0 1.0 CAN Peripheral CAN CAN 0x40014000 0x0 0x400 registers CAN0 72 CAN1 74 CNSTAT_CMB0 Buffer Status / Control Register 0x0 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB0 CAN Frame Timestamp 0x4 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB0 CAN Frame Data Word 3 0x8 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB0 CAN Frame Data Word 2 0xC read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB0 CAN Frame Data Word 1 0x10 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB0 CAN Frame Data Word 0 0x14 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB0 CAN Frame Identifier Word 0 0x18 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB0 CAN Frame Identifier Word 1 0x1C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB1 Buffer Status / Control Register 0x20 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB1 CAN Frame Timestamp 0x24 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB1 CAN Frame Data Word 3 0x28 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB1 CAN Frame Data Word 2 0x2C read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB1 CAN Frame Data Word 2 0x30 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB1 CAN Frame Data Word 0 0x34 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB1 CAN Frame Identifier Word 0 0x38 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB1 CAN Frame Identifier Word 1 0x3C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB2 Buffer Status / Control Register 0x40 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB2 CAN Frame Timestamp 0x44 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB2 CAN Frame Data Word 3 0x48 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB2 CAN Frame Data Word 2 0x4C read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB2 CAN Frame Data Word 2 0x50 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB2 CAN Frame Data Word 0 0x54 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB2 CAN Frame Identifier Word 0 0x58 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB2 CAN Frame Identifier Word 1 0x5C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB3 Buffer Status / Control Register 0x60 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB3 CAN Frame Timestamp 0x64 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB3 CAN Frame Data Word 3 0x68 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB3 CAN Frame Data Word 2 0x6C read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB3 CAN Frame Data Word 2 0x70 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB3 CAN Frame Data Word 0 0x74 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB3 CAN Frame Identifier Word 0 0x78 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB3 CAN Frame Identifier Word 1 0x7C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB4 Buffer Status / Control Register 0x80 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB4 CAN Frame Timestamp 0x84 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB4 CAN Frame Data Word 3 0x88 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB4 CAN Frame Data Word 2 0x8C read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB4 CAN Frame Data Word 2 0x90 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB4 CAN Frame Data Word 0 0x94 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB4 CAN Frame Identifier Word 0 0x98 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB4 CAN Frame Identifier Word 1 0x9C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB5 Buffer Status / Control Register 0xA0 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB5 CAN Frame Timestamp 0xA4 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB5 CAN Frame Data Word 3 0xA8 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB5 CAN Frame Data Word 2 0xAC read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB5 CAN Frame Data Word 2 0xB0 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB5 CAN Frame Data Word 0 0xB4 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB5 CAN Frame Identifier Word 0 0xB8 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB5 CAN Frame Identifier Word 1 0xBC 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB6 Buffer Status / Control Register 0xC0 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB6 CAN Frame Timestamp 0xC4 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB6 CAN Frame Data Word 3 0xC8 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB6 CAN Frame Data Word 2 0xCC read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB6 CAN Frame Data Word 2 0xD0 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB6 CAN Frame Data Word 0 0xD4 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB6 CAN Frame Identifier Word 0 0xD8 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB6 CAN Frame Identifier Word 1 0xDC 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB7 Buffer Status / Control Register 0xE0 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB7 CAN Frame Timestamp 0xE4 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB7 CAN Frame Data Word 3 0xE8 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB7 CAN Frame Data Word 2 0xEC read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB7 CAN Frame Data Word 2 0xF0 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB7 CAN Frame Data Word 0 0xF4 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB7 CAN Frame Identifier Word 0 0xF8 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB7 CAN Frame Identifier Word 1 0xFC 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB8 Buffer Status / Control Register 0x100 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB8 CAN Frame Timestamp 0x104 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB8 CAN Frame Data Word 3 0x108 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB8 CAN Frame Data Word 2 0x10C read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB8 CAN Frame Data Word 2 0x110 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB8 CAN Frame Data Word 0 0x114 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB8 CAN Frame Identifier Word 0 0x118 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB8 CAN Frame Identifier Word 1 0x11C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB9 Buffer Status / Control Register 0x120 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB9 CAN Frame Timestamp 0x124 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB9 CAN Frame Data Word 3 0x128 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB9 CAN Frame Data Word 2 0x12C read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB9 CAN Frame Data Word 2 0x130 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB9 CAN Frame Data Word 0 0x134 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB9 CAN Frame Identifier Word 0 0x138 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB9 CAN Frame Identifier Word 1 0x13C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB10 Buffer Status / Control Register 0x140 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB10 CAN Frame Timestamp 0x144 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB10 CAN Frame Data Word 3 0x148 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB10 CAN Frame Data Word 2 0x14C read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB10 CAN Frame Data Word 2 0x150 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB10 CAN Frame Data Word 0 0x154 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB10 CAN Frame Identifier Word 0 0x158 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB10 CAN Frame Identifier Word 1 0x15C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB11 Buffer Status / Control Register 0x160 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB11 CAN Frame Timestamp 0x164 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB11 CAN Frame Data Word 3 0x168 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB11 CAN Frame Data Word 2 0x16C read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB11 CAN Frame Data Word 2 0x170 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB11 CAN Frame Data Word 0 0x174 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB11 CAN Frame Identifier Word 0 0x178 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB11 CAN Frame Identifier Word 1 0x17C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB12 Buffer Status / Control Register 0x180 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB12 CAN Frame Timestamp 0x184 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB12 CAN Frame Data Word 3 0x188 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB12 CAN Frame Data Word 2 0x18C read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB12 CAN Frame Data Word 2 0x190 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB12 CAN Frame Data Word 0 0x194 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB12 CAN Frame Identifier Word 0 0x198 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB12 CAN Frame Identifier Word 1 0x19C 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB13 Buffer Status / Control Register 0x1A0 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB13 CAN Frame Timestamp 0x1A4 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB13 CAN Frame Data Word 3 0x1A8 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB13 CAN Frame Data Word 2 0x1AC read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB13 CAN Frame Data Word 2 0x1B0 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB13 CAN Frame Data Word 0 0x1B4 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB13 CAN Frame Identifier Word 0 0x1B8 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB13 CAN Frame Identifier Word 1 0x1BC 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_CMB14 Buffer Status / Control Register 0x1C0 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_CMB14 CAN Frame Timestamp 0x1C4 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_CMB14 CAN Frame Data Word 3 0x1C8 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_CMB14 CAN Frame Data Word 2 0x1CC read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_CMB14 CAN Frame Data Word 2 0x1D0 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_CMB14 CAN Frame Data Word 0 0x1D4 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_CMB14 CAN Frame Identifier Word 0 0x1D8 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_CMB14 CAN Frame Identifier Word 1 0x1DC 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CNSTAT_HCMB Buffer Status / Control Register 0x1E0 0x00000000 DLC Data Length Code [15:12] PRI Transmit Priority Code [7:4] ST Buffer Status [3:0] TSTP_HCMB CAN Frame Timestamp 0x1E4 0x00000000 TIMESTAMP Timestamp [15:0] DATA3_HCMB CAN Frame Data Word 3 0x1E8 0x00000000 BYTE7 Data Byte 7 [15:8] BYTE8 Data Byte 8 [7:0] DATA2_HCMB CAN Frame Data Word 2 0x1EC read-write 0x00000000 BYTE5 Data Byte 5 [15:8] BYTE6 Data Byte 6 [7:0] DATA1_HCMB CAN Frame Data Word 2 0x1F0 0x00000000 BYTE3 Data Byte 3 [15:8] BYTE4 Data Byte 4 [7:0] DATA0_HCMB CAN Frame Data Word 0 0x1F4 read-write 0x00000000 BYTE1 Data Byte 1 [15:8] BYTE2 Data Byte 2 [7:0] ID0_HCMB CAN Frame Identifier Word 0 0x1F8 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] ID1_HCMB CAN Frame Identifier Word 1 0x1FC 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] CGCR CAN Global Configuration Register 0x200 0x00000000 EIT Error Interrupt Type [11:11] DIAGEN Diagnostic Enable [10:10] INTERNAL Internal [9:9] LOOPBACK Loopback [8:8] IGNACK Ignore Acknowledge [7:7] LO Listen Only [6:6] DDIR Data Direction [5:5] TSTPEN Time Sync Enable [4:4] BUFFLOCK Buffer Lock [3:3] CTX RW,Control Transmit [2:2] CRX RW,Control Receive [1:1] CANEN CAN Enable [0:0] CTIM CAN Timing Register 0x204 0x00000000 PSC Prescaler Configuration [15:9] SJW Synchronization Jump Width [8:7] TSEG1 Time Segment 1 [6:3] TSEG2 Time Segment 2 [2:0] GMSKX CAN Global Mask Extension 0x208 0x00000000 GM GM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard [15:1] XRTR Extended Remote transmission Request Bit [0:0] GMSKB CAN Global Mask Base 0x20C 0x00000000 GM1 GM[28:18] - ID[10:0] in standard, ID[28:18] in extended [15:5] RTR Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended [4:4] IDE Identifier Extension Bit [3:3] GM0 GM[17:15] - Unused in standard, ID[17:15] in extended [2:0] BMSKX CAN Basic Mask Extension 0x210 0x00000000 BM BM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard [15:1] XRTR Extended Remote transmission Request Bit [0:0] BMSKB CAN Basic Mask Base 0x214 0x00000000 BM1 BM[28:18] - ID[10:0] in standard, ID[28:18] in extended [15:5] RTR Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended [4:4] IDE Identifier Extension Bit [3:3] BM0 BM[17:15] - Unused in standard, ID[17:15] in extended [2:0] CIEN CAN Interrupt Enable Register 0x218 0x00000000 EIEN Error Interrupt Enable [15:15] IEN Buffer Interrupt Enable[14:0] [14:0] CIPND CAN Interrupt Pending Register 0x21C 0x00000000 EIPND Error Interrupt Pending [15:15] IPND Buffer Interrupt Pending[14:0] [14:0] CICLR CAN Interrupt Clear Register 0x220 0x00000000 EICLR Error Interrupt Clear [15:15] ICLR Buffer Interrupt Clear[14:0] [14:0] CICEN CAN Interrupt Code Enable Register 0x224 0x00000000 EICEN Error Interrupt Code Enable [15:15] ICEN Buffer Interrupt Code Enable[14:0] [14:0] CSTPND CAN Status Pending Register 0x228 0x00000000 NS CAN Node Status [7:5] IRQ Interrupt Request portion of Interrupt Code [4:4] IST Interrupt Source portion of Interrupt Code [3:0] CANEC CAN Error Counter Register 0x22C 0x00000000 REC Receive Error Counter [15:8] TEC Transmit Error Counter [7:0] CEDIAG CAN Error Diagnostic Register 0x230 0x00000000 DRIVE Drive [14:14] MON Monitor [13:13] CRC CRC [12:12] STUFF Stuff Error [11:11] TXE Transmit Error [10:10] EBID Error Bit Identifier [9:4] EFID Error Field Identifier [3:0] CTMR CAN Timer Register 0x234 0x00000000 CTMR Time Stamp Counter [15:0] read-only CAN1 0x40014400 ADC 1.0 Analog to Digital Converter Peripheral ADC ADC 0x40022000 0x0 0x1000 registers ADC 44 CTRL Control Register 0x0 0x00000000 CONV_CNT Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions) [23:20] MANUAL_TRIG Starts analog acquisition [19:19] EXT_TRIG_EN Allows the external trigger to start analog acquisition [18:18] SWEEP_EN ADC data acquisition for all enabled channel [17:17] CHAN_TAG_EN Enables the channel tag to be saved with the ADC data [16:16] CHAN_EN Enables the channel for data collection [15:0] FIFO_DATA FIFO data 0x4 read-only 0x00000000 CHAN_TAG If enabled, this will include the number of the channel corresponding to the measurement [15:12] read-only ADC_DATA ADC acquisition data from the FIFO [11:0] STATUS Status 0x8 read-only 0x00000000 ADC_BUSY Indicates an ADC data acquisition is in process [7:7] FIFO_ENTRY_CNT Indicates the number of entries in the FIFO [5:0] IRQ_ENB Interrupt Enable 0xC 0x00000000 FIFO_DEPTH_TRIG Enables the interrupt for the FIFO entry count meets or exceeds the trigger level [6:6] TRIG_ERROR Enables the interrupt for a trigger error [5:5] ADC_DONE Enables the interrupt for an ADC data acquisition completion [4:4] FIFO_UFLOW Enables the interrupt for a FIFO underflow [3:3] FIFO_OFLOW Enables the interrupt for a FIFO overflow [2:2] FIFO_FULL Enables the interrupt for FIFO full [1:1] FIFO_EMPTY Enables the interrupt for FIFO empty [0:0] IRQ_RAW Raw Interrupt Status 0x10 read-only 0x00000001 FIFO_DEPTH_TRIG Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level [6:6] TRIG_ERROR Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion [5:5] ADC_DONE Indicates that a ADC conversion is done [4:4] FIFO_UFLOW Indicates data was unavailable when a new trigger for ADC update is received [3:3] FIFO_OFLOW Indicates a FIFO overflow occurred (FIFO was full when new data was written) [2:2] FIFO_FULL Indicates the FIFO is full [1:1] FIFO_EMPTY Indicates the FIFO is empty [0:0] IRQ_END Enabled Interrupt Status 0x14 read-only 0x00000000 FIFO_DEPTH_TRIG Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level [6:6] TRIG_ERROR Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled [5:5] ADC_DONE Indicates that a ADC conversion is done and the interrupt is enabled [4:4] FIFO_UFLOW Indicates a FIFO underflow occurred and the interrupt is enabled [3:3] FIFO_OFLOW Indicates a FIFO overflow occurred and the interrupt is enabled [2:2] FIFO_FULL Indicates the FIFO is full and the interrupt is enabled [1:1] FIFO_EMPTY Indicates the FIFO is empty and the interrupt is enabled [0:0] IRQ_CLR Clear Interrupt 0x18 write-only 0x00000000 TRIG_ERROR Clears the trigger error interrupt status. Always reads 0 [3:3] ADC_DONE Clears the ADC done interrupt status. Always reads 0 [2:2] FIFO_UFLOW Clears the FIFO underflow interrupt status. Always reads 0 [1:1] FIFO_OFLOW Clears the FIFO overflow interrupt status. Always reads 0 [0:0] RXFIFOIRQTRG Receive FIFO Interrupt Trigger Value 0x1C 0x00000010 LEVEL Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt [4:0] FIFO_CLR FIFO Clear 0x20 0x00000000 FIFO_CLR Clears the ADC FIFO. Always reads 0 [0:0] write-only PERID Peripheral ID Register 0xFFC read-only 0x001907E9 DAC0 1.0 Digital to Analog Converter Peripheral DAC DAC 0x40023000 0x0 0x800 registers DAC0 40 DAC1 41 CTRL0 Control Register 0 0x0 0x00000000 MAN_TRIG_EN Enables manual trigger [11:11] EXT_TRIG_EN Enables external trigger [10:10] CTRL1 Control Register 1 0x4 0x00000000 DAC_EN Enables the DAC analog block [8:8] DAC_SETTLING Sets the the amount of time in microseconds the control FSM waits for the DAC settling time [7:5] FIFO_DATA FIFO data 0x8 read-write 0x00000000 DATA Data for FIFO write [11:0] write-only STATUS Status 0xC read-only 0x00000000 DAC_BUSY Indicates a DAC data acquisition is in process [7:7] FIFO_ENTRY_CNT Indicates the number of entries in the FIFO [5:0] IRQ_ENB Interrupt Enable 0x10 0x00000000 FIFO_DEPTH_TRIG Enables the interrupt for the FIFO entry count is less than or equal to the trigger level [6:6] TRIG_ERROR Enables the interrupt for a trigger error [5:5] DAC_DONE Enables the interrupt for a DAC data acquisition completion [4:4] FIFO_UFLOW Enables the interrupt for a FIFO underflow [3:3] FIFO_OFLOW Enables the interrupt for a FIFO overflow [2:2] FIFO_FULL Enables the interrupt for FIFO full [1:1] FIFO_EMPTY Enables the interrupt for FIFO empty [0:0] IRQ_RAW Raw Interrupt Status 0x14 read-only 0x00000041 FIFO_DEPTH_TRIG Indicates the FIFO entry count is less than or equal to the trigger level [6:6] TRIG_ERROR Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion [5:5] DAC_DONE Indicates that a DAC conversion is done [4:4] FIFO_UFLOW Indicates data was unavailable when a new trigger for DAC update is received [3:3] FIFO_OFLOW Indicates a FIFO overflow occurred (FIFO was full when new data was written) [2:2] FIFO_FULL Indicates the FIFO is full [1:1] FIFO_EMPTY Indicates the FIFO is empty [0:0] IRQ_END Enabled Interrupt Status 0x18 read-only 0x00000000 FIFO_DEPTH_TRIG Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled [6:6] TRIG_ERROR Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled [5:5] DAC_DONE Indicates that a DAC conversion is done and the interrupt is enabled [4:4] FIFO_UFLOW Indicates a FIFO underflow occurred and the interrupt is enabled [3:3] FIFO_OFLOW Indicates a FIFO overflow occurred and the interrupt is enabled [2:2] FIFO_FULL Indicates the FIFO is full and the interrupt is enabled [1:1] FIFO_EMPTY Indicates the FIFO is empty and the interrupt is enabled [0:0] IRQ_CLR Clear Interrupt 0x1C write-only 0x00000000 TRIG_ERROR Clears the trigger error interrupt status. Always reads 0 [3:3] DAC_DONE Clears the DAC done interrupt status. Always reads 0 [2:2] FIFO_UFLOW Clears the FIFO underflow interrupt status. Always reads 0 [1:1] FIFO_OFLOW Clears the FIFO overflow interrupt status. Always reads 0 [0:0] TXFIFOIRQTRG Receive FIFO Interrupt Trigger Value 0x20 0x00000010 LEVEL Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt [4:0] FIFO_CLR FIFO Clear 0x24 0x00000000 FIFO_CLR Clears the DAC FIFO. Always reads 0 [0:0] write-only PERID Peripheral ID Register 0x7FC read-only 0x002007E9 DAC1 0x40023800 SPW 1.0 SpaceWire Peripheral SPW SPW 0x40003000 0x0 0x400 registers SpW 38 CTRL Control Register 0x0 0xA2010004 RA Reads as 1 if the RMAP command handler is available [31:31] read-only RX Reads as 1 if unaligned writes are available for the receiver [30:30] read-only RC Reads as 1 if RMAP CRC is enabled in the core [29:29] read-only NCH Number of DMA Channels minus one [28:27] read-only PO The number of available SpaceWire ports minus one [26:26] read-only CC CCSDS/CCITT CRC-16 [25:25] read-only ID Interrupt distribution available [24:24] read-only LE Loop-back Enable [22:22] read-write PS Selects the active port when the no port force bit is zero [21:21] read-write NP Disable port force [20:20] read-write PNPA SpW Plug-and-Play Available [19:18] read-only RD If set only one RMAP buffer is used [17:17] read-write RE Enable RMAP command handler [16:16] read-write PE SpW Plug-and-Play Enable [15:15] read-write TL Transmitter Enable Lock Control [13:13] read-write TF Time-code Flag Filter [12:12] read-write TR Enable time-code receptions [11:11] TT Enable time-code transmissions [10:10] LI Generate interrupt when link error occurs [9:9] TQ Generate interrupt when a valid time-code is received [8:8] RS Make complete reset of the SpaceWire node. Self-clearing [6:6] PM Enable Promiscuous mode [5:5] TI The host can generate a tick by writing a one to this field [4:4] IE If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs [3:3] AS Automatically start the link when a NULL has been received [2:2] LS Start the link [1:1] LD Disable the SpaceWire CODEC [0:0] STS Status/Interrupt Source Register 0x4 0x06400000 NRXD Number of Receive Descriptors [27:26] NTXD Number of Transmit Descriptors [25:24] LS Link State [23:21] AP Active port [9:9] EE Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet [8:8] IA Packet is received with an invalid destination address field [7:7] WE A synchronization problem has occurred when receiving NChars [6:6] PE Parity error has occurred [4:4] DE Disconnection error has occurred [3:3] ER Escape error has occurred [2:2] CE Credit has occurred [1:1] TO A new time count value was received [0:0] DEFADDR Node Address Register 0x8 read-write 0x000000FE DEFMASK 8-bit default mask used for node identification on the SpaceWire network [15:8] DEFADDR 8-bit node address used for node identification on the SpaceWire network [7:0] CLKDIV Clock Divisor Register 0xC read-write 0x00000909 CLKDIVSTART 8-bit Clock divisor value used for the clock-divider during startup [15:8] CLKDIVRUN 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state [7:0] DKEY Destination Key 0x10 0x00000000 DESTKEY RMAP destination key [7:0] TC Time Code Register 0x14 read-write 0x00000000 TIRQ_END The current value of the time control flags [7:6] TIMECNT The current value of the system time counter [5:0] TDR Timer and Disconnect Register 0x18 read-only 0x00000000 DISCONNECT Used to generate the 850 ns disconnect time period [21:12] TIMER64 Used to generate the 6.4 and 12.8 us time periods [11:0] DMACTRL0 DMA Control Register 0x20 read-write 0x00000000 INTNUM Interrupt number used for this channel [31:26] EP EEP Termination [23:23] TR Truncated [22:22] IE Interrupt code transmit enable on EEP [21:21] IT Interrupt code transmit enable on truncation [20:20] RP Receive Packet IRQ [19:19] TP Transmit Packet IRQ [18:18] TL Transmit Enable Lock [17:17] LE Disable transmitter when a link error occurs [16:16] SP Strip PID [15:15] SA Strip Address [14:14] EN Enable Address [13:13] NS If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated [12:12] RD Indicates to the GRSPW that there are enabled descriptors in the descriptor table [11:11] RX Reception to the DMA channel is currently active [10:10] read-only AT Abort the currently transmitting packet and disable transmissions [9:9] read-only RA An error response was detected on the AHB bus - DMA receive [8:8] TA An error response was detected on the AHB bus - DMA transmit [7:7] PR Set each time a packet has been received [6:6] PS Set each time a packet has been sent [5:5] AI An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus [4:4] RI An interrupt will be generated each time a packet has been received [3:3] TI An interrupt will be generated each time a packet is transmitted [2:2] RE Packets are allowed to be received to this channel [1:1] TE Write a one to this bit each time new descriptors are activated in the table [0:0] DMAMAXLEN0 DMA RX Maximum Length Register 0x24 read-write 0x00000000 RXMAXLEN Receiver packet maximum length in bytes [24:2] DMATXDESC0 DMA Transmitter Descriptor Table Address Register 0x28 read-write 0x00000000 DESCBASEADDR Sets the base address of the descriptor table [31:10] DESCSEL Offset into the descriptor table [9:4] DMARXDESC0 DMA Receiver Table Destination Register 0x2C read-write 0x00000000 DESCBASEADDR Sets the base address of the descriptor table [31:10] DESCSEL Offset into the descriptor table [9:3] DMAADDR0 DMA Receiver Table Address Register 0x30 read-write 0x00000000 MASK Mask [15:8] ADDR Address [7:0] IRQ_ROUTER 1.0 Interrupt Router Peripheral IRQ 0x40002000 0x0 0x1000 registers U0 0 U1 1 U2 2 U3 3 U4 4 U5 5 U6 6 U7 7 U8 8 U9 9 U10 10 U11 11 U12 12 U13 13 U14 14 U15 15 U37 37 U39 39 U73 73 U75 75 FPU 194 TXEV 195 DMASEL0 Interrupt select for DMA channel 0 0x0 read-write 0x0000007F DMASEL DMA trigger source selection value [6:0] DMASEL1 Interrupt select for DMA channel 1 0x4 read-write 0x0000007F DMASEL DMA trigger source selection value [6:0] DMASEL2 Interrupt select for DMA channel 2 0x8 read-write 0x0000007F DMASEL DMA trigger source selection value [6:0] DMASEL3 Interrupt select for DMA channel 3 0xC read-write 0x0000007F DMASEL DMA trigger source selection value [6:0] DMATTSEL Trigger select for the DMA channels 0x10 read-write 0x00000000 DMATTSEL DMA trigger type selection value [3:0] ADCSEL Interrupt select for ADC 0x14 read-write 0x0000001F ADCSEL ADC trigger source selection value [4:0] DACSEL0 Interrupt select for DAC0 0x18 read-write 0x0000001F DACSEL DAC trigger source selection value [4:0] DACSEL1 Interrupt select for DAC1 0x1C read-write 0x0000001F DACSEL DAC trigger source selection value [4:0] IRQ_OUT0 DEBUG IRQ_OUT[31:0] 0x20 read-only 0x00000000 IRQ_OUT0 IRQ_OUT[31:0] [31:0] IRQ_OUT1 DEBUG IRQ_OUT[63:32] 0x24 read-only 0x00000000 IRQ_OUT1 IRQ_OUT[63:32] [31:0] IRQ_OUT2 DEBUG IRQ_OUT[95:64] 0x28 read-only 0x00000000 IRQ_OUT2 IRQ_OUT[95:64] [31:0] IRQ_OUT3 DEBUG IRQ_OUT[127:96] 0x2C read-only 0x00000000 IRQ_OUT3 IRQ_OUT[127:96] [31:0] IRQ_OUT4 DEBUG IRQ_OUT[159:128] 0x30 read-only 0x00000000 IRQ_OUT4 IRQ_OUT[159:128] [31:0] IRQ_OUT5 DEBUG IRQ_OUT[179:160] 0x34 read-only 0x00000000 IRQ_OUT5 IRQ_OUT[179:160] [19:0] PERID Peripheral ID Register 0xFFC read-only 0x028107E9 WATCH_DOG 1.0 Watchdog Block Peripheral WDOG 0x40021000 0x0 0x1000 registers WATCHDOG 47 WDOGLOAD Counter Start Value 0x0 read-write 0xFFFFFFFF CNT Count to load [31:0] WDOGVALUE Down Counter Value 0x4 read-only 0xFFFFFFFF CNT Actual Count [31:0] WDOGCONTROL Enable for block reset and interrupt 0x8 read-write 0x00000000 RESEN Enable watchdog reset output [1:1] INTEN Enable watchdog interrupt [0:0] WDOGINTCLR A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register 0xC read-write 0x00000000 CLEAR Write any value to clear interrupt [31:0] WDOGRIS Raw interrupt status 0x10 read-only 0x00000000 INTERRUPT Interrupt Status [0:0] WDOGMIS Interrupt status 0x14 read-only 0x00000000 INTERRUPT Masked Interrupt Status [0:0] WDOGLOCK Lock 0xC0 read-write 0x00000000 REG_WR_EN Register write enable status [31:0] WDOGITCR Integration test control 0xF00 read-write 0x00000000 TEST_MODE_EN Enable test mode of WDOGINT and WDOGRES [0:0] WDOGITOP Integration test output set 0xF04 read-write 0x00000000 WDOGINT Set output value [1:1] WDOGRES Set output value [0:0] WDOGPERIPHID0 Peripheral ID 0xFE0 read-only 0x00000024 PERIPHID Peripheral ID [7:0] WDOGPERIPHID1 Peripheral ID 0xFE4 read-only 0x000000B8 PERIPHID Peripheral ID [7:0] WDOGPERIPHID2 Peripheral ID 0xFE8 read-only 0x0000001B PERIPHID Peripheral ID [7:0] WDOGPERIPHID3 Peripheral ID 0xFEC read-only 0x00000000 PERIPHID Peripheral ID [7:0] WDOGPCELLID0 PrimeCell ID 0xFF0 read-only 0x0000000D PCELLID Prime Cell ID [7:0] WDOGPCELLID1 PrimeCell ID 0xFF4 read-only 0x000000F0 PCELLID Prime Cell ID [7:0] WDOGPCELLID2 PrimeCell ID 0xFF8 read-only 0x00000005 PCELLID Prime Cell ID [7:0] WDOGPCELLID3 PrimeCell ID 0xFFC read-only 0x000000B1 PCELLID Prime Cell ID [7:0] TRNG 1.0 True Random Number Generator TRNG 0x40027000 0x0 0x400 registers TRNG 42 IMR Interrupt Mask Register 0x100 read-write 0x0000000F VN_ERR_INT_MASK Mask the Von Neumann error [3:3] CRNGT_ERR_INT_MASK Mask the CRNGT error [2:2] AUTOCORR_ERR_INT_MASK Mask the Autocorrelation error [1:1] EHR_VALID_INT_MASK Mask when the TRNG has collected 192 bits [0:0] ISR Interrupt Status Register 0x104 read-only 0x00000000 VN_ERR Indicates a Von Neumann error [3:3] CRNGT_ERR Indicates a Continuous Random Number Generation Testing (CRNGT) error [2:2] AUTOCORR_ERR Indicates that the Autocorrelation test failed four times in a row [1:1] EHR_VALID 192 bits have been collected in the TRNG [0:0] ICR Interrupt Clear Register 0x108 read-write 0x00000000 VN_ERR Clears a Von Neumann error [3:3] CRNGT_ERR Clear a Continuous Random Number Generation Testing (CRNGT) error [2:2] AUTOCORR_ERR Software cannot clear this bit. Only a TRNG reset can clear this bit [1:1] EHR_VALID Set to 1 after the EHR_DATA[0,1,2,3,4,5] registers have been read [0:0] CONFIG Configuration Register 0x10C read-write 0x00000000 RND_SRC_SEL Selects the number of inverters (out of four possible selections) in the ring oscillator [1:0] VALID Valid Register 0x110 read-only 0x00000000 EHR_VALID Indicates that the collection of bits in the TRNG is complete [0:0] EHR_DATA0 Entropy Holding Register Data Register 0x114 read-only 0x00000000 EHR_DATA 32 Bits of Entropy Holding Register [31:0] EHR_DATA1 Entropy Holding Register Data Register 0x118 EHR_DATA2 Entropy Holding Register Data Register 0x11C EHR_DATA3 Entropy Holding Register Data Register 0x120 EHR_DATA4 Entropy Holding Register Data Register 0x124 EHR_DATA5 Entropy Holding Register Data Register 0x128 RND_SOURCE_ENABLE Random Source Enable Register 0x12C read-write 0x00000000 RND_SRC_EN The entropy source, ring oscillator, is enabled [0:0] SAMPLE_CNT1 Section TBD 0x130 read-write 0x0000FFFF SAMPLE_CNTR1 Sets the number of clk cycles between two consecutive ring oscillator samples [31:0] AUTOCORR_STATISTIC Auto-correlator Statistic Register 0x134 read-write 0x00000000 AUTOCORR_FAILS Count each time an autocorrelation test fails [21:14] AUTOCORR_TRYS Count each time an autocorrelation test starts [13:0] DEBUG_CONTROL Section TBD 0x138 read-write 0x00000000 AUTO_CORRELATE_BYPASS The autocorrelation test in the TRNG module is bypassed [3:3] CRNGT_BYPASS The CRNGT test in the TRNG is bypassed [2:2] VNC_PYPASS The Von Neumann balancer is bypassed [1:1] SW_RESET Reset Register 0x140 read-write 0x00000000 SW_RESET Writing 1 to this register causes an internal TRNG reset [0:0] BUSY Busy Register 0x1B8 read-only 0x00000000 BUSY Reflects the status of the rng_busy signal [0:0] RST_BITS_COUNTER Reset Bits Counter Register 0x1BC read-write 0x00000000 RST_BITS_COUNTER Writing any value to this bit resets the bits counter and TRNG valid registers [0:0] BIST_CNTR0 BIST Counter Register 0x1E0 read-only 0x00000000 ROSC_CNTR_VAL Returns the results of the TRNG BIST counter [21:0] BIST_CNTR1 BIST Counter Register 0x1E4 BIST_CNTR2 BIST Counter Register 0x1E8 ETH 1.1 Ethernet Block ETH 0x40004000 0x0 0x2000 registers Ethernet 36 MAC_CONFIG Operation mode register for the MAC 0x0 read-write 0x00000000 WD Watchdog disable [23:23] JD Jabber Disable [22:22] BE Frame Burst Enable [21:21] JE Jumbo Frame Enable [20:20] IFG Inter-Frame Gap [19:17] DCRS Disable Carrier Sense During Transmission [16:16] PS Port Select [15:15] FES Speed [14:14] DRO Disable Receive Own [13:13] LM Loopback Mode [12:12] DM Duplex Mode [11:11] IPC Checksum Offload [10:10] DR Disable Retry [9:9] ACS Automatic Pad, or CRC Stripping [7:7] BL Back-Off-Limit [6:5] DC Deferral Check [4:4] TE Transmitter Enable [3:3] RE Receiver Enable [2:2] PRELEN Preamble Length for Transmit frames [1:0] MAC_FRAME_FLTR Contains the frame filtering controls 0x4 read-write 0x00000000 RA Receive All [31:31] DNTU Drop non TCP/UDP over IP Frames [21:21] VFTE VLAN Tag Filter Enable [16:16] HDF Hash or Perfect Filter [10:10] SAF Source Address Filter Enable [9:9] SAIF SA Inverse Filtering [8:8] PCF Pass Control Frames [7:6] DBF Disable Broadcast Frames [5:5] PM Pass All Multicast [4:4] DAIF DA Inverse Filtering [3:3] HMC Hash Multicast [2:2] HUC Hash Unicast [1:1] PR Promiscuous Mode [0:0] MAC_GMII_ADDR Controls the management cycles to an external PHY 0x10 read-write 0x00000000 PA Physical Layer Address [15:11] GR GMII Register [10:6] CR CSR Clock Range [5:2] GW GMII Write/Read [1:1] GB GMII Busy [0:0] MAC_GMII_DATA Contains the data to be written to or read from the PHY register 0x14 read-write 0x00000000 GD GMII Data [15:0] MAC_FLOW_CTRL Controls the generation of control frames 0x18 read-write 0x00000000 PT Pause time [31:16] DZPQ Disable Zero-Quanta Pause [7:7] PLT Pause Low Threshold [5:4] UP Unicast Pause Frame Detect [3:3] RFE Receive Flow Control Enable [2:2] TFE Transmit Flow Control Enable [1:1] FCB_BPA Flow Control Busy or Backpressure Activate [0:0] MAC_VLAN_TAG Identifies IEEE 802.1Q VLAN type frames 0x1C read-write 0x00000000 ESVL Enable S-VLAN [18:18] VTIM VLAN Tag Inverse Match Enable [17:17] ETV Enable 12-Bit VLAN Tag Comparison [16:16] VL VLAN Tag identifier for Receive Frames [15:0] MAC_DEBUG Gives the status of the various internal blocks for debugging 0x24 read-only 0x00000000 TXSTSFSTS MTL TxStatus FIFO Full Status [25:25] TXFSTS MTL Tx FIFO Not Empty Status [24:24] TWCSTS MTL Tx FIFO Write Controller Status [22:22] TRCSTS MTL Tx FIFO Read Controller Status [21:20] TXPAUSED MAC Transmitter in Pause [19:19] TFCSTS PAC Transmit Frame Controller Status [18:17] TPESTS MAC GMII or MII Transmit Protocol Engine Status [16:16] RXFSTS MTL RxFIFO Fill-Level Status [9:8] RRCSTS MTL RxFIFO Read Controller State [6:5] RWCSTS MTL Rx FIFO Write Controller Active Status [4:4] RFCFCSTS MAC Receive Frame FIFO Controller Status [2:1] RPESTS MAC GMII or MII Receive Protocol Engine Status [0:0] MAC_INTR_STAT Contains the interrupt status 0x38 read-only 0x00000000 TSIS Timestamp Interrupt Status [9:9] MMCRXIPIS MMC Receive Checksum Offload Interrupt Status [7:7] MMCTXIS MMC Transmit Interrupt Status [6:6] MMCRXIS MMC Receive Interrupt Status [5:5] MMCIS MMC Interrupt Status [4:4] MAC_INTR_MASK Contains the masks for generating interrupt 0x3C read-write 0x00000000 TSIM Timestamp Interrupt Mask [9:9] MAC_ADDR_H Contains the high 16-bits of the first MAC Address 0x40 read-write 0x8000FFFF AE Address Enable, This bit is always set to 1 [31:31] read-only ADDRHI MAC Address0[47:32] [15:0] read-only MAC_ADDR_L Contains the Low 32-bits of the first MAC Address 0x44 read-write 0xFFFFFFFF ADDRLO MAC Address0[31:0] [31:0] read-only MAC_WDOG_TO Controls the watchdog time-out for received frames 0xDC read-write 0x00000000 PWE Programmable Watchdog Enable [16:16] WTO Watchdog Timeout [13:0] MMC_CNTRL MMC Control Register 0x100 read-write 0x00000000 UCDBC Update MMC Counters for Dropped Broadcast Frames [8:8] CNTPRSTLVL Full-Half Preset [5:5] CNTPRST Counters Preset [4:4] CNTFREEZ MMC Counter Freeze [3:3] RSTONRD Reset on Read [2:2] CNTSTOPRO Counter Stop Rollover [1:1] CNTRST Counters Reset [0:0] MMC_INTR_RX MMC Receive Interrupt Register 0x104 read-write 0x00000000 RXCTRLFIS MMC Receive Control Frame Counter Interrupt Status [25:25] RXRCVERRFIS MMC Receive Error Frame Counter Interrupt Status [24:24] RXWDOGFIS MMC Receive Watchdog Error Frame Counter Interrupt Status [23:23] RXVLANGBFIS MMC Receive VLAN Good Bad Frame Counter Interrupt Status [22:22] RXFOVFIS MMC Receive FIFO Overflow Frame Counter Interrupt Status [21:21] RXPAUSFIS MMC Receive Pause Frame Counter Interrupt Status [20:20] RXORANGEFIS MMC Receive Out Of Range Error Frame Counter Interrupt Status. [19:19] RXLENERFIS MMC Receive Length Error Frame Counter Interrupt Status [18:18] RXUCGFIS MMC Receive Unicast Good Frame Counter Interrupt Status [17:17] RX1024TMAXOCTGBFIS MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. [16:16] RX512T1023OCTGBFIS MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status [15:15] RX256T511OCTGBFIS MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status [14:14] RX128T255OCTGBFIS MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status [13:13] RX65T127OCTGBFIS MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status [12:12] RX64OCTGBFIS MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status [11:11] RXOSIZEGFIS MMC Receive Oversize Good Frame Counter Interrupt Status [10:10] RXUSIZEGFIS MMC Receive Undersize Good Frame Counter Interrupt Status [9:9] RXJABERFIS MMC Receive Jabber Error Frame Counter Interrupt Status [8:8] RXRUNTFIS MMC Receive Runt Frame Counter Interrupt Status [7:7] RXALGNERFIS MMC Receive Alignment Error Frame Counter Interrupt Status [6:6] RXCRCERFIS MMC Receive CRC Error Frame Counter Interrupt Status [5:5] RXMCGFIS MMC Receive Multicast Good Frame Counter Interrupt Status [4:4] RXBCGFIS MMC Receive Broadcast Good Frame Counter Interrupt Status [3:3] RXGOCTIS MMC Receive Good Octet Counter Interrupt Status [2:2] RXGBOCTIS MMC Receive Good Bad Octet Counter Interrupt Status [1:1] RXGBFRMIS MMC Receive Good Bad Frame Counter Interrupt Status [0:0] MMC_INTR_TX MMC Transmit Interrupt Register 0x108 read-write 0x00000000 TXOSIZEGFIS MMC Transmit Oversize Good Frame Counter Interrupt Status [25:25] TXVLANGFIS MMC Transmit VLAN Good Frame Counter Interrupt Status [24:24] TXPAUSFIS MMC Transmit Pause Frame Counter Interrupt Status [23:23] TXEXDEFFIS MMC Transmit Excessive Deferral Frame Counter Interrupt Status [22:22] TXGFRMIS MMC Transmit Good Frame Counter Interrupt Status [21:21] TXGOCTIS MMC Transmit Good Octet Counter Interrupt Status [20:20] TXCARERFIS MMC Transmit Carrier Error Frame Counter Interrupt Status [19:19] TXEXCOLFIS MMC Transmit Excessive Collision Frame Counter Interrupt Status [18:18] TXLATCOLFIS MMC Transmit Late Collision Frame Counter Interrupt Status [17:17] TXDEFFIS MMC Transmit Deferred Frame Counter Interrupt Status [16:16] TXMCOLGFIS MMC Transmit Multiple Collision Good Frame Counter Interrupt Status [15:15] TXSCOLGFIS MMC Transmit Single Collision Good Frame Counter Interrupt Status [14:14] TXUFLOWERFIS MMC Transmit Underflow Error Frame Counter Interrupt Status [13:13] TXBCGBFIS MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status [12:12] TXMCGBFIS MMC Transmit Multicast Good Bad Frame Counter Interrupt Status [11:11] TXUCGBFIS MMC Transmit Unicast Good Bad Frame Counter Interrupt Status [10:10] TX1024TMAXOCTGBFIS MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter [9:9] TX512T1023OCTGBFIS MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status [8:8] TX256T511OCTGBFIS MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status [7:7] TX128T255OCTGBFIS MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status [6:6] TX65T127OCTGBFIS MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status [5:5] TX64OCTGBFIS MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status [4:4] TXMCGFIS MMC Transmit Multicast Good Frame Counter Interrupt Status [3:3] TXBCGFIS MMC Transmit Broadcast Good Frame Counter Interrupt Status [2:2] TXGBFRMIS MMC Transmit Good Bad Frame Counter Interrupt Status [1:1] TXGBOCTIS MMC Transmit Good Bad Octet Counter Interrupt Status [0:0] MMC_INTR_MASK_RX MMC Receive Interrupt Mask Register 0x10C read-write 0x00000000 RXCTRLFIM MMC Receive Control Frame Counter Interrupt Mask [25:25] RXRCVERRFIM MMC Receive Error Frame Counter Interrupt Mask [24:24] RXWDOGFIM MMC Receive Watchdog Error Frame Counter Interrupt Mask [23:23] RXVLANGBFIM MMC Receive VLAN Good Bad Frame Counter Interrupt Mask [22:22] RXFOVFIM MMC Receive FIFO Overflow Frame Counter Interrupt Mask [21:21] RXPAUSFIM MMC Receive Pause Frame Counter Interrupt Mask [20:20] RXORANGEFIM MMC Receive Out Of Range Error Frame Counter Interrupt Mask [19:19] RXLENERFIM MMC Receive Length Error Frame Counter Interrupt Mask [18:18] RXUCGFIM MMC Receive Unicast Good Frame Counter Interrupt Mask [17:17] RX1024TMAXOCTGBFIM MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. [16:16] RX512T1023OCTGBFIM MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask [15:15] RX256T511OCTGBFIM MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask [14:14] RX128T255OCTGBFIM MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask [13:13] RX65T127OCTGBFIM MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask [12:12] RX64OCTGBFIM MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask [11:11] RXOSIZEGFIM MMC Receive Oversize Good Frame Counter Interrupt Mask [10:10] RXUSIZEGFIM MMC Receive Undersize Good Frame Counter Interrupt Mask [9:9] RXJABERFIM MMC Receive Jabber Error Frame Counter Interrupt Mask [8:8] RXRUNTFIM MMC Receive Runt Frame Counter Interrupt Mask [7:7] RXALGNERFIM MMC Receive Alignment Error Frame Counter Interrupt Mask [6:6] RXCRCERFIM MMC Receive CRC Error Frame Counter Interrupt Mask [5:5] RXMCGFIM MMC Receive Multicast Good Frame Counter Interrupt Mask [4:4] RXBCGFIM MMC Receive Broadcast Good Frame Counter Interrupt Mask [3:3] RXGOCTIM MMC Receive Good Octet Counter Interrupt Mask [2:2] RXGBOCTIM MMC Receive Good Bad Octet Counter Interrupt Mask. [1:1] RXGBFRMIM MMC Receive Good Bad Frame Counter Interrupt Mask [0:0] MMC_INTR_MASK_TX MMC Transmit Interrupt Mask Register 0x110 read-write 0x00000000 TXOSIZEGFIM MMC Transmit Oversize Good Frame Counter Interrupt Mask [25:25] TXVLANGFIM MMC Transmit VLAN Good Frame Counter Interrupt Mask [24:24] TXPAUSFIM MMC Transmit Pause Frame Counter Interrupt Mask [23:23] TXEXDEFFIM MMC Transmit Excessive Deferral Frame Counter Interrupt Mask [22:22] TXGFRMIM MMC Transmit Good Frame Counter Interrupt Mask [21:21] TXGOCTIM MMC Transmit Good Octet Counter Interrupt Mask [20:20] TXCARERFIM MMC Transmit Carrier Error Frame Counter Interrupt Mask [19:19] TXEXCOLFIM MMC Transmit Excessive Collision Frame Counter Interrupt Mask [18:18] TXLATCOLFIM MMC Transmit Late Collision Frame Counter Interrupt Mask [17:17] TXDEFFIM MMC Transmit Deferred Frame Counter Interrupt Mask [16:16] TXMCOLGFIM MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask [15:15] TXSCOLGFIM MMC Transmit Single Collision Good Frame Counter Interrupt Mask [14:14] TXUFLOWERFIM MMC Transmit Underflow Error Frame Counter Interrupt Mask [13:13] TXBCGBFIM MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask [12:12] TXMCGBFIM MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask [11:11] TXUCGBFIM MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask [10:10] TX1024TMAXOCTGBFIM MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask [9:9] TX512T1023OCTGBFIM MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask [8:8] TX256T511OCTGBFIM MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask [7:7] TX128T255OCTGBFIM MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask [6:6] TX65T127OCTGBFIM MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask [5:5] TX64OCTGBFIM MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask [4:4] TXMCGFIM MMC Transmit Multicast Good Frame Counter Interrupt Mask [3:3] TXBCGFIM MMC Transmit Broadcast Good Frame Counter Interrupt Mask [2:2] TXGBFRMIM MMC Transmit Good Bad Frame Counter Interrupt Mask [1:1] TXGBOCTIM MMC Transmit Good Bad Octet Counter Interrupt Mask [0:0] TXOCTETCOUNT_GB MMC Transmit Count 0x114 read-only 0x00000000 COUNT Number of bytes [31:0] TXFRAMECOUNT_GB MMC Frame Count Register 0x118 read-only 0x00000000 COUNT Number of frames [31:0] TXBCASTFRAMES_G MMC Good Broadcast Frames Register 0x11C read-only 0x00000000 COUNT Number of frames [31:0] TXMCASTFRAMES_G MMC Good Multicast Frames Register 0x120 read-only 0x00000000 COUNT Number of frames [31:0] TX64OCT_GB MMC Good and bad Frames transmitted with length 64 0x124 read-only 0x00000000 COUNT Number of frames [31:0] TX65TO127OCT_GB MMC Good and bad Frames transmitted with length 65 to 127 0x128 read-only 0x00000000 COUNT Number of frames [31:0] TX128TO255OCT_GB MMC Good and bad Frames transmitted with length 128 to 255 0x12C read-only 0x00000000 COUNT Number of frames [31:0] TX256TO511OCT_GB MMC Good and bad Frames transmitted with length 256 to 511 0x130 read-only 0x00000000 COUNT Number of frames [31:0] TX512TO1023OCT_GB MMC Good and bad Frames transmitted with length 512 to 1023 0x134 read-only 0x00000000 COUNT Number of frames [31:0] TX1024MAXOCT_GB MMC Good and bad Frames transmitted with length 1024 to max bytes 0x138 read-only 0x00000000 COUNT Number of frames [31:0] TXUCASTFRAME_GB MMC number of good and bad unicast frames transmitted 0x13C read-only 0x00000000 COUNT Number of frames [31:0] TXMCASTFRAME_GB MMC number of good and bad MULTIcast frames transmitted 0x140 read-only 0x00000000 COUNT Number of frames [31:0] TXBCASTFRAME_GB MMC number of good and bad broadcast frames transmitted 0x144 read-only 0x00000000 COUNT Number of frames [31:0] TXUNDERERR MMC number of frames aborted because of frame underflow error 0x148 read-only 0x00000000 COUNT Number of frames [31:0] TXSINGLECOL_G MMC Number of successfully transmitted frames after a single collision 0x14C read-only 0x00000000 COUNT Number of frames [31:0] TXMULTICOL_G MMC Number of successfully transmitted frames after multiple collisions 0x150 read-only 0x00000000 COUNT Number of frames [31:0] TXDEFERRED MMC Number of successfully transmitted frames after a deferral 0x154 read-only 0x00000000 COUNT Number of frames [31:0] TXLATECOL MMC Number of aborted frames because of late collision error 0x158 read-only 0x00000000 COUNT Number of frames [31:0] TXEXESSCOL MMC Number of aborted frames because of excessive collision errors 0x15C read-only 0x00000000 COUNT Number of frames [31:0] TXCARRIERERROR MMC Number of aborted frames because of carrier sense error 0x160 read-only 0x00000000 COUNT Number of frames [31:0] TXOCTETCOUNT_G MMC Number of bytes transmitted frames only in good frames 0x164 read-only 0x00000000 COUNT Number of bytes [31:0] TXFRAMECOUNT_G MMC Number of good frames transmitted 0x168 read-only 0x00000000 COUNT Number of frames [31:0] TXEXCESSDEF MMC Number of frames aborted because of excessive deferral error 0x16C read-only 0x00000000 COUNT Number of frames [31:0] TXPAUSEFRAMES MMC Number of good pause frames transmitted 0x170 read-only 0x00000000 COUNT Number of frames [31:0] TXLANFRAMES_G MMC Number of good VLAN frames transmitted 0x174 read-only 0x00000000 COUNT Number of frames [31:0] TXOVERSIZE_G MMC Number of frames transmitted without errors 0x178 read-only 0x00000000 COUNT Number of frames [31:0] RXFRAMECOUNT_GB MMC Number of good and bad frames received 0x180 read-only 0x00000000 COUNT Number of frames [31:0] RXOCTETCOUNT_GB MMC Number of bytes received in good and bad frames 0x184 read-only 0x00000000 COUNT Number of bytes [31:0] RXOCTETCOUNT_G MMC Number of bytes received in good frames only 0x188 read-only 0x00000000 COUNT Number of bytes [31:0] RXBCASTFRAMES_G MMC Number of good broadcast frames received 0x18C read-only 0x00000000 COUNT Number of frames [31:0] RXMCASTFRAMES_G MMC Number of good multicast frames received 0x190 read-only 0x00000000 COUNT Number of frames [31:0] RXCRCERROR MMC Number of frames received with CRC error 0x194 read-only 0x00000000 COUNT Number of frames [31:0] RXALIGNERROR MMC Number of frames received with alignment error 0x198 read-only 0x00000000 COUNT Number of frames [31:0] RXRUNTERROR MMC Number of frames received with runt error 0x19C read-only 0x00000000 COUNT Number of frames [31:0] RXJABBERERROR MMC Number of giant frames received with length greater than 1518 bytes and with CRC error 0x1A0 read-only 0x00000000 COUNT Number of frames [31:0] RXUNDERSIZE_G MMC Number of frames received with length less than 64 bytes 0x1A4 read-only 0x00000000 COUNT Number of frames [31:0] RXOVERSIZE_G MMC Number of frames received without errors with length greater than the max size 0x1A8 read-only 0x00000000 COUNT Number of frames [31:0] RX64OCTETS_GB MMC Number of good and bad frames received with length 64 bytes 0x1AC read-only 0x00000000 COUNT Number of frames [31:0] RX65TO127OCT_GB MMC Number of good and bad frames received with length between 65 and 127 bytes 0x1B0 read-only 0x00000000 COUNT Number of frames [31:0] RX128TO255OCT_GB MMC Number of good and bad frames received with length between 128 and 255 bytes 0x1B4 read-only 0x00000000 COUNT Number of frames [31:0] RX256TO511OCT_GB MMC Number of good and bad frames received with length between 256 and 511 bytes 0x1B8 read-only 0x00000000 COUNT Number of frames [31:0] RX512TO1023OCT_GB MMC Number of good and bad frames received with length between 512 and 1023 bytes 0x1BC read-only 0x00000000 COUNT Number of frames [31:0] RX1024MAXOCT_GB MMC Number of good and bad frames received with length between 1024 and max size bytes 0x1C0 read-only 0x00000000 COUNT Number of frames [31:0] RXUCASTFRAMES_G MMC Number of received good unicast frames 0x1C4 read-only 0x00000000 COUNT Number of frames [31:0] RXLENGTHERROR MMC Number of frames received with length error 0x1C8 read-only 0x00000000 COUNT Number of frames [31:0] RXOUTRANGETYPE MMC Number of frames received with length field not equal to the valid frame size 0x1CC read-only 0x00000000 COUNT Number of frames [31:0] RXPAUSEFRAMES MMC Number of good and valid Pause frames received 0x1D0 read-only 0x00000000 COUNT Number of frames [31:0] RXFIFOOVERFLOW MMC Number of missed received frames because of FIFO overflow 0x1D4 read-only 0x00000000 COUNT Number of frames [31:0] RXVLANFRAMES_GB MMC Number of good and bad VLAN frames received 0x1D8 read-only 0x00000000 COUNT Number of frames [31:0] RXWDOGERROR MMC Number of frames received with error because of watchdog timeout error 0x1DC read-only 0x00000000 COUNT Number of frames [31:0] RXRCVERROR MMC Number of frames received with Receive error or Frame Extension error 0x1E0 read-only 0x00000000 COUNT Number of frames [31:0] RXCTRLFRAMES_G MMC Number of received good control frames 0x1E4 read-only 0x00000000 COUNT Number of frames [31:0] VLAN_INCREPLACE Holds the VLAN Tag for insertion into or replacement in the transmit frames 0x584 read-write 0x00000000 CSVL C-VLAN or S-VLAN [19:19] VLP VLAN Priority Control [18:18] VLC VLAN Tag Control in Transmit Frames [17:16] VLT VLAN Tag for Transmit Frames [15:0] VLAN_HASHTABLE Holds the VLAN Hash Table 0x588 read-write 0x00000000 VLHT VLAN Hash Table [15:0] TIMESTAMP_CTRL Controls the IEEE 1588 timestamp generation and update logic 0x700 read-write 0x00000000 ATSEN3 Auxiliary Snapshot 3 Enable [28:28] ATSEN2 Auxiliary Snapshot 2 Enable [27:27] ATSEN1 Auxiliary Snapshot 1 Enable [26:26] ATSEN0 Auxiliary Snapshot 0 Enable [25:25] ATSFC Auxiliary Snapshot FIFO Clear [24:24] TSENMACADDR Enable MAC address for PTP Frame Filtering [18:18] SNAPTYPSEL Select PTP packets for Taking Snapshots [17:16] TSMSTRENA Enable Snapshot for Messages Relevant to Master [15:15] TSEVNTENA Enable Timestamp Snapshot for Event Messages [14:14] TSIPV4ENA Enable Processing of PTP Frames Sent over IPv4-UDP [13:13] TSIPV6ENA Enable Processing of PTP Frames Sent over IPv6-UDP [12:12] TSIPENA Enable Processing of PTP over Ethernet Frames [11:11] TSVER2ENA Enable PTP packet Processing for Version 2 Format [10:10] TSCTRLSSR Timestamp Digital or Binary Rollover Control [9:9] TSENALL Enable Timestamp for All Frames [8:8] TSADDRREG Addend Reg Update [5:5] TSTRIG Timestamp Interrupt Trigger Enable [4:4] TSUPDT Timestamp Update [3:3] TSINIT Timestamp Initialize [2:2] TSCFUPDT Timestamp Fine or Coarse Update [1:1] TSENA Timestamp Enable [0:0] SUBSEC_INC Holds the 8-bit value by which the Sub-Second register is incremented 0x704 read-write 0x00000000 SSINC Sub-Second Increment Valuee [7:0] SYSTIME_SECONDS Holds the lower 32 bits of the second field of the system time 0x708 read-only 0x00000000 TSS Timestamp Second [31:0] SYSTIME_NANOSEC Holds 32 bits of the nano-second field of the system time 0x70C read-only 0x00000000 TSSS Timestamp Sub Seconds [30:0] SYSTIME_SECSUPDAT Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value 0x710 read-write 0x00000000 TSS Timestamp Second [31:0] SYSTIME_NSECUP Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value 0x714 read-write 0x00000000 ADDSUB Add or Subtract Time [31:31] TSSS Timestamp Sub Seconds [30:0] TIMESTAMPADDEND This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency 0x718 read-write 0x00000000 TSAR Timestamp Addend Register [31:0] TARGET_TIME_SECS Holds the high 32-bits of time to be compared with the system time 0x71C read-write 0x00000000 TSTR Target Time Seconds Registe [31:0] TARGET_TIME_NSEC Holds the lower 32-bits of time to be compared with the system time 0x720 read-write 0x00000000 TRGTBUSY 32 Bits of Hash Table [31:31] TTSLO Target Timestamp Low Register [30:0] DMA_BUS_MODE Controls the DMA Host Interface Mode 0x1000 read-write 0x00020101 RIB Rebuild INCRx Burst [31:31] PRWG Channel Priority Weights [29:28] TXPR Transmit Priority [27:27] MB Mixed Burst [26:26] AAL Address-Aligned Beats [25:25] PBLx8 PBLx8 Mode [24:24] USP Use Separate PBL [23:23] RPBL Rx DMA PBL [22:17] FB Fixed Burste [16:16] PR Priority Ratio [15:14] PBL Programmable Burst Lengthe [13:8] DSL Descriptor Skip Length [6:2] DA DMA Arbitration Scheme [1:1] SWR Software Reset (Read, Write Set, and Self Clear) [0:0] DMA_TX_POLL_DEMAND Used by the host to instruct the DMA to poll the transmit Descriptor list 0x1004 read-write 0x00000000 TPD Transmit Poll Demand (Read Only and Write Trigger) [31:0] DMA_RX_POLL_DEMAND Used by the host to instruct the DMA to poll the Receive Descriptor list 0x1008 read-write 0x00000000 RPD Receive Poll Demand (Read Only and Write Trigger) [31:0] DMA_RX_DESC_LIST_ADDR Points the DMA to the start of the Receive Descriptor list 0x100C read-write 0x00000000 RDESLA Start of Receive List [31:0] DMA_TX_DESC_LIST_ADDR Points the DMA to the start of the Transmit Descriptor list 0x1010 read-write 0x00000000 TDESLA Start of Transmit List [31:0] DMA_STATUS Used to determine the status of the DMA 0x1014 read-only 0x00000000 TTI Timestamp Trigger Interrupt [29:29] GMI GMAC MMC Interrupt [27:27] EB Error Bits [25:23] TS Transmit Process State [22:20] RS Receive Process State [19:17] NIS Normal Interrupt Summary [16:16] AIS Abnormal Interrupt Summary [15:15] ERI Early Receive Interrupt [14:14] FBI Fatal Bus Error Interruptble [13:13] ETI Early Transmit Interrupt [10:10] RWT Receive Watchdog Timeout [9:9] RPS Receive Process Stopped [8:8] RU Receive Buffer Unavailable [7:7] RI Receive Interrupt [6:6] UNF Transmit Underflow [5:5] OVF Receive Underflow [4:4] TJT Transmit Jabber Timeout [3:3] TU Transmit Buffer Unavailable [2:2] TPS Transmit Process Stopped [1:1] TI Transmit Interrupt [0:0] DMA_OPER_MODE Sets the Receive and Transmit operation mode and command 0x1018 read-write 0x00000000 DT Disable Dropping of TCP/IP Checksum Error Frames [26:26] RSF Receive Store and Forward [25:25] DFF Disable Flushing of Received Frames [24:24] TSF Transmit Store and Forward [21:21] FTF Flush Transmit FIFO [20:20] TTC Transmit Threshold Control [16:14] ST Start or Stop Transmission Command [13:13] RFD Threshold for Deactivating Flow Control [12:11] RFA Threshold for Activating Flow Control [10:9] FEF Forward Error Frames [7:7] FUF Forward Undersized Good Frames [6:6] DGF Drop Giant Frames [5:5] RTC Receive Threshold Control [4:3] OSF Operate on Second Frame [2:2] SR Start or Stop Receive [1:1] DMA_INTR_EN Enables the interrupts reported in the status register 0x101C read-write 0x00000000 NIE Normal Interrupt Summary Enable [16:16] AIE Abnormal Interrupt Summary Enable [15:15] ERE Early Receive Interrupt Enable [14:14] FBE Fatal Bus Error Enable [13:13] ETE Early Transmit Interrupt Enable [10:10] RWE Receive Watchdog Timeout Enable [9:9] RSE Receive Stopped Enable [8:8] RUE Receive Buffer Unavailable Enable [7:7] RIE Receive Interrupt Enable [6:6] UNE Underflow Interrupt Enable [5:5] OVE Overflow Interrupt Enable [4:4] THE Transmit Jabber Timeout Enable [3:3] TUE Transmit Buffer Unavailable Enable [2:2] TSE Transmit Stopped Enable [1:1] TIE Transmit Interrupt Enable [0:0] DMA_MISS_OVER_COUNTER Contains the counters for discarded frames because no Receive Descriptor is available 0x1020 read-write 0x00000000 OVFCNTOVF This bit is set every time the Overflow Frame Counter (Bits[27:17])overflows [28:28] OVFFRMCNT This field indicates the number of frames missed by the application [27:17] MISCNTOVF This bit is set every time Missed Frame Counter (Bits[15:0]) overflows [16:16] MISFRMCNT This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. [15:0] DMA_RX_INTR_WDOG_TIMER Watchdog timeout for Receive Interrupt from DMA 0x1024 read-write 0x00000000 RIWT These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set. [7:0] DMA_AHB_STATUS Provides the active status of the read and write channels of the AHB master interface 0x102C read-write 0x00000000 AHBMASTRSTS When high, indicates that the AHB master interface FSMs are in the non-idle state [0:0] DMA_CURR_TX_DESC Contains the start address of the current Transmit Descriptor read by the DMA 0x1048 read-write 0x00000000 CURTDESAPTR Cleared on Reset. Pointer updated by the DMA during operation. [31:0] DMA_CURR_RX_DESC Contains the start address of the current Receive Descriptor read by the DMA 0x104C read-write 0x00000000 CURRDESAPTR Cleared on Reset. Pointer updated by the DMA during operation. [31:0] DMA_CURR_TX_BUFR_ADDR Contains the start address of the current Receive Descriptor read by the DMA 0x1050 read-write 0x00000000 CURTBUFAPTR Cleared on Reset. Pointer updated by the DMA during operation. [31:0] DMA_CURR_RX_BUFR_ADDR Contains the current Receive Buffer address read by the DMA 0x1054 read-write 0x00000000 CURTBUFAPTR Cleared on Reset. Pointer updated by the DMA during operation. [31:0]