417 lines
11 KiB
Rust
417 lines
11 KiB
Rust
//! Custom register definitions for the CAN register block to circumvent PAC API / SVD
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//! shortcomings.
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use arbitrary_int::{u11, u15, u2, u3, u4, u6, u7, Number};
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pub const CAN_0_BASE: usize = 0x4001_4000;
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pub const CAN_1_BASE: usize = 0x4001_4400;
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#[derive(Debug, PartialEq, Eq)]
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#[bitbybit::bitenum(u4)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum BufferState {
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/// Passive channel.
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RxNotActive = 0b0000,
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/// This condition indicated that SW wrote RxNotActive to a buffer when a data copy
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/// process is still active.
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RxBusy = 0b0001,
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RxReady = 0b0010,
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/// Indicated that data is being copied for the first time (RxRead -> RxBusy0).
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RxBusy0 = 0b0011,
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RxFull = 0b0100,
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/// Indicated that data is being copied for the second time (RxFull -> RxBusy2).
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RxBusy1 = 0b0101,
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RxOverrun = 0b0110,
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RxBusy2 = 0b0111,
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TxNotActive = 0b1000,
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/// Automatical response to a remote frame.
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TxRtr = 0b1010,
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/// Transmit one frame.
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TxOnce = 0b1100,
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TxBusy0 = 0b1101,
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/// Transmit one frame, and changes to TxRtr after that. This can either be written by
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/// software, or it will be written by the hardware after an auto response of the
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/// [BufferState::TxRtr] state.
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TxOnceRtr = 0b1110,
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TxBusy2 = 0b1111,
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}
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/// Status control register for individual message buffers.
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct BufStatusAndControl {
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/// Data length code.
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#[bits(12..=15, rw)]
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dlc: u4,
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#[bits(4..=7, rw)]
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priority: u4,
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#[bits(0..=3, rw)]
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state: Option<BufferState>,
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}
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#[derive(Debug)]
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pub struct Timestamp(arbitrary_int::UInt<u32, 16>);
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impl Timestamp {
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pub fn new(value: u16) -> Self {
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Self(value.into())
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}
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pub fn value(&self) -> u16 {
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self.0.value() as u16
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}
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pub fn write(&mut self, value: u16) {
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self.0 = value.into();
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}
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct TwoBytesData {
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#[bits(0..=7, rw)]
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data_lower_byte: u8,
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#[bits(8..=15, rw)]
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data_upper_byte: u8,
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}
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct CanMsgBuf {
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stat_ctrl: BufStatusAndControl,
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timestamp: Timestamp,
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data3: TwoBytesData,
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data2: TwoBytesData,
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data1: TwoBytesData,
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data0: TwoBytesData,
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id0: ExtendedId,
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id1: BaseId,
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}
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static_assertions::const_assert_eq!(core::mem::size_of::<CanMsgBuf>(), 0x20);
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impl MmioCanMsgBuf<'_> {
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pub fn reset(&mut self) {
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self.write_stat_ctrl(BufStatusAndControl::new_with_raw_value(0));
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self.write_timestamp(Timestamp::new(0));
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self.write_data0(TwoBytesData::new_with_raw_value(0));
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self.write_data1(TwoBytesData::new_with_raw_value(0));
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self.write_data2(TwoBytesData::new_with_raw_value(0));
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self.write_data3(TwoBytesData::new_with_raw_value(0));
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self.write_id1(BaseId::new_with_raw_value(0));
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self.write_id0(ExtendedId::new_with_raw_value(0));
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}
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug)]
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pub enum PinLogicLevel {
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DominantIsZero = 0b0,
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DominantIsOne = 0b1,
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug)]
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pub enum ErrorInterruptType {
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/// EIPND bit is set on every error.
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EveryError = 0b0,
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/// EIPND bit is only set if error state changes as a result of a receive or transmit
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/// error counter increment.
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ErrorOnRxTxCounterChange = 0b1,
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug)]
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pub enum DataDirection {
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FirstByteAtHighestAddr = 0b0,
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LastByteAtHighestAddr = 0b1,
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}
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#[bitbybit::bitfield(u32)]
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pub struct Control {
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#[bit(11, rw)]
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error_interrupt_type: ErrorInterruptType,
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/// Enables special diagnostics features of the CAN like LO, IGNACK, LOOPBACK, INTERNAL.
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#[bit(10, rw)]
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diag_enable: bool,
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/// CANTX and CANRX pins are internally connected to each other.
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#[bit(9, rw)]
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internal: bool,
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/// All messages sent by the CAN controller can also be received by a CAN buffer with a
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/// matching buffer ID.
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#[bit(8, rw)]
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loopback: bool,
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/// IGNACK feature. The CAN does not expect to receive an ACK bit.
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#[bit(7, rw)]
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ignore_ack: bool,
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/// LO feature. The CAN is only configured as a receiver.
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#[bit(6, rw)]
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listen_only: bool,
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#[bit(5, rw)]
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data_dir: DataDirection,
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#[bit(4, rw)]
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timestamp_enable: bool,
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#[bit(3, rw)]
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bufflock: bool,
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#[bit(2, rw)]
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tx_logic_level: PinLogicLevel,
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#[bit(1, rw)]
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rx_logic_level: PinLogicLevel,
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#[bit(0, rw)]
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enable: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct TimingConfig {
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#[bits(0..=2, rw)]
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tseg2: u3,
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#[bits(3..=6, rw)]
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tseg1: u4,
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#[bits(7..=8, rw)]
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sync_jump_width: u2,
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#[bits(9..=15, rw)]
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prescaler: u7,
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct InterruptEnable {
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#[bit(15, rw)]
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error: bool,
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#[bit(0, rw)]
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buffer: [bool; 15],
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct InterruptClear {
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#[bit(15, w)]
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error: bool,
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#[bit(0, w)]
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buffer: [bool; 15],
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct InterruptPending {
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#[bit(15, r)]
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error: bool,
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#[bit(0, r)]
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buffer: [bool; 15],
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}
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#[derive(Debug)]
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#[repr(usize)]
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pub enum CanInterruptId {
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None = 0b00000,
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Error = 0b10000,
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Buffer(usize),
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct StatusPending {
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#[bits(5..=7, r)]
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ns: u3,
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#[bit(4, r)]
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irq: bool,
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#[bits(0..=3, r)]
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ist: u4,
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}
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impl StatusPending {
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pub fn interrupt_id(&self) -> Option<CanInterruptId> {
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if !self.irq() && self.ist().value() == 0 {
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return Some(CanInterruptId::None);
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}
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//let raw_value = ((self.irq() as u8) << 4) | self.ist().as_u8();
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if self.irq() && self.ist().value() == 0 {
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return Some(CanInterruptId::Error);
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}
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if !self.irq() {
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return None;
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}
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Some(CanInterruptId::Buffer(self.ist().as_usize()))
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}
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct ErrorCounter {
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#[bits(0..=7, r)]
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transmit: u8,
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#[bits(8..=15, r)]
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receive: u8,
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}
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/// This register is unused for standard frames.
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct ExtendedId {
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/// Mask for ID bits \[14:0\] of extended frames.
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#[bits(1..=15, rw)]
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mask_14_0: u15,
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/// CAN XRTR bit.
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#[bit(0, rw)]
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xrtr: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct BaseId {
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/// This will contain ID\[10:0\] for standard frames and bits [28:18] for extended frames.
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#[bits(5..=15, rw)]
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mask_28_18: u11,
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/// This is the RTR bit for standard frames, and the SRR bit for extended frames.
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#[bit(4, rw)]
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rtr_or_srr: bool,
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/// Identifier extension bit.
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#[bit(3, rw)]
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ide: bool,
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/// Mask for ID bits \[17:15\] of extended frames.
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#[bits(0..=2, rw)]
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mask_17_15: u3,
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}
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#[derive(Debug, PartialEq, Eq)]
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#[bitbybit::bitenum(u4, exhaustive = true)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum ErrorFieldId {
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Error = 0b0000,
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ErrorDel = 0b0001,
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ErrorEcho = 0b0010,
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BusIdle = 0b0011,
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Ack = 0b0100,
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Eof = 0b0101,
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Intermission = 0b0110,
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SuspendTransmission = 0b0111,
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Sof = 0b1000,
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Arbitration = 0b1001,
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Ide = 0b1010,
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ExtendedArbitration = 0b1011,
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R1R0 = 0b1100,
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Dlc = 0b1101,
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Data = 0b1110,
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Crc = 0b1111,
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}
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#[bitbybit::bitfield(u32)]
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pub struct DiagnosticRegister {
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/// Shows the output value on the CAN TX pin at the time of the error.
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#[bit(14, r)]
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drive: bool,
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/// Shows the bus value on the CAN RX pin as sampled by the CAN module at the time of the
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/// error.
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#[bit(13, r)]
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mon: bool,
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/// Indicated whether the CRC is invalid. This bit should only be checked if the EFID field
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/// is [ErrorFieldId::Ack].
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#[bit(12, r)]
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crc: bool,
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/// Indicated whether the bit stuffing rule was violated at the time the error occured.
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#[bit(11, r)]
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stuff: bool,
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/// Indicated whether the CAN module was an active transmitter at the time the error occured.
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#[bit(10, r)]
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txe: bool,
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#[bits(4..=9, r)]
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ebid: u6,
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#[bits(0..=3, r)]
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efid: ErrorFieldId,
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}
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impl core::fmt::Debug for DiagnosticRegister {
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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f.debug_struct("DiagnosticRegister")
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.field("efid", &self.efid())
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.field("ebid", &self.ebid())
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.field("txe", &self.txe())
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.field("stuff", &self.stuff())
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.field("crc", &self.crc())
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.field("mon", &self.mon())
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.field("drive", &self.drive())
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.finish()
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}
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}
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#[cfg(feature = "defmt")]
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impl defmt::Format for DiagnosticRegister {
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fn format(&self, fmt: defmt::Formatter) {
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defmt::write!(
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fmt,
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"DiagnosticRegister {{ efid: {}, ebid: {}, txe: {}, stuff: {}, crc: {}, mon: {}, drive: {} }}",
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self.efid(),
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self.ebid(),
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self.txe(),
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self.stuff(),
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self.crc(),
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self.mon(),
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self.drive()
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)
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}
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}
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#[derive(derive_mmio::Mmio)]
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#[mmio(const_inner)]
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#[repr(C)]
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pub struct Can {
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#[mmio(inner)]
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cmbs: [CanMsgBuf; 15],
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/// Hidden CAN message buffer. Only allowed to be used internally by the peripheral.
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#[mmio(inner)]
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_hcmb: CanMsgBuf,
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control: Control,
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timing: TimingConfig,
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/// Global mask extension used for buffers 0 to 13.
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gmskx: ExtendedId,
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/// Global mask base used for buffers 0 to 13.
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gmskb: BaseId,
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/// Basic mask extension used for buffer 14.
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bmskx: ExtendedId,
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/// Basic mask base used for buffer 14.
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bmskb: BaseId,
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ien: InterruptEnable,
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#[mmio(PureRead)]
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ipnd: InterruptPending,
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#[mmio(Write)]
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iclr: InterruptClear,
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/// Interrupt Code Enable Register.
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icen: InterruptEnable,
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#[mmio(PureRead)]
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status_pending: StatusPending,
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#[mmio(PureRead)]
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error_counter: ErrorCounter,
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#[mmio(PureRead)]
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diag: DiagnosticRegister,
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#[mmio(PureRead)]
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timer: u32,
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}
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static_assertions::const_assert_eq!(core::mem::size_of::<Can>(), 0x238);
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impl Can {
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/// Create a new CAN MMIO instance for peripheral 0.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio_fixed_0() -> MmioCan<'static> {
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Self::new_mmio_at(CAN_0_BASE)
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}
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/// Create a new CAN MMIO instance for peripheral 1.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio_fixed_1() -> MmioCan<'static> {
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Self::new_mmio_at(CAN_1_BASE)
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}
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}
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