Robin Mueller
935ee9dbb1
Changed: - Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) which is mostly re-exported in this crate. - Overhaul and simplification of several HAL APIs. The system configuration and IRQ router peripheral instance generally does not need to be passed to HAL API anymore. - All HAL drivers are now type erased. The constructors will still expect and consume the PAC singleton component for resource management purposes, but are not cached anymore. - Refactoring of GPIO library to be more inline with embassy GPIO API. Added: - I2C clock timeout feature support.
441 lines
14 KiB
Rust
441 lines
14 KiB
Rust
//! API for using the [crate::pac::Clkgen] peripheral.
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//!
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//! It also includes functionality to enable the peripheral clocks.
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//! Calling [ClockConfigurator::new] returns a builder structure which allows
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//! setting up the clock.
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//!
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//! Calling [ClockConfigurator::freeze] returns the frozen clock configuration inside the [Clocks]
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//! structure. This structure can also be used to configure other structures provided by this HAL.
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//!
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//! # Examples
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//!
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//! - [UART example on the PEB1 board](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs)
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#[cfg(not(feature = "va41628"))]
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use crate::adc::ADC_MAX_CLK;
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use crate::pac;
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use crate::time::Hertz;
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pub use vorago_shared_periphs::clock::{Clocks, HBO_FREQ};
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use vorago_shared_periphs::{enable_peripheral_clock, PeripheralSelect};
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pub const XTAL_OSC_TSTART_MS: u32 = 15;
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum FilterClkSel {
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SysClk = 0,
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Clk1 = 1,
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Clk2 = 2,
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Clk3 = 3,
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Clk4 = 4,
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Clk5 = 5,
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Clk6 = 6,
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Clk7 = 7,
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}
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/// Refer to chapter 8 (p.57) of the programmers guide for detailed information.
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum ClkselSys {
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// Internal Heart-Beat Osciallator. Not tightly controlled (+/-20 %). Not recommended as the regular clock!
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Hbo = 0b00,
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// External clock signal on XTAL_N line, 1-100 MHz
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XtalN = 0b01,
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// Internal Phase-Locked Loop.
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Pll = 0b10,
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// Crystal oscillator amplified, 4-10 MHz.
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XtalOsc = 0b11,
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}
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/// This selects the input clock to the the CLKGEN peripheral in addition to the HBO clock.
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///
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/// This can either be a clock connected directly on the XTAL_N line or a chrystal on the XTAL_P
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/// line which goes through an oscillator amplifier.
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///
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/// Refer to chapter 8 (p.57) of the programmers guide for detailed information.
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#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum RefClkSel {
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#[default]
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None = 0b00,
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XtalOsc = 0b01,
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XtalN = 0b10,
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}
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#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum ClkDivSel {
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#[default]
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Div1 = 0b00,
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Div2 = 0b01,
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Div4 = 0b10,
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Div8 = 0b11,
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}
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum AdcClkDivSel {
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Div8 = 0b00,
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Div4 = 0b01,
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Div2 = 0b10,
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Div1 = 0b11,
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}
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#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct PllCfg {
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/// Reference clock divider.
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pub clkr: u8,
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/// Clock divider on feedback path
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pub clkf: u8,
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// Output clock divider.
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pub clkod: u8,
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/// Bandwidth adjustment
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pub bwadj: u8,
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}
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pub fn clk_after_div(clk: Hertz, div_sel: ClkDivSel) -> Hertz {
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match div_sel {
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ClkDivSel::Div1 => clk,
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ClkDivSel::Div2 => clk / 2,
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ClkDivSel::Div4 => clk / 4,
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ClkDivSel::Div8 => clk / 8,
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}
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}
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/// Wait for 500 reference clock cycles like specified in the datasheet.
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pub fn pll_setup_delay() {
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for _ in 0..500 {
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cortex_m::asm::nop()
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}
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}
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pub trait ClkgenExt {
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fn constrain(self) -> ClockConfigurator;
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}
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impl ClkgenExt for pac::Clkgen {
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fn constrain(self) -> ClockConfigurator {
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ClockConfigurator {
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source_clk: None,
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ref_clk_sel: RefClkSel::None,
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clksel_sys: ClkselSys::Hbo,
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clk_div_sel: ClkDivSel::Div1,
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clk_lost_detection: false,
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pll_lock_lost_detection: false,
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pll_cfg: None,
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clkgen: self,
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}
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}
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}
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct ClkSourceFreqNotSet;
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum ClkCfgError {
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ClkSourceFreqNotSet,
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PllConfigNotSet,
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PllInitError,
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InconsistentCfg,
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}
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pub struct ClockConfigurator {
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ref_clk_sel: RefClkSel,
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clksel_sys: ClkselSys,
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clk_div_sel: ClkDivSel,
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/// The source clock frequency which is either an external clock connected to XTAL_N, or a
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/// crystal connected to the XTAL_OSC input.
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source_clk: Option<Hertz>,
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pll_cfg: Option<PllCfg>,
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clk_lost_detection: bool,
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/// Feature only works on revision B of the board.
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#[cfg(feature = "revb")]
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pll_lock_lost_detection: bool,
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clkgen: pac::Clkgen,
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}
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/// Delays a given amount of milliseconds.
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///
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/// Taken from the HAL implementation. This implementation is probably not precise and it
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/// also blocks!
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pub fn hbo_clock_delay_ms(ms: u32) {
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let wdt = unsafe { pac::WatchDog::steal() };
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for _ in 0..ms {
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for _ in 0..10_000 {
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cortex_m::asm::nop();
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}
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wdt.wdogintclr().write(|w| unsafe { w.bits(1) });
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}
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}
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impl ClockConfigurator {
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/// Create a new clock configuration instance.
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pub fn new(clkgen: pac::Clkgen) -> Self {
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ClockConfigurator {
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source_clk: None,
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ref_clk_sel: RefClkSel::None,
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clksel_sys: ClkselSys::Hbo,
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clk_div_sel: ClkDivSel::Div1,
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clk_lost_detection: false,
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pll_lock_lost_detection: false,
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pll_cfg: None,
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clkgen,
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}
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}
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/// Steals a new [ClockConfigurator] instance.
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///
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/// # Safety
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///
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/// Circumvents HAL ownership rules.
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pub unsafe fn steal() -> Self {
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Self::new(unsafe { pac::Clkgen::steal() })
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}
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#[inline]
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pub fn source_clk(mut self, src_clk: Hertz) -> Self {
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self.source_clk = Some(src_clk);
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self
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}
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/// This function can be used to utilize the XTAL_N clock input directly without the
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/// oscillator.
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///
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/// It sets the internal configuration to [ClkselSys::XtalN] and [RefClkSel::XtalN].
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#[inline]
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pub fn xtal_n_clk(mut self) -> Self {
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self.clksel_sys = ClkselSys::XtalN;
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self.ref_clk_sel = RefClkSel::XtalN;
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self
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}
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#[inline]
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pub fn xtal_n_clk_with_src_freq(mut self, src_clk: Hertz) -> Self {
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self = self.xtal_n_clk();
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self.source_clk(src_clk)
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}
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#[inline]
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pub fn clksel_sys(mut self, clksel_sys: ClkselSys) -> Self {
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self.clksel_sys = clksel_sys;
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self
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}
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#[inline]
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pub fn pll_cfg(mut self, pll_cfg: PllCfg) -> Self {
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self.pll_cfg = Some(pll_cfg);
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self
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}
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#[inline]
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pub fn ref_clk_sel(mut self, ref_clk_sel: RefClkSel) -> Self {
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self.ref_clk_sel = ref_clk_sel;
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self
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}
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/// Configures all clocks and return a clock configuration structure containing the final
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/// frozen clocks.
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///
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/// Internal implementation details: This implementation is based on the HAL implementation
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/// which performs a lot of delays. I do not know if all of those are necessary, but
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/// I am going to be conservative here and assume that the vendor has tested though and
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/// might have had a reason for those, so I am going to keep them. Chances are, this
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/// process only has to be performed once, and it does not matter if it takes a few
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/// microseconds or milliseconds longer.
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pub fn freeze(self) -> Result<Clocks, ClkCfgError> {
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// Sanitize configuration.
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if self.source_clk.is_none() {
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return Err(ClkCfgError::ClkSourceFreqNotSet);
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}
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if self.clksel_sys == ClkselSys::XtalOsc && self.ref_clk_sel != RefClkSel::XtalOsc {
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return Err(ClkCfgError::InconsistentCfg);
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}
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if self.clksel_sys == ClkselSys::XtalN && self.ref_clk_sel != RefClkSel::XtalN {
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return Err(ClkCfgError::InconsistentCfg);
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}
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if self.clksel_sys == ClkselSys::Pll && self.pll_cfg.is_none() {
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return Err(ClkCfgError::PllConfigNotSet);
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}
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enable_peripheral_clock(PeripheralSelect::Clkgen);
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let mut final_sysclk = self.source_clk.unwrap();
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// The HAL forces back the HBO clock here with a delay.. Even though this is
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// not stricly necessary when coming from a fresh start, it could be still become relevant
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// later if the clock lost detection mechanism require a re-configuration of the clocks.
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// Therefore, we do it here as well.
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self.clkgen
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.ctrl0()
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.modify(|_, w| unsafe { w.clksel_sys().bits(ClkselSys::Hbo as u8) });
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pll_setup_delay();
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self.clkgen
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.ctrl0()
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.modify(|_, w| unsafe { w.clk_div_sel().bits(ClkDivSel::Div1 as u8) });
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// Set up oscillator and PLL input clock.
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self.clkgen
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.ctrl0()
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.modify(|_, w| unsafe { w.ref_clk_sel().bits(self.ref_clk_sel as u8) });
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self.clkgen.ctrl1().modify(|_, w| {
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w.xtal_en().clear_bit();
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w.xtal_n_en().clear_bit();
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w
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});
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match self.ref_clk_sel {
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RefClkSel::None => pll_setup_delay(),
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RefClkSel::XtalOsc => {
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self.clkgen.ctrl1().modify(|_, w| w.xtal_en().set_bit());
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hbo_clock_delay_ms(XTAL_OSC_TSTART_MS);
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}
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RefClkSel::XtalN => {
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self.clkgen.ctrl1().modify(|_, w| w.xtal_n_en().set_bit());
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pll_setup_delay()
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}
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}
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// Set up PLL configuration.
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match self.pll_cfg {
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Some(cfg) => {
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self.clkgen.ctrl0().modify(|_, w| w.pll_pwdn().clear_bit());
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// Done in C HAL. I guess this gives the PLL some time to power down properly.
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cortex_m::asm::nop();
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cortex_m::asm::nop();
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self.clkgen.ctrl0().modify(|_, w| {
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unsafe {
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w.pll_clkf().bits(cfg.clkf);
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}
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unsafe {
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w.pll_clkr().bits(cfg.clkr);
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}
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unsafe {
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w.pll_clkod().bits(cfg.clkod);
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}
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unsafe {
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w.pll_bwadj().bits(cfg.bwadj);
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}
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w.pll_test().clear_bit();
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w.pll_bypass().clear_bit();
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w.pll_intfb().set_bit()
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});
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// Taken from SystemCoreClockUpdate implementation from Vorago.
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final_sysclk /= cfg.clkr as u32 + 1;
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final_sysclk *= cfg.clkf as u32 + 1;
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final_sysclk /= cfg.clkod as u32 + 1;
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// Reset PLL.
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self.clkgen.ctrl0().modify(|_, w| w.pll_reset().set_bit());
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// The HAL does this, the datasheet specifies a delay of 5 us. I guess it does not
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// really matter because the PLL lock detect is used later..
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pll_setup_delay();
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self.clkgen.ctrl0().modify(|_, w| w.pll_reset().clear_bit());
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pll_setup_delay();
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// check for lock
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let stat = self.clkgen.stat().read();
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if stat.fbslip().bit() || stat.rfslip().bit() {
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pll_setup_delay();
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if stat.fbslip().bit() || stat.rfslip().bit() {
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// This is what the HAL does. We could continue, but then we would at least
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// have to somehow report a partial error.. Chances are, the user does not
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// want to continue with a broken PLL clock.
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return Err(ClkCfgError::PllInitError);
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}
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}
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}
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None => {
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self.clkgen.ctrl0().modify(|_, w| w.pll_pwdn().set_bit());
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}
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}
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if self.clk_lost_detection {
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rearm_sysclk_lost_with_periph(&self.clkgen)
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}
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#[cfg(feature = "revb")]
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if self.pll_lock_lost_detection {
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rearm_pll_lock_lost_with_periph(&self.clkgen)
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}
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self.clkgen
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.ctrl0()
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.modify(|_, w| unsafe { w.clk_div_sel().bits(self.clk_div_sel as u8) });
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final_sysclk = clk_after_div(final_sysclk, self.clk_div_sel);
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// The HAL does this. I don't know why..
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pll_setup_delay();
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self.clkgen
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.ctrl0()
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.modify(|_, w| unsafe { w.clksel_sys().bits(self.clksel_sys as u8) });
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Ok(Clocks::__new(
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final_sysclk,
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#[cfg(not(feature = "va41628"))]
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self.cfg_adc_clk_div(final_sysclk),
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))
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}
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#[cfg(not(feature = "va41628"))]
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fn cfg_adc_clk_div(&self, final_sysclk: Hertz) -> Hertz {
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// I will just do the ADC stuff like Vorago does it.
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// ADC clock (must be 2-12.5 MHz)
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// NOTE: Not using divide by 1 or /2 ratio in REVA silicon because of triggering issue
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// For this reason, keep SYSCLK above 8MHz to have the ADC /4 ratio in range)
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if final_sysclk.raw() <= ADC_MAX_CLK.raw() * 4 {
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self.clkgen
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.ctrl1()
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.modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div4 as u8) });
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final_sysclk / 4
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} else {
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self.clkgen
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.ctrl1()
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.modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div8 as u8) });
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final_sysclk / 8
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}
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}
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}
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pub fn rearm_sysclk_lost() {
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rearm_sysclk_lost_with_periph(&unsafe { pac::Clkgen::steal() })
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}
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fn rearm_sysclk_lost_with_periph(clkgen: &pac::Clkgen) {
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clkgen
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.ctrl0()
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.modify(|_, w| w.sys_clk_lost_det_en().set_bit());
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clkgen
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.ctrl1()
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.write(|w| w.sys_clk_lost_det_rearm().set_bit());
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clkgen
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.ctrl1()
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.write(|w| w.sys_clk_lost_det_rearm().clear_bit());
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}
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#[cfg(feature = "revb")]
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pub fn rearm_pll_lock_lost() {
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rearm_pll_lock_lost_with_periph(&unsafe { pac::Clkgen::steal() })
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}
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fn rearm_pll_lock_lost_with_periph(clkgen: &pac::Clkgen) {
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clkgen
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.ctrl1()
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.modify(|_, w| w.pll_lost_lock_det_en().set_bit());
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clkgen.ctrl1().write(|w| w.pll_lck_det_rearm().set_bit());
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clkgen.ctrl1().write(|w| w.pll_lck_det_rearm().clear_bit());
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn test_basic_div() {
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assert_eq!(
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clk_after_div(Hertz::from_raw(10_000_000), super::ClkDivSel::Div2),
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Hertz::from_raw(5_000_000)
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);
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}
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}
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