Robin Mueller
abede6057e
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Rust/va416xx-rs/pipeline/pr-main This commit looks good
1139 lines
34 KiB
Rust
1139 lines
34 KiB
Rust
//! # API for the UART peripheral
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//!
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//! The core of this API are the [Uart], [UartBase], [Rx] and [Tx] structures.
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//! The RX structure also has a dedicated [RxWithIrq] variant which allows reading the receiver
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//! using interrupts.
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//!
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//! ## Examples
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//!
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//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs)
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//! - [UART echo with IRQ and Embassy](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/embassy/src/bin/uart-echo-with-irq.rs)
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//! - [Flashloader app using UART with IRQs](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/flashloader)
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use core::ops::Deref;
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use embedded_hal_nb::serial::Read;
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use fugit::RateExtU32;
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use crate::clock::{Clocks, PeripheralSelect, SyscfgExt};
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use crate::gpio::PF13;
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use crate::time::Hertz;
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use crate::{disable_interrupt, enable_interrupt};
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use crate::{
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gpio::{
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AltFunc1, AltFunc2, AltFunc3, Pin, PA2, PA3, PB14, PB15, PC14, PC4, PC5, PD11, PD12, PE2,
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PE3, PF12, PF9, PG0, PG1,
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},
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pac::{self, uart0 as uart_base, Uart0, Uart1, Uart2},
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};
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#[cfg(not(feature = "va41628"))]
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use crate::gpio::{PC15, PF8};
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//==================================================================================================
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// Type-Level support
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//==================================================================================================
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pub trait RxPin<Uart> {}
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pub trait TxPin<Uart> {}
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impl TxPin<Uart0> for Pin<PA2, AltFunc3> {}
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impl RxPin<Uart0> for Pin<PA3, AltFunc3> {}
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impl TxPin<Uart0> for Pin<PC4, AltFunc2> {}
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impl RxPin<Uart0> for Pin<PC5, AltFunc2> {}
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impl TxPin<Uart0> for Pin<PE2, AltFunc3> {}
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impl RxPin<Uart0> for Pin<PE3, AltFunc3> {}
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impl TxPin<Uart0> for Pin<PG0, AltFunc1> {}
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impl RxPin<Uart0> for Pin<PG1, AltFunc1> {}
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impl TxPin<Uart1> for Pin<PB14, AltFunc3> {}
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impl RxPin<Uart1> for Pin<PB15, AltFunc3> {}
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impl TxPin<Uart1> for Pin<PD11, AltFunc3> {}
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impl RxPin<Uart1> for Pin<PD12, AltFunc3> {}
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impl TxPin<Uart1> for Pin<PF12, AltFunc1> {}
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impl RxPin<Uart1> for Pin<PF13, AltFunc1> {}
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impl TxPin<Uart2> for Pin<PC14, AltFunc2> {}
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#[cfg(not(feature = "va41628"))]
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impl RxPin<Uart2> for Pin<PC15, AltFunc2> {}
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#[cfg(not(feature = "va41628"))]
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impl TxPin<Uart2> for Pin<PF8, AltFunc1> {}
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impl RxPin<Uart2> for Pin<PF9, AltFunc1> {}
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//==================================================================================================
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// Regular Definitions
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//==================================================================================================
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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Overrun,
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FramingError,
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ParityError,
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BreakCondition,
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TransferPending,
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BufferTooShort,
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}
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Event {
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// Receiver FIFO interrupt enable. Generates interrupt
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// when FIFO is at least half full. Half full is defined as FIFO
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// count >= RXFIFOIRQTRG
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RxFifoHalfFull,
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// Framing error, Overrun error, Parity Error and Break error
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RxError,
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// Event for timeout condition: Data in the FIFO and no receiver
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// FIFO activity for 4 character times
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RxTimeout,
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// Transmitter FIFO interrupt enable. Generates interrupt
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// when FIFO is at least half full. Half full is defined as FIFO
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// count >= TXFIFOIRQTRG
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TxFifoHalfFull,
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// FIFO overflow error
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TxError,
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// Generate interrupt when transmit FIFO is empty and TXBUSY is 0
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TxEmpty,
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// Interrupt when CTSn changes value
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TxCts,
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}
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Parity {
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None,
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Odd,
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Even,
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}
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum StopBits {
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One = 0,
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Two = 1,
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}
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum WordSize {
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Five = 0,
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Six = 1,
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Seven = 2,
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Eight = 3,
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}
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct Config {
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pub baudrate: Hertz,
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pub parity: Parity,
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pub stopbits: StopBits,
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// When false, use standard 16x baud clock, other 8x baud clock
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pub baud8: bool,
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pub wordsize: WordSize,
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pub enable_tx: bool,
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pub enable_rx: bool,
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}
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impl Config {
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pub fn baudrate(mut self, baudrate: Hertz) -> Self {
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self.baudrate = baudrate;
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self
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}
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pub fn parity_none(mut self) -> Self {
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self.parity = Parity::None;
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self
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}
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pub fn parity_even(mut self) -> Self {
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self.parity = Parity::Even;
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self
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}
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pub fn parity_odd(mut self) -> Self {
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self.parity = Parity::Odd;
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self
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}
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pub fn stopbits(mut self, stopbits: StopBits) -> Self {
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self.stopbits = stopbits;
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self
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}
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pub fn wordsize(mut self, wordsize: WordSize) -> Self {
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self.wordsize = wordsize;
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self
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}
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pub fn baud8(mut self, baud: bool) -> Self {
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self.baud8 = baud;
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self
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}
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}
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impl Default for Config {
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fn default() -> Config {
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Config {
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baudrate: 115200_u32.Hz(),
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parity: Parity::None,
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stopbits: StopBits::One,
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baud8: false,
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wordsize: WordSize::Eight,
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enable_tx: true,
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enable_rx: true,
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}
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}
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}
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impl From<Hertz> for Config {
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fn from(value: Hertz) -> Self {
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Config::default().baudrate(value)
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}
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}
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//==================================================================================================
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// IRQ Definitions
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//==================================================================================================
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#[derive(Debug, Copy, Clone)]
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pub struct IrqContextTimeoutOrMaxSize {
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rx_idx: usize,
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mode: IrqReceptionMode,
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pub max_len: usize,
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}
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impl IrqContextTimeoutOrMaxSize {
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pub fn new(max_len: usize) -> Self {
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IrqContextTimeoutOrMaxSize {
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rx_idx: 0,
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max_len,
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mode: IrqReceptionMode::Idle,
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}
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}
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}
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impl IrqContextTimeoutOrMaxSize {
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pub fn reset(&mut self) {
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self.rx_idx = 0;
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self.mode = IrqReceptionMode::Idle;
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}
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}
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/// This struct is used to return the default IRQ handler result to the user
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#[derive(Debug, Default)]
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pub struct IrqResult {
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pub bytes_read: usize,
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pub errors: IrqUartError,
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}
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/// This struct is used to return the default IRQ handler result to the user
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#[derive(Debug, Default)]
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pub struct IrqResultMaxSizeTimeout {
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complete: bool,
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timeout: bool,
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pub errors: IrqUartError,
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pub bytes_read: usize,
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}
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impl IrqResultMaxSizeTimeout {
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pub fn new() -> Self {
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IrqResultMaxSizeTimeout {
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complete: false,
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timeout: false,
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errors: IrqUartError::default(),
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bytes_read: 0,
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}
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}
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}
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impl IrqResultMaxSizeTimeout {
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#[inline]
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pub fn error(&self) -> bool {
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if self.errors.overflow || self.errors.parity || self.errors.framing {
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return true;
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}
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false
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}
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#[inline]
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pub fn overflow_error(&self) -> bool {
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self.errors.overflow
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}
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#[inline]
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pub fn framing_error(&self) -> bool {
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self.errors.framing
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}
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#[inline]
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pub fn parity_error(&self) -> bool {
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self.errors.parity
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}
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#[inline]
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pub fn timeout(&self) -> bool {
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self.timeout
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}
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#[inline]
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pub fn complete(&self) -> bool {
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self.complete
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}
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}
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#[derive(Debug, PartialEq, Copy, Clone)]
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enum IrqReceptionMode {
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Idle,
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Pending,
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}
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//==================================================================================================
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// UART implementation
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//==================================================================================================
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/// Type erased variant of a UART. Can be created with the [Uart::downgrade] function.
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pub struct UartBase<Uart> {
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uart: Uart,
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tx: Tx<Uart>,
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rx: Rx<Uart>,
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}
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/// Serial abstraction. Entry point to create a new UART
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pub struct Uart<UartInstance, Pins> {
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inner: UartBase<UartInstance>,
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pins: Pins,
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}
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/// Serial receiver.
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///
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/// Can be created by using the [Uart::split] or [UartBase::split] API.
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pub struct Rx<Uart>(Uart);
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/// Serial transmitter
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///
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/// Can be created by using the [Uart::split] or [UartBase::split] API.
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pub struct Tx<Uart>(Uart);
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impl<Uart: Instance> Rx<Uart> {
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fn new(uart: Uart) -> Self {
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Self(uart)
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}
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}
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impl<Uart> Tx<Uart> {
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fn new(uart: Uart) -> Self {
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Self(uart)
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}
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}
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pub trait Instance: Deref<Target = uart_base::RegisterBlock> {
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const IDX: u8;
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const PERIPH_SEL: PeripheralSelect;
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const IRQ_RX: pac::Interrupt;
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const IRQ_TX: pac::Interrupt;
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/// Retrieve the peripheral structure.
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///
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/// # Safety
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///
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/// This circumvents the safety guarantees of the HAL.
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unsafe fn steal() -> Self;
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fn ptr() -> *const uart_base::RegisterBlock;
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}
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impl Instance for Uart0 {
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const IDX: u8 = 0;
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const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart0;
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const IRQ_RX: pac::Interrupt = pac::Interrupt::UART0_RX;
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const IRQ_TX: pac::Interrupt = pac::Interrupt::UART0_TX;
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unsafe fn steal() -> Self {
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pac::Peripherals::steal().uart0
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}
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fn ptr() -> *const uart_base::RegisterBlock {
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Uart0::ptr() as *const _
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}
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}
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impl Instance for Uart1 {
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const IDX: u8 = 1;
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const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart1;
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const IRQ_RX: pac::Interrupt = pac::Interrupt::UART1_RX;
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const IRQ_TX: pac::Interrupt = pac::Interrupt::UART1_TX;
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unsafe fn steal() -> Self {
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pac::Peripherals::steal().uart1
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}
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fn ptr() -> *const uart_base::RegisterBlock {
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Uart1::ptr() as *const _
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}
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}
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impl Instance for Uart2 {
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const IDX: u8 = 2;
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const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart2;
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const IRQ_RX: pac::Interrupt = pac::Interrupt::UART2_RX;
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const IRQ_TX: pac::Interrupt = pac::Interrupt::UART2_TX;
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unsafe fn steal() -> Self {
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pac::Peripherals::steal().uart2
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}
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fn ptr() -> *const uart_base::RegisterBlock {
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Uart2::ptr() as *const _
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}
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}
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impl<Uart: Instance> UartBase<Uart> {
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fn init(self, config: Config, clocks: &Clocks) -> Self {
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if Uart::IDX == 2 {
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self.init_with_clock_freq(config, clocks.apb1())
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} else {
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self.init_with_clock_freq(config, clocks.apb2())
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}
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}
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/// This function assumes that the peripheral clock was alredy enabled
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/// in the SYSCONFIG register
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fn init_with_clock_freq(self, config: Config, apb_clk: Hertz) -> Self {
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let baud_multiplier = match config.baud8 {
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false => 16,
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true => 8,
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};
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// This is the calculation: (64.0 * (x - integer_part as f32) + 0.5) as u32 without floating
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// point calculations.
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let frac = ((apb_clk.raw() % (config.baudrate.raw() * 16)) * 64
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+ (config.baudrate.raw() * 8))
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/ (config.baudrate.raw() * 16);
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// Calculations here are derived from chapter 10.4.4 (p.74) of the datasheet.
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let x = apb_clk.raw() as f32 / (config.baudrate.raw() * baud_multiplier) as f32;
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let integer_part = x as u32;
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self.uart.clkscale().write(|w| unsafe {
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w.frac().bits(frac as u8);
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w.int().bits(integer_part)
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});
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let (paren, pareven) = match config.parity {
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Parity::None => (false, false),
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Parity::Odd => (true, false),
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Parity::Even => (true, true),
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};
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let stopbits = match config.stopbits {
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StopBits::One => false,
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StopBits::Two => true,
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};
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let wordsize = config.wordsize as u8;
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let baud8 = config.baud8;
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self.uart.ctrl().write(|w| {
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w.paren().bit(paren);
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w.pareven().bit(pareven);
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w.stopbits().bit(stopbits);
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w.baud8().bit(baud8);
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unsafe { w.wordsize().bits(wordsize) }
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});
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let (txenb, rxenb) = (config.enable_tx, config.enable_rx);
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// Clear the FIFO
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self.uart.fifo_clr().write(|w| {
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w.rxfifo().set_bit();
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w.txfifo().set_bit()
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});
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self.uart.enable().write(|w| {
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w.rxenable().bit(rxenb);
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w.txenable().bit(txenb)
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});
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self
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}
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#[inline]
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pub fn enable_rx(&mut self) {
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self.uart.enable().modify(|_, w| w.rxenable().set_bit());
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}
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#[inline]
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pub fn disable_rx(&mut self) {
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self.uart.enable().modify(|_, w| w.rxenable().clear_bit());
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}
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#[inline]
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pub fn enable_tx(&mut self) {
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self.uart.enable().modify(|_, w| w.txenable().set_bit());
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}
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#[inline]
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pub fn disable_tx(&mut self) {
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self.uart.enable().modify(|_, w| w.txenable().clear_bit());
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}
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#[inline]
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pub fn clear_rx_fifo(&mut self) {
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self.uart.fifo_clr().write(|w| w.rxfifo().set_bit());
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}
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#[inline]
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pub fn clear_tx_fifo(&mut self) {
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self.uart.fifo_clr().write(|w| w.txfifo().set_bit());
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}
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pub fn listen(&self, event: Event) {
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self.uart.irq_enb().modify(|_, w| match event {
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Event::RxError => w.irq_rx_status().set_bit(),
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Event::RxFifoHalfFull => w.irq_rx().set_bit(),
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Event::RxTimeout => w.irq_rx_to().set_bit(),
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Event::TxEmpty => w.irq_tx_empty().set_bit(),
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Event::TxError => w.irq_tx_status().set_bit(),
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Event::TxFifoHalfFull => w.irq_tx().set_bit(),
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Event::TxCts => w.irq_tx_cts().set_bit(),
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});
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}
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pub fn unlisten(&self, event: Event) {
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self.uart.irq_enb().modify(|_, w| match event {
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Event::RxError => w.irq_rx_status().clear_bit(),
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Event::RxFifoHalfFull => w.irq_rx().clear_bit(),
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Event::RxTimeout => w.irq_rx_to().clear_bit(),
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Event::TxEmpty => w.irq_tx_empty().clear_bit(),
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Event::TxError => w.irq_tx_status().clear_bit(),
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Event::TxFifoHalfFull => w.irq_tx().clear_bit(),
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Event::TxCts => w.irq_tx_cts().clear_bit(),
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});
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}
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pub fn release(self) -> Uart {
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// Clear the FIFO
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self.uart.fifo_clr().write(|w| {
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w.rxfifo().set_bit();
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w.txfifo().set_bit()
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});
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self.uart.enable().write(|w| {
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w.rxenable().clear_bit();
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w.txenable().clear_bit()
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});
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disable_interrupt(Uart::IRQ_RX);
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self.uart
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}
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|
|
pub fn split(self) -> (Tx<Uart>, Rx<Uart>) {
|
|
(self.tx, self.rx)
|
|
}
|
|
}
|
|
|
|
impl<TxPinInst: TxPin<UartInstance>, RxPinInst: RxPin<UartInstance>, UartInstance: Instance>
|
|
Uart<UartInstance, (TxPinInst, RxPinInst)>
|
|
{
|
|
pub fn new(
|
|
uart: UartInstance,
|
|
pins: (TxPinInst, RxPinInst),
|
|
config: impl Into<Config>,
|
|
syscfg: &mut va416xx::Sysconfig,
|
|
clocks: &Clocks,
|
|
) -> Self {
|
|
crate::clock::enable_peripheral_clock(syscfg, UartInstance::PERIPH_SEL);
|
|
// This is done in the C HAL.
|
|
syscfg.assert_periph_reset_for_two_cycles(UartInstance::PERIPH_SEL);
|
|
Uart {
|
|
inner: UartBase {
|
|
uart,
|
|
tx: Tx::new(unsafe { UartInstance::steal() }),
|
|
rx: Rx::new(unsafe { UartInstance::steal() }),
|
|
},
|
|
pins,
|
|
}
|
|
.init(config.into(), clocks)
|
|
}
|
|
|
|
pub fn new_with_clock_freq(
|
|
uart: UartInstance,
|
|
pins: (TxPinInst, RxPinInst),
|
|
config: impl Into<Config>,
|
|
syscfg: &mut va416xx::Sysconfig,
|
|
clock: impl Into<Hertz>,
|
|
) -> Self {
|
|
crate::clock::enable_peripheral_clock(syscfg, UartInstance::PERIPH_SEL);
|
|
Uart {
|
|
inner: UartBase {
|
|
uart,
|
|
tx: Tx::new(unsafe { UartInstance::steal() }),
|
|
rx: Rx::new(unsafe { UartInstance::steal() }),
|
|
},
|
|
pins,
|
|
}
|
|
.init_with_clock_freq(config.into(), clock.into())
|
|
}
|
|
|
|
fn init(mut self, config: Config, clocks: &Clocks) -> Self {
|
|
self.inner = self.inner.init(config, clocks);
|
|
self
|
|
}
|
|
|
|
/// This function assumes that the peripheral clock was already enabled
|
|
/// in the SYSCONFIG register
|
|
#[allow(dead_code)]
|
|
fn init_with_clock_freq(mut self, config: Config, sys_clk: Hertz) -> Self {
|
|
self.inner = self.inner.init_with_clock_freq(config, sys_clk);
|
|
self
|
|
}
|
|
|
|
delegate::delegate! {
|
|
to self.inner {
|
|
#[inline]
|
|
pub fn enable_rx(&mut self);
|
|
#[inline]
|
|
pub fn disable_rx(&mut self);
|
|
|
|
#[inline]
|
|
pub fn enable_tx(&mut self);
|
|
#[inline]
|
|
pub fn disable_tx(&mut self);
|
|
|
|
#[inline]
|
|
pub fn clear_rx_fifo(&mut self);
|
|
#[inline]
|
|
pub fn clear_tx_fifo(&mut self);
|
|
|
|
#[inline]
|
|
pub fn listen(&self, event: Event);
|
|
#[inline]
|
|
pub fn unlisten(&self, event: Event);
|
|
#[inline]
|
|
pub fn split(self) -> (Tx<UartInstance>, Rx<UartInstance>);
|
|
}
|
|
}
|
|
|
|
pub fn downgrade(self) -> UartBase<UartInstance> {
|
|
UartBase {
|
|
uart: self.inner.uart,
|
|
tx: self.inner.tx,
|
|
rx: self.inner.rx,
|
|
}
|
|
}
|
|
|
|
pub fn release(self) -> (UartInstance, (TxPinInst, RxPinInst)) {
|
|
(self.inner.release(), self.pins)
|
|
}
|
|
}
|
|
|
|
impl<Uart: Instance> Rx<Uart> {
|
|
/// Direct access to the peripheral structure.
|
|
///
|
|
/// # Safety
|
|
///
|
|
/// You must ensure that only registers related to the operation of the RX side are used.
|
|
pub unsafe fn uart(&self) -> &Uart {
|
|
&self.0
|
|
}
|
|
|
|
#[inline]
|
|
pub fn clear_fifo(&self) {
|
|
self.0.fifo_clr().write(|w| w.rxfifo().set_bit());
|
|
}
|
|
|
|
#[inline]
|
|
pub fn enable(&mut self) {
|
|
self.0.enable().modify(|_, w| w.rxenable().set_bit());
|
|
}
|
|
|
|
#[inline]
|
|
pub fn disable(&mut self) {
|
|
self.0.enable().modify(|_, w| w.rxenable().clear_bit());
|
|
}
|
|
|
|
pub fn to_rx_with_irq(self) -> RxWithIrq<Uart> {
|
|
RxWithIrq(self)
|
|
}
|
|
|
|
pub fn release(self) -> Uart {
|
|
self.0
|
|
}
|
|
}
|
|
|
|
impl<Uart: Instance> Tx<Uart> {
|
|
/// Direct access to the peripheral structure.
|
|
///
|
|
/// # Safety
|
|
///
|
|
/// You must ensure that only registers related to the operation of the TX side are used.
|
|
pub unsafe fn uart(&self) -> &Uart {
|
|
&self.0
|
|
}
|
|
|
|
#[inline]
|
|
pub fn clear_fifo(&self) {
|
|
self.0.fifo_clr().write(|w| w.txfifo().set_bit());
|
|
}
|
|
|
|
#[inline]
|
|
pub fn enable(&mut self) {
|
|
self.0.enable().modify(|_, w| w.txenable().set_bit());
|
|
}
|
|
|
|
#[inline]
|
|
pub fn disable(&mut self) {
|
|
self.0.enable().modify(|_, w| w.txenable().clear_bit());
|
|
}
|
|
}
|
|
|
|
#[derive(Default, Debug)]
|
|
pub struct IrqUartError {
|
|
overflow: bool,
|
|
framing: bool,
|
|
parity: bool,
|
|
other: bool,
|
|
}
|
|
|
|
impl IrqUartError {
|
|
#[inline(always)]
|
|
pub fn overflow(&self) -> bool {
|
|
self.overflow
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn framing(&self) -> bool {
|
|
self.framing
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn parity(&self) -> bool {
|
|
self.parity
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn other(&self) -> bool {
|
|
self.other
|
|
}
|
|
}
|
|
|
|
impl IrqUartError {
|
|
#[inline(always)]
|
|
pub fn error(&self) -> bool {
|
|
self.overflow || self.framing || self.parity
|
|
}
|
|
}
|
|
|
|
#[derive(Debug)]
|
|
pub enum IrqError {
|
|
BufferTooShort { found: usize, expected: usize },
|
|
Uart(IrqUartError),
|
|
}
|
|
|
|
/// Serial receiver, using interrupts to offload reading to the hardware.
|
|
///
|
|
/// You can use [Rx::to_rx_with_irq] to convert a normal [Rx] structure into this structure.
|
|
/// This structure provides two distinct ways to read the UART RX using interrupts. It should
|
|
/// be noted that the interrupt service routine (ISR) still has to be provided by the user. However,
|
|
/// this structure provides API calls which can be used inside the ISRs to simplify the reading
|
|
/// of the UART.
|
|
///
|
|
/// 1. The first way simply empties the FIFO on an interrupt into a user provided buffer. You
|
|
/// can simply use [Self::start] to prepare the peripheral and then call the
|
|
/// [Self::irq_handler] in the interrupt service routine.
|
|
/// 2. The second way reads packets bounded by a maximum size or a baudtick based timeout. You
|
|
/// can use [Self::read_fixed_len_or_timeout_based_using_irq] to prepare the peripheral and
|
|
/// then call the [Self::irq_handler_max_size_or_timeout_based] in the interrupt service
|
|
/// routine. You have to call [Self::read_fixed_len_or_timeout_based_using_irq] in the ISR to
|
|
/// start reading the next packet.
|
|
pub struct RxWithIrq<Uart>(Rx<Uart>);
|
|
|
|
impl<Uart: Instance> RxWithIrq<Uart> {
|
|
/// This function should be called once at initialization time if the regular
|
|
/// [Self::irq_handler] is used to read the UART receiver to enable and start the receiver.
|
|
pub fn start(&mut self) {
|
|
self.0.enable();
|
|
self.enable_rx_irq_sources(true);
|
|
unsafe { enable_interrupt(Uart::IRQ_RX) };
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn uart(&self) -> &Uart {
|
|
&self.0 .0
|
|
}
|
|
|
|
/// This function is used together with the [Self::irq_handler_max_size_or_timeout_based]
|
|
/// function to read packets with a maximum size or variable sized packets by using the
|
|
/// receive timeout of the hardware.
|
|
///
|
|
/// This function should be called once at initialization to initiate the context state
|
|
/// and to [Self::start] the receiver. After that, it should be called after each
|
|
/// completed [Self::irq_handler_max_size_or_timeout_based] call to restart the reception
|
|
/// of a packet.
|
|
pub fn read_fixed_len_or_timeout_based_using_irq(
|
|
&mut self,
|
|
context: &mut IrqContextTimeoutOrMaxSize,
|
|
) -> Result<(), Error> {
|
|
if context.mode != IrqReceptionMode::Idle {
|
|
return Err(Error::TransferPending);
|
|
}
|
|
context.mode = IrqReceptionMode::Pending;
|
|
context.rx_idx = 0;
|
|
self.start();
|
|
Ok(())
|
|
}
|
|
|
|
#[inline]
|
|
fn enable_rx_irq_sources(&mut self, timeout: bool) {
|
|
self.uart().irq_enb().modify(|_, w| {
|
|
if timeout {
|
|
w.irq_rx_to().set_bit();
|
|
}
|
|
w.irq_rx_status().set_bit();
|
|
w.irq_rx().set_bit()
|
|
});
|
|
}
|
|
|
|
#[inline]
|
|
fn disable_rx_irq_sources(&mut self) {
|
|
self.uart().irq_enb().modify(|_, w| {
|
|
w.irq_rx_to().clear_bit();
|
|
w.irq_rx_status().clear_bit();
|
|
w.irq_rx().clear_bit()
|
|
});
|
|
}
|
|
|
|
pub fn cancel_transfer(&mut self) {
|
|
self.disable_rx_irq_sources();
|
|
self.0.clear_fifo();
|
|
}
|
|
|
|
/// This function should be called in the user provided UART interrupt handler.
|
|
///
|
|
/// It simply empties any bytes in the FIFO into the user provided buffer and returns the
|
|
/// result of the operation.
|
|
///
|
|
/// This function will not disable the RX interrupts, so you don't need to call any other
|
|
/// API after calling this function to continue emptying the FIFO.
|
|
pub fn irq_handler(&mut self, buf: &mut [u8; 16]) -> Result<IrqResult, IrqUartError> {
|
|
let mut result = IrqResult::default();
|
|
|
|
let irq_end = self.uart().irq_end().read();
|
|
let enb_status = self.uart().enable().read();
|
|
let rx_enabled = enb_status.rxenable().bit_is_set();
|
|
|
|
// Half-Full interrupt. We have a guaranteed amount of data we can read.
|
|
if irq_end.irq_rx().bit_is_set() {
|
|
let available_bytes = self.uart().rxfifoirqtrg().read().bits() as usize;
|
|
|
|
// If this interrupt bit is set, the trigger level is available at the very least.
|
|
// Read everything as fast as possible
|
|
for _ in 0..available_bytes {
|
|
buf[result.bytes_read] = (self.uart().data().read().bits() & 0xff) as u8;
|
|
result.bytes_read += 1;
|
|
}
|
|
}
|
|
|
|
// Timeout, empty the FIFO completely.
|
|
if irq_end.irq_rx_to().bit_is_set() {
|
|
loop {
|
|
// While there is data in the FIFO, write it into the reception buffer
|
|
let read_result = self.0.read();
|
|
if let Some(byte) = self.read_handler(&mut result.errors, &read_result) {
|
|
buf[result.bytes_read] = byte;
|
|
result.bytes_read += 1;
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// RX transfer not complete, check for RX errors
|
|
if rx_enabled {
|
|
self.check_for_errors(&mut result.errors);
|
|
}
|
|
|
|
// Clear the interrupt status bits
|
|
self.uart()
|
|
.irq_clr()
|
|
.write(|w| unsafe { w.bits(irq_end.bits()) });
|
|
Ok(result)
|
|
}
|
|
|
|
/// This function should be called in the user provided UART interrupt handler.
|
|
///
|
|
/// This function is used to read packets which either have a maximum size or variable sized
|
|
/// packet which are bounded by sufficient delays between them, triggering a hardware timeout.
|
|
///
|
|
/// If either the maximum number of packets have been read or a timeout occured, the transfer
|
|
/// will be deemed completed. The state information of the transfer is tracked in the
|
|
/// [IrqContextTimeoutOrMaxSize] structure.
|
|
///
|
|
/// If passed buffer is equal to or larger than the specified maximum length, an
|
|
/// [`Error::BufferTooShort`] will be returned
|
|
pub fn irq_handler_max_size_or_timeout_based(
|
|
&mut self,
|
|
context: &mut IrqContextTimeoutOrMaxSize,
|
|
buf: &mut [u8],
|
|
) -> Result<IrqResultMaxSizeTimeout, IrqError> {
|
|
if buf.len() < context.max_len {
|
|
return Err(IrqError::BufferTooShort {
|
|
found: buf.len(),
|
|
expected: context.max_len,
|
|
});
|
|
}
|
|
let mut result = IrqResultMaxSizeTimeout::default();
|
|
|
|
let irq_end = self.uart().irq_end().read();
|
|
let enb_status = self.uart().enable().read();
|
|
let rx_enabled = enb_status.rxenable().bit_is_set();
|
|
|
|
// Half-Full interrupt. We have a guaranteed amount of data we can read.
|
|
if irq_end.irq_rx().bit_is_set() {
|
|
// Determine the number of bytes to read, ensuring we leave 1 byte in the FIFO.
|
|
// We use this trick/hack because the timeout feature of the peripheral relies on data
|
|
// being in the RX FIFO. If data continues arriving, another half-full IRQ will fire.
|
|
// If not, the last byte(s) is/are emptied by the timeout interrupt.
|
|
let available_bytes = self.uart().rxfifoirqtrg().read().bits() as usize;
|
|
|
|
let bytes_to_read = core::cmp::min(
|
|
available_bytes.saturating_sub(1),
|
|
context.max_len - context.rx_idx,
|
|
);
|
|
|
|
// If this interrupt bit is set, the trigger level is available at the very least.
|
|
// Read everything as fast as possible
|
|
for _ in 0..bytes_to_read {
|
|
buf[context.rx_idx] = (self.uart().data().read().bits() & 0xff) as u8;
|
|
context.rx_idx += 1;
|
|
}
|
|
|
|
// On high-baudrates, data might be available immediately, and we possible have to
|
|
// read continuosly? Then again, the CPU should always be faster than that. I'd rather
|
|
// rely on the hardware firing another IRQ. I have not tried baudrates higher than
|
|
// 115200 so far.
|
|
}
|
|
// Timeout, empty the FIFO completely.
|
|
if irq_end.irq_rx_to().bit_is_set() {
|
|
// While there is data in the FIFO, write it into the reception buffer
|
|
loop {
|
|
if context.rx_idx == context.max_len {
|
|
break;
|
|
}
|
|
let read_result = self.0.read();
|
|
if let Some(byte) = self.read_handler(&mut result.errors, &read_result) {
|
|
buf[context.rx_idx] = byte;
|
|
context.rx_idx += 1;
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
self.irq_completion_handler_max_size_timeout(&mut result, context);
|
|
return Ok(result);
|
|
}
|
|
|
|
// RX transfer not complete, check for RX errors
|
|
if (context.rx_idx < context.max_len) && rx_enabled {
|
|
self.check_for_errors(&mut result.errors);
|
|
}
|
|
|
|
// Clear the interrupt status bits
|
|
self.uart()
|
|
.irq_clr()
|
|
.write(|w| unsafe { w.bits(irq_end.bits()) });
|
|
Ok(result)
|
|
}
|
|
|
|
fn read_handler(
|
|
&self,
|
|
errors: &mut IrqUartError,
|
|
read_res: &nb::Result<u8, Error>,
|
|
) -> Option<u8> {
|
|
match read_res {
|
|
Ok(byte) => Some(*byte),
|
|
Err(nb::Error::WouldBlock) => None,
|
|
Err(nb::Error::Other(e)) => {
|
|
match e {
|
|
Error::Overrun => {
|
|
errors.overflow = true;
|
|
}
|
|
Error::FramingError => {
|
|
errors.framing = true;
|
|
}
|
|
Error::ParityError => {
|
|
errors.parity = true;
|
|
}
|
|
_ => {
|
|
errors.other = true;
|
|
}
|
|
}
|
|
None
|
|
}
|
|
}
|
|
}
|
|
|
|
fn check_for_errors(&self, errors: &mut IrqUartError) {
|
|
// Read status register again, might have changed since reading received data
|
|
let rx_status = self.uart().rxstatus().read();
|
|
if rx_status.rxovr().bit_is_set() {
|
|
errors.overflow = true;
|
|
}
|
|
if rx_status.rxfrm().bit_is_set() {
|
|
errors.framing = true;
|
|
}
|
|
if rx_status.rxpar().bit_is_set() {
|
|
errors.parity = true;
|
|
}
|
|
}
|
|
|
|
fn irq_completion_handler_max_size_timeout(
|
|
&mut self,
|
|
res: &mut IrqResultMaxSizeTimeout,
|
|
context: &mut IrqContextTimeoutOrMaxSize,
|
|
) {
|
|
self.disable_rx_irq_sources();
|
|
self.0.disable();
|
|
res.bytes_read = context.rx_idx;
|
|
res.complete = true;
|
|
context.mode = IrqReceptionMode::Idle;
|
|
context.rx_idx = 0;
|
|
}
|
|
|
|
pub fn release(self) -> Uart {
|
|
self.0.release()
|
|
}
|
|
}
|
|
|
|
impl embedded_io::Error for Error {
|
|
fn kind(&self) -> embedded_io::ErrorKind {
|
|
embedded_io::ErrorKind::Other
|
|
}
|
|
}
|
|
|
|
impl embedded_hal_nb::serial::Error for Error {
|
|
fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
|
|
embedded_hal_nb::serial::ErrorKind::Other
|
|
}
|
|
}
|
|
|
|
impl<Uart> embedded_io::ErrorType for Rx<Uart> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<Uart> embedded_hal_nb::serial::ErrorType for Rx<Uart> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<Uart: Instance> embedded_hal_nb::serial::Read<u8> for Rx<Uart> {
|
|
fn read(&mut self) -> nb::Result<u8, Self::Error> {
|
|
let uart = unsafe { &(*Uart::ptr()) };
|
|
let status_reader = uart.rxstatus().read();
|
|
let err = if status_reader.rxovr().bit_is_set() {
|
|
Some(Error::Overrun)
|
|
} else if status_reader.rxfrm().bit_is_set() {
|
|
Some(Error::FramingError)
|
|
} else if status_reader.rxpar().bit_is_set() {
|
|
Some(Error::ParityError)
|
|
} else {
|
|
None
|
|
};
|
|
if let Some(err) = err {
|
|
// The status code is always related to the next bit for the framing
|
|
// and parity status bits. We have to read the DATA register
|
|
// so that the next status reflects the next DATA word
|
|
// For overrun error, we read as well to clear the peripheral
|
|
uart.data().read().bits();
|
|
Err(err.into())
|
|
} else if status_reader.rdavl().bit_is_set() {
|
|
let data = uart.data().read().bits();
|
|
Ok((data & 0xff) as u8)
|
|
} else {
|
|
Err(nb::Error::WouldBlock)
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<Uart: Instance> embedded_io::Read for Rx<Uart> {
|
|
fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
if buf.is_empty() {
|
|
return Ok(0);
|
|
}
|
|
|
|
for byte in buf.iter_mut() {
|
|
let w = nb::block!(<Self as embedded_hal_nb::serial::Read<u8>>::read(self))?;
|
|
*byte = w;
|
|
}
|
|
|
|
Ok(buf.len())
|
|
}
|
|
}
|
|
|
|
impl<Uart> embedded_io::ErrorType for Tx<Uart> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<Uart> embedded_hal_nb::serial::ErrorType for Tx<Uart> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<Uart: Instance> embedded_hal_nb::serial::Write<u8> for Tx<Uart> {
|
|
fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
|
|
let reader = unsafe { &(*Uart::ptr()) }.txstatus().read();
|
|
if reader.wrrdy().bit_is_clear() {
|
|
return Err(nb::Error::WouldBlock);
|
|
} else {
|
|
// DPARITY bit not supported yet
|
|
unsafe {
|
|
// NOTE(unsafe) atomic write to data register
|
|
// NOTE(write_volatile) 8-bit write that's not
|
|
// possible through the svd2rust API
|
|
(*Uart::ptr()).data().write(|w| w.bits(word as u32));
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn flush(&mut self) -> nb::Result<(), Self::Error> {
|
|
// SAFETY: Only TX related registers are used.
|
|
let reader = unsafe { &(*Uart::ptr()) }.txstatus().read();
|
|
if reader.wrbusy().bit_is_set() {
|
|
return Err(nb::Error::WouldBlock);
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
|
|
fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
if buf.is_empty() {
|
|
return Ok(0);
|
|
}
|
|
|
|
for byte in buf.iter() {
|
|
nb::block!(<Self as embedded_hal_nb::serial::Write<u8>>::write(
|
|
self, *byte
|
|
))?;
|
|
}
|
|
|
|
Ok(buf.len())
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
nb::block!(<Self as embedded_hal_nb::serial::Write<u8>>::flush(self))
|
|
}
|
|
}
|
|
|
|
impl<UartInstance> embedded_io::ErrorType for UartBase<UartInstance> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<UartInstance> embedded_hal_nb::serial::ErrorType for UartBase<UartInstance> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<Uart: Instance> embedded_hal_nb::serial::Read<u8> for UartBase<Uart> {
|
|
fn read(&mut self) -> nb::Result<u8, Self::Error> {
|
|
self.rx.read()
|
|
}
|
|
}
|
|
|
|
impl<Uart: Instance> embedded_hal_nb::serial::Write<u8> for UartBase<Uart> {
|
|
fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
|
|
self.tx.write(word)
|
|
}
|
|
|
|
fn flush(&mut self) -> nb::Result<(), Self::Error> {
|
|
self.tx.flush()
|
|
}
|
|
}
|