496 lines
25 KiB
Rust
496 lines
25 KiB
Rust
#[repr(C)]
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#[doc = "Register block"]
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pub struct RegisterBlock {
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rst_stat: RstStat,
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rst_cntl_rom: RstCntlRom,
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rst_cntl_ram0: RstCntlRam0,
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rst_cntl_ram1: RstCntlRam1,
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rom_prot: RomProt,
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rom_scrub: RomScrub,
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ram0_scrub: Ram0Scrub,
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ram1_scrub: Ram1Scrub,
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irq_enb: IrqEnb,
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irq_raw: IrqRaw,
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irq_end: IrqEnd,
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irq_clr: IrqClr,
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ram0_sbe: Ram0Sbe,
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ram1_sbe: Ram1Sbe,
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ram0_mbe: Ram0Mbe,
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ram1_mbe: Ram1Mbe,
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rom_sbe: RomSbe,
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rom_mbe: RomMbe,
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rom_retries: RomRetries,
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refresh_config_h: RefreshConfigH,
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tim_reset: TimReset,
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tim_clk_enable: TimClkEnable,
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peripheral_reset: PeripheralReset,
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peripheral_clk_enable: PeripheralClkEnable,
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spw_m4_ctrl: SpwM4Ctrl,
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pmu_ctrl: PmuCtrl,
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wakeup_cnt: WakeupCnt,
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ebi_cfg0: EbiCfg0,
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ebi_cfg1: EbiCfg1,
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ebi_cfg2: EbiCfg2,
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ebi_cfg3: EbiCfg3,
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analog_cntl: AnalogCntl,
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sw_clkdiv10: SwClkdiv10,
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refresh_config_l: RefreshConfigL,
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_reserved34: [u8; 0x0f48],
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dac0_cal: Dac0Cal,
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dac1_cal: Dac1Cal,
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adc_cal: AdcCal,
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bg_cal: BgCal,
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dreg_cal: DregCal,
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areg_cal: AregCal,
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hbo_cal: HboCal,
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ef_config: EfConfig,
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ef_id0: EfId0,
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ef_id1: EfId1,
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procid: Procid,
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perid: Perid,
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}
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impl RegisterBlock {
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#[doc = "0x00 - System Reset Status"]
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#[inline(always)]
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pub const fn rst_stat(&self) -> &RstStat {
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&self.rst_stat
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}
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#[doc = "0x04 - ROM Reset Control"]
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#[inline(always)]
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pub const fn rst_cntl_rom(&self) -> &RstCntlRom {
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&self.rst_cntl_rom
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}
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#[doc = "0x08 - RAM Reset Control"]
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#[inline(always)]
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pub const fn rst_cntl_ram0(&self) -> &RstCntlRam0 {
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&self.rst_cntl_ram0
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}
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#[doc = "0x0c - RAM Reset Control"]
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#[inline(always)]
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pub const fn rst_cntl_ram1(&self) -> &RstCntlRam1 {
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&self.rst_cntl_ram1
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}
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#[doc = "0x10 - ROM Protection Configuration"]
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#[inline(always)]
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pub const fn rom_prot(&self) -> &RomProt {
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&self.rom_prot
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}
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#[doc = "0x14 - ROM Scrub Period Configuration"]
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#[inline(always)]
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pub const fn rom_scrub(&self) -> &RomScrub {
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&self.rom_scrub
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}
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#[doc = "0x18 - RAM0 Scrub Period Configuration"]
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#[inline(always)]
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pub const fn ram0_scrub(&self) -> &Ram0Scrub {
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&self.ram0_scrub
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}
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#[doc = "0x1c - RAM1 Scrub Period Configuration"]
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#[inline(always)]
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pub const fn ram1_scrub(&self) -> &Ram1Scrub {
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&self.ram1_scrub
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}
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#[doc = "0x20 - Enable EDAC Error Interrupt Register"]
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#[inline(always)]
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pub const fn irq_enb(&self) -> &IrqEnb {
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&self.irq_enb
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}
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#[doc = "0x24 - Raw EDAC Error Interrupt Status"]
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#[inline(always)]
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pub const fn irq_raw(&self) -> &IrqRaw {
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&self.irq_raw
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}
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#[doc = "0x28 - Enabled EDAC Error Interrupt Status"]
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#[inline(always)]
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pub const fn irq_end(&self) -> &IrqEnd {
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&self.irq_end
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}
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#[doc = "0x2c - Clear EDAC Error Interrupt Status"]
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#[inline(always)]
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pub const fn irq_clr(&self) -> &IrqClr {
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&self.irq_clr
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}
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#[doc = "0x30 - Count of RAM0 EDAC Single Bit Errors"]
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#[inline(always)]
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pub const fn ram0_sbe(&self) -> &Ram0Sbe {
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&self.ram0_sbe
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}
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#[doc = "0x34 - Count of RAM1 EDAC Single Bit Errors"]
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#[inline(always)]
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pub const fn ram1_sbe(&self) -> &Ram1Sbe {
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&self.ram1_sbe
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}
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#[doc = "0x38 - Count of RAM0 EDAC Multi Bit Errors"]
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#[inline(always)]
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pub const fn ram0_mbe(&self) -> &Ram0Mbe {
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&self.ram0_mbe
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}
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#[doc = "0x3c - Count of RAM1 EDAC Multi Bit Errors"]
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#[inline(always)]
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pub const fn ram1_mbe(&self) -> &Ram1Mbe {
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&self.ram1_mbe
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}
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#[doc = "0x40 - Count of ROM EDAC Single Bit Errors"]
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#[inline(always)]
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pub const fn rom_sbe(&self) -> &RomSbe {
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&self.rom_sbe
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}
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#[doc = "0x44 - Count of ROM EDAC Multi Bit Errors"]
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#[inline(always)]
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pub const fn rom_mbe(&self) -> &RomMbe {
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&self.rom_mbe
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}
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#[doc = "0x48 - ROM BOOT Retry count"]
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#[inline(always)]
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pub const fn rom_retries(&self) -> &RomRetries {
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&self.rom_retries
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}
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#[doc = "0x4c - Register Refresh Rate for TMR registers"]
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#[inline(always)]
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pub const fn refresh_config_h(&self) -> &RefreshConfigH {
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&self.refresh_config_h
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}
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#[doc = "0x50 - TIM Reset Control"]
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#[inline(always)]
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pub const fn tim_reset(&self) -> &TimReset {
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&self.tim_reset
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}
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#[doc = "0x54 - TIM Enable Control"]
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#[inline(always)]
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pub const fn tim_clk_enable(&self) -> &TimClkEnable {
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&self.tim_clk_enable
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}
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#[doc = "0x58 - Peripheral Reset Control"]
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#[inline(always)]
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pub const fn peripheral_reset(&self) -> &PeripheralReset {
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&self.peripheral_reset
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}
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#[doc = "0x5c - Peripheral Enable Control"]
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#[inline(always)]
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pub const fn peripheral_clk_enable(&self) -> &PeripheralClkEnable {
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&self.peripheral_clk_enable
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}
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#[doc = "0x60 - SPW M4 control register"]
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#[inline(always)]
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pub const fn spw_m4_ctrl(&self) -> &SpwM4Ctrl {
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&self.spw_m4_ctrl
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}
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#[doc = "0x64 - PMU Control Register"]
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#[inline(always)]
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pub const fn pmu_ctrl(&self) -> &PmuCtrl {
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&self.pmu_ctrl
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}
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#[doc = "0x68 - Wakeup Control"]
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#[inline(always)]
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pub const fn wakeup_cnt(&self) -> &WakeupCnt {
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&self.wakeup_cnt
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}
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#[doc = "0x6c - EBI Config Register 0"]
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#[inline(always)]
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pub const fn ebi_cfg0(&self) -> &EbiCfg0 {
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&self.ebi_cfg0
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}
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#[doc = "0x70 - EBI Config Register 1"]
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#[inline(always)]
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pub const fn ebi_cfg1(&self) -> &EbiCfg1 {
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&self.ebi_cfg1
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}
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#[doc = "0x74 - EBI Config Register 2"]
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#[inline(always)]
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pub const fn ebi_cfg2(&self) -> &EbiCfg2 {
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&self.ebi_cfg2
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}
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#[doc = "0x78 - EBI Config Register 3"]
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#[inline(always)]
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pub const fn ebi_cfg3(&self) -> &EbiCfg3 {
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&self.ebi_cfg3
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}
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#[doc = "0x7c - Analog Control Register"]
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#[inline(always)]
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pub const fn analog_cntl(&self) -> &AnalogCntl {
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&self.analog_cntl
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}
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#[doc = "0x80 - Initial SpW Clock Divider Value"]
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#[inline(always)]
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pub const fn sw_clkdiv10(&self) -> &SwClkdiv10 {
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&self.sw_clkdiv10
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}
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#[doc = "0x84 - Register Refresh Rate for TMR registers"]
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#[inline(always)]
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pub const fn refresh_config_l(&self) -> &RefreshConfigL {
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&self.refresh_config_l
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}
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#[doc = "0xfd0 - DAC0 Calibration Register"]
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#[inline(always)]
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pub const fn dac0_cal(&self) -> &Dac0Cal {
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&self.dac0_cal
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}
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#[doc = "0xfd4 - DAC1 Calibration Register"]
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#[inline(always)]
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pub const fn dac1_cal(&self) -> &Dac1Cal {
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&self.dac1_cal
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}
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#[doc = "0xfd8 - ADC Calibration Register"]
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#[inline(always)]
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pub const fn adc_cal(&self) -> &AdcCal {
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&self.adc_cal
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}
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#[doc = "0xfdc - Bandgap Calibration Register"]
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#[inline(always)]
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pub const fn bg_cal(&self) -> &BgCal {
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&self.bg_cal
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}
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#[doc = "0xfe0 - Digital LDO Regulator Calibration Register"]
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#[inline(always)]
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pub const fn dreg_cal(&self) -> &DregCal {
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&self.dreg_cal
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}
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#[doc = "0xfe4 - Analog LDO Regulator Calibration Register"]
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#[inline(always)]
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pub const fn areg_cal(&self) -> &AregCal {
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&self.areg_cal
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}
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#[doc = "0xfe8 - Heart Beat OSC Calibration Register"]
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#[inline(always)]
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pub const fn hbo_cal(&self) -> &HboCal {
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&self.hbo_cal
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}
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#[doc = "0xfec - EFuse Config Register"]
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#[inline(always)]
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pub const fn ef_config(&self) -> &EfConfig {
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&self.ef_config
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}
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#[doc = "0xff0 - EFuse ID0 Register"]
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#[inline(always)]
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pub const fn ef_id0(&self) -> &EfId0 {
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&self.ef_id0
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}
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#[doc = "0xff4 - EFuse ID1 Register"]
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#[inline(always)]
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pub const fn ef_id1(&self) -> &EfId1 {
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&self.ef_id1
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}
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#[doc = "0xff8 - Processor ID Register"]
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#[inline(always)]
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pub const fn procid(&self) -> &Procid {
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&self.procid
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}
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#[doc = "0xffc - Peripheral ID Register"]
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#[inline(always)]
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pub const fn perid(&self) -> &Perid {
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&self.perid
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}
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}
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#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`]
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module"]
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#[doc(alias = "RST_STAT")]
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pub type RstStat = crate::Reg<rst_stat::RstStatSpec>;
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#[doc = "System Reset Status"]
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pub mod rst_stat;
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pub use rst_stat as rst_cntl_rom;
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pub use rst_stat as rst_cntl_ram0;
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pub use rst_stat as rst_cntl_ram1;
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pub use RstStat as RstCntlRom;
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pub use RstStat as RstCntlRam0;
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pub use RstStat as RstCntlRam1;
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#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`]
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module"]
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#[doc(alias = "ROM_PROT")]
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pub type RomProt = crate::Reg<rom_prot::RomProtSpec>;
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#[doc = "ROM Protection Configuration"]
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pub mod rom_prot;
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#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`]
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module"]
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#[doc(alias = "ROM_SCRUB")]
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pub type RomScrub = crate::Reg<rom_scrub::RomScrubSpec>;
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#[doc = "ROM Scrub Period Configuration"]
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pub mod rom_scrub;
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pub use rom_scrub as ram0_scrub;
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pub use rom_scrub as ram1_scrub;
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pub use RomScrub as Ram0Scrub;
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pub use RomScrub as Ram1Scrub;
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#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
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module"]
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#[doc(alias = "IRQ_ENB")]
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pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
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#[doc = "Enable EDAC Error Interrupt Register"]
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pub mod irq_enb;
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pub use irq_enb as irq_raw;
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pub use irq_enb as irq_end;
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pub use irq_enb as irq_clr;
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pub use IrqEnb as IrqRaw;
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pub use IrqEnb as IrqEnd;
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pub use IrqEnb as IrqClr;
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#[doc = "RAM0_SBE (rw) register accessor: Count of RAM0 EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram0_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram0_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram0_sbe`]
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module"]
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#[doc(alias = "RAM0_SBE")]
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pub type Ram0Sbe = crate::Reg<ram0_sbe::Ram0SbeSpec>;
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#[doc = "Count of RAM0 EDAC Single Bit Errors"]
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pub mod ram0_sbe;
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pub use ram0_sbe as ram1_sbe;
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pub use Ram0Sbe as Ram1Sbe;
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#[doc = "RAM0_MBE (rw) register accessor: Count of RAM0 EDAC Multi Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram0_mbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram0_mbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram0_mbe`]
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module"]
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#[doc(alias = "RAM0_MBE")]
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pub type Ram0Mbe = crate::Reg<ram0_mbe::Ram0MbeSpec>;
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#[doc = "Count of RAM0 EDAC Multi Bit Errors"]
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pub mod ram0_mbe;
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pub use ram0_mbe as ram1_mbe;
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pub use ram0_mbe as rom_mbe;
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pub use ram0_sbe as rom_sbe;
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pub use Ram0Mbe as Ram1Mbe;
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pub use Ram0Mbe as RomMbe;
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pub use Ram0Sbe as RomSbe;
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#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`]
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module"]
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#[doc(alias = "ROM_RETRIES")]
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pub type RomRetries = crate::Reg<rom_retries::RomRetriesSpec>;
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#[doc = "ROM BOOT Retry count"]
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pub mod rom_retries;
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#[doc = "REFRESH_CONFIG_H (rw) register accessor: Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config_h`]
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module"]
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#[doc(alias = "REFRESH_CONFIG_H")]
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pub type RefreshConfigH = crate::Reg<refresh_config_h::RefreshConfigHSpec>;
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#[doc = "Register Refresh Rate for TMR registers"]
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pub mod refresh_config_h;
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#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`]
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module"]
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#[doc(alias = "TIM_RESET")]
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pub type TimReset = crate::Reg<tim_reset::TimResetSpec>;
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#[doc = "TIM Reset Control"]
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pub mod tim_reset;
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#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`]
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module"]
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#[doc(alias = "TIM_CLK_ENABLE")]
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pub type TimClkEnable = crate::Reg<tim_clk_enable::TimClkEnableSpec>;
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#[doc = "TIM Enable Control"]
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pub mod tim_clk_enable;
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#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`]
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module"]
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#[doc(alias = "PERIPHERAL_RESET")]
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pub type PeripheralReset = crate::Reg<peripheral_reset::PeripheralResetSpec>;
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#[doc = "Peripheral Reset Control"]
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pub mod peripheral_reset;
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pub use peripheral_reset as peripheral_clk_enable;
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pub use PeripheralReset as PeripheralClkEnable;
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#[doc = "SPW_M4_CTRL (rw) register accessor: SPW M4 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spw_m4_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spw_m4_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spw_m4_ctrl`]
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module"]
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#[doc(alias = "SPW_M4_CTRL")]
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pub type SpwM4Ctrl = crate::Reg<spw_m4_ctrl::SpwM4CtrlSpec>;
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#[doc = "SPW M4 control register"]
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pub mod spw_m4_ctrl;
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#[doc = "PMU_CTRL (rw) register accessor: PMU Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pmu_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmu_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmu_ctrl`]
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module"]
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#[doc(alias = "PMU_CTRL")]
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pub type PmuCtrl = crate::Reg<pmu_ctrl::PmuCtrlSpec>;
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#[doc = "PMU Control Register"]
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pub mod pmu_ctrl;
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#[doc = "WAKEUP_CNT (rw) register accessor: Wakeup Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeup_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeup_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup_cnt`]
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module"]
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#[doc(alias = "WAKEUP_CNT")]
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pub type WakeupCnt = crate::Reg<wakeup_cnt::WakeupCntSpec>;
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#[doc = "Wakeup Control"]
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pub mod wakeup_cnt;
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#[doc = "EBI_CFG0 (rw) register accessor: EBI Config Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ebi_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ebi_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ebi_cfg0`]
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module"]
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#[doc(alias = "EBI_CFG0")]
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pub type EbiCfg0 = crate::Reg<ebi_cfg0::EbiCfg0Spec>;
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#[doc = "EBI Config Register 0"]
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pub mod ebi_cfg0;
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pub use ebi_cfg0 as ebi_cfg1;
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pub use ebi_cfg0 as ebi_cfg2;
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pub use ebi_cfg0 as ebi_cfg3;
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pub use EbiCfg0 as EbiCfg1;
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pub use EbiCfg0 as EbiCfg2;
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pub use EbiCfg0 as EbiCfg3;
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#[doc = "ANALOG_CNTL (rw) register accessor: Analog Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`analog_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`analog_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@analog_cntl`]
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module"]
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#[doc(alias = "ANALOG_CNTL")]
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pub type AnalogCntl = crate::Reg<analog_cntl::AnalogCntlSpec>;
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#[doc = "Analog Control Register"]
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pub mod analog_cntl;
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#[doc = "SW_CLKDIV10 (rw) register accessor: Initial SpW Clock Divider Value\n\nYou can [`read`](crate::Reg::read) this register and get [`sw_clkdiv10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_clkdiv10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_clkdiv10`]
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module"]
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#[doc(alias = "SW_CLKDIV10")]
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pub type SwClkdiv10 = crate::Reg<sw_clkdiv10::SwClkdiv10Spec>;
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#[doc = "Initial SpW Clock Divider Value"]
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pub mod sw_clkdiv10;
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#[doc = "REFRESH_CONFIG_L (rw) register accessor: Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config_l`]
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module"]
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#[doc(alias = "REFRESH_CONFIG_L")]
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pub type RefreshConfigL = crate::Reg<refresh_config_l::RefreshConfigLSpec>;
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#[doc = "Register Refresh Rate for TMR registers"]
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pub mod refresh_config_l;
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#[doc = "DAC0_CAL (r) register accessor: DAC0 Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dac0_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac0_cal`]
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module"]
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#[doc(alias = "DAC0_CAL")]
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pub type Dac0Cal = crate::Reg<dac0_cal::Dac0CalSpec>;
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#[doc = "DAC0 Calibration Register"]
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pub mod dac0_cal;
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#[doc = "DAC1_CAL (r) register accessor: DAC1 Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dac1_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac1_cal`]
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module"]
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#[doc(alias = "DAC1_CAL")]
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pub type Dac1Cal = crate::Reg<dac1_cal::Dac1CalSpec>;
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#[doc = "DAC1 Calibration Register"]
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pub mod dac1_cal;
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#[doc = "ADC_CAL (r) register accessor: ADC Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`adc_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc_cal`]
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module"]
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#[doc(alias = "ADC_CAL")]
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pub type AdcCal = crate::Reg<adc_cal::AdcCalSpec>;
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#[doc = "ADC Calibration Register"]
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pub mod adc_cal;
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#[doc = "BG_CAL (r) register accessor: Bandgap Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`bg_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bg_cal`]
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module"]
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#[doc(alias = "BG_CAL")]
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pub type BgCal = crate::Reg<bg_cal::BgCalSpec>;
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#[doc = "Bandgap Calibration Register"]
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pub mod bg_cal;
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#[doc = "DREG_CAL (r) register accessor: Digital LDO Regulator Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dreg_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dreg_cal`]
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module"]
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#[doc(alias = "DREG_CAL")]
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pub type DregCal = crate::Reg<dreg_cal::DregCalSpec>;
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#[doc = "Digital LDO Regulator Calibration Register"]
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pub mod dreg_cal;
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#[doc = "AREG_CAL (r) register accessor: Analog LDO Regulator Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`areg_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@areg_cal`]
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module"]
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#[doc(alias = "AREG_CAL")]
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pub type AregCal = crate::Reg<areg_cal::AregCalSpec>;
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#[doc = "Analog LDO Regulator Calibration Register"]
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pub mod areg_cal;
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#[doc = "HBO_CAL (r) register accessor: Heart Beat OSC Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hbo_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hbo_cal`]
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module"]
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#[doc(alias = "HBO_CAL")]
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pub type HboCal = crate::Reg<hbo_cal::HboCalSpec>;
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#[doc = "Heart Beat OSC Calibration Register"]
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pub mod hbo_cal;
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#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`]
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module"]
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#[doc(alias = "EF_CONFIG")]
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pub type EfConfig = crate::Reg<ef_config::EfConfigSpec>;
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#[doc = "EFuse Config Register"]
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pub mod ef_config;
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#[doc = "EF_ID0 (r) register accessor: EFuse ID0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id0`]
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module"]
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#[doc(alias = "EF_ID0")]
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pub type EfId0 = crate::Reg<ef_id0::EfId0Spec>;
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#[doc = "EFuse ID0 Register"]
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pub mod ef_id0;
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#[doc = "EF_ID1 (r) register accessor: EFuse ID1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id1`]
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module"]
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#[doc(alias = "EF_ID1")]
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pub type EfId1 = crate::Reg<ef_id1::EfId1Spec>;
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#[doc = "EFuse ID1 Register"]
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pub mod ef_id1;
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#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`]
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module"]
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#[doc(alias = "PROCID")]
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pub type Procid = crate::Reg<procid::ProcidSpec>;
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#[doc = "Processor ID Register"]
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pub mod procid;
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#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
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module"]
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#[doc(alias = "PERID")]
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pub type Perid = crate::Reg<perid::PeridSpec>;
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#[doc = "Peripheral ID Register"]
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pub mod perid;
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