Robin Mueller
935ee9dbb1
Changed: - Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) which is mostly re-exported in this crate. - Overhaul and simplification of several HAL APIs. The system configuration and IRQ router peripheral instance generally does not need to be passed to HAL API anymore. - All HAL drivers are now type erased. The constructors will still expect and consume the PAC singleton component for resource management purposes, but are not cached anymore. - Refactoring of GPIO library to be more inline with embassy GPIO API. Added: - I2C clock timeout feature support.
108 lines
2.8 KiB
Rust
108 lines
2.8 KiB
Rust
//! # API for the Watchdog peripheral
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//!
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//! ## Examples
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//!
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//! - [Watchdog simple example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/wdt.rs)
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use vorago_shared_periphs::{
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enable_peripheral_clock, reset_peripheral_for_cycles, PeripheralSelect,
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};
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use crate::time::Hertz;
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use crate::{clock::Clocks, pac};
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use crate::{disable_nvic_interrupt, enable_nvic_interrupt};
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pub const WDT_UNLOCK_VALUE: u32 = 0x1ACC_E551;
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/// Watchdog peripheral driver.
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pub struct Wdt {
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clock_freq: Hertz,
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wdt: pac::WatchDog,
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}
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/// Type alias for backwards compatibility
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#[deprecated(since = "0.2.0", note = "Please use `Wdt` instead")]
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pub type WdtController = Wdt;
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/// Enable the watchdog interrupt
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///
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/// # Safety
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///
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/// This function is `unsafe` because it can break mask-based critical sections.
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#[inline]
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pub unsafe fn enable_wdt_interrupts() {
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enable_nvic_interrupt(pac::Interrupt::WATCHDOG)
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}
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#[inline]
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pub fn disable_wdt_interrupts() {
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disable_nvic_interrupt(pac::Interrupt::WATCHDOG)
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}
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impl Wdt {
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pub fn new(wdt: pac::WatchDog, clocks: &Clocks, wdt_freq_ms: u32) -> Self {
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Self::start(wdt, clocks, wdt_freq_ms)
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}
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pub fn start(wdt: pac::WatchDog, clocks: &Clocks, wdt_freq_ms: u32) -> Self {
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enable_peripheral_clock(PeripheralSelect::Watchdog);
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reset_peripheral_for_cycles(PeripheralSelect::Watchdog, 2);
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let wdt_clock = clocks.apb2();
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let mut wdt_ctrl = Self {
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clock_freq: wdt_clock,
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wdt,
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};
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wdt_ctrl.set_freq(wdt_freq_ms);
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wdt_ctrl.wdt.wdogcontrol().write(|w| w.inten().set_bit());
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wdt_ctrl.feed();
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// Unmask the watchdog interrupt
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unsafe {
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enable_wdt_interrupts();
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}
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wdt_ctrl
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}
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#[inline]
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pub fn set_freq(&mut self, freq_ms: u32) {
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let counter = (self.clock_freq.raw() / 1000) * freq_ms;
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self.wdt.wdogload().write(|w| unsafe { w.bits(counter) });
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}
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#[inline]
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pub fn disable_reset(&mut self) {
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self.wdt.wdogcontrol().modify(|_, w| w.resen().clear_bit());
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}
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#[inline]
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pub fn enable_reset(&mut self) {
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self.wdt.wdogcontrol().modify(|_, w| w.resen().set_bit());
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}
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#[inline]
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pub fn counter(&self) -> u32 {
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self.wdt.wdogvalue().read().bits()
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}
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#[inline]
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pub fn feed(&self) {
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self.wdt.wdogintclr().write(|w| unsafe { w.bits(1) });
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}
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#[inline]
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pub fn lock(&self) {
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self.wdt.wdoglock().write(|w| unsafe { w.bits(0) });
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}
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#[inline]
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pub fn unlock(&self) {
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self.wdt
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.wdoglock()
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.write(|w| unsafe { w.bits(WDT_UNLOCK_VALUE) });
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}
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#[inline]
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pub fn is_locked(&self) -> bool {
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self.wdt.wdogload().read().bits() == 1
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}
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}
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