From 6145f4163f234e8e6a803a7536a4171fb325fd9c Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Sun, 21 Nov 2021 20:06:32 +0100 Subject: [PATCH] first building version of the PAC --- Cargo.toml | 16 + build.rs | 16 + device.x | 197 ++ gen-helper.sh | 21 + src/adc.rs | 65 + src/adc/ctrl.rs | 328 +++ src/adc/fifo_clr.rs | 72 + src/adc/fifo_data.rs | 73 + src/adc/irq_clr.rs | 153 ++ src/adc/irq_enb.rs | 395 ++++ src/adc/irq_end.rs | 173 ++ src/adc/irq_raw.rs | 173 ++ src/adc/perid.rs | 31 + src/adc/rxfifoirqtrg.rs | 103 + src/adc/status.rs | 73 + src/can0.rs | 856 ++++++++ src/can0/bmskb.rs | 254 +++ src/can0/bmskx.rs | 158 ++ src/can0/canec.rs | 140 ++ src/can0/cediag.rs | 375 ++++ src/can0/cgcr.rs | 630 ++++++ src/can0/cicen.rs | 150 ++ src/can0/ciclr.rs | 150 ++ src/can0/cien.rs | 150 ++ src/can0/cipnd.rs | 150 ++ src/can0/cnstat_cmb0.rs | 177 ++ src/can0/cnstat_cmb1.rs | 177 ++ src/can0/cnstat_cmb10.rs | 177 ++ src/can0/cnstat_cmb11.rs | 177 ++ src/can0/cnstat_cmb12.rs | 177 ++ src/can0/cnstat_cmb13.rs | 177 ++ src/can0/cnstat_cmb14.rs | 177 ++ src/can0/cnstat_cmb2.rs | 177 ++ src/can0/cnstat_cmb3.rs | 177 ++ src/can0/cnstat_cmb4.rs | 177 ++ src/can0/cnstat_cmb5.rs | 177 ++ src/can0/cnstat_cmb6.rs | 177 ++ src/can0/cnstat_cmb7.rs | 177 ++ src/can0/cnstat_cmb8.rs | 177 ++ src/can0/cnstat_cmb9.rs | 177 ++ src/can0/cnstat_hcmb.rs | 177 ++ src/can0/cstpnd.rs | 187 ++ src/can0/ctim.rs | 214 ++ src/can0/ctmr.rs | 53 + src/can0/data0_cmb0.rs | 140 ++ src/can0/data0_cmb1.rs | 140 ++ src/can0/data0_cmb10.rs | 140 ++ src/can0/data0_cmb11.rs | 140 ++ src/can0/data0_cmb12.rs | 140 ++ src/can0/data0_cmb13.rs | 140 ++ src/can0/data0_cmb14.rs | 140 ++ src/can0/data0_cmb2.rs | 140 ++ src/can0/data0_cmb3.rs | 140 ++ src/can0/data0_cmb4.rs | 140 ++ src/can0/data0_cmb5.rs | 140 ++ src/can0/data0_cmb6.rs | 140 ++ src/can0/data0_cmb7.rs | 140 ++ src/can0/data0_cmb8.rs | 140 ++ src/can0/data0_cmb9.rs | 140 ++ src/can0/data0_hcmb.rs | 140 ++ src/can0/data1_cmb0.rs | 140 ++ src/can0/data1_cmb1.rs | 140 ++ src/can0/data1_cmb10.rs | 140 ++ src/can0/data1_cmb11.rs | 140 ++ src/can0/data1_cmb12.rs | 140 ++ src/can0/data1_cmb13.rs | 140 ++ src/can0/data1_cmb14.rs | 140 ++ src/can0/data1_cmb2.rs | 140 ++ src/can0/data1_cmb3.rs | 140 ++ src/can0/data1_cmb4.rs | 140 ++ src/can0/data1_cmb5.rs | 140 ++ src/can0/data1_cmb6.rs | 140 ++ src/can0/data1_cmb7.rs | 140 ++ src/can0/data1_cmb8.rs | 140 ++ src/can0/data1_cmb9.rs | 140 ++ src/can0/data1_hcmb.rs | 140 ++ src/can0/data2_cmb0.rs | 140 ++ src/can0/data2_cmb1.rs | 140 ++ src/can0/data2_cmb10.rs | 140 ++ src/can0/data2_cmb11.rs | 140 ++ src/can0/data2_cmb12.rs | 140 ++ src/can0/data2_cmb13.rs | 140 ++ src/can0/data2_cmb14.rs | 140 ++ src/can0/data2_cmb2.rs | 140 ++ src/can0/data2_cmb3.rs | 140 ++ src/can0/data2_cmb4.rs | 140 ++ src/can0/data2_cmb5.rs | 140 ++ src/can0/data2_cmb6.rs | 140 ++ src/can0/data2_cmb7.rs | 140 ++ src/can0/data2_cmb8.rs | 140 ++ src/can0/data2_cmb9.rs | 140 ++ src/can0/data2_hcmb.rs | 140 ++ src/can0/data3_cmb0.rs | 140 ++ src/can0/data3_cmb1.rs | 140 ++ src/can0/data3_cmb10.rs | 140 ++ src/can0/data3_cmb11.rs | 140 ++ src/can0/data3_cmb12.rs | 140 ++ src/can0/data3_cmb13.rs | 140 ++ src/can0/data3_cmb14.rs | 140 ++ src/can0/data3_cmb2.rs | 140 ++ src/can0/data3_cmb3.rs | 140 ++ src/can0/data3_cmb4.rs | 140 ++ src/can0/data3_cmb5.rs | 140 ++ src/can0/data3_cmb6.rs | 140 ++ src/can0/data3_cmb7.rs | 140 ++ src/can0/data3_cmb8.rs | 140 ++ src/can0/data3_cmb9.rs | 140 ++ src/can0/data3_hcmb.rs | 140 ++ src/can0/gmskb.rs | 254 +++ src/can0/gmskx.rs | 158 ++ src/can0/id0_cmb0.rs | 103 + src/can0/id0_cmb1.rs | 103 + src/can0/id0_cmb10.rs | 103 + src/can0/id0_cmb11.rs | 103 + src/can0/id0_cmb12.rs | 103 + src/can0/id0_cmb13.rs | 103 + src/can0/id0_cmb14.rs | 103 + src/can0/id0_cmb2.rs | 103 + src/can0/id0_cmb3.rs | 103 + src/can0/id0_cmb4.rs | 103 + src/can0/id0_cmb5.rs | 103 + src/can0/id0_cmb6.rs | 103 + src/can0/id0_cmb7.rs | 103 + src/can0/id0_cmb8.rs | 103 + src/can0/id0_cmb9.rs | 103 + src/can0/id0_hcmb.rs | 103 + src/can0/id1_cmb0.rs | 103 + src/can0/id1_cmb1.rs | 103 + src/can0/id1_cmb10.rs | 103 + src/can0/id1_cmb11.rs | 103 + src/can0/id1_cmb12.rs | 103 + src/can0/id1_cmb13.rs | 103 + src/can0/id1_cmb14.rs | 103 + src/can0/id1_cmb2.rs | 103 + src/can0/id1_cmb3.rs | 103 + src/can0/id1_cmb4.rs | 103 + src/can0/id1_cmb5.rs | 103 + src/can0/id1_cmb6.rs | 103 + src/can0/id1_cmb7.rs | 103 + src/can0/id1_cmb8.rs | 103 + src/can0/id1_cmb9.rs | 103 + src/can0/id1_hcmb.rs | 103 + src/can0/tstp_cmb0.rs | 103 + src/can0/tstp_cmb1.rs | 103 + src/can0/tstp_cmb10.rs | 103 + src/can0/tstp_cmb11.rs | 103 + src/can0/tstp_cmb12.rs | 103 + src/can0/tstp_cmb13.rs | 103 + src/can0/tstp_cmb14.rs | 103 + src/can0/tstp_cmb2.rs | 103 + src/can0/tstp_cmb3.rs | 103 + src/can0/tstp_cmb4.rs | 103 + src/can0/tstp_cmb5.rs | 103 + src/can0/tstp_cmb6.rs | 103 + src/can0/tstp_cmb7.rs | 103 + src/can0/tstp_cmb8.rs | 103 + src/can0/tstp_cmb9.rs | 103 + src/can0/tstp_hcmb.rs | 103 + src/clkgen.rs | 22 + src/clkgen/ctrl0.rs | 607 ++++++ src/clkgen/ctrl1.rs | 338 +++ src/clkgen/stat.rs | 113 + src/dac0.rs | 71 + src/dac0/ctrl0.rs | 160 ++ src/dac0/ctrl1.rs | 150 ++ src/dac0/fifo_clr.rs | 72 + src/dac0/fifo_data.rs | 81 + src/dac0/irq_clr.rs | 153 ++ src/dac0/irq_enb.rs | 395 ++++ src/dac0/irq_end.rs | 173 ++ src/dac0/irq_raw.rs | 173 ++ src/dac0/perid.rs | 31 + src/dac0/status.rs | 73 + src/dac0/txfifoirqtrg.rs | 103 + src/dma.rs | 223 ++ src/dma/alt_ctrl_base_ptr.rs | 103 + src/dma/cfg.rs | 62 + src/dma/chnl_enable_clr.rs | 254 +++ src/dma/chnl_enable_set.rs | 254 +++ src/dma/chnl_pri_alt_clr.rs | 254 +++ src/dma/chnl_pri_alt_set.rs | 254 +++ src/dma/chnl_priority_clr.rs | 153 ++ src/dma/chnl_priority_set.rs | 254 +++ src/dma/chnl_req_mask_clr.rs | 254 +++ src/dma/chnl_req_mask_set.rs | 254 +++ src/dma/chnl_sw_request.rs | 153 ++ src/dma/chnl_useburst_clr.rs | 254 +++ src/dma/chnl_useburst_set.rs | 254 +++ src/dma/ctrl_base_ptr.rs | 103 + src/dma/dma_active_clr.rs | 254 +++ src/dma/dma_active_set.rs | 254 +++ src/dma/dma_done_clr.rs | 254 +++ src/dma/dma_done_set.rs | 254 +++ src/dma/dma_req_status.rs | 254 +++ src/dma/dma_sreq_status.rs | 254 +++ src/dma/err_clr.rs | 113 + src/dma/err_set.rs | 53 + src/dma/integration_cfg.rs | 113 + src/dma/periph_id_0.rs | 103 + src/dma/periph_id_1.rs | 73 + src/dma/periph_id_2.rs | 187 ++ src/dma/periph_id_3.rs | 103 + src/dma/periph_id_4.rs | 140 ++ src/dma/primecell_id_0.rs | 103 + src/dma/primecell_id_1.rs | 103 + src/dma/primecell_id_2.rs | 103 + src/dma/primecell_id_3.rs | 103 + src/dma/stall_status.rs | 53 + src/dma/status.rs | 113 + src/dma/waitonreq_status.rs | 113 + src/eth.rs | 585 +++++ src/eth/dma_ahb_status.rs | 113 + src/eth/dma_bus_mode.rs | 674 ++++++ src/eth/dma_curr_rx_bufr_addr.rs | 103 + src/eth/dma_curr_rx_desc.rs | 103 + src/eth/dma_curr_tx_bufr_addr.rs | 103 + src/eth/dma_curr_tx_desc.rs | 103 + src/eth/dma_intr_en.rs | 771 +++++++ src/eth/dma_miss_over_counter.rs | 234 ++ src/eth/dma_oper_mode.rs | 731 +++++++ src/eth/dma_rx_desc_list_addr.rs | 103 + src/eth/dma_rx_intr_wdog_timer.rs | 103 + src/eth/dma_rx_poll_demand.rs | 103 + src/eth/dma_status.rs | 433 ++++ src/eth/dma_tx_desc_list_addr.rs | 103 + src/eth/dma_tx_poll_demand.rs | 103 + src/eth/mac_addr_h.rs | 106 + src/eth/mac_addr_l.rs | 86 + src/eth/mac_config.rs | 929 ++++++++ src/eth/mac_debug.rs | 273 +++ src/eth/mac_flow_ctrl.rs | 375 ++++ src/eth/mac_frame_fltr.rs | 667 ++++++ src/eth/mac_gmii_addr.rs | 271 +++ src/eth/mac_gmii_data.rs | 103 + src/eth/mac_intr_mask.rs | 113 + src/eth/mac_intr_stat.rs | 133 ++ src/eth/mac_vlan_tag.rs | 244 +++ src/eth/mac_wdog_to.rs | 150 ++ src/eth/mmc_cntrl.rs | 395 ++++ src/eth/mmc_intr_mask_rx.rs | 1288 +++++++++++ src/eth/mmc_intr_mask_tx.rs | 1288 +++++++++++ src/eth/mmc_intr_rx.rs | 1288 +++++++++++ src/eth/mmc_intr_tx.rs | 1288 +++++++++++ src/eth/rx1024maxoct_gb.rs | 53 + src/eth/rx128to255oct_gb.rs | 53 + src/eth/rx256to511oct_gb.rs | 53 + src/eth/rx512to1023oct_gb.rs | 53 + src/eth/rx64octets_gb.rs | 53 + src/eth/rx65to127oct_gb.rs | 53 + src/eth/rxalignerror.rs | 53 + src/eth/rxbcastframes_g.rs | 53 + src/eth/rxcrcerror.rs | 53 + src/eth/rxctrlframes_g.rs | 53 + src/eth/rxfifooverflow.rs | 53 + src/eth/rxframecount_gb.rs | 53 + src/eth/rxjabbererror.rs | 53 + src/eth/rxlengtherror.rs | 53 + src/eth/rxmcastframes_g.rs | 53 + src/eth/rxoctetcount_g.rs | 53 + src/eth/rxoctetcount_gb.rs | 53 + src/eth/rxoutrangetype.rs | 53 + src/eth/rxoversize_g.rs | 53 + src/eth/rxpauseframes.rs | 53 + src/eth/rxrcverror.rs | 53 + src/eth/rxrunterror.rs | 53 + src/eth/rxucastframes_g.rs | 53 + src/eth/rxundersize_g.rs | 53 + src/eth/rxvlanframes_gb.rs | 53 + src/eth/rxwdogerror.rs | 53 + src/eth/subsec_inc.rs | 103 + src/eth/systime_nanosec.rs | 53 + src/eth/systime_nsecup.rs | 150 ++ src/eth/systime_seconds.rs | 53 + src/eth/systime_secsupdat.rs | 103 + src/eth/target_time_nsec.rs | 150 ++ src/eth/target_time_secs.rs | 103 + src/eth/timestamp_ctrl.rs | 1043 +++++++++ src/eth/timestampaddend.rs | 103 + src/eth/tx1024maxoct_gb.rs | 53 + src/eth/tx128to255oct_gb.rs | 53 + src/eth/tx256to511oct_gb.rs | 53 + src/eth/tx512to1023oct_gb.rs | 53 + src/eth/tx64oct_gb.rs | 53 + src/eth/tx65to127oct_gb.rs | 53 + src/eth/txbcastframe_gb.rs | 53 + src/eth/txbcastframes_g.rs | 53 + src/eth/txcarriererror.rs | 53 + src/eth/txdeferred.rs | 53 + src/eth/txexcessdef.rs | 53 + src/eth/txexesscol.rs | 53 + src/eth/txframecount_g.rs | 53 + src/eth/txframecount_gb.rs | 53 + src/eth/txlanframes_g.rs | 53 + src/eth/txlatecol.rs | 53 + src/eth/txmcastframe_gb.rs | 53 + src/eth/txmcastframes_g.rs | 53 + src/eth/txmulticol_g.rs | 53 + src/eth/txoctetcount_g.rs | 53 + src/eth/txoctetcount_gb.rs | 53 + src/eth/txoversize_g.rs | 53 + src/eth/txpauseframes.rs | 53 + src/eth/txsinglecol_g.rs | 53 + src/eth/txucastframe_gb.rs | 53 + src/eth/txundererr.rs | 53 + src/eth/vlan_hashtable.rs | 103 + src/eth/vlan_increplace.rs | 234 ++ src/generic.rs | 260 +++ src/i2c0.rs | 240 ++ src/i2c0/address.rs | 64 + src/i2c0/clkscale.rs | 150 ++ src/i2c0/clktolimit.rs | 64 + src/i2c0/cmd.rs | 64 + src/i2c0/ctrl.rs | 489 +++++ src/i2c0/data.rs | 64 + src/i2c0/fifo_clr.rs | 99 + src/i2c0/irq_clr.rs | 423 ++++ src/i2c0/irq_enb.rs | 724 +++++++ src/i2c0/irq_end.rs | 313 +++ src/i2c0/irq_raw.rs | 313 +++ src/i2c0/perid.rs | 31 + src/i2c0/rxcount.rs | 31 + src/i2c0/rxfifoirqtrg.rs | 64 + src/i2c0/s0_address.rs | 197 ++ src/i2c0/s0_addressb.rs | 197 ++ src/i2c0/s0_addressmask.rs | 150 ++ src/i2c0/s0_addressmaskb.rs | 150 ++ src/i2c0/s0_ctrl.rs | 301 +++ src/i2c0/s0_data.rs | 103 + src/i2c0/s0_fifo_clr.rs | 99 + src/i2c0/s0_irq_clr.rs | 477 ++++ src/i2c0/s0_irq_enb.rs | 818 +++++++ src/i2c0/s0_irq_end.rs | 353 +++ src/i2c0/s0_irq_raw.rs | 353 +++ src/i2c0/s0_lastaddress.rs | 73 + src/i2c0/s0_maxwords.rs | 150 ++ src/i2c0/s0_rxcount.rs | 53 + src/i2c0/s0_rxfifoirqtrg.rs | 103 + src/i2c0/s0_state.rs | 31 + src/i2c0/s0_status.rs | 373 ++++ src/i2c0/s0_txcount.rs | 53 + src/i2c0/s0_txfifoirqtrg.rs | 103 + src/i2c0/state.rs | 31 + src/i2c0/status.rs | 771 +++++++ src/i2c0/tmconfig.rs | 64 + src/i2c0/txcount.rs | 31 + src/i2c0/txfifoirqtrg.rs | 64 + src/i2c0/words.rs | 64 + src/ioconfig.rs | 102 + src/ioconfig/clkdiv0.rs | 31 + src/ioconfig/clkdiv1.rs | 64 + src/ioconfig/clkdiv2.rs | 64 + src/ioconfig/clkdiv3.rs | 64 + src/ioconfig/clkdiv4.rs | 64 + src/ioconfig/clkdiv5.rs | 64 + src/ioconfig/clkdiv6.rs | 64 + src/ioconfig/clkdiv7.rs | 64 + src/ioconfig/perid.rs | 31 + src/ioconfig/porta.rs | 655 ++++++ src/ioconfig/portb.rs | 655 ++++++ src/ioconfig/portc.rs | 655 ++++++ src/ioconfig/portd.rs | 655 ++++++ src/ioconfig/porte.rs | 655 ++++++ src/ioconfig/portf.rs | 655 ++++++ src/ioconfig/portg.rs | 655 ++++++ src/irq_router.rs | 95 + src/irq_router/adcsel.rs | 103 + src/irq_router/dacsel0.rs | 103 + src/irq_router/dacsel1.rs | 103 + src/irq_router/dmasel0.rs | 103 + src/irq_router/dmasel1.rs | 103 + src/irq_router/dmasel2.rs | 103 + src/irq_router/dmasel3.rs | 103 + src/irq_router/dmattsel.rs | 103 + src/irq_router/irq_out0.rs | 53 + src/irq_router/irq_out1.rs | 53 + src/irq_router/irq_out2.rs | 53 + src/irq_router/irq_out3.rs | 53 + src/irq_router/irq_out4.rs | 53 + src/irq_router/irq_out5.rs | 53 + src/irq_router/perid.rs | 31 + src/lib.rs | 2763 +++++++++++++++++++++++- src/porta.rs | 380 ++++ src/porta/clrout.rs | 45 + src/porta/clroutbyte.rs | 46 + src/porta/datain.rs | 31 + src/porta/datainbyte.rs | 32 + src/porta/datainraw.rs | 31 + src/porta/datainrawbyte.rs | 32 + src/porta/datamask.rs | 64 + src/porta/datamaskbyte.rs | 65 + src/porta/dataout.rs | 45 + src/porta/dataoutbyte.rs | 46 + src/porta/dataoutraw.rs | 45 + src/porta/dataoutrawbyte.rs | 46 + src/porta/delay1.rs | 64 + src/porta/delay1byte.rs | 65 + src/porta/delay2.rs | 64 + src/porta/delay2byte.rs | 65 + src/porta/dir.rs | 64 + src/porta/dirbyte.rs | 65 + src/porta/edge_status.rs | 64 + src/porta/irq_edge.rs | 64 + src/porta/irq_enb.rs | 64 + src/porta/irq_end.rs | 31 + src/porta/irq_evt.rs | 64 + src/porta/irq_raw.rs | 31 + src/porta/irq_sen.rs | 64 + src/porta/perid.rs | 31 + src/porta/pulse.rs | 64 + src/porta/pulsebase.rs | 64 + src/porta/pulsebasebyte.rs | 65 + src/porta/pulsebyte.rs | 65 + src/porta/setout.rs | 45 + src/porta/setoutbyte.rs | 46 + src/porta/togout.rs | 45 + src/porta/togoutbyte.rs | 46 + src/spi0.rs | 89 + src/spi0/clkprescale.rs | 64 + src/spi0/ctrl0.rs | 234 ++ src/spi0/ctrl1.rs | 526 +++++ src/spi0/data.rs | 64 + src/spi0/fifo_clr.rs | 99 + src/spi0/irq_clr.rs | 153 ++ src/spi0/irq_enb.rs | 254 +++ src/spi0/irq_end.rs | 113 + src/spi0/irq_raw.rs | 113 + src/spi0/perid.rs | 31 + src/spi0/rxfifoirqtrg.rs | 64 + src/spi0/state.rs | 31 + src/spi0/status.rs | 193 ++ src/spi0/txfifoirqtrg.rs | 64 + src/spw.rs | 77 + src/spw/clkdiv.rs | 140 ++ src/spw/ctrl.rs | 1119 ++++++++++ src/spw/defaddr.rs | 140 ++ src/spw/dkey.rs | 103 + src/spw/dmaaddr0.rs | 140 ++ src/spw/dmactrl0.rs | 1177 ++++++++++ src/spw/dmamaxlen0.rs | 103 + src/spw/dmarxdesc0.rs | 140 ++ src/spw/dmatxdesc0.rs | 140 ++ src/spw/sts.rs | 600 +++++ src/spw/tc.rs | 140 ++ src/spw/tdr.rs | 73 + src/sysconfig.rs | 281 +++ src/sysconfig/adc_cal.rs | 53 + src/sysconfig/analog_cntl.rs | 704 ++++++ src/sysconfig/areg_cal.rs | 53 + src/sysconfig/bg_cal.rs | 53 + src/sysconfig/dac0_cal.rs | 53 + src/sysconfig/dac1_cal.rs | 53 + src/sysconfig/dreg_cal.rs | 53 + src/sysconfig/ebi_cfg0.rs | 298 +++ src/sysconfig/ebi_cfg1.rs | 298 +++ src/sysconfig/ebi_cfg2.rs | 298 +++ src/sysconfig/ebi_cfg3.rs | 298 +++ src/sysconfig/ef_config.rs | 253 +++ src/sysconfig/ef_id0.rs | 31 + src/sysconfig/ef_id1.rs | 31 + src/sysconfig/hbo_cal.rs | 73 + src/sysconfig/irq_clr.rs | 207 ++ src/sysconfig/irq_enb.rs | 348 +++ src/sysconfig/irq_end.rs | 153 ++ src/sysconfig/irq_raw.rs | 153 ++ src/sysconfig/perid.rs | 93 + src/sysconfig/peripheral_clk_enable.rs | 1523 +++++++++++++ src/sysconfig/peripheral_reset.rs | 1523 +++++++++++++ src/sysconfig/pmu_ctrl.rs | 103 + src/sysconfig/procid.rs | 31 + src/sysconfig/ram0_mbe.rs | 103 + src/sysconfig/ram0_sbe.rs | 103 + src/sysconfig/ram0_scrub.rs | 130 ++ src/sysconfig/ram1_mbe.rs | 103 + src/sysconfig/ram1_sbe.rs | 103 + src/sysconfig/ram1_scrub.rs | 130 ++ src/sysconfig/refresh_config_h.rs | 140 ++ src/sysconfig/refresh_config_l.rs | 103 + src/sysconfig/rom_mbe.rs | 103 + src/sysconfig/rom_prot.rs | 113 + src/sysconfig/rom_retries.rs | 53 + src/sysconfig/rom_sbe.rs | 103 + src/sysconfig/rom_scrub.rs | 130 ++ src/sysconfig/rst_cntl_ram0.rs | 321 +++ src/sysconfig/rst_cntl_ram1.rs | 321 +++ src/sysconfig/rst_cntl_rom.rs | 321 +++ src/sysconfig/rst_stat.rs | 321 +++ src/sysconfig/spw_m4_ctrl.rs | 197 ++ src/sysconfig/sw_clkdiv10.rs | 103 + src/sysconfig/tim_clk_enable.rs | 103 + src/sysconfig/tim_reset.rs | 103 + src/sysconfig/wakeup_cnt.rs | 150 ++ src/tim0.rs | 92 + src/tim0/cascade0.rs | 103 + src/tim0/cascade1.rs | 103 + src/tim0/cascade2.rs | 103 + src/tim0/cnt_value.rs | 64 + src/tim0/csd_ctrl.rs | 536 +++++ src/tim0/ctrl.rs | 519 +++++ src/tim0/enable.rs | 113 + src/tim0/perid.rs | 31 + src/tim0/pwm_value.rs | 64 + src/tim0/pwma_value.rs | 64 + src/tim0/pwmb_value.rs | 64 + src/tim0/rst_value.rs | 64 + src/trng.rs | 134 ++ src/trng/autocorr_statistic.rs | 140 ++ src/trng/bist_cntr0.rs | 53 + src/trng/bist_cntr1.rs | 53 + src/trng/bist_cntr2.rs | 53 + src/trng/busy.rs | 53 + src/trng/config.rs | 103 + src/trng/debug_control.rs | 207 ++ src/trng/ehr_data0.rs | 53 + src/trng/ehr_data1.rs | 53 + src/trng/ehr_data2.rs | 53 + src/trng/ehr_data3.rs | 53 + src/trng/ehr_data4.rs | 53 + src/trng/ehr_data5.rs | 53 + src/trng/icr.rs | 258 +++ src/trng/imr.rs | 254 +++ src/trng/isr.rs | 113 + src/trng/rnd_source_enable.rs | 113 + src/trng/rst_bits_counter.rs | 113 + src/trng/sample_cnt1.rs | 103 + src/trng/sw_reset.rs | 113 + src/trng/valid.rs | 53 + src/uart0.rs | 119 + src/uart0/addr9.rs | 64 + src/uart0/addr9mask.rs | 64 + src/uart0/clkscale.rs | 167 ++ src/uart0/ctrl.rs | 573 +++++ src/uart0/data.rs | 64 + src/uart0/enable.rs | 160 ++ src/uart0/fifo_clr.rs | 99 + src/uart0/irq_clr.rs | 234 ++ src/uart0/irq_enb.rs | 395 ++++ src/uart0/irq_end.rs | 173 ++ src/uart0/irq_raw.rs | 173 ++ src/uart0/perid.rs | 31 + src/uart0/rxfifoirqtrg.rs | 64 + src/uart0/rxfifortstrg.rs | 64 + src/uart0/rxstatus.rs | 253 +++ src/uart0/state.rs | 31 + src/uart0/txbreak.rs | 45 + src/uart0/txfifoirqtrg.rs | 64 + src/uart0/txstatus.rs | 133 ++ src/utility.rs | 96 + src/utility/perid.rs | 31 + src/utility/ram_trap_addr0.rs | 150 ++ src/utility/ram_trap_addr1.rs | 150 ++ src/utility/ram_trap_synd0.rs | 140 ++ src/utility/ram_trap_synd1.rs | 140 ++ src/utility/rom_trap_address.rs | 150 ++ src/utility/rom_trap_synd.rs | 140 ++ src/utility/synd_check_32_44_data.rs | 31 + src/utility/synd_check_32_44_synd.rs | 93 + src/utility/synd_check_32_52_data.rs | 31 + src/utility/synd_check_32_52_synd.rs | 93 + src/utility/synd_data.rs | 64 + src/utility/synd_enc_32_44.rs | 140 ++ src/utility/synd_enc_32_52.rs | 53 + src/utility/synd_synd.rs | 103 + src/watch_dog.rs | 109 + src/watch_dog/wdogcontrol.rs | 160 ++ src/watch_dog/wdogintclr.rs | 103 + src/watch_dog/wdogitcr.rs | 113 + src/watch_dog/wdogitop.rs | 160 ++ src/watch_dog/wdogload.rs | 103 + src/watch_dog/wdoglock.rs | 103 + src/watch_dog/wdogmis.rs | 53 + src/watch_dog/wdogpcellid0.rs | 53 + src/watch_dog/wdogpcellid1.rs | 53 + src/watch_dog/wdogpcellid2.rs | 53 + src/watch_dog/wdogpcellid3.rs | 53 + src/watch_dog/wdogperiphid0.rs | 53 + src/watch_dog/wdogperiphid1.rs | 53 + src/watch_dog/wdogperiphid2.rs | 53 + src/watch_dog/wdogperiphid3.rs | 53 + src/watch_dog/wdogris.rs | 53 + src/watch_dog/wdogvalue.rs | 53 + 580 files changed, 96467 insertions(+), 6 deletions(-) create mode 100644 build.rs create mode 100644 device.x create mode 100755 gen-helper.sh create mode 100644 src/adc.rs create mode 100644 src/adc/ctrl.rs create mode 100644 src/adc/fifo_clr.rs create mode 100644 src/adc/fifo_data.rs create mode 100644 src/adc/irq_clr.rs create mode 100644 src/adc/irq_enb.rs create mode 100644 src/adc/irq_end.rs create mode 100644 src/adc/irq_raw.rs create mode 100644 src/adc/perid.rs create mode 100644 src/adc/rxfifoirqtrg.rs create mode 100644 src/adc/status.rs create mode 100644 src/can0.rs create mode 100644 src/can0/bmskb.rs create mode 100644 src/can0/bmskx.rs create mode 100644 src/can0/canec.rs create mode 100644 src/can0/cediag.rs create mode 100644 src/can0/cgcr.rs create mode 100644 src/can0/cicen.rs create mode 100644 src/can0/ciclr.rs create mode 100644 src/can0/cien.rs create mode 100644 src/can0/cipnd.rs create mode 100644 src/can0/cnstat_cmb0.rs create mode 100644 src/can0/cnstat_cmb1.rs create mode 100644 src/can0/cnstat_cmb10.rs create mode 100644 src/can0/cnstat_cmb11.rs create mode 100644 src/can0/cnstat_cmb12.rs create mode 100644 src/can0/cnstat_cmb13.rs create mode 100644 src/can0/cnstat_cmb14.rs create mode 100644 src/can0/cnstat_cmb2.rs create mode 100644 src/can0/cnstat_cmb3.rs create mode 100644 src/can0/cnstat_cmb4.rs create mode 100644 src/can0/cnstat_cmb5.rs create mode 100644 src/can0/cnstat_cmb6.rs create mode 100644 src/can0/cnstat_cmb7.rs create mode 100644 src/can0/cnstat_cmb8.rs create mode 100644 src/can0/cnstat_cmb9.rs create mode 100644 src/can0/cnstat_hcmb.rs create mode 100644 src/can0/cstpnd.rs create mode 100644 src/can0/ctim.rs create mode 100644 src/can0/ctmr.rs create mode 100644 src/can0/data0_cmb0.rs create mode 100644 src/can0/data0_cmb1.rs create mode 100644 src/can0/data0_cmb10.rs create mode 100644 src/can0/data0_cmb11.rs create mode 100644 src/can0/data0_cmb12.rs create mode 100644 src/can0/data0_cmb13.rs create mode 100644 src/can0/data0_cmb14.rs create mode 100644 src/can0/data0_cmb2.rs create mode 100644 src/can0/data0_cmb3.rs create mode 100644 src/can0/data0_cmb4.rs create mode 100644 src/can0/data0_cmb5.rs create mode 100644 src/can0/data0_cmb6.rs create mode 100644 src/can0/data0_cmb7.rs create mode 100644 src/can0/data0_cmb8.rs create mode 100644 src/can0/data0_cmb9.rs create mode 100644 src/can0/data0_hcmb.rs create mode 100644 src/can0/data1_cmb0.rs create mode 100644 src/can0/data1_cmb1.rs create mode 100644 src/can0/data1_cmb10.rs create mode 100644 src/can0/data1_cmb11.rs create mode 100644 src/can0/data1_cmb12.rs create mode 100644 src/can0/data1_cmb13.rs create mode 100644 src/can0/data1_cmb14.rs create mode 100644 src/can0/data1_cmb2.rs create mode 100644 src/can0/data1_cmb3.rs create mode 100644 src/can0/data1_cmb4.rs create mode 100644 src/can0/data1_cmb5.rs create mode 100644 src/can0/data1_cmb6.rs create mode 100644 src/can0/data1_cmb7.rs create mode 100644 src/can0/data1_cmb8.rs create mode 100644 src/can0/data1_cmb9.rs create mode 100644 src/can0/data1_hcmb.rs create mode 100644 src/can0/data2_cmb0.rs create mode 100644 src/can0/data2_cmb1.rs create mode 100644 src/can0/data2_cmb10.rs create mode 100644 src/can0/data2_cmb11.rs create mode 100644 src/can0/data2_cmb12.rs create mode 100644 src/can0/data2_cmb13.rs create mode 100644 src/can0/data2_cmb14.rs create mode 100644 src/can0/data2_cmb2.rs create mode 100644 src/can0/data2_cmb3.rs create mode 100644 src/can0/data2_cmb4.rs create mode 100644 src/can0/data2_cmb5.rs create mode 100644 src/can0/data2_cmb6.rs create mode 100644 src/can0/data2_cmb7.rs create mode 100644 src/can0/data2_cmb8.rs create mode 100644 src/can0/data2_cmb9.rs create mode 100644 src/can0/data2_hcmb.rs create mode 100644 src/can0/data3_cmb0.rs create mode 100644 src/can0/data3_cmb1.rs create mode 100644 src/can0/data3_cmb10.rs create mode 100644 src/can0/data3_cmb11.rs create mode 100644 src/can0/data3_cmb12.rs create mode 100644 src/can0/data3_cmb13.rs create mode 100644 src/can0/data3_cmb14.rs create mode 100644 src/can0/data3_cmb2.rs create mode 100644 src/can0/data3_cmb3.rs create mode 100644 src/can0/data3_cmb4.rs create mode 100644 src/can0/data3_cmb5.rs create mode 100644 src/can0/data3_cmb6.rs create mode 100644 src/can0/data3_cmb7.rs create mode 100644 src/can0/data3_cmb8.rs create mode 100644 src/can0/data3_cmb9.rs create mode 100644 src/can0/data3_hcmb.rs create mode 100644 src/can0/gmskb.rs create mode 100644 src/can0/gmskx.rs create mode 100644 src/can0/id0_cmb0.rs create mode 100644 src/can0/id0_cmb1.rs create mode 100644 src/can0/id0_cmb10.rs create mode 100644 src/can0/id0_cmb11.rs create mode 100644 src/can0/id0_cmb12.rs create mode 100644 src/can0/id0_cmb13.rs create mode 100644 src/can0/id0_cmb14.rs create mode 100644 src/can0/id0_cmb2.rs create mode 100644 src/can0/id0_cmb3.rs create mode 100644 src/can0/id0_cmb4.rs create mode 100644 src/can0/id0_cmb5.rs create mode 100644 src/can0/id0_cmb6.rs create mode 100644 src/can0/id0_cmb7.rs create mode 100644 src/can0/id0_cmb8.rs create mode 100644 src/can0/id0_cmb9.rs create mode 100644 src/can0/id0_hcmb.rs create mode 100644 src/can0/id1_cmb0.rs create mode 100644 src/can0/id1_cmb1.rs create mode 100644 src/can0/id1_cmb10.rs create mode 100644 src/can0/id1_cmb11.rs create mode 100644 src/can0/id1_cmb12.rs create mode 100644 src/can0/id1_cmb13.rs create mode 100644 src/can0/id1_cmb14.rs create mode 100644 src/can0/id1_cmb2.rs create mode 100644 src/can0/id1_cmb3.rs create mode 100644 src/can0/id1_cmb4.rs create mode 100644 src/can0/id1_cmb5.rs create mode 100644 src/can0/id1_cmb6.rs create mode 100644 src/can0/id1_cmb7.rs create mode 100644 src/can0/id1_cmb8.rs create mode 100644 src/can0/id1_cmb9.rs create mode 100644 src/can0/id1_hcmb.rs create mode 100644 src/can0/tstp_cmb0.rs create mode 100644 src/can0/tstp_cmb1.rs create mode 100644 src/can0/tstp_cmb10.rs create mode 100644 src/can0/tstp_cmb11.rs create mode 100644 src/can0/tstp_cmb12.rs create mode 100644 src/can0/tstp_cmb13.rs create mode 100644 src/can0/tstp_cmb14.rs create mode 100644 src/can0/tstp_cmb2.rs create mode 100644 src/can0/tstp_cmb3.rs create mode 100644 src/can0/tstp_cmb4.rs create mode 100644 src/can0/tstp_cmb5.rs create mode 100644 src/can0/tstp_cmb6.rs create mode 100644 src/can0/tstp_cmb7.rs create mode 100644 src/can0/tstp_cmb8.rs create mode 100644 src/can0/tstp_cmb9.rs create mode 100644 src/can0/tstp_hcmb.rs create mode 100644 src/clkgen.rs create mode 100644 src/clkgen/ctrl0.rs create mode 100644 src/clkgen/ctrl1.rs create mode 100644 src/clkgen/stat.rs create mode 100644 src/dac0.rs create mode 100644 src/dac0/ctrl0.rs create mode 100644 src/dac0/ctrl1.rs create mode 100644 src/dac0/fifo_clr.rs create mode 100644 src/dac0/fifo_data.rs create mode 100644 src/dac0/irq_clr.rs create mode 100644 src/dac0/irq_enb.rs create mode 100644 src/dac0/irq_end.rs create mode 100644 src/dac0/irq_raw.rs create mode 100644 src/dac0/perid.rs create mode 100644 src/dac0/status.rs create mode 100644 src/dac0/txfifoirqtrg.rs create mode 100644 src/dma.rs create mode 100644 src/dma/alt_ctrl_base_ptr.rs create mode 100644 src/dma/cfg.rs create mode 100644 src/dma/chnl_enable_clr.rs create mode 100644 src/dma/chnl_enable_set.rs create mode 100644 src/dma/chnl_pri_alt_clr.rs create mode 100644 src/dma/chnl_pri_alt_set.rs create mode 100644 src/dma/chnl_priority_clr.rs create mode 100644 src/dma/chnl_priority_set.rs create mode 100644 src/dma/chnl_req_mask_clr.rs create mode 100644 src/dma/chnl_req_mask_set.rs create mode 100644 src/dma/chnl_sw_request.rs create mode 100644 src/dma/chnl_useburst_clr.rs create mode 100644 src/dma/chnl_useburst_set.rs create mode 100644 src/dma/ctrl_base_ptr.rs create mode 100644 src/dma/dma_active_clr.rs create mode 100644 src/dma/dma_active_set.rs create mode 100644 src/dma/dma_done_clr.rs create mode 100644 src/dma/dma_done_set.rs create mode 100644 src/dma/dma_req_status.rs create mode 100644 src/dma/dma_sreq_status.rs create mode 100644 src/dma/err_clr.rs create mode 100644 src/dma/err_set.rs create mode 100644 src/dma/integration_cfg.rs create mode 100644 src/dma/periph_id_0.rs create mode 100644 src/dma/periph_id_1.rs create mode 100644 src/dma/periph_id_2.rs create mode 100644 src/dma/periph_id_3.rs create mode 100644 src/dma/periph_id_4.rs create mode 100644 src/dma/primecell_id_0.rs create mode 100644 src/dma/primecell_id_1.rs create mode 100644 src/dma/primecell_id_2.rs create mode 100644 src/dma/primecell_id_3.rs create mode 100644 src/dma/stall_status.rs create mode 100644 src/dma/status.rs create mode 100644 src/dma/waitonreq_status.rs create mode 100644 src/eth.rs create mode 100644 src/eth/dma_ahb_status.rs create mode 100644 src/eth/dma_bus_mode.rs create mode 100644 src/eth/dma_curr_rx_bufr_addr.rs create mode 100644 src/eth/dma_curr_rx_desc.rs create mode 100644 src/eth/dma_curr_tx_bufr_addr.rs create mode 100644 src/eth/dma_curr_tx_desc.rs create mode 100644 src/eth/dma_intr_en.rs create mode 100644 src/eth/dma_miss_over_counter.rs create mode 100644 src/eth/dma_oper_mode.rs create mode 100644 src/eth/dma_rx_desc_list_addr.rs create mode 100644 src/eth/dma_rx_intr_wdog_timer.rs create mode 100644 src/eth/dma_rx_poll_demand.rs create mode 100644 src/eth/dma_status.rs create mode 100644 src/eth/dma_tx_desc_list_addr.rs create mode 100644 src/eth/dma_tx_poll_demand.rs create mode 100644 src/eth/mac_addr_h.rs create mode 100644 src/eth/mac_addr_l.rs create mode 100644 src/eth/mac_config.rs create mode 100644 src/eth/mac_debug.rs create mode 100644 src/eth/mac_flow_ctrl.rs create mode 100644 src/eth/mac_frame_fltr.rs create mode 100644 src/eth/mac_gmii_addr.rs create mode 100644 src/eth/mac_gmii_data.rs create mode 100644 src/eth/mac_intr_mask.rs create mode 100644 src/eth/mac_intr_stat.rs create mode 100644 src/eth/mac_vlan_tag.rs create mode 100644 src/eth/mac_wdog_to.rs create mode 100644 src/eth/mmc_cntrl.rs create mode 100644 src/eth/mmc_intr_mask_rx.rs create mode 100644 src/eth/mmc_intr_mask_tx.rs create mode 100644 src/eth/mmc_intr_rx.rs create mode 100644 src/eth/mmc_intr_tx.rs create mode 100644 src/eth/rx1024maxoct_gb.rs create mode 100644 src/eth/rx128to255oct_gb.rs create mode 100644 src/eth/rx256to511oct_gb.rs create mode 100644 src/eth/rx512to1023oct_gb.rs create mode 100644 src/eth/rx64octets_gb.rs create mode 100644 src/eth/rx65to127oct_gb.rs create mode 100644 src/eth/rxalignerror.rs create mode 100644 src/eth/rxbcastframes_g.rs create mode 100644 src/eth/rxcrcerror.rs create mode 100644 src/eth/rxctrlframes_g.rs create mode 100644 src/eth/rxfifooverflow.rs create mode 100644 src/eth/rxframecount_gb.rs create mode 100644 src/eth/rxjabbererror.rs create mode 100644 src/eth/rxlengtherror.rs create mode 100644 src/eth/rxmcastframes_g.rs create mode 100644 src/eth/rxoctetcount_g.rs create mode 100644 src/eth/rxoctetcount_gb.rs create mode 100644 src/eth/rxoutrangetype.rs create mode 100644 src/eth/rxoversize_g.rs create mode 100644 src/eth/rxpauseframes.rs create mode 100644 src/eth/rxrcverror.rs create mode 100644 src/eth/rxrunterror.rs create mode 100644 src/eth/rxucastframes_g.rs create mode 100644 src/eth/rxundersize_g.rs create mode 100644 src/eth/rxvlanframes_gb.rs create mode 100644 src/eth/rxwdogerror.rs create mode 100644 src/eth/subsec_inc.rs create mode 100644 src/eth/systime_nanosec.rs create mode 100644 src/eth/systime_nsecup.rs create mode 100644 src/eth/systime_seconds.rs create mode 100644 src/eth/systime_secsupdat.rs create mode 100644 src/eth/target_time_nsec.rs create mode 100644 src/eth/target_time_secs.rs create mode 100644 src/eth/timestamp_ctrl.rs create mode 100644 src/eth/timestampaddend.rs create mode 100644 src/eth/tx1024maxoct_gb.rs create mode 100644 src/eth/tx128to255oct_gb.rs create mode 100644 src/eth/tx256to511oct_gb.rs create mode 100644 src/eth/tx512to1023oct_gb.rs create mode 100644 src/eth/tx64oct_gb.rs create mode 100644 src/eth/tx65to127oct_gb.rs create mode 100644 src/eth/txbcastframe_gb.rs create mode 100644 src/eth/txbcastframes_g.rs create mode 100644 src/eth/txcarriererror.rs create mode 100644 src/eth/txdeferred.rs create mode 100644 src/eth/txexcessdef.rs create mode 100644 src/eth/txexesscol.rs create mode 100644 src/eth/txframecount_g.rs create mode 100644 src/eth/txframecount_gb.rs create mode 100644 src/eth/txlanframes_g.rs create mode 100644 src/eth/txlatecol.rs create mode 100644 src/eth/txmcastframe_gb.rs create mode 100644 src/eth/txmcastframes_g.rs create mode 100644 src/eth/txmulticol_g.rs create mode 100644 src/eth/txoctetcount_g.rs create mode 100644 src/eth/txoctetcount_gb.rs create mode 100644 src/eth/txoversize_g.rs create mode 100644 src/eth/txpauseframes.rs create mode 100644 src/eth/txsinglecol_g.rs create mode 100644 src/eth/txucastframe_gb.rs create mode 100644 src/eth/txundererr.rs create mode 100644 src/eth/vlan_hashtable.rs create mode 100644 src/eth/vlan_increplace.rs create mode 100644 src/generic.rs create mode 100644 src/i2c0.rs create mode 100644 src/i2c0/address.rs create mode 100644 src/i2c0/clkscale.rs create mode 100644 src/i2c0/clktolimit.rs create mode 100644 src/i2c0/cmd.rs create mode 100644 src/i2c0/ctrl.rs create mode 100644 src/i2c0/data.rs create mode 100644 src/i2c0/fifo_clr.rs create mode 100644 src/i2c0/irq_clr.rs create mode 100644 src/i2c0/irq_enb.rs create mode 100644 src/i2c0/irq_end.rs create mode 100644 src/i2c0/irq_raw.rs create mode 100644 src/i2c0/perid.rs create mode 100644 src/i2c0/rxcount.rs create mode 100644 src/i2c0/rxfifoirqtrg.rs create mode 100644 src/i2c0/s0_address.rs create mode 100644 src/i2c0/s0_addressb.rs create mode 100644 src/i2c0/s0_addressmask.rs create mode 100644 src/i2c0/s0_addressmaskb.rs create mode 100644 src/i2c0/s0_ctrl.rs create mode 100644 src/i2c0/s0_data.rs create mode 100644 src/i2c0/s0_fifo_clr.rs create mode 100644 src/i2c0/s0_irq_clr.rs create mode 100644 src/i2c0/s0_irq_enb.rs create mode 100644 src/i2c0/s0_irq_end.rs create mode 100644 src/i2c0/s0_irq_raw.rs create mode 100644 src/i2c0/s0_lastaddress.rs create mode 100644 src/i2c0/s0_maxwords.rs create mode 100644 src/i2c0/s0_rxcount.rs create mode 100644 src/i2c0/s0_rxfifoirqtrg.rs create mode 100644 src/i2c0/s0_state.rs create mode 100644 src/i2c0/s0_status.rs create mode 100644 src/i2c0/s0_txcount.rs create mode 100644 src/i2c0/s0_txfifoirqtrg.rs create mode 100644 src/i2c0/state.rs create mode 100644 src/i2c0/status.rs create mode 100644 src/i2c0/tmconfig.rs create mode 100644 src/i2c0/txcount.rs create mode 100644 src/i2c0/txfifoirqtrg.rs create mode 100644 src/i2c0/words.rs create mode 100644 src/ioconfig.rs create mode 100644 src/ioconfig/clkdiv0.rs create mode 100644 src/ioconfig/clkdiv1.rs create mode 100644 src/ioconfig/clkdiv2.rs create mode 100644 src/ioconfig/clkdiv3.rs create mode 100644 src/ioconfig/clkdiv4.rs create mode 100644 src/ioconfig/clkdiv5.rs create mode 100644 src/ioconfig/clkdiv6.rs create mode 100644 src/ioconfig/clkdiv7.rs create mode 100644 src/ioconfig/perid.rs create mode 100644 src/ioconfig/porta.rs create mode 100644 src/ioconfig/portb.rs create mode 100644 src/ioconfig/portc.rs create mode 100644 src/ioconfig/portd.rs create mode 100644 src/ioconfig/porte.rs create mode 100644 src/ioconfig/portf.rs create mode 100644 src/ioconfig/portg.rs create mode 100644 src/irq_router.rs create mode 100644 src/irq_router/adcsel.rs create mode 100644 src/irq_router/dacsel0.rs create mode 100644 src/irq_router/dacsel1.rs create mode 100644 src/irq_router/dmasel0.rs create mode 100644 src/irq_router/dmasel1.rs create mode 100644 src/irq_router/dmasel2.rs create mode 100644 src/irq_router/dmasel3.rs create mode 100644 src/irq_router/dmattsel.rs create mode 100644 src/irq_router/irq_out0.rs create mode 100644 src/irq_router/irq_out1.rs create mode 100644 src/irq_router/irq_out2.rs create mode 100644 src/irq_router/irq_out3.rs create mode 100644 src/irq_router/irq_out4.rs create mode 100644 src/irq_router/irq_out5.rs create mode 100644 src/irq_router/perid.rs create mode 100644 src/porta.rs create mode 100644 src/porta/clrout.rs create mode 100644 src/porta/clroutbyte.rs create mode 100644 src/porta/datain.rs create mode 100644 src/porta/datainbyte.rs create mode 100644 src/porta/datainraw.rs create mode 100644 src/porta/datainrawbyte.rs create mode 100644 src/porta/datamask.rs create mode 100644 src/porta/datamaskbyte.rs create mode 100644 src/porta/dataout.rs create mode 100644 src/porta/dataoutbyte.rs create mode 100644 src/porta/dataoutraw.rs create mode 100644 src/porta/dataoutrawbyte.rs create mode 100644 src/porta/delay1.rs create mode 100644 src/porta/delay1byte.rs create mode 100644 src/porta/delay2.rs create mode 100644 src/porta/delay2byte.rs create mode 100644 src/porta/dir.rs create mode 100644 src/porta/dirbyte.rs create mode 100644 src/porta/edge_status.rs create mode 100644 src/porta/irq_edge.rs create mode 100644 src/porta/irq_enb.rs create mode 100644 src/porta/irq_end.rs create mode 100644 src/porta/irq_evt.rs create mode 100644 src/porta/irq_raw.rs create mode 100644 src/porta/irq_sen.rs create mode 100644 src/porta/perid.rs create mode 100644 src/porta/pulse.rs create mode 100644 src/porta/pulsebase.rs create mode 100644 src/porta/pulsebasebyte.rs create mode 100644 src/porta/pulsebyte.rs create mode 100644 src/porta/setout.rs create mode 100644 src/porta/setoutbyte.rs create mode 100644 src/porta/togout.rs create mode 100644 src/porta/togoutbyte.rs create mode 100644 src/spi0.rs create mode 100644 src/spi0/clkprescale.rs create mode 100644 src/spi0/ctrl0.rs create mode 100644 src/spi0/ctrl1.rs create mode 100644 src/spi0/data.rs create mode 100644 src/spi0/fifo_clr.rs create mode 100644 src/spi0/irq_clr.rs create mode 100644 src/spi0/irq_enb.rs create mode 100644 src/spi0/irq_end.rs create mode 100644 src/spi0/irq_raw.rs create mode 100644 src/spi0/perid.rs create mode 100644 src/spi0/rxfifoirqtrg.rs create mode 100644 src/spi0/state.rs create mode 100644 src/spi0/status.rs create mode 100644 src/spi0/txfifoirqtrg.rs create mode 100644 src/spw.rs create mode 100644 src/spw/clkdiv.rs create mode 100644 src/spw/ctrl.rs create mode 100644 src/spw/defaddr.rs create mode 100644 src/spw/dkey.rs create mode 100644 src/spw/dmaaddr0.rs create mode 100644 src/spw/dmactrl0.rs create mode 100644 src/spw/dmamaxlen0.rs create mode 100644 src/spw/dmarxdesc0.rs create mode 100644 src/spw/dmatxdesc0.rs create mode 100644 src/spw/sts.rs create mode 100644 src/spw/tc.rs create mode 100644 src/spw/tdr.rs create mode 100644 src/sysconfig.rs create mode 100644 src/sysconfig/adc_cal.rs create mode 100644 src/sysconfig/analog_cntl.rs create mode 100644 src/sysconfig/areg_cal.rs create mode 100644 src/sysconfig/bg_cal.rs create mode 100644 src/sysconfig/dac0_cal.rs create mode 100644 src/sysconfig/dac1_cal.rs create mode 100644 src/sysconfig/dreg_cal.rs create mode 100644 src/sysconfig/ebi_cfg0.rs create mode 100644 src/sysconfig/ebi_cfg1.rs create mode 100644 src/sysconfig/ebi_cfg2.rs create mode 100644 src/sysconfig/ebi_cfg3.rs create mode 100644 src/sysconfig/ef_config.rs create mode 100644 src/sysconfig/ef_id0.rs create mode 100644 src/sysconfig/ef_id1.rs create mode 100644 src/sysconfig/hbo_cal.rs create mode 100644 src/sysconfig/irq_clr.rs create mode 100644 src/sysconfig/irq_enb.rs create mode 100644 src/sysconfig/irq_end.rs create mode 100644 src/sysconfig/irq_raw.rs create mode 100644 src/sysconfig/perid.rs create mode 100644 src/sysconfig/peripheral_clk_enable.rs create mode 100644 src/sysconfig/peripheral_reset.rs create mode 100644 src/sysconfig/pmu_ctrl.rs create mode 100644 src/sysconfig/procid.rs create mode 100644 src/sysconfig/ram0_mbe.rs create mode 100644 src/sysconfig/ram0_sbe.rs create mode 100644 src/sysconfig/ram0_scrub.rs create mode 100644 src/sysconfig/ram1_mbe.rs create mode 100644 src/sysconfig/ram1_sbe.rs create mode 100644 src/sysconfig/ram1_scrub.rs create mode 100644 src/sysconfig/refresh_config_h.rs create mode 100644 src/sysconfig/refresh_config_l.rs create mode 100644 src/sysconfig/rom_mbe.rs create mode 100644 src/sysconfig/rom_prot.rs create mode 100644 src/sysconfig/rom_retries.rs create mode 100644 src/sysconfig/rom_sbe.rs create mode 100644 src/sysconfig/rom_scrub.rs create mode 100644 src/sysconfig/rst_cntl_ram0.rs create mode 100644 src/sysconfig/rst_cntl_ram1.rs create mode 100644 src/sysconfig/rst_cntl_rom.rs create mode 100644 src/sysconfig/rst_stat.rs create mode 100644 src/sysconfig/spw_m4_ctrl.rs create mode 100644 src/sysconfig/sw_clkdiv10.rs create mode 100644 src/sysconfig/tim_clk_enable.rs create mode 100644 src/sysconfig/tim_reset.rs create mode 100644 src/sysconfig/wakeup_cnt.rs create mode 100644 src/tim0.rs create mode 100644 src/tim0/cascade0.rs create mode 100644 src/tim0/cascade1.rs create mode 100644 src/tim0/cascade2.rs create mode 100644 src/tim0/cnt_value.rs create mode 100644 src/tim0/csd_ctrl.rs create mode 100644 src/tim0/ctrl.rs create mode 100644 src/tim0/enable.rs create mode 100644 src/tim0/perid.rs create mode 100644 src/tim0/pwm_value.rs create mode 100644 src/tim0/pwma_value.rs create mode 100644 src/tim0/pwmb_value.rs create mode 100644 src/tim0/rst_value.rs create mode 100644 src/trng.rs create mode 100644 src/trng/autocorr_statistic.rs create mode 100644 src/trng/bist_cntr0.rs create mode 100644 src/trng/bist_cntr1.rs create mode 100644 src/trng/bist_cntr2.rs create mode 100644 src/trng/busy.rs create mode 100644 src/trng/config.rs create mode 100644 src/trng/debug_control.rs create mode 100644 src/trng/ehr_data0.rs create mode 100644 src/trng/ehr_data1.rs create mode 100644 src/trng/ehr_data2.rs create mode 100644 src/trng/ehr_data3.rs create mode 100644 src/trng/ehr_data4.rs create mode 100644 src/trng/ehr_data5.rs create mode 100644 src/trng/icr.rs create mode 100644 src/trng/imr.rs create mode 100644 src/trng/isr.rs create mode 100644 src/trng/rnd_source_enable.rs create mode 100644 src/trng/rst_bits_counter.rs create mode 100644 src/trng/sample_cnt1.rs create mode 100644 src/trng/sw_reset.rs create mode 100644 src/trng/valid.rs create mode 100644 src/uart0.rs create mode 100644 src/uart0/addr9.rs create mode 100644 src/uart0/addr9mask.rs create mode 100644 src/uart0/clkscale.rs create mode 100644 src/uart0/ctrl.rs create mode 100644 src/uart0/data.rs create mode 100644 src/uart0/enable.rs create mode 100644 src/uart0/fifo_clr.rs create mode 100644 src/uart0/irq_clr.rs create mode 100644 src/uart0/irq_enb.rs create mode 100644 src/uart0/irq_end.rs create mode 100644 src/uart0/irq_raw.rs create mode 100644 src/uart0/perid.rs create mode 100644 src/uart0/rxfifoirqtrg.rs create mode 100644 src/uart0/rxfifortstrg.rs create mode 100644 src/uart0/rxstatus.rs create mode 100644 src/uart0/state.rs create mode 100644 src/uart0/txbreak.rs create mode 100644 src/uart0/txfifoirqtrg.rs create mode 100644 src/uart0/txstatus.rs create mode 100644 src/utility.rs create mode 100644 src/utility/perid.rs create mode 100644 src/utility/ram_trap_addr0.rs create mode 100644 src/utility/ram_trap_addr1.rs create mode 100644 src/utility/ram_trap_synd0.rs create mode 100644 src/utility/ram_trap_synd1.rs create mode 100644 src/utility/rom_trap_address.rs create mode 100644 src/utility/rom_trap_synd.rs create mode 100644 src/utility/synd_check_32_44_data.rs create mode 100644 src/utility/synd_check_32_44_synd.rs create mode 100644 src/utility/synd_check_32_52_data.rs create mode 100644 src/utility/synd_check_32_52_synd.rs create mode 100644 src/utility/synd_data.rs create mode 100644 src/utility/synd_enc_32_44.rs create mode 100644 src/utility/synd_enc_32_52.rs create mode 100644 src/utility/synd_synd.rs create mode 100644 src/watch_dog.rs create mode 100644 src/watch_dog/wdogcontrol.rs create mode 100644 src/watch_dog/wdogintclr.rs create mode 100644 src/watch_dog/wdogitcr.rs create mode 100644 src/watch_dog/wdogitop.rs create mode 100644 src/watch_dog/wdogload.rs create mode 100644 src/watch_dog/wdoglock.rs create mode 100644 src/watch_dog/wdogmis.rs create mode 100644 src/watch_dog/wdogpcellid0.rs create mode 100644 src/watch_dog/wdogpcellid1.rs create mode 100644 src/watch_dog/wdogpcellid2.rs create mode 100644 src/watch_dog/wdogpcellid3.rs create mode 100644 src/watch_dog/wdogperiphid0.rs create mode 100644 src/watch_dog/wdogperiphid1.rs create mode 100644 src/watch_dog/wdogperiphid2.rs create mode 100644 src/watch_dog/wdogperiphid3.rs create mode 100644 src/watch_dog/wdogris.rs create mode 100644 src/watch_dog/wdogvalue.rs diff --git a/Cargo.toml b/Cargo.toml index af1f682..e5ce8ea 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,8 +1,24 @@ [package] name = "va416xx" version = "0.1.0" +authors = ["Robin Mueller "] edition = "2021" +description = "PAC for the Vorago VA416xx family of microcontrollers" +homepage = "https://github.com/robamu/va416xx-rs" +repository = "https://github.com/robamu/va416xx-rs" +license = "MIT OR Apache-2.0" +keywords = ["no-std", "arm", "cortex-m", "vorago", "va416xx"] +categories = ["embedded", "no-std", "hardware-support"] # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html [dependencies] +cortex-m = "0.7.3" +vcell = "0.1.3" + +[dependencies.cortex-m-rt] +optional = true +version = ">=0.6.15,<0.8" + +[features] +rt = ["cortex-m-rt/device"] diff --git a/build.rs b/build.rs new file mode 100644 index 0000000..597923f --- /dev/null +++ b/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/device.x b/device.x new file mode 100644 index 0000000..b62a5a9 --- /dev/null +++ b/device.x @@ -0,0 +1,197 @@ +PROVIDE(U0 = DefaultHandler); +PROVIDE(U1 = DefaultHandler); +PROVIDE(U2 = DefaultHandler); +PROVIDE(U3 = DefaultHandler); +PROVIDE(U4 = DefaultHandler); +PROVIDE(U5 = DefaultHandler); +PROVIDE(U6 = DefaultHandler); +PROVIDE(U7 = DefaultHandler); +PROVIDE(U8 = DefaultHandler); +PROVIDE(U9 = DefaultHandler); +PROVIDE(U10 = DefaultHandler); +PROVIDE(U11 = DefaultHandler); +PROVIDE(U12 = DefaultHandler); +PROVIDE(U13 = DefaultHandler); +PROVIDE(U14 = DefaultHandler); +PROVIDE(U15 = DefaultHandler); +PROVIDE(SPI0_TX = DefaultHandler); +PROVIDE(SPI0_RX = DefaultHandler); +PROVIDE(SPI1_TX = DefaultHandler); +PROVIDE(SPI1_RX = DefaultHandler); +PROVIDE(SPI2_TX = DefaultHandler); +PROVIDE(SPI2_RX = DefaultHandler); +PROVIDE(SPI3_TX = DefaultHandler); +PROVIDE(SPI3_RX = DefaultHandler); +PROVIDE(UART0_TX = DefaultHandler); +PROVIDE(UART0_RX = DefaultHandler); +PROVIDE(UART1_TX = DefaultHandler); +PROVIDE(UART1_RX = DefaultHandler); +PROVIDE(UART2_TX = DefaultHandler); +PROVIDE(UART2_RX = DefaultHandler); +PROVIDE(I2C0_MS = DefaultHandler); +PROVIDE(I2C0_SL = DefaultHandler); +PROVIDE(I2C1_MS = DefaultHandler); +PROVIDE(I2C1_SL = DefaultHandler); +PROVIDE(I2C2_MS = DefaultHandler); +PROVIDE(I2C2_SL = DefaultHandler); +PROVIDE(ETHERNET = DefaultHandler); +PROVIDE(U37 = DefaultHandler); +PROVIDE(SPW = DefaultHandler); +PROVIDE(U39 = DefaultHandler); +PROVIDE(DAC0 = DefaultHandler); +PROVIDE(DAC1 = DefaultHandler); +PROVIDE(TRNG = DefaultHandler); +PROVIDE(DMA_ERROR = DefaultHandler); +PROVIDE(ADC = DefaultHandler); +PROVIDE(LOCLK = DefaultHandler); +PROVIDE(LVD = DefaultHandler); +PROVIDE(WATCHDOG = DefaultHandler); +PROVIDE(TIM0 = DefaultHandler); +PROVIDE(TIM1 = DefaultHandler); +PROVIDE(TIM2 = DefaultHandler); +PROVIDE(TIM3 = DefaultHandler); +PROVIDE(TIM4 = DefaultHandler); +PROVIDE(TIM5 = DefaultHandler); +PROVIDE(TIM6 = DefaultHandler); +PROVIDE(TIM7 = DefaultHandler); +PROVIDE(TIM8 = DefaultHandler); +PROVIDE(TIM9 = DefaultHandler); +PROVIDE(TIM10 = DefaultHandler); +PROVIDE(TIM11 = DefaultHandler); +PROVIDE(TIM12 = DefaultHandler); +PROVIDE(TIM13 = DefaultHandler); +PROVIDE(TIM14 = DefaultHandler); +PROVIDE(TIM15 = DefaultHandler); +PROVIDE(TIM16 = DefaultHandler); +PROVIDE(TIM17 = DefaultHandler); +PROVIDE(TIM18 = DefaultHandler); +PROVIDE(TIM19 = DefaultHandler); +PROVIDE(TIM20 = DefaultHandler); +PROVIDE(TIM21 = DefaultHandler); +PROVIDE(TIM22 = DefaultHandler); +PROVIDE(TIM23 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(U73 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(U75 = DefaultHandler); +PROVIDE(EDAC_MBE = DefaultHandler); +PROVIDE(EDAC_SBE = DefaultHandler); +PROVIDE(PORTA0 = DefaultHandler); +PROVIDE(PORTA1 = DefaultHandler); +PROVIDE(PORTA2 = DefaultHandler); +PROVIDE(PORTA3 = DefaultHandler); +PROVIDE(PORTA4 = DefaultHandler); +PROVIDE(PORTA5 = DefaultHandler); +PROVIDE(PORTA6 = DefaultHandler); +PROVIDE(PORTA7 = DefaultHandler); +PROVIDE(PORTA8 = DefaultHandler); +PROVIDE(PORTA9 = DefaultHandler); +PROVIDE(PORTA10 = DefaultHandler); +PROVIDE(PORTA11 = DefaultHandler); +PROVIDE(PORTA12 = DefaultHandler); +PROVIDE(PORTA13 = DefaultHandler); +PROVIDE(PORTA14 = DefaultHandler); +PROVIDE(PORTA15 = DefaultHandler); +PROVIDE(PORTB0 = DefaultHandler); +PROVIDE(PORTB1 = DefaultHandler); +PROVIDE(PORTB2 = DefaultHandler); +PROVIDE(PORTB3 = DefaultHandler); +PROVIDE(PORTB4 = DefaultHandler); +PROVIDE(PORTB5 = DefaultHandler); +PROVIDE(PORTB6 = DefaultHandler); +PROVIDE(PORTB7 = DefaultHandler); +PROVIDE(PORTB8 = DefaultHandler); +PROVIDE(PORTB9 = DefaultHandler); +PROVIDE(PORTB10 = DefaultHandler); +PROVIDE(PORTB11 = DefaultHandler); +PROVIDE(PORTB12 = DefaultHandler); +PROVIDE(PORTB13 = DefaultHandler); +PROVIDE(PORTB14 = DefaultHandler); +PROVIDE(PORTB15 = DefaultHandler); +PROVIDE(PORTC0 = DefaultHandler); +PROVIDE(PORTC1 = DefaultHandler); +PROVIDE(PORTC2 = DefaultHandler); +PROVIDE(PORTC3 = DefaultHandler); +PROVIDE(PORTC4 = DefaultHandler); +PROVIDE(PORTC5 = DefaultHandler); +PROVIDE(PORTC6 = DefaultHandler); +PROVIDE(PORTC7 = DefaultHandler); +PROVIDE(PORTC8 = DefaultHandler); +PROVIDE(PORTC9 = DefaultHandler); +PROVIDE(PORTC10 = DefaultHandler); +PROVIDE(PORTC11 = DefaultHandler); +PROVIDE(PORTC12 = DefaultHandler); +PROVIDE(PORTC13 = DefaultHandler); +PROVIDE(PORTC14 = DefaultHandler); +PROVIDE(PORTC15 = DefaultHandler); +PROVIDE(PORTD0 = DefaultHandler); +PROVIDE(PORTD1 = DefaultHandler); +PROVIDE(PORTD2 = DefaultHandler); +PROVIDE(PORTD3 = DefaultHandler); +PROVIDE(PORTD4 = DefaultHandler); +PROVIDE(PORTD5 = DefaultHandler); +PROVIDE(PORTD6 = DefaultHandler); +PROVIDE(PORTD7 = DefaultHandler); +PROVIDE(PORTD8 = DefaultHandler); +PROVIDE(PORTD9 = DefaultHandler); +PROVIDE(PORTD10 = DefaultHandler); +PROVIDE(PORTD11 = DefaultHandler); +PROVIDE(PORTD12 = DefaultHandler); +PROVIDE(PORTD13 = DefaultHandler); +PROVIDE(PORTD14 = DefaultHandler); +PROVIDE(PORTD15 = DefaultHandler); +PROVIDE(PORTE0 = DefaultHandler); +PROVIDE(PORTE1 = DefaultHandler); +PROVIDE(PORTE2 = DefaultHandler); +PROVIDE(PORTE3 = DefaultHandler); +PROVIDE(PORTE4 = DefaultHandler); +PROVIDE(PORTE5 = DefaultHandler); +PROVIDE(PORTE6 = DefaultHandler); +PROVIDE(PORTE7 = DefaultHandler); +PROVIDE(PORTE8 = DefaultHandler); +PROVIDE(PORTE9 = DefaultHandler); +PROVIDE(PORTE10 = DefaultHandler); +PROVIDE(PORTE11 = DefaultHandler); +PROVIDE(PORTE12 = DefaultHandler); +PROVIDE(PORTE13 = DefaultHandler); +PROVIDE(PORTE14 = DefaultHandler); +PROVIDE(PORTE15 = DefaultHandler); +PROVIDE(PORTF0 = DefaultHandler); +PROVIDE(PORTF1 = DefaultHandler); +PROVIDE(PORTF2 = DefaultHandler); +PROVIDE(PORTF3 = DefaultHandler); +PROVIDE(PORTF4 = DefaultHandler); +PROVIDE(PORTF5 = DefaultHandler); +PROVIDE(PORTF6 = DefaultHandler); +PROVIDE(PORTF7 = DefaultHandler); +PROVIDE(PORTF8 = DefaultHandler); +PROVIDE(PORTF9 = DefaultHandler); +PROVIDE(PORTF10 = DefaultHandler); +PROVIDE(PORTF11 = DefaultHandler); +PROVIDE(PORTF12 = DefaultHandler); +PROVIDE(PORTF13 = DefaultHandler); +PROVIDE(PORTF14 = DefaultHandler); +PROVIDE(PORTF15 = DefaultHandler); +PROVIDE(DMA_ACTIVE0 = DefaultHandler); +PROVIDE(DMA_ACTIVE1 = DefaultHandler); +PROVIDE(DMA_ACTIVE2 = DefaultHandler); +PROVIDE(DMA_ACTIVE3 = DefaultHandler); +PROVIDE(DMA_DONE0 = DefaultHandler); +PROVIDE(DMA_DONE1 = DefaultHandler); +PROVIDE(DMA_DONE2 = DefaultHandler); +PROVIDE(DMA_DONE3 = DefaultHandler); +PROVIDE(I2C0_MS_RX = DefaultHandler); +PROVIDE(I2C0_MS_TX = DefaultHandler); +PROVIDE(I2C0_SL_RX = DefaultHandler); +PROVIDE(I2C0_SL_TX = DefaultHandler); +PROVIDE(I2C1_MS_RX = DefaultHandler); +PROVIDE(I2C1_MS_TX = DefaultHandler); +PROVIDE(I2C1_SL_RX = DefaultHandler); +PROVIDE(I2C1_SL_TX = DefaultHandler); +PROVIDE(I2C2_MS_RX = DefaultHandler); +PROVIDE(I2C2_MS_TX = DefaultHandler); +PROVIDE(I2C2_SL_RX = DefaultHandler); +PROVIDE(I2C2_SL_TX = DefaultHandler); +PROVIDE(FPU = DefaultHandler); +PROVIDE(TXEV = DefaultHandler); + diff --git a/gen-helper.sh b/gen-helper.sh new file mode 100755 index 0000000..635e214 --- /dev/null +++ b/gen-helper.sh @@ -0,0 +1,21 @@ +#!/bin/sh + +# Use installed tool by default +svd2rust_bin="svd2rust" +# Automates the steps specified in https://docs.rs/svd2rust/0.19.0/svd2rust/ +if [ -f svd2rust ]; then + # If the local directory contains svd2rust, use that version instead + svd2rust_bin="./svd2rust" +elif [ -f ../svd2rust ]; then + # Keeps the repository clean + svd2rust_bin="../svd2rust" +fi +if [ -x "$(${svd2rust_bin} --version)" ]; then + echo "No svd2rust found locally or installed." \ + "Install it with cargo install svd2rust" + exit +fi +${svd2rust_bin} -i svd/va416xx-base.svd +rm -rf src +form -i lib.rs -o src/ && rm lib.rs +cargo fmt diff --git a/src/adc.rs b/src/adc.rs new file mode 100644 index 0000000..3d2d2cc --- /dev/null +++ b/src/adc.rs @@ -0,0 +1,65 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control Register"] + pub ctrl: crate::Reg, + #[doc = "0x04 - FIFO data"] + pub fifo_data: crate::Reg, + #[doc = "0x08 - Status"] + pub status: crate::Reg, + #[doc = "0x0c - Interrupt Enable"] + pub irq_enb: crate::Reg, + #[doc = "0x10 - Raw Interrupt Status"] + pub irq_raw: crate::Reg, + #[doc = "0x14 - Enabled Interrupt Status"] + pub irq_end: crate::Reg, + #[doc = "0x18 - Clear Interrupt"] + pub irq_clr: crate::Reg, + #[doc = "0x1c - Receive FIFO Interrupt Trigger Value"] + pub rxfifoirqtrg: crate::Reg, + #[doc = "0x20 - FIFO Clear"] + pub fifo_clr: crate::Reg, + _reserved9: [u8; 0x0fd8], + #[doc = "0xffc - Peripheral ID Register"] + pub perid: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "FIFO_DATA register accessor: an alias for `Reg`"] +pub type FIFO_DATA = crate::Reg; +#[doc = "FIFO data"] +pub mod fifo_data; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "IRQ_ENB register accessor: an alias for `Reg`"] +pub type IRQ_ENB = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod irq_enb; +#[doc = "IRQ_RAW register accessor: an alias for `Reg`"] +pub type IRQ_RAW = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END register accessor: an alias for `Reg`"] +pub type IRQ_END = crate::Reg; +#[doc = "Enabled Interrupt Status"] +pub mod irq_end; +#[doc = "IRQ_CLR register accessor: an alias for `Reg`"] +pub type IRQ_CLR = crate::Reg; +#[doc = "Clear Interrupt"] +pub mod irq_clr; +#[doc = "RXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type RXFIFOIRQTRG = crate::Reg; +#[doc = "Receive FIFO Interrupt Trigger Value"] +pub mod rxfifoirqtrg; +#[doc = "FIFO_CLR register accessor: an alias for `Reg`"] +pub type FIFO_CLR = crate::Reg; +#[doc = "FIFO Clear"] +pub mod fifo_clr; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/adc/ctrl.rs b/src/adc/ctrl.rs new file mode 100644 index 0000000..358a959 --- /dev/null +++ b/src/adc/ctrl.rs @@ -0,0 +1,328 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CONV_CNT` reader - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] +pub struct CONV_CNT_R(crate::FieldReader); +impl CONV_CNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CONV_CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CONV_CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CONV_CNT` writer - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] +pub struct CONV_CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CONV_CNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 20)) | ((value as u32 & 0x0f) << 20); + self.w + } +} +#[doc = "Field `MANUAL_TRIG` reader - Starts analog acquisition"] +pub struct MANUAL_TRIG_R(crate::FieldReader); +impl MANUAL_TRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MANUAL_TRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANUAL_TRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MANUAL_TRIG` writer - Starts analog acquisition"] +pub struct MANUAL_TRIG_W<'a> { + w: &'a mut W, +} +impl<'a> MANUAL_TRIG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `EXT_TRIG_EN` reader - Allows the external trigger to start analog acquisition"] +pub struct EXT_TRIG_EN_R(crate::FieldReader); +impl EXT_TRIG_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_TRIG_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_TRIG_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT_TRIG_EN` writer - Allows the external trigger to start analog acquisition"] +pub struct EXT_TRIG_EN_W<'a> { + w: &'a mut W, +} +impl<'a> EXT_TRIG_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SWEEP_EN` reader - ADC data acquisition for all enabled channel"] +pub struct SWEEP_EN_R(crate::FieldReader); +impl SWEEP_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWEEP_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWEEP_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWEEP_EN` writer - ADC data acquisition for all enabled channel"] +pub struct SWEEP_EN_W<'a> { + w: &'a mut W, +} +impl<'a> SWEEP_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `CHAN_TAG_EN` reader - Enables the channel tag to be saved with the ADC data"] +pub struct CHAN_TAG_EN_R(crate::FieldReader); +impl CHAN_TAG_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CHAN_TAG_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHAN_TAG_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHAN_TAG_EN` writer - Enables the channel tag to be saved with the ADC data"] +pub struct CHAN_TAG_EN_W<'a> { + w: &'a mut W, +} +impl<'a> CHAN_TAG_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `CHAN_EN` reader - Enables the channel for data collection"] +pub struct CHAN_EN_R(crate::FieldReader); +impl CHAN_EN_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CHAN_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHAN_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHAN_EN` writer - Enables the channel for data collection"] +pub struct CHAN_EN_W<'a> { + w: &'a mut W, +} +impl<'a> CHAN_EN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] + #[inline(always)] + pub fn conv_cnt(&self) -> CONV_CNT_R { + CONV_CNT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bit 19 - Starts analog acquisition"] + #[inline(always)] + pub fn manual_trig(&self) -> MANUAL_TRIG_R { + MANUAL_TRIG_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"] + #[inline(always)] + pub fn ext_trig_en(&self) -> EXT_TRIG_EN_R { + EXT_TRIG_EN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC data acquisition for all enabled channel"] + #[inline(always)] + pub fn sweep_en(&self) -> SWEEP_EN_R { + SWEEP_EN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"] + #[inline(always)] + pub fn chan_tag_en(&self) -> CHAN_TAG_EN_R { + CHAN_TAG_EN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 0:15 - Enables the channel for data collection"] + #[inline(always)] + pub fn chan_en(&self) -> CHAN_EN_R { + CHAN_EN_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] + #[inline(always)] + pub fn conv_cnt(&mut self) -> CONV_CNT_W { + CONV_CNT_W { w: self } + } + #[doc = "Bit 19 - Starts analog acquisition"] + #[inline(always)] + pub fn manual_trig(&mut self) -> MANUAL_TRIG_W { + MANUAL_TRIG_W { w: self } + } + #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"] + #[inline(always)] + pub fn ext_trig_en(&mut self) -> EXT_TRIG_EN_W { + EXT_TRIG_EN_W { w: self } + } + #[doc = "Bit 17 - ADC data acquisition for all enabled channel"] + #[inline(always)] + pub fn sweep_en(&mut self) -> SWEEP_EN_W { + SWEEP_EN_W { w: self } + } + #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"] + #[inline(always)] + pub fn chan_tag_en(&mut self) -> CHAN_TAG_EN_W { + CHAN_TAG_EN_W { w: self } + } + #[doc = "Bits 0:15 - Enables the channel for data collection"] + #[inline(always)] + pub fn chan_en(&mut self) -> CHAN_EN_W { + CHAN_EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/adc/fifo_clr.rs b/src/adc/fifo_clr.rs new file mode 100644 index 0000000..4cacd77 --- /dev/null +++ b/src/adc/fifo_clr.rs @@ -0,0 +1,72 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FIFO_CLR` writer - Clears the ADC FIFO. Always reads 0"] +pub struct FIFO_CLR_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_CLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Clears the ADC FIFO. Always reads 0"] + #[inline(always)] + pub fn fifo_clr(&mut self) -> FIFO_CLR_W { + FIFO_CLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIFO Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_clr](index.html) module"] +pub struct FIFO_CLR_SPEC; +impl crate::RegisterSpec for FIFO_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [fifo_clr::W](W) writer structure"] +impl crate::Writable for FIFO_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FIFO_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/adc/fifo_data.rs b/src/adc/fifo_data.rs new file mode 100644 index 0000000..dd00713 --- /dev/null +++ b/src/adc/fifo_data.rs @@ -0,0 +1,73 @@ +#[doc = "Register `FIFO_DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHAN_TAG` reader - If enabled, this will include the number of the channel corresponding to the measurement"] +pub struct CHAN_TAG_R(crate::FieldReader); +impl CHAN_TAG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHAN_TAG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHAN_TAG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC_DATA` reader - ADC acquisition data from the FIFO"] +pub struct ADC_DATA_R(crate::FieldReader); +impl ADC_DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADC_DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 12:15 - If enabled, this will include the number of the channel corresponding to the measurement"] + #[inline(always)] + pub fn chan_tag(&self) -> CHAN_TAG_R { + CHAN_TAG_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 0:11 - ADC acquisition data from the FIFO"] + #[inline(always)] + pub fn adc_data(&self) -> ADC_DATA_R { + ADC_DATA_R::new((self.bits & 0x0fff) as u16) + } +} +#[doc = "FIFO data\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_data](index.html) module"] +pub struct FIFO_DATA_SPEC; +impl crate::RegisterSpec for FIFO_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fifo_data::R](R) reader structure"] +impl crate::Readable for FIFO_DATA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FIFO_DATA to value 0"] +impl crate::Resettable for FIFO_DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/adc/irq_clr.rs b/src/adc/irq_clr.rs new file mode 100644 index 0000000..1594779 --- /dev/null +++ b/src/adc/irq_clr.rs @@ -0,0 +1,153 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRIG_ERROR` writer - Clears the trigger error interrupt status. Always reads 0"] +pub struct TRIG_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> TRIG_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ADC_DONE` writer - Clears the ADC done interrupt status. Always reads 0"] +pub struct ADC_DONE_W<'a> { + w: &'a mut W, +} +impl<'a> ADC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FIFO_UFLOW` writer - Clears the FIFO underflow interrupt status. Always reads 0"] +pub struct FIFO_UFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_UFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FIFO_OFLOW` writer - Clears the FIFO overflow interrupt status. Always reads 0"] +pub struct FIFO_OFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_OFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"] + #[inline(always)] + pub fn trig_error(&mut self) -> TRIG_ERROR_W { + TRIG_ERROR_W { w: self } + } + #[doc = "Bit 2 - Clears the ADC done interrupt status. Always reads 0"] + #[inline(always)] + pub fn adc_done(&mut self) -> ADC_DONE_W { + ADC_DONE_W { w: self } + } + #[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"] + #[inline(always)] + pub fn fifo_uflow(&mut self) -> FIFO_UFLOW_W { + FIFO_UFLOW_W { w: self } + } + #[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"] + #[inline(always)] + pub fn fifo_oflow(&mut self) -> FIFO_OFLOW_W { + FIFO_OFLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear Interrupt\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"] +pub struct IRQ_CLR_SPEC; +impl crate::RegisterSpec for IRQ_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"] +impl crate::Writable for IRQ_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IRQ_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/adc/irq_enb.rs b/src/adc/irq_enb.rs new file mode 100644 index 0000000..7130c8c --- /dev/null +++ b/src/adc/irq_enb.rs @@ -0,0 +1,395 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_ENB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub struct FIFO_DEPTH_TRIG_R(crate::FieldReader); +impl FIFO_DEPTH_TRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_DEPTH_TRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_DEPTH_TRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub struct FIFO_DEPTH_TRIG_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_DEPTH_TRIG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"] +pub struct TRIG_ERROR_R(crate::FieldReader); +impl TRIG_ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRIG_ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIG_ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"] +pub struct TRIG_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> TRIG_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `ADC_DONE` reader - Enables the interrupt for an ADC data acquisition completion"] +pub struct ADC_DONE_R(crate::FieldReader); +impl ADC_DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC_DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC_DONE` writer - Enables the interrupt for an ADC data acquisition completion"] +pub struct ADC_DONE_W<'a> { + w: &'a mut W, +} +impl<'a> ADC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"] +pub struct FIFO_UFLOW_R(crate::FieldReader); +impl FIFO_UFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_UFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_UFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"] +pub struct FIFO_UFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_UFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"] +pub struct FIFO_OFLOW_R(crate::FieldReader); +impl FIFO_OFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_OFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_OFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"] +pub struct FIFO_OFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_OFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"] +pub struct FIFO_FULL_R(crate::FieldReader); +impl FIFO_FULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_FULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_FULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"] +pub struct FIFO_FULL_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"] +pub struct FIFO_EMPTY_R(crate::FieldReader); +impl FIFO_EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"] +pub struct FIFO_EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FIFO_DEPTH_TRIG_R { + FIFO_DEPTH_TRIG_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&self) -> TRIG_ERROR_R { + TRIG_ERROR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"] + #[inline(always)] + pub fn adc_done(&self) -> ADC_DONE_R { + ADC_DONE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FIFO_UFLOW_R { + FIFO_UFLOW_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FIFO_OFLOW_R { + FIFO_OFLOW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&self) -> FIFO_FULL_R { + FIFO_FULL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&mut self) -> FIFO_DEPTH_TRIG_W { + FIFO_DEPTH_TRIG_W { w: self } + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&mut self) -> TRIG_ERROR_W { + TRIG_ERROR_W { w: self } + } + #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"] + #[inline(always)] + pub fn adc_done(&mut self) -> ADC_DONE_W { + ADC_DONE_W { w: self } + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&mut self) -> FIFO_UFLOW_W { + FIFO_UFLOW_W { w: self } + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&mut self) -> FIFO_OFLOW_W { + FIFO_OFLOW_W { w: self } + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&mut self) -> FIFO_FULL_W { + FIFO_FULL_W { w: self } + } + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&mut self) -> FIFO_EMPTY_W { + FIFO_EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"] +pub struct IRQ_ENB_SPEC; +impl crate::RegisterSpec for IRQ_ENB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_enb::R](R) reader structure"] +impl crate::Readable for IRQ_ENB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"] +impl crate::Writable for IRQ_ENB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IRQ_ENB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/adc/irq_end.rs b/src/adc/irq_end.rs new file mode 100644 index 0000000..30c7f42 --- /dev/null +++ b/src/adc/irq_end.rs @@ -0,0 +1,173 @@ +#[doc = "Register `IRQ_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub struct FIFO_DEPTH_TRIG_R(crate::FieldReader); +impl FIFO_DEPTH_TRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_DEPTH_TRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_DEPTH_TRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"] +pub struct TRIG_ERROR_R(crate::FieldReader); +impl TRIG_ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRIG_ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIG_ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done and the interrupt is enabled"] +pub struct ADC_DONE_R(crate::FieldReader); +impl ADC_DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC_DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_UFLOW` reader - Indicates a FIFO underflow occurred and the interrupt is enabled"] +pub struct FIFO_UFLOW_R(crate::FieldReader); +impl FIFO_UFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_UFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_UFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred and the interrupt is enabled"] +pub struct FIFO_OFLOW_R(crate::FieldReader); +impl FIFO_OFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_OFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_OFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full and the interrupt is enabled"] +pub struct FIFO_FULL_R(crate::FieldReader); +impl FIFO_FULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_FULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_FULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty and the interrupt is enabled"] +pub struct FIFO_EMPTY_R(crate::FieldReader); +impl FIFO_EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FIFO_DEPTH_TRIG_R { + FIFO_DEPTH_TRIG_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"] + #[inline(always)] + pub fn trig_error(&self) -> TRIG_ERROR_R { + TRIG_ERROR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Indicates that a ADC conversion is done and the interrupt is enabled"] + #[inline(always)] + pub fn adc_done(&self) -> ADC_DONE_R { + ADC_DONE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Indicates a FIFO underflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FIFO_UFLOW_R { + FIFO_UFLOW_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FIFO_OFLOW_R { + FIFO_OFLOW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_full(&self) -> FIFO_FULL_R { + FIFO_FULL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Indicates the FIFO is empty and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Enabled Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"] +pub struct IRQ_END_SPEC; +impl crate::RegisterSpec for IRQ_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_end::R](R) reader structure"] +impl crate::Readable for IRQ_END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IRQ_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/adc/irq_raw.rs b/src/adc/irq_raw.rs new file mode 100644 index 0000000..877b658 --- /dev/null +++ b/src/adc/irq_raw.rs @@ -0,0 +1,173 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub struct FIFO_DEPTH_TRIG_R(crate::FieldReader); +impl FIFO_DEPTH_TRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_DEPTH_TRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_DEPTH_TRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"] +pub struct TRIG_ERROR_R(crate::FieldReader); +impl TRIG_ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRIG_ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIG_ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done"] +pub struct ADC_DONE_R(crate::FieldReader); +impl ADC_DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC_DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_UFLOW` reader - Indicates data was unavailable when a new trigger for ADC update is received"] +pub struct FIFO_UFLOW_R(crate::FieldReader); +impl FIFO_UFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_UFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_UFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] +pub struct FIFO_OFLOW_R(crate::FieldReader); +impl FIFO_OFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_OFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_OFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full"] +pub struct FIFO_FULL_R(crate::FieldReader); +impl FIFO_FULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_FULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_FULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty"] +pub struct FIFO_EMPTY_R(crate::FieldReader); +impl FIFO_EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FIFO_DEPTH_TRIG_R { + FIFO_DEPTH_TRIG_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"] + #[inline(always)] + pub fn trig_error(&self) -> TRIG_ERROR_R { + TRIG_ERROR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Indicates that a ADC conversion is done"] + #[inline(always)] + pub fn adc_done(&self) -> ADC_DONE_R { + ADC_DONE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Indicates data was unavailable when a new trigger for ADC update is received"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FIFO_UFLOW_R { + FIFO_UFLOW_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FIFO_OFLOW_R { + FIFO_OFLOW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full"] + #[inline(always)] + pub fn fifo_full(&self) -> FIFO_FULL_R { + FIFO_FULL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Indicates the FIFO is empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Raw Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"] +pub struct IRQ_RAW_SPEC; +impl crate::RegisterSpec for IRQ_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_raw::R](R) reader structure"] +impl crate::Readable for IRQ_RAW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_RAW to value 0x01"] +impl crate::Resettable for IRQ_RAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/src/adc/perid.rs b/src/adc/perid.rs new file mode 100644 index 0000000..a7f3c64 --- /dev/null +++ b/src/adc/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0019_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0019_07e9 + } +} diff --git a/src/adc/rxfifoirqtrg.rs b/src/adc/rxfifoirqtrg.rs new file mode 100644 index 0000000..f428ea9 --- /dev/null +++ b/src/adc/rxfifoirqtrg.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEVEL` reader - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Receive FIFO Interrupt Trigger Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifoirqtrg](index.html) module"] +pub struct RXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for RXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxfifoirqtrg::R](R) reader structure"] +impl crate::Readable for RXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxfifoirqtrg::W](W) writer structure"] +impl crate::Writable for RXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0x10"] +impl crate::Resettable for RXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/src/adc/status.rs b/src/adc/status.rs new file mode 100644 index 0000000..7347c13 --- /dev/null +++ b/src/adc/status.rs @@ -0,0 +1,73 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ADC_BUSY` reader - Indicates an ADC data acquisition is in process"] +pub struct ADC_BUSY_R(crate::FieldReader); +impl ADC_BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC_BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_ENTRY_CNT` reader - Indicates the number of entries in the FIFO"] +pub struct FIFO_ENTRY_CNT_R(crate::FieldReader); +impl FIFO_ENTRY_CNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIFO_ENTRY_CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_ENTRY_CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Indicates an ADC data acquisition is in process"] + #[inline(always)] + pub fn adc_busy(&self) -> ADC_BUSY_R { + ADC_BUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 0:5 - Indicates the number of entries in the FIFO"] + #[inline(always)] + pub fn fifo_entry_cnt(&self) -> FIFO_ENTRY_CNT_R { + FIFO_ENTRY_CNT_R::new((self.bits & 0x3f) as u8) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0.rs b/src/can0.rs new file mode 100644 index 0000000..62ec834 --- /dev/null +++ b/src/can0.rs @@ -0,0 +1,856 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Buffer Status / Control Register"] + pub cnstat_cmb0: crate::Reg, + #[doc = "0x04 - CAN Frame Timestamp"] + pub tstp_cmb0: crate::Reg, + #[doc = "0x08 - CAN Frame Data Word 3"] + pub data3_cmb0: crate::Reg, + #[doc = "0x0c - CAN Frame Data Word 2"] + pub data2_cmb0: crate::Reg, + #[doc = "0x10 - CAN Frame Data Word 1"] + pub data1_cmb0: crate::Reg, + #[doc = "0x14 - CAN Frame Data Word 0"] + pub data0_cmb0: crate::Reg, + #[doc = "0x18 - CAN Frame Identifier Word 0"] + pub id0_cmb0: crate::Reg, + #[doc = "0x1c - CAN Frame Identifier Word 1"] + pub id1_cmb0: crate::Reg, + #[doc = "0x20 - Buffer Status / Control Register"] + pub cnstat_cmb1: crate::Reg, + #[doc = "0x24 - CAN Frame Timestamp"] + pub tstp_cmb1: crate::Reg, + #[doc = "0x28 - CAN Frame Data Word 3"] + pub data3_cmb1: crate::Reg, + #[doc = "0x2c - CAN Frame Data Word 2"] + pub data2_cmb1: crate::Reg, + #[doc = "0x30 - CAN Frame Data Word 2"] + pub data1_cmb1: crate::Reg, + #[doc = "0x34 - CAN Frame Data Word 0"] + pub data0_cmb1: crate::Reg, + #[doc = "0x38 - CAN Frame Identifier Word 0"] + pub id0_cmb1: crate::Reg, + #[doc = "0x3c - CAN Frame Identifier Word 1"] + pub id1_cmb1: crate::Reg, + #[doc = "0x40 - Buffer Status / Control Register"] + pub cnstat_cmb2: crate::Reg, + #[doc = "0x44 - CAN Frame Timestamp"] + pub tstp_cmb2: crate::Reg, + #[doc = "0x48 - CAN Frame Data Word 3"] + pub data3_cmb2: crate::Reg, + #[doc = "0x4c - CAN Frame Data Word 2"] + pub data2_cmb2: crate::Reg, + #[doc = "0x50 - CAN Frame Data Word 2"] + pub data1_cmb2: crate::Reg, + #[doc = "0x54 - CAN Frame Data Word 0"] + pub data0_cmb2: crate::Reg, + #[doc = "0x58 - CAN Frame Identifier Word 0"] + pub id0_cmb2: crate::Reg, + #[doc = "0x5c - CAN Frame Identifier Word 1"] + pub id1_cmb2: crate::Reg, + #[doc = "0x60 - Buffer Status / Control Register"] + pub cnstat_cmb3: crate::Reg, + #[doc = "0x64 - CAN Frame Timestamp"] + pub tstp_cmb3: crate::Reg, + #[doc = "0x68 - CAN Frame Data Word 3"] + pub data3_cmb3: crate::Reg, + #[doc = "0x6c - CAN Frame Data Word 2"] + pub data2_cmb3: crate::Reg, + #[doc = "0x70 - CAN Frame Data Word 2"] + pub data1_cmb3: crate::Reg, + #[doc = "0x74 - CAN Frame Data Word 0"] + pub data0_cmb3: crate::Reg, + #[doc = "0x78 - CAN Frame Identifier Word 0"] + pub id0_cmb3: crate::Reg, + #[doc = "0x7c - CAN Frame Identifier Word 1"] + pub id1_cmb3: crate::Reg, + #[doc = "0x80 - Buffer Status / Control Register"] + pub cnstat_cmb4: crate::Reg, + #[doc = "0x84 - CAN Frame Timestamp"] + pub tstp_cmb4: crate::Reg, + #[doc = "0x88 - CAN Frame Data Word 3"] + pub data3_cmb4: crate::Reg, + #[doc = "0x8c - CAN Frame Data Word 2"] + pub data2_cmb4: crate::Reg, + #[doc = "0x90 - CAN Frame Data Word 2"] + pub data1_cmb4: crate::Reg, + #[doc = "0x94 - CAN Frame Data Word 0"] + pub data0_cmb4: crate::Reg, + #[doc = "0x98 - CAN Frame Identifier Word 0"] + pub id0_cmb4: crate::Reg, + #[doc = "0x9c - CAN Frame Identifier Word 1"] + pub id1_cmb4: crate::Reg, + #[doc = "0xa0 - Buffer Status / Control Register"] + pub cnstat_cmb5: crate::Reg, + #[doc = "0xa4 - CAN Frame Timestamp"] + pub tstp_cmb5: crate::Reg, + #[doc = "0xa8 - CAN Frame Data Word 3"] + pub data3_cmb5: crate::Reg, + #[doc = "0xac - CAN Frame Data Word 2"] + pub data2_cmb5: crate::Reg, + #[doc = "0xb0 - CAN Frame Data Word 2"] + pub data1_cmb5: crate::Reg, + #[doc = "0xb4 - CAN Frame Data Word 0"] + pub data0_cmb5: crate::Reg, + #[doc = "0xb8 - CAN Frame Identifier Word 0"] + pub id0_cmb5: crate::Reg, + #[doc = "0xbc - CAN Frame Identifier Word 1"] + pub id1_cmb5: crate::Reg, + #[doc = "0xc0 - Buffer Status / Control Register"] + pub cnstat_cmb6: crate::Reg, + #[doc = "0xc4 - CAN Frame Timestamp"] + pub tstp_cmb6: crate::Reg, + #[doc = "0xc8 - CAN Frame Data Word 3"] + pub data3_cmb6: crate::Reg, + #[doc = "0xcc - CAN Frame Data Word 2"] + pub data2_cmb6: crate::Reg, + #[doc = "0xd0 - CAN Frame Data Word 2"] + pub data1_cmb6: crate::Reg, + #[doc = "0xd4 - CAN Frame Data Word 0"] + pub data0_cmb6: crate::Reg, + #[doc = "0xd8 - CAN Frame Identifier Word 0"] + pub id0_cmb6: crate::Reg, + #[doc = "0xdc - CAN Frame Identifier Word 1"] + pub id1_cmb6: crate::Reg, + #[doc = "0xe0 - Buffer Status / Control Register"] + pub cnstat_cmb7: crate::Reg, + #[doc = "0xe4 - CAN Frame Timestamp"] + pub tstp_cmb7: crate::Reg, + #[doc = "0xe8 - CAN Frame Data Word 3"] + pub data3_cmb7: crate::Reg, + #[doc = "0xec - CAN Frame Data Word 2"] + pub data2_cmb7: crate::Reg, + #[doc = "0xf0 - CAN Frame Data Word 2"] + pub data1_cmb7: crate::Reg, + #[doc = "0xf4 - CAN Frame Data Word 0"] + pub data0_cmb7: crate::Reg, + #[doc = "0xf8 - CAN Frame Identifier Word 0"] + pub id0_cmb7: crate::Reg, + #[doc = "0xfc - CAN Frame Identifier Word 1"] + pub id1_cmb7: crate::Reg, + #[doc = "0x100 - Buffer Status / Control Register"] + pub cnstat_cmb8: crate::Reg, + #[doc = "0x104 - CAN Frame Timestamp"] + pub tstp_cmb8: crate::Reg, + #[doc = "0x108 - CAN Frame Data Word 3"] + pub data3_cmb8: crate::Reg, + #[doc = "0x10c - CAN Frame Data Word 2"] + pub data2_cmb8: crate::Reg, + #[doc = "0x110 - CAN Frame Data Word 2"] + pub data1_cmb8: crate::Reg, + #[doc = "0x114 - CAN Frame Data Word 0"] + pub data0_cmb8: crate::Reg, + #[doc = "0x118 - CAN Frame Identifier Word 0"] + pub id0_cmb8: crate::Reg, + #[doc = "0x11c - CAN Frame Identifier Word 1"] + pub id1_cmb8: crate::Reg, + #[doc = "0x120 - Buffer Status / Control Register"] + pub cnstat_cmb9: crate::Reg, + #[doc = "0x124 - CAN Frame Timestamp"] + pub tstp_cmb9: crate::Reg, + #[doc = "0x128 - CAN Frame Data Word 3"] + pub data3_cmb9: crate::Reg, + #[doc = "0x12c - CAN Frame Data Word 2"] + pub data2_cmb9: crate::Reg, + #[doc = "0x130 - CAN Frame Data Word 2"] + pub data1_cmb9: crate::Reg, + #[doc = "0x134 - CAN Frame Data Word 0"] + pub data0_cmb9: crate::Reg, + #[doc = "0x138 - CAN Frame Identifier Word 0"] + pub id0_cmb9: crate::Reg, + #[doc = "0x13c - CAN Frame Identifier Word 1"] + pub id1_cmb9: crate::Reg, + #[doc = "0x140 - Buffer Status / Control Register"] + pub cnstat_cmb10: crate::Reg, + #[doc = "0x144 - CAN Frame Timestamp"] + pub tstp_cmb10: crate::Reg, + #[doc = "0x148 - CAN Frame Data Word 3"] + pub data3_cmb10: crate::Reg, + #[doc = "0x14c - CAN Frame Data Word 2"] + pub data2_cmb10: crate::Reg, + #[doc = "0x150 - CAN Frame Data Word 2"] + pub data1_cmb10: crate::Reg, + #[doc = "0x154 - CAN Frame Data Word 0"] + pub data0_cmb10: crate::Reg, + #[doc = "0x158 - CAN Frame Identifier Word 0"] + pub id0_cmb10: crate::Reg, + #[doc = "0x15c - CAN Frame Identifier Word 1"] + pub id1_cmb10: crate::Reg, + #[doc = "0x160 - Buffer Status / Control Register"] + pub cnstat_cmb11: crate::Reg, + #[doc = "0x164 - CAN Frame Timestamp"] + pub tstp_cmb11: crate::Reg, + #[doc = "0x168 - CAN Frame Data Word 3"] + pub data3_cmb11: crate::Reg, + #[doc = "0x16c - CAN Frame Data Word 2"] + pub data2_cmb11: crate::Reg, + #[doc = "0x170 - CAN Frame Data Word 2"] + pub data1_cmb11: crate::Reg, + #[doc = "0x174 - CAN Frame Data Word 0"] + pub data0_cmb11: crate::Reg, + #[doc = "0x178 - CAN Frame Identifier Word 0"] + pub id0_cmb11: crate::Reg, + #[doc = "0x17c - CAN Frame Identifier Word 1"] + pub id1_cmb11: crate::Reg, + #[doc = "0x180 - Buffer Status / Control Register"] + pub cnstat_cmb12: crate::Reg, + #[doc = "0x184 - CAN Frame Timestamp"] + pub tstp_cmb12: crate::Reg, + #[doc = "0x188 - CAN Frame Data Word 3"] + pub data3_cmb12: crate::Reg, + #[doc = "0x18c - CAN Frame Data Word 2"] + pub data2_cmb12: crate::Reg, + #[doc = "0x190 - CAN Frame Data Word 2"] + pub data1_cmb12: crate::Reg, + #[doc = "0x194 - CAN Frame Data Word 0"] + pub data0_cmb12: crate::Reg, + #[doc = "0x198 - CAN Frame Identifier Word 0"] + pub id0_cmb12: crate::Reg, + #[doc = "0x19c - CAN Frame Identifier Word 1"] + pub id1_cmb12: crate::Reg, + #[doc = "0x1a0 - Buffer Status / Control Register"] + pub cnstat_cmb13: crate::Reg, + #[doc = "0x1a4 - CAN Frame Timestamp"] + pub tstp_cmb13: crate::Reg, + #[doc = "0x1a8 - CAN Frame Data Word 3"] + pub data3_cmb13: crate::Reg, + #[doc = "0x1ac - CAN Frame Data Word 2"] + pub data2_cmb13: crate::Reg, + #[doc = "0x1b0 - CAN Frame Data Word 2"] + pub data1_cmb13: crate::Reg, + #[doc = "0x1b4 - CAN Frame Data Word 0"] + pub data0_cmb13: crate::Reg, + #[doc = "0x1b8 - CAN Frame Identifier Word 0"] + pub id0_cmb13: crate::Reg, + #[doc = "0x1bc - CAN Frame Identifier Word 1"] + pub id1_cmb13: crate::Reg, + #[doc = "0x1c0 - Buffer Status / Control Register"] + pub cnstat_cmb14: crate::Reg, + #[doc = "0x1c4 - CAN Frame Timestamp"] + pub tstp_cmb14: crate::Reg, + #[doc = "0x1c8 - CAN Frame Data Word 3"] + pub data3_cmb14: crate::Reg, + #[doc = "0x1cc - CAN Frame Data Word 2"] + pub data2_cmb14: crate::Reg, + #[doc = "0x1d0 - CAN Frame Data Word 2"] + pub data1_cmb14: crate::Reg, + #[doc = "0x1d4 - CAN Frame Data Word 0"] + pub data0_cmb14: crate::Reg, + #[doc = "0x1d8 - CAN Frame Identifier Word 0"] + pub id0_cmb14: crate::Reg, + #[doc = "0x1dc - CAN Frame Identifier Word 1"] + pub id1_cmb14: crate::Reg, + #[doc = "0x1e0 - Buffer Status / Control Register"] + pub cnstat_hcmb: crate::Reg, + #[doc = "0x1e4 - CAN Frame Timestamp"] + pub tstp_hcmb: crate::Reg, + #[doc = "0x1e8 - CAN Frame Data Word 3"] + pub data3_hcmb: crate::Reg, + #[doc = "0x1ec - CAN Frame Data Word 2"] + pub data2_hcmb: crate::Reg, + #[doc = "0x1f0 - CAN Frame Data Word 2"] + pub data1_hcmb: crate::Reg, + #[doc = "0x1f4 - CAN Frame Data Word 0"] + pub data0_hcmb: crate::Reg, + #[doc = "0x1f8 - CAN Frame Identifier Word 0"] + pub id0_hcmb: crate::Reg, + #[doc = "0x1fc - CAN Frame Identifier Word 1"] + pub id1_hcmb: crate::Reg, + #[doc = "0x200 - CAN Global Configuration Register"] + pub cgcr: crate::Reg, + #[doc = "0x204 - CAN Timing Register"] + pub ctim: crate::Reg, + #[doc = "0x208 - CAN Global Mask Extension"] + pub gmskx: crate::Reg, + #[doc = "0x20c - CAN Global Mask Base"] + pub gmskb: crate::Reg, + #[doc = "0x210 - CAN Basic Mask Extension"] + pub bmskx: crate::Reg, + #[doc = "0x214 - CAN Basic Mask Base"] + pub bmskb: crate::Reg, + #[doc = "0x218 - CAN Interrupt Enable Register"] + pub cien: crate::Reg, + #[doc = "0x21c - CAN Interrupt Pending Register"] + pub cipnd: crate::Reg, + #[doc = "0x220 - CAN Interrupt Clear Register"] + pub ciclr: crate::Reg, + #[doc = "0x224 - CAN Interrupt Code Enable Register"] + pub cicen: crate::Reg, + #[doc = "0x228 - CAN Status Pending Register"] + pub cstpnd: crate::Reg, + #[doc = "0x22c - CAN Error Counter Register"] + pub canec: crate::Reg, + #[doc = "0x230 - CAN Error Diagnostic Register"] + pub cediag: crate::Reg, + #[doc = "0x234 - CAN Timer Register"] + pub ctmr: crate::Reg, +} +#[doc = "CNSTAT_CMB0 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB0 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb0; +#[doc = "TSTP_CMB0 register accessor: an alias for `Reg`"] +pub type TSTP_CMB0 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb0; +#[doc = "DATA3_CMB0 register accessor: an alias for `Reg`"] +pub type DATA3_CMB0 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb0; +#[doc = "DATA2_CMB0 register accessor: an alias for `Reg`"] +pub type DATA2_CMB0 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb0; +#[doc = "DATA1_CMB0 register accessor: an alias for `Reg`"] +pub type DATA1_CMB0 = crate::Reg; +#[doc = "CAN Frame Data Word 1"] +pub mod data1_cmb0; +#[doc = "DATA0_CMB0 register accessor: an alias for `Reg`"] +pub type DATA0_CMB0 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb0; +#[doc = "ID0_CMB0 register accessor: an alias for `Reg`"] +pub type ID0_CMB0 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb0; +#[doc = "ID1_CMB0 register accessor: an alias for `Reg`"] +pub type ID1_CMB0 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb0; +#[doc = "CNSTAT_CMB1 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB1 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb1; +#[doc = "TSTP_CMB1 register accessor: an alias for `Reg`"] +pub type TSTP_CMB1 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb1; +#[doc = "DATA3_CMB1 register accessor: an alias for `Reg`"] +pub type DATA3_CMB1 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb1; +#[doc = "DATA2_CMB1 register accessor: an alias for `Reg`"] +pub type DATA2_CMB1 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb1; +#[doc = "DATA1_CMB1 register accessor: an alias for `Reg`"] +pub type DATA1_CMB1 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb1; +#[doc = "DATA0_CMB1 register accessor: an alias for `Reg`"] +pub type DATA0_CMB1 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb1; +#[doc = "ID0_CMB1 register accessor: an alias for `Reg`"] +pub type ID0_CMB1 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb1; +#[doc = "ID1_CMB1 register accessor: an alias for `Reg`"] +pub type ID1_CMB1 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb1; +#[doc = "CNSTAT_CMB2 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB2 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb2; +#[doc = "TSTP_CMB2 register accessor: an alias for `Reg`"] +pub type TSTP_CMB2 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb2; +#[doc = "DATA3_CMB2 register accessor: an alias for `Reg`"] +pub type DATA3_CMB2 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb2; +#[doc = "DATA2_CMB2 register accessor: an alias for `Reg`"] +pub type DATA2_CMB2 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb2; +#[doc = "DATA1_CMB2 register accessor: an alias for `Reg`"] +pub type DATA1_CMB2 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb2; +#[doc = "DATA0_CMB2 register accessor: an alias for `Reg`"] +pub type DATA0_CMB2 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb2; +#[doc = "ID0_CMB2 register accessor: an alias for `Reg`"] +pub type ID0_CMB2 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb2; +#[doc = "ID1_CMB2 register accessor: an alias for `Reg`"] +pub type ID1_CMB2 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb2; +#[doc = "CNSTAT_CMB3 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB3 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb3; +#[doc = "TSTP_CMB3 register accessor: an alias for `Reg`"] +pub type TSTP_CMB3 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb3; +#[doc = "DATA3_CMB3 register accessor: an alias for `Reg`"] +pub type DATA3_CMB3 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb3; +#[doc = "DATA2_CMB3 register accessor: an alias for `Reg`"] +pub type DATA2_CMB3 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb3; +#[doc = "DATA1_CMB3 register accessor: an alias for `Reg`"] +pub type DATA1_CMB3 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb3; +#[doc = "DATA0_CMB3 register accessor: an alias for `Reg`"] +pub type DATA0_CMB3 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb3; +#[doc = "ID0_CMB3 register accessor: an alias for `Reg`"] +pub type ID0_CMB3 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb3; +#[doc = "ID1_CMB3 register accessor: an alias for `Reg`"] +pub type ID1_CMB3 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb3; +#[doc = "CNSTAT_CMB4 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB4 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb4; +#[doc = "TSTP_CMB4 register accessor: an alias for `Reg`"] +pub type TSTP_CMB4 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb4; +#[doc = "DATA3_CMB4 register accessor: an alias for `Reg`"] +pub type DATA3_CMB4 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb4; +#[doc = "DATA2_CMB4 register accessor: an alias for `Reg`"] +pub type DATA2_CMB4 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb4; +#[doc = "DATA1_CMB4 register accessor: an alias for `Reg`"] +pub type DATA1_CMB4 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb4; +#[doc = "DATA0_CMB4 register accessor: an alias for `Reg`"] +pub type DATA0_CMB4 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb4; +#[doc = "ID0_CMB4 register accessor: an alias for `Reg`"] +pub type ID0_CMB4 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb4; +#[doc = "ID1_CMB4 register accessor: an alias for `Reg`"] +pub type ID1_CMB4 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb4; +#[doc = "CNSTAT_CMB5 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB5 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb5; +#[doc = "TSTP_CMB5 register accessor: an alias for `Reg`"] +pub type TSTP_CMB5 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb5; +#[doc = "DATA3_CMB5 register accessor: an alias for `Reg`"] +pub type DATA3_CMB5 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb5; +#[doc = "DATA2_CMB5 register accessor: an alias for `Reg`"] +pub type DATA2_CMB5 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb5; +#[doc = "DATA1_CMB5 register accessor: an alias for `Reg`"] +pub type DATA1_CMB5 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb5; +#[doc = "DATA0_CMB5 register accessor: an alias for `Reg`"] +pub type DATA0_CMB5 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb5; +#[doc = "ID0_CMB5 register accessor: an alias for `Reg`"] +pub type ID0_CMB5 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb5; +#[doc = "ID1_CMB5 register accessor: an alias for `Reg`"] +pub type ID1_CMB5 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb5; +#[doc = "CNSTAT_CMB6 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB6 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb6; +#[doc = "TSTP_CMB6 register accessor: an alias for `Reg`"] +pub type TSTP_CMB6 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb6; +#[doc = "DATA3_CMB6 register accessor: an alias for `Reg`"] +pub type DATA3_CMB6 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb6; +#[doc = "DATA2_CMB6 register accessor: an alias for `Reg`"] +pub type DATA2_CMB6 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb6; +#[doc = "DATA1_CMB6 register accessor: an alias for `Reg`"] +pub type DATA1_CMB6 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb6; +#[doc = "DATA0_CMB6 register accessor: an alias for `Reg`"] +pub type DATA0_CMB6 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb6; +#[doc = "ID0_CMB6 register accessor: an alias for `Reg`"] +pub type ID0_CMB6 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb6; +#[doc = "ID1_CMB6 register accessor: an alias for `Reg`"] +pub type ID1_CMB6 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb6; +#[doc = "CNSTAT_CMB7 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB7 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb7; +#[doc = "TSTP_CMB7 register accessor: an alias for `Reg`"] +pub type TSTP_CMB7 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb7; +#[doc = "DATA3_CMB7 register accessor: an alias for `Reg`"] +pub type DATA3_CMB7 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb7; +#[doc = "DATA2_CMB7 register accessor: an alias for `Reg`"] +pub type DATA2_CMB7 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb7; +#[doc = "DATA1_CMB7 register accessor: an alias for `Reg`"] +pub type DATA1_CMB7 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb7; +#[doc = "DATA0_CMB7 register accessor: an alias for `Reg`"] +pub type DATA0_CMB7 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb7; +#[doc = "ID0_CMB7 register accessor: an alias for `Reg`"] +pub type ID0_CMB7 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb7; +#[doc = "ID1_CMB7 register accessor: an alias for `Reg`"] +pub type ID1_CMB7 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb7; +#[doc = "CNSTAT_CMB8 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB8 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb8; +#[doc = "TSTP_CMB8 register accessor: an alias for `Reg`"] +pub type TSTP_CMB8 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb8; +#[doc = "DATA3_CMB8 register accessor: an alias for `Reg`"] +pub type DATA3_CMB8 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb8; +#[doc = "DATA2_CMB8 register accessor: an alias for `Reg`"] +pub type DATA2_CMB8 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb8; +#[doc = "DATA1_CMB8 register accessor: an alias for `Reg`"] +pub type DATA1_CMB8 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb8; +#[doc = "DATA0_CMB8 register accessor: an alias for `Reg`"] +pub type DATA0_CMB8 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb8; +#[doc = "ID0_CMB8 register accessor: an alias for `Reg`"] +pub type ID0_CMB8 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb8; +#[doc = "ID1_CMB8 register accessor: an alias for `Reg`"] +pub type ID1_CMB8 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb8; +#[doc = "CNSTAT_CMB9 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB9 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb9; +#[doc = "TSTP_CMB9 register accessor: an alias for `Reg`"] +pub type TSTP_CMB9 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb9; +#[doc = "DATA3_CMB9 register accessor: an alias for `Reg`"] +pub type DATA3_CMB9 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb9; +#[doc = "DATA2_CMB9 register accessor: an alias for `Reg`"] +pub type DATA2_CMB9 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb9; +#[doc = "DATA1_CMB9 register accessor: an alias for `Reg`"] +pub type DATA1_CMB9 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb9; +#[doc = "DATA0_CMB9 register accessor: an alias for `Reg`"] +pub type DATA0_CMB9 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb9; +#[doc = "ID0_CMB9 register accessor: an alias for `Reg`"] +pub type ID0_CMB9 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb9; +#[doc = "ID1_CMB9 register accessor: an alias for `Reg`"] +pub type ID1_CMB9 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb9; +#[doc = "CNSTAT_CMB10 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB10 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb10; +#[doc = "TSTP_CMB10 register accessor: an alias for `Reg`"] +pub type TSTP_CMB10 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb10; +#[doc = "DATA3_CMB10 register accessor: an alias for `Reg`"] +pub type DATA3_CMB10 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb10; +#[doc = "DATA2_CMB10 register accessor: an alias for `Reg`"] +pub type DATA2_CMB10 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb10; +#[doc = "DATA1_CMB10 register accessor: an alias for `Reg`"] +pub type DATA1_CMB10 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb10; +#[doc = "DATA0_CMB10 register accessor: an alias for `Reg`"] +pub type DATA0_CMB10 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb10; +#[doc = "ID0_CMB10 register accessor: an alias for `Reg`"] +pub type ID0_CMB10 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb10; +#[doc = "ID1_CMB10 register accessor: an alias for `Reg`"] +pub type ID1_CMB10 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb10; +#[doc = "CNSTAT_CMB11 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB11 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb11; +#[doc = "TSTP_CMB11 register accessor: an alias for `Reg`"] +pub type TSTP_CMB11 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb11; +#[doc = "DATA3_CMB11 register accessor: an alias for `Reg`"] +pub type DATA3_CMB11 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb11; +#[doc = "DATA2_CMB11 register accessor: an alias for `Reg`"] +pub type DATA2_CMB11 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb11; +#[doc = "DATA1_CMB11 register accessor: an alias for `Reg`"] +pub type DATA1_CMB11 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb11; +#[doc = "DATA0_CMB11 register accessor: an alias for `Reg`"] +pub type DATA0_CMB11 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb11; +#[doc = "ID0_CMB11 register accessor: an alias for `Reg`"] +pub type ID0_CMB11 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb11; +#[doc = "ID1_CMB11 register accessor: an alias for `Reg`"] +pub type ID1_CMB11 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb11; +#[doc = "CNSTAT_CMB12 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB12 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb12; +#[doc = "TSTP_CMB12 register accessor: an alias for `Reg`"] +pub type TSTP_CMB12 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb12; +#[doc = "DATA3_CMB12 register accessor: an alias for `Reg`"] +pub type DATA3_CMB12 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb12; +#[doc = "DATA2_CMB12 register accessor: an alias for `Reg`"] +pub type DATA2_CMB12 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb12; +#[doc = "DATA1_CMB12 register accessor: an alias for `Reg`"] +pub type DATA1_CMB12 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb12; +#[doc = "DATA0_CMB12 register accessor: an alias for `Reg`"] +pub type DATA0_CMB12 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb12; +#[doc = "ID0_CMB12 register accessor: an alias for `Reg`"] +pub type ID0_CMB12 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb12; +#[doc = "ID1_CMB12 register accessor: an alias for `Reg`"] +pub type ID1_CMB12 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb12; +#[doc = "CNSTAT_CMB13 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB13 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb13; +#[doc = "TSTP_CMB13 register accessor: an alias for `Reg`"] +pub type TSTP_CMB13 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb13; +#[doc = "DATA3_CMB13 register accessor: an alias for `Reg`"] +pub type DATA3_CMB13 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb13; +#[doc = "DATA2_CMB13 register accessor: an alias for `Reg`"] +pub type DATA2_CMB13 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb13; +#[doc = "DATA1_CMB13 register accessor: an alias for `Reg`"] +pub type DATA1_CMB13 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb13; +#[doc = "DATA0_CMB13 register accessor: an alias for `Reg`"] +pub type DATA0_CMB13 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb13; +#[doc = "ID0_CMB13 register accessor: an alias for `Reg`"] +pub type ID0_CMB13 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb13; +#[doc = "ID1_CMB13 register accessor: an alias for `Reg`"] +pub type ID1_CMB13 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb13; +#[doc = "CNSTAT_CMB14 register accessor: an alias for `Reg`"] +pub type CNSTAT_CMB14 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb14; +#[doc = "TSTP_CMB14 register accessor: an alias for `Reg`"] +pub type TSTP_CMB14 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb14; +#[doc = "DATA3_CMB14 register accessor: an alias for `Reg`"] +pub type DATA3_CMB14 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb14; +#[doc = "DATA2_CMB14 register accessor: an alias for `Reg`"] +pub type DATA2_CMB14 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb14; +#[doc = "DATA1_CMB14 register accessor: an alias for `Reg`"] +pub type DATA1_CMB14 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb14; +#[doc = "DATA0_CMB14 register accessor: an alias for `Reg`"] +pub type DATA0_CMB14 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb14; +#[doc = "ID0_CMB14 register accessor: an alias for `Reg`"] +pub type ID0_CMB14 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb14; +#[doc = "ID1_CMB14 register accessor: an alias for `Reg`"] +pub type ID1_CMB14 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb14; +#[doc = "CNSTAT_HCMB register accessor: an alias for `Reg`"] +pub type CNSTAT_HCMB = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_hcmb; +#[doc = "TSTP_HCMB register accessor: an alias for `Reg`"] +pub type TSTP_HCMB = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_hcmb; +#[doc = "DATA3_HCMB register accessor: an alias for `Reg`"] +pub type DATA3_HCMB = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_hcmb; +#[doc = "DATA2_HCMB register accessor: an alias for `Reg`"] +pub type DATA2_HCMB = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_hcmb; +#[doc = "DATA1_HCMB register accessor: an alias for `Reg`"] +pub type DATA1_HCMB = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_hcmb; +#[doc = "DATA0_HCMB register accessor: an alias for `Reg`"] +pub type DATA0_HCMB = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_hcmb; +#[doc = "ID0_HCMB register accessor: an alias for `Reg`"] +pub type ID0_HCMB = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_hcmb; +#[doc = "ID1_HCMB register accessor: an alias for `Reg`"] +pub type ID1_HCMB = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_hcmb; +#[doc = "CGCR register accessor: an alias for `Reg`"] +pub type CGCR = crate::Reg; +#[doc = "CAN Global Configuration Register"] +pub mod cgcr; +#[doc = "CTIM register accessor: an alias for `Reg`"] +pub type CTIM = crate::Reg; +#[doc = "CAN Timing Register"] +pub mod ctim; +#[doc = "GMSKX register accessor: an alias for `Reg`"] +pub type GMSKX = crate::Reg; +#[doc = "CAN Global Mask Extension"] +pub mod gmskx; +#[doc = "GMSKB register accessor: an alias for `Reg`"] +pub type GMSKB = crate::Reg; +#[doc = "CAN Global Mask Base"] +pub mod gmskb; +#[doc = "BMSKX register accessor: an alias for `Reg`"] +pub type BMSKX = crate::Reg; +#[doc = "CAN Basic Mask Extension"] +pub mod bmskx; +#[doc = "BMSKB register accessor: an alias for `Reg`"] +pub type BMSKB = crate::Reg; +#[doc = "CAN Basic Mask Base"] +pub mod bmskb; +#[doc = "CIEN register accessor: an alias for `Reg`"] +pub type CIEN = crate::Reg; +#[doc = "CAN Interrupt Enable Register"] +pub mod cien; +#[doc = "CIPND register accessor: an alias for `Reg`"] +pub type CIPND = crate::Reg; +#[doc = "CAN Interrupt Pending Register"] +pub mod cipnd; +#[doc = "CICLR register accessor: an alias for `Reg`"] +pub type CICLR = crate::Reg; +#[doc = "CAN Interrupt Clear Register"] +pub mod ciclr; +#[doc = "CICEN register accessor: an alias for `Reg`"] +pub type CICEN = crate::Reg; +#[doc = "CAN Interrupt Code Enable Register"] +pub mod cicen; +#[doc = "CSTPND register accessor: an alias for `Reg`"] +pub type CSTPND = crate::Reg; +#[doc = "CAN Status Pending Register"] +pub mod cstpnd; +#[doc = "CANEC register accessor: an alias for `Reg`"] +pub type CANEC = crate::Reg; +#[doc = "CAN Error Counter Register"] +pub mod canec; +#[doc = "CEDIAG register accessor: an alias for `Reg`"] +pub type CEDIAG = crate::Reg; +#[doc = "CAN Error Diagnostic Register"] +pub mod cediag; +#[doc = "CTMR register accessor: an alias for `Reg`"] +pub type CTMR = crate::Reg; +#[doc = "CAN Timer Register"] +pub mod ctmr; diff --git a/src/can0/bmskb.rs b/src/can0/bmskb.rs new file mode 100644 index 0000000..031a25b --- /dev/null +++ b/src/can0/bmskb.rs @@ -0,0 +1,254 @@ +#[doc = "Register `BMSKB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BMSKB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BM1` reader - BM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] +pub struct BM1_R(crate::FieldReader); +impl BM1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BM1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BM1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BM1` writer - BM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] +pub struct BM1_W<'a> { + w: &'a mut W, +} +impl<'a> BM1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 5)) | ((value as u32 & 0x07ff) << 5); + self.w + } +} +#[doc = "Field `RTR` reader - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub struct RTR_R(crate::FieldReader); +impl RTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTR` writer - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub struct RTR_W<'a> { + w: &'a mut W, +} +impl<'a> RTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `IDE` reader - Identifier Extension Bit"] +pub struct IDE_R(crate::FieldReader); +impl IDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDE` writer - Identifier Extension Bit"] +pub struct IDE_W<'a> { + w: &'a mut W, +} +impl<'a> IDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `BM0` reader - BM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] +pub struct BM0_R(crate::FieldReader); +impl BM0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BM0` writer - BM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] +pub struct BM0_W<'a> { + w: &'a mut W, +} +impl<'a> BM0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 5:15 - BM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] + #[inline(always)] + pub fn bm1(&self) -> BM1_R { + BM1_R::new(((self.bits >> 5) & 0x07ff) as u16) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&self) -> RTR_R { + RTR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&self) -> IDE_R { + IDE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 0:2 - BM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] + #[inline(always)] + pub fn bm0(&self) -> BM0_R { + BM0_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 5:15 - BM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] + #[inline(always)] + pub fn bm1(&mut self) -> BM1_W { + BM1_W { w: self } + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&mut self) -> RTR_W { + RTR_W { w: self } + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&mut self) -> IDE_W { + IDE_W { w: self } + } + #[doc = "Bits 0:2 - BM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] + #[inline(always)] + pub fn bm0(&mut self) -> BM0_W { + BM0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Basic Mask Base\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bmskb](index.html) module"] +pub struct BMSKB_SPEC; +impl crate::RegisterSpec for BMSKB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bmskb::R](R) reader structure"] +impl crate::Readable for BMSKB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bmskb::W](W) writer structure"] +impl crate::Writable for BMSKB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BMSKB to value 0"] +impl crate::Resettable for BMSKB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/bmskx.rs b/src/can0/bmskx.rs new file mode 100644 index 0000000..ab598c3 --- /dev/null +++ b/src/can0/bmskx.rs @@ -0,0 +1,158 @@ +#[doc = "Register `BMSKX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BMSKX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BM` reader - BM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] +pub struct BM_R(crate::FieldReader); +impl BM_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + BM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BM` writer - BM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] +pub struct BM_W<'a> { + w: &'a mut W, +} +impl<'a> BM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7fff << 1)) | ((value as u32 & 0x7fff) << 1); + self.w + } +} +#[doc = "Field `XRTR` reader - Extended Remote transmission Request Bit"] +pub struct XRTR_R(crate::FieldReader); +impl XRTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XRTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XRTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XRTR` writer - Extended Remote transmission Request Bit"] +pub struct XRTR_W<'a> { + w: &'a mut W, +} +impl<'a> XRTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bits 1:15 - BM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] + #[inline(always)] + pub fn bm(&self) -> BM_R { + BM_R::new(((self.bits >> 1) & 0x7fff) as u16) + } + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&self) -> XRTR_R { + XRTR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 1:15 - BM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] + #[inline(always)] + pub fn bm(&mut self) -> BM_W { + BM_W { w: self } + } + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&mut self) -> XRTR_W { + XRTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Basic Mask Extension\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bmskx](index.html) module"] +pub struct BMSKX_SPEC; +impl crate::RegisterSpec for BMSKX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bmskx::R](R) reader structure"] +impl crate::Readable for BMSKX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bmskx::W](W) writer structure"] +impl crate::Writable for BMSKX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BMSKX to value 0"] +impl crate::Resettable for BMSKX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/canec.rs b/src/can0/canec.rs new file mode 100644 index 0000000..5101844 --- /dev/null +++ b/src/can0/canec.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CANEC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CANEC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REC` reader - Receive Error Counter"] +pub struct REC_R(crate::FieldReader); +impl REC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REC` writer - Receive Error Counter"] +pub struct REC_W<'a> { + w: &'a mut W, +} +impl<'a> REC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `TEC` reader - Transmit Error Counter"] +pub struct TEC_R(crate::FieldReader); +impl TEC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TEC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEC` writer - Transmit Error Counter"] +pub struct TEC_W<'a> { + w: &'a mut W, +} +impl<'a> TEC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Receive Error Counter"] + #[inline(always)] + pub fn rec(&self) -> REC_R { + REC_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn tec(&self) -> TEC_R { + TEC_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Receive Error Counter"] + #[inline(always)] + pub fn rec(&mut self) -> REC_W { + REC_W { w: self } + } + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn tec(&mut self) -> TEC_W { + TEC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Error Counter Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [canec](index.html) module"] +pub struct CANEC_SPEC; +impl crate::RegisterSpec for CANEC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [canec::R](R) reader structure"] +impl crate::Readable for CANEC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [canec::W](W) writer structure"] +impl crate::Writable for CANEC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CANEC to value 0"] +impl crate::Resettable for CANEC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cediag.rs b/src/can0/cediag.rs new file mode 100644 index 0000000..58b275a --- /dev/null +++ b/src/can0/cediag.rs @@ -0,0 +1,375 @@ +#[doc = "Register `CEDIAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CEDIAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRIVE` reader - Drive"] +pub struct DRIVE_R(crate::FieldReader); +impl DRIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRIVE` writer - Drive"] +pub struct DRIVE_W<'a> { + w: &'a mut W, +} +impl<'a> DRIVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `MON` reader - Monitor"] +pub struct MON_R(crate::FieldReader); +impl MON_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MON` writer - Monitor"] +pub struct MON_W<'a> { + w: &'a mut W, +} +impl<'a> MON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `CRC` reader - CRC"] +pub struct CRC_R(crate::FieldReader); +impl CRC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRC` writer - CRC"] +pub struct CRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `STUFF` reader - Stuff Error"] +pub struct STUFF_R(crate::FieldReader); +impl STUFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STUFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STUFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STUFF` writer - Stuff Error"] +pub struct STUFF_W<'a> { + w: &'a mut W, +} +impl<'a> STUFF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TXE` reader - Transmit Error"] +pub struct TXE_R(crate::FieldReader); +impl TXE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXE` writer - Transmit Error"] +pub struct TXE_W<'a> { + w: &'a mut W, +} +impl<'a> TXE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `EBID` reader - Error Bit Identifier"] +pub struct EBID_R(crate::FieldReader); +impl EBID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EBID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EBID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EBID` writer - Error Bit Identifier"] +pub struct EBID_W<'a> { + w: &'a mut W, +} +impl<'a> EBID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 4)) | ((value as u32 & 0x3f) << 4); + self.w + } +} +#[doc = "Field `EFID` reader - Error Field Identifier"] +pub struct EFID_R(crate::FieldReader); +impl EFID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EFID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EFID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EFID` writer - Error Field Identifier"] +pub struct EFID_W<'a> { + w: &'a mut W, +} +impl<'a> EFID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bit 14 - Drive"] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - Monitor"] + #[inline(always)] + pub fn mon(&self) -> MON_R { + MON_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 12 - CRC"] + #[inline(always)] + pub fn crc(&self) -> CRC_R { + CRC_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 11 - Stuff Error"] + #[inline(always)] + pub fn stuff(&self) -> STUFF_R { + STUFF_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - Transmit Error"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bits 4:9 - Error Bit Identifier"] + #[inline(always)] + pub fn ebid(&self) -> EBID_R { + EBID_R::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 0:3 - Error Field Identifier"] + #[inline(always)] + pub fn efid(&self) -> EFID_R { + EFID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 14 - Drive"] + #[inline(always)] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W { w: self } + } + #[doc = "Bit 13 - Monitor"] + #[inline(always)] + pub fn mon(&mut self) -> MON_W { + MON_W { w: self } + } + #[doc = "Bit 12 - CRC"] + #[inline(always)] + pub fn crc(&mut self) -> CRC_W { + CRC_W { w: self } + } + #[doc = "Bit 11 - Stuff Error"] + #[inline(always)] + pub fn stuff(&mut self) -> STUFF_W { + STUFF_W { w: self } + } + #[doc = "Bit 10 - Transmit Error"] + #[inline(always)] + pub fn txe(&mut self) -> TXE_W { + TXE_W { w: self } + } + #[doc = "Bits 4:9 - Error Bit Identifier"] + #[inline(always)] + pub fn ebid(&mut self) -> EBID_W { + EBID_W { w: self } + } + #[doc = "Bits 0:3 - Error Field Identifier"] + #[inline(always)] + pub fn efid(&mut self) -> EFID_W { + EFID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Error Diagnostic Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cediag](index.html) module"] +pub struct CEDIAG_SPEC; +impl crate::RegisterSpec for CEDIAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cediag::R](R) reader structure"] +impl crate::Readable for CEDIAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cediag::W](W) writer structure"] +impl crate::Writable for CEDIAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CEDIAG to value 0"] +impl crate::Resettable for CEDIAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cgcr.rs b/src/can0/cgcr.rs new file mode 100644 index 0000000..8eb20a5 --- /dev/null +++ b/src/can0/cgcr.rs @@ -0,0 +1,630 @@ +#[doc = "Register `CGCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CGCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EIT` reader - Error Interrupt Type"] +pub struct EIT_R(crate::FieldReader); +impl EIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIT` writer - Error Interrupt Type"] +pub struct EIT_W<'a> { + w: &'a mut W, +} +impl<'a> EIT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIAGEN` reader - Diagnostic Enable"] +pub struct DIAGEN_R(crate::FieldReader); +impl DIAGEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIAGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIAGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIAGEN` writer - Diagnostic Enable"] +pub struct DIAGEN_W<'a> { + w: &'a mut W, +} +impl<'a> DIAGEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `INTERNAL` reader - Internal"] +pub struct INTERNAL_R(crate::FieldReader); +impl INTERNAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INTERNAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INTERNAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTERNAL` writer - Internal"] +pub struct INTERNAL_W<'a> { + w: &'a mut W, +} +impl<'a> INTERNAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LOOPBACK` reader - Loopback"] +pub struct LOOPBACK_R(crate::FieldReader); +impl LOOPBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOOPBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOOPBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOOPBACK` writer - Loopback"] +pub struct LOOPBACK_W<'a> { + w: &'a mut W, +} +impl<'a> LOOPBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IGNACK` reader - Ignore Acknowledge"] +pub struct IGNACK_R(crate::FieldReader); +impl IGNACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IGNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IGNACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IGNACK` writer - Ignore Acknowledge"] +pub struct IGNACK_W<'a> { + w: &'a mut W, +} +impl<'a> IGNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LO` reader - Listen Only"] +pub struct LO_R(crate::FieldReader); +impl LO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LO` writer - Listen Only"] +pub struct LO_W<'a> { + w: &'a mut W, +} +impl<'a> LO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DDIR` reader - Data Direction"] +pub struct DDIR_R(crate::FieldReader); +impl DDIR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DDIR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DDIR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DDIR` writer - Data Direction"] +pub struct DDIR_W<'a> { + w: &'a mut W, +} +impl<'a> DDIR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTPEN` reader - Time Sync Enable"] +pub struct TSTPEN_R(crate::FieldReader); +impl TSTPEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTPEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTPEN` writer - Time Sync Enable"] +pub struct TSTPEN_W<'a> { + w: &'a mut W, +} +impl<'a> TSTPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `BUFFLOCK` reader - Buffer Lock"] +pub struct BUFFLOCK_R(crate::FieldReader); +impl BUFFLOCK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUFFLOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFFLOCK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFFLOCK` writer - Buffer Lock"] +pub struct BUFFLOCK_W<'a> { + w: &'a mut W, +} +impl<'a> BUFFLOCK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CTX` reader - RW,Control Transmit"] +pub struct CTX_R(crate::FieldReader); +impl CTX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CTX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTX` writer - RW,Control Transmit"] +pub struct CTX_W<'a> { + w: &'a mut W, +} +impl<'a> CTX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CRX` reader - RW,Control Receive"] +pub struct CRX_R(crate::FieldReader); +impl CRX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRX` writer - RW,Control Receive"] +pub struct CRX_W<'a> { + w: &'a mut W, +} +impl<'a> CRX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CANEN` reader - CAN Enable"] +pub struct CANEN_R(crate::FieldReader); +impl CANEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CANEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CANEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CANEN` writer - CAN Enable"] +pub struct CANEN_W<'a> { + w: &'a mut W, +} +impl<'a> CANEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 11 - Error Interrupt Type"] + #[inline(always)] + pub fn eit(&self) -> EIT_R { + EIT_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - Diagnostic Enable"] + #[inline(always)] + pub fn diagen(&self) -> DIAGEN_R { + DIAGEN_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - Internal"] + #[inline(always)] + pub fn internal(&self) -> INTERNAL_R { + INTERNAL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - Loopback"] + #[inline(always)] + pub fn loopback(&self) -> LOOPBACK_R { + LOOPBACK_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 7 - Ignore Acknowledge"] + #[inline(always)] + pub fn ignack(&self) -> IGNACK_R { + IGNACK_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - Listen Only"] + #[inline(always)] + pub fn lo(&self) -> LO_R { + LO_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Data Direction"] + #[inline(always)] + pub fn ddir(&self) -> DDIR_R { + DDIR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Time Sync Enable"] + #[inline(always)] + pub fn tstpen(&self) -> TSTPEN_R { + TSTPEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Buffer Lock"] + #[inline(always)] + pub fn bufflock(&self) -> BUFFLOCK_R { + BUFFLOCK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - RW,Control Transmit"] + #[inline(always)] + pub fn ctx(&self) -> CTX_R { + CTX_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - RW,Control Receive"] + #[inline(always)] + pub fn crx(&self) -> CRX_R { + CRX_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - CAN Enable"] + #[inline(always)] + pub fn canen(&self) -> CANEN_R { + CANEN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 11 - Error Interrupt Type"] + #[inline(always)] + pub fn eit(&mut self) -> EIT_W { + EIT_W { w: self } + } + #[doc = "Bit 10 - Diagnostic Enable"] + #[inline(always)] + pub fn diagen(&mut self) -> DIAGEN_W { + DIAGEN_W { w: self } + } + #[doc = "Bit 9 - Internal"] + #[inline(always)] + pub fn internal(&mut self) -> INTERNAL_W { + INTERNAL_W { w: self } + } + #[doc = "Bit 8 - Loopback"] + #[inline(always)] + pub fn loopback(&mut self) -> LOOPBACK_W { + LOOPBACK_W { w: self } + } + #[doc = "Bit 7 - Ignore Acknowledge"] + #[inline(always)] + pub fn ignack(&mut self) -> IGNACK_W { + IGNACK_W { w: self } + } + #[doc = "Bit 6 - Listen Only"] + #[inline(always)] + pub fn lo(&mut self) -> LO_W { + LO_W { w: self } + } + #[doc = "Bit 5 - Data Direction"] + #[inline(always)] + pub fn ddir(&mut self) -> DDIR_W { + DDIR_W { w: self } + } + #[doc = "Bit 4 - Time Sync Enable"] + #[inline(always)] + pub fn tstpen(&mut self) -> TSTPEN_W { + TSTPEN_W { w: self } + } + #[doc = "Bit 3 - Buffer Lock"] + #[inline(always)] + pub fn bufflock(&mut self) -> BUFFLOCK_W { + BUFFLOCK_W { w: self } + } + #[doc = "Bit 2 - RW,Control Transmit"] + #[inline(always)] + pub fn ctx(&mut self) -> CTX_W { + CTX_W { w: self } + } + #[doc = "Bit 1 - RW,Control Receive"] + #[inline(always)] + pub fn crx(&mut self) -> CRX_W { + CRX_W { w: self } + } + #[doc = "Bit 0 - CAN Enable"] + #[inline(always)] + pub fn canen(&mut self) -> CANEN_W { + CANEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Global Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cgcr](index.html) module"] +pub struct CGCR_SPEC; +impl crate::RegisterSpec for CGCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cgcr::R](R) reader structure"] +impl crate::Readable for CGCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cgcr::W](W) writer structure"] +impl crate::Writable for CGCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CGCR to value 0"] +impl crate::Resettable for CGCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cicen.rs b/src/can0/cicen.rs new file mode 100644 index 0000000..58724ea --- /dev/null +++ b/src/can0/cicen.rs @@ -0,0 +1,150 @@ +#[doc = "Register `CICEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CICEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EICEN` reader - Error Interrupt Code Enable"] +pub struct EICEN_R(crate::FieldReader); +impl EICEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EICEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EICEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EICEN` writer - Error Interrupt Code Enable"] +pub struct EICEN_W<'a> { + w: &'a mut W, +} +impl<'a> EICEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ICEN` reader - Buffer Interrupt Code Enable\\[14:0\\]"] +pub struct ICEN_R(crate::FieldReader); +impl ICEN_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ICEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ICEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ICEN` writer - Buffer Interrupt Code Enable\\[14:0\\]"] +pub struct ICEN_W<'a> { + w: &'a mut W, +} +impl<'a> ICEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7fff) | (value as u32 & 0x7fff); + self.w + } +} +impl R { + #[doc = "Bit 15 - Error Interrupt Code Enable"] + #[inline(always)] + pub fn eicen(&self) -> EICEN_R { + EICEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"] + #[inline(always)] + pub fn icen(&self) -> ICEN_R { + ICEN_R::new((self.bits & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bit 15 - Error Interrupt Code Enable"] + #[inline(always)] + pub fn eicen(&mut self) -> EICEN_W { + EICEN_W { w: self } + } + #[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"] + #[inline(always)] + pub fn icen(&mut self) -> ICEN_W { + ICEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Interrupt Code Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cicen](index.html) module"] +pub struct CICEN_SPEC; +impl crate::RegisterSpec for CICEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cicen::R](R) reader structure"] +impl crate::Readable for CICEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cicen::W](W) writer structure"] +impl crate::Writable for CICEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CICEN to value 0"] +impl crate::Resettable for CICEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/ciclr.rs b/src/can0/ciclr.rs new file mode 100644 index 0000000..f3ec466 --- /dev/null +++ b/src/can0/ciclr.rs @@ -0,0 +1,150 @@ +#[doc = "Register `CICLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CICLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EICLR` reader - Error Interrupt Clear"] +pub struct EICLR_R(crate::FieldReader); +impl EICLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EICLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EICLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EICLR` writer - Error Interrupt Clear"] +pub struct EICLR_W<'a> { + w: &'a mut W, +} +impl<'a> EICLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ICLR` reader - Buffer Interrupt Clear\\[14:0\\]"] +pub struct ICLR_R(crate::FieldReader); +impl ICLR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ICLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ICLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ICLR` writer - Buffer Interrupt Clear\\[14:0\\]"] +pub struct ICLR_W<'a> { + w: &'a mut W, +} +impl<'a> ICLR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7fff) | (value as u32 & 0x7fff); + self.w + } +} +impl R { + #[doc = "Bit 15 - Error Interrupt Clear"] + #[inline(always)] + pub fn eiclr(&self) -> EICLR_R { + EICLR_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 0:14 - Buffer Interrupt Clear\\[14:0\\]"] + #[inline(always)] + pub fn iclr(&self) -> ICLR_R { + ICLR_R::new((self.bits & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bit 15 - Error Interrupt Clear"] + #[inline(always)] + pub fn eiclr(&mut self) -> EICLR_W { + EICLR_W { w: self } + } + #[doc = "Bits 0:14 - Buffer Interrupt Clear\\[14:0\\]"] + #[inline(always)] + pub fn iclr(&mut self) -> ICLR_W { + ICLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ciclr](index.html) module"] +pub struct CICLR_SPEC; +impl crate::RegisterSpec for CICLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ciclr::R](R) reader structure"] +impl crate::Readable for CICLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ciclr::W](W) writer structure"] +impl crate::Writable for CICLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CICLR to value 0"] +impl crate::Resettable for CICLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cien.rs b/src/can0/cien.rs new file mode 100644 index 0000000..f2eef9e --- /dev/null +++ b/src/can0/cien.rs @@ -0,0 +1,150 @@ +#[doc = "Register `CIEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CIEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EIEN` reader - Error Interrupt Enable"] +pub struct EIEN_R(crate::FieldReader); +impl EIEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIEN` writer - Error Interrupt Enable"] +pub struct EIEN_W<'a> { + w: &'a mut W, +} +impl<'a> EIEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `IEN` reader - Buffer Interrupt Enable\\[14:0\\]"] +pub struct IEN_R(crate::FieldReader); +impl IEN_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + IEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IEN` writer - Buffer Interrupt Enable\\[14:0\\]"] +pub struct IEN_W<'a> { + w: &'a mut W, +} +impl<'a> IEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7fff) | (value as u32 & 0x7fff); + self.w + } +} +impl R { + #[doc = "Bit 15 - Error Interrupt Enable"] + #[inline(always)] + pub fn eien(&self) -> EIEN_R { + EIEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 0:14 - Buffer Interrupt Enable\\[14:0\\]"] + #[inline(always)] + pub fn ien(&self) -> IEN_R { + IEN_R::new((self.bits & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bit 15 - Error Interrupt Enable"] + #[inline(always)] + pub fn eien(&mut self) -> EIEN_W { + EIEN_W { w: self } + } + #[doc = "Bits 0:14 - Buffer Interrupt Enable\\[14:0\\]"] + #[inline(always)] + pub fn ien(&mut self) -> IEN_W { + IEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cien](index.html) module"] +pub struct CIEN_SPEC; +impl crate::RegisterSpec for CIEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cien::R](R) reader structure"] +impl crate::Readable for CIEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cien::W](W) writer structure"] +impl crate::Writable for CIEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CIEN to value 0"] +impl crate::Resettable for CIEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cipnd.rs b/src/can0/cipnd.rs new file mode 100644 index 0000000..99f7715 --- /dev/null +++ b/src/can0/cipnd.rs @@ -0,0 +1,150 @@ +#[doc = "Register `CIPND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CIPND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EIPND` reader - Error Interrupt Pending"] +pub struct EIPND_R(crate::FieldReader); +impl EIPND_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EIPND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIPND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIPND` writer - Error Interrupt Pending"] +pub struct EIPND_W<'a> { + w: &'a mut W, +} +impl<'a> EIPND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `IPND` reader - Buffer Interrupt Pending\\[14:0\\]"] +pub struct IPND_R(crate::FieldReader); +impl IPND_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + IPND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IPND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IPND` writer - Buffer Interrupt Pending\\[14:0\\]"] +pub struct IPND_W<'a> { + w: &'a mut W, +} +impl<'a> IPND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7fff) | (value as u32 & 0x7fff); + self.w + } +} +impl R { + #[doc = "Bit 15 - Error Interrupt Pending"] + #[inline(always)] + pub fn eipnd(&self) -> EIPND_R { + EIPND_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 0:14 - Buffer Interrupt Pending\\[14:0\\]"] + #[inline(always)] + pub fn ipnd(&self) -> IPND_R { + IPND_R::new((self.bits & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bit 15 - Error Interrupt Pending"] + #[inline(always)] + pub fn eipnd(&mut self) -> EIPND_W { + EIPND_W { w: self } + } + #[doc = "Bits 0:14 - Buffer Interrupt Pending\\[14:0\\]"] + #[inline(always)] + pub fn ipnd(&mut self) -> IPND_W { + IPND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Interrupt Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cipnd](index.html) module"] +pub struct CIPND_SPEC; +impl crate::RegisterSpec for CIPND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cipnd::R](R) reader structure"] +impl crate::Readable for CIPND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cipnd::W](W) writer structure"] +impl crate::Writable for CIPND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CIPND to value 0"] +impl crate::Resettable for CIPND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb0.rs b/src/can0/cnstat_cmb0.rs new file mode 100644 index 0000000..d69b01f --- /dev/null +++ b/src/can0/cnstat_cmb0.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb0](index.html) module"] +pub struct CNSTAT_CMB0_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb0::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb0::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB0 to value 0"] +impl crate::Resettable for CNSTAT_CMB0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb1.rs b/src/can0/cnstat_cmb1.rs new file mode 100644 index 0000000..d4d8377 --- /dev/null +++ b/src/can0/cnstat_cmb1.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb1](index.html) module"] +pub struct CNSTAT_CMB1_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb1::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb1::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB1 to value 0"] +impl crate::Resettable for CNSTAT_CMB1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb10.rs b/src/can0/cnstat_cmb10.rs new file mode 100644 index 0000000..815d4a3 --- /dev/null +++ b/src/can0/cnstat_cmb10.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb10](index.html) module"] +pub struct CNSTAT_CMB10_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb10::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb10::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB10_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB10 to value 0"] +impl crate::Resettable for CNSTAT_CMB10_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb11.rs b/src/can0/cnstat_cmb11.rs new file mode 100644 index 0000000..1eefb36 --- /dev/null +++ b/src/can0/cnstat_cmb11.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb11](index.html) module"] +pub struct CNSTAT_CMB11_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb11::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb11::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB11_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB11 to value 0"] +impl crate::Resettable for CNSTAT_CMB11_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb12.rs b/src/can0/cnstat_cmb12.rs new file mode 100644 index 0000000..f9e9132 --- /dev/null +++ b/src/can0/cnstat_cmb12.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb12](index.html) module"] +pub struct CNSTAT_CMB12_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb12::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb12::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB12_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB12 to value 0"] +impl crate::Resettable for CNSTAT_CMB12_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb13.rs b/src/can0/cnstat_cmb13.rs new file mode 100644 index 0000000..c0562e0 --- /dev/null +++ b/src/can0/cnstat_cmb13.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb13](index.html) module"] +pub struct CNSTAT_CMB13_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb13::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb13::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB13_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB13 to value 0"] +impl crate::Resettable for CNSTAT_CMB13_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb14.rs b/src/can0/cnstat_cmb14.rs new file mode 100644 index 0000000..bbf5adb --- /dev/null +++ b/src/can0/cnstat_cmb14.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb14](index.html) module"] +pub struct CNSTAT_CMB14_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb14::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb14::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB14_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB14 to value 0"] +impl crate::Resettable for CNSTAT_CMB14_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb2.rs b/src/can0/cnstat_cmb2.rs new file mode 100644 index 0000000..68e4d04 --- /dev/null +++ b/src/can0/cnstat_cmb2.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb2](index.html) module"] +pub struct CNSTAT_CMB2_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb2::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb2::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB2 to value 0"] +impl crate::Resettable for CNSTAT_CMB2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb3.rs b/src/can0/cnstat_cmb3.rs new file mode 100644 index 0000000..f0b91d5 --- /dev/null +++ b/src/can0/cnstat_cmb3.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb3](index.html) module"] +pub struct CNSTAT_CMB3_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb3::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb3::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB3 to value 0"] +impl crate::Resettable for CNSTAT_CMB3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb4.rs b/src/can0/cnstat_cmb4.rs new file mode 100644 index 0000000..edced8d --- /dev/null +++ b/src/can0/cnstat_cmb4.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb4](index.html) module"] +pub struct CNSTAT_CMB4_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb4::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb4::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB4 to value 0"] +impl crate::Resettable for CNSTAT_CMB4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb5.rs b/src/can0/cnstat_cmb5.rs new file mode 100644 index 0000000..2f68875 --- /dev/null +++ b/src/can0/cnstat_cmb5.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb5](index.html) module"] +pub struct CNSTAT_CMB5_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb5::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb5::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB5_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB5 to value 0"] +impl crate::Resettable for CNSTAT_CMB5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb6.rs b/src/can0/cnstat_cmb6.rs new file mode 100644 index 0000000..dfa33da --- /dev/null +++ b/src/can0/cnstat_cmb6.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb6](index.html) module"] +pub struct CNSTAT_CMB6_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb6::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb6::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB6_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB6 to value 0"] +impl crate::Resettable for CNSTAT_CMB6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb7.rs b/src/can0/cnstat_cmb7.rs new file mode 100644 index 0000000..5ce5387 --- /dev/null +++ b/src/can0/cnstat_cmb7.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb7](index.html) module"] +pub struct CNSTAT_CMB7_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb7::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb7::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB7_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB7 to value 0"] +impl crate::Resettable for CNSTAT_CMB7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb8.rs b/src/can0/cnstat_cmb8.rs new file mode 100644 index 0000000..130f332 --- /dev/null +++ b/src/can0/cnstat_cmb8.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb8](index.html) module"] +pub struct CNSTAT_CMB8_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb8::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb8::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB8_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB8 to value 0"] +impl crate::Resettable for CNSTAT_CMB8_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_cmb9.rs b/src/can0/cnstat_cmb9.rs new file mode 100644 index 0000000..ed021fa --- /dev/null +++ b/src/can0/cnstat_cmb9.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_CMB9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_CMB9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_cmb9](index.html) module"] +pub struct CNSTAT_CMB9_SPEC; +impl crate::RegisterSpec for CNSTAT_CMB9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_cmb9::R](R) reader structure"] +impl crate::Readable for CNSTAT_CMB9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_cmb9::W](W) writer structure"] +impl crate::Writable for CNSTAT_CMB9_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_CMB9 to value 0"] +impl crate::Resettable for CNSTAT_CMB9_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cnstat_hcmb.rs b/src/can0/cnstat_hcmb.rs new file mode 100644 index 0000000..a7bdd05 --- /dev/null +++ b/src/can0/cnstat_hcmb.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CNSTAT_HCMB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNSTAT_HCMB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DLC` reader - Data Length Code"] +pub struct DLC_R(crate::FieldReader); +impl DLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLC` writer - Data Length Code"] +pub struct DLC_W<'a> { + w: &'a mut W, +} +impl<'a> DLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); + self.w + } +} +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub struct PRI_R(crate::FieldReader); +impl PRI_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub struct PRI_W<'a> { + w: &'a mut W, +} +impl<'a> PRI_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `ST` reader - Buffer Status"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Buffer Status"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DLC_R { + DLC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PRI_R { + PRI_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DLC_W { + DLC_W { w: self } + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PRI_W { + PRI_W { w: self } + } + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Buffer Status / Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnstat_hcmb](index.html) module"] +pub struct CNSTAT_HCMB_SPEC; +impl crate::RegisterSpec for CNSTAT_HCMB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnstat_hcmb::R](R) reader structure"] +impl crate::Readable for CNSTAT_HCMB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnstat_hcmb::W](W) writer structure"] +impl crate::Writable for CNSTAT_HCMB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNSTAT_HCMB to value 0"] +impl crate::Resettable for CNSTAT_HCMB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/cstpnd.rs b/src/can0/cstpnd.rs new file mode 100644 index 0000000..1d6581e --- /dev/null +++ b/src/can0/cstpnd.rs @@ -0,0 +1,187 @@ +#[doc = "Register `CSTPND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSTPND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NS` reader - CAN Node Status"] +pub struct NS_R(crate::FieldReader); +impl NS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NS` writer - CAN Node Status"] +pub struct NS_W<'a> { + w: &'a mut W, +} +impl<'a> NS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u32 & 0x07) << 5); + self.w + } +} +#[doc = "Field `IRQ` reader - Interrupt Request portion of Interrupt Code"] +pub struct IRQ_R(crate::FieldReader); +impl IRQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ` writer - Interrupt Request portion of Interrupt Code"] +pub struct IRQ_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `IST` reader - Interrupt Source portion of Interrupt Code"] +pub struct IST_R(crate::FieldReader); +impl IST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IST` writer - Interrupt Source portion of Interrupt Code"] +pub struct IST_W<'a> { + w: &'a mut W, +} +impl<'a> IST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 5:7 - CAN Node Status"] + #[inline(always)] + pub fn ns(&self) -> NS_R { + NS_R::new(((self.bits >> 5) & 0x07) as u8) + } + #[doc = "Bit 4 - Interrupt Request portion of Interrupt Code"] + #[inline(always)] + pub fn irq(&self) -> IRQ_R { + IRQ_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 0:3 - Interrupt Source portion of Interrupt Code"] + #[inline(always)] + pub fn ist(&self) -> IST_R { + IST_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 5:7 - CAN Node Status"] + #[inline(always)] + pub fn ns(&mut self) -> NS_W { + NS_W { w: self } + } + #[doc = "Bit 4 - Interrupt Request portion of Interrupt Code"] + #[inline(always)] + pub fn irq(&mut self) -> IRQ_W { + IRQ_W { w: self } + } + #[doc = "Bits 0:3 - Interrupt Source portion of Interrupt Code"] + #[inline(always)] + pub fn ist(&mut self) -> IST_W { + IST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Status Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cstpnd](index.html) module"] +pub struct CSTPND_SPEC; +impl crate::RegisterSpec for CSTPND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cstpnd::R](R) reader structure"] +impl crate::Readable for CSTPND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cstpnd::W](W) writer structure"] +impl crate::Writable for CSTPND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSTPND to value 0"] +impl crate::Resettable for CSTPND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/ctim.rs b/src/can0/ctim.rs new file mode 100644 index 0000000..7e77def --- /dev/null +++ b/src/can0/ctim.rs @@ -0,0 +1,214 @@ +#[doc = "Register `CTIM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTIM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PSC` reader - Prescaler Configuration"] +pub struct PSC_R(crate::FieldReader); +impl PSC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PSC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PSC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PSC` writer - Prescaler Configuration"] +pub struct PSC_W<'a> { + w: &'a mut W, +} +impl<'a> PSC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 9)) | ((value as u32 & 0x7f) << 9); + self.w + } +} +#[doc = "Field `SJW` reader - Synchronization Jump Width"] +pub struct SJW_R(crate::FieldReader); +impl SJW_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SJW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SJW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SJW` writer - Synchronization Jump Width"] +pub struct SJW_W<'a> { + w: &'a mut W, +} +impl<'a> SJW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 7)) | ((value as u32 & 0x03) << 7); + self.w + } +} +#[doc = "Field `TSEG1` reader - Time Segment 1"] +pub struct TSEG1_R(crate::FieldReader); +impl TSEG1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TSEG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEG1` writer - Time Segment 1"] +pub struct TSEG1_W<'a> { + w: &'a mut W, +} +impl<'a> TSEG1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 3)) | ((value as u32 & 0x0f) << 3); + self.w + } +} +#[doc = "Field `TSEG2` reader - Time Segment 2"] +pub struct TSEG2_R(crate::FieldReader); +impl TSEG2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TSEG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEG2` writer - Time Segment 2"] +pub struct TSEG2_W<'a> { + w: &'a mut W, +} +impl<'a> TSEG2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 9:15 - Prescaler Configuration"] + #[inline(always)] + pub fn psc(&self) -> PSC_R { + PSC_R::new(((self.bits >> 9) & 0x7f) as u8) + } + #[doc = "Bits 7:8 - Synchronization Jump Width"] + #[inline(always)] + pub fn sjw(&self) -> SJW_R { + SJW_R::new(((self.bits >> 7) & 0x03) as u8) + } + #[doc = "Bits 3:6 - Time Segment 1"] + #[inline(always)] + pub fn tseg1(&self) -> TSEG1_R { + TSEG1_R::new(((self.bits >> 3) & 0x0f) as u8) + } + #[doc = "Bits 0:2 - Time Segment 2"] + #[inline(always)] + pub fn tseg2(&self) -> TSEG2_R { + TSEG2_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 9:15 - Prescaler Configuration"] + #[inline(always)] + pub fn psc(&mut self) -> PSC_W { + PSC_W { w: self } + } + #[doc = "Bits 7:8 - Synchronization Jump Width"] + #[inline(always)] + pub fn sjw(&mut self) -> SJW_W { + SJW_W { w: self } + } + #[doc = "Bits 3:6 - Time Segment 1"] + #[inline(always)] + pub fn tseg1(&mut self) -> TSEG1_W { + TSEG1_W { w: self } + } + #[doc = "Bits 0:2 - Time Segment 2"] + #[inline(always)] + pub fn tseg2(&mut self) -> TSEG2_W { + TSEG2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Timing Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctim](index.html) module"] +pub struct CTIM_SPEC; +impl crate::RegisterSpec for CTIM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctim::R](R) reader structure"] +impl crate::Readable for CTIM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctim::W](W) writer structure"] +impl crate::Writable for CTIM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTIM to value 0"] +impl crate::Resettable for CTIM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/ctmr.rs b/src/can0/ctmr.rs new file mode 100644 index 0000000..94a2236 --- /dev/null +++ b/src/can0/ctmr.rs @@ -0,0 +1,53 @@ +#[doc = "Register `CTMR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CTMR` reader - Time Stamp Counter"] +pub struct CTMR_R(crate::FieldReader); +impl CTMR_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + CTMR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTMR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:15 - Time Stamp Counter"] + #[inline(always)] + pub fn ctmr(&self) -> CTMR_R { + CTMR_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "CAN Timer Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctmr](index.html) module"] +pub struct CTMR_SPEC; +impl crate::RegisterSpec for CTMR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctmr::R](R) reader structure"] +impl crate::Readable for CTMR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CTMR to value 0"] +impl crate::Resettable for CTMR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb0.rs b/src/can0/data0_cmb0.rs new file mode 100644 index 0000000..87a6731 --- /dev/null +++ b/src/can0/data0_cmb0.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb0](index.html) module"] +pub struct DATA0_CMB0_SPEC; +impl crate::RegisterSpec for DATA0_CMB0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb0::R](R) reader structure"] +impl crate::Readable for DATA0_CMB0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb0::W](W) writer structure"] +impl crate::Writable for DATA0_CMB0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB0 to value 0"] +impl crate::Resettable for DATA0_CMB0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb1.rs b/src/can0/data0_cmb1.rs new file mode 100644 index 0000000..5f0bdb0 --- /dev/null +++ b/src/can0/data0_cmb1.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb1](index.html) module"] +pub struct DATA0_CMB1_SPEC; +impl crate::RegisterSpec for DATA0_CMB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb1::R](R) reader structure"] +impl crate::Readable for DATA0_CMB1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb1::W](W) writer structure"] +impl crate::Writable for DATA0_CMB1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB1 to value 0"] +impl crate::Resettable for DATA0_CMB1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb10.rs b/src/can0/data0_cmb10.rs new file mode 100644 index 0000000..0190436 --- /dev/null +++ b/src/can0/data0_cmb10.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb10](index.html) module"] +pub struct DATA0_CMB10_SPEC; +impl crate::RegisterSpec for DATA0_CMB10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb10::R](R) reader structure"] +impl crate::Readable for DATA0_CMB10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb10::W](W) writer structure"] +impl crate::Writable for DATA0_CMB10_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB10 to value 0"] +impl crate::Resettable for DATA0_CMB10_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb11.rs b/src/can0/data0_cmb11.rs new file mode 100644 index 0000000..e2fee80 --- /dev/null +++ b/src/can0/data0_cmb11.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb11](index.html) module"] +pub struct DATA0_CMB11_SPEC; +impl crate::RegisterSpec for DATA0_CMB11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb11::R](R) reader structure"] +impl crate::Readable for DATA0_CMB11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb11::W](W) writer structure"] +impl crate::Writable for DATA0_CMB11_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB11 to value 0"] +impl crate::Resettable for DATA0_CMB11_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb12.rs b/src/can0/data0_cmb12.rs new file mode 100644 index 0000000..5e2bbe5 --- /dev/null +++ b/src/can0/data0_cmb12.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb12](index.html) module"] +pub struct DATA0_CMB12_SPEC; +impl crate::RegisterSpec for DATA0_CMB12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb12::R](R) reader structure"] +impl crate::Readable for DATA0_CMB12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb12::W](W) writer structure"] +impl crate::Writable for DATA0_CMB12_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB12 to value 0"] +impl crate::Resettable for DATA0_CMB12_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb13.rs b/src/can0/data0_cmb13.rs new file mode 100644 index 0000000..b8938cc --- /dev/null +++ b/src/can0/data0_cmb13.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb13](index.html) module"] +pub struct DATA0_CMB13_SPEC; +impl crate::RegisterSpec for DATA0_CMB13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb13::R](R) reader structure"] +impl crate::Readable for DATA0_CMB13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb13::W](W) writer structure"] +impl crate::Writable for DATA0_CMB13_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB13 to value 0"] +impl crate::Resettable for DATA0_CMB13_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb14.rs b/src/can0/data0_cmb14.rs new file mode 100644 index 0000000..94001e0 --- /dev/null +++ b/src/can0/data0_cmb14.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb14](index.html) module"] +pub struct DATA0_CMB14_SPEC; +impl crate::RegisterSpec for DATA0_CMB14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb14::R](R) reader structure"] +impl crate::Readable for DATA0_CMB14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb14::W](W) writer structure"] +impl crate::Writable for DATA0_CMB14_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB14 to value 0"] +impl crate::Resettable for DATA0_CMB14_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb2.rs b/src/can0/data0_cmb2.rs new file mode 100644 index 0000000..1392dd7 --- /dev/null +++ b/src/can0/data0_cmb2.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb2](index.html) module"] +pub struct DATA0_CMB2_SPEC; +impl crate::RegisterSpec for DATA0_CMB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb2::R](R) reader structure"] +impl crate::Readable for DATA0_CMB2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb2::W](W) writer structure"] +impl crate::Writable for DATA0_CMB2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB2 to value 0"] +impl crate::Resettable for DATA0_CMB2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb3.rs b/src/can0/data0_cmb3.rs new file mode 100644 index 0000000..aff06b5 --- /dev/null +++ b/src/can0/data0_cmb3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb3](index.html) module"] +pub struct DATA0_CMB3_SPEC; +impl crate::RegisterSpec for DATA0_CMB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb3::R](R) reader structure"] +impl crate::Readable for DATA0_CMB3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb3::W](W) writer structure"] +impl crate::Writable for DATA0_CMB3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB3 to value 0"] +impl crate::Resettable for DATA0_CMB3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb4.rs b/src/can0/data0_cmb4.rs new file mode 100644 index 0000000..bf3f2ef --- /dev/null +++ b/src/can0/data0_cmb4.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb4](index.html) module"] +pub struct DATA0_CMB4_SPEC; +impl crate::RegisterSpec for DATA0_CMB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb4::R](R) reader structure"] +impl crate::Readable for DATA0_CMB4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb4::W](W) writer structure"] +impl crate::Writable for DATA0_CMB4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB4 to value 0"] +impl crate::Resettable for DATA0_CMB4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb5.rs b/src/can0/data0_cmb5.rs new file mode 100644 index 0000000..a45b5b0 --- /dev/null +++ b/src/can0/data0_cmb5.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb5](index.html) module"] +pub struct DATA0_CMB5_SPEC; +impl crate::RegisterSpec for DATA0_CMB5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb5::R](R) reader structure"] +impl crate::Readable for DATA0_CMB5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb5::W](W) writer structure"] +impl crate::Writable for DATA0_CMB5_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB5 to value 0"] +impl crate::Resettable for DATA0_CMB5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb6.rs b/src/can0/data0_cmb6.rs new file mode 100644 index 0000000..2ba1514 --- /dev/null +++ b/src/can0/data0_cmb6.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb6](index.html) module"] +pub struct DATA0_CMB6_SPEC; +impl crate::RegisterSpec for DATA0_CMB6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb6::R](R) reader structure"] +impl crate::Readable for DATA0_CMB6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb6::W](W) writer structure"] +impl crate::Writable for DATA0_CMB6_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB6 to value 0"] +impl crate::Resettable for DATA0_CMB6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb7.rs b/src/can0/data0_cmb7.rs new file mode 100644 index 0000000..2634861 --- /dev/null +++ b/src/can0/data0_cmb7.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb7](index.html) module"] +pub struct DATA0_CMB7_SPEC; +impl crate::RegisterSpec for DATA0_CMB7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb7::R](R) reader structure"] +impl crate::Readable for DATA0_CMB7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb7::W](W) writer structure"] +impl crate::Writable for DATA0_CMB7_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB7 to value 0"] +impl crate::Resettable for DATA0_CMB7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb8.rs b/src/can0/data0_cmb8.rs new file mode 100644 index 0000000..c074139 --- /dev/null +++ b/src/can0/data0_cmb8.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb8](index.html) module"] +pub struct DATA0_CMB8_SPEC; +impl crate::RegisterSpec for DATA0_CMB8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb8::R](R) reader structure"] +impl crate::Readable for DATA0_CMB8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb8::W](W) writer structure"] +impl crate::Writable for DATA0_CMB8_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB8 to value 0"] +impl crate::Resettable for DATA0_CMB8_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_cmb9.rs b/src/can0/data0_cmb9.rs new file mode 100644 index 0000000..873bd2b --- /dev/null +++ b/src/can0/data0_cmb9.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_CMB9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_CMB9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_cmb9](index.html) module"] +pub struct DATA0_CMB9_SPEC; +impl crate::RegisterSpec for DATA0_CMB9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_cmb9::R](R) reader structure"] +impl crate::Readable for DATA0_CMB9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_cmb9::W](W) writer structure"] +impl crate::Writable for DATA0_CMB9_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_CMB9 to value 0"] +impl crate::Resettable for DATA0_CMB9_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data0_hcmb.rs b/src/can0/data0_hcmb.rs new file mode 100644 index 0000000..4166962 --- /dev/null +++ b/src/can0/data0_hcmb.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA0_HCMB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA0_HCMB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub struct BYTE1_R(crate::FieldReader); +impl BYTE1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub struct BYTE1_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub struct BYTE2_R(crate::FieldReader); +impl BYTE2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub struct BYTE2_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> BYTE1_R { + BYTE1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> BYTE2_R { + BYTE2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> BYTE1_W { + BYTE1_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> BYTE2_W { + BYTE2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data0_hcmb](index.html) module"] +pub struct DATA0_HCMB_SPEC; +impl crate::RegisterSpec for DATA0_HCMB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data0_hcmb::R](R) reader structure"] +impl crate::Readable for DATA0_HCMB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data0_hcmb::W](W) writer structure"] +impl crate::Writable for DATA0_HCMB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA0_HCMB to value 0"] +impl crate::Resettable for DATA0_HCMB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb0.rs b/src/can0/data1_cmb0.rs new file mode 100644 index 0000000..2ac48f8 --- /dev/null +++ b/src/can0/data1_cmb0.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb0](index.html) module"] +pub struct DATA1_CMB0_SPEC; +impl crate::RegisterSpec for DATA1_CMB0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb0::R](R) reader structure"] +impl crate::Readable for DATA1_CMB0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb0::W](W) writer structure"] +impl crate::Writable for DATA1_CMB0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB0 to value 0"] +impl crate::Resettable for DATA1_CMB0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb1.rs b/src/can0/data1_cmb1.rs new file mode 100644 index 0000000..52952b7 --- /dev/null +++ b/src/can0/data1_cmb1.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb1](index.html) module"] +pub struct DATA1_CMB1_SPEC; +impl crate::RegisterSpec for DATA1_CMB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb1::R](R) reader structure"] +impl crate::Readable for DATA1_CMB1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb1::W](W) writer structure"] +impl crate::Writable for DATA1_CMB1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB1 to value 0"] +impl crate::Resettable for DATA1_CMB1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb10.rs b/src/can0/data1_cmb10.rs new file mode 100644 index 0000000..f82a89f --- /dev/null +++ b/src/can0/data1_cmb10.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb10](index.html) module"] +pub struct DATA1_CMB10_SPEC; +impl crate::RegisterSpec for DATA1_CMB10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb10::R](R) reader structure"] +impl crate::Readable for DATA1_CMB10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb10::W](W) writer structure"] +impl crate::Writable for DATA1_CMB10_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB10 to value 0"] +impl crate::Resettable for DATA1_CMB10_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb11.rs b/src/can0/data1_cmb11.rs new file mode 100644 index 0000000..ce22304 --- /dev/null +++ b/src/can0/data1_cmb11.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb11](index.html) module"] +pub struct DATA1_CMB11_SPEC; +impl crate::RegisterSpec for DATA1_CMB11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb11::R](R) reader structure"] +impl crate::Readable for DATA1_CMB11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb11::W](W) writer structure"] +impl crate::Writable for DATA1_CMB11_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB11 to value 0"] +impl crate::Resettable for DATA1_CMB11_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb12.rs b/src/can0/data1_cmb12.rs new file mode 100644 index 0000000..8c861e7 --- /dev/null +++ b/src/can0/data1_cmb12.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb12](index.html) module"] +pub struct DATA1_CMB12_SPEC; +impl crate::RegisterSpec for DATA1_CMB12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb12::R](R) reader structure"] +impl crate::Readable for DATA1_CMB12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb12::W](W) writer structure"] +impl crate::Writable for DATA1_CMB12_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB12 to value 0"] +impl crate::Resettable for DATA1_CMB12_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb13.rs b/src/can0/data1_cmb13.rs new file mode 100644 index 0000000..1db6b66 --- /dev/null +++ b/src/can0/data1_cmb13.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb13](index.html) module"] +pub struct DATA1_CMB13_SPEC; +impl crate::RegisterSpec for DATA1_CMB13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb13::R](R) reader structure"] +impl crate::Readable for DATA1_CMB13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb13::W](W) writer structure"] +impl crate::Writable for DATA1_CMB13_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB13 to value 0"] +impl crate::Resettable for DATA1_CMB13_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb14.rs b/src/can0/data1_cmb14.rs new file mode 100644 index 0000000..b4ac3bd --- /dev/null +++ b/src/can0/data1_cmb14.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb14](index.html) module"] +pub struct DATA1_CMB14_SPEC; +impl crate::RegisterSpec for DATA1_CMB14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb14::R](R) reader structure"] +impl crate::Readable for DATA1_CMB14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb14::W](W) writer structure"] +impl crate::Writable for DATA1_CMB14_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB14 to value 0"] +impl crate::Resettable for DATA1_CMB14_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb2.rs b/src/can0/data1_cmb2.rs new file mode 100644 index 0000000..2106284 --- /dev/null +++ b/src/can0/data1_cmb2.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb2](index.html) module"] +pub struct DATA1_CMB2_SPEC; +impl crate::RegisterSpec for DATA1_CMB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb2::R](R) reader structure"] +impl crate::Readable for DATA1_CMB2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb2::W](W) writer structure"] +impl crate::Writable for DATA1_CMB2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB2 to value 0"] +impl crate::Resettable for DATA1_CMB2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb3.rs b/src/can0/data1_cmb3.rs new file mode 100644 index 0000000..e2ac3aa --- /dev/null +++ b/src/can0/data1_cmb3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb3](index.html) module"] +pub struct DATA1_CMB3_SPEC; +impl crate::RegisterSpec for DATA1_CMB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb3::R](R) reader structure"] +impl crate::Readable for DATA1_CMB3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb3::W](W) writer structure"] +impl crate::Writable for DATA1_CMB3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB3 to value 0"] +impl crate::Resettable for DATA1_CMB3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb4.rs b/src/can0/data1_cmb4.rs new file mode 100644 index 0000000..83aea2b --- /dev/null +++ b/src/can0/data1_cmb4.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb4](index.html) module"] +pub struct DATA1_CMB4_SPEC; +impl crate::RegisterSpec for DATA1_CMB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb4::R](R) reader structure"] +impl crate::Readable for DATA1_CMB4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb4::W](W) writer structure"] +impl crate::Writable for DATA1_CMB4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB4 to value 0"] +impl crate::Resettable for DATA1_CMB4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb5.rs b/src/can0/data1_cmb5.rs new file mode 100644 index 0000000..d92877d --- /dev/null +++ b/src/can0/data1_cmb5.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb5](index.html) module"] +pub struct DATA1_CMB5_SPEC; +impl crate::RegisterSpec for DATA1_CMB5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb5::R](R) reader structure"] +impl crate::Readable for DATA1_CMB5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb5::W](W) writer structure"] +impl crate::Writable for DATA1_CMB5_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB5 to value 0"] +impl crate::Resettable for DATA1_CMB5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb6.rs b/src/can0/data1_cmb6.rs new file mode 100644 index 0000000..18fa007 --- /dev/null +++ b/src/can0/data1_cmb6.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb6](index.html) module"] +pub struct DATA1_CMB6_SPEC; +impl crate::RegisterSpec for DATA1_CMB6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb6::R](R) reader structure"] +impl crate::Readable for DATA1_CMB6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb6::W](W) writer structure"] +impl crate::Writable for DATA1_CMB6_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB6 to value 0"] +impl crate::Resettable for DATA1_CMB6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb7.rs b/src/can0/data1_cmb7.rs new file mode 100644 index 0000000..827f38f --- /dev/null +++ b/src/can0/data1_cmb7.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb7](index.html) module"] +pub struct DATA1_CMB7_SPEC; +impl crate::RegisterSpec for DATA1_CMB7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb7::R](R) reader structure"] +impl crate::Readable for DATA1_CMB7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb7::W](W) writer structure"] +impl crate::Writable for DATA1_CMB7_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB7 to value 0"] +impl crate::Resettable for DATA1_CMB7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb8.rs b/src/can0/data1_cmb8.rs new file mode 100644 index 0000000..105989f --- /dev/null +++ b/src/can0/data1_cmb8.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb8](index.html) module"] +pub struct DATA1_CMB8_SPEC; +impl crate::RegisterSpec for DATA1_CMB8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb8::R](R) reader structure"] +impl crate::Readable for DATA1_CMB8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb8::W](W) writer structure"] +impl crate::Writable for DATA1_CMB8_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB8 to value 0"] +impl crate::Resettable for DATA1_CMB8_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_cmb9.rs b/src/can0/data1_cmb9.rs new file mode 100644 index 0000000..537630b --- /dev/null +++ b/src/can0/data1_cmb9.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_CMB9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_CMB9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_cmb9](index.html) module"] +pub struct DATA1_CMB9_SPEC; +impl crate::RegisterSpec for DATA1_CMB9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_cmb9::R](R) reader structure"] +impl crate::Readable for DATA1_CMB9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_cmb9::W](W) writer structure"] +impl crate::Writable for DATA1_CMB9_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_CMB9 to value 0"] +impl crate::Resettable for DATA1_CMB9_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data1_hcmb.rs b/src/can0/data1_hcmb.rs new file mode 100644 index 0000000..ed2864e --- /dev/null +++ b/src/can0/data1_hcmb.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA1_HCMB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA1_HCMB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub struct BYTE3_R(crate::FieldReader); +impl BYTE3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub struct BYTE3_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub struct BYTE4_R(crate::FieldReader); +impl BYTE4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub struct BYTE4_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> BYTE3_R { + BYTE3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> BYTE4_R { + BYTE4_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> BYTE3_W { + BYTE3_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> BYTE4_W { + BYTE4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data1_hcmb](index.html) module"] +pub struct DATA1_HCMB_SPEC; +impl crate::RegisterSpec for DATA1_HCMB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data1_hcmb::R](R) reader structure"] +impl crate::Readable for DATA1_HCMB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data1_hcmb::W](W) writer structure"] +impl crate::Writable for DATA1_HCMB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA1_HCMB to value 0"] +impl crate::Resettable for DATA1_HCMB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb0.rs b/src/can0/data2_cmb0.rs new file mode 100644 index 0000000..8a12713 --- /dev/null +++ b/src/can0/data2_cmb0.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb0](index.html) module"] +pub struct DATA2_CMB0_SPEC; +impl crate::RegisterSpec for DATA2_CMB0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb0::R](R) reader structure"] +impl crate::Readable for DATA2_CMB0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb0::W](W) writer structure"] +impl crate::Writable for DATA2_CMB0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB0 to value 0"] +impl crate::Resettable for DATA2_CMB0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb1.rs b/src/can0/data2_cmb1.rs new file mode 100644 index 0000000..f2337d9 --- /dev/null +++ b/src/can0/data2_cmb1.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb1](index.html) module"] +pub struct DATA2_CMB1_SPEC; +impl crate::RegisterSpec for DATA2_CMB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb1::R](R) reader structure"] +impl crate::Readable for DATA2_CMB1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb1::W](W) writer structure"] +impl crate::Writable for DATA2_CMB1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB1 to value 0"] +impl crate::Resettable for DATA2_CMB1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb10.rs b/src/can0/data2_cmb10.rs new file mode 100644 index 0000000..5f39cdf --- /dev/null +++ b/src/can0/data2_cmb10.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb10](index.html) module"] +pub struct DATA2_CMB10_SPEC; +impl crate::RegisterSpec for DATA2_CMB10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb10::R](R) reader structure"] +impl crate::Readable for DATA2_CMB10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb10::W](W) writer structure"] +impl crate::Writable for DATA2_CMB10_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB10 to value 0"] +impl crate::Resettable for DATA2_CMB10_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb11.rs b/src/can0/data2_cmb11.rs new file mode 100644 index 0000000..b6a7665 --- /dev/null +++ b/src/can0/data2_cmb11.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb11](index.html) module"] +pub struct DATA2_CMB11_SPEC; +impl crate::RegisterSpec for DATA2_CMB11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb11::R](R) reader structure"] +impl crate::Readable for DATA2_CMB11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb11::W](W) writer structure"] +impl crate::Writable for DATA2_CMB11_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB11 to value 0"] +impl crate::Resettable for DATA2_CMB11_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb12.rs b/src/can0/data2_cmb12.rs new file mode 100644 index 0000000..e6b811c --- /dev/null +++ b/src/can0/data2_cmb12.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb12](index.html) module"] +pub struct DATA2_CMB12_SPEC; +impl crate::RegisterSpec for DATA2_CMB12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb12::R](R) reader structure"] +impl crate::Readable for DATA2_CMB12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb12::W](W) writer structure"] +impl crate::Writable for DATA2_CMB12_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB12 to value 0"] +impl crate::Resettable for DATA2_CMB12_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb13.rs b/src/can0/data2_cmb13.rs new file mode 100644 index 0000000..1039ff1 --- /dev/null +++ b/src/can0/data2_cmb13.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb13](index.html) module"] +pub struct DATA2_CMB13_SPEC; +impl crate::RegisterSpec for DATA2_CMB13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb13::R](R) reader structure"] +impl crate::Readable for DATA2_CMB13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb13::W](W) writer structure"] +impl crate::Writable for DATA2_CMB13_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB13 to value 0"] +impl crate::Resettable for DATA2_CMB13_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb14.rs b/src/can0/data2_cmb14.rs new file mode 100644 index 0000000..3dc1c19 --- /dev/null +++ b/src/can0/data2_cmb14.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb14](index.html) module"] +pub struct DATA2_CMB14_SPEC; +impl crate::RegisterSpec for DATA2_CMB14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb14::R](R) reader structure"] +impl crate::Readable for DATA2_CMB14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb14::W](W) writer structure"] +impl crate::Writable for DATA2_CMB14_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB14 to value 0"] +impl crate::Resettable for DATA2_CMB14_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb2.rs b/src/can0/data2_cmb2.rs new file mode 100644 index 0000000..4f018eb --- /dev/null +++ b/src/can0/data2_cmb2.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb2](index.html) module"] +pub struct DATA2_CMB2_SPEC; +impl crate::RegisterSpec for DATA2_CMB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb2::R](R) reader structure"] +impl crate::Readable for DATA2_CMB2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb2::W](W) writer structure"] +impl crate::Writable for DATA2_CMB2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB2 to value 0"] +impl crate::Resettable for DATA2_CMB2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb3.rs b/src/can0/data2_cmb3.rs new file mode 100644 index 0000000..9c79da6 --- /dev/null +++ b/src/can0/data2_cmb3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb3](index.html) module"] +pub struct DATA2_CMB3_SPEC; +impl crate::RegisterSpec for DATA2_CMB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb3::R](R) reader structure"] +impl crate::Readable for DATA2_CMB3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb3::W](W) writer structure"] +impl crate::Writable for DATA2_CMB3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB3 to value 0"] +impl crate::Resettable for DATA2_CMB3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb4.rs b/src/can0/data2_cmb4.rs new file mode 100644 index 0000000..07d76a4 --- /dev/null +++ b/src/can0/data2_cmb4.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb4](index.html) module"] +pub struct DATA2_CMB4_SPEC; +impl crate::RegisterSpec for DATA2_CMB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb4::R](R) reader structure"] +impl crate::Readable for DATA2_CMB4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb4::W](W) writer structure"] +impl crate::Writable for DATA2_CMB4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB4 to value 0"] +impl crate::Resettable for DATA2_CMB4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb5.rs b/src/can0/data2_cmb5.rs new file mode 100644 index 0000000..0507ea7 --- /dev/null +++ b/src/can0/data2_cmb5.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb5](index.html) module"] +pub struct DATA2_CMB5_SPEC; +impl crate::RegisterSpec for DATA2_CMB5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb5::R](R) reader structure"] +impl crate::Readable for DATA2_CMB5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb5::W](W) writer structure"] +impl crate::Writable for DATA2_CMB5_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB5 to value 0"] +impl crate::Resettable for DATA2_CMB5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb6.rs b/src/can0/data2_cmb6.rs new file mode 100644 index 0000000..a6185aa --- /dev/null +++ b/src/can0/data2_cmb6.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb6](index.html) module"] +pub struct DATA2_CMB6_SPEC; +impl crate::RegisterSpec for DATA2_CMB6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb6::R](R) reader structure"] +impl crate::Readable for DATA2_CMB6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb6::W](W) writer structure"] +impl crate::Writable for DATA2_CMB6_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB6 to value 0"] +impl crate::Resettable for DATA2_CMB6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb7.rs b/src/can0/data2_cmb7.rs new file mode 100644 index 0000000..761a033 --- /dev/null +++ b/src/can0/data2_cmb7.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb7](index.html) module"] +pub struct DATA2_CMB7_SPEC; +impl crate::RegisterSpec for DATA2_CMB7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb7::R](R) reader structure"] +impl crate::Readable for DATA2_CMB7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb7::W](W) writer structure"] +impl crate::Writable for DATA2_CMB7_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB7 to value 0"] +impl crate::Resettable for DATA2_CMB7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb8.rs b/src/can0/data2_cmb8.rs new file mode 100644 index 0000000..395a922 --- /dev/null +++ b/src/can0/data2_cmb8.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb8](index.html) module"] +pub struct DATA2_CMB8_SPEC; +impl crate::RegisterSpec for DATA2_CMB8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb8::R](R) reader structure"] +impl crate::Readable for DATA2_CMB8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb8::W](W) writer structure"] +impl crate::Writable for DATA2_CMB8_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB8 to value 0"] +impl crate::Resettable for DATA2_CMB8_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_cmb9.rs b/src/can0/data2_cmb9.rs new file mode 100644 index 0000000..310fcd6 --- /dev/null +++ b/src/can0/data2_cmb9.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_CMB9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_CMB9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_cmb9](index.html) module"] +pub struct DATA2_CMB9_SPEC; +impl crate::RegisterSpec for DATA2_CMB9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_cmb9::R](R) reader structure"] +impl crate::Readable for DATA2_CMB9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_cmb9::W](W) writer structure"] +impl crate::Writable for DATA2_CMB9_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_CMB9 to value 0"] +impl crate::Resettable for DATA2_CMB9_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data2_hcmb.rs b/src/can0/data2_hcmb.rs new file mode 100644 index 0000000..a389749 --- /dev/null +++ b/src/can0/data2_hcmb.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA2_HCMB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA2_HCMB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub struct BYTE5_R(crate::FieldReader); +impl BYTE5_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub struct BYTE5_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE5_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub struct BYTE6_R(crate::FieldReader); +impl BYTE6_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE6_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub struct BYTE6_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE6_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> BYTE5_R { + BYTE5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> BYTE6_R { + BYTE6_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> BYTE5_W { + BYTE5_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> BYTE6_W { + BYTE6_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data2_hcmb](index.html) module"] +pub struct DATA2_HCMB_SPEC; +impl crate::RegisterSpec for DATA2_HCMB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data2_hcmb::R](R) reader structure"] +impl crate::Readable for DATA2_HCMB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data2_hcmb::W](W) writer structure"] +impl crate::Writable for DATA2_HCMB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA2_HCMB to value 0"] +impl crate::Resettable for DATA2_HCMB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb0.rs b/src/can0/data3_cmb0.rs new file mode 100644 index 0000000..526d454 --- /dev/null +++ b/src/can0/data3_cmb0.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb0](index.html) module"] +pub struct DATA3_CMB0_SPEC; +impl crate::RegisterSpec for DATA3_CMB0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb0::R](R) reader structure"] +impl crate::Readable for DATA3_CMB0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb0::W](W) writer structure"] +impl crate::Writable for DATA3_CMB0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB0 to value 0"] +impl crate::Resettable for DATA3_CMB0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb1.rs b/src/can0/data3_cmb1.rs new file mode 100644 index 0000000..29a1630 --- /dev/null +++ b/src/can0/data3_cmb1.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb1](index.html) module"] +pub struct DATA3_CMB1_SPEC; +impl crate::RegisterSpec for DATA3_CMB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb1::R](R) reader structure"] +impl crate::Readable for DATA3_CMB1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb1::W](W) writer structure"] +impl crate::Writable for DATA3_CMB1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB1 to value 0"] +impl crate::Resettable for DATA3_CMB1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb10.rs b/src/can0/data3_cmb10.rs new file mode 100644 index 0000000..1c24934 --- /dev/null +++ b/src/can0/data3_cmb10.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb10](index.html) module"] +pub struct DATA3_CMB10_SPEC; +impl crate::RegisterSpec for DATA3_CMB10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb10::R](R) reader structure"] +impl crate::Readable for DATA3_CMB10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb10::W](W) writer structure"] +impl crate::Writable for DATA3_CMB10_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB10 to value 0"] +impl crate::Resettable for DATA3_CMB10_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb11.rs b/src/can0/data3_cmb11.rs new file mode 100644 index 0000000..3ddb29b --- /dev/null +++ b/src/can0/data3_cmb11.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb11](index.html) module"] +pub struct DATA3_CMB11_SPEC; +impl crate::RegisterSpec for DATA3_CMB11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb11::R](R) reader structure"] +impl crate::Readable for DATA3_CMB11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb11::W](W) writer structure"] +impl crate::Writable for DATA3_CMB11_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB11 to value 0"] +impl crate::Resettable for DATA3_CMB11_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb12.rs b/src/can0/data3_cmb12.rs new file mode 100644 index 0000000..18d9fd5 --- /dev/null +++ b/src/can0/data3_cmb12.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb12](index.html) module"] +pub struct DATA3_CMB12_SPEC; +impl crate::RegisterSpec for DATA3_CMB12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb12::R](R) reader structure"] +impl crate::Readable for DATA3_CMB12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb12::W](W) writer structure"] +impl crate::Writable for DATA3_CMB12_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB12 to value 0"] +impl crate::Resettable for DATA3_CMB12_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb13.rs b/src/can0/data3_cmb13.rs new file mode 100644 index 0000000..8e375c4 --- /dev/null +++ b/src/can0/data3_cmb13.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb13](index.html) module"] +pub struct DATA3_CMB13_SPEC; +impl crate::RegisterSpec for DATA3_CMB13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb13::R](R) reader structure"] +impl crate::Readable for DATA3_CMB13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb13::W](W) writer structure"] +impl crate::Writable for DATA3_CMB13_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB13 to value 0"] +impl crate::Resettable for DATA3_CMB13_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb14.rs b/src/can0/data3_cmb14.rs new file mode 100644 index 0000000..5de083f --- /dev/null +++ b/src/can0/data3_cmb14.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb14](index.html) module"] +pub struct DATA3_CMB14_SPEC; +impl crate::RegisterSpec for DATA3_CMB14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb14::R](R) reader structure"] +impl crate::Readable for DATA3_CMB14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb14::W](W) writer structure"] +impl crate::Writable for DATA3_CMB14_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB14 to value 0"] +impl crate::Resettable for DATA3_CMB14_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb2.rs b/src/can0/data3_cmb2.rs new file mode 100644 index 0000000..0915773 --- /dev/null +++ b/src/can0/data3_cmb2.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb2](index.html) module"] +pub struct DATA3_CMB2_SPEC; +impl crate::RegisterSpec for DATA3_CMB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb2::R](R) reader structure"] +impl crate::Readable for DATA3_CMB2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb2::W](W) writer structure"] +impl crate::Writable for DATA3_CMB2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB2 to value 0"] +impl crate::Resettable for DATA3_CMB2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb3.rs b/src/can0/data3_cmb3.rs new file mode 100644 index 0000000..5cb0bf0 --- /dev/null +++ b/src/can0/data3_cmb3.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb3](index.html) module"] +pub struct DATA3_CMB3_SPEC; +impl crate::RegisterSpec for DATA3_CMB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb3::R](R) reader structure"] +impl crate::Readable for DATA3_CMB3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb3::W](W) writer structure"] +impl crate::Writable for DATA3_CMB3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB3 to value 0"] +impl crate::Resettable for DATA3_CMB3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb4.rs b/src/can0/data3_cmb4.rs new file mode 100644 index 0000000..f741827 --- /dev/null +++ b/src/can0/data3_cmb4.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb4](index.html) module"] +pub struct DATA3_CMB4_SPEC; +impl crate::RegisterSpec for DATA3_CMB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb4::R](R) reader structure"] +impl crate::Readable for DATA3_CMB4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb4::W](W) writer structure"] +impl crate::Writable for DATA3_CMB4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB4 to value 0"] +impl crate::Resettable for DATA3_CMB4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb5.rs b/src/can0/data3_cmb5.rs new file mode 100644 index 0000000..aa4470f --- /dev/null +++ b/src/can0/data3_cmb5.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb5](index.html) module"] +pub struct DATA3_CMB5_SPEC; +impl crate::RegisterSpec for DATA3_CMB5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb5::R](R) reader structure"] +impl crate::Readable for DATA3_CMB5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb5::W](W) writer structure"] +impl crate::Writable for DATA3_CMB5_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB5 to value 0"] +impl crate::Resettable for DATA3_CMB5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb6.rs b/src/can0/data3_cmb6.rs new file mode 100644 index 0000000..bb809e9 --- /dev/null +++ b/src/can0/data3_cmb6.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb6](index.html) module"] +pub struct DATA3_CMB6_SPEC; +impl crate::RegisterSpec for DATA3_CMB6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb6::R](R) reader structure"] +impl crate::Readable for DATA3_CMB6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb6::W](W) writer structure"] +impl crate::Writable for DATA3_CMB6_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB6 to value 0"] +impl crate::Resettable for DATA3_CMB6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb7.rs b/src/can0/data3_cmb7.rs new file mode 100644 index 0000000..60ae85a --- /dev/null +++ b/src/can0/data3_cmb7.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb7](index.html) module"] +pub struct DATA3_CMB7_SPEC; +impl crate::RegisterSpec for DATA3_CMB7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb7::R](R) reader structure"] +impl crate::Readable for DATA3_CMB7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb7::W](W) writer structure"] +impl crate::Writable for DATA3_CMB7_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB7 to value 0"] +impl crate::Resettable for DATA3_CMB7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb8.rs b/src/can0/data3_cmb8.rs new file mode 100644 index 0000000..7fa6220 --- /dev/null +++ b/src/can0/data3_cmb8.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb8](index.html) module"] +pub struct DATA3_CMB8_SPEC; +impl crate::RegisterSpec for DATA3_CMB8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb8::R](R) reader structure"] +impl crate::Readable for DATA3_CMB8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb8::W](W) writer structure"] +impl crate::Writable for DATA3_CMB8_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB8 to value 0"] +impl crate::Resettable for DATA3_CMB8_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_cmb9.rs b/src/can0/data3_cmb9.rs new file mode 100644 index 0000000..27605b6 --- /dev/null +++ b/src/can0/data3_cmb9.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_CMB9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_CMB9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_cmb9](index.html) module"] +pub struct DATA3_CMB9_SPEC; +impl crate::RegisterSpec for DATA3_CMB9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_cmb9::R](R) reader structure"] +impl crate::Readable for DATA3_CMB9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_cmb9::W](W) writer structure"] +impl crate::Writable for DATA3_CMB9_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_CMB9 to value 0"] +impl crate::Resettable for DATA3_CMB9_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/data3_hcmb.rs b/src/can0/data3_hcmb.rs new file mode 100644 index 0000000..34f5f5c --- /dev/null +++ b/src/can0/data3_hcmb.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DATA3_HCMB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA3_HCMB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub struct BYTE7_R(crate::FieldReader); +impl BYTE7_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE7_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub struct BYTE7_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE7_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub struct BYTE8_R(crate::FieldReader); +impl BYTE8_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BYTE8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BYTE8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub struct BYTE8_W<'a> { + w: &'a mut W, +} +impl<'a> BYTE8_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> BYTE7_R { + BYTE7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> BYTE8_R { + BYTE8_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> BYTE7_W { + BYTE7_W { w: self } + } + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> BYTE8_W { + BYTE8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Data Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data3_hcmb](index.html) module"] +pub struct DATA3_HCMB_SPEC; +impl crate::RegisterSpec for DATA3_HCMB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data3_hcmb::R](R) reader structure"] +impl crate::Readable for DATA3_HCMB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data3_hcmb::W](W) writer structure"] +impl crate::Writable for DATA3_HCMB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA3_HCMB to value 0"] +impl crate::Resettable for DATA3_HCMB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/gmskb.rs b/src/can0/gmskb.rs new file mode 100644 index 0000000..f1b4b3b --- /dev/null +++ b/src/can0/gmskb.rs @@ -0,0 +1,254 @@ +#[doc = "Register `GMSKB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GMSKB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GM1` reader - GM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] +pub struct GM1_R(crate::FieldReader); +impl GM1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GM1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GM1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GM1` writer - GM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] +pub struct GM1_W<'a> { + w: &'a mut W, +} +impl<'a> GM1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 5)) | ((value as u32 & 0x07ff) << 5); + self.w + } +} +#[doc = "Field `RTR` reader - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub struct RTR_R(crate::FieldReader); +impl RTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTR` writer - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub struct RTR_W<'a> { + w: &'a mut W, +} +impl<'a> RTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `IDE` reader - Identifier Extension Bit"] +pub struct IDE_R(crate::FieldReader); +impl IDE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDE` writer - Identifier Extension Bit"] +pub struct IDE_W<'a> { + w: &'a mut W, +} +impl<'a> IDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `GM0` reader - GM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] +pub struct GM0_R(crate::FieldReader); +impl GM0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GM0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GM0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GM0` writer - GM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] +pub struct GM0_W<'a> { + w: &'a mut W, +} +impl<'a> GM0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 5:15 - GM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] + #[inline(always)] + pub fn gm1(&self) -> GM1_R { + GM1_R::new(((self.bits >> 5) & 0x07ff) as u16) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&self) -> RTR_R { + RTR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&self) -> IDE_R { + IDE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 0:2 - GM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] + #[inline(always)] + pub fn gm0(&self) -> GM0_R { + GM0_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 5:15 - GM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] + #[inline(always)] + pub fn gm1(&mut self) -> GM1_W { + GM1_W { w: self } + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&mut self) -> RTR_W { + RTR_W { w: self } + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&mut self) -> IDE_W { + IDE_W { w: self } + } + #[doc = "Bits 0:2 - GM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] + #[inline(always)] + pub fn gm0(&mut self) -> GM0_W { + GM0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Global Mask Base\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gmskb](index.html) module"] +pub struct GMSKB_SPEC; +impl crate::RegisterSpec for GMSKB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gmskb::R](R) reader structure"] +impl crate::Readable for GMSKB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gmskb::W](W) writer structure"] +impl crate::Writable for GMSKB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GMSKB to value 0"] +impl crate::Resettable for GMSKB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/gmskx.rs b/src/can0/gmskx.rs new file mode 100644 index 0000000..e3934dd --- /dev/null +++ b/src/can0/gmskx.rs @@ -0,0 +1,158 @@ +#[doc = "Register `GMSKX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GMSKX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GM` reader - GM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] +pub struct GM_R(crate::FieldReader); +impl GM_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GM` writer - GM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] +pub struct GM_W<'a> { + w: &'a mut W, +} +impl<'a> GM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7fff << 1)) | ((value as u32 & 0x7fff) << 1); + self.w + } +} +#[doc = "Field `XRTR` reader - Extended Remote transmission Request Bit"] +pub struct XRTR_R(crate::FieldReader); +impl XRTR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XRTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XRTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XRTR` writer - Extended Remote transmission Request Bit"] +pub struct XRTR_W<'a> { + w: &'a mut W, +} +impl<'a> XRTR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bits 1:15 - GM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] + #[inline(always)] + pub fn gm(&self) -> GM_R { + GM_R::new(((self.bits >> 1) & 0x7fff) as u16) + } + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&self) -> XRTR_R { + XRTR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 1:15 - GM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] + #[inline(always)] + pub fn gm(&mut self) -> GM_W { + GM_W { w: self } + } + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&mut self) -> XRTR_W { + XRTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Global Mask Extension\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gmskx](index.html) module"] +pub struct GMSKX_SPEC; +impl crate::RegisterSpec for GMSKX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gmskx::R](R) reader structure"] +impl crate::Readable for GMSKX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gmskx::W](W) writer structure"] +impl crate::Writable for GMSKX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets GMSKX to value 0"] +impl crate::Resettable for GMSKX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb0.rs b/src/can0/id0_cmb0.rs new file mode 100644 index 0000000..bb437fa --- /dev/null +++ b/src/can0/id0_cmb0.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb0](index.html) module"] +pub struct ID0_CMB0_SPEC; +impl crate::RegisterSpec for ID0_CMB0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb0::R](R) reader structure"] +impl crate::Readable for ID0_CMB0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb0::W](W) writer structure"] +impl crate::Writable for ID0_CMB0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB0 to value 0"] +impl crate::Resettable for ID0_CMB0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb1.rs b/src/can0/id0_cmb1.rs new file mode 100644 index 0000000..62d07b6 --- /dev/null +++ b/src/can0/id0_cmb1.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb1](index.html) module"] +pub struct ID0_CMB1_SPEC; +impl crate::RegisterSpec for ID0_CMB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb1::R](R) reader structure"] +impl crate::Readable for ID0_CMB1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb1::W](W) writer structure"] +impl crate::Writable for ID0_CMB1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB1 to value 0"] +impl crate::Resettable for ID0_CMB1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb10.rs b/src/can0/id0_cmb10.rs new file mode 100644 index 0000000..62d1a50 --- /dev/null +++ b/src/can0/id0_cmb10.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb10](index.html) module"] +pub struct ID0_CMB10_SPEC; +impl crate::RegisterSpec for ID0_CMB10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb10::R](R) reader structure"] +impl crate::Readable for ID0_CMB10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb10::W](W) writer structure"] +impl crate::Writable for ID0_CMB10_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB10 to value 0"] +impl crate::Resettable for ID0_CMB10_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb11.rs b/src/can0/id0_cmb11.rs new file mode 100644 index 0000000..9f9b2b1 --- /dev/null +++ b/src/can0/id0_cmb11.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb11](index.html) module"] +pub struct ID0_CMB11_SPEC; +impl crate::RegisterSpec for ID0_CMB11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb11::R](R) reader structure"] +impl crate::Readable for ID0_CMB11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb11::W](W) writer structure"] +impl crate::Writable for ID0_CMB11_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB11 to value 0"] +impl crate::Resettable for ID0_CMB11_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb12.rs b/src/can0/id0_cmb12.rs new file mode 100644 index 0000000..b99fde3 --- /dev/null +++ b/src/can0/id0_cmb12.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb12](index.html) module"] +pub struct ID0_CMB12_SPEC; +impl crate::RegisterSpec for ID0_CMB12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb12::R](R) reader structure"] +impl crate::Readable for ID0_CMB12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb12::W](W) writer structure"] +impl crate::Writable for ID0_CMB12_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB12 to value 0"] +impl crate::Resettable for ID0_CMB12_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb13.rs b/src/can0/id0_cmb13.rs new file mode 100644 index 0000000..2a6c634 --- /dev/null +++ b/src/can0/id0_cmb13.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb13](index.html) module"] +pub struct ID0_CMB13_SPEC; +impl crate::RegisterSpec for ID0_CMB13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb13::R](R) reader structure"] +impl crate::Readable for ID0_CMB13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb13::W](W) writer structure"] +impl crate::Writable for ID0_CMB13_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB13 to value 0"] +impl crate::Resettable for ID0_CMB13_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb14.rs b/src/can0/id0_cmb14.rs new file mode 100644 index 0000000..f89f538 --- /dev/null +++ b/src/can0/id0_cmb14.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb14](index.html) module"] +pub struct ID0_CMB14_SPEC; +impl crate::RegisterSpec for ID0_CMB14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb14::R](R) reader structure"] +impl crate::Readable for ID0_CMB14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb14::W](W) writer structure"] +impl crate::Writable for ID0_CMB14_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB14 to value 0"] +impl crate::Resettable for ID0_CMB14_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb2.rs b/src/can0/id0_cmb2.rs new file mode 100644 index 0000000..9099d00 --- /dev/null +++ b/src/can0/id0_cmb2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb2](index.html) module"] +pub struct ID0_CMB2_SPEC; +impl crate::RegisterSpec for ID0_CMB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb2::R](R) reader structure"] +impl crate::Readable for ID0_CMB2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb2::W](W) writer structure"] +impl crate::Writable for ID0_CMB2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB2 to value 0"] +impl crate::Resettable for ID0_CMB2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb3.rs b/src/can0/id0_cmb3.rs new file mode 100644 index 0000000..e1996c3 --- /dev/null +++ b/src/can0/id0_cmb3.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb3](index.html) module"] +pub struct ID0_CMB3_SPEC; +impl crate::RegisterSpec for ID0_CMB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb3::R](R) reader structure"] +impl crate::Readable for ID0_CMB3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb3::W](W) writer structure"] +impl crate::Writable for ID0_CMB3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB3 to value 0"] +impl crate::Resettable for ID0_CMB3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb4.rs b/src/can0/id0_cmb4.rs new file mode 100644 index 0000000..24889c7 --- /dev/null +++ b/src/can0/id0_cmb4.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb4](index.html) module"] +pub struct ID0_CMB4_SPEC; +impl crate::RegisterSpec for ID0_CMB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb4::R](R) reader structure"] +impl crate::Readable for ID0_CMB4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb4::W](W) writer structure"] +impl crate::Writable for ID0_CMB4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB4 to value 0"] +impl crate::Resettable for ID0_CMB4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb5.rs b/src/can0/id0_cmb5.rs new file mode 100644 index 0000000..11a6b6f --- /dev/null +++ b/src/can0/id0_cmb5.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb5](index.html) module"] +pub struct ID0_CMB5_SPEC; +impl crate::RegisterSpec for ID0_CMB5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb5::R](R) reader structure"] +impl crate::Readable for ID0_CMB5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb5::W](W) writer structure"] +impl crate::Writable for ID0_CMB5_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB5 to value 0"] +impl crate::Resettable for ID0_CMB5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb6.rs b/src/can0/id0_cmb6.rs new file mode 100644 index 0000000..a591843 --- /dev/null +++ b/src/can0/id0_cmb6.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb6](index.html) module"] +pub struct ID0_CMB6_SPEC; +impl crate::RegisterSpec for ID0_CMB6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb6::R](R) reader structure"] +impl crate::Readable for ID0_CMB6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb6::W](W) writer structure"] +impl crate::Writable for ID0_CMB6_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB6 to value 0"] +impl crate::Resettable for ID0_CMB6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb7.rs b/src/can0/id0_cmb7.rs new file mode 100644 index 0000000..0cc091e --- /dev/null +++ b/src/can0/id0_cmb7.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb7](index.html) module"] +pub struct ID0_CMB7_SPEC; +impl crate::RegisterSpec for ID0_CMB7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb7::R](R) reader structure"] +impl crate::Readable for ID0_CMB7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb7::W](W) writer structure"] +impl crate::Writable for ID0_CMB7_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB7 to value 0"] +impl crate::Resettable for ID0_CMB7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb8.rs b/src/can0/id0_cmb8.rs new file mode 100644 index 0000000..829253b --- /dev/null +++ b/src/can0/id0_cmb8.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb8](index.html) module"] +pub struct ID0_CMB8_SPEC; +impl crate::RegisterSpec for ID0_CMB8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb8::R](R) reader structure"] +impl crate::Readable for ID0_CMB8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb8::W](W) writer structure"] +impl crate::Writable for ID0_CMB8_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB8 to value 0"] +impl crate::Resettable for ID0_CMB8_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_cmb9.rs b/src/can0/id0_cmb9.rs new file mode 100644 index 0000000..b1551d0 --- /dev/null +++ b/src/can0/id0_cmb9.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_CMB9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_CMB9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_cmb9](index.html) module"] +pub struct ID0_CMB9_SPEC; +impl crate::RegisterSpec for ID0_CMB9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_cmb9::R](R) reader structure"] +impl crate::Readable for ID0_CMB9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_cmb9::W](W) writer structure"] +impl crate::Writable for ID0_CMB9_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_CMB9 to value 0"] +impl crate::Resettable for ID0_CMB9_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id0_hcmb.rs b/src/can0/id0_hcmb.rs new file mode 100644 index 0000000..e094114 --- /dev/null +++ b/src/can0/id0_hcmb.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID0_HCMB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID0_HCMB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_R(crate::FieldReader); +impl ID0_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID0_W<'a> { + w: &'a mut W, +} +impl<'a> ID0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> ID0_R { + ID0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> ID0_W { + ID0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0_hcmb](index.html) module"] +pub struct ID0_HCMB_SPEC; +impl crate::RegisterSpec for ID0_HCMB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id0_hcmb::R](R) reader structure"] +impl crate::Readable for ID0_HCMB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id0_hcmb::W](W) writer structure"] +impl crate::Writable for ID0_HCMB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID0_HCMB to value 0"] +impl crate::Resettable for ID0_HCMB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb0.rs b/src/can0/id1_cmb0.rs new file mode 100644 index 0000000..ff48665 --- /dev/null +++ b/src/can0/id1_cmb0.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb0](index.html) module"] +pub struct ID1_CMB0_SPEC; +impl crate::RegisterSpec for ID1_CMB0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb0::R](R) reader structure"] +impl crate::Readable for ID1_CMB0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb0::W](W) writer structure"] +impl crate::Writable for ID1_CMB0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB0 to value 0"] +impl crate::Resettable for ID1_CMB0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb1.rs b/src/can0/id1_cmb1.rs new file mode 100644 index 0000000..2b6904e --- /dev/null +++ b/src/can0/id1_cmb1.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb1](index.html) module"] +pub struct ID1_CMB1_SPEC; +impl crate::RegisterSpec for ID1_CMB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb1::R](R) reader structure"] +impl crate::Readable for ID1_CMB1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb1::W](W) writer structure"] +impl crate::Writable for ID1_CMB1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB1 to value 0"] +impl crate::Resettable for ID1_CMB1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb10.rs b/src/can0/id1_cmb10.rs new file mode 100644 index 0000000..c605904 --- /dev/null +++ b/src/can0/id1_cmb10.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb10](index.html) module"] +pub struct ID1_CMB10_SPEC; +impl crate::RegisterSpec for ID1_CMB10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb10::R](R) reader structure"] +impl crate::Readable for ID1_CMB10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb10::W](W) writer structure"] +impl crate::Writable for ID1_CMB10_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB10 to value 0"] +impl crate::Resettable for ID1_CMB10_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb11.rs b/src/can0/id1_cmb11.rs new file mode 100644 index 0000000..fdf2759 --- /dev/null +++ b/src/can0/id1_cmb11.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb11](index.html) module"] +pub struct ID1_CMB11_SPEC; +impl crate::RegisterSpec for ID1_CMB11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb11::R](R) reader structure"] +impl crate::Readable for ID1_CMB11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb11::W](W) writer structure"] +impl crate::Writable for ID1_CMB11_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB11 to value 0"] +impl crate::Resettable for ID1_CMB11_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb12.rs b/src/can0/id1_cmb12.rs new file mode 100644 index 0000000..6b24042 --- /dev/null +++ b/src/can0/id1_cmb12.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb12](index.html) module"] +pub struct ID1_CMB12_SPEC; +impl crate::RegisterSpec for ID1_CMB12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb12::R](R) reader structure"] +impl crate::Readable for ID1_CMB12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb12::W](W) writer structure"] +impl crate::Writable for ID1_CMB12_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB12 to value 0"] +impl crate::Resettable for ID1_CMB12_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb13.rs b/src/can0/id1_cmb13.rs new file mode 100644 index 0000000..121be4d --- /dev/null +++ b/src/can0/id1_cmb13.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb13](index.html) module"] +pub struct ID1_CMB13_SPEC; +impl crate::RegisterSpec for ID1_CMB13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb13::R](R) reader structure"] +impl crate::Readable for ID1_CMB13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb13::W](W) writer structure"] +impl crate::Writable for ID1_CMB13_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB13 to value 0"] +impl crate::Resettable for ID1_CMB13_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb14.rs b/src/can0/id1_cmb14.rs new file mode 100644 index 0000000..7d8e81e --- /dev/null +++ b/src/can0/id1_cmb14.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb14](index.html) module"] +pub struct ID1_CMB14_SPEC; +impl crate::RegisterSpec for ID1_CMB14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb14::R](R) reader structure"] +impl crate::Readable for ID1_CMB14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb14::W](W) writer structure"] +impl crate::Writable for ID1_CMB14_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB14 to value 0"] +impl crate::Resettable for ID1_CMB14_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb2.rs b/src/can0/id1_cmb2.rs new file mode 100644 index 0000000..d231216 --- /dev/null +++ b/src/can0/id1_cmb2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb2](index.html) module"] +pub struct ID1_CMB2_SPEC; +impl crate::RegisterSpec for ID1_CMB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb2::R](R) reader structure"] +impl crate::Readable for ID1_CMB2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb2::W](W) writer structure"] +impl crate::Writable for ID1_CMB2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB2 to value 0"] +impl crate::Resettable for ID1_CMB2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb3.rs b/src/can0/id1_cmb3.rs new file mode 100644 index 0000000..5ef31bf --- /dev/null +++ b/src/can0/id1_cmb3.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb3](index.html) module"] +pub struct ID1_CMB3_SPEC; +impl crate::RegisterSpec for ID1_CMB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb3::R](R) reader structure"] +impl crate::Readable for ID1_CMB3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb3::W](W) writer structure"] +impl crate::Writable for ID1_CMB3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB3 to value 0"] +impl crate::Resettable for ID1_CMB3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb4.rs b/src/can0/id1_cmb4.rs new file mode 100644 index 0000000..7a7976b --- /dev/null +++ b/src/can0/id1_cmb4.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb4](index.html) module"] +pub struct ID1_CMB4_SPEC; +impl crate::RegisterSpec for ID1_CMB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb4::R](R) reader structure"] +impl crate::Readable for ID1_CMB4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb4::W](W) writer structure"] +impl crate::Writable for ID1_CMB4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB4 to value 0"] +impl crate::Resettable for ID1_CMB4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb5.rs b/src/can0/id1_cmb5.rs new file mode 100644 index 0000000..fd0d892 --- /dev/null +++ b/src/can0/id1_cmb5.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb5](index.html) module"] +pub struct ID1_CMB5_SPEC; +impl crate::RegisterSpec for ID1_CMB5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb5::R](R) reader structure"] +impl crate::Readable for ID1_CMB5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb5::W](W) writer structure"] +impl crate::Writable for ID1_CMB5_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB5 to value 0"] +impl crate::Resettable for ID1_CMB5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb6.rs b/src/can0/id1_cmb6.rs new file mode 100644 index 0000000..775c81d --- /dev/null +++ b/src/can0/id1_cmb6.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb6](index.html) module"] +pub struct ID1_CMB6_SPEC; +impl crate::RegisterSpec for ID1_CMB6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb6::R](R) reader structure"] +impl crate::Readable for ID1_CMB6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb6::W](W) writer structure"] +impl crate::Writable for ID1_CMB6_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB6 to value 0"] +impl crate::Resettable for ID1_CMB6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb7.rs b/src/can0/id1_cmb7.rs new file mode 100644 index 0000000..055c337 --- /dev/null +++ b/src/can0/id1_cmb7.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb7](index.html) module"] +pub struct ID1_CMB7_SPEC; +impl crate::RegisterSpec for ID1_CMB7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb7::R](R) reader structure"] +impl crate::Readable for ID1_CMB7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb7::W](W) writer structure"] +impl crate::Writable for ID1_CMB7_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB7 to value 0"] +impl crate::Resettable for ID1_CMB7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb8.rs b/src/can0/id1_cmb8.rs new file mode 100644 index 0000000..e1bbde4 --- /dev/null +++ b/src/can0/id1_cmb8.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb8](index.html) module"] +pub struct ID1_CMB8_SPEC; +impl crate::RegisterSpec for ID1_CMB8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb8::R](R) reader structure"] +impl crate::Readable for ID1_CMB8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb8::W](W) writer structure"] +impl crate::Writable for ID1_CMB8_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB8 to value 0"] +impl crate::Resettable for ID1_CMB8_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_cmb9.rs b/src/can0/id1_cmb9.rs new file mode 100644 index 0000000..04e0a69 --- /dev/null +++ b/src/can0/id1_cmb9.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_CMB9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_CMB9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_cmb9](index.html) module"] +pub struct ID1_CMB9_SPEC; +impl crate::RegisterSpec for ID1_CMB9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_cmb9::R](R) reader structure"] +impl crate::Readable for ID1_CMB9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_cmb9::W](W) writer structure"] +impl crate::Writable for ID1_CMB9_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_CMB9 to value 0"] +impl crate::Resettable for ID1_CMB9_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/id1_hcmb.rs b/src/can0/id1_hcmb.rs new file mode 100644 index 0000000..4467078 --- /dev/null +++ b/src/can0/id1_hcmb.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ID1_HCMB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ID1_HCMB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_R(crate::FieldReader); +impl ID1_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ID1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub struct ID1_W<'a> { + w: &'a mut W, +} +impl<'a> ID1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> ID1_R { + ID1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> ID1_W { + ID1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Identifier Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id1_hcmb](index.html) module"] +pub struct ID1_HCMB_SPEC; +impl crate::RegisterSpec for ID1_HCMB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [id1_hcmb::R](R) reader structure"] +impl crate::Readable for ID1_HCMB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [id1_hcmb::W](W) writer structure"] +impl crate::Writable for ID1_HCMB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ID1_HCMB to value 0"] +impl crate::Resettable for ID1_HCMB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb0.rs b/src/can0/tstp_cmb0.rs new file mode 100644 index 0000000..2f694cf --- /dev/null +++ b/src/can0/tstp_cmb0.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb0](index.html) module"] +pub struct TSTP_CMB0_SPEC; +impl crate::RegisterSpec for TSTP_CMB0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb0::R](R) reader structure"] +impl crate::Readable for TSTP_CMB0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb0::W](W) writer structure"] +impl crate::Writable for TSTP_CMB0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB0 to value 0"] +impl crate::Resettable for TSTP_CMB0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb1.rs b/src/can0/tstp_cmb1.rs new file mode 100644 index 0000000..a94ce9e --- /dev/null +++ b/src/can0/tstp_cmb1.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb1](index.html) module"] +pub struct TSTP_CMB1_SPEC; +impl crate::RegisterSpec for TSTP_CMB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb1::R](R) reader structure"] +impl crate::Readable for TSTP_CMB1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb1::W](W) writer structure"] +impl crate::Writable for TSTP_CMB1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB1 to value 0"] +impl crate::Resettable for TSTP_CMB1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb10.rs b/src/can0/tstp_cmb10.rs new file mode 100644 index 0000000..20389a4 --- /dev/null +++ b/src/can0/tstp_cmb10.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb10](index.html) module"] +pub struct TSTP_CMB10_SPEC; +impl crate::RegisterSpec for TSTP_CMB10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb10::R](R) reader structure"] +impl crate::Readable for TSTP_CMB10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb10::W](W) writer structure"] +impl crate::Writable for TSTP_CMB10_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB10 to value 0"] +impl crate::Resettable for TSTP_CMB10_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb11.rs b/src/can0/tstp_cmb11.rs new file mode 100644 index 0000000..83a1cff --- /dev/null +++ b/src/can0/tstp_cmb11.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB11` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB11` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb11](index.html) module"] +pub struct TSTP_CMB11_SPEC; +impl crate::RegisterSpec for TSTP_CMB11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb11::R](R) reader structure"] +impl crate::Readable for TSTP_CMB11_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb11::W](W) writer structure"] +impl crate::Writable for TSTP_CMB11_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB11 to value 0"] +impl crate::Resettable for TSTP_CMB11_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb12.rs b/src/can0/tstp_cmb12.rs new file mode 100644 index 0000000..1c24a3c --- /dev/null +++ b/src/can0/tstp_cmb12.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb12](index.html) module"] +pub struct TSTP_CMB12_SPEC; +impl crate::RegisterSpec for TSTP_CMB12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb12::R](R) reader structure"] +impl crate::Readable for TSTP_CMB12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb12::W](W) writer structure"] +impl crate::Writable for TSTP_CMB12_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB12 to value 0"] +impl crate::Resettable for TSTP_CMB12_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb13.rs b/src/can0/tstp_cmb13.rs new file mode 100644 index 0000000..48e5e7e --- /dev/null +++ b/src/can0/tstp_cmb13.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB13` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB13` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb13](index.html) module"] +pub struct TSTP_CMB13_SPEC; +impl crate::RegisterSpec for TSTP_CMB13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb13::R](R) reader structure"] +impl crate::Readable for TSTP_CMB13_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb13::W](W) writer structure"] +impl crate::Writable for TSTP_CMB13_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB13 to value 0"] +impl crate::Resettable for TSTP_CMB13_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb14.rs b/src/can0/tstp_cmb14.rs new file mode 100644 index 0000000..f495c1e --- /dev/null +++ b/src/can0/tstp_cmb14.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB14` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB14` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb14](index.html) module"] +pub struct TSTP_CMB14_SPEC; +impl crate::RegisterSpec for TSTP_CMB14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb14::R](R) reader structure"] +impl crate::Readable for TSTP_CMB14_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb14::W](W) writer structure"] +impl crate::Writable for TSTP_CMB14_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB14 to value 0"] +impl crate::Resettable for TSTP_CMB14_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb2.rs b/src/can0/tstp_cmb2.rs new file mode 100644 index 0000000..c561231 --- /dev/null +++ b/src/can0/tstp_cmb2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb2](index.html) module"] +pub struct TSTP_CMB2_SPEC; +impl crate::RegisterSpec for TSTP_CMB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb2::R](R) reader structure"] +impl crate::Readable for TSTP_CMB2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb2::W](W) writer structure"] +impl crate::Writable for TSTP_CMB2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB2 to value 0"] +impl crate::Resettable for TSTP_CMB2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb3.rs b/src/can0/tstp_cmb3.rs new file mode 100644 index 0000000..b2c9b18 --- /dev/null +++ b/src/can0/tstp_cmb3.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb3](index.html) module"] +pub struct TSTP_CMB3_SPEC; +impl crate::RegisterSpec for TSTP_CMB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb3::R](R) reader structure"] +impl crate::Readable for TSTP_CMB3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb3::W](W) writer structure"] +impl crate::Writable for TSTP_CMB3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB3 to value 0"] +impl crate::Resettable for TSTP_CMB3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb4.rs b/src/can0/tstp_cmb4.rs new file mode 100644 index 0000000..2e236d8 --- /dev/null +++ b/src/can0/tstp_cmb4.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb4](index.html) module"] +pub struct TSTP_CMB4_SPEC; +impl crate::RegisterSpec for TSTP_CMB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb4::R](R) reader structure"] +impl crate::Readable for TSTP_CMB4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb4::W](W) writer structure"] +impl crate::Writable for TSTP_CMB4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB4 to value 0"] +impl crate::Resettable for TSTP_CMB4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb5.rs b/src/can0/tstp_cmb5.rs new file mode 100644 index 0000000..2e9d399 --- /dev/null +++ b/src/can0/tstp_cmb5.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb5](index.html) module"] +pub struct TSTP_CMB5_SPEC; +impl crate::RegisterSpec for TSTP_CMB5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb5::R](R) reader structure"] +impl crate::Readable for TSTP_CMB5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb5::W](W) writer structure"] +impl crate::Writable for TSTP_CMB5_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB5 to value 0"] +impl crate::Resettable for TSTP_CMB5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb6.rs b/src/can0/tstp_cmb6.rs new file mode 100644 index 0000000..edc03d7 --- /dev/null +++ b/src/can0/tstp_cmb6.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb6](index.html) module"] +pub struct TSTP_CMB6_SPEC; +impl crate::RegisterSpec for TSTP_CMB6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb6::R](R) reader structure"] +impl crate::Readable for TSTP_CMB6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb6::W](W) writer structure"] +impl crate::Writable for TSTP_CMB6_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB6 to value 0"] +impl crate::Resettable for TSTP_CMB6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb7.rs b/src/can0/tstp_cmb7.rs new file mode 100644 index 0000000..f39dbbc --- /dev/null +++ b/src/can0/tstp_cmb7.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb7](index.html) module"] +pub struct TSTP_CMB7_SPEC; +impl crate::RegisterSpec for TSTP_CMB7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb7::R](R) reader structure"] +impl crate::Readable for TSTP_CMB7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb7::W](W) writer structure"] +impl crate::Writable for TSTP_CMB7_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB7 to value 0"] +impl crate::Resettable for TSTP_CMB7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb8.rs b/src/can0/tstp_cmb8.rs new file mode 100644 index 0000000..bc59625 --- /dev/null +++ b/src/can0/tstp_cmb8.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB8` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB8` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb8](index.html) module"] +pub struct TSTP_CMB8_SPEC; +impl crate::RegisterSpec for TSTP_CMB8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb8::R](R) reader structure"] +impl crate::Readable for TSTP_CMB8_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb8::W](W) writer structure"] +impl crate::Writable for TSTP_CMB8_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB8 to value 0"] +impl crate::Resettable for TSTP_CMB8_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_cmb9.rs b/src/can0/tstp_cmb9.rs new file mode 100644 index 0000000..0aec1eb --- /dev/null +++ b/src/can0/tstp_cmb9.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_CMB9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_CMB9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_cmb9](index.html) module"] +pub struct TSTP_CMB9_SPEC; +impl crate::RegisterSpec for TSTP_CMB9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_cmb9::R](R) reader structure"] +impl crate::Readable for TSTP_CMB9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_cmb9::W](W) writer structure"] +impl crate::Writable for TSTP_CMB9_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_CMB9 to value 0"] +impl crate::Resettable for TSTP_CMB9_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/can0/tstp_hcmb.rs b/src/can0/tstp_hcmb.rs new file mode 100644 index 0000000..72fd5e4 --- /dev/null +++ b/src/can0/tstp_hcmb.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TSTP_HCMB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TSTP_HCMB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub struct TIMESTAMP_R(crate::FieldReader); +impl TIMESTAMP_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMESTAMP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMESTAMP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub struct TIMESTAMP_W<'a> { + w: &'a mut W, +} +impl<'a> TIMESTAMP_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TIMESTAMP_R { + TIMESTAMP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TIMESTAMP_W { + TIMESTAMP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CAN Frame Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tstp_hcmb](index.html) module"] +pub struct TSTP_HCMB_SPEC; +impl crate::RegisterSpec for TSTP_HCMB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tstp_hcmb::R](R) reader structure"] +impl crate::Readable for TSTP_HCMB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tstp_hcmb::W](W) writer structure"] +impl crate::Writable for TSTP_HCMB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TSTP_HCMB to value 0"] +impl crate::Resettable for TSTP_HCMB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/clkgen.rs b/src/clkgen.rs new file mode 100644 index 0000000..c4031a1 --- /dev/null +++ b/src/clkgen.rs @@ -0,0 +1,22 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Clock Generation Module Control Register 0"] + pub ctrl0: crate::Reg, + #[doc = "0x04 - Clock Generation Module Status Register"] + pub stat: crate::Reg, + #[doc = "0x08 - Clock Generation Module Control Register 1"] + pub ctrl1: crate::Reg, +} +#[doc = "CTRL0 register accessor: an alias for `Reg`"] +pub type CTRL0 = crate::Reg; +#[doc = "Clock Generation Module Control Register 0"] +pub mod ctrl0; +#[doc = "STAT register accessor: an alias for `Reg`"] +pub type STAT = crate::Reg; +#[doc = "Clock Generation Module Status Register"] +pub mod stat; +#[doc = "CTRL1 register accessor: an alias for `Reg`"] +pub type CTRL1 = crate::Reg; +#[doc = "Clock Generation Module Control Register 1"] +pub mod ctrl1; diff --git a/src/clkgen/ctrl0.rs b/src/clkgen/ctrl0.rs new file mode 100644 index 0000000..97e5dc9 --- /dev/null +++ b/src/clkgen/ctrl0.rs @@ -0,0 +1,607 @@ +#[doc = "Register `CTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYS_CLK_LOST_DET_EN` reader - Enable the circuit that detects loss of SYS_CLK"] +pub struct SYS_CLK_LOST_DET_EN_R(crate::FieldReader); +impl SYS_CLK_LOST_DET_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYS_CLK_LOST_DET_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYS_CLK_LOST_DET_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYS_CLK_LOST_DET_EN` writer - Enable the circuit that detects loss of SYS_CLK"] +pub struct SYS_CLK_LOST_DET_EN_W<'a> { + w: &'a mut W, +} +impl<'a> SYS_CLK_LOST_DET_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +#[doc = "Field `PLL_RESET` reader - Writing this bit to 1 puts the PLL into reset"] +pub struct PLL_RESET_R(crate::FieldReader); +impl PLL_RESET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLL_RESET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_RESET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_RESET` writer - Writing this bit to 1 puts the PLL into reset"] +pub struct PLL_RESET_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `CLK_DIV_SEL` reader - Selects the PLL out divider to divide by 1/2/4/8"] +pub struct CLK_DIV_SEL_R(crate::FieldReader); +impl CLK_DIV_SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CLK_DIV_SEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLK_DIV_SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLK_DIV_SEL` writer - Selects the PLL out divider to divide by 1/2/4/8"] +pub struct CLK_DIV_SEL_W<'a> { + w: &'a mut W, +} +impl<'a> CLK_DIV_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `PLL_CLKR` reader - PLL Symbol; selects the values 1-16 for the reference divider"] +pub struct PLL_CLKR_R(crate::FieldReader); +impl PLL_CLKR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PLL_CLKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_CLKR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_CLKR` writer - PLL Symbol; selects the values 1-16 for the reference divider"] +pub struct PLL_CLKR_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_CLKR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `PLL_CLKF` reader - PLL Symbol; selects the values 1-64 for the multiplication factor"] +pub struct PLL_CLKF_R(crate::FieldReader); +impl PLL_CLKF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PLL_CLKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_CLKF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_CLKF` writer - PLL Symbol; selects the values 1-64 for the multiplication factor"] +pub struct PLL_CLKF_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_CLKF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 18)) | ((value as u32 & 0x3f) << 18); + self.w + } +} +#[doc = "Field `PLL_CLKOD` reader - PLL Symbol; selects the values 1-16 for the post VCO divider"] +pub struct PLL_CLKOD_R(crate::FieldReader); +impl PLL_CLKOD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PLL_CLKOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_CLKOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_CLKOD` writer - PLL Symbol; selects the values 1-16 for the post VCO divider"] +pub struct PLL_CLKOD_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_CLKOD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 14)) | ((value as u32 & 0x0f) << 14); + self.w + } +} +#[doc = "Field `PLL_BWADJ` reader - PLL Symbol; selects the values 1-64 for the bandwidth divider"] +pub struct PLL_BWADJ_R(crate::FieldReader); +impl PLL_BWADJ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PLL_BWADJ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_BWADJ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_BWADJ` writer - PLL Symbol; selects the values 1-64 for the bandwidth divider"] +pub struct PLL_BWADJ_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_BWADJ_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Field `PLL_TEST` reader - PLL Symbol; Reference-to-counters-to-output bypass when high"] +pub struct PLL_TEST_R(crate::FieldReader); +impl PLL_TEST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLL_TEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_TEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_TEST` writer - PLL Symbol; Reference-to-counters-to-output bypass when high"] +pub struct PLL_TEST_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_TEST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PLL_BYPASS` reader - PLL Symbol; reference-to-output bypass when high"] +pub struct PLL_BYPASS_R(crate::FieldReader); +impl PLL_BYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLL_BYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_BYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_BYPASS` writer - PLL Symbol; reference-to-output bypass when high"] +pub struct PLL_BYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PLL_PWDN` reader - PLL Symbol; power down when high"] +pub struct PLL_PWDN_R(crate::FieldReader); +impl PLL_PWDN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLL_PWDN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_PWDN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_PWDN` writer - PLL Symbol; power down when high"] +pub struct PLL_PWDN_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_PWDN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PLL_INTFB` reader - PLL Symbol; select internal feedback path when high rather than FCLK"] +pub struct PLL_INTFB_R(crate::FieldReader); +impl PLL_INTFB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLL_INTFB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_INTFB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_INTFB` writer - PLL Symbol; select internal feedback path when high rather than FCLK"] +pub struct PLL_INTFB_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_INTFB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CLKSEL_SYS` reader - Input clock select to PLL"] +pub struct CLKSEL_SYS_R(crate::FieldReader); +impl CLKSEL_SYS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CLKSEL_SYS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKSEL_SYS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKSEL_SYS` writer - Input clock select to PLL"] +pub struct CLKSEL_SYS_W<'a> { + w: &'a mut W, +} +impl<'a> CLKSEL_SYS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u32 & 0x03) << 2); + self.w + } +} +#[doc = "Field `REF_CLK_SEL` reader - PLL Reference Clock Select"] +pub struct REF_CLK_SEL_R(crate::FieldReader); +impl REF_CLK_SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REF_CLK_SEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REF_CLK_SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REF_CLK_SEL` writer - PLL Reference Clock Select"] +pub struct REF_CLK_SEL_W<'a> { + w: &'a mut W, +} +impl<'a> REF_CLK_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +impl R { + #[doc = "Bit 31 - Enable the circuit that detects loss of SYS_CLK"] + #[inline(always)] + pub fn sys_clk_lost_det_en(&self) -> SYS_CLK_LOST_DET_EN_R { + SYS_CLK_LOST_DET_EN_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bit 30 - Writing this bit to 1 puts the PLL into reset"] + #[inline(always)] + pub fn pll_reset(&self) -> PLL_RESET_R { + PLL_RESET_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Selects the PLL out divider to divide by 1/2/4/8"] + #[inline(always)] + pub fn clk_div_sel(&self) -> CLK_DIV_SEL_R { + CLK_DIV_SEL_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bits 24:27 - PLL Symbol; selects the values 1-16 for the reference divider"] + #[inline(always)] + pub fn pll_clkr(&self) -> PLL_CLKR_R { + PLL_CLKR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 18:23 - PLL Symbol; selects the values 1-64 for the multiplication factor"] + #[inline(always)] + pub fn pll_clkf(&self) -> PLL_CLKF_R { + PLL_CLKF_R::new(((self.bits >> 18) & 0x3f) as u8) + } + #[doc = "Bits 14:17 - PLL Symbol; selects the values 1-16 for the post VCO divider"] + #[inline(always)] + pub fn pll_clkod(&self) -> PLL_CLKOD_R { + PLL_CLKOD_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 8:13 - PLL Symbol; selects the values 1-64 for the bandwidth divider"] + #[inline(always)] + pub fn pll_bwadj(&self) -> PLL_BWADJ_R { + PLL_BWADJ_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bit 7 - PLL Symbol; Reference-to-counters-to-output bypass when high"] + #[inline(always)] + pub fn pll_test(&self) -> PLL_TEST_R { + PLL_TEST_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - PLL Symbol; reference-to-output bypass when high"] + #[inline(always)] + pub fn pll_bypass(&self) -> PLL_BYPASS_R { + PLL_BYPASS_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - PLL Symbol; power down when high"] + #[inline(always)] + pub fn pll_pwdn(&self) -> PLL_PWDN_R { + PLL_PWDN_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - PLL Symbol; select internal feedback path when high rather than FCLK"] + #[inline(always)] + pub fn pll_intfb(&self) -> PLL_INTFB_R { + PLL_INTFB_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 2:3 - Input clock select to PLL"] + #[inline(always)] + pub fn clksel_sys(&self) -> CLKSEL_SYS_R { + CLKSEL_SYS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 0:1 - PLL Reference Clock Select"] + #[inline(always)] + pub fn ref_clk_sel(&self) -> REF_CLK_SEL_R { + REF_CLK_SEL_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 31 - Enable the circuit that detects loss of SYS_CLK"] + #[inline(always)] + pub fn sys_clk_lost_det_en(&mut self) -> SYS_CLK_LOST_DET_EN_W { + SYS_CLK_LOST_DET_EN_W { w: self } + } + #[doc = "Bit 30 - Writing this bit to 1 puts the PLL into reset"] + #[inline(always)] + pub fn pll_reset(&mut self) -> PLL_RESET_W { + PLL_RESET_W { w: self } + } + #[doc = "Bits 28:29 - Selects the PLL out divider to divide by 1/2/4/8"] + #[inline(always)] + pub fn clk_div_sel(&mut self) -> CLK_DIV_SEL_W { + CLK_DIV_SEL_W { w: self } + } + #[doc = "Bits 24:27 - PLL Symbol; selects the values 1-16 for the reference divider"] + #[inline(always)] + pub fn pll_clkr(&mut self) -> PLL_CLKR_W { + PLL_CLKR_W { w: self } + } + #[doc = "Bits 18:23 - PLL Symbol; selects the values 1-64 for the multiplication factor"] + #[inline(always)] + pub fn pll_clkf(&mut self) -> PLL_CLKF_W { + PLL_CLKF_W { w: self } + } + #[doc = "Bits 14:17 - PLL Symbol; selects the values 1-16 for the post VCO divider"] + #[inline(always)] + pub fn pll_clkod(&mut self) -> PLL_CLKOD_W { + PLL_CLKOD_W { w: self } + } + #[doc = "Bits 8:13 - PLL Symbol; selects the values 1-64 for the bandwidth divider"] + #[inline(always)] + pub fn pll_bwadj(&mut self) -> PLL_BWADJ_W { + PLL_BWADJ_W { w: self } + } + #[doc = "Bit 7 - PLL Symbol; Reference-to-counters-to-output bypass when high"] + #[inline(always)] + pub fn pll_test(&mut self) -> PLL_TEST_W { + PLL_TEST_W { w: self } + } + #[doc = "Bit 6 - PLL Symbol; reference-to-output bypass when high"] + #[inline(always)] + pub fn pll_bypass(&mut self) -> PLL_BYPASS_W { + PLL_BYPASS_W { w: self } + } + #[doc = "Bit 5 - PLL Symbol; power down when high"] + #[inline(always)] + pub fn pll_pwdn(&mut self) -> PLL_PWDN_W { + PLL_PWDN_W { w: self } + } + #[doc = "Bit 4 - PLL Symbol; select internal feedback path when high rather than FCLK"] + #[inline(always)] + pub fn pll_intfb(&mut self) -> PLL_INTFB_W { + PLL_INTFB_W { w: self } + } + #[doc = "Bits 2:3 - Input clock select to PLL"] + #[inline(always)] + pub fn clksel_sys(&mut self) -> CLKSEL_SYS_W { + CLKSEL_SYS_W { w: self } + } + #[doc = "Bits 0:1 - PLL Reference Clock Select"] + #[inline(always)] + pub fn ref_clk_sel(&mut self) -> REF_CLK_SEL_W { + REF_CLK_SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Generation Module Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl0](index.html) module"] +pub struct CTRL0_SPEC; +impl crate::RegisterSpec for CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl0::R](R) reader structure"] +impl crate::Readable for CTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl0::W](W) writer structure"] +impl crate::Writable for CTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL0 to value 0x30"] +impl crate::Resettable for CTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x30 + } +} diff --git a/src/clkgen/ctrl1.rs b/src/clkgen/ctrl1.rs new file mode 100644 index 0000000..02eb12d --- /dev/null +++ b/src/clkgen/ctrl1.rs @@ -0,0 +1,338 @@ +#[doc = "Register `CTRL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADC_CLK_DIV_SEL` reader - Clock divider select for ADC"] +pub struct ADC_CLK_DIV_SEL_R(crate::FieldReader); +impl ADC_CLK_DIV_SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADC_CLK_DIV_SEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_CLK_DIV_SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC_CLK_DIV_SEL` writer - Clock divider select for ADC"] +pub struct ADC_CLK_DIV_SEL_W<'a> { + w: &'a mut W, +} +impl<'a> ADC_CLK_DIV_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `XTAL_N_EN` reader - Enables XTAL_N output"] +pub struct XTAL_N_EN_R(crate::FieldReader); +impl XTAL_N_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTAL_N_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTAL_N_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTAL_N_EN` writer - Enables XTAL_N output"] +pub struct XTAL_N_EN_W<'a> { + w: &'a mut W, +} +impl<'a> XTAL_N_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `XTAL_EN` reader - Enables the crystal oscillator"] +pub struct XTAL_EN_R(crate::FieldReader); +impl XTAL_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + XTAL_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTAL_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTAL_EN` writer - Enables the crystal oscillator"] +pub struct XTAL_EN_W<'a> { + w: &'a mut W, +} +impl<'a> XTAL_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `PLL_LOST_LOCK_DET_EN` reader - Enables the PLL lock lost detection circuit"] +pub struct PLL_LOST_LOCK_DET_EN_R(crate::FieldReader); +impl PLL_LOST_LOCK_DET_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLL_LOST_LOCK_DET_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_LOST_LOCK_DET_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_LOST_LOCK_DET_EN` writer - Enables the PLL lock lost detection circuit"] +pub struct PLL_LOST_LOCK_DET_EN_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_LOST_LOCK_DET_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PLL_LCK_DET_REARM` reader - Resets/Rearms the PLL lock detect circuit"] +pub struct PLL_LCK_DET_REARM_R(crate::FieldReader); +impl PLL_LCK_DET_REARM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLL_LCK_DET_REARM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLL_LCK_DET_REARM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLL_LCK_DET_REARM` writer - Resets/Rearms the PLL lock detect circuit"] +pub struct PLL_LCK_DET_REARM_W<'a> { + w: &'a mut W, +} +impl<'a> PLL_LCK_DET_REARM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYS_CLK_LOST_DET_REARM` reader - Resets/Rearms the SYS_CLK lost detection feature"] +pub struct SYS_CLK_LOST_DET_REARM_R(crate::FieldReader); +impl SYS_CLK_LOST_DET_REARM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYS_CLK_LOST_DET_REARM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYS_CLK_LOST_DET_REARM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYS_CLK_LOST_DET_REARM` writer - Resets/Rearms the SYS_CLK lost detection feature"] +pub struct SYS_CLK_LOST_DET_REARM_W<'a> { + w: &'a mut W, +} +impl<'a> SYS_CLK_LOST_DET_REARM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bits 5:6 - Clock divider select for ADC"] + #[inline(always)] + pub fn adc_clk_div_sel(&self) -> ADC_CLK_DIV_SEL_R { + ADC_CLK_DIV_SEL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 4 - Enables XTAL_N output"] + #[inline(always)] + pub fn xtal_n_en(&self) -> XTAL_N_EN_R { + XTAL_N_EN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Enables the crystal oscillator"] + #[inline(always)] + pub fn xtal_en(&self) -> XTAL_EN_R { + XTAL_EN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Enables the PLL lock lost detection circuit"] + #[inline(always)] + pub fn pll_lost_lock_det_en(&self) -> PLL_LOST_LOCK_DET_EN_R { + PLL_LOST_LOCK_DET_EN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Resets/Rearms the PLL lock detect circuit"] + #[inline(always)] + pub fn pll_lck_det_rearm(&self) -> PLL_LCK_DET_REARM_R { + PLL_LCK_DET_REARM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Resets/Rearms the SYS_CLK lost detection feature"] + #[inline(always)] + pub fn sys_clk_lost_det_rearm(&self) -> SYS_CLK_LOST_DET_REARM_R { + SYS_CLK_LOST_DET_REARM_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 5:6 - Clock divider select for ADC"] + #[inline(always)] + pub fn adc_clk_div_sel(&mut self) -> ADC_CLK_DIV_SEL_W { + ADC_CLK_DIV_SEL_W { w: self } + } + #[doc = "Bit 4 - Enables XTAL_N output"] + #[inline(always)] + pub fn xtal_n_en(&mut self) -> XTAL_N_EN_W { + XTAL_N_EN_W { w: self } + } + #[doc = "Bit 3 - Enables the crystal oscillator"] + #[inline(always)] + pub fn xtal_en(&mut self) -> XTAL_EN_W { + XTAL_EN_W { w: self } + } + #[doc = "Bit 2 - Enables the PLL lock lost detection circuit"] + #[inline(always)] + pub fn pll_lost_lock_det_en(&mut self) -> PLL_LOST_LOCK_DET_EN_W { + PLL_LOST_LOCK_DET_EN_W { w: self } + } + #[doc = "Bit 1 - Resets/Rearms the PLL lock detect circuit"] + #[inline(always)] + pub fn pll_lck_det_rearm(&mut self) -> PLL_LCK_DET_REARM_W { + PLL_LCK_DET_REARM_W { w: self } + } + #[doc = "Bit 0 - Resets/Rearms the SYS_CLK lost detection feature"] + #[inline(always)] + pub fn sys_clk_lost_det_rearm(&mut self) -> SYS_CLK_LOST_DET_REARM_W { + SYS_CLK_LOST_DET_REARM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Generation Module Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl1](index.html) module"] +pub struct CTRL1_SPEC; +impl crate::RegisterSpec for CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl1::R](R) reader structure"] +impl crate::Readable for CTRL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl1::W](W) writer structure"] +impl crate::Writable for CTRL1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for CTRL1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/clkgen/stat.rs b/src/clkgen/stat.rs new file mode 100644 index 0000000..0e083f5 --- /dev/null +++ b/src/clkgen/stat.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYSCLKLOST` reader - Set when SYS_CLK has dropped to less than 1MHz"] +pub struct SYSCLKLOST_R(crate::FieldReader); +impl SYSCLKLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSCLKLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSCLKLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOCKLOST` reader - LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles"] +pub struct LOCKLOST_R(crate::FieldReader); +impl LOCKLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOCKLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCKLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFSLIP` reader - Reference cycle slip output (CLKOUT frequency high)"] +pub struct RFSLIP_R(crate::FieldReader); +impl RFSLIP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RFSLIP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFSLIP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FBSLIP` reader - Feedback cycle slip output (CLKOUT frequency low)"] +pub struct FBSLIP_R(crate::FieldReader); +impl FBSLIP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FBSLIP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FBSLIP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Set when SYS_CLK has dropped to less than 1MHz"] + #[inline(always)] + pub fn sysclklost(&self) -> SYSCLKLOST_R { + SYSCLKLOST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles"] + #[inline(always)] + pub fn locklost(&self) -> LOCKLOST_R { + LOCKLOST_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Reference cycle slip output (CLKOUT frequency high)"] + #[inline(always)] + pub fn rfslip(&self) -> RFSLIP_R { + RFSLIP_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Feedback cycle slip output (CLKOUT frequency low)"] + #[inline(always)] + pub fn fbslip(&self) -> FBSLIP_R { + FBSLIP_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Clock Generation Module Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat](index.html) module"] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [stat::R](R) reader structure"] +impl crate::Readable for STAT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for STAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dac0.rs b/src/dac0.rs new file mode 100644 index 0000000..44be2ab --- /dev/null +++ b/src/dac0.rs @@ -0,0 +1,71 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control Register 0"] + pub ctrl0: crate::Reg, + #[doc = "0x04 - Control Register 1"] + pub ctrl1: crate::Reg, + #[doc = "0x08 - FIFO data"] + pub fifo_data: crate::Reg, + #[doc = "0x0c - Status"] + pub status: crate::Reg, + #[doc = "0x10 - Interrupt Enable"] + pub irq_enb: crate::Reg, + #[doc = "0x14 - Raw Interrupt Status"] + pub irq_raw: crate::Reg, + #[doc = "0x18 - Enabled Interrupt Status"] + pub irq_end: crate::Reg, + #[doc = "0x1c - Clear Interrupt"] + pub irq_clr: crate::Reg, + #[doc = "0x20 - Receive FIFO Interrupt Trigger Value"] + pub txfifoirqtrg: crate::Reg, + #[doc = "0x24 - FIFO Clear"] + pub fifo_clr: crate::Reg, + _reserved10: [u8; 0x07d4], + #[doc = "0x7fc - Peripheral ID Register"] + pub perid: crate::Reg, +} +#[doc = "CTRL0 register accessor: an alias for `Reg`"] +pub type CTRL0 = crate::Reg; +#[doc = "Control Register 0"] +pub mod ctrl0; +#[doc = "CTRL1 register accessor: an alias for `Reg`"] +pub type CTRL1 = crate::Reg; +#[doc = "Control Register 1"] +pub mod ctrl1; +#[doc = "FIFO_DATA register accessor: an alias for `Reg`"] +pub type FIFO_DATA = crate::Reg; +#[doc = "FIFO data"] +pub mod fifo_data; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "IRQ_ENB register accessor: an alias for `Reg`"] +pub type IRQ_ENB = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod irq_enb; +#[doc = "IRQ_RAW register accessor: an alias for `Reg`"] +pub type IRQ_RAW = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END register accessor: an alias for `Reg`"] +pub type IRQ_END = crate::Reg; +#[doc = "Enabled Interrupt Status"] +pub mod irq_end; +#[doc = "IRQ_CLR register accessor: an alias for `Reg`"] +pub type IRQ_CLR = crate::Reg; +#[doc = "Clear Interrupt"] +pub mod irq_clr; +#[doc = "TXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type TXFIFOIRQTRG = crate::Reg; +#[doc = "Receive FIFO Interrupt Trigger Value"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR register accessor: an alias for `Reg`"] +pub type FIFO_CLR = crate::Reg; +#[doc = "FIFO Clear"] +pub mod fifo_clr; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/dac0/ctrl0.rs b/src/dac0/ctrl0.rs new file mode 100644 index 0000000..e3e6b1f --- /dev/null +++ b/src/dac0/ctrl0.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAN_TRIG_EN` reader - Enables manual trigger"] +pub struct MAN_TRIG_EN_R(crate::FieldReader); +impl MAN_TRIG_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MAN_TRIG_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MAN_TRIG_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MAN_TRIG_EN` writer - Enables manual trigger"] +pub struct MAN_TRIG_EN_W<'a> { + w: &'a mut W, +} +impl<'a> MAN_TRIG_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `EXT_TRIG_EN` reader - Enables external trigger"] +pub struct EXT_TRIG_EN_R(crate::FieldReader); +impl EXT_TRIG_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXT_TRIG_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXT_TRIG_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXT_TRIG_EN` writer - Enables external trigger"] +pub struct EXT_TRIG_EN_W<'a> { + w: &'a mut W, +} +impl<'a> EXT_TRIG_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 11 - Enables manual trigger"] + #[inline(always)] + pub fn man_trig_en(&self) -> MAN_TRIG_EN_R { + MAN_TRIG_EN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - Enables external trigger"] + #[inline(always)] + pub fn ext_trig_en(&self) -> EXT_TRIG_EN_R { + EXT_TRIG_EN_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 11 - Enables manual trigger"] + #[inline(always)] + pub fn man_trig_en(&mut self) -> MAN_TRIG_EN_W { + MAN_TRIG_EN_W { w: self } + } + #[doc = "Bit 10 - Enables external trigger"] + #[inline(always)] + pub fn ext_trig_en(&mut self) -> EXT_TRIG_EN_W { + EXT_TRIG_EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl0](index.html) module"] +pub struct CTRL0_SPEC; +impl crate::RegisterSpec for CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl0::R](R) reader structure"] +impl crate::Readable for CTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl0::W](W) writer structure"] +impl crate::Writable for CTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL0 to value 0"] +impl crate::Resettable for CTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dac0/ctrl1.rs b/src/dac0/ctrl1.rs new file mode 100644 index 0000000..8851082 --- /dev/null +++ b/src/dac0/ctrl1.rs @@ -0,0 +1,150 @@ +#[doc = "Register `CTRL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DAC_EN` reader - Enables the DAC analog block"] +pub struct DAC_EN_R(crate::FieldReader); +impl DAC_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_EN` writer - Enables the DAC analog block"] +pub struct DAC_EN_W<'a> { + w: &'a mut W, +} +impl<'a> DAC_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DAC_SETTLING` reader - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] +pub struct DAC_SETTLING_R(crate::FieldReader); +impl DAC_SETTLING_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAC_SETTLING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC_SETTLING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_SETTLING` writer - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] +pub struct DAC_SETTLING_W<'a> { + w: &'a mut W, +} +impl<'a> DAC_SETTLING_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u32 & 0x07) << 5); + self.w + } +} +impl R { + #[doc = "Bit 8 - Enables the DAC analog block"] + #[inline(always)] + pub fn dac_en(&self) -> DAC_EN_R { + DAC_EN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] + #[inline(always)] + pub fn dac_settling(&self) -> DAC_SETTLING_R { + DAC_SETTLING_R::new(((self.bits >> 5) & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 8 - Enables the DAC analog block"] + #[inline(always)] + pub fn dac_en(&mut self) -> DAC_EN_W { + DAC_EN_W { w: self } + } + #[doc = "Bits 5:7 - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] + #[inline(always)] + pub fn dac_settling(&mut self) -> DAC_SETTLING_W { + DAC_SETTLING_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl1](index.html) module"] +pub struct CTRL1_SPEC; +impl crate::RegisterSpec for CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl1::R](R) reader structure"] +impl crate::Readable for CTRL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl1::W](W) writer structure"] +impl crate::Writable for CTRL1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for CTRL1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dac0/fifo_clr.rs b/src/dac0/fifo_clr.rs new file mode 100644 index 0000000..64c74cf --- /dev/null +++ b/src/dac0/fifo_clr.rs @@ -0,0 +1,72 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FIFO_CLR` writer - Clears the DAC FIFO. Always reads 0"] +pub struct FIFO_CLR_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_CLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 0 - Clears the DAC FIFO. Always reads 0"] + #[inline(always)] + pub fn fifo_clr(&mut self) -> FIFO_CLR_W { + FIFO_CLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIFO Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_clr](index.html) module"] +pub struct FIFO_CLR_SPEC; +impl crate::RegisterSpec for FIFO_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [fifo_clr::W](W) writer structure"] +impl crate::Writable for FIFO_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FIFO_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dac0/fifo_data.rs b/src/dac0/fifo_data.rs new file mode 100644 index 0000000..49a5e2f --- /dev/null +++ b/src/dac0/fifo_data.rs @@ -0,0 +1,81 @@ +#[doc = "Register `FIFO_DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FIFO_DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` writer - Data for FIFO write"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +impl W { + #[doc = "Bits 0:11 - Data for FIFO write"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "FIFO data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_data](index.html) module"] +pub struct FIFO_DATA_SPEC; +impl crate::RegisterSpec for FIFO_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fifo_data::R](R) reader structure"] +impl crate::Readable for FIFO_DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fifo_data::W](W) writer structure"] +impl crate::Writable for FIFO_DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FIFO_DATA to value 0"] +impl crate::Resettable for FIFO_DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dac0/irq_clr.rs b/src/dac0/irq_clr.rs new file mode 100644 index 0000000..2f91f97 --- /dev/null +++ b/src/dac0/irq_clr.rs @@ -0,0 +1,153 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRIG_ERROR` writer - Clears the trigger error interrupt status. Always reads 0"] +pub struct TRIG_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> TRIG_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DAC_DONE` writer - Clears the DAC done interrupt status. Always reads 0"] +pub struct DAC_DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DAC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FIFO_UFLOW` writer - Clears the FIFO underflow interrupt status. Always reads 0"] +pub struct FIFO_UFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_UFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FIFO_OFLOW` writer - Clears the FIFO overflow interrupt status. Always reads 0"] +pub struct FIFO_OFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_OFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"] + #[inline(always)] + pub fn trig_error(&mut self) -> TRIG_ERROR_W { + TRIG_ERROR_W { w: self } + } + #[doc = "Bit 2 - Clears the DAC done interrupt status. Always reads 0"] + #[inline(always)] + pub fn dac_done(&mut self) -> DAC_DONE_W { + DAC_DONE_W { w: self } + } + #[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"] + #[inline(always)] + pub fn fifo_uflow(&mut self) -> FIFO_UFLOW_W { + FIFO_UFLOW_W { w: self } + } + #[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"] + #[inline(always)] + pub fn fifo_oflow(&mut self) -> FIFO_OFLOW_W { + FIFO_OFLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear Interrupt\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"] +pub struct IRQ_CLR_SPEC; +impl crate::RegisterSpec for IRQ_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"] +impl crate::Writable for IRQ_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IRQ_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dac0/irq_enb.rs b/src/dac0/irq_enb.rs new file mode 100644 index 0000000..f40f538 --- /dev/null +++ b/src/dac0/irq_enb.rs @@ -0,0 +1,395 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_ENB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] +pub struct FIFO_DEPTH_TRIG_R(crate::FieldReader); +impl FIFO_DEPTH_TRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_DEPTH_TRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_DEPTH_TRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] +pub struct FIFO_DEPTH_TRIG_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_DEPTH_TRIG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"] +pub struct TRIG_ERROR_R(crate::FieldReader); +impl TRIG_ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRIG_ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIG_ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"] +pub struct TRIG_ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> TRIG_ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DAC_DONE` reader - Enables the interrupt for a DAC data acquisition completion"] +pub struct DAC_DONE_R(crate::FieldReader); +impl DAC_DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC_DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC_DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_DONE` writer - Enables the interrupt for a DAC data acquisition completion"] +pub struct DAC_DONE_W<'a> { + w: &'a mut W, +} +impl<'a> DAC_DONE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"] +pub struct FIFO_UFLOW_R(crate::FieldReader); +impl FIFO_UFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_UFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_UFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"] +pub struct FIFO_UFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_UFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"] +pub struct FIFO_OFLOW_R(crate::FieldReader); +impl FIFO_OFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_OFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_OFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"] +pub struct FIFO_OFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_OFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"] +pub struct FIFO_FULL_R(crate::FieldReader); +impl FIFO_FULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_FULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_FULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"] +pub struct FIFO_FULL_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_FULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"] +pub struct FIFO_EMPTY_R(crate::FieldReader); +impl FIFO_EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"] +pub struct FIFO_EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> FIFO_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FIFO_DEPTH_TRIG_R { + FIFO_DEPTH_TRIG_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&self) -> TRIG_ERROR_R { + TRIG_ERROR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Enables the interrupt for a DAC data acquisition completion"] + #[inline(always)] + pub fn dac_done(&self) -> DAC_DONE_R { + DAC_DONE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FIFO_UFLOW_R { + FIFO_UFLOW_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FIFO_OFLOW_R { + FIFO_OFLOW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&self) -> FIFO_FULL_R { + FIFO_FULL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&mut self) -> FIFO_DEPTH_TRIG_W { + FIFO_DEPTH_TRIG_W { w: self } + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&mut self) -> TRIG_ERROR_W { + TRIG_ERROR_W { w: self } + } + #[doc = "Bit 4 - Enables the interrupt for a DAC data acquisition completion"] + #[inline(always)] + pub fn dac_done(&mut self) -> DAC_DONE_W { + DAC_DONE_W { w: self } + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&mut self) -> FIFO_UFLOW_W { + FIFO_UFLOW_W { w: self } + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&mut self) -> FIFO_OFLOW_W { + FIFO_OFLOW_W { w: self } + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&mut self) -> FIFO_FULL_W { + FIFO_FULL_W { w: self } + } + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&mut self) -> FIFO_EMPTY_W { + FIFO_EMPTY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"] +pub struct IRQ_ENB_SPEC; +impl crate::RegisterSpec for IRQ_ENB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_enb::R](R) reader structure"] +impl crate::Readable for IRQ_ENB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"] +impl crate::Writable for IRQ_ENB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IRQ_ENB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dac0/irq_end.rs b/src/dac0/irq_end.rs new file mode 100644 index 0000000..1fcf31d --- /dev/null +++ b/src/dac0/irq_end.rs @@ -0,0 +1,173 @@ +#[doc = "Register `IRQ_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled"] +pub struct FIFO_DEPTH_TRIG_R(crate::FieldReader); +impl FIFO_DEPTH_TRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_DEPTH_TRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_DEPTH_TRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled"] +pub struct TRIG_ERROR_R(crate::FieldReader); +impl TRIG_ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRIG_ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIG_ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_DONE` reader - Indicates that a DAC conversion is done and the interrupt is enabled"] +pub struct DAC_DONE_R(crate::FieldReader); +impl DAC_DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC_DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC_DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_UFLOW` reader - Indicates a FIFO underflow occurred and the interrupt is enabled"] +pub struct FIFO_UFLOW_R(crate::FieldReader); +impl FIFO_UFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_UFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_UFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred and the interrupt is enabled"] +pub struct FIFO_OFLOW_R(crate::FieldReader); +impl FIFO_OFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_OFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_OFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full and the interrupt is enabled"] +pub struct FIFO_FULL_R(crate::FieldReader); +impl FIFO_FULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_FULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_FULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty and the interrupt is enabled"] +pub struct FIFO_EMPTY_R(crate::FieldReader); +impl FIFO_EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 6 - Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FIFO_DEPTH_TRIG_R { + FIFO_DEPTH_TRIG_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled"] + #[inline(always)] + pub fn trig_error(&self) -> TRIG_ERROR_R { + TRIG_ERROR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Indicates that a DAC conversion is done and the interrupt is enabled"] + #[inline(always)] + pub fn dac_done(&self) -> DAC_DONE_R { + DAC_DONE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Indicates a FIFO underflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FIFO_UFLOW_R { + FIFO_UFLOW_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FIFO_OFLOW_R { + FIFO_OFLOW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_full(&self) -> FIFO_FULL_R { + FIFO_FULL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Indicates the FIFO is empty and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Enabled Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"] +pub struct IRQ_END_SPEC; +impl crate::RegisterSpec for IRQ_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_end::R](R) reader structure"] +impl crate::Readable for IRQ_END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IRQ_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dac0/irq_raw.rs b/src/dac0/irq_raw.rs new file mode 100644 index 0000000..31a0ba2 --- /dev/null +++ b/src/dac0/irq_raw.rs @@ -0,0 +1,173 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the FIFO entry count is less than or equal to the trigger level"] +pub struct FIFO_DEPTH_TRIG_R(crate::FieldReader); +impl FIFO_DEPTH_TRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_DEPTH_TRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_DEPTH_TRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion"] +pub struct TRIG_ERROR_R(crate::FieldReader); +impl TRIG_ERROR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRIG_ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRIG_ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_DONE` reader - Indicates that a DAC conversion is done"] +pub struct DAC_DONE_R(crate::FieldReader); +impl DAC_DONE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC_DONE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC_DONE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_UFLOW` reader - Indicates data was unavailable when a new trigger for DAC update is received"] +pub struct FIFO_UFLOW_R(crate::FieldReader); +impl FIFO_UFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_UFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_UFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] +pub struct FIFO_OFLOW_R(crate::FieldReader); +impl FIFO_OFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_OFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_OFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full"] +pub struct FIFO_FULL_R(crate::FieldReader); +impl FIFO_FULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_FULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_FULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty"] +pub struct FIFO_EMPTY_R(crate::FieldReader); +impl FIFO_EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FIFO_EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 6 - Indicates the FIFO entry count is less than or equal to the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FIFO_DEPTH_TRIG_R { + FIFO_DEPTH_TRIG_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion"] + #[inline(always)] + pub fn trig_error(&self) -> TRIG_ERROR_R { + TRIG_ERROR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Indicates that a DAC conversion is done"] + #[inline(always)] + pub fn dac_done(&self) -> DAC_DONE_R { + DAC_DONE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Indicates data was unavailable when a new trigger for DAC update is received"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FIFO_UFLOW_R { + FIFO_UFLOW_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FIFO_OFLOW_R { + FIFO_OFLOW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full"] + #[inline(always)] + pub fn fifo_full(&self) -> FIFO_FULL_R { + FIFO_FULL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Indicates the FIFO is empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Raw Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"] +pub struct IRQ_RAW_SPEC; +impl crate::RegisterSpec for IRQ_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_raw::R](R) reader structure"] +impl crate::Readable for IRQ_RAW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_RAW to value 0x41"] +impl crate::Resettable for IRQ_RAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x41 + } +} diff --git a/src/dac0/perid.rs b/src/dac0/perid.rs new file mode 100644 index 0000000..cefe79c --- /dev/null +++ b/src/dac0/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0020_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0020_07e9 + } +} diff --git a/src/dac0/status.rs b/src/dac0/status.rs new file mode 100644 index 0000000..f96c544 --- /dev/null +++ b/src/dac0/status.rs @@ -0,0 +1,73 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DAC_BUSY` reader - Indicates a DAC data acquisition is in process"] +pub struct DAC_BUSY_R(crate::FieldReader); +impl DAC_BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC_BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC_BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FIFO_ENTRY_CNT` reader - Indicates the number of entries in the FIFO"] +pub struct FIFO_ENTRY_CNT_R(crate::FieldReader); +impl FIFO_ENTRY_CNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FIFO_ENTRY_CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FIFO_ENTRY_CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 7 - Indicates a DAC data acquisition is in process"] + #[inline(always)] + pub fn dac_busy(&self) -> DAC_BUSY_R { + DAC_BUSY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 0:5 - Indicates the number of entries in the FIFO"] + #[inline(always)] + pub fn fifo_entry_cnt(&self) -> FIFO_ENTRY_CNT_R { + FIFO_ENTRY_CNT_R::new((self.bits & 0x3f) as u8) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dac0/txfifoirqtrg.rs b/src/dac0/txfifoirqtrg.rs new file mode 100644 index 0000000..1d2650c --- /dev/null +++ b/src/dac0/txfifoirqtrg.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEVEL` reader - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Receive FIFO Interrupt Trigger Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfifoirqtrg](index.html) module"] +pub struct TXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for TXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txfifoirqtrg::R](R) reader structure"] +impl crate::Readable for TXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txfifoirqtrg::W](W) writer structure"] +impl crate::Writable for TXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0x10"] +impl crate::Resettable for TXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x10 + } +} diff --git a/src/dma.rs b/src/dma.rs new file mode 100644 index 0000000..28845a5 --- /dev/null +++ b/src/dma.rs @@ -0,0 +1,223 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - DMA Status"] + pub status: crate::Reg, + #[doc = "0x04 - DMA Configuration"] + pub cfg: crate::Reg, + #[doc = "0x08 - Base Pointer for DMA Control Registers"] + pub ctrl_base_ptr: crate::Reg, + #[doc = "0x0c - DMA Channel alternate control data base pointer"] + pub alt_ctrl_base_ptr: crate::Reg, + #[doc = "0x10 - DMA channel wait on request status"] + pub waitonreq_status: crate::Reg, + #[doc = "0x14 - DMA channel software request"] + pub chnl_sw_request: crate::Reg, + #[doc = "0x18 - DMA channel useburst set"] + pub chnl_useburst_set: crate::Reg, + #[doc = "0x1c - DMA channel useburst clear"] + pub chnl_useburst_clr: crate::Reg, + #[doc = "0x20 - DMA channel request mask set"] + pub chnl_req_mask_set: crate::Reg, + #[doc = "0x24 - DMA channel request mask clear"] + pub chnl_req_mask_clr: crate::Reg, + #[doc = "0x28 - DMA channel enable set"] + pub chnl_enable_set: crate::Reg, + #[doc = "0x2c - DMA channel enable clear"] + pub chnl_enable_clr: crate::Reg, + #[doc = "0x30 - DMA channel primary alternate set"] + pub chnl_pri_alt_set: crate::Reg, + #[doc = "0x34 - DMA channel primary alternate clear"] + pub chnl_pri_alt_clr: crate::Reg, + #[doc = "0x38 - DMA channel priority set"] + pub chnl_priority_set: crate::Reg, + #[doc = "0x3c - DMA channel priority clear"] + pub chnl_priority_clr: crate::Reg, + _reserved16: [u8; 0x0c], + #[doc = "0x4c - DMA bus error clear"] + pub err_clr: crate::Reg, + _reserved17: [u8; 0x0db0], + #[doc = "0xe00 - DMA integration configuration"] + pub integration_cfg: crate::Reg, + _reserved18: [u8; 0x04], + #[doc = "0xe08 - DMA stall status"] + pub stall_status: crate::Reg, + _reserved19: [u8; 0x04], + #[doc = "0xe10 - DMA Configuration"] + pub dma_req_status: crate::Reg, + _reserved20: [u8; 0x04], + #[doc = "0xe18 - DMA single request status"] + pub dma_sreq_status: crate::Reg, + _reserved21: [u8; 0x04], + #[doc = "0xe20 - DMA done set"] + pub dma_done_set: crate::Reg, + #[doc = "0xe24 - DMA done clear"] + pub dma_done_clr: crate::Reg, + #[doc = "0xe28 - DMA active set"] + pub dma_active_set: crate::Reg, + #[doc = "0xe2c - DMA active clear"] + pub dma_active_clr: crate::Reg, + _reserved25: [u8; 0x18], + #[doc = "0xe48 - DMA bus error set"] + pub err_set: crate::Reg, + _reserved26: [u8; 0x0184], + #[doc = "0xfd0 - DMA Peripheral ID 4"] + pub periph_id_4: crate::Reg, + _reserved27: [u8; 0x0c], + #[doc = "0xfe0 - DMA Peripheral ID 0"] + pub periph_id_0: crate::Reg, + #[doc = "0xfe4 - DMA Peripheral ID 1"] + pub periph_id_1: crate::Reg, + #[doc = "0xfe8 - DMA Peripheral ID 2"] + pub periph_id_2: crate::Reg, + #[doc = "0xfec - DMA Peripheral ID 3"] + pub periph_id_3: crate::Reg, + #[doc = "0xff0 - DMA PrimeCell ID 0"] + pub primecell_id_0: crate::Reg, + #[doc = "0xff4 - DMA PrimeCell ID 1"] + pub primecell_id_1: crate::Reg, + #[doc = "0xff8 - DMA PrimeCell ID 2"] + pub primecell_id_2: crate::Reg, + #[doc = "0xffc - DMA PrimeCell ID 3"] + pub primecell_id_3: crate::Reg, +} +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "DMA Status"] +pub mod status; +#[doc = "CFG register accessor: an alias for `Reg`"] +pub type CFG = crate::Reg; +#[doc = "DMA Configuration"] +pub mod cfg; +#[doc = "CTRL_BASE_PTR register accessor: an alias for `Reg`"] +pub type CTRL_BASE_PTR = crate::Reg; +#[doc = "Base Pointer for DMA Control Registers"] +pub mod ctrl_base_ptr; +#[doc = "ALT_CTRL_BASE_PTR register accessor: an alias for `Reg`"] +pub type ALT_CTRL_BASE_PTR = crate::Reg; +#[doc = "DMA Channel alternate control data base pointer"] +pub mod alt_ctrl_base_ptr; +#[doc = "WAITONREQ_STATUS register accessor: an alias for `Reg`"] +pub type WAITONREQ_STATUS = crate::Reg; +#[doc = "DMA channel wait on request status"] +pub mod waitonreq_status; +#[doc = "CHNL_SW_REQUEST register accessor: an alias for `Reg`"] +pub type CHNL_SW_REQUEST = crate::Reg; +#[doc = "DMA channel software request"] +pub mod chnl_sw_request; +#[doc = "CHNL_USEBURST_SET register accessor: an alias for `Reg`"] +pub type CHNL_USEBURST_SET = crate::Reg; +#[doc = "DMA channel useburst set"] +pub mod chnl_useburst_set; +#[doc = "CHNL_USEBURST_CLR register accessor: an alias for `Reg`"] +pub type CHNL_USEBURST_CLR = crate::Reg; +#[doc = "DMA channel useburst clear"] +pub mod chnl_useburst_clr; +#[doc = "CHNL_REQ_MASK_SET register accessor: an alias for `Reg`"] +pub type CHNL_REQ_MASK_SET = crate::Reg; +#[doc = "DMA channel request mask set"] +pub mod chnl_req_mask_set; +#[doc = "CHNL_REQ_MASK_CLR register accessor: an alias for `Reg`"] +pub type CHNL_REQ_MASK_CLR = crate::Reg; +#[doc = "DMA channel request mask clear"] +pub mod chnl_req_mask_clr; +#[doc = "CHNL_ENABLE_SET register accessor: an alias for `Reg`"] +pub type CHNL_ENABLE_SET = crate::Reg; +#[doc = "DMA channel enable set"] +pub mod chnl_enable_set; +#[doc = "CHNL_ENABLE_CLR register accessor: an alias for `Reg`"] +pub type CHNL_ENABLE_CLR = crate::Reg; +#[doc = "DMA channel enable clear"] +pub mod chnl_enable_clr; +#[doc = "CHNL_PRI_ALT_SET register accessor: an alias for `Reg`"] +pub type CHNL_PRI_ALT_SET = crate::Reg; +#[doc = "DMA channel primary alternate set"] +pub mod chnl_pri_alt_set; +#[doc = "CHNL_PRI_ALT_CLR register accessor: an alias for `Reg`"] +pub type CHNL_PRI_ALT_CLR = crate::Reg; +#[doc = "DMA channel primary alternate clear"] +pub mod chnl_pri_alt_clr; +#[doc = "CHNL_PRIORITY_SET register accessor: an alias for `Reg`"] +pub type CHNL_PRIORITY_SET = crate::Reg; +#[doc = "DMA channel priority set"] +pub mod chnl_priority_set; +#[doc = "CHNL_PRIORITY_CLR register accessor: an alias for `Reg`"] +pub type CHNL_PRIORITY_CLR = crate::Reg; +#[doc = "DMA channel priority clear"] +pub mod chnl_priority_clr; +#[doc = "ERR_CLR register accessor: an alias for `Reg`"] +pub type ERR_CLR = crate::Reg; +#[doc = "DMA bus error clear"] +pub mod err_clr; +#[doc = "INTEGRATION_CFG register accessor: an alias for `Reg`"] +pub type INTEGRATION_CFG = crate::Reg; +#[doc = "DMA integration configuration"] +pub mod integration_cfg; +#[doc = "STALL_STATUS register accessor: an alias for `Reg`"] +pub type STALL_STATUS = crate::Reg; +#[doc = "DMA stall status"] +pub mod stall_status; +#[doc = "DMA_REQ_STATUS register accessor: an alias for `Reg`"] +pub type DMA_REQ_STATUS = crate::Reg; +#[doc = "DMA Configuration"] +pub mod dma_req_status; +#[doc = "DMA_SREQ_STATUS register accessor: an alias for `Reg`"] +pub type DMA_SREQ_STATUS = crate::Reg; +#[doc = "DMA single request status"] +pub mod dma_sreq_status; +#[doc = "DMA_DONE_SET register accessor: an alias for `Reg`"] +pub type DMA_DONE_SET = crate::Reg; +#[doc = "DMA done set"] +pub mod dma_done_set; +#[doc = "DMA_DONE_CLR register accessor: an alias for `Reg`"] +pub type DMA_DONE_CLR = crate::Reg; +#[doc = "DMA done clear"] +pub mod dma_done_clr; +#[doc = "DMA_ACTIVE_SET register accessor: an alias for `Reg`"] +pub type DMA_ACTIVE_SET = crate::Reg; +#[doc = "DMA active set"] +pub mod dma_active_set; +#[doc = "DMA_ACTIVE_CLR register accessor: an alias for `Reg`"] +pub type DMA_ACTIVE_CLR = crate::Reg; +#[doc = "DMA active clear"] +pub mod dma_active_clr; +#[doc = "ERR_SET register accessor: an alias for `Reg`"] +pub type ERR_SET = crate::Reg; +#[doc = "DMA bus error set"] +pub mod err_set; +#[doc = "PERIPH_ID_4 register accessor: an alias for `Reg`"] +pub type PERIPH_ID_4 = crate::Reg; +#[doc = "DMA Peripheral ID 4"] +pub mod periph_id_4; +#[doc = "PERIPH_ID_0 register accessor: an alias for `Reg`"] +pub type PERIPH_ID_0 = crate::Reg; +#[doc = "DMA Peripheral ID 0"] +pub mod periph_id_0; +#[doc = "PERIPH_ID_1 register accessor: an alias for `Reg`"] +pub type PERIPH_ID_1 = crate::Reg; +#[doc = "DMA Peripheral ID 1"] +pub mod periph_id_1; +#[doc = "PERIPH_ID_2 register accessor: an alias for `Reg`"] +pub type PERIPH_ID_2 = crate::Reg; +#[doc = "DMA Peripheral ID 2"] +pub mod periph_id_2; +#[doc = "PERIPH_ID_3 register accessor: an alias for `Reg`"] +pub type PERIPH_ID_3 = crate::Reg; +#[doc = "DMA Peripheral ID 3"] +pub mod periph_id_3; +#[doc = "PRIMECELL_ID_0 register accessor: an alias for `Reg`"] +pub type PRIMECELL_ID_0 = crate::Reg; +#[doc = "DMA PrimeCell ID 0"] +pub mod primecell_id_0; +#[doc = "PRIMECELL_ID_1 register accessor: an alias for `Reg`"] +pub type PRIMECELL_ID_1 = crate::Reg; +#[doc = "DMA PrimeCell ID 1"] +pub mod primecell_id_1; +#[doc = "PRIMECELL_ID_2 register accessor: an alias for `Reg`"] +pub type PRIMECELL_ID_2 = crate::Reg; +#[doc = "DMA PrimeCell ID 2"] +pub mod primecell_id_2; +#[doc = "PRIMECELL_ID_3 register accessor: an alias for `Reg`"] +pub type PRIMECELL_ID_3 = crate::Reg; +#[doc = "DMA PrimeCell ID 3"] +pub mod primecell_id_3; diff --git a/src/dma/alt_ctrl_base_ptr.rs b/src/dma/alt_ctrl_base_ptr.rs new file mode 100644 index 0000000..3be2a2a --- /dev/null +++ b/src/dma/alt_ctrl_base_ptr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ALT_CTRL_BASE_PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALT_CTRL_BASE_PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ALT_CTRL_BASE_PTR` reader - Base Pointer for Alternate DMA Control Register"] +pub struct ALT_CTRL_BASE_PTR_R(crate::FieldReader); +impl ALT_CTRL_BASE_PTR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ALT_CTRL_BASE_PTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALT_CTRL_BASE_PTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALT_CTRL_BASE_PTR` writer - Base Pointer for Alternate DMA Control Register"] +pub struct ALT_CTRL_BASE_PTR_W<'a> { + w: &'a mut W, +} +impl<'a> ALT_CTRL_BASE_PTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Base Pointer for Alternate DMA Control Register"] + #[inline(always)] + pub fn alt_ctrl_base_ptr(&self) -> ALT_CTRL_BASE_PTR_R { + ALT_CTRL_BASE_PTR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Base Pointer for Alternate DMA Control Register"] + #[inline(always)] + pub fn alt_ctrl_base_ptr(&mut self) -> ALT_CTRL_BASE_PTR_W { + ALT_CTRL_BASE_PTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Channel alternate control data base pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alt_ctrl_base_ptr](index.html) module"] +pub struct ALT_CTRL_BASE_PTR_SPEC; +impl crate::RegisterSpec for ALT_CTRL_BASE_PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alt_ctrl_base_ptr::R](R) reader structure"] +impl crate::Readable for ALT_CTRL_BASE_PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alt_ctrl_base_ptr::W](W) writer structure"] +impl crate::Writable for ALT_CTRL_BASE_PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ALT_CTRL_BASE_PTR to value 0"] +impl crate::Resettable for ALT_CTRL_BASE_PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/cfg.rs b/src/dma/cfg.rs new file mode 100644 index 0000000..b1115ae --- /dev/null +++ b/src/dma/cfg.rs @@ -0,0 +1,62 @@ +#[doc = "Register `CFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHNL_PROT_CTRL` writer - HPROT\\[3:0\\]"] +pub struct CHNL_PROT_CTRL_W<'a> { + w: &'a mut W, +} +impl<'a> CHNL_PROT_CTRL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u32 & 0x07) << 5); + self.w + } +} +impl W { + #[doc = "Bits 5:7 - HPROT\\[3:0\\]"] + #[inline(always)] + pub fn chnl_prot_ctrl(&mut self) -> CHNL_PROT_CTRL_W { + CHNL_PROT_CTRL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CFG_SPEC; +impl crate::RegisterSpec for CFG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [cfg::W](W) writer structure"] +impl crate::Writable for CFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFG to value 0"] +impl crate::Resettable for CFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_enable_clr.rs b/src/dma/chnl_enable_clr.rs new file mode 100644 index 0000000..58a31ae --- /dev/null +++ b/src/dma/chnl_enable_clr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CHNL_ENABLE_CLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHNL_ENABLE_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - Channel Enable clear"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - Channel Enable clear"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - Channel Enable clear"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - Channel Enable clear"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - Channel Enable clear"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - Channel Enable clear"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - Channel Enable clear"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - Channel Enable clear"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Channel Enable clear"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Enable clear"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable clear"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel Enable clear"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Channel Enable clear"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel Enable clear"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel Enable clear"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel Enable clear"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_enable_clr](index.html) module"] +pub struct CHNL_ENABLE_CLR_SPEC; +impl crate::RegisterSpec for CHNL_ENABLE_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chnl_enable_clr::R](R) reader structure"] +impl crate::Readable for CHNL_ENABLE_CLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chnl_enable_clr::W](W) writer structure"] +impl crate::Writable for CHNL_ENABLE_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_ENABLE_CLR to value 0"] +impl crate::Resettable for CHNL_ENABLE_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_enable_set.rs b/src/dma/chnl_enable_set.rs new file mode 100644 index 0000000..4edfebf --- /dev/null +++ b/src/dma/chnl_enable_set.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CHNL_ENABLE_SET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHNL_ENABLE_SET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - Channel Enable set"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - Channel Enable set"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - Channel Enable set"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - Channel Enable set"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - Channel Enable set"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - Channel Enable set"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - Channel Enable set"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - Channel Enable set"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Channel Enable set"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Enable set"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable set"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel Enable set"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Channel Enable set"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel Enable set"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel Enable set"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel Enable set"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_enable_set](index.html) module"] +pub struct CHNL_ENABLE_SET_SPEC; +impl crate::RegisterSpec for CHNL_ENABLE_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chnl_enable_set::R](R) reader structure"] +impl crate::Readable for CHNL_ENABLE_SET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chnl_enable_set::W](W) writer structure"] +impl crate::Writable for CHNL_ENABLE_SET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_ENABLE_SET to value 0"] +impl crate::Resettable for CHNL_ENABLE_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_pri_alt_clr.rs b/src/dma/chnl_pri_alt_clr.rs new file mode 100644 index 0000000..4976775 --- /dev/null +++ b/src/dma/chnl_pri_alt_clr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CHNL_PRI_ALT_CLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHNL_PRI_ALT_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - Channel PRI_ALT clear"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - Channel PRI_ALT clear"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - Channel PRI_ALT clear"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - Channel PRI_ALT clear"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - Channel PRI_ALT clear"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - Channel PRI_ALT clear"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - Channel PRI_ALT clear"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - Channel PRI_ALT clear"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel primary alternate clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_pri_alt_clr](index.html) module"] +pub struct CHNL_PRI_ALT_CLR_SPEC; +impl crate::RegisterSpec for CHNL_PRI_ALT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chnl_pri_alt_clr::R](R) reader structure"] +impl crate::Readable for CHNL_PRI_ALT_CLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chnl_pri_alt_clr::W](W) writer structure"] +impl crate::Writable for CHNL_PRI_ALT_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_PRI_ALT_CLR to value 0"] +impl crate::Resettable for CHNL_PRI_ALT_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_pri_alt_set.rs b/src/dma/chnl_pri_alt_set.rs new file mode 100644 index 0000000..65a8c09 --- /dev/null +++ b/src/dma/chnl_pri_alt_set.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CHNL_PRI_ALT_SET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHNL_PRI_ALT_SET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - Channel PRI_ALT set"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - Channel PRI_ALT set"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - Channel PRI_ALT set"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - Channel PRI_ALT set"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - Channel PRI_ALT set"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - Channel PRI_ALT set"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - Channel PRI_ALT set"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - Channel PRI_ALT set"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel primary alternate set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_pri_alt_set](index.html) module"] +pub struct CHNL_PRI_ALT_SET_SPEC; +impl crate::RegisterSpec for CHNL_PRI_ALT_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chnl_pri_alt_set::R](R) reader structure"] +impl crate::Readable for CHNL_PRI_ALT_SET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chnl_pri_alt_set::W](W) writer structure"] +impl crate::Writable for CHNL_PRI_ALT_SET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_PRI_ALT_SET to value 0"] +impl crate::Resettable for CHNL_PRI_ALT_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_priority_clr.rs b/src/dma/chnl_priority_clr.rs new file mode 100644 index 0000000..d6731cb --- /dev/null +++ b/src/dma/chnl_priority_clr.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CHNL_PRIORITY_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` writer - Channel PRIORITY clear"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` writer - Channel PRIORITY clear"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` writer - Channel PRIORITY clear"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` writer - Channel PRIORITY clear"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 3 - Channel PRIORITY clear"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel PRIORITY clear"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel PRIORITY clear"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel PRIORITY clear"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel priority clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_priority_clr](index.html) module"] +pub struct CHNL_PRIORITY_CLR_SPEC; +impl crate::RegisterSpec for CHNL_PRIORITY_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [chnl_priority_clr::W](W) writer structure"] +impl crate::Writable for CHNL_PRIORITY_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_PRIORITY_CLR to value 0"] +impl crate::Resettable for CHNL_PRIORITY_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_priority_set.rs b/src/dma/chnl_priority_set.rs new file mode 100644 index 0000000..e5a3626 --- /dev/null +++ b/src/dma/chnl_priority_set.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CHNL_PRIORITY_SET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHNL_PRIORITY_SET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - Channel PRIORITY set"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - Channel PRIORITY set"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - Channel PRIORITY set"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - Channel PRIORITY set"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - Channel PRIORITY set"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - Channel PRIORITY set"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - Channel PRIORITY set"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - Channel PRIORITY set"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel priority set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_priority_set](index.html) module"] +pub struct CHNL_PRIORITY_SET_SPEC; +impl crate::RegisterSpec for CHNL_PRIORITY_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chnl_priority_set::R](R) reader structure"] +impl crate::Readable for CHNL_PRIORITY_SET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chnl_priority_set::W](W) writer structure"] +impl crate::Writable for CHNL_PRIORITY_SET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_PRIORITY_SET to value 0"] +impl crate::Resettable for CHNL_PRIORITY_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_req_mask_clr.rs b/src/dma/chnl_req_mask_clr.rs new file mode 100644 index 0000000..8bd9acd --- /dev/null +++ b/src/dma/chnl_req_mask_clr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CHNL_REQ_MASK_CLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHNL_REQ_MASK_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - Channel Request Mask clear"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - Channel Request Mask clear"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - Channel Request Mask clear"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - Channel Request Mask clear"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - Channel Request Mask clear"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - Channel Request Mask clear"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - Channel Request Mask clear"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - Channel Request Mask clear"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel request mask clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_req_mask_clr](index.html) module"] +pub struct CHNL_REQ_MASK_CLR_SPEC; +impl crate::RegisterSpec for CHNL_REQ_MASK_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chnl_req_mask_clr::R](R) reader structure"] +impl crate::Readable for CHNL_REQ_MASK_CLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chnl_req_mask_clr::W](W) writer structure"] +impl crate::Writable for CHNL_REQ_MASK_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_REQ_MASK_CLR to value 0"] +impl crate::Resettable for CHNL_REQ_MASK_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_req_mask_set.rs b/src/dma/chnl_req_mask_set.rs new file mode 100644 index 0000000..9ed07ca --- /dev/null +++ b/src/dma/chnl_req_mask_set.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CHNL_REQ_MASK_SET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHNL_REQ_MASK_SET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - Channel Request Mask set"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - Channel Request Mask set"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - Channel Request Mask set"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - Channel Request Mask set"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - Channel Request Mask set"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - Channel Request Mask set"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - Channel Request Mask set"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - Channel Request Mask set"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Channel Request Mask set"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Request Mask set"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Request Mask set"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel Request Mask set"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Channel Request Mask set"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel Request Mask set"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel Request Mask set"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel Request Mask set"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel request mask set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_req_mask_set](index.html) module"] +pub struct CHNL_REQ_MASK_SET_SPEC; +impl crate::RegisterSpec for CHNL_REQ_MASK_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chnl_req_mask_set::R](R) reader structure"] +impl crate::Readable for CHNL_REQ_MASK_SET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chnl_req_mask_set::W](W) writer structure"] +impl crate::Writable for CHNL_REQ_MASK_SET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_REQ_MASK_SET to value 0"] +impl crate::Resettable for CHNL_REQ_MASK_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_sw_request.rs b/src/dma/chnl_sw_request.rs new file mode 100644 index 0000000..8a75692 --- /dev/null +++ b/src/dma/chnl_sw_request.rs @@ -0,0 +1,153 @@ +#[doc = "Register `CHNL_SW_REQUEST` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` writer - Channel SW request"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` writer - Channel SW request"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` writer - Channel SW request"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` writer - Channel SW request"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl W { + #[doc = "Bit 3 - Channel SW request"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel SW request"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel SW request"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel SW request"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel software request\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_sw_request](index.html) module"] +pub struct CHNL_SW_REQUEST_SPEC; +impl crate::RegisterSpec for CHNL_SW_REQUEST_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [chnl_sw_request::W](W) writer structure"] +impl crate::Writable for CHNL_SW_REQUEST_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_SW_REQUEST to value 0"] +impl crate::Resettable for CHNL_SW_REQUEST_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_useburst_clr.rs b/src/dma/chnl_useburst_clr.rs new file mode 100644 index 0000000..c7fa011 --- /dev/null +++ b/src/dma/chnl_useburst_clr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CHNL_USEBURST_CLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHNL_USEBURST_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - Channel use burst clear"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - Channel use burst clear"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - Channel use burst clear"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - Channel use burst clear"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - Channel use burst clear"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - Channel use burst clear"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - Channel use burst clear"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - Channel use burst clear"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Channel use burst clear"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel use burst clear"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Channel use burst clear"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel use burst clear"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Channel use burst clear"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel use burst clear"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel use burst clear"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel use burst clear"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel useburst clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_useburst_clr](index.html) module"] +pub struct CHNL_USEBURST_CLR_SPEC; +impl crate::RegisterSpec for CHNL_USEBURST_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chnl_useburst_clr::R](R) reader structure"] +impl crate::Readable for CHNL_USEBURST_CLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chnl_useburst_clr::W](W) writer structure"] +impl crate::Writable for CHNL_USEBURST_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_USEBURST_CLR to value 0"] +impl crate::Resettable for CHNL_USEBURST_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/chnl_useburst_set.rs b/src/dma/chnl_useburst_set.rs new file mode 100644 index 0000000..a2055d2 --- /dev/null +++ b/src/dma/chnl_useburst_set.rs @@ -0,0 +1,254 @@ +#[doc = "Register `CHNL_USEBURST_SET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHNL_USEBURST_SET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - Channel use burst set"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - Channel use burst set"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - Channel use burst set"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - Channel use burst set"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - Channel use burst set"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - Channel use burst set"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - Channel use burst set"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - Channel use burst set"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Channel use burst set"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel use burst set"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Channel use burst set"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Channel use burst set"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Channel use burst set"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - Channel use burst set"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - Channel use burst set"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - Channel use burst set"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA channel useburst set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_useburst_set](index.html) module"] +pub struct CHNL_USEBURST_SET_SPEC; +impl crate::RegisterSpec for CHNL_USEBURST_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chnl_useburst_set::R](R) reader structure"] +impl crate::Readable for CHNL_USEBURST_SET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chnl_useburst_set::W](W) writer structure"] +impl crate::Writable for CHNL_USEBURST_SET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHNL_USEBURST_SET to value 0"] +impl crate::Resettable for CHNL_USEBURST_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/ctrl_base_ptr.rs b/src/dma/ctrl_base_ptr.rs new file mode 100644 index 0000000..8471c0f --- /dev/null +++ b/src/dma/ctrl_base_ptr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL_BASE_PTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL_BASE_PTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CTRL_BASE_PTR` reader - Base Pointer for DMA Control Registers"] +pub struct CTRL_BASE_PTR_R(crate::FieldReader); +impl CTRL_BASE_PTR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CTRL_BASE_PTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRL_BASE_PTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRL_BASE_PTR` writer - Base Pointer for DMA Control Registers"] +pub struct CTRL_BASE_PTR_W<'a> { + w: &'a mut W, +} +impl<'a> CTRL_BASE_PTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01ff_ffff << 7)) | ((value as u32 & 0x01ff_ffff) << 7); + self.w + } +} +impl R { + #[doc = "Bits 7:31 - Base Pointer for DMA Control Registers"] + #[inline(always)] + pub fn ctrl_base_ptr(&self) -> CTRL_BASE_PTR_R { + CTRL_BASE_PTR_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 7:31 - Base Pointer for DMA Control Registers"] + #[inline(always)] + pub fn ctrl_base_ptr(&mut self) -> CTRL_BASE_PTR_W { + CTRL_BASE_PTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Base Pointer for DMA Control Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl_base_ptr](index.html) module"] +pub struct CTRL_BASE_PTR_SPEC; +impl crate::RegisterSpec for CTRL_BASE_PTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl_base_ptr::R](R) reader structure"] +impl crate::Readable for CTRL_BASE_PTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl_base_ptr::W](W) writer structure"] +impl crate::Writable for CTRL_BASE_PTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL_BASE_PTR to value 0"] +impl crate::Resettable for CTRL_BASE_PTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/dma_active_clr.rs b/src/dma/dma_active_clr.rs new file mode 100644 index 0000000..930411c --- /dev/null +++ b/src/dma/dma_active_clr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `DMA_ACTIVE_CLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_ACTIVE_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - DMA Active clear"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - DMA Active clear"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - DMA Active clear"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - DMA Active clear"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - DMA Active clear"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - DMA Active clear"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - DMA Active clear"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - DMA Active clear"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - DMA Active clear"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - DMA Active clear"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Active clear"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - DMA Active clear"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - DMA Active clear"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - DMA Active clear"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - DMA Active clear"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - DMA Active clear"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA active clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_active_clr](index.html) module"] +pub struct DMA_ACTIVE_CLR_SPEC; +impl crate::RegisterSpec for DMA_ACTIVE_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_active_clr::R](R) reader structure"] +impl crate::Readable for DMA_ACTIVE_CLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_active_clr::W](W) writer structure"] +impl crate::Writable for DMA_ACTIVE_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_ACTIVE_CLR to value 0"] +impl crate::Resettable for DMA_ACTIVE_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/dma_active_set.rs b/src/dma/dma_active_set.rs new file mode 100644 index 0000000..6a792b3 --- /dev/null +++ b/src/dma/dma_active_set.rs @@ -0,0 +1,254 @@ +#[doc = "Register `DMA_ACTIVE_SET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_ACTIVE_SET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - DMA Active Set"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - DMA Active Set"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - DMA Active Set"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - DMA Active Set"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - DMA Active Set"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - DMA Active Set"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - DMA Active Set"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - DMA Active Set"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - DMA Active Set"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - DMA Active Set"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Active Set"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - DMA Active Set"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - DMA Active Set"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - DMA Active Set"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - DMA Active Set"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - DMA Active Set"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA active set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_active_set](index.html) module"] +pub struct DMA_ACTIVE_SET_SPEC; +impl crate::RegisterSpec for DMA_ACTIVE_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_active_set::R](R) reader structure"] +impl crate::Readable for DMA_ACTIVE_SET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_active_set::W](W) writer structure"] +impl crate::Writable for DMA_ACTIVE_SET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_ACTIVE_SET to value 0"] +impl crate::Resettable for DMA_ACTIVE_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/dma_done_clr.rs b/src/dma/dma_done_clr.rs new file mode 100644 index 0000000..121bb53 --- /dev/null +++ b/src/dma/dma_done_clr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `DMA_DONE_CLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_DONE_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - DMA Done clear for this CH"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - DMA Done clear for this CH"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - DMA Done clear for this CH"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - DMA Done clear for this CH"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - DMA Done clear for this CH"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - DMA Done clear for this CH"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - DMA Done clear for this CH"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - DMA Done clear for this CH"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA done clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_done_clr](index.html) module"] +pub struct DMA_DONE_CLR_SPEC; +impl crate::RegisterSpec for DMA_DONE_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_done_clr::R](R) reader structure"] +impl crate::Readable for DMA_DONE_CLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_done_clr::W](W) writer structure"] +impl crate::Writable for DMA_DONE_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_DONE_CLR to value 0"] +impl crate::Resettable for DMA_DONE_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/dma_done_set.rs b/src/dma/dma_done_set.rs new file mode 100644 index 0000000..47e598a --- /dev/null +++ b/src/dma/dma_done_set.rs @@ -0,0 +1,254 @@ +#[doc = "Register `DMA_DONE_SET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_DONE_SET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - DMA Done Set for this CH"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - DMA Done Set for this CH"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - DMA Done Set for this CH"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - DMA Done Set for this CH"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - DMA Done Set for this CH"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - DMA Done Set for this CH"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - DMA Done Set for this CH"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - DMA Done Set for this CH"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA done set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_done_set](index.html) module"] +pub struct DMA_DONE_SET_SPEC; +impl crate::RegisterSpec for DMA_DONE_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_done_set::R](R) reader structure"] +impl crate::Readable for DMA_DONE_SET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_done_set::W](W) writer structure"] +impl crate::Writable for DMA_DONE_SET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_DONE_SET to value 0"] +impl crate::Resettable for DMA_DONE_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/dma_req_status.rs b/src/dma/dma_req_status.rs new file mode 100644 index 0000000..7c745e2 --- /dev/null +++ b/src/dma/dma_req_status.rs @@ -0,0 +1,254 @@ +#[doc = "Register `DMA_REQ_STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_REQ_STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - DMA Request Status for this CH"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - DMA Request Status for this CH"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - DMA Request Status for this CH"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - DMA Request Status for this CH"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - DMA Request Status for this CH"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - DMA Request Status for this CH"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - DMA Request Status for this CH"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - DMA Request Status for this CH"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_req_status](index.html) module"] +pub struct DMA_REQ_STATUS_SPEC; +impl crate::RegisterSpec for DMA_REQ_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_req_status::R](R) reader structure"] +impl crate::Readable for DMA_REQ_STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_req_status::W](W) writer structure"] +impl crate::Writable for DMA_REQ_STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_REQ_STATUS to value 0"] +impl crate::Resettable for DMA_REQ_STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/dma_sreq_status.rs b/src/dma/dma_sreq_status.rs new file mode 100644 index 0000000..b553d44 --- /dev/null +++ b/src/dma/dma_sreq_status.rs @@ -0,0 +1,254 @@ +#[doc = "Register `DMA_SREQ_STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_SREQ_STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CH3` reader - DMA SRequest Status for this CH"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH3` writer - DMA SRequest Status for this CH"] +pub struct CH3_W<'a> { + w: &'a mut W, +} +impl<'a> CH3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CH2` reader - DMA SRequest Status for this CH"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` writer - DMA SRequest Status for this CH"] +pub struct CH2_W<'a> { + w: &'a mut W, +} +impl<'a> CH2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CH1` reader - DMA SRequest Status for this CH"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` writer - DMA SRequest Status for this CH"] +pub struct CH1_W<'a> { + w: &'a mut W, +} +impl<'a> CH1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CH0` reader - DMA SRequest Status for this CH"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` writer - DMA SRequest Status for this CH"] +pub struct CH0_W<'a> { + w: &'a mut W, +} +impl<'a> CH0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch3(&mut self) -> CH3_W { + CH3_W { w: self } + } + #[doc = "Bit 2 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch2(&mut self) -> CH2_W { + CH2_W { w: self } + } + #[doc = "Bit 1 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch1(&mut self) -> CH1_W { + CH1_W { w: self } + } + #[doc = "Bit 0 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch0(&mut self) -> CH0_W { + CH0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA single request status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_sreq_status](index.html) module"] +pub struct DMA_SREQ_STATUS_SPEC; +impl crate::RegisterSpec for DMA_SREQ_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_sreq_status::R](R) reader structure"] +impl crate::Readable for DMA_SREQ_STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_sreq_status::W](W) writer structure"] +impl crate::Writable for DMA_SREQ_STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_SREQ_STATUS to value 0"] +impl crate::Resettable for DMA_SREQ_STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/err_clr.rs b/src/dma/err_clr.rs new file mode 100644 index 0000000..9dbc04f --- /dev/null +++ b/src/dma/err_clr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `ERR_CLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ERR_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR_CLR` reader - Error Clear"] +pub struct ERR_CLR_R(crate::FieldReader); +impl ERR_CLR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_CLR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_CLR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR_CLR` writer - Error Clear"] +pub struct ERR_CLR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_CLR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn err_clr(&self) -> ERR_CLR_R { + ERR_CLR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn err_clr(&mut self) -> ERR_CLR_W { + ERR_CLR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA bus error clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [err_clr](index.html) module"] +pub struct ERR_CLR_SPEC; +impl crate::RegisterSpec for ERR_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [err_clr::R](R) reader structure"] +impl crate::Readable for ERR_CLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [err_clr::W](W) writer structure"] +impl crate::Writable for ERR_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ERR_CLR to value 0"] +impl crate::Resettable for ERR_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/err_set.rs b/src/dma/err_set.rs new file mode 100644 index 0000000..0c335e9 --- /dev/null +++ b/src/dma/err_set.rs @@ -0,0 +1,53 @@ +#[doc = "Register `ERR_SET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ERR_SET` reader - Set Error"] +pub struct ERR_SET_R(crate::FieldReader); +impl ERR_SET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERR_SET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_SET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Set Error"] + #[inline(always)] + pub fn err_set(&self) -> ERR_SET_R { + ERR_SET_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "DMA bus error set\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [err_set](index.html) module"] +pub struct ERR_SET_SPEC; +impl crate::RegisterSpec for ERR_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [err_set::R](R) reader structure"] +impl crate::Readable for ERR_SET_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ERR_SET to value 0"] +impl crate::Resettable for ERR_SET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/integration_cfg.rs b/src/dma/integration_cfg.rs new file mode 100644 index 0000000..ee457c5 --- /dev/null +++ b/src/dma/integration_cfg.rs @@ -0,0 +1,113 @@ +#[doc = "Register `INTEGRATION_CFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTEGRATION_CFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INT_TEST_EN` reader - Error Clear"] +pub struct INT_TEST_EN_R(crate::FieldReader); +impl INT_TEST_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INT_TEST_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INT_TEST_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INT_TEST_EN` writer - Error Clear"] +pub struct INT_TEST_EN_W<'a> { + w: &'a mut W, +} +impl<'a> INT_TEST_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn int_test_en(&self) -> INT_TEST_EN_R { + INT_TEST_EN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn int_test_en(&mut self) -> INT_TEST_EN_W { + INT_TEST_EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA integration configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [integration_cfg](index.html) module"] +pub struct INTEGRATION_CFG_SPEC; +impl crate::RegisterSpec for INTEGRATION_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [integration_cfg::R](R) reader structure"] +impl crate::Readable for INTEGRATION_CFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [integration_cfg::W](W) writer structure"] +impl crate::Writable for INTEGRATION_CFG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTEGRATION_CFG to value 0"] +impl crate::Resettable for INTEGRATION_CFG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/periph_id_0.rs b/src/dma/periph_id_0.rs new file mode 100644 index 0000000..df8a4bf --- /dev/null +++ b/src/dma/periph_id_0.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERIPH_ID_0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERIPH_ID_0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PART_NUMBER_0` reader - Part Number"] +pub struct PART_NUMBER_0_R(crate::FieldReader); +impl PART_NUMBER_0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PART_NUMBER_0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PART_NUMBER_0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PART_NUMBER_0` writer - Part Number"] +pub struct PART_NUMBER_0_W<'a> { + w: &'a mut W, +} +impl<'a> PART_NUMBER_0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Part Number"] + #[inline(always)] + pub fn part_number_0(&self) -> PART_NUMBER_0_R { + PART_NUMBER_0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Part Number"] + #[inline(always)] + pub fn part_number_0(&mut self) -> PART_NUMBER_0_W { + PART_NUMBER_0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Peripheral ID 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [periph_id_0](index.html) module"] +pub struct PERIPH_ID_0_SPEC; +impl crate::RegisterSpec for PERIPH_ID_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [periph_id_0::R](R) reader structure"] +impl crate::Readable for PERIPH_ID_0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [periph_id_0::W](W) writer structure"] +impl crate::Writable for PERIPH_ID_0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERIPH_ID_0 to value 0x30"] +impl crate::Resettable for PERIPH_ID_0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x30 + } +} diff --git a/src/dma/periph_id_1.rs b/src/dma/periph_id_1.rs new file mode 100644 index 0000000..e97040e --- /dev/null +++ b/src/dma/periph_id_1.rs @@ -0,0 +1,73 @@ +#[doc = "Register `PERIPH_ID_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEP106_ID_3_0` reader - Indentity Code"] +pub struct JEP106_ID_3_0_R(crate::FieldReader); +impl JEP106_ID_3_0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEP106_ID_3_0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEP106_ID_3_0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PART_NUMBER_1` reader - Part Number 1"] +pub struct PART_NUMBER_1_R(crate::FieldReader); +impl PART_NUMBER_1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PART_NUMBER_1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PART_NUMBER_1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 4:7 - Indentity Code"] + #[inline(always)] + pub fn jep106_id_3_0(&self) -> JEP106_ID_3_0_R { + JEP106_ID_3_0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - Part Number 1"] + #[inline(always)] + pub fn part_number_1(&self) -> PART_NUMBER_1_R { + PART_NUMBER_1_R::new((self.bits & 0x0f) as u8) + } +} +#[doc = "DMA Peripheral ID 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [periph_id_1](index.html) module"] +pub struct PERIPH_ID_1_SPEC; +impl crate::RegisterSpec for PERIPH_ID_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [periph_id_1::R](R) reader structure"] +impl crate::Readable for PERIPH_ID_1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERIPH_ID_1 to value 0xb2"] +impl crate::Resettable for PERIPH_ID_1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb2 + } +} diff --git a/src/dma/periph_id_2.rs b/src/dma/periph_id_2.rs new file mode 100644 index 0000000..d6b5e70 --- /dev/null +++ b/src/dma/periph_id_2.rs @@ -0,0 +1,187 @@ +#[doc = "Register `PERIPH_ID_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERIPH_ID_2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REVISION` reader - Revision"] +pub struct REVISION_R(crate::FieldReader); +impl REVISION_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + REVISION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REVISION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REVISION` writer - Revision"] +pub struct REVISION_W<'a> { + w: &'a mut W, +} +impl<'a> REVISION_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `JEDEC_USED` reader - JEDEC"] +pub struct JEDEC_USED_R(crate::FieldReader); +impl JEDEC_USED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JEDEC_USED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEDEC_USED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEDEC_USED` writer - JEDEC"] +pub struct JEDEC_USED_W<'a> { + w: &'a mut W, +} +impl<'a> JEDEC_USED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `JEP106_ID_6_4` reader - JEP106"] +pub struct JEP106_ID_6_4_R(crate::FieldReader); +impl JEP106_ID_6_4_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEP106_ID_6_4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEP106_ID_6_4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEP106_ID_6_4` writer - JEP106"] +pub struct JEP106_ID_6_4_W<'a> { + w: &'a mut W, +} +impl<'a> JEP106_ID_6_4_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 4:7 - Revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 3 - JEDEC"] + #[inline(always)] + pub fn jedec_used(&self) -> JEDEC_USED_R { + JEDEC_USED_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 0:2 - JEP106"] + #[inline(always)] + pub fn jep106_id_6_4(&self) -> JEP106_ID_6_4_R { + JEP106_ID_6_4_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - Revision"] + #[inline(always)] + pub fn revision(&mut self) -> REVISION_W { + REVISION_W { w: self } + } + #[doc = "Bit 3 - JEDEC"] + #[inline(always)] + pub fn jedec_used(&mut self) -> JEDEC_USED_W { + JEDEC_USED_W { w: self } + } + #[doc = "Bits 0:2 - JEP106"] + #[inline(always)] + pub fn jep106_id_6_4(&mut self) -> JEP106_ID_6_4_W { + JEP106_ID_6_4_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Peripheral ID 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [periph_id_2](index.html) module"] +pub struct PERIPH_ID_2_SPEC; +impl crate::RegisterSpec for PERIPH_ID_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [periph_id_2::R](R) reader structure"] +impl crate::Readable for PERIPH_ID_2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [periph_id_2::W](W) writer structure"] +impl crate::Writable for PERIPH_ID_2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERIPH_ID_2 to value 0xbc"] +impl crate::Resettable for PERIPH_ID_2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xbc + } +} diff --git a/src/dma/periph_id_3.rs b/src/dma/periph_id_3.rs new file mode 100644 index 0000000..c9c9312 --- /dev/null +++ b/src/dma/periph_id_3.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PERIPH_ID_3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERIPH_ID_3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MOD_NUMBER` reader - Controller Modifications"] +pub struct MOD_NUMBER_R(crate::FieldReader); +impl MOD_NUMBER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MOD_NUMBER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MOD_NUMBER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MOD_NUMBER` writer - Controller Modifications"] +pub struct MOD_NUMBER_W<'a> { + w: &'a mut W, +} +impl<'a> MOD_NUMBER_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Controller Modifications"] + #[inline(always)] + pub fn mod_number(&self) -> MOD_NUMBER_R { + MOD_NUMBER_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Controller Modifications"] + #[inline(always)] + pub fn mod_number(&mut self) -> MOD_NUMBER_W { + MOD_NUMBER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Peripheral ID 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [periph_id_3](index.html) module"] +pub struct PERIPH_ID_3_SPEC; +impl crate::RegisterSpec for PERIPH_ID_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [periph_id_3::R](R) reader structure"] +impl crate::Readable for PERIPH_ID_3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [periph_id_3::W](W) writer structure"] +impl crate::Writable for PERIPH_ID_3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERIPH_ID_3 to value 0"] +impl crate::Resettable for PERIPH_ID_3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/periph_id_4.rs b/src/dma/periph_id_4.rs new file mode 100644 index 0000000..6a2a891 --- /dev/null +++ b/src/dma/periph_id_4.rs @@ -0,0 +1,140 @@ +#[doc = "Register `PERIPH_ID_4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERIPH_ID_4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BLOCK_COUNT` reader - The Number of 4k Address Blocks Required"] +pub struct BLOCK_COUNT_R(crate::FieldReader); +impl BLOCK_COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BLOCK_COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLOCK_COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLOCK_COUNT` writer - The Number of 4k Address Blocks Required"] +pub struct BLOCK_COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> BLOCK_COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); + self.w + } +} +#[doc = "Field `JEP106_C_CODE` reader - JEP106"] +pub struct JEP106_C_CODE_R(crate::FieldReader); +impl JEP106_C_CODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + JEP106_C_CODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JEP106_C_CODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JEP106_C_CODE` writer - JEP106"] +pub struct JEP106_C_CODE_W<'a> { + w: &'a mut W, +} +impl<'a> JEP106_C_CODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 4:7 - The Number of 4k Address Blocks Required"] + #[inline(always)] + pub fn block_count(&self) -> BLOCK_COUNT_R { + BLOCK_COUNT_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 0:3 - JEP106"] + #[inline(always)] + pub fn jep106_c_code(&self) -> JEP106_C_CODE_R { + JEP106_C_CODE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - The Number of 4k Address Blocks Required"] + #[inline(always)] + pub fn block_count(&mut self) -> BLOCK_COUNT_W { + BLOCK_COUNT_W { w: self } + } + #[doc = "Bits 0:3 - JEP106"] + #[inline(always)] + pub fn jep106_c_code(&mut self) -> JEP106_C_CODE_W { + JEP106_C_CODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Peripheral ID 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [periph_id_4](index.html) module"] +pub struct PERIPH_ID_4_SPEC; +impl crate::RegisterSpec for PERIPH_ID_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [periph_id_4::R](R) reader structure"] +impl crate::Readable for PERIPH_ID_4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [periph_id_4::W](W) writer structure"] +impl crate::Writable for PERIPH_ID_4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERIPH_ID_4 to value 0x04"] +impl crate::Resettable for PERIPH_ID_4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x04 + } +} diff --git a/src/dma/primecell_id_0.rs b/src/dma/primecell_id_0.rs new file mode 100644 index 0000000..7b0aa36 --- /dev/null +++ b/src/dma/primecell_id_0.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PRIMECELL_ID_0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRIMECELL_ID_0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRIMECELL_ID_0` reader - PrimeCell Identification"] +pub struct PRIMECELL_ID_0_R(crate::FieldReader); +impl PRIMECELL_ID_0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRIMECELL_ID_0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRIMECELL_ID_0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRIMECELL_ID_0` writer - PrimeCell Identification"] +pub struct PRIMECELL_ID_0_W<'a> { + w: &'a mut W, +} +impl<'a> PRIMECELL_ID_0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_0(&self) -> PRIMECELL_ID_0_R { + PRIMECELL_ID_0_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_0(&mut self) -> PRIMECELL_ID_0_W { + PRIMECELL_ID_0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA PrimeCell ID 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [primecell_id_0](index.html) module"] +pub struct PRIMECELL_ID_0_SPEC; +impl crate::RegisterSpec for PRIMECELL_ID_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [primecell_id_0::R](R) reader structure"] +impl crate::Readable for PRIMECELL_ID_0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [primecell_id_0::W](W) writer structure"] +impl crate::Writable for PRIMECELL_ID_0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRIMECELL_ID_0 to value 0x0d"] +impl crate::Resettable for PRIMECELL_ID_0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/src/dma/primecell_id_1.rs b/src/dma/primecell_id_1.rs new file mode 100644 index 0000000..5d6413a --- /dev/null +++ b/src/dma/primecell_id_1.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PRIMECELL_ID_1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRIMECELL_ID_1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRIMECELL_ID_1` reader - PrimeCell Identification"] +pub struct PRIMECELL_ID_1_R(crate::FieldReader); +impl PRIMECELL_ID_1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRIMECELL_ID_1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRIMECELL_ID_1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRIMECELL_ID_1` writer - PrimeCell Identification"] +pub struct PRIMECELL_ID_1_W<'a> { + w: &'a mut W, +} +impl<'a> PRIMECELL_ID_1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_1(&self) -> PRIMECELL_ID_1_R { + PRIMECELL_ID_1_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_1(&mut self) -> PRIMECELL_ID_1_W { + PRIMECELL_ID_1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA PrimeCell ID 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [primecell_id_1](index.html) module"] +pub struct PRIMECELL_ID_1_SPEC; +impl crate::RegisterSpec for PRIMECELL_ID_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [primecell_id_1::R](R) reader structure"] +impl crate::Readable for PRIMECELL_ID_1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [primecell_id_1::W](W) writer structure"] +impl crate::Writable for PRIMECELL_ID_1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRIMECELL_ID_1 to value 0xf0"] +impl crate::Resettable for PRIMECELL_ID_1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xf0 + } +} diff --git a/src/dma/primecell_id_2.rs b/src/dma/primecell_id_2.rs new file mode 100644 index 0000000..45ac294 --- /dev/null +++ b/src/dma/primecell_id_2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PRIMECELL_ID_2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRIMECELL_ID_2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRIMECELL_ID_2` reader - PrimeCell Identification"] +pub struct PRIMECELL_ID_2_R(crate::FieldReader); +impl PRIMECELL_ID_2_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRIMECELL_ID_2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRIMECELL_ID_2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRIMECELL_ID_2` writer - PrimeCell Identification"] +pub struct PRIMECELL_ID_2_W<'a> { + w: &'a mut W, +} +impl<'a> PRIMECELL_ID_2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_2(&self) -> PRIMECELL_ID_2_R { + PRIMECELL_ID_2_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_2(&mut self) -> PRIMECELL_ID_2_W { + PRIMECELL_ID_2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA PrimeCell ID 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [primecell_id_2](index.html) module"] +pub struct PRIMECELL_ID_2_SPEC; +impl crate::RegisterSpec for PRIMECELL_ID_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [primecell_id_2::R](R) reader structure"] +impl crate::Readable for PRIMECELL_ID_2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [primecell_id_2::W](W) writer structure"] +impl crate::Writable for PRIMECELL_ID_2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRIMECELL_ID_2 to value 0x05"] +impl crate::Resettable for PRIMECELL_ID_2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/src/dma/primecell_id_3.rs b/src/dma/primecell_id_3.rs new file mode 100644 index 0000000..edcd9ad --- /dev/null +++ b/src/dma/primecell_id_3.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PRIMECELL_ID_3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRIMECELL_ID_3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRIMECELL_ID_3` reader - PrimeCell Identification"] +pub struct PRIMECELL_ID_3_R(crate::FieldReader); +impl PRIMECELL_ID_3_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRIMECELL_ID_3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRIMECELL_ID_3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRIMECELL_ID_3` writer - PrimeCell Identification"] +pub struct PRIMECELL_ID_3_W<'a> { + w: &'a mut W, +} +impl<'a> PRIMECELL_ID_3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_3(&self) -> PRIMECELL_ID_3_R { + PRIMECELL_ID_3_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_3(&mut self) -> PRIMECELL_ID_3_W { + PRIMECELL_ID_3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA PrimeCell ID 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [primecell_id_3](index.html) module"] +pub struct PRIMECELL_ID_3_SPEC; +impl crate::RegisterSpec for PRIMECELL_ID_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [primecell_id_3::R](R) reader structure"] +impl crate::Readable for PRIMECELL_ID_3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [primecell_id_3::W](W) writer structure"] +impl crate::Writable for PRIMECELL_ID_3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRIMECELL_ID_3 to value 0xb1"] +impl crate::Resettable for PRIMECELL_ID_3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/src/dma/stall_status.rs b/src/dma/stall_status.rs new file mode 100644 index 0000000..2688bb3 --- /dev/null +++ b/src/dma/stall_status.rs @@ -0,0 +1,53 @@ +#[doc = "Register `STALL_STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STALL_STATUS` reader - DMA is stalled"] +pub struct STALL_STATUS_R(crate::FieldReader); +impl STALL_STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALL_STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALL_STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DMA is stalled"] + #[inline(always)] + pub fn stall_status(&self) -> STALL_STATUS_R { + STALL_STATUS_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "DMA stall status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stall_status](index.html) module"] +pub struct STALL_STATUS_SPEC; +impl crate::RegisterSpec for STALL_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [stall_status::R](R) reader structure"] +impl crate::Readable for STALL_STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STALL_STATUS to value 0"] +impl crate::Resettable for STALL_STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/status.rs b/src/dma/status.rs new file mode 100644 index 0000000..950a111 --- /dev/null +++ b/src/dma/status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TEST_STATUS` reader - Test Status Logic Included"] +pub struct TEST_STATUS_R(crate::FieldReader); +impl TEST_STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TEST_STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEST_STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHNLS_MINUS1` reader - Number of Available Channels Minus 1"] +pub struct CHNLS_MINUS1_R(crate::FieldReader); +impl CHNLS_MINUS1_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CHNLS_MINUS1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHNLS_MINUS1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATE` reader - Current State of the control state machine"] +pub struct STATE_R(crate::FieldReader); +impl STATE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASTER_ENABLE` reader - Enable status of the controller"] +pub struct MASTER_ENABLE_R(crate::FieldReader); +impl MASTER_ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MASTER_ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASTER_ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 28:31 - Test Status Logic Included"] + #[inline(always)] + pub fn test_status(&self) -> TEST_STATUS_R { + TEST_STATUS_R::new(((self.bits >> 28) & 0x0f) as u8) + } + #[doc = "Bits 16:20 - Number of Available Channels Minus 1"] + #[inline(always)] + pub fn chnls_minus1(&self) -> CHNLS_MINUS1_R { + CHNLS_MINUS1_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 4:7 - Current State of the control state machine"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 0 - Enable status of the controller"] + #[inline(always)] + pub fn master_enable(&self) -> MASTER_ENABLE_R { + MASTER_ENABLE_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "DMA Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dma/waitonreq_status.rs b/src/dma/waitonreq_status.rs new file mode 100644 index 0000000..c778f95 --- /dev/null +++ b/src/dma/waitonreq_status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `WAITONREQ_STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CH3` reader - DMA wait on request"] +pub struct CH3_R(crate::FieldReader); +impl CH3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH2` reader - DMA wait on request"] +pub struct CH2_R(crate::FieldReader); +impl CH2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH1` reader - DMA wait on request"] +pub struct CH1_R(crate::FieldReader); +impl CH1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CH0` reader - DMA wait on request"] +pub struct CH0_R(crate::FieldReader); +impl CH0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - DMA wait on request"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - DMA wait on request"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - DMA wait on request"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - DMA wait on request"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "DMA channel wait on request status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [waitonreq_status](index.html) module"] +pub struct WAITONREQ_STATUS_SPEC; +impl crate::RegisterSpec for WAITONREQ_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [waitonreq_status::R](R) reader structure"] +impl crate::Readable for WAITONREQ_STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WAITONREQ_STATUS to value 0"] +impl crate::Resettable for WAITONREQ_STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth.rs b/src/eth.rs new file mode 100644 index 0000000..8f034c1 --- /dev/null +++ b/src/eth.rs @@ -0,0 +1,585 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Operation mode register for the MAC"] + pub mac_config: crate::Reg, + #[doc = "0x04 - Contains the frame filtering controls"] + pub mac_frame_fltr: crate::Reg, + _reserved2: [u8; 0x08], + #[doc = "0x10 - Controls the management cycles to an external PHY"] + pub mac_gmii_addr: crate::Reg, + #[doc = "0x14 - Contains the data to be written to or read from the PHY register"] + pub mac_gmii_data: crate::Reg, + #[doc = "0x18 - Controls the generation of control frames"] + pub mac_flow_ctrl: crate::Reg, + #[doc = "0x1c - Identifies IEEE 802.1Q VLAN type frames"] + pub mac_vlan_tag: crate::Reg, + _reserved6: [u8; 0x04], + #[doc = "0x24 - Gives the status of the various internal blocks for debugging"] + pub mac_debug: crate::Reg, + _reserved7: [u8; 0x10], + #[doc = "0x38 - Contains the interrupt status"] + pub mac_intr_stat: crate::Reg, + #[doc = "0x3c - Contains the masks for generating interrupt"] + pub mac_intr_mask: crate::Reg, + #[doc = "0x40 - Contains the high 16-bits of the first MAC Address"] + pub mac_addr_h: crate::Reg, + #[doc = "0x44 - Contains the Low 32-bits of the first MAC Address"] + pub mac_addr_l: crate::Reg, + _reserved11: [u8; 0x94], + #[doc = "0xdc - Controls the watchdog time-out for received frames"] + pub mac_wdog_to: crate::Reg, + _reserved12: [u8; 0x20], + #[doc = "0x100 - MMC Control Register"] + pub mmc_cntrl: crate::Reg, + #[doc = "0x104 - MMC Receive Interrupt Register"] + pub mmc_intr_rx: crate::Reg, + #[doc = "0x108 - MMC Transmit Interrupt Register"] + pub mmc_intr_tx: crate::Reg, + #[doc = "0x10c - MMC Receive Interrupt Mask Register"] + pub mmc_intr_mask_rx: crate::Reg, + #[doc = "0x110 - MMC Transmit Interrupt Mask Register"] + pub mmc_intr_mask_tx: crate::Reg, + #[doc = "0x114 - MMC Transmit Count"] + pub txoctetcount_gb: crate::Reg, + #[doc = "0x118 - MMC Frame Count Register"] + pub txframecount_gb: crate::Reg, + #[doc = "0x11c - MMC Good Broadcast Frames Register"] + pub txbcastframes_g: crate::Reg, + #[doc = "0x120 - MMC Good Multicast Frames Register"] + pub txmcastframes_g: crate::Reg, + #[doc = "0x124 - MMC Good and bad Frames transmitted with length 64"] + pub tx64oct_gb: crate::Reg, + #[doc = "0x128 - MMC Good and bad Frames transmitted with length 65 to 127"] + pub tx65to127oct_gb: crate::Reg, + #[doc = "0x12c - MMC Good and bad Frames transmitted with length 128 to 255"] + pub tx128to255oct_gb: crate::Reg, + #[doc = "0x130 - MMC Good and bad Frames transmitted with length 256 to 511"] + pub tx256to511oct_gb: crate::Reg, + #[doc = "0x134 - MMC Good and bad Frames transmitted with length 512 to 1023"] + pub tx512to1023oct_gb: crate::Reg, + #[doc = "0x138 - MMC Good and bad Frames transmitted with length 1024 to max bytes"] + pub tx1024maxoct_gb: crate::Reg, + #[doc = "0x13c - MMC number of good and bad unicast frames transmitted"] + pub txucastframe_gb: crate::Reg, + #[doc = "0x140 - MMC number of good and bad MULTIcast frames transmitted"] + pub txmcastframe_gb: crate::Reg, + #[doc = "0x144 - MMC number of good and bad broadcast frames transmitted"] + pub txbcastframe_gb: crate::Reg, + #[doc = "0x148 - MMC number of frames aborted because of frame underflow error"] + pub txundererr: crate::Reg, + #[doc = "0x14c - MMC Number of successfully transmitted frames after a single collision"] + pub txsinglecol_g: crate::Reg, + #[doc = "0x150 - MMC Number of successfully transmitted frames after multiple collisions"] + pub txmulticol_g: crate::Reg, + #[doc = "0x154 - MMC Number of successfully transmitted frames after a deferral"] + pub txdeferred: crate::Reg, + #[doc = "0x158 - MMC Number of aborted frames because of late collision error"] + pub txlatecol: crate::Reg, + #[doc = "0x15c - MMC Number of aborted frames because of excessive collision errors"] + pub txexesscol: crate::Reg, + #[doc = "0x160 - MMC Number of aborted frames because of carrier sense error"] + pub txcarriererror: crate::Reg, + #[doc = "0x164 - MMC Number of bytes transmitted frames only in good frames"] + pub txoctetcount_g: crate::Reg, + #[doc = "0x168 - MMC Number of good frames transmitted"] + pub txframecount_g: crate::Reg, + #[doc = "0x16c - MMC Number of frames aborted because of excessive deferral error"] + pub txexcessdef: crate::Reg, + #[doc = "0x170 - MMC Number of good pause frames transmitted"] + pub txpauseframes: crate::Reg, + #[doc = "0x174 - MMC Number of good VLAN frames transmitted"] + pub txlanframes_g: crate::Reg, + #[doc = "0x178 - MMC Number of frames transmitted without errors"] + pub txoversize_g: crate::Reg, + _reserved43: [u8; 0x04], + #[doc = "0x180 - MMC Number of good and bad frames received"] + pub rxframecount_gb: crate::Reg, + #[doc = "0x184 - MMC Number of bytes received in good and bad frames"] + pub rxoctetcount_gb: crate::Reg, + #[doc = "0x188 - MMC Number of bytes received in good frames only"] + pub rxoctetcount_g: crate::Reg, + #[doc = "0x18c - MMC Number of good broadcast frames received"] + pub rxbcastframes_g: crate::Reg, + #[doc = "0x190 - MMC Number of good multicast frames received"] + pub rxmcastframes_g: crate::Reg, + #[doc = "0x194 - MMC Number of frames received with CRC error"] + pub rxcrcerror: crate::Reg, + #[doc = "0x198 - MMC Number of frames received with alignment error"] + pub rxalignerror: crate::Reg, + #[doc = "0x19c - MMC Number of frames received with runt error"] + pub rxrunterror: crate::Reg, + #[doc = "0x1a0 - MMC Number of giant frames received with length greater than 1518 bytes and with CRC error"] + pub rxjabbererror: crate::Reg, + #[doc = "0x1a4 - MMC Number of frames received with length less than 64 bytes"] + pub rxundersize_g: crate::Reg, + #[doc = "0x1a8 - MMC Number of frames received without errors with length greater than the max size"] + pub rxoversize_g: crate::Reg, + #[doc = "0x1ac - MMC Number of good and bad frames received with length 64 bytes"] + pub rx64octets_gb: crate::Reg, + #[doc = "0x1b0 - MMC Number of good and bad frames received with length between 65 and 127 bytes"] + pub rx65to127oct_gb: crate::Reg, + #[doc = "0x1b4 - MMC Number of good and bad frames received with length between 128 and 255 bytes"] + pub rx128to255oct_gb: crate::Reg, + #[doc = "0x1b8 - MMC Number of good and bad frames received with length between 256 and 511 bytes"] + pub rx256to511oct_gb: crate::Reg, + #[doc = "0x1bc - MMC Number of good and bad frames received with length between 512 and 1023 bytes"] + pub rx512to1023oct_gb: crate::Reg, + #[doc = "0x1c0 - MMC Number of good and bad frames received with length between 1024 and max size bytes"] + pub rx1024maxoct_gb: crate::Reg, + #[doc = "0x1c4 - MMC Number of received good unicast frames"] + pub rxucastframes_g: crate::Reg, + #[doc = "0x1c8 - MMC Number of frames received with length error"] + pub rxlengtherror: crate::Reg, + #[doc = "0x1cc - MMC Number of frames received with length field not equal to the valid frame size"] + pub rxoutrangetype: crate::Reg, + #[doc = "0x1d0 - MMC Number of good and valid Pause frames received"] + pub rxpauseframes: crate::Reg, + #[doc = "0x1d4 - MMC Number of missed received frames because of FIFO overflow"] + pub rxfifooverflow: crate::Reg, + #[doc = "0x1d8 - MMC Number of good and bad VLAN frames received"] + pub rxvlanframes_gb: crate::Reg, + #[doc = "0x1dc - MMC Number of frames received with error because of watchdog timeout error"] + pub rxwdogerror: crate::Reg, + #[doc = "0x1e0 - MMC Number of frames received with Receive error or Frame Extension error"] + pub rxrcverror: crate::Reg, + #[doc = "0x1e4 - MMC Number of received good control frames"] + pub rxctrlframes_g: crate::Reg, + _reserved69: [u8; 0x039c], + #[doc = "0x584 - Holds the VLAN Tag for insertion into or replacement in the transmit frames"] + pub vlan_increplace: crate::Reg, + #[doc = "0x588 - Holds the VLAN Hash Table"] + pub vlan_hashtable: crate::Reg, + _reserved71: [u8; 0x0174], + #[doc = "0x700 - Controls the IEEE 1588 timestamp generation and update logic"] + pub timestamp_ctrl: crate::Reg, + #[doc = "0x704 - Holds the 8-bit value by which the Sub-Second register is incremented"] + pub subsec_inc: crate::Reg, + #[doc = "0x708 - Holds the lower 32 bits of the second field of the system time"] + pub systime_seconds: crate::Reg, + #[doc = "0x70c - Holds 32 bits of the nano-second field of the system time"] + pub systime_nanosec: crate::Reg, + #[doc = "0x710 - Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value"] + pub systime_secsupdat: crate::Reg, + #[doc = "0x714 - Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value"] + pub systime_nsecup: crate::Reg, + #[doc = "0x718 - This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency"] + pub timestampaddend: crate::Reg, + #[doc = "0x71c - Holds the high 32-bits of time to be compared with the system time"] + pub target_time_secs: crate::Reg, + #[doc = "0x720 - Holds the lower 32-bits of time to be compared with the system time"] + pub target_time_nsec: crate::Reg, + _reserved80: [u8; 0x08dc], + #[doc = "0x1000 - Controls the DMA Host Interface Mode"] + pub dma_bus_mode: crate::Reg, + #[doc = "0x1004 - Used by the host to instruct the DMA to poll the transmit Descriptor list"] + pub dma_tx_poll_demand: crate::Reg, + #[doc = "0x1008 - Used by the host to instruct the DMA to poll the Receive Descriptor list"] + pub dma_rx_poll_demand: crate::Reg, + #[doc = "0x100c - Points the DMA to the start of the Receive Descriptor list"] + pub dma_rx_desc_list_addr: crate::Reg, + #[doc = "0x1010 - Points the DMA to the start of the Transmit Descriptor list"] + pub dma_tx_desc_list_addr: crate::Reg, + #[doc = "0x1014 - Used to determine the status of the DMA"] + pub dma_status: crate::Reg, + #[doc = "0x1018 - Sets the Receive and Transmit operation mode and command"] + pub dma_oper_mode: crate::Reg, + #[doc = "0x101c - Enables the interrupts reported in the status register"] + pub dma_intr_en: crate::Reg, + #[doc = "0x1020 - Contains the counters for discarded frames because no Receive Descriptor is available"] + pub dma_miss_over_counter: crate::Reg, + #[doc = "0x1024 - Watchdog timeout for Receive Interrupt from DMA"] + pub dma_rx_intr_wdog_timer: crate::Reg, + _reserved90: [u8; 0x04], + #[doc = "0x102c - Provides the active status of the read and write channels of the AHB master interface"] + pub dma_ahb_status: crate::Reg, + _reserved91: [u8; 0x18], + #[doc = "0x1048 - Contains the start address of the current Transmit Descriptor read by the DMA"] + pub dma_curr_tx_desc: crate::Reg, + #[doc = "0x104c - Contains the start address of the current Receive Descriptor read by the DMA"] + pub dma_curr_rx_desc: crate::Reg, + #[doc = "0x1050 - Contains the start address of the current Receive Descriptor read by the DMA"] + pub dma_curr_tx_bufr_addr: crate::Reg, + #[doc = "0x1054 - Contains the current Receive Buffer address read by the DMA"] + pub dma_curr_rx_bufr_addr: crate::Reg, +} +#[doc = "MAC_CONFIG register accessor: an alias for `Reg`"] +pub type MAC_CONFIG = crate::Reg; +#[doc = "Operation mode register for the MAC"] +pub mod mac_config; +#[doc = "MAC_FRAME_FLTR register accessor: an alias for `Reg`"] +pub type MAC_FRAME_FLTR = crate::Reg; +#[doc = "Contains the frame filtering controls"] +pub mod mac_frame_fltr; +#[doc = "MAC_GMII_ADDR register accessor: an alias for `Reg`"] +pub type MAC_GMII_ADDR = crate::Reg; +#[doc = "Controls the management cycles to an external PHY"] +pub mod mac_gmii_addr; +#[doc = "MAC_GMII_DATA register accessor: an alias for `Reg`"] +pub type MAC_GMII_DATA = crate::Reg; +#[doc = "Contains the data to be written to or read from the PHY register"] +pub mod mac_gmii_data; +#[doc = "MAC_FLOW_CTRL register accessor: an alias for `Reg`"] +pub type MAC_FLOW_CTRL = crate::Reg; +#[doc = "Controls the generation of control frames"] +pub mod mac_flow_ctrl; +#[doc = "MAC_VLAN_TAG register accessor: an alias for `Reg`"] +pub type MAC_VLAN_TAG = crate::Reg; +#[doc = "Identifies IEEE 802.1Q VLAN type frames"] +pub mod mac_vlan_tag; +#[doc = "MAC_DEBUG register accessor: an alias for `Reg`"] +pub type MAC_DEBUG = crate::Reg; +#[doc = "Gives the status of the various internal blocks for debugging"] +pub mod mac_debug; +#[doc = "MAC_INTR_STAT register accessor: an alias for `Reg`"] +pub type MAC_INTR_STAT = crate::Reg; +#[doc = "Contains the interrupt status"] +pub mod mac_intr_stat; +#[doc = "MAC_INTR_MASK register accessor: an alias for `Reg`"] +pub type MAC_INTR_MASK = crate::Reg; +#[doc = "Contains the masks for generating interrupt"] +pub mod mac_intr_mask; +#[doc = "MAC_ADDR_H register accessor: an alias for `Reg`"] +pub type MAC_ADDR_H = crate::Reg; +#[doc = "Contains the high 16-bits of the first MAC Address"] +pub mod mac_addr_h; +#[doc = "MAC_ADDR_L register accessor: an alias for `Reg`"] +pub type MAC_ADDR_L = crate::Reg; +#[doc = "Contains the Low 32-bits of the first MAC Address"] +pub mod mac_addr_l; +#[doc = "MAC_WDOG_TO register accessor: an alias for `Reg`"] +pub type MAC_WDOG_TO = crate::Reg; +#[doc = "Controls the watchdog time-out for received frames"] +pub mod mac_wdog_to; +#[doc = "MMC_CNTRL register accessor: an alias for `Reg`"] +pub type MMC_CNTRL = crate::Reg; +#[doc = "MMC Control Register"] +pub mod mmc_cntrl; +#[doc = "MMC_INTR_RX register accessor: an alias for `Reg`"] +pub type MMC_INTR_RX = crate::Reg; +#[doc = "MMC Receive Interrupt Register"] +pub mod mmc_intr_rx; +#[doc = "MMC_INTR_TX register accessor: an alias for `Reg`"] +pub type MMC_INTR_TX = crate::Reg; +#[doc = "MMC Transmit Interrupt Register"] +pub mod mmc_intr_tx; +#[doc = "MMC_INTR_MASK_RX register accessor: an alias for `Reg`"] +pub type MMC_INTR_MASK_RX = crate::Reg; +#[doc = "MMC Receive Interrupt Mask Register"] +pub mod mmc_intr_mask_rx; +#[doc = "MMC_INTR_MASK_TX register accessor: an alias for `Reg`"] +pub type MMC_INTR_MASK_TX = crate::Reg; +#[doc = "MMC Transmit Interrupt Mask Register"] +pub mod mmc_intr_mask_tx; +#[doc = "TXOCTETCOUNT_GB register accessor: an alias for `Reg`"] +pub type TXOCTETCOUNT_GB = crate::Reg; +#[doc = "MMC Transmit Count"] +pub mod txoctetcount_gb; +#[doc = "TXFRAMECOUNT_GB register accessor: an alias for `Reg`"] +pub type TXFRAMECOUNT_GB = crate::Reg; +#[doc = "MMC Frame Count Register"] +pub mod txframecount_gb; +#[doc = "TXBCASTFRAMES_G register accessor: an alias for `Reg`"] +pub type TXBCASTFRAMES_G = crate::Reg; +#[doc = "MMC Good Broadcast Frames Register"] +pub mod txbcastframes_g; +#[doc = "TXMCASTFRAMES_G register accessor: an alias for `Reg`"] +pub type TXMCASTFRAMES_G = crate::Reg; +#[doc = "MMC Good Multicast Frames Register"] +pub mod txmcastframes_g; +#[doc = "TX64OCT_GB register accessor: an alias for `Reg`"] +pub type TX64OCT_GB = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 64"] +pub mod tx64oct_gb; +#[doc = "TX65TO127OCT_GB register accessor: an alias for `Reg`"] +pub type TX65TO127OCT_GB = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 65 to 127"] +pub mod tx65to127oct_gb; +#[doc = "TX128TO255OCT_GB register accessor: an alias for `Reg`"] +pub type TX128TO255OCT_GB = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 128 to 255"] +pub mod tx128to255oct_gb; +#[doc = "TX256TO511OCT_GB register accessor: an alias for `Reg`"] +pub type TX256TO511OCT_GB = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 256 to 511"] +pub mod tx256to511oct_gb; +#[doc = "TX512TO1023OCT_GB register accessor: an alias for `Reg`"] +pub type TX512TO1023OCT_GB = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 512 to 1023"] +pub mod tx512to1023oct_gb; +#[doc = "TX1024MAXOCT_GB register accessor: an alias for `Reg`"] +pub type TX1024MAXOCT_GB = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 1024 to max bytes"] +pub mod tx1024maxoct_gb; +#[doc = "TXUCASTFRAME_GB register accessor: an alias for `Reg`"] +pub type TXUCASTFRAME_GB = crate::Reg; +#[doc = "MMC number of good and bad unicast frames transmitted"] +pub mod txucastframe_gb; +#[doc = "TXMCASTFRAME_GB register accessor: an alias for `Reg`"] +pub type TXMCASTFRAME_GB = crate::Reg; +#[doc = "MMC number of good and bad MULTIcast frames transmitted"] +pub mod txmcastframe_gb; +#[doc = "TXBCASTFRAME_GB register accessor: an alias for `Reg`"] +pub type TXBCASTFRAME_GB = crate::Reg; +#[doc = "MMC number of good and bad broadcast frames transmitted"] +pub mod txbcastframe_gb; +#[doc = "TXUNDERERR register accessor: an alias for `Reg`"] +pub type TXUNDERERR = crate::Reg; +#[doc = "MMC number of frames aborted because of frame underflow error"] +pub mod txundererr; +#[doc = "TXSINGLECOL_G register accessor: an alias for `Reg`"] +pub type TXSINGLECOL_G = crate::Reg; +#[doc = "MMC Number of successfully transmitted frames after a single collision"] +pub mod txsinglecol_g; +#[doc = "TXMULTICOL_G register accessor: an alias for `Reg`"] +pub type TXMULTICOL_G = crate::Reg; +#[doc = "MMC Number of successfully transmitted frames after multiple collisions"] +pub mod txmulticol_g; +#[doc = "TXDEFERRED register accessor: an alias for `Reg`"] +pub type TXDEFERRED = crate::Reg; +#[doc = "MMC Number of successfully transmitted frames after a deferral"] +pub mod txdeferred; +#[doc = "TXLATECOL register accessor: an alias for `Reg`"] +pub type TXLATECOL = crate::Reg; +#[doc = "MMC Number of aborted frames because of late collision error"] +pub mod txlatecol; +#[doc = "TXEXESSCOL register accessor: an alias for `Reg`"] +pub type TXEXESSCOL = crate::Reg; +#[doc = "MMC Number of aborted frames because of excessive collision errors"] +pub mod txexesscol; +#[doc = "TXCARRIERERROR register accessor: an alias for `Reg`"] +pub type TXCARRIERERROR = crate::Reg; +#[doc = "MMC Number of aborted frames because of carrier sense error"] +pub mod txcarriererror; +#[doc = "TXOCTETCOUNT_G register accessor: an alias for `Reg`"] +pub type TXOCTETCOUNT_G = crate::Reg; +#[doc = "MMC Number of bytes transmitted frames only in good frames"] +pub mod txoctetcount_g; +#[doc = "TXFRAMECOUNT_G register accessor: an alias for `Reg`"] +pub type TXFRAMECOUNT_G = crate::Reg; +#[doc = "MMC Number of good frames transmitted"] +pub mod txframecount_g; +#[doc = "TXEXCESSDEF register accessor: an alias for `Reg`"] +pub type TXEXCESSDEF = crate::Reg; +#[doc = "MMC Number of frames aborted because of excessive deferral error"] +pub mod txexcessdef; +#[doc = "TXPAUSEFRAMES register accessor: an alias for `Reg`"] +pub type TXPAUSEFRAMES = crate::Reg; +#[doc = "MMC Number of good pause frames transmitted"] +pub mod txpauseframes; +#[doc = "TXLANFRAMES_G register accessor: an alias for `Reg`"] +pub type TXLANFRAMES_G = crate::Reg; +#[doc = "MMC Number of good VLAN frames transmitted"] +pub mod txlanframes_g; +#[doc = "TXOVERSIZE_G register accessor: an alias for `Reg`"] +pub type TXOVERSIZE_G = crate::Reg; +#[doc = "MMC Number of frames transmitted without errors"] +pub mod txoversize_g; +#[doc = "RXFRAMECOUNT_GB register accessor: an alias for `Reg`"] +pub type RXFRAMECOUNT_GB = crate::Reg; +#[doc = "MMC Number of good and bad frames received"] +pub mod rxframecount_gb; +#[doc = "RXOCTETCOUNT_GB register accessor: an alias for `Reg`"] +pub type RXOCTETCOUNT_GB = crate::Reg; +#[doc = "MMC Number of bytes received in good and bad frames"] +pub mod rxoctetcount_gb; +#[doc = "RXOCTETCOUNT_G register accessor: an alias for `Reg`"] +pub type RXOCTETCOUNT_G = crate::Reg; +#[doc = "MMC Number of bytes received in good frames only"] +pub mod rxoctetcount_g; +#[doc = "RXBCASTFRAMES_G register accessor: an alias for `Reg`"] +pub type RXBCASTFRAMES_G = crate::Reg; +#[doc = "MMC Number of good broadcast frames received"] +pub mod rxbcastframes_g; +#[doc = "RXMCASTFRAMES_G register accessor: an alias for `Reg`"] +pub type RXMCASTFRAMES_G = crate::Reg; +#[doc = "MMC Number of good multicast frames received"] +pub mod rxmcastframes_g; +#[doc = "RXCRCERROR register accessor: an alias for `Reg`"] +pub type RXCRCERROR = crate::Reg; +#[doc = "MMC Number of frames received with CRC error"] +pub mod rxcrcerror; +#[doc = "RXALIGNERROR register accessor: an alias for `Reg`"] +pub type RXALIGNERROR = crate::Reg; +#[doc = "MMC Number of frames received with alignment error"] +pub mod rxalignerror; +#[doc = "RXRUNTERROR register accessor: an alias for `Reg`"] +pub type RXRUNTERROR = crate::Reg; +#[doc = "MMC Number of frames received with runt error"] +pub mod rxrunterror; +#[doc = "RXJABBERERROR register accessor: an alias for `Reg`"] +pub type RXJABBERERROR = crate::Reg; +#[doc = "MMC Number of giant frames received with length greater than 1518 bytes and with CRC error"] +pub mod rxjabbererror; +#[doc = "RXUNDERSIZE_G register accessor: an alias for `Reg`"] +pub type RXUNDERSIZE_G = crate::Reg; +#[doc = "MMC Number of frames received with length less than 64 bytes"] +pub mod rxundersize_g; +#[doc = "RXOVERSIZE_G register accessor: an alias for `Reg`"] +pub type RXOVERSIZE_G = crate::Reg; +#[doc = "MMC Number of frames received without errors with length greater than the max size"] +pub mod rxoversize_g; +#[doc = "RX64OCTETS_GB register accessor: an alias for `Reg`"] +pub type RX64OCTETS_GB = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length 64 bytes"] +pub mod rx64octets_gb; +#[doc = "RX65TO127OCT_GB register accessor: an alias for `Reg`"] +pub type RX65TO127OCT_GB = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 65 and 127 bytes"] +pub mod rx65to127oct_gb; +#[doc = "RX128TO255OCT_GB register accessor: an alias for `Reg`"] +pub type RX128TO255OCT_GB = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 128 and 255 bytes"] +pub mod rx128to255oct_gb; +#[doc = "RX256TO511OCT_GB register accessor: an alias for `Reg`"] +pub type RX256TO511OCT_GB = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 256 and 511 bytes"] +pub mod rx256to511oct_gb; +#[doc = "RX512TO1023OCT_GB register accessor: an alias for `Reg`"] +pub type RX512TO1023OCT_GB = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 512 and 1023 bytes"] +pub mod rx512to1023oct_gb; +#[doc = "RX1024MAXOCT_GB register accessor: an alias for `Reg`"] +pub type RX1024MAXOCT_GB = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 1024 and max size bytes"] +pub mod rx1024maxoct_gb; +#[doc = "RXUCASTFRAMES_G register accessor: an alias for `Reg`"] +pub type RXUCASTFRAMES_G = crate::Reg; +#[doc = "MMC Number of received good unicast frames"] +pub mod rxucastframes_g; +#[doc = "RXLENGTHERROR register accessor: an alias for `Reg`"] +pub type RXLENGTHERROR = crate::Reg; +#[doc = "MMC Number of frames received with length error"] +pub mod rxlengtherror; +#[doc = "RXOUTRANGETYPE register accessor: an alias for `Reg`"] +pub type RXOUTRANGETYPE = crate::Reg; +#[doc = "MMC Number of frames received with length field not equal to the valid frame size"] +pub mod rxoutrangetype; +#[doc = "RXPAUSEFRAMES register accessor: an alias for `Reg`"] +pub type RXPAUSEFRAMES = crate::Reg; +#[doc = "MMC Number of good and valid Pause frames received"] +pub mod rxpauseframes; +#[doc = "RXFIFOOVERFLOW register accessor: an alias for `Reg`"] +pub type RXFIFOOVERFLOW = crate::Reg; +#[doc = "MMC Number of missed received frames because of FIFO overflow"] +pub mod rxfifooverflow; +#[doc = "RXVLANFRAMES_GB register accessor: an alias for `Reg`"] +pub type RXVLANFRAMES_GB = crate::Reg; +#[doc = "MMC Number of good and bad VLAN frames received"] +pub mod rxvlanframes_gb; +#[doc = "RXWDOGERROR register accessor: an alias for `Reg`"] +pub type RXWDOGERROR = crate::Reg; +#[doc = "MMC Number of frames received with error because of watchdog timeout error"] +pub mod rxwdogerror; +#[doc = "RXRCVERROR register accessor: an alias for `Reg`"] +pub type RXRCVERROR = crate::Reg; +#[doc = "MMC Number of frames received with Receive error or Frame Extension error"] +pub mod rxrcverror; +#[doc = "RXCTRLFRAMES_G register accessor: an alias for `Reg`"] +pub type RXCTRLFRAMES_G = crate::Reg; +#[doc = "MMC Number of received good control frames"] +pub mod rxctrlframes_g; +#[doc = "VLAN_INCREPLACE register accessor: an alias for `Reg`"] +pub type VLAN_INCREPLACE = crate::Reg; +#[doc = "Holds the VLAN Tag for insertion into or replacement in the transmit frames"] +pub mod vlan_increplace; +#[doc = "VLAN_HASHTABLE register accessor: an alias for `Reg`"] +pub type VLAN_HASHTABLE = crate::Reg; +#[doc = "Holds the VLAN Hash Table"] +pub mod vlan_hashtable; +#[doc = "TIMESTAMP_CTRL register accessor: an alias for `Reg`"] +pub type TIMESTAMP_CTRL = crate::Reg; +#[doc = "Controls the IEEE 1588 timestamp generation and update logic"] +pub mod timestamp_ctrl; +#[doc = "SUBSEC_INC register accessor: an alias for `Reg`"] +pub type SUBSEC_INC = crate::Reg; +#[doc = "Holds the 8-bit value by which the Sub-Second register is incremented"] +pub mod subsec_inc; +#[doc = "SYSTIME_SECONDS register accessor: an alias for `Reg`"] +pub type SYSTIME_SECONDS = crate::Reg; +#[doc = "Holds the lower 32 bits of the second field of the system time"] +pub mod systime_seconds; +#[doc = "SYSTIME_NANOSEC register accessor: an alias for `Reg`"] +pub type SYSTIME_NANOSEC = crate::Reg; +#[doc = "Holds 32 bits of the nano-second field of the system time"] +pub mod systime_nanosec; +#[doc = "SYSTIME_SECSUPDAT register accessor: an alias for `Reg`"] +pub type SYSTIME_SECSUPDAT = crate::Reg; +#[doc = "Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value"] +pub mod systime_secsupdat; +#[doc = "SYSTIME_NSECUP register accessor: an alias for `Reg`"] +pub type SYSTIME_NSECUP = crate::Reg; +#[doc = "Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value"] +pub mod systime_nsecup; +#[doc = "TIMESTAMPADDEND register accessor: an alias for `Reg`"] +pub type TIMESTAMPADDEND = crate::Reg; +#[doc = "This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency"] +pub mod timestampaddend; +#[doc = "TARGET_TIME_SECS register accessor: an alias for `Reg`"] +pub type TARGET_TIME_SECS = crate::Reg; +#[doc = "Holds the high 32-bits of time to be compared with the system time"] +pub mod target_time_secs; +#[doc = "TARGET_TIME_NSEC register accessor: an alias for `Reg`"] +pub type TARGET_TIME_NSEC = crate::Reg; +#[doc = "Holds the lower 32-bits of time to be compared with the system time"] +pub mod target_time_nsec; +#[doc = "DMA_BUS_MODE register accessor: an alias for `Reg`"] +pub type DMA_BUS_MODE = crate::Reg; +#[doc = "Controls the DMA Host Interface Mode"] +pub mod dma_bus_mode; +#[doc = "DMA_TX_POLL_DEMAND register accessor: an alias for `Reg`"] +pub type DMA_TX_POLL_DEMAND = crate::Reg; +#[doc = "Used by the host to instruct the DMA to poll the transmit Descriptor list"] +pub mod dma_tx_poll_demand; +#[doc = "DMA_RX_POLL_DEMAND register accessor: an alias for `Reg`"] +pub type DMA_RX_POLL_DEMAND = crate::Reg; +#[doc = "Used by the host to instruct the DMA to poll the Receive Descriptor list"] +pub mod dma_rx_poll_demand; +#[doc = "DMA_RX_DESC_LIST_ADDR register accessor: an alias for `Reg`"] +pub type DMA_RX_DESC_LIST_ADDR = crate::Reg; +#[doc = "Points the DMA to the start of the Receive Descriptor list"] +pub mod dma_rx_desc_list_addr; +#[doc = "DMA_TX_DESC_LIST_ADDR register accessor: an alias for `Reg`"] +pub type DMA_TX_DESC_LIST_ADDR = crate::Reg; +#[doc = "Points the DMA to the start of the Transmit Descriptor list"] +pub mod dma_tx_desc_list_addr; +#[doc = "DMA_STATUS register accessor: an alias for `Reg`"] +pub type DMA_STATUS = crate::Reg; +#[doc = "Used to determine the status of the DMA"] +pub mod dma_status; +#[doc = "DMA_OPER_MODE register accessor: an alias for `Reg`"] +pub type DMA_OPER_MODE = crate::Reg; +#[doc = "Sets the Receive and Transmit operation mode and command"] +pub mod dma_oper_mode; +#[doc = "DMA_INTR_EN register accessor: an alias for `Reg`"] +pub type DMA_INTR_EN = crate::Reg; +#[doc = "Enables the interrupts reported in the status register"] +pub mod dma_intr_en; +#[doc = "DMA_MISS_OVER_COUNTER register accessor: an alias for `Reg`"] +pub type DMA_MISS_OVER_COUNTER = crate::Reg; +#[doc = "Contains the counters for discarded frames because no Receive Descriptor is available"] +pub mod dma_miss_over_counter; +#[doc = "DMA_RX_INTR_WDOG_TIMER register accessor: an alias for `Reg`"] +pub type DMA_RX_INTR_WDOG_TIMER = crate::Reg; +#[doc = "Watchdog timeout for Receive Interrupt from DMA"] +pub mod dma_rx_intr_wdog_timer; +#[doc = "DMA_AHB_STATUS register accessor: an alias for `Reg`"] +pub type DMA_AHB_STATUS = crate::Reg; +#[doc = "Provides the active status of the read and write channels of the AHB master interface"] +pub mod dma_ahb_status; +#[doc = "DMA_CURR_TX_DESC register accessor: an alias for `Reg`"] +pub type DMA_CURR_TX_DESC = crate::Reg; +#[doc = "Contains the start address of the current Transmit Descriptor read by the DMA"] +pub mod dma_curr_tx_desc; +#[doc = "DMA_CURR_RX_DESC register accessor: an alias for `Reg`"] +pub type DMA_CURR_RX_DESC = crate::Reg; +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA"] +pub mod dma_curr_rx_desc; +#[doc = "DMA_CURR_TX_BUFR_ADDR register accessor: an alias for `Reg`"] +pub type DMA_CURR_TX_BUFR_ADDR = crate::Reg; +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA"] +pub mod dma_curr_tx_bufr_addr; +#[doc = "DMA_CURR_RX_BUFR_ADDR register accessor: an alias for `Reg`"] +pub type DMA_CURR_RX_BUFR_ADDR = crate::Reg; +#[doc = "Contains the current Receive Buffer address read by the DMA"] +pub mod dma_curr_rx_bufr_addr; diff --git a/src/eth/dma_ahb_status.rs b/src/eth/dma_ahb_status.rs new file mode 100644 index 0000000..b1bf946 --- /dev/null +++ b/src/eth/dma_ahb_status.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DMA_AHB_STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_AHB_STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AHBMASTRSTS` reader - When high, indicates that the AHB master interface FSMs are in the non-idle state"] +pub struct AHBMASTRSTS_R(crate::FieldReader); +impl AHBMASTRSTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AHBMASTRSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AHBMASTRSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AHBMASTRSTS` writer - When high, indicates that the AHB master interface FSMs are in the non-idle state"] +pub struct AHBMASTRSTS_W<'a> { + w: &'a mut W, +} +impl<'a> AHBMASTRSTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - When high, indicates that the AHB master interface FSMs are in the non-idle state"] + #[inline(always)] + pub fn ahbmastrsts(&self) -> AHBMASTRSTS_R { + AHBMASTRSTS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - When high, indicates that the AHB master interface FSMs are in the non-idle state"] + #[inline(always)] + pub fn ahbmastrsts(&mut self) -> AHBMASTRSTS_W { + AHBMASTRSTS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Provides the active status of the read and write channels of the AHB master interface\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_ahb_status](index.html) module"] +pub struct DMA_AHB_STATUS_SPEC; +impl crate::RegisterSpec for DMA_AHB_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_ahb_status::R](R) reader structure"] +impl crate::Readable for DMA_AHB_STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_ahb_status::W](W) writer structure"] +impl crate::Writable for DMA_AHB_STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_AHB_STATUS to value 0"] +impl crate::Resettable for DMA_AHB_STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_bus_mode.rs b/src/eth/dma_bus_mode.rs new file mode 100644 index 0000000..cd6bd5c --- /dev/null +++ b/src/eth/dma_bus_mode.rs @@ -0,0 +1,674 @@ +#[doc = "Register `DMA_BUS_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_BUS_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RIB` reader - Rebuild INCRx Burst"] +pub struct RIB_R(crate::FieldReader); +impl RIB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RIB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RIB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RIB` writer - Rebuild INCRx Burst"] +pub struct RIB_W<'a> { + w: &'a mut W, +} +impl<'a> RIB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +#[doc = "Field `PRWG` reader - Channel Priority Weights"] +pub struct PRWG_R(crate::FieldReader); +impl PRWG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRWG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRWG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRWG` writer - Channel Priority Weights"] +pub struct PRWG_W<'a> { + w: &'a mut W, +} +impl<'a> PRWG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `TXPR` reader - Transmit Priority"] +pub struct TXPR_R(crate::FieldReader); +impl TXPR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXPR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXPR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPR` writer - Transmit Priority"] +pub struct TXPR_W<'a> { + w: &'a mut W, +} +impl<'a> TXPR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `MB` reader - Mixed Burst"] +pub struct MB_R(crate::FieldReader); +impl MB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Mixed Burst"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `AAL` reader - Address-Aligned Beats"] +pub struct AAL_R(crate::FieldReader); +impl AAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AAL` writer - Address-Aligned Beats"] +pub struct AAL_W<'a> { + w: &'a mut W, +} +impl<'a> AAL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `PBLx8` reader - PBLx8 Mode"] +pub struct PBLX8_R(crate::FieldReader); +impl PBLX8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PBLX8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PBLX8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PBLx8` writer - PBLx8 Mode"] +pub struct PBLX8_W<'a> { + w: &'a mut W, +} +impl<'a> PBLX8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `USP` reader - Use Separate PBL"] +pub struct USP_R(crate::FieldReader); +impl USP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + USP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for USP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `USP` writer - Use Separate PBL"] +pub struct USP_W<'a> { + w: &'a mut W, +} +impl<'a> USP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `RPBL` reader - Rx DMA PBL"] +pub struct RPBL_R(crate::FieldReader); +impl RPBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RPBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RPBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RPBL` writer - Rx DMA PBL"] +pub struct RPBL_W<'a> { + w: &'a mut W, +} +impl<'a> RPBL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 17)) | ((value as u32 & 0x3f) << 17); + self.w + } +} +#[doc = "Field `FB` reader - Fixed Burste"] +pub struct FB_R(crate::FieldReader); +impl FB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FB` writer - Fixed Burste"] +pub struct FB_W<'a> { + w: &'a mut W, +} +impl<'a> FB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `PR` reader - Priority Ratio"] +pub struct PR_R(crate::FieldReader); +impl PR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PR` writer - Priority Ratio"] +pub struct PR_W<'a> { + w: &'a mut W, +} +impl<'a> PR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `PBL` reader - Programmable Burst Lengthe"] +pub struct PBL_R(crate::FieldReader); +impl PBL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PBL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PBL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PBL` writer - Programmable Burst Lengthe"] +pub struct PBL_W<'a> { + w: &'a mut W, +} +impl<'a> PBL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Field `DSL` reader - Descriptor Skip Length"] +pub struct DSL_R(crate::FieldReader); +impl DSL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSL` writer - Descriptor Skip Length"] +pub struct DSL_W<'a> { + w: &'a mut W, +} +impl<'a> DSL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 2)) | ((value as u32 & 0x1f) << 2); + self.w + } +} +#[doc = "Field `DA` reader - DMA Arbitration Scheme"] +pub struct DA_R(crate::FieldReader); +impl DA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DA` writer - DMA Arbitration Scheme"] +pub struct DA_W<'a> { + w: &'a mut W, +} +impl<'a> DA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWR` reader - Software Reset (Read, Write Set, and Self Clear)"] +pub struct SWR_R(crate::FieldReader); +impl SWR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SWR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWR` writer - Software Reset (Read, Write Set, and Self Clear)"] +pub struct SWR_W<'a> { + w: &'a mut W, +} +impl<'a> SWR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 31 - Rebuild INCRx Burst"] + #[inline(always)] + pub fn rib(&self) -> RIB_R { + RIB_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Channel Priority Weights"] + #[inline(always)] + pub fn prwg(&self) -> PRWG_R { + PRWG_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 27 - Transmit Priority"] + #[inline(always)] + pub fn txpr(&self) -> TXPR_R { + TXPR_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 26 - Mixed Burst"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 25 - Address-Aligned Beats"] + #[inline(always)] + pub fn aal(&self) -> AAL_R { + AAL_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 24 - PBLx8 Mode"] + #[inline(always)] + pub fn pblx8(&self) -> PBLX8_R { + PBLX8_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 23 - Use Separate PBL"] + #[inline(always)] + pub fn usp(&self) -> USP_R { + USP_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 17:22 - Rx DMA PBL"] + #[inline(always)] + pub fn rpbl(&self) -> RPBL_R { + RPBL_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bit 16 - Fixed Burste"] + #[inline(always)] + pub fn fb(&self) -> FB_R { + FB_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Priority Ratio"] + #[inline(always)] + pub fn pr(&self) -> PR_R { + PR_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Programmable Burst Lengthe"] + #[inline(always)] + pub fn pbl(&self) -> PBL_R { + PBL_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 2:6 - Descriptor Skip Length"] + #[inline(always)] + pub fn dsl(&self) -> DSL_R { + DSL_R::new(((self.bits >> 2) & 0x1f) as u8) + } + #[doc = "Bit 1 - DMA Arbitration Scheme"] + #[inline(always)] + pub fn da(&self) -> DA_R { + DA_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Software Reset (Read, Write Set, and Self Clear)"] + #[inline(always)] + pub fn swr(&self) -> SWR_R { + SWR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 31 - Rebuild INCRx Burst"] + #[inline(always)] + pub fn rib(&mut self) -> RIB_W { + RIB_W { w: self } + } + #[doc = "Bits 28:29 - Channel Priority Weights"] + #[inline(always)] + pub fn prwg(&mut self) -> PRWG_W { + PRWG_W { w: self } + } + #[doc = "Bit 27 - Transmit Priority"] + #[inline(always)] + pub fn txpr(&mut self) -> TXPR_W { + TXPR_W { w: self } + } + #[doc = "Bit 26 - Mixed Burst"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 25 - Address-Aligned Beats"] + #[inline(always)] + pub fn aal(&mut self) -> AAL_W { + AAL_W { w: self } + } + #[doc = "Bit 24 - PBLx8 Mode"] + #[inline(always)] + pub fn pblx8(&mut self) -> PBLX8_W { + PBLX8_W { w: self } + } + #[doc = "Bit 23 - Use Separate PBL"] + #[inline(always)] + pub fn usp(&mut self) -> USP_W { + USP_W { w: self } + } + #[doc = "Bits 17:22 - Rx DMA PBL"] + #[inline(always)] + pub fn rpbl(&mut self) -> RPBL_W { + RPBL_W { w: self } + } + #[doc = "Bit 16 - Fixed Burste"] + #[inline(always)] + pub fn fb(&mut self) -> FB_W { + FB_W { w: self } + } + #[doc = "Bits 14:15 - Priority Ratio"] + #[inline(always)] + pub fn pr(&mut self) -> PR_W { + PR_W { w: self } + } + #[doc = "Bits 8:13 - Programmable Burst Lengthe"] + #[inline(always)] + pub fn pbl(&mut self) -> PBL_W { + PBL_W { w: self } + } + #[doc = "Bits 2:6 - Descriptor Skip Length"] + #[inline(always)] + pub fn dsl(&mut self) -> DSL_W { + DSL_W { w: self } + } + #[doc = "Bit 1 - DMA Arbitration Scheme"] + #[inline(always)] + pub fn da(&mut self) -> DA_W { + DA_W { w: self } + } + #[doc = "Bit 0 - Software Reset (Read, Write Set, and Self Clear)"] + #[inline(always)] + pub fn swr(&mut self) -> SWR_W { + SWR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Controls the DMA Host Interface Mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_bus_mode](index.html) module"] +pub struct DMA_BUS_MODE_SPEC; +impl crate::RegisterSpec for DMA_BUS_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_bus_mode::R](R) reader structure"] +impl crate::Readable for DMA_BUS_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_bus_mode::W](W) writer structure"] +impl crate::Writable for DMA_BUS_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_BUS_MODE to value 0x0002_0101"] +impl crate::Resettable for DMA_BUS_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0002_0101 + } +} diff --git a/src/eth/dma_curr_rx_bufr_addr.rs b/src/eth/dma_curr_rx_bufr_addr.rs new file mode 100644 index 0000000..4425eff --- /dev/null +++ b/src/eth/dma_curr_rx_bufr_addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMA_CURR_RX_BUFR_ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_CURR_RX_BUFR_ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURTBUFAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub struct CURTBUFAPTR_R(crate::FieldReader); +impl CURTBUFAPTR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURTBUFAPTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURTBUFAPTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURTBUFAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub struct CURTBUFAPTR_W<'a> { + w: &'a mut W, +} +impl<'a> CURTBUFAPTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&self) -> CURTBUFAPTR_R { + CURTBUFAPTR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&mut self) -> CURTBUFAPTR_W { + CURTBUFAPTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the current Receive Buffer address read by the DMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_curr_rx_bufr_addr](index.html) module"] +pub struct DMA_CURR_RX_BUFR_ADDR_SPEC; +impl crate::RegisterSpec for DMA_CURR_RX_BUFR_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_curr_rx_bufr_addr::R](R) reader structure"] +impl crate::Readable for DMA_CURR_RX_BUFR_ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_curr_rx_bufr_addr::W](W) writer structure"] +impl crate::Writable for DMA_CURR_RX_BUFR_ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_CURR_RX_BUFR_ADDR to value 0"] +impl crate::Resettable for DMA_CURR_RX_BUFR_ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_curr_rx_desc.rs b/src/eth/dma_curr_rx_desc.rs new file mode 100644 index 0000000..ab76a2f --- /dev/null +++ b/src/eth/dma_curr_rx_desc.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMA_CURR_RX_DESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_CURR_RX_DESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURRDESAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub struct CURRDESAPTR_R(crate::FieldReader); +impl CURRDESAPTR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURRDESAPTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURRDESAPTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURRDESAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub struct CURRDESAPTR_W<'a> { + w: &'a mut W, +} +impl<'a> CURRDESAPTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn currdesaptr(&self) -> CURRDESAPTR_R { + CURRDESAPTR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn currdesaptr(&mut self) -> CURRDESAPTR_W { + CURRDESAPTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_curr_rx_desc](index.html) module"] +pub struct DMA_CURR_RX_DESC_SPEC; +impl crate::RegisterSpec for DMA_CURR_RX_DESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_curr_rx_desc::R](R) reader structure"] +impl crate::Readable for DMA_CURR_RX_DESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_curr_rx_desc::W](W) writer structure"] +impl crate::Writable for DMA_CURR_RX_DESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_CURR_RX_DESC to value 0"] +impl crate::Resettable for DMA_CURR_RX_DESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_curr_tx_bufr_addr.rs b/src/eth/dma_curr_tx_bufr_addr.rs new file mode 100644 index 0000000..788c758 --- /dev/null +++ b/src/eth/dma_curr_tx_bufr_addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMA_CURR_TX_BUFR_ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_CURR_TX_BUFR_ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURTBUFAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub struct CURTBUFAPTR_R(crate::FieldReader); +impl CURTBUFAPTR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURTBUFAPTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURTBUFAPTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURTBUFAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub struct CURTBUFAPTR_W<'a> { + w: &'a mut W, +} +impl<'a> CURTBUFAPTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&self) -> CURTBUFAPTR_R { + CURTBUFAPTR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&mut self) -> CURTBUFAPTR_W { + CURTBUFAPTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_curr_tx_bufr_addr](index.html) module"] +pub struct DMA_CURR_TX_BUFR_ADDR_SPEC; +impl crate::RegisterSpec for DMA_CURR_TX_BUFR_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_curr_tx_bufr_addr::R](R) reader structure"] +impl crate::Readable for DMA_CURR_TX_BUFR_ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_curr_tx_bufr_addr::W](W) writer structure"] +impl crate::Writable for DMA_CURR_TX_BUFR_ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_CURR_TX_BUFR_ADDR to value 0"] +impl crate::Resettable for DMA_CURR_TX_BUFR_ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_curr_tx_desc.rs b/src/eth/dma_curr_tx_desc.rs new file mode 100644 index 0000000..1382b75 --- /dev/null +++ b/src/eth/dma_curr_tx_desc.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMA_CURR_TX_DESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_CURR_TX_DESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CURTDESAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub struct CURTDESAPTR_R(crate::FieldReader); +impl CURTDESAPTR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CURTDESAPTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CURTDESAPTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CURTDESAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub struct CURTDESAPTR_W<'a> { + w: &'a mut W, +} +impl<'a> CURTDESAPTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtdesaptr(&self) -> CURTDESAPTR_R { + CURTDESAPTR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtdesaptr(&mut self) -> CURTDESAPTR_W { + CURTDESAPTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the start address of the current Transmit Descriptor read by the DMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_curr_tx_desc](index.html) module"] +pub struct DMA_CURR_TX_DESC_SPEC; +impl crate::RegisterSpec for DMA_CURR_TX_DESC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_curr_tx_desc::R](R) reader structure"] +impl crate::Readable for DMA_CURR_TX_DESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_curr_tx_desc::W](W) writer structure"] +impl crate::Writable for DMA_CURR_TX_DESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_CURR_TX_DESC to value 0"] +impl crate::Resettable for DMA_CURR_TX_DESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_intr_en.rs b/src/eth/dma_intr_en.rs new file mode 100644 index 0000000..67a3818 --- /dev/null +++ b/src/eth/dma_intr_en.rs @@ -0,0 +1,771 @@ +#[doc = "Register `DMA_INTR_EN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_INTR_EN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NIE` reader - Normal Interrupt Summary Enable"] +pub struct NIE_R(crate::FieldReader); +impl NIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NIE` writer - Normal Interrupt Summary Enable"] +pub struct NIE_W<'a> { + w: &'a mut W, +} +impl<'a> NIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `AIE` reader - Abnormal Interrupt Summary Enable"] +pub struct AIE_R(crate::FieldReader); +impl AIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AIE` writer - Abnormal Interrupt Summary Enable"] +pub struct AIE_W<'a> { + w: &'a mut W, +} +impl<'a> AIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ERE` reader - Early Receive Interrupt Enable"] +pub struct ERE_R(crate::FieldReader); +impl ERE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERE` writer - Early Receive Interrupt Enable"] +pub struct ERE_W<'a> { + w: &'a mut W, +} +impl<'a> ERE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `FBE` reader - Fatal Bus Error Enable"] +pub struct FBE_R(crate::FieldReader); +impl FBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FBE` writer - Fatal Bus Error Enable"] +pub struct FBE_W<'a> { + w: &'a mut W, +} +impl<'a> FBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `ETE` reader - Early Transmit Interrupt Enable"] +pub struct ETE_R(crate::FieldReader); +impl ETE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ETE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ETE` writer - Early Transmit Interrupt Enable"] +pub struct ETE_W<'a> { + w: &'a mut W, +} +impl<'a> ETE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `RWE` reader - Receive Watchdog Timeout Enable"] +pub struct RWE_R(crate::FieldReader); +impl RWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWE` writer - Receive Watchdog Timeout Enable"] +pub struct RWE_W<'a> { + w: &'a mut W, +} +impl<'a> RWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `RSE` reader - Receive Stopped Enable"] +pub struct RSE_R(crate::FieldReader); +impl RSE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSE` writer - Receive Stopped Enable"] +pub struct RSE_W<'a> { + w: &'a mut W, +} +impl<'a> RSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RUE` reader - Receive Buffer Unavailable Enable"] +pub struct RUE_R(crate::FieldReader); +impl RUE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUE` writer - Receive Buffer Unavailable Enable"] +pub struct RUE_W<'a> { + w: &'a mut W, +} +impl<'a> RUE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RIE` reader - Receive Interrupt Enable"] +pub struct RIE_R(crate::FieldReader); +impl RIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RIE` writer - Receive Interrupt Enable"] +pub struct RIE_W<'a> { + w: &'a mut W, +} +impl<'a> RIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `UNE` reader - Underflow Interrupt Enable"] +pub struct UNE_R(crate::FieldReader); +impl UNE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNE` writer - Underflow Interrupt Enable"] +pub struct UNE_W<'a> { + w: &'a mut W, +} +impl<'a> UNE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `OVE` reader - Overflow Interrupt Enable"] +pub struct OVE_R(crate::FieldReader); +impl OVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVE` writer - Overflow Interrupt Enable"] +pub struct OVE_W<'a> { + w: &'a mut W, +} +impl<'a> OVE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `THE` reader - Transmit Jabber Timeout Enable"] +pub struct THE_R(crate::FieldReader); +impl THE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + THE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for THE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `THE` writer - Transmit Jabber Timeout Enable"] +pub struct THE_W<'a> { + w: &'a mut W, +} +impl<'a> THE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TUE` reader - Transmit Buffer Unavailable Enable"] +pub struct TUE_R(crate::FieldReader); +impl TUE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TUE` writer - Transmit Buffer Unavailable Enable"] +pub struct TUE_W<'a> { + w: &'a mut W, +} +impl<'a> TUE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TSE` reader - Transmit Stopped Enable"] +pub struct TSE_R(crate::FieldReader); +impl TSE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSE` writer - Transmit Stopped Enable"] +pub struct TSE_W<'a> { + w: &'a mut W, +} +impl<'a> TSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TIE` reader - Transmit Interrupt Enable"] +pub struct TIE_R(crate::FieldReader); +impl TIE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIE` writer - Transmit Interrupt Enable"] +pub struct TIE_W<'a> { + w: &'a mut W, +} +impl<'a> TIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 16 - Normal Interrupt Summary Enable"] + #[inline(always)] + pub fn nie(&self) -> NIE_R { + NIE_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 15 - Abnormal Interrupt Summary Enable"] + #[inline(always)] + pub fn aie(&self) -> AIE_R { + AIE_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 14 - Early Receive Interrupt Enable"] + #[inline(always)] + pub fn ere(&self) -> ERE_R { + ERE_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - Fatal Bus Error Enable"] + #[inline(always)] + pub fn fbe(&self) -> FBE_R { + FBE_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 10 - Early Transmit Interrupt Enable"] + #[inline(always)] + pub fn ete(&self) -> ETE_R { + ETE_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - Receive Watchdog Timeout Enable"] + #[inline(always)] + pub fn rwe(&self) -> RWE_R { + RWE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - Receive Stopped Enable"] + #[inline(always)] + pub fn rse(&self) -> RSE_R { + RSE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 7 - Receive Buffer Unavailable Enable"] + #[inline(always)] + pub fn rue(&self) -> RUE_R { + RUE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - Receive Interrupt Enable"] + #[inline(always)] + pub fn rie(&self) -> RIE_R { + RIE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Underflow Interrupt Enable"] + #[inline(always)] + pub fn une(&self) -> UNE_R { + UNE_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ove(&self) -> OVE_R { + OVE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmit Jabber Timeout Enable"] + #[inline(always)] + pub fn the(&self) -> THE_R { + THE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmit Buffer Unavailable Enable"] + #[inline(always)] + pub fn tue(&self) -> TUE_R { + TUE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Stopped Enable"] + #[inline(always)] + pub fn tse(&self) -> TSE_R { + TSE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Transmit Interrupt Enable"] + #[inline(always)] + pub fn tie(&self) -> TIE_R { + TIE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 16 - Normal Interrupt Summary Enable"] + #[inline(always)] + pub fn nie(&mut self) -> NIE_W { + NIE_W { w: self } + } + #[doc = "Bit 15 - Abnormal Interrupt Summary Enable"] + #[inline(always)] + pub fn aie(&mut self) -> AIE_W { + AIE_W { w: self } + } + #[doc = "Bit 14 - Early Receive Interrupt Enable"] + #[inline(always)] + pub fn ere(&mut self) -> ERE_W { + ERE_W { w: self } + } + #[doc = "Bit 13 - Fatal Bus Error Enable"] + #[inline(always)] + pub fn fbe(&mut self) -> FBE_W { + FBE_W { w: self } + } + #[doc = "Bit 10 - Early Transmit Interrupt Enable"] + #[inline(always)] + pub fn ete(&mut self) -> ETE_W { + ETE_W { w: self } + } + #[doc = "Bit 9 - Receive Watchdog Timeout Enable"] + #[inline(always)] + pub fn rwe(&mut self) -> RWE_W { + RWE_W { w: self } + } + #[doc = "Bit 8 - Receive Stopped Enable"] + #[inline(always)] + pub fn rse(&mut self) -> RSE_W { + RSE_W { w: self } + } + #[doc = "Bit 7 - Receive Buffer Unavailable Enable"] + #[inline(always)] + pub fn rue(&mut self) -> RUE_W { + RUE_W { w: self } + } + #[doc = "Bit 6 - Receive Interrupt Enable"] + #[inline(always)] + pub fn rie(&mut self) -> RIE_W { + RIE_W { w: self } + } + #[doc = "Bit 5 - Underflow Interrupt Enable"] + #[inline(always)] + pub fn une(&mut self) -> UNE_W { + UNE_W { w: self } + } + #[doc = "Bit 4 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ove(&mut self) -> OVE_W { + OVE_W { w: self } + } + #[doc = "Bit 3 - Transmit Jabber Timeout Enable"] + #[inline(always)] + pub fn the(&mut self) -> THE_W { + THE_W { w: self } + } + #[doc = "Bit 2 - Transmit Buffer Unavailable Enable"] + #[inline(always)] + pub fn tue(&mut self) -> TUE_W { + TUE_W { w: self } + } + #[doc = "Bit 1 - Transmit Stopped Enable"] + #[inline(always)] + pub fn tse(&mut self) -> TSE_W { + TSE_W { w: self } + } + #[doc = "Bit 0 - Transmit Interrupt Enable"] + #[inline(always)] + pub fn tie(&mut self) -> TIE_W { + TIE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enables the interrupts reported in the status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_intr_en](index.html) module"] +pub struct DMA_INTR_EN_SPEC; +impl crate::RegisterSpec for DMA_INTR_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_intr_en::R](R) reader structure"] +impl crate::Readable for DMA_INTR_EN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_intr_en::W](W) writer structure"] +impl crate::Writable for DMA_INTR_EN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_INTR_EN to value 0"] +impl crate::Resettable for DMA_INTR_EN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_miss_over_counter.rs b/src/eth/dma_miss_over_counter.rs new file mode 100644 index 0000000..5b435bb --- /dev/null +++ b/src/eth/dma_miss_over_counter.rs @@ -0,0 +1,234 @@ +#[doc = "Register `DMA_MISS_OVER_COUNTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_MISS_OVER_COUNTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVFCNTOVF` reader - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] +pub struct OVFCNTOVF_R(crate::FieldReader); +impl OVFCNTOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVFCNTOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFCNTOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFCNTOVF` writer - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] +pub struct OVFCNTOVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVFCNTOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `OVFFRMCNT` reader - This field indicates the number of frames missed by the application"] +pub struct OVFFRMCNT_R(crate::FieldReader); +impl OVFFRMCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + OVFFRMCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVFFRMCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVFFRMCNT` writer - This field indicates the number of frames missed by the application"] +pub struct OVFFRMCNT_W<'a> { + w: &'a mut W, +} +impl<'a> OVFFRMCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 17)) | ((value as u32 & 0x07ff) << 17); + self.w + } +} +#[doc = "Field `MISCNTOVF` reader - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] +pub struct MISCNTOVF_R(crate::FieldReader); +impl MISCNTOVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MISCNTOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MISCNTOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MISCNTOVF` writer - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] +pub struct MISCNTOVF_W<'a> { + w: &'a mut W, +} +impl<'a> MISCNTOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `MISFRMCNT` reader - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] +pub struct MISFRMCNT_R(crate::FieldReader); +impl MISFRMCNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + MISFRMCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MISFRMCNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MISFRMCNT` writer - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] +pub struct MISFRMCNT_W<'a> { + w: &'a mut W, +} +impl<'a> MISFRMCNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bit 28 - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] + #[inline(always)] + pub fn ovfcntovf(&self) -> OVFCNTOVF_R { + OVFCNTOVF_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bits 17:27 - This field indicates the number of frames missed by the application"] + #[inline(always)] + pub fn ovffrmcnt(&self) -> OVFFRMCNT_R { + OVFFRMCNT_R::new(((self.bits >> 17) & 0x07ff) as u16) + } + #[doc = "Bit 16 - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] + #[inline(always)] + pub fn miscntovf(&self) -> MISCNTOVF_R { + MISCNTOVF_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 0:15 - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] + #[inline(always)] + pub fn misfrmcnt(&self) -> MISFRMCNT_R { + MISFRMCNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 28 - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] + #[inline(always)] + pub fn ovfcntovf(&mut self) -> OVFCNTOVF_W { + OVFCNTOVF_W { w: self } + } + #[doc = "Bits 17:27 - This field indicates the number of frames missed by the application"] + #[inline(always)] + pub fn ovffrmcnt(&mut self) -> OVFFRMCNT_W { + OVFFRMCNT_W { w: self } + } + #[doc = "Bit 16 - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] + #[inline(always)] + pub fn miscntovf(&mut self) -> MISCNTOVF_W { + MISCNTOVF_W { w: self } + } + #[doc = "Bits 0:15 - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] + #[inline(always)] + pub fn misfrmcnt(&mut self) -> MISFRMCNT_W { + MISFRMCNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the counters for discarded frames because no Receive Descriptor is available\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_miss_over_counter](index.html) module"] +pub struct DMA_MISS_OVER_COUNTER_SPEC; +impl crate::RegisterSpec for DMA_MISS_OVER_COUNTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_miss_over_counter::R](R) reader structure"] +impl crate::Readable for DMA_MISS_OVER_COUNTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_miss_over_counter::W](W) writer structure"] +impl crate::Writable for DMA_MISS_OVER_COUNTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_MISS_OVER_COUNTER to value 0"] +impl crate::Resettable for DMA_MISS_OVER_COUNTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_oper_mode.rs b/src/eth/dma_oper_mode.rs new file mode 100644 index 0000000..f1c57c6 --- /dev/null +++ b/src/eth/dma_oper_mode.rs @@ -0,0 +1,731 @@ +#[doc = "Register `DMA_OPER_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_OPER_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DT` reader - Disable Dropping of TCP/IP Checksum Error Frames"] +pub struct DT_R(crate::FieldReader); +impl DT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DT` writer - Disable Dropping of TCP/IP Checksum Error Frames"] +pub struct DT_W<'a> { + w: &'a mut W, +} +impl<'a> DT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `RSF` reader - Receive Store and Forward"] +pub struct RSF_R(crate::FieldReader); +impl RSF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSF` writer - Receive Store and Forward"] +pub struct RSF_W<'a> { + w: &'a mut W, +} +impl<'a> RSF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `DFF` reader - Disable Flushing of Received Frames"] +pub struct DFF_R(crate::FieldReader); +impl DFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DFF` writer - Disable Flushing of Received Frames"] +pub struct DFF_W<'a> { + w: &'a mut W, +} +impl<'a> DFF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `TSF` reader - Transmit Store and Forward"] +pub struct TSF_R(crate::FieldReader); +impl TSF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSF` writer - Transmit Store and Forward"] +pub struct TSF_W<'a> { + w: &'a mut W, +} +impl<'a> TSF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `FTF` reader - Flush Transmit FIFO"] +pub struct FTF_R(crate::FieldReader); +impl FTF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FTF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FTF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FTF` writer - Flush Transmit FIFO"] +pub struct FTF_W<'a> { + w: &'a mut W, +} +impl<'a> FTF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `TTC` reader - Transmit Threshold Control"] +pub struct TTC_R(crate::FieldReader); +impl TTC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TTC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TTC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TTC` writer - Transmit Threshold Control"] +pub struct TTC_W<'a> { + w: &'a mut W, +} +impl<'a> TTC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 14)) | ((value as u32 & 0x07) << 14); + self.w + } +} +#[doc = "Field `ST` reader - Start or Stop Transmission Command"] +pub struct ST_R(crate::FieldReader); +impl ST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ST` writer - Start or Stop Transmission Command"] +pub struct ST_W<'a> { + w: &'a mut W, +} +impl<'a> ST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `RFD` reader - Threshold for Deactivating Flow Control"] +pub struct RFD_R(crate::FieldReader); +impl RFD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RFD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFD` writer - Threshold for Deactivating Flow Control"] +pub struct RFD_W<'a> { + w: &'a mut W, +} +impl<'a> RFD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 11)) | ((value as u32 & 0x03) << 11); + self.w + } +} +#[doc = "Field `RFA` reader - Threshold for Activating Flow Control"] +pub struct RFA_R(crate::FieldReader); +impl RFA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RFA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFA` writer - Threshold for Activating Flow Control"] +pub struct RFA_W<'a> { + w: &'a mut W, +} +impl<'a> RFA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 9)) | ((value as u32 & 0x03) << 9); + self.w + } +} +#[doc = "Field `FEF` reader - Forward Error Frames"] +pub struct FEF_R(crate::FieldReader); +impl FEF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FEF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FEF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FEF` writer - Forward Error Frames"] +pub struct FEF_W<'a> { + w: &'a mut W, +} +impl<'a> FEF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `FUF` reader - Forward Undersized Good Frames"] +pub struct FUF_R(crate::FieldReader); +impl FUF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FUF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FUF` writer - Forward Undersized Good Frames"] +pub struct FUF_W<'a> { + w: &'a mut W, +} +impl<'a> FUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DGF` reader - Drop Giant Frames"] +pub struct DGF_R(crate::FieldReader); +impl DGF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DGF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DGF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DGF` writer - Drop Giant Frames"] +pub struct DGF_W<'a> { + w: &'a mut W, +} +impl<'a> DGF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RTC` reader - Receive Threshold Control"] +pub struct RTC_R(crate::FieldReader); +impl RTC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RTC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC` writer - Receive Threshold Control"] +pub struct RTC_W<'a> { + w: &'a mut W, +} +impl<'a> RTC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u32 & 0x03) << 3); + self.w + } +} +#[doc = "Field `OSF` reader - Operate on Second Frame"] +pub struct OSF_R(crate::FieldReader); +impl OSF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSF` writer - Operate on Second Frame"] +pub struct OSF_W<'a> { + w: &'a mut W, +} +impl<'a> OSF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SR` reader - Start or Stop Receive"] +pub struct SR_R(crate::FieldReader); +impl SR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SR` writer - Start or Stop Receive"] +pub struct SR_W<'a> { + w: &'a mut W, +} +impl<'a> SR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 26 - Disable Dropping of TCP/IP Checksum Error Frames"] + #[inline(always)] + pub fn dt(&self) -> DT_R { + DT_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 25 - Receive Store and Forward"] + #[inline(always)] + pub fn rsf(&self) -> RSF_R { + RSF_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 24 - Disable Flushing of Received Frames"] + #[inline(always)] + pub fn dff(&self) -> DFF_R { + DFF_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 21 - Transmit Store and Forward"] + #[inline(always)] + pub fn tsf(&self) -> TSF_R { + TSF_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 20 - Flush Transmit FIFO"] + #[inline(always)] + pub fn ftf(&self) -> FTF_R { + FTF_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bits 14:16 - Transmit Threshold Control"] + #[inline(always)] + pub fn ttc(&self) -> TTC_R { + TTC_R::new(((self.bits >> 14) & 0x07) as u8) + } + #[doc = "Bit 13 - Start or Stop Transmission Command"] + #[inline(always)] + pub fn st(&self) -> ST_R { + ST_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 11:12 - Threshold for Deactivating Flow Control"] + #[inline(always)] + pub fn rfd(&self) -> RFD_R { + RFD_R::new(((self.bits >> 11) & 0x03) as u8) + } + #[doc = "Bits 9:10 - Threshold for Activating Flow Control"] + #[inline(always)] + pub fn rfa(&self) -> RFA_R { + RFA_R::new(((self.bits >> 9) & 0x03) as u8) + } + #[doc = "Bit 7 - Forward Error Frames"] + #[inline(always)] + pub fn fef(&self) -> FEF_R { + FEF_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - Forward Undersized Good Frames"] + #[inline(always)] + pub fn fuf(&self) -> FUF_R { + FUF_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Drop Giant Frames"] + #[inline(always)] + pub fn dgf(&self) -> DGF_R { + DGF_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bits 3:4 - Receive Threshold Control"] + #[inline(always)] + pub fn rtc(&self) -> RTC_R { + RTC_R::new(((self.bits >> 3) & 0x03) as u8) + } + #[doc = "Bit 2 - Operate on Second Frame"] + #[inline(always)] + pub fn osf(&self) -> OSF_R { + OSF_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Start or Stop Receive"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 26 - Disable Dropping of TCP/IP Checksum Error Frames"] + #[inline(always)] + pub fn dt(&mut self) -> DT_W { + DT_W { w: self } + } + #[doc = "Bit 25 - Receive Store and Forward"] + #[inline(always)] + pub fn rsf(&mut self) -> RSF_W { + RSF_W { w: self } + } + #[doc = "Bit 24 - Disable Flushing of Received Frames"] + #[inline(always)] + pub fn dff(&mut self) -> DFF_W { + DFF_W { w: self } + } + #[doc = "Bit 21 - Transmit Store and Forward"] + #[inline(always)] + pub fn tsf(&mut self) -> TSF_W { + TSF_W { w: self } + } + #[doc = "Bit 20 - Flush Transmit FIFO"] + #[inline(always)] + pub fn ftf(&mut self) -> FTF_W { + FTF_W { w: self } + } + #[doc = "Bits 14:16 - Transmit Threshold Control"] + #[inline(always)] + pub fn ttc(&mut self) -> TTC_W { + TTC_W { w: self } + } + #[doc = "Bit 13 - Start or Stop Transmission Command"] + #[inline(always)] + pub fn st(&mut self) -> ST_W { + ST_W { w: self } + } + #[doc = "Bits 11:12 - Threshold for Deactivating Flow Control"] + #[inline(always)] + pub fn rfd(&mut self) -> RFD_W { + RFD_W { w: self } + } + #[doc = "Bits 9:10 - Threshold for Activating Flow Control"] + #[inline(always)] + pub fn rfa(&mut self) -> RFA_W { + RFA_W { w: self } + } + #[doc = "Bit 7 - Forward Error Frames"] + #[inline(always)] + pub fn fef(&mut self) -> FEF_W { + FEF_W { w: self } + } + #[doc = "Bit 6 - Forward Undersized Good Frames"] + #[inline(always)] + pub fn fuf(&mut self) -> FUF_W { + FUF_W { w: self } + } + #[doc = "Bit 5 - Drop Giant Frames"] + #[inline(always)] + pub fn dgf(&mut self) -> DGF_W { + DGF_W { w: self } + } + #[doc = "Bits 3:4 - Receive Threshold Control"] + #[inline(always)] + pub fn rtc(&mut self) -> RTC_W { + RTC_W { w: self } + } + #[doc = "Bit 2 - Operate on Second Frame"] + #[inline(always)] + pub fn osf(&mut self) -> OSF_W { + OSF_W { w: self } + } + #[doc = "Bit 1 - Start or Stop Receive"] + #[inline(always)] + pub fn sr(&mut self) -> SR_W { + SR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sets the Receive and Transmit operation mode and command\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_oper_mode](index.html) module"] +pub struct DMA_OPER_MODE_SPEC; +impl crate::RegisterSpec for DMA_OPER_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_oper_mode::R](R) reader structure"] +impl crate::Readable for DMA_OPER_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_oper_mode::W](W) writer structure"] +impl crate::Writable for DMA_OPER_MODE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_OPER_MODE to value 0"] +impl crate::Resettable for DMA_OPER_MODE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_rx_desc_list_addr.rs b/src/eth/dma_rx_desc_list_addr.rs new file mode 100644 index 0000000..e66f11c --- /dev/null +++ b/src/eth/dma_rx_desc_list_addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMA_RX_DESC_LIST_ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_RX_DESC_LIST_ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RDESLA` reader - Start of Receive List"] +pub struct RDESLA_R(crate::FieldReader); +impl RDESLA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RDESLA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RDESLA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RDESLA` writer - Start of Receive List"] +pub struct RDESLA_W<'a> { + w: &'a mut W, +} +impl<'a> RDESLA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Start of Receive List"] + #[inline(always)] + pub fn rdesla(&self) -> RDESLA_R { + RDESLA_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Start of Receive List"] + #[inline(always)] + pub fn rdesla(&mut self) -> RDESLA_W { + RDESLA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Points the DMA to the start of the Receive Descriptor list\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_rx_desc_list_addr](index.html) module"] +pub struct DMA_RX_DESC_LIST_ADDR_SPEC; +impl crate::RegisterSpec for DMA_RX_DESC_LIST_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_rx_desc_list_addr::R](R) reader structure"] +impl crate::Readable for DMA_RX_DESC_LIST_ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_rx_desc_list_addr::W](W) writer structure"] +impl crate::Writable for DMA_RX_DESC_LIST_ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_RX_DESC_LIST_ADDR to value 0"] +impl crate::Resettable for DMA_RX_DESC_LIST_ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_rx_intr_wdog_timer.rs b/src/eth/dma_rx_intr_wdog_timer.rs new file mode 100644 index 0000000..2f710ae --- /dev/null +++ b/src/eth/dma_rx_intr_wdog_timer.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMA_RX_INTR_WDOG_TIMER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_RX_INTR_WDOG_TIMER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RIWT` reader - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] +pub struct RIWT_R(crate::FieldReader); +impl RIWT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RIWT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RIWT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RIWT` writer - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] +pub struct RIWT_W<'a> { + w: &'a mut W, +} +impl<'a> RIWT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] + #[inline(always)] + pub fn riwt(&self) -> RIWT_R { + RIWT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] + #[inline(always)] + pub fn riwt(&mut self) -> RIWT_W { + RIWT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Watchdog timeout for Receive Interrupt from DMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_rx_intr_wdog_timer](index.html) module"] +pub struct DMA_RX_INTR_WDOG_TIMER_SPEC; +impl crate::RegisterSpec for DMA_RX_INTR_WDOG_TIMER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_rx_intr_wdog_timer::R](R) reader structure"] +impl crate::Readable for DMA_RX_INTR_WDOG_TIMER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_rx_intr_wdog_timer::W](W) writer structure"] +impl crate::Writable for DMA_RX_INTR_WDOG_TIMER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_RX_INTR_WDOG_TIMER to value 0"] +impl crate::Resettable for DMA_RX_INTR_WDOG_TIMER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_rx_poll_demand.rs b/src/eth/dma_rx_poll_demand.rs new file mode 100644 index 0000000..c49ed7c --- /dev/null +++ b/src/eth/dma_rx_poll_demand.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMA_RX_POLL_DEMAND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_RX_POLL_DEMAND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RPD` reader - Receive Poll Demand (Read Only and Write Trigger)"] +pub struct RPD_R(crate::FieldReader); +impl RPD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RPD` writer - Receive Poll Demand (Read Only and Write Trigger)"] +pub struct RPD_W<'a> { + w: &'a mut W, +} +impl<'a> RPD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Receive Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn rpd(&self) -> RPD_R { + RPD_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Receive Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn rpd(&mut self) -> RPD_W { + RPD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Used by the host to instruct the DMA to poll the Receive Descriptor list\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_rx_poll_demand](index.html) module"] +pub struct DMA_RX_POLL_DEMAND_SPEC; +impl crate::RegisterSpec for DMA_RX_POLL_DEMAND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_rx_poll_demand::R](R) reader structure"] +impl crate::Readable for DMA_RX_POLL_DEMAND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_rx_poll_demand::W](W) writer structure"] +impl crate::Writable for DMA_RX_POLL_DEMAND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_RX_POLL_DEMAND to value 0"] +impl crate::Resettable for DMA_RX_POLL_DEMAND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_status.rs b/src/eth/dma_status.rs new file mode 100644 index 0000000..2ffa7c6 --- /dev/null +++ b/src/eth/dma_status.rs @@ -0,0 +1,433 @@ +#[doc = "Register `DMA_STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TTI` reader - Timestamp Trigger Interrupt"] +pub struct TTI_R(crate::FieldReader); +impl TTI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TTI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TTI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GMI` reader - GMAC MMC Interrupt"] +pub struct GMI_R(crate::FieldReader); +impl GMI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GMI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GMI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EB` reader - Error Bits"] +pub struct EB_R(crate::FieldReader); +impl EB_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + EB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TS` reader - Transmit Process State"] +pub struct TS_R(crate::FieldReader); +impl TS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RS` reader - Receive Process State"] +pub struct RS_R(crate::FieldReader); +impl RS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NIS` reader - Normal Interrupt Summary"] +pub struct NIS_R(crate::FieldReader); +impl NIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AIS` reader - Abnormal Interrupt Summary"] +pub struct AIS_R(crate::FieldReader); +impl AIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERI` reader - Early Receive Interrupt"] +pub struct ERI_R(crate::FieldReader); +impl ERI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ERI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FBI` reader - Fatal Bus Error Interruptble"] +pub struct FBI_R(crate::FieldReader); +impl FBI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FBI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FBI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ETI` reader - Early Transmit Interrupt"] +pub struct ETI_R(crate::FieldReader); +impl ETI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ETI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWT` reader - Receive Watchdog Timeout"] +pub struct RWT_R(crate::FieldReader); +impl RWT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RWT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RPS` reader - Receive Process Stopped"] +pub struct RPS_R(crate::FieldReader); +impl RPS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RPS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RPS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RU` reader - Receive Buffer Unavailable"] +pub struct RU_R(crate::FieldReader); +impl RU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RI` reader - Receive Interrupt"] +pub struct RI_R(crate::FieldReader); +impl RI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UNF` reader - Transmit Underflow"] +pub struct UNF_R(crate::FieldReader); +impl UNF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UNF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UNF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` reader - Receive Underflow"] +pub struct OVF_R(crate::FieldReader); +impl OVF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TJT` reader - Transmit Jabber Timeout"] +pub struct TJT_R(crate::FieldReader); +impl TJT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TJT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TJT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TU` reader - Transmit Buffer Unavailable"] +pub struct TU_R(crate::FieldReader); +impl TU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TPS` reader - Transmit Process Stopped"] +pub struct TPS_R(crate::FieldReader); +impl TPS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TPS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TPS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TI` reader - Transmit Interrupt"] +pub struct TI_R(crate::FieldReader); +impl TI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 29 - Timestamp Trigger Interrupt"] + #[inline(always)] + pub fn tti(&self) -> TTI_R { + TTI_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 27 - GMAC MMC Interrupt"] + #[inline(always)] + pub fn gmi(&self) -> GMI_R { + GMI_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 23:25 - Error Bits"] + #[inline(always)] + pub fn eb(&self) -> EB_R { + EB_R::new(((self.bits >> 23) & 0x07) as u8) + } + #[doc = "Bits 20:22 - Transmit Process State"] + #[inline(always)] + pub fn ts(&self) -> TS_R { + TS_R::new(((self.bits >> 20) & 0x07) as u8) + } + #[doc = "Bits 17:19 - Receive Process State"] + #[inline(always)] + pub fn rs(&self) -> RS_R { + RS_R::new(((self.bits >> 17) & 0x07) as u8) + } + #[doc = "Bit 16 - Normal Interrupt Summary"] + #[inline(always)] + pub fn nis(&self) -> NIS_R { + NIS_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 15 - Abnormal Interrupt Summary"] + #[inline(always)] + pub fn ais(&self) -> AIS_R { + AIS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 14 - Early Receive Interrupt"] + #[inline(always)] + pub fn eri(&self) -> ERI_R { + ERI_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - Fatal Bus Error Interruptble"] + #[inline(always)] + pub fn fbi(&self) -> FBI_R { + FBI_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 10 - Early Transmit Interrupt"] + #[inline(always)] + pub fn eti(&self) -> ETI_R { + ETI_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - Receive Watchdog Timeout"] + #[inline(always)] + pub fn rwt(&self) -> RWT_R { + RWT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - Receive Process Stopped"] + #[inline(always)] + pub fn rps(&self) -> RPS_R { + RPS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 7 - Receive Buffer Unavailable"] + #[inline(always)] + pub fn ru(&self) -> RU_R { + RU_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - Receive Interrupt"] + #[inline(always)] + pub fn ri(&self) -> RI_R { + RI_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Transmit Underflow"] + #[inline(always)] + pub fn unf(&self) -> UNF_R { + UNF_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Receive Underflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmit Jabber Timeout"] + #[inline(always)] + pub fn tjt(&self) -> TJT_R { + TJT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Transmit Buffer Unavailable"] + #[inline(always)] + pub fn tu(&self) -> TU_R { + TU_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Process Stopped"] + #[inline(always)] + pub fn tps(&self) -> TPS_R { + TPS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Transmit Interrupt"] + #[inline(always)] + pub fn ti(&self) -> TI_R { + TI_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Used to determine the status of the DMA\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_status](index.html) module"] +pub struct DMA_STATUS_SPEC; +impl crate::RegisterSpec for DMA_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_status::R](R) reader structure"] +impl crate::Readable for DMA_STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DMA_STATUS to value 0"] +impl crate::Resettable for DMA_STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_tx_desc_list_addr.rs b/src/eth/dma_tx_desc_list_addr.rs new file mode 100644 index 0000000..74a6ed2 --- /dev/null +++ b/src/eth/dma_tx_desc_list_addr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMA_TX_DESC_LIST_ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_TX_DESC_LIST_ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TDESLA` reader - Start of Transmit List"] +pub struct TDESLA_R(crate::FieldReader); +impl TDESLA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TDESLA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TDESLA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TDESLA` writer - Start of Transmit List"] +pub struct TDESLA_W<'a> { + w: &'a mut W, +} +impl<'a> TDESLA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Start of Transmit List"] + #[inline(always)] + pub fn tdesla(&self) -> TDESLA_R { + TDESLA_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Start of Transmit List"] + #[inline(always)] + pub fn tdesla(&mut self) -> TDESLA_W { + TDESLA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Points the DMA to the start of the Transmit Descriptor list\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_tx_desc_list_addr](index.html) module"] +pub struct DMA_TX_DESC_LIST_ADDR_SPEC; +impl crate::RegisterSpec for DMA_TX_DESC_LIST_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_tx_desc_list_addr::R](R) reader structure"] +impl crate::Readable for DMA_TX_DESC_LIST_ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_tx_desc_list_addr::W](W) writer structure"] +impl crate::Writable for DMA_TX_DESC_LIST_ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_TX_DESC_LIST_ADDR to value 0"] +impl crate::Resettable for DMA_TX_DESC_LIST_ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/dma_tx_poll_demand.rs b/src/eth/dma_tx_poll_demand.rs new file mode 100644 index 0000000..d96841a --- /dev/null +++ b/src/eth/dma_tx_poll_demand.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMA_TX_POLL_DEMAND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMA_TX_POLL_DEMAND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TPD` reader - Transmit Poll Demand (Read Only and Write Trigger)"] +pub struct TPD_R(crate::FieldReader); +impl TPD_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TPD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TPD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TPD` writer - Transmit Poll Demand (Read Only and Write Trigger)"] +pub struct TPD_W<'a> { + w: &'a mut W, +} +impl<'a> TPD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Transmit Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn tpd(&self) -> TPD_R { + TPD_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Transmit Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn tpd(&mut self) -> TPD_W { + TPD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Used by the host to instruct the DMA to poll the transmit Descriptor list\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_tx_poll_demand](index.html) module"] +pub struct DMA_TX_POLL_DEMAND_SPEC; +impl crate::RegisterSpec for DMA_TX_POLL_DEMAND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dma_tx_poll_demand::R](R) reader structure"] +impl crate::Readable for DMA_TX_POLL_DEMAND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dma_tx_poll_demand::W](W) writer structure"] +impl crate::Writable for DMA_TX_POLL_DEMAND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMA_TX_POLL_DEMAND to value 0"] +impl crate::Resettable for DMA_TX_POLL_DEMAND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_addr_h.rs b/src/eth/mac_addr_h.rs new file mode 100644 index 0000000..ebe3d27 --- /dev/null +++ b/src/eth/mac_addr_h.rs @@ -0,0 +1,106 @@ +#[doc = "Register `MAC_ADDR_H` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_ADDR_H` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AE` reader - Address Enable, This bit is always set to 1"] +pub struct AE_R(crate::FieldReader); +impl AE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRHI` reader - MAC Address0\\[47:32\\]"] +pub struct ADDRHI_R(crate::FieldReader); +impl ADDRHI_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRHI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRHI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 31 - Address Enable, This bit is always set to 1"] + #[inline(always)] + pub fn ae(&self) -> AE_R { + AE_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bits 0:15 - MAC Address0\\[47:32\\]"] + #[inline(always)] + pub fn addrhi(&self) -> ADDRHI_R { + ADDRHI_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the high 16-bits of the first MAC Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_addr_h](index.html) module"] +pub struct MAC_ADDR_H_SPEC; +impl crate::RegisterSpec for MAC_ADDR_H_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_addr_h::R](R) reader structure"] +impl crate::Readable for MAC_ADDR_H_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_addr_h::W](W) writer structure"] +impl crate::Writable for MAC_ADDR_H_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_ADDR_H to value 0x8000_ffff"] +impl crate::Resettable for MAC_ADDR_H_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x8000_ffff + } +} diff --git a/src/eth/mac_addr_l.rs b/src/eth/mac_addr_l.rs new file mode 100644 index 0000000..852c8bb --- /dev/null +++ b/src/eth/mac_addr_l.rs @@ -0,0 +1,86 @@ +#[doc = "Register `MAC_ADDR_L` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_ADDR_L` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDRLO` reader - MAC Address0\\[31:0\\]"] +pub struct ADDRLO_R(crate::FieldReader); +impl ADDRLO_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDRLO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRLO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - MAC Address0\\[31:0\\]"] + #[inline(always)] + pub fn addrlo(&self) -> ADDRLO_R { + ADDRLO_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the Low 32-bits of the first MAC Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_addr_l](index.html) module"] +pub struct MAC_ADDR_L_SPEC; +impl crate::RegisterSpec for MAC_ADDR_L_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_addr_l::R](R) reader structure"] +impl crate::Readable for MAC_ADDR_L_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_addr_l::W](W) writer structure"] +impl crate::Writable for MAC_ADDR_L_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_ADDR_L to value 0xffff_ffff"] +impl crate::Resettable for MAC_ADDR_L_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/src/eth/mac_config.rs b/src/eth/mac_config.rs new file mode 100644 index 0000000..a37ed51 --- /dev/null +++ b/src/eth/mac_config.rs @@ -0,0 +1,929 @@ +#[doc = "Register `MAC_CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WD` reader - Watchdog disable"] +pub struct WD_R(crate::FieldReader); +impl WD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WD` writer - Watchdog disable"] +pub struct WD_W<'a> { + w: &'a mut W, +} +impl<'a> WD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `JD` reader - Jabber Disable"] +pub struct JD_R(crate::FieldReader); +impl JD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JD` writer - Jabber Disable"] +pub struct JD_W<'a> { + w: &'a mut W, +} +impl<'a> JD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `BE` reader - Frame Burst Enable"] +pub struct BE_R(crate::FieldReader); +impl BE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BE` writer - Frame Burst Enable"] +pub struct BE_W<'a> { + w: &'a mut W, +} +impl<'a> BE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `JE` reader - Jumbo Frame Enable"] +pub struct JE_R(crate::FieldReader); +impl JE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JE` writer - Jumbo Frame Enable"] +pub struct JE_W<'a> { + w: &'a mut W, +} +impl<'a> JE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `IFG` reader - Inter-Frame Gap"] +pub struct IFG_R(crate::FieldReader); +impl IFG_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + IFG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IFG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IFG` writer - Inter-Frame Gap"] +pub struct IFG_W<'a> { + w: &'a mut W, +} +impl<'a> IFG_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 17)) | ((value as u32 & 0x07) << 17); + self.w + } +} +#[doc = "Field `DCRS` reader - Disable Carrier Sense During Transmission"] +pub struct DCRS_R(crate::FieldReader); +impl DCRS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCRS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCRS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCRS` writer - Disable Carrier Sense During Transmission"] +pub struct DCRS_W<'a> { + w: &'a mut W, +} +impl<'a> DCRS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `PS` reader - Port Select"] +pub struct PS_R(crate::FieldReader); +impl PS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PS` writer - Port Select"] +pub struct PS_W<'a> { + w: &'a mut W, +} +impl<'a> PS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `FES` reader - Speed"] +pub struct FES_R(crate::FieldReader); +impl FES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FES` writer - Speed"] +pub struct FES_W<'a> { + w: &'a mut W, +} +impl<'a> FES_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `DRO` reader - Disable Receive Own"] +pub struct DRO_R(crate::FieldReader); +impl DRO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DRO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRO` writer - Disable Receive Own"] +pub struct DRO_W<'a> { + w: &'a mut W, +} +impl<'a> DRO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `LM` reader - Loopback Mode"] +pub struct LM_R(crate::FieldReader); +impl LM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LM` writer - Loopback Mode"] +pub struct LM_W<'a> { + w: &'a mut W, +} +impl<'a> LM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DM` reader - Duplex Mode"] +pub struct DM_R(crate::FieldReader); +impl DM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DM` writer - Duplex Mode"] +pub struct DM_W<'a> { + w: &'a mut W, +} +impl<'a> DM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `IPC` reader - Checksum Offload"] +pub struct IPC_R(crate::FieldReader); +impl IPC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IPC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IPC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IPC` writer - Checksum Offload"] +pub struct IPC_W<'a> { + w: &'a mut W, +} +impl<'a> IPC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DR` reader - Disable Retry"] +pub struct DR_R(crate::FieldReader); +impl DR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DR` writer - Disable Retry"] +pub struct DR_W<'a> { + w: &'a mut W, +} +impl<'a> DR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `ACS` reader - Automatic Pad, or CRC Stripping"] +pub struct ACS_R(crate::FieldReader); +impl ACS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACS` writer - Automatic Pad, or CRC Stripping"] +pub struct ACS_W<'a> { + w: &'a mut W, +} +impl<'a> ACS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `BL` reader - Back-Off-Limit"] +pub struct BL_R(crate::FieldReader); +impl BL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BL` writer - Back-Off-Limit"] +pub struct BL_W<'a> { + w: &'a mut W, +} +impl<'a> BL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `DC` reader - Deferral Check"] +pub struct DC_R(crate::FieldReader); +impl DC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DC` writer - Deferral Check"] +pub struct DC_W<'a> { + w: &'a mut W, +} +impl<'a> DC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TE` reader - Transmitter Enable"] +pub struct TE_R(crate::FieldReader); +impl TE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TE` writer - Transmitter Enable"] +pub struct TE_W<'a> { + w: &'a mut W, +} +impl<'a> TE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RE` reader - Receiver Enable"] +pub struct RE_R(crate::FieldReader); +impl RE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RE` writer - Receiver Enable"] +pub struct RE_W<'a> { + w: &'a mut W, +} +impl<'a> RE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `PRELEN` reader - Preamble Length for Transmit frames"] +pub struct PRELEN_R(crate::FieldReader); +impl PRELEN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PRELEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PRELEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRELEN` writer - Preamble Length for Transmit frames"] +pub struct PRELEN_W<'a> { + w: &'a mut W, +} +impl<'a> PRELEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +impl R { + #[doc = "Bit 23 - Watchdog disable"] + #[inline(always)] + pub fn wd(&self) -> WD_R { + WD_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 22 - Jabber Disable"] + #[inline(always)] + pub fn jd(&self) -> JD_R { + JD_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 21 - Frame Burst Enable"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 20 - Jumbo Frame Enable"] + #[inline(always)] + pub fn je(&self) -> JE_R { + JE_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bits 17:19 - Inter-Frame Gap"] + #[inline(always)] + pub fn ifg(&self) -> IFG_R { + IFG_R::new(((self.bits >> 17) & 0x07) as u8) + } + #[doc = "Bit 16 - Disable Carrier Sense During Transmission"] + #[inline(always)] + pub fn dcrs(&self) -> DCRS_R { + DCRS_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 15 - Port Select"] + #[inline(always)] + pub fn ps(&self) -> PS_R { + PS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 14 - Speed"] + #[inline(always)] + pub fn fes(&self) -> FES_R { + FES_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - Disable Receive Own"] + #[inline(always)] + pub fn dro(&self) -> DRO_R { + DRO_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 12 - Loopback Mode"] + #[inline(always)] + pub fn lm(&self) -> LM_R { + LM_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 11 - Duplex Mode"] + #[inline(always)] + pub fn dm(&self) -> DM_R { + DM_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - Checksum Offload"] + #[inline(always)] + pub fn ipc(&self) -> IPC_R { + IPC_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - Disable Retry"] + #[inline(always)] + pub fn dr(&self) -> DR_R { + DR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 7 - Automatic Pad, or CRC Stripping"] + #[inline(always)] + pub fn acs(&self) -> ACS_R { + ACS_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Back-Off-Limit"] + #[inline(always)] + pub fn bl(&self) -> BL_R { + BL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 4 - Deferral Check"] + #[inline(always)] + pub fn dc(&self) -> DC_R { + DC_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Transmitter Enable"] + #[inline(always)] + pub fn te(&self) -> TE_R { + TE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Receiver Enable"] + #[inline(always)] + pub fn re(&self) -> RE_R { + RE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 0:1 - Preamble Length for Transmit frames"] + #[inline(always)] + pub fn prelen(&self) -> PRELEN_R { + PRELEN_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bit 23 - Watchdog disable"] + #[inline(always)] + pub fn wd(&mut self) -> WD_W { + WD_W { w: self } + } + #[doc = "Bit 22 - Jabber Disable"] + #[inline(always)] + pub fn jd(&mut self) -> JD_W { + JD_W { w: self } + } + #[doc = "Bit 21 - Frame Burst Enable"] + #[inline(always)] + pub fn be(&mut self) -> BE_W { + BE_W { w: self } + } + #[doc = "Bit 20 - Jumbo Frame Enable"] + #[inline(always)] + pub fn je(&mut self) -> JE_W { + JE_W { w: self } + } + #[doc = "Bits 17:19 - Inter-Frame Gap"] + #[inline(always)] + pub fn ifg(&mut self) -> IFG_W { + IFG_W { w: self } + } + #[doc = "Bit 16 - Disable Carrier Sense During Transmission"] + #[inline(always)] + pub fn dcrs(&mut self) -> DCRS_W { + DCRS_W { w: self } + } + #[doc = "Bit 15 - Port Select"] + #[inline(always)] + pub fn ps(&mut self) -> PS_W { + PS_W { w: self } + } + #[doc = "Bit 14 - Speed"] + #[inline(always)] + pub fn fes(&mut self) -> FES_W { + FES_W { w: self } + } + #[doc = "Bit 13 - Disable Receive Own"] + #[inline(always)] + pub fn dro(&mut self) -> DRO_W { + DRO_W { w: self } + } + #[doc = "Bit 12 - Loopback Mode"] + #[inline(always)] + pub fn lm(&mut self) -> LM_W { + LM_W { w: self } + } + #[doc = "Bit 11 - Duplex Mode"] + #[inline(always)] + pub fn dm(&mut self) -> DM_W { + DM_W { w: self } + } + #[doc = "Bit 10 - Checksum Offload"] + #[inline(always)] + pub fn ipc(&mut self) -> IPC_W { + IPC_W { w: self } + } + #[doc = "Bit 9 - Disable Retry"] + #[inline(always)] + pub fn dr(&mut self) -> DR_W { + DR_W { w: self } + } + #[doc = "Bit 7 - Automatic Pad, or CRC Stripping"] + #[inline(always)] + pub fn acs(&mut self) -> ACS_W { + ACS_W { w: self } + } + #[doc = "Bits 5:6 - Back-Off-Limit"] + #[inline(always)] + pub fn bl(&mut self) -> BL_W { + BL_W { w: self } + } + #[doc = "Bit 4 - Deferral Check"] + #[inline(always)] + pub fn dc(&mut self) -> DC_W { + DC_W { w: self } + } + #[doc = "Bit 3 - Transmitter Enable"] + #[inline(always)] + pub fn te(&mut self) -> TE_W { + TE_W { w: self } + } + #[doc = "Bit 2 - Receiver Enable"] + #[inline(always)] + pub fn re(&mut self) -> RE_W { + RE_W { w: self } + } + #[doc = "Bits 0:1 - Preamble Length for Transmit frames"] + #[inline(always)] + pub fn prelen(&mut self) -> PRELEN_W { + PRELEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Operation mode register for the MAC\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_config](index.html) module"] +pub struct MAC_CONFIG_SPEC; +impl crate::RegisterSpec for MAC_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_config::R](R) reader structure"] +impl crate::Readable for MAC_CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_config::W](W) writer structure"] +impl crate::Writable for MAC_CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_CONFIG to value 0"] +impl crate::Resettable for MAC_CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_debug.rs b/src/eth/mac_debug.rs new file mode 100644 index 0000000..14d8b2b --- /dev/null +++ b/src/eth/mac_debug.rs @@ -0,0 +1,273 @@ +#[doc = "Register `MAC_DEBUG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TXSTSFSTS` reader - MTL TxStatus FIFO Full Status"] +pub struct TXSTSFSTS_R(crate::FieldReader); +impl TXSTSFSTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTSFSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTSFSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXFSTS` reader - MTL Tx FIFO Not Empty Status"] +pub struct TXFSTS_R(crate::FieldReader); +impl TXFSTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXFSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXFSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TWCSTS` reader - MTL Tx FIFO Write Controller Status"] +pub struct TWCSTS_R(crate::FieldReader); +impl TWCSTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TWCSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TWCSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRCSTS` reader - MTL Tx FIFO Read Controller Status"] +pub struct TRCSTS_R(crate::FieldReader); +impl TRCSTS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TRCSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRCSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPAUSED` reader - MAC Transmitter in Pause"] +pub struct TXPAUSED_R(crate::FieldReader); +impl TXPAUSED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXPAUSED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXPAUSED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFCSTS` reader - PAC Transmit Frame Controller Status"] +pub struct TFCSTS_R(crate::FieldReader); +impl TFCSTS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TFCSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFCSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TPESTS` reader - MAC GMII or MII Transmit Protocol Engine Status"] +pub struct TPESTS_R(crate::FieldReader); +impl TPESTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TPESTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TPESTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFSTS` reader - MTL RxFIFO Fill-Level Status"] +pub struct RXFSTS_R(crate::FieldReader); +impl RXFSTS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RXFSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRCSTS` reader - MTL RxFIFO Read Controller State"] +pub struct RRCSTS_R(crate::FieldReader); +impl RRCSTS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RRCSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRCSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWCSTS` reader - MTL Rx FIFO Write Controller Active Status"] +pub struct RWCSTS_R(crate::FieldReader); +impl RWCSTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RWCSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWCSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFCFCSTS` reader - MAC Receive Frame FIFO Controller Status"] +pub struct RFCFCSTS_R(crate::FieldReader); +impl RFCFCSTS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RFCFCSTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFCFCSTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RPESTS` reader - MAC GMII or MII Receive Protocol Engine Status"] +pub struct RPESTS_R(crate::FieldReader); +impl RPESTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RPESTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RPESTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 25 - MTL TxStatus FIFO Full Status"] + #[inline(always)] + pub fn txstsfsts(&self) -> TXSTSFSTS_R { + TXSTSFSTS_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 24 - MTL Tx FIFO Not Empty Status"] + #[inline(always)] + pub fn txfsts(&self) -> TXFSTS_R { + TXFSTS_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 22 - MTL Tx FIFO Write Controller Status"] + #[inline(always)] + pub fn twcsts(&self) -> TWCSTS_R { + TWCSTS_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bits 20:21 - MTL Tx FIFO Read Controller Status"] + #[inline(always)] + pub fn trcsts(&self) -> TRCSTS_R { + TRCSTS_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 19 - MAC Transmitter in Pause"] + #[inline(always)] + pub fn txpaused(&self) -> TXPAUSED_R { + TXPAUSED_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bits 17:18 - PAC Transmit Frame Controller Status"] + #[inline(always)] + pub fn tfcsts(&self) -> TFCSTS_R { + TFCSTS_R::new(((self.bits >> 17) & 0x03) as u8) + } + #[doc = "Bit 16 - MAC GMII or MII Transmit Protocol Engine Status"] + #[inline(always)] + pub fn tpests(&self) -> TPESTS_R { + TPESTS_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 8:9 - MTL RxFIFO Fill-Level Status"] + #[inline(always)] + pub fn rxfsts(&self) -> RXFSTS_R { + RXFSTS_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 5:6 - MTL RxFIFO Read Controller State"] + #[inline(always)] + pub fn rrcsts(&self) -> RRCSTS_R { + RRCSTS_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bit 4 - MTL Rx FIFO Write Controller Active Status"] + #[inline(always)] + pub fn rwcsts(&self) -> RWCSTS_R { + RWCSTS_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 1:2 - MAC Receive Frame FIFO Controller Status"] + #[inline(always)] + pub fn rfcfcsts(&self) -> RFCFCSTS_R { + RFCFCSTS_R::new(((self.bits >> 1) & 0x03) as u8) + } + #[doc = "Bit 0 - MAC GMII or MII Receive Protocol Engine Status"] + #[inline(always)] + pub fn rpests(&self) -> RPESTS_R { + RPESTS_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Gives the status of the various internal blocks for debugging\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_debug](index.html) module"] +pub struct MAC_DEBUG_SPEC; +impl crate::RegisterSpec for MAC_DEBUG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_debug::R](R) reader structure"] +impl crate::Readable for MAC_DEBUG_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MAC_DEBUG to value 0"] +impl crate::Resettable for MAC_DEBUG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_flow_ctrl.rs b/src/eth/mac_flow_ctrl.rs new file mode 100644 index 0000000..190009d --- /dev/null +++ b/src/eth/mac_flow_ctrl.rs @@ -0,0 +1,375 @@ +#[doc = "Register `MAC_FLOW_CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_FLOW_CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PT` reader - Pause time"] +pub struct PT_R(crate::FieldReader); +impl PT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + PT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PT` writer - Pause time"] +pub struct PT_W<'a> { + w: &'a mut W, +} +impl<'a> PT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xffff << 16)) | ((value as u32 & 0xffff) << 16); + self.w + } +} +#[doc = "Field `DZPQ` reader - Disable Zero-Quanta Pause"] +pub struct DZPQ_R(crate::FieldReader); +impl DZPQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DZPQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DZPQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DZPQ` writer - Disable Zero-Quanta Pause"] +pub struct DZPQ_W<'a> { + w: &'a mut W, +} +impl<'a> DZPQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PLT` reader - Pause Low Threshold"] +pub struct PLT_R(crate::FieldReader); +impl PLT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLT` writer - Pause Low Threshold"] +pub struct PLT_W<'a> { + w: &'a mut W, +} +impl<'a> PLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `UP` reader - Unicast Pause Frame Detect"] +pub struct UP_R(crate::FieldReader); +impl UP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UP` writer - Unicast Pause Frame Detect"] +pub struct UP_W<'a> { + w: &'a mut W, +} +impl<'a> UP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RFE` reader - Receive Flow Control Enable"] +pub struct RFE_R(crate::FieldReader); +impl RFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFE` writer - Receive Flow Control Enable"] +pub struct RFE_W<'a> { + w: &'a mut W, +} +impl<'a> RFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TFE` reader - Transmit Flow Control Enable"] +pub struct TFE_R(crate::FieldReader); +impl TFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TFE` writer - Transmit Flow Control Enable"] +pub struct TFE_W<'a> { + w: &'a mut W, +} +impl<'a> TFE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `FCB_BPA` reader - Flow Control Busy or Backpressure Activate"] +pub struct FCB_BPA_R(crate::FieldReader); +impl FCB_BPA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FCB_BPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCB_BPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCB_BPA` writer - Flow Control Busy or Backpressure Activate"] +pub struct FCB_BPA_W<'a> { + w: &'a mut W, +} +impl<'a> FCB_BPA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bits 16:31 - Pause time"] + #[inline(always)] + pub fn pt(&self) -> PT_R { + PT_R::new(((self.bits >> 16) & 0xffff) as u16) + } + #[doc = "Bit 7 - Disable Zero-Quanta Pause"] + #[inline(always)] + pub fn dzpq(&self) -> DZPQ_R { + DZPQ_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Pause Low Threshold"] + #[inline(always)] + pub fn plt(&self) -> PLT_R { + PLT_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 3 - Unicast Pause Frame Detect"] + #[inline(always)] + pub fn up(&self) -> UP_R { + UP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Flow Control Enable"] + #[inline(always)] + pub fn rfe(&self) -> RFE_R { + RFE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Flow Control Enable"] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Flow Control Busy or Backpressure Activate"] + #[inline(always)] + pub fn fcb_bpa(&self) -> FCB_BPA_R { + FCB_BPA_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 16:31 - Pause time"] + #[inline(always)] + pub fn pt(&mut self) -> PT_W { + PT_W { w: self } + } + #[doc = "Bit 7 - Disable Zero-Quanta Pause"] + #[inline(always)] + pub fn dzpq(&mut self) -> DZPQ_W { + DZPQ_W { w: self } + } + #[doc = "Bits 4:5 - Pause Low Threshold"] + #[inline(always)] + pub fn plt(&mut self) -> PLT_W { + PLT_W { w: self } + } + #[doc = "Bit 3 - Unicast Pause Frame Detect"] + #[inline(always)] + pub fn up(&mut self) -> UP_W { + UP_W { w: self } + } + #[doc = "Bit 2 - Receive Flow Control Enable"] + #[inline(always)] + pub fn rfe(&mut self) -> RFE_W { + RFE_W { w: self } + } + #[doc = "Bit 1 - Transmit Flow Control Enable"] + #[inline(always)] + pub fn tfe(&mut self) -> TFE_W { + TFE_W { w: self } + } + #[doc = "Bit 0 - Flow Control Busy or Backpressure Activate"] + #[inline(always)] + pub fn fcb_bpa(&mut self) -> FCB_BPA_W { + FCB_BPA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Controls the generation of control frames\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_flow_ctrl](index.html) module"] +pub struct MAC_FLOW_CTRL_SPEC; +impl crate::RegisterSpec for MAC_FLOW_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_flow_ctrl::R](R) reader structure"] +impl crate::Readable for MAC_FLOW_CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_flow_ctrl::W](W) writer structure"] +impl crate::Writable for MAC_FLOW_CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_FLOW_CTRL to value 0"] +impl crate::Resettable for MAC_FLOW_CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_frame_fltr.rs b/src/eth/mac_frame_fltr.rs new file mode 100644 index 0000000..2ca0e7c --- /dev/null +++ b/src/eth/mac_frame_fltr.rs @@ -0,0 +1,667 @@ +#[doc = "Register `MAC_FRAME_FLTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_FRAME_FLTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RA` reader - Receive All"] +pub struct RA_R(crate::FieldReader); +impl RA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RA` writer - Receive All"] +pub struct RA_W<'a> { + w: &'a mut W, +} +impl<'a> RA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +#[doc = "Field `DNTU` reader - Drop non TCP/UDP over IP Frames"] +pub struct DNTU_R(crate::FieldReader); +impl DNTU_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DNTU_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DNTU_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DNTU` writer - Drop non TCP/UDP over IP Frames"] +pub struct DNTU_W<'a> { + w: &'a mut W, +} +impl<'a> DNTU_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `VFTE` reader - VLAN Tag Filter Enable"] +pub struct VFTE_R(crate::FieldReader); +impl VFTE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VFTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VFTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VFTE` writer - VLAN Tag Filter Enable"] +pub struct VFTE_W<'a> { + w: &'a mut W, +} +impl<'a> VFTE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `HDF` reader - Hash or Perfect Filter"] +pub struct HDF_R(crate::FieldReader); +impl HDF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HDF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HDF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HDF` writer - Hash or Perfect Filter"] +pub struct HDF_W<'a> { + w: &'a mut W, +} +impl<'a> HDF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SAF` reader - Source Address Filter Enable"] +pub struct SAF_R(crate::FieldReader); +impl SAF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAF` writer - Source Address Filter Enable"] +pub struct SAF_W<'a> { + w: &'a mut W, +} +impl<'a> SAF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SAIF` reader - SA Inverse Filtering"] +pub struct SAIF_R(crate::FieldReader); +impl SAIF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SAIF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAIF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAIF` writer - SA Inverse Filtering"] +pub struct SAIF_W<'a> { + w: &'a mut W, +} +impl<'a> SAIF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `PCF` reader - Pass Control Frames"] +pub struct PCF_R(crate::FieldReader); +impl PCF_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PCF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PCF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PCF` writer - Pass Control Frames"] +pub struct PCF_W<'a> { + w: &'a mut W, +} +impl<'a> PCF_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `DBF` reader - Disable Broadcast Frames"] +pub struct DBF_R(crate::FieldReader); +impl DBF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DBF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBF` writer - Disable Broadcast Frames"] +pub struct DBF_W<'a> { + w: &'a mut W, +} +impl<'a> DBF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `PM` reader - Pass All Multicast"] +pub struct PM_R(crate::FieldReader); +impl PM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM` writer - Pass All Multicast"] +pub struct PM_W<'a> { + w: &'a mut W, +} +impl<'a> PM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DAIF` reader - DA Inverse Filtering"] +pub struct DAIF_R(crate::FieldReader); +impl DAIF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAIF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAIF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAIF` writer - DA Inverse Filtering"] +pub struct DAIF_W<'a> { + w: &'a mut W, +} +impl<'a> DAIF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMC` reader - Hash Multicast"] +pub struct HMC_R(crate::FieldReader); +impl HMC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HMC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMC` writer - Hash Multicast"] +pub struct HMC_W<'a> { + w: &'a mut W, +} +impl<'a> HMC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HUC` reader - Hash Unicast"] +pub struct HUC_R(crate::FieldReader); +impl HUC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + HUC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HUC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HUC` writer - Hash Unicast"] +pub struct HUC_W<'a> { + w: &'a mut W, +} +impl<'a> HUC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PR` reader - Promiscuous Mode"] +pub struct PR_R(crate::FieldReader); +impl PR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PR` writer - Promiscuous Mode"] +pub struct PR_W<'a> { + w: &'a mut W, +} +impl<'a> PR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 31 - Receive All"] + #[inline(always)] + pub fn ra(&self) -> RA_R { + RA_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bit 21 - Drop non TCP/UDP over IP Frames"] + #[inline(always)] + pub fn dntu(&self) -> DNTU_R { + DNTU_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 16 - VLAN Tag Filter Enable"] + #[inline(always)] + pub fn vfte(&self) -> VFTE_R { + VFTE_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 10 - Hash or Perfect Filter"] + #[inline(always)] + pub fn hdf(&self) -> HDF_R { + HDF_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - Source Address Filter Enable"] + #[inline(always)] + pub fn saf(&self) -> SAF_R { + SAF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - SA Inverse Filtering"] + #[inline(always)] + pub fn saif(&self) -> SAIF_R { + SAIF_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 6:7 - Pass Control Frames"] + #[inline(always)] + pub fn pcf(&self) -> PCF_R { + PCF_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bit 5 - Disable Broadcast Frames"] + #[inline(always)] + pub fn dbf(&self) -> DBF_R { + DBF_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Pass All Multicast"] + #[inline(always)] + pub fn pm(&self) -> PM_R { + PM_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - DA Inverse Filtering"] + #[inline(always)] + pub fn daif(&self) -> DAIF_R { + DAIF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Hash Multicast"] + #[inline(always)] + pub fn hmc(&self) -> HMC_R { + HMC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Hash Unicast"] + #[inline(always)] + pub fn huc(&self) -> HUC_R { + HUC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Promiscuous Mode"] + #[inline(always)] + pub fn pr(&self) -> PR_R { + PR_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 31 - Receive All"] + #[inline(always)] + pub fn ra(&mut self) -> RA_W { + RA_W { w: self } + } + #[doc = "Bit 21 - Drop non TCP/UDP over IP Frames"] + #[inline(always)] + pub fn dntu(&mut self) -> DNTU_W { + DNTU_W { w: self } + } + #[doc = "Bit 16 - VLAN Tag Filter Enable"] + #[inline(always)] + pub fn vfte(&mut self) -> VFTE_W { + VFTE_W { w: self } + } + #[doc = "Bit 10 - Hash or Perfect Filter"] + #[inline(always)] + pub fn hdf(&mut self) -> HDF_W { + HDF_W { w: self } + } + #[doc = "Bit 9 - Source Address Filter Enable"] + #[inline(always)] + pub fn saf(&mut self) -> SAF_W { + SAF_W { w: self } + } + #[doc = "Bit 8 - SA Inverse Filtering"] + #[inline(always)] + pub fn saif(&mut self) -> SAIF_W { + SAIF_W { w: self } + } + #[doc = "Bits 6:7 - Pass Control Frames"] + #[inline(always)] + pub fn pcf(&mut self) -> PCF_W { + PCF_W { w: self } + } + #[doc = "Bit 5 - Disable Broadcast Frames"] + #[inline(always)] + pub fn dbf(&mut self) -> DBF_W { + DBF_W { w: self } + } + #[doc = "Bit 4 - Pass All Multicast"] + #[inline(always)] + pub fn pm(&mut self) -> PM_W { + PM_W { w: self } + } + #[doc = "Bit 3 - DA Inverse Filtering"] + #[inline(always)] + pub fn daif(&mut self) -> DAIF_W { + DAIF_W { w: self } + } + #[doc = "Bit 2 - Hash Multicast"] + #[inline(always)] + pub fn hmc(&mut self) -> HMC_W { + HMC_W { w: self } + } + #[doc = "Bit 1 - Hash Unicast"] + #[inline(always)] + pub fn huc(&mut self) -> HUC_W { + HUC_W { w: self } + } + #[doc = "Bit 0 - Promiscuous Mode"] + #[inline(always)] + pub fn pr(&mut self) -> PR_W { + PR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the frame filtering controls\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_frame_fltr](index.html) module"] +pub struct MAC_FRAME_FLTR_SPEC; +impl crate::RegisterSpec for MAC_FRAME_FLTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_frame_fltr::R](R) reader structure"] +impl crate::Readable for MAC_FRAME_FLTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_frame_fltr::W](W) writer structure"] +impl crate::Writable for MAC_FRAME_FLTR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_FRAME_FLTR to value 0"] +impl crate::Resettable for MAC_FRAME_FLTR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_gmii_addr.rs b/src/eth/mac_gmii_addr.rs new file mode 100644 index 0000000..a072474 --- /dev/null +++ b/src/eth/mac_gmii_addr.rs @@ -0,0 +1,271 @@ +#[doc = "Register `MAC_GMII_ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_GMII_ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PA` reader - Physical Layer Address"] +pub struct PA_R(crate::FieldReader); +impl PA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PA` writer - Physical Layer Address"] +pub struct PA_W<'a> { + w: &'a mut W, +} +impl<'a> PA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 11)) | ((value as u32 & 0x1f) << 11); + self.w + } +} +#[doc = "Field `GR` reader - GMII Register"] +pub struct GR_R(crate::FieldReader); +impl GR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + GR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GR` writer - GMII Register"] +pub struct GR_W<'a> { + w: &'a mut W, +} +impl<'a> GR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1f << 6)) | ((value as u32 & 0x1f) << 6); + self.w + } +} +#[doc = "Field `CR` reader - CSR Clock Range"] +pub struct CR_R(crate::FieldReader); +impl CR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CR` writer - CSR Clock Range"] +pub struct CR_W<'a> { + w: &'a mut W, +} +impl<'a> CR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 2)) | ((value as u32 & 0x0f) << 2); + self.w + } +} +#[doc = "Field `GW` reader - GMII Write/Read"] +pub struct GW_R(crate::FieldReader); +impl GW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GW` writer - GMII Write/Read"] +pub struct GW_W<'a> { + w: &'a mut W, +} +impl<'a> GW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `GB` reader - GMII Busy"] +pub struct GB_R(crate::FieldReader); +impl GB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + GB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GB` writer - GMII Busy"] +pub struct GB_W<'a> { + w: &'a mut W, +} +impl<'a> GB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bits 11:15 - Physical Layer Address"] + #[inline(always)] + pub fn pa(&self) -> PA_R { + PA_R::new(((self.bits >> 11) & 0x1f) as u8) + } + #[doc = "Bits 6:10 - GMII Register"] + #[inline(always)] + pub fn gr(&self) -> GR_R { + GR_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 2:5 - CSR Clock Range"] + #[inline(always)] + pub fn cr(&self) -> CR_R { + CR_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 1 - GMII Write/Read"] + #[inline(always)] + pub fn gw(&self) -> GW_R { + GW_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - GMII Busy"] + #[inline(always)] + pub fn gb(&self) -> GB_R { + GB_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 11:15 - Physical Layer Address"] + #[inline(always)] + pub fn pa(&mut self) -> PA_W { + PA_W { w: self } + } + #[doc = "Bits 6:10 - GMII Register"] + #[inline(always)] + pub fn gr(&mut self) -> GR_W { + GR_W { w: self } + } + #[doc = "Bits 2:5 - CSR Clock Range"] + #[inline(always)] + pub fn cr(&mut self) -> CR_W { + CR_W { w: self } + } + #[doc = "Bit 1 - GMII Write/Read"] + #[inline(always)] + pub fn gw(&mut self) -> GW_W { + GW_W { w: self } + } + #[doc = "Bit 0 - GMII Busy"] + #[inline(always)] + pub fn gb(&mut self) -> GB_W { + GB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Controls the management cycles to an external PHY\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_gmii_addr](index.html) module"] +pub struct MAC_GMII_ADDR_SPEC; +impl crate::RegisterSpec for MAC_GMII_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_gmii_addr::R](R) reader structure"] +impl crate::Readable for MAC_GMII_ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_gmii_addr::W](W) writer structure"] +impl crate::Writable for MAC_GMII_ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_GMII_ADDR to value 0"] +impl crate::Resettable for MAC_GMII_ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_gmii_data.rs b/src/eth/mac_gmii_data.rs new file mode 100644 index 0000000..4565f2e --- /dev/null +++ b/src/eth/mac_gmii_data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `MAC_GMII_DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_GMII_DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GD` reader - GMII Data"] +pub struct GD_R(crate::FieldReader); +impl GD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + GD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GD` writer - GMII Data"] +pub struct GD_W<'a> { + w: &'a mut W, +} +impl<'a> GD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - GMII Data"] + #[inline(always)] + pub fn gd(&self) -> GD_R { + GD_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - GMII Data"] + #[inline(always)] + pub fn gd(&mut self) -> GD_W { + GD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the data to be written to or read from the PHY register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_gmii_data](index.html) module"] +pub struct MAC_GMII_DATA_SPEC; +impl crate::RegisterSpec for MAC_GMII_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_gmii_data::R](R) reader structure"] +impl crate::Readable for MAC_GMII_DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_gmii_data::W](W) writer structure"] +impl crate::Writable for MAC_GMII_DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_GMII_DATA to value 0"] +impl crate::Resettable for MAC_GMII_DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_intr_mask.rs b/src/eth/mac_intr_mask.rs new file mode 100644 index 0000000..3a8df9f --- /dev/null +++ b/src/eth/mac_intr_mask.rs @@ -0,0 +1,113 @@ +#[doc = "Register `MAC_INTR_MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_INTR_MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSIM` reader - Timestamp Interrupt Mask"] +pub struct TSIM_R(crate::FieldReader); +impl TSIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSIM` writer - Timestamp Interrupt Mask"] +pub struct TSIM_W<'a> { + w: &'a mut W, +} +impl<'a> TSIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 9 - Timestamp Interrupt Mask"] + #[inline(always)] + pub fn tsim(&self) -> TSIM_R { + TSIM_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 9 - Timestamp Interrupt Mask"] + #[inline(always)] + pub fn tsim(&mut self) -> TSIM_W { + TSIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Contains the masks for generating interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_intr_mask](index.html) module"] +pub struct MAC_INTR_MASK_SPEC; +impl crate::RegisterSpec for MAC_INTR_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_intr_mask::R](R) reader structure"] +impl crate::Readable for MAC_INTR_MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_intr_mask::W](W) writer structure"] +impl crate::Writable for MAC_INTR_MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_INTR_MASK to value 0"] +impl crate::Resettable for MAC_INTR_MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_intr_stat.rs b/src/eth/mac_intr_stat.rs new file mode 100644 index 0000000..b4de8f7 --- /dev/null +++ b/src/eth/mac_intr_stat.rs @@ -0,0 +1,133 @@ +#[doc = "Register `MAC_INTR_STAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TSIS` reader - Timestamp Interrupt Status"] +pub struct TSIS_R(crate::FieldReader); +impl TSIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MMCRXIPIS` reader - MMC Receive Checksum Offload Interrupt Status"] +pub struct MMCRXIPIS_R(crate::FieldReader); +impl MMCRXIPIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MMCRXIPIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MMCRXIPIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MMCTXIS` reader - MMC Transmit Interrupt Status"] +pub struct MMCTXIS_R(crate::FieldReader); +impl MMCTXIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MMCTXIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MMCTXIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MMCRXIS` reader - MMC Receive Interrupt Status"] +pub struct MMCRXIS_R(crate::FieldReader); +impl MMCRXIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MMCRXIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MMCRXIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MMCIS` reader - MMC Interrupt Status"] +pub struct MMCIS_R(crate::FieldReader); +impl MMCIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MMCIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MMCIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 9 - Timestamp Interrupt Status"] + #[inline(always)] + pub fn tsis(&self) -> TSIS_R { + TSIS_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 7 - MMC Receive Checksum Offload Interrupt Status"] + #[inline(always)] + pub fn mmcrxipis(&self) -> MMCRXIPIS_R { + MMCRXIPIS_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - MMC Transmit Interrupt Status"] + #[inline(always)] + pub fn mmctxis(&self) -> MMCTXIS_R { + MMCTXIS_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - MMC Receive Interrupt Status"] + #[inline(always)] + pub fn mmcrxis(&self) -> MMCRXIS_R { + MMCRXIS_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - MMC Interrupt Status"] + #[inline(always)] + pub fn mmcis(&self) -> MMCIS_R { + MMCIS_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +#[doc = "Contains the interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_intr_stat](index.html) module"] +pub struct MAC_INTR_STAT_SPEC; +impl crate::RegisterSpec for MAC_INTR_STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_intr_stat::R](R) reader structure"] +impl crate::Readable for MAC_INTR_STAT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MAC_INTR_STAT to value 0"] +impl crate::Resettable for MAC_INTR_STAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_vlan_tag.rs b/src/eth/mac_vlan_tag.rs new file mode 100644 index 0000000..5d74de0 --- /dev/null +++ b/src/eth/mac_vlan_tag.rs @@ -0,0 +1,244 @@ +#[doc = "Register `MAC_VLAN_TAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_VLAN_TAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ESVL` reader - Enable S-VLAN"] +pub struct ESVL_R(crate::FieldReader); +impl ESVL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ESVL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ESVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ESVL` writer - Enable S-VLAN"] +pub struct ESVL_W<'a> { + w: &'a mut W, +} +impl<'a> ESVL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `VTIM` reader - VLAN Tag Inverse Match Enable"] +pub struct VTIM_R(crate::FieldReader); +impl VTIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VTIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VTIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VTIM` writer - VLAN Tag Inverse Match Enable"] +pub struct VTIM_W<'a> { + w: &'a mut W, +} +impl<'a> VTIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ETV` reader - Enable 12-Bit VLAN Tag Comparison"] +pub struct ETV_R(crate::FieldReader); +impl ETV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ETV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ETV` writer - Enable 12-Bit VLAN Tag Comparison"] +pub struct ETV_W<'a> { + w: &'a mut W, +} +impl<'a> ETV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `VL` reader - VLAN Tag identifier for Receive Frames"] +pub struct VL_R(crate::FieldReader); +impl VL_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VL` writer - VLAN Tag identifier for Receive Frames"] +pub struct VL_W<'a> { + w: &'a mut W, +} +impl<'a> VL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bit 18 - Enable S-VLAN"] + #[inline(always)] + pub fn esvl(&self) -> ESVL_R { + ESVL_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 17 - VLAN Tag Inverse Match Enable"] + #[inline(always)] + pub fn vtim(&self) -> VTIM_R { + VTIM_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison"] + #[inline(always)] + pub fn etv(&self) -> ETV_R { + ETV_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 0:15 - VLAN Tag identifier for Receive Frames"] + #[inline(always)] + pub fn vl(&self) -> VL_R { + VL_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 18 - Enable S-VLAN"] + #[inline(always)] + pub fn esvl(&mut self) -> ESVL_W { + ESVL_W { w: self } + } + #[doc = "Bit 17 - VLAN Tag Inverse Match Enable"] + #[inline(always)] + pub fn vtim(&mut self) -> VTIM_W { + VTIM_W { w: self } + } + #[doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison"] + #[inline(always)] + pub fn etv(&mut self) -> ETV_W { + ETV_W { w: self } + } + #[doc = "Bits 0:15 - VLAN Tag identifier for Receive Frames"] + #[inline(always)] + pub fn vl(&mut self) -> VL_W { + VL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Identifies IEEE 802.1Q VLAN type frames\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_vlan_tag](index.html) module"] +pub struct MAC_VLAN_TAG_SPEC; +impl crate::RegisterSpec for MAC_VLAN_TAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_vlan_tag::R](R) reader structure"] +impl crate::Readable for MAC_VLAN_TAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_vlan_tag::W](W) writer structure"] +impl crate::Writable for MAC_VLAN_TAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_VLAN_TAG to value 0"] +impl crate::Resettable for MAC_VLAN_TAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mac_wdog_to.rs b/src/eth/mac_wdog_to.rs new file mode 100644 index 0000000..5feb0b8 --- /dev/null +++ b/src/eth/mac_wdog_to.rs @@ -0,0 +1,150 @@ +#[doc = "Register `MAC_WDOG_TO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MAC_WDOG_TO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PWE` reader - Programmable Watchdog Enable"] +pub struct PWE_R(crate::FieldReader); +impl PWE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PWE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PWE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PWE` writer - Programmable Watchdog Enable"] +pub struct PWE_W<'a> { + w: &'a mut W, +} +impl<'a> PWE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `WTO` reader - Watchdog Timeout"] +pub struct WTO_R(crate::FieldReader); +impl WTO_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + WTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WTO` writer - Watchdog Timeout"] +pub struct WTO_W<'a> { + w: &'a mut W, +} +impl<'a> WTO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3fff) | (value as u32 & 0x3fff); + self.w + } +} +impl R { + #[doc = "Bit 16 - Programmable Watchdog Enable"] + #[inline(always)] + pub fn pwe(&self) -> PWE_R { + PWE_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 0:13 - Watchdog Timeout"] + #[inline(always)] + pub fn wto(&self) -> WTO_R { + WTO_R::new((self.bits & 0x3fff) as u16) + } +} +impl W { + #[doc = "Bit 16 - Programmable Watchdog Enable"] + #[inline(always)] + pub fn pwe(&mut self) -> PWE_W { + PWE_W { w: self } + } + #[doc = "Bits 0:13 - Watchdog Timeout"] + #[inline(always)] + pub fn wto(&mut self) -> WTO_W { + WTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Controls the watchdog time-out for received frames\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mac_wdog_to](index.html) module"] +pub struct MAC_WDOG_TO_SPEC; +impl crate::RegisterSpec for MAC_WDOG_TO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mac_wdog_to::R](R) reader structure"] +impl crate::Readable for MAC_WDOG_TO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mac_wdog_to::W](W) writer structure"] +impl crate::Writable for MAC_WDOG_TO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MAC_WDOG_TO to value 0"] +impl crate::Resettable for MAC_WDOG_TO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mmc_cntrl.rs b/src/eth/mmc_cntrl.rs new file mode 100644 index 0000000..86070b6 --- /dev/null +++ b/src/eth/mmc_cntrl.rs @@ -0,0 +1,395 @@ +#[doc = "Register `MMC_CNTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MMC_CNTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `UCDBC` reader - Update MMC Counters for Dropped Broadcast Frames"] +pub struct UCDBC_R(crate::FieldReader); +impl UCDBC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UCDBC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UCDBC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UCDBC` writer - Update MMC Counters for Dropped Broadcast Frames"] +pub struct UCDBC_W<'a> { + w: &'a mut W, +} +impl<'a> UCDBC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CNTPRSTLVL` reader - Full-Half Preset"] +pub struct CNTPRSTLVL_R(crate::FieldReader); +impl CNTPRSTLVL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTPRSTLVL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTPRSTLVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTPRSTLVL` writer - Full-Half Preset"] +pub struct CNTPRSTLVL_W<'a> { + w: &'a mut W, +} +impl<'a> CNTPRSTLVL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `CNTPRST` reader - Counters Preset"] +pub struct CNTPRST_R(crate::FieldReader); +impl CNTPRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTPRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTPRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTPRST` writer - Counters Preset"] +pub struct CNTPRST_W<'a> { + w: &'a mut W, +} +impl<'a> CNTPRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CNTFREEZ` reader - MMC Counter Freeze"] +pub struct CNTFREEZ_R(crate::FieldReader); +impl CNTFREEZ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTFREEZ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTFREEZ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTFREEZ` writer - MMC Counter Freeze"] +pub struct CNTFREEZ_W<'a> { + w: &'a mut W, +} +impl<'a> CNTFREEZ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RSTONRD` reader - Reset on Read"] +pub struct RSTONRD_R(crate::FieldReader); +impl RSTONRD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RSTONRD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTONRD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTONRD` writer - Reset on Read"] +pub struct RSTONRD_W<'a> { + w: &'a mut W, +} +impl<'a> RSTONRD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CNTSTOPRO` reader - Counter Stop Rollover"] +pub struct CNTSTOPRO_R(crate::FieldReader); +impl CNTSTOPRO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTSTOPRO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTSTOPRO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSTOPRO` writer - Counter Stop Rollover"] +pub struct CNTSTOPRO_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSTOPRO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CNTRST` reader - Counters Reset"] +pub struct CNTRST_R(crate::FieldReader); +impl CNTRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTRST` writer - Counters Reset"] +pub struct CNTRST_W<'a> { + w: &'a mut W, +} +impl<'a> CNTRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 8 - Update MMC Counters for Dropped Broadcast Frames"] + #[inline(always)] + pub fn ucdbc(&self) -> UCDBC_R { + UCDBC_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 5 - Full-Half Preset"] + #[inline(always)] + pub fn cntprstlvl(&self) -> CNTPRSTLVL_R { + CNTPRSTLVL_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Counters Preset"] + #[inline(always)] + pub fn cntprst(&self) -> CNTPRST_R { + CNTPRST_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - MMC Counter Freeze"] + #[inline(always)] + pub fn cntfreez(&self) -> CNTFREEZ_R { + CNTFREEZ_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Reset on Read"] + #[inline(always)] + pub fn rstonrd(&self) -> RSTONRD_R { + RSTONRD_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Counter Stop Rollover"] + #[inline(always)] + pub fn cntstopro(&self) -> CNTSTOPRO_R { + CNTSTOPRO_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Counters Reset"] + #[inline(always)] + pub fn cntrst(&self) -> CNTRST_R { + CNTRST_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Update MMC Counters for Dropped Broadcast Frames"] + #[inline(always)] + pub fn ucdbc(&mut self) -> UCDBC_W { + UCDBC_W { w: self } + } + #[doc = "Bit 5 - Full-Half Preset"] + #[inline(always)] + pub fn cntprstlvl(&mut self) -> CNTPRSTLVL_W { + CNTPRSTLVL_W { w: self } + } + #[doc = "Bit 4 - Counters Preset"] + #[inline(always)] + pub fn cntprst(&mut self) -> CNTPRST_W { + CNTPRST_W { w: self } + } + #[doc = "Bit 3 - MMC Counter Freeze"] + #[inline(always)] + pub fn cntfreez(&mut self) -> CNTFREEZ_W { + CNTFREEZ_W { w: self } + } + #[doc = "Bit 2 - Reset on Read"] + #[inline(always)] + pub fn rstonrd(&mut self) -> RSTONRD_W { + RSTONRD_W { w: self } + } + #[doc = "Bit 1 - Counter Stop Rollover"] + #[inline(always)] + pub fn cntstopro(&mut self) -> CNTSTOPRO_W { + CNTSTOPRO_W { w: self } + } + #[doc = "Bit 0 - Counters Reset"] + #[inline(always)] + pub fn cntrst(&mut self) -> CNTRST_W { + CNTRST_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MMC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmc_cntrl](index.html) module"] +pub struct MMC_CNTRL_SPEC; +impl crate::RegisterSpec for MMC_CNTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mmc_cntrl::R](R) reader structure"] +impl crate::Readable for MMC_CNTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mmc_cntrl::W](W) writer structure"] +impl crate::Writable for MMC_CNTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MMC_CNTRL to value 0"] +impl crate::Resettable for MMC_CNTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mmc_intr_mask_rx.rs b/src/eth/mmc_intr_mask_rx.rs new file mode 100644 index 0000000..1a929c8 --- /dev/null +++ b/src/eth/mmc_intr_mask_rx.rs @@ -0,0 +1,1288 @@ +#[doc = "Register `MMC_INTR_MASK_RX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MMC_INTR_MASK_RX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXCTRLFIM` reader - MMC Receive Control Frame Counter Interrupt Mask"] +pub struct RXCTRLFIM_R(crate::FieldReader); +impl RXCTRLFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXCTRLFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXCTRLFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXCTRLFIM` writer - MMC Receive Control Frame Counter Interrupt Mask"] +pub struct RXCTRLFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXCTRLFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `RXRCVERRFIM` reader - MMC Receive Error Frame Counter Interrupt Mask"] +pub struct RXRCVERRFIM_R(crate::FieldReader); +impl RXRCVERRFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRCVERRFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRCVERRFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRCVERRFIM` writer - MMC Receive Error Frame Counter Interrupt Mask"] +pub struct RXRCVERRFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXRCVERRFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `RXWDOGFIM` reader - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] +pub struct RXWDOGFIM_R(crate::FieldReader); +impl RXWDOGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXWDOGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXWDOGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXWDOGFIM` writer - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] +pub struct RXWDOGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXWDOGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `RXVLANGBFIM` reader - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] +pub struct RXVLANGBFIM_R(crate::FieldReader); +impl RXVLANGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXVLANGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXVLANGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXVLANGBFIM` writer - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] +pub struct RXVLANGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXVLANGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `RXFOVFIM` reader - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] +pub struct RXFOVFIM_R(crate::FieldReader); +impl RXFOVFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFOVFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFOVFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFOVFIM` writer - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] +pub struct RXFOVFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXFOVFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `RXPAUSFIM` reader - MMC Receive Pause Frame Counter Interrupt Mask"] +pub struct RXPAUSFIM_R(crate::FieldReader); +impl RXPAUSFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXPAUSFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPAUSFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPAUSFIM` writer - MMC Receive Pause Frame Counter Interrupt Mask"] +pub struct RXPAUSFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXPAUSFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `RXORANGEFIM` reader - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] +pub struct RXORANGEFIM_R(crate::FieldReader); +impl RXORANGEFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXORANGEFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXORANGEFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXORANGEFIM` writer - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] +pub struct RXORANGEFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXORANGEFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `RXLENERFIM` reader - MMC Receive Length Error Frame Counter Interrupt Mask"] +pub struct RXLENERFIM_R(crate::FieldReader); +impl RXLENERFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXLENERFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXLENERFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXLENERFIM` writer - MMC Receive Length Error Frame Counter Interrupt Mask"] +pub struct RXLENERFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXLENERFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `RXUCGFIM` reader - MMC Receive Unicast Good Frame Counter Interrupt Mask"] +pub struct RXUCGFIM_R(crate::FieldReader); +impl RXUCGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXUCGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXUCGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXUCGFIM` writer - MMC Receive Unicast Good Frame Counter Interrupt Mask"] +pub struct RXUCGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXUCGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `RX1024TMAXOCTGBFIM` reader - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] +pub struct RX1024TMAXOCTGBFIM_R(crate::FieldReader); +impl RX1024TMAXOCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX1024TMAXOCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX1024TMAXOCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX1024TMAXOCTGBFIM` writer - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] +pub struct RX1024TMAXOCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RX1024TMAXOCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RX512T1023OCTGBFIM` reader - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX512T1023OCTGBFIM_R(crate::FieldReader); +impl RX512T1023OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX512T1023OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX512T1023OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX512T1023OCTGBFIM` writer - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX512T1023OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RX512T1023OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `RX256T511OCTGBFIM` reader - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX256T511OCTGBFIM_R(crate::FieldReader); +impl RX256T511OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX256T511OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX256T511OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX256T511OCTGBFIM` writer - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX256T511OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RX256T511OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RX128T255OCTGBFIM` reader - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX128T255OCTGBFIM_R(crate::FieldReader); +impl RX128T255OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX128T255OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX128T255OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX128T255OCTGBFIM` writer - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX128T255OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RX128T255OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `RX65T127OCTGBFIM` reader - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX65T127OCTGBFIM_R(crate::FieldReader); +impl RX65T127OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX65T127OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX65T127OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX65T127OCTGBFIM` writer - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX65T127OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RX65T127OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RX64OCTGBFIM` reader - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX64OCTGBFIM_R(crate::FieldReader); +impl RX64OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX64OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX64OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX64OCTGBFIM` writer - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct RX64OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RX64OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `RXOSIZEGFIM` reader - MMC Receive Oversize Good Frame Counter Interrupt Mask"] +pub struct RXOSIZEGFIM_R(crate::FieldReader); +impl RXOSIZEGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOSIZEGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOSIZEGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOSIZEGFIM` writer - MMC Receive Oversize Good Frame Counter Interrupt Mask"] +pub struct RXOSIZEGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXOSIZEGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `RXUSIZEGFIM` reader - MMC Receive Undersize Good Frame Counter Interrupt Mask"] +pub struct RXUSIZEGFIM_R(crate::FieldReader); +impl RXUSIZEGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXUSIZEGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXUSIZEGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXUSIZEGFIM` writer - MMC Receive Undersize Good Frame Counter Interrupt Mask"] +pub struct RXUSIZEGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXUSIZEGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `RXJABERFIM` reader - MMC Receive Jabber Error Frame Counter Interrupt Mask"] +pub struct RXJABERFIM_R(crate::FieldReader); +impl RXJABERFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXJABERFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXJABERFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXJABERFIM` writer - MMC Receive Jabber Error Frame Counter Interrupt Mask"] +pub struct RXJABERFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXJABERFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RXRUNTFIM` reader - MMC Receive Runt Frame Counter Interrupt Mask"] +pub struct RXRUNTFIM_R(crate::FieldReader); +impl RXRUNTFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRUNTFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRUNTFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRUNTFIM` writer - MMC Receive Runt Frame Counter Interrupt Mask"] +pub struct RXRUNTFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXRUNTFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RXALGNERFIM` reader - MMC Receive Alignment Error Frame Counter Interrupt Mask"] +pub struct RXALGNERFIM_R(crate::FieldReader); +impl RXALGNERFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXALGNERFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXALGNERFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXALGNERFIM` writer - MMC Receive Alignment Error Frame Counter Interrupt Mask"] +pub struct RXALGNERFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXALGNERFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RXCRCERFIM` reader - MMC Receive CRC Error Frame Counter Interrupt Mask"] +pub struct RXCRCERFIM_R(crate::FieldReader); +impl RXCRCERFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXCRCERFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXCRCERFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXCRCERFIM` writer - MMC Receive CRC Error Frame Counter Interrupt Mask"] +pub struct RXCRCERFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXCRCERFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RXMCGFIM` reader - MMC Receive Multicast Good Frame Counter Interrupt Mask"] +pub struct RXMCGFIM_R(crate::FieldReader); +impl RXMCGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXMCGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXMCGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXMCGFIM` writer - MMC Receive Multicast Good Frame Counter Interrupt Mask"] +pub struct RXMCGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXMCGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBCGFIM` reader - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] +pub struct RXBCGFIM_R(crate::FieldReader); +impl RXBCGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBCGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBCGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBCGFIM` writer - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] +pub struct RXBCGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXBCGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXGOCTIM` reader - MMC Receive Good Octet Counter Interrupt Mask"] +pub struct RXGOCTIM_R(crate::FieldReader); +impl RXGOCTIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXGOCTIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXGOCTIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXGOCTIM` writer - MMC Receive Good Octet Counter Interrupt Mask"] +pub struct RXGOCTIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXGOCTIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXGBOCTIM` reader - MMC Receive Good Bad Octet Counter Interrupt Mask."] +pub struct RXGBOCTIM_R(crate::FieldReader); +impl RXGBOCTIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXGBOCTIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXGBOCTIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXGBOCTIM` writer - MMC Receive Good Bad Octet Counter Interrupt Mask."] +pub struct RXGBOCTIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXGBOCTIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXGBFRMIM` reader - MMC Receive Good Bad Frame Counter Interrupt Mask"] +pub struct RXGBFRMIM_R(crate::FieldReader); +impl RXGBFRMIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXGBFRMIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXGBFRMIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXGBFRMIM` writer - MMC Receive Good Bad Frame Counter Interrupt Mask"] +pub struct RXGBFRMIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXGBFRMIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxctrlfim(&self) -> RXCTRLFIM_R { + RXCTRLFIM_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxrcverrfim(&self) -> RXRCVERRFIM_R { + RXRCVERRFIM_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxwdogfim(&self) -> RXWDOGFIM_R { + RXWDOGFIM_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxvlangbfim(&self) -> RXVLANGBFIM_R { + RXVLANGBFIM_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxfovfim(&self) -> RXFOVFIM_R { + RXFOVFIM_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxpausfim(&self) -> RXPAUSFIM_R { + RXPAUSFIM_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxorangefim(&self) -> RXORANGEFIM_R { + RXORANGEFIM_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxlenerfim(&self) -> RXLENERFIM_R { + RXLENERFIM_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxucgfim(&self) -> RXUCGFIM_R { + RXUCGFIM_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] + #[inline(always)] + pub fn rx1024tmaxoctgbfim(&self) -> RX1024TMAXOCTGBFIM_R { + RX1024TMAXOCTGBFIM_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx512t1023octgbfim(&self) -> RX512T1023OCTGBFIM_R { + RX512T1023OCTGBFIM_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx256t511octgbfim(&self) -> RX256T511OCTGBFIM_R { + RX256T511OCTGBFIM_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx128t255octgbfim(&self) -> RX128T255OCTGBFIM_R { + RX128T255OCTGBFIM_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx65t127octgbfim(&self) -> RX65T127OCTGBFIM_R { + RX65T127OCTGBFIM_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx64octgbfim(&self) -> RX64OCTGBFIM_R { + RX64OCTGBFIM_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxosizegfim(&self) -> RXOSIZEGFIM_R { + RXOSIZEGFIM_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxusizegfim(&self) -> RXUSIZEGFIM_R { + RXUSIZEGFIM_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxjaberfim(&self) -> RXJABERFIM_R { + RXJABERFIM_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxruntfim(&self) -> RXRUNTFIM_R { + RXRUNTFIM_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxalgnerfim(&self) -> RXALGNERFIM_R { + RXALGNERFIM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxcrcerfim(&self) -> RXCRCERFIM_R { + RXCRCERFIM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxmcgfim(&self) -> RXMCGFIM_R { + RXMCGFIM_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxbcgfim(&self) -> RXBCGFIM_R { + RXBCGFIM_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgoctim(&self) -> RXGOCTIM_R { + RXGOCTIM_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Mask."] + #[inline(always)] + pub fn rxgboctim(&self) -> RXGBOCTIM_R { + RXGBOCTIM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgbfrmim(&self) -> RXGBFRMIM_R { + RXGBFRMIM_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxctrlfim(&mut self) -> RXCTRLFIM_W { + RXCTRLFIM_W { w: self } + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxrcverrfim(&mut self) -> RXRCVERRFIM_W { + RXRCVERRFIM_W { w: self } + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxwdogfim(&mut self) -> RXWDOGFIM_W { + RXWDOGFIM_W { w: self } + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxvlangbfim(&mut self) -> RXVLANGBFIM_W { + RXVLANGBFIM_W { w: self } + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxfovfim(&mut self) -> RXFOVFIM_W { + RXFOVFIM_W { w: self } + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxpausfim(&mut self) -> RXPAUSFIM_W { + RXPAUSFIM_W { w: self } + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxorangefim(&mut self) -> RXORANGEFIM_W { + RXORANGEFIM_W { w: self } + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxlenerfim(&mut self) -> RXLENERFIM_W { + RXLENERFIM_W { w: self } + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxucgfim(&mut self) -> RXUCGFIM_W { + RXUCGFIM_W { w: self } + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] + #[inline(always)] + pub fn rx1024tmaxoctgbfim(&mut self) -> RX1024TMAXOCTGBFIM_W { + RX1024TMAXOCTGBFIM_W { w: self } + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx512t1023octgbfim(&mut self) -> RX512T1023OCTGBFIM_W { + RX512T1023OCTGBFIM_W { w: self } + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx256t511octgbfim(&mut self) -> RX256T511OCTGBFIM_W { + RX256T511OCTGBFIM_W { w: self } + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx128t255octgbfim(&mut self) -> RX128T255OCTGBFIM_W { + RX128T255OCTGBFIM_W { w: self } + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx65t127octgbfim(&mut self) -> RX65T127OCTGBFIM_W { + RX65T127OCTGBFIM_W { w: self } + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx64octgbfim(&mut self) -> RX64OCTGBFIM_W { + RX64OCTGBFIM_W { w: self } + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxosizegfim(&mut self) -> RXOSIZEGFIM_W { + RXOSIZEGFIM_W { w: self } + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxusizegfim(&mut self) -> RXUSIZEGFIM_W { + RXUSIZEGFIM_W { w: self } + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxjaberfim(&mut self) -> RXJABERFIM_W { + RXJABERFIM_W { w: self } + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxruntfim(&mut self) -> RXRUNTFIM_W { + RXRUNTFIM_W { w: self } + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxalgnerfim(&mut self) -> RXALGNERFIM_W { + RXALGNERFIM_W { w: self } + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxcrcerfim(&mut self) -> RXCRCERFIM_W { + RXCRCERFIM_W { w: self } + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxmcgfim(&mut self) -> RXMCGFIM_W { + RXMCGFIM_W { w: self } + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxbcgfim(&mut self) -> RXBCGFIM_W { + RXBCGFIM_W { w: self } + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgoctim(&mut self) -> RXGOCTIM_W { + RXGOCTIM_W { w: self } + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Mask."] + #[inline(always)] + pub fn rxgboctim(&mut self) -> RXGBOCTIM_W { + RXGBOCTIM_W { w: self } + } + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgbfrmim(&mut self) -> RXGBFRMIM_W { + RXGBFRMIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MMC Receive Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmc_intr_mask_rx](index.html) module"] +pub struct MMC_INTR_MASK_RX_SPEC; +impl crate::RegisterSpec for MMC_INTR_MASK_RX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mmc_intr_mask_rx::R](R) reader structure"] +impl crate::Readable for MMC_INTR_MASK_RX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mmc_intr_mask_rx::W](W) writer structure"] +impl crate::Writable for MMC_INTR_MASK_RX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MMC_INTR_MASK_RX to value 0"] +impl crate::Resettable for MMC_INTR_MASK_RX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mmc_intr_mask_tx.rs b/src/eth/mmc_intr_mask_tx.rs new file mode 100644 index 0000000..5469351 --- /dev/null +++ b/src/eth/mmc_intr_mask_tx.rs @@ -0,0 +1,1288 @@ +#[doc = "Register `MMC_INTR_MASK_TX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MMC_INTR_MASK_TX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TXOSIZEGFIM` reader - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] +pub struct TXOSIZEGFIM_R(crate::FieldReader); +impl TXOSIZEGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXOSIZEGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXOSIZEGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXOSIZEGFIM` writer - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] +pub struct TXOSIZEGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXOSIZEGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `TXVLANGFIM` reader - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] +pub struct TXVLANGFIM_R(crate::FieldReader); +impl TXVLANGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXVLANGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXVLANGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXVLANGFIM` writer - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] +pub struct TXVLANGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXVLANGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `TXPAUSFIM` reader - MMC Transmit Pause Frame Counter Interrupt Mask"] +pub struct TXPAUSFIM_R(crate::FieldReader); +impl TXPAUSFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXPAUSFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXPAUSFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPAUSFIM` writer - MMC Transmit Pause Frame Counter Interrupt Mask"] +pub struct TXPAUSFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXPAUSFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `TXEXDEFFIM` reader - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] +pub struct TXEXDEFFIM_R(crate::FieldReader); +impl TXEXDEFFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEXDEFFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEXDEFFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEXDEFFIM` writer - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] +pub struct TXEXDEFFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXEXDEFFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TXGFRMIM` reader - MMC Transmit Good Frame Counter Interrupt Mask"] +pub struct TXGFRMIM_R(crate::FieldReader); +impl TXGFRMIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXGFRMIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXGFRMIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXGFRMIM` writer - MMC Transmit Good Frame Counter Interrupt Mask"] +pub struct TXGFRMIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXGFRMIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `TXGOCTIM` reader - MMC Transmit Good Octet Counter Interrupt Mask"] +pub struct TXGOCTIM_R(crate::FieldReader); +impl TXGOCTIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXGOCTIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXGOCTIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXGOCTIM` writer - MMC Transmit Good Octet Counter Interrupt Mask"] +pub struct TXGOCTIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXGOCTIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `TXCARERFIM` reader - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] +pub struct TXCARERFIM_R(crate::FieldReader); +impl TXCARERFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXCARERFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXCARERFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXCARERFIM` writer - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] +pub struct TXCARERFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXCARERFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `TXEXCOLFIM` reader - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] +pub struct TXEXCOLFIM_R(crate::FieldReader); +impl TXEXCOLFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEXCOLFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEXCOLFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEXCOLFIM` writer - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] +pub struct TXEXCOLFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXEXCOLFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `TXLATCOLFIM` reader - MMC Transmit Late Collision Frame Counter Interrupt Mask"] +pub struct TXLATCOLFIM_R(crate::FieldReader); +impl TXLATCOLFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXLATCOLFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXLATCOLFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXLATCOLFIM` writer - MMC Transmit Late Collision Frame Counter Interrupt Mask"] +pub struct TXLATCOLFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXLATCOLFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TXDEFFIM` reader - MMC Transmit Deferred Frame Counter Interrupt Mask"] +pub struct TXDEFFIM_R(crate::FieldReader); +impl TXDEFFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXDEFFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXDEFFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXDEFFIM` writer - MMC Transmit Deferred Frame Counter Interrupt Mask"] +pub struct TXDEFFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXDEFFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `TXMCOLGFIM` reader - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] +pub struct TXMCOLGFIM_R(crate::FieldReader); +impl TXMCOLGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXMCOLGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXMCOLGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXMCOLGFIM` writer - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] +pub struct TXMCOLGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXMCOLGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TXSCOLGFIM` reader - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] +pub struct TXSCOLGFIM_R(crate::FieldReader); +impl TXSCOLGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSCOLGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSCOLGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSCOLGFIM` writer - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] +pub struct TXSCOLGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXSCOLGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TXUFLOWERFIM` reader - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] +pub struct TXUFLOWERFIM_R(crate::FieldReader); +impl TXUFLOWERFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUFLOWERFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUFLOWERFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUFLOWERFIM` writer - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] +pub struct TXUFLOWERFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXUFLOWERFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXBCGBFIM` reader - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] +pub struct TXBCGBFIM_R(crate::FieldReader); +impl TXBCGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXBCGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXBCGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXBCGBFIM` writer - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] +pub struct TXBCGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXBCGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXMCGBFIM` reader - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] +pub struct TXMCGBFIM_R(crate::FieldReader); +impl TXMCGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXMCGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXMCGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXMCGBFIM` writer - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] +pub struct TXMCGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXMCGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TXUCGBFIM` reader - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] +pub struct TXUCGBFIM_R(crate::FieldReader); +impl TXUCGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUCGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUCGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUCGBFIM` writer - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] +pub struct TXUCGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXUCGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TX1024TMAXOCTGBFIM` reader - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX1024TMAXOCTGBFIM_R(crate::FieldReader); +impl TX1024TMAXOCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX1024TMAXOCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX1024TMAXOCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX1024TMAXOCTGBFIM` writer - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX1024TMAXOCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TX1024TMAXOCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TX512T1023OCTGBFIM` reader - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX512T1023OCTGBFIM_R(crate::FieldReader); +impl TX512T1023OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX512T1023OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX512T1023OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX512T1023OCTGBFIM` writer - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX512T1023OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TX512T1023OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TX256T511OCTGBFIM` reader - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX256T511OCTGBFIM_R(crate::FieldReader); +impl TX256T511OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX256T511OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX256T511OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX256T511OCTGBFIM` writer - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX256T511OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TX256T511OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TX128T255OCTGBFIM` reader - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX128T255OCTGBFIM_R(crate::FieldReader); +impl TX128T255OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX128T255OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX128T255OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX128T255OCTGBFIM` writer - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX128T255OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TX128T255OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TX65T127OCTGBFIM` reader - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX65T127OCTGBFIM_R(crate::FieldReader); +impl TX65T127OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX65T127OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX65T127OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX65T127OCTGBFIM` writer - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX65T127OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TX65T127OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TX64OCTGBFIM` reader - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX64OCTGBFIM_R(crate::FieldReader); +impl TX64OCTGBFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX64OCTGBFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX64OCTGBFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX64OCTGBFIM` writer - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub struct TX64OCTGBFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TX64OCTGBFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TXMCGFIM` reader - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] +pub struct TXMCGFIM_R(crate::FieldReader); +impl TXMCGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXMCGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXMCGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXMCGFIM` writer - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] +pub struct TXMCGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXMCGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXBCGFIM` reader - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] +pub struct TXBCGFIM_R(crate::FieldReader); +impl TXBCGFIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXBCGFIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXBCGFIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXBCGFIM` writer - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] +pub struct TXBCGFIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXBCGFIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TXGBFRMIM` reader - MMC Transmit Good Bad Frame Counter Interrupt Mask"] +pub struct TXGBFRMIM_R(crate::FieldReader); +impl TXGBFRMIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXGBFRMIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXGBFRMIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXGBFRMIM` writer - MMC Transmit Good Bad Frame Counter Interrupt Mask"] +pub struct TXGBFRMIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXGBFRMIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TXGBOCTIM` reader - MMC Transmit Good Bad Octet Counter Interrupt Mask"] +pub struct TXGBOCTIM_R(crate::FieldReader); +impl TXGBOCTIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXGBOCTIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXGBOCTIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXGBOCTIM` writer - MMC Transmit Good Bad Octet Counter Interrupt Mask"] +pub struct TXGBOCTIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXGBOCTIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txosizegfim(&self) -> TXOSIZEGFIM_R { + TXOSIZEGFIM_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txvlangfim(&self) -> TXVLANGFIM_R { + TXVLANGFIM_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txpausfim(&self) -> TXPAUSFIM_R { + TXPAUSFIM_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexdeffim(&self) -> TXEXDEFFIM_R { + TXEXDEFFIM_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgfrmim(&self) -> TXGFRMIM_R { + TXGFRMIM_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgoctim(&self) -> TXGOCTIM_R { + TXGOCTIM_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txcarerfim(&self) -> TXCARERFIM_R { + TXCARERFIM_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexcolfim(&self) -> TXEXCOLFIM_R { + TXEXCOLFIM_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txlatcolfim(&self) -> TXLATCOLFIM_R { + TXLATCOLFIM_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txdeffim(&self) -> TXDEFFIM_R { + TXDEFFIM_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcolgfim(&self) -> TXMCOLGFIM_R { + TXMCOLGFIM_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txscolgfim(&self) -> TXSCOLGFIM_R { + TXSCOLGFIM_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txuflowerfim(&self) -> TXUFLOWERFIM_R { + TXUFLOWERFIM_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgbfim(&self) -> TXBCGBFIM_R { + TXBCGBFIM_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgbfim(&self) -> TXMCGBFIM_R { + TXMCGBFIM_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txucgbfim(&self) -> TXUCGBFIM_R { + TXUCGBFIM_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx1024tmaxoctgbfim(&self) -> TX1024TMAXOCTGBFIM_R { + TX1024TMAXOCTGBFIM_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx512t1023octgbfim(&self) -> TX512T1023OCTGBFIM_R { + TX512T1023OCTGBFIM_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 7 - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx256t511octgbfim(&self) -> TX256T511OCTGBFIM_R { + TX256T511OCTGBFIM_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx128t255octgbfim(&self) -> TX128T255OCTGBFIM_R { + TX128T255OCTGBFIM_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx65t127octgbfim(&self) -> TX65T127OCTGBFIM_R { + TX65T127OCTGBFIM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx64octgbfim(&self) -> TX64OCTGBFIM_R { + TX64OCTGBFIM_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgfim(&self) -> TXMCGFIM_R { + TXMCGFIM_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgfim(&self) -> TXBCGFIM_R { + TXBCGFIM_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgbfrmim(&self) -> TXGBFRMIM_R { + TXGBFRMIM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgboctim(&self) -> TXGBOCTIM_R { + TXGBOCTIM_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txosizegfim(&mut self) -> TXOSIZEGFIM_W { + TXOSIZEGFIM_W { w: self } + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txvlangfim(&mut self) -> TXVLANGFIM_W { + TXVLANGFIM_W { w: self } + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txpausfim(&mut self) -> TXPAUSFIM_W { + TXPAUSFIM_W { w: self } + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexdeffim(&mut self) -> TXEXDEFFIM_W { + TXEXDEFFIM_W { w: self } + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgfrmim(&mut self) -> TXGFRMIM_W { + TXGFRMIM_W { w: self } + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgoctim(&mut self) -> TXGOCTIM_W { + TXGOCTIM_W { w: self } + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txcarerfim(&mut self) -> TXCARERFIM_W { + TXCARERFIM_W { w: self } + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexcolfim(&mut self) -> TXEXCOLFIM_W { + TXEXCOLFIM_W { w: self } + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txlatcolfim(&mut self) -> TXLATCOLFIM_W { + TXLATCOLFIM_W { w: self } + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txdeffim(&mut self) -> TXDEFFIM_W { + TXDEFFIM_W { w: self } + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcolgfim(&mut self) -> TXMCOLGFIM_W { + TXMCOLGFIM_W { w: self } + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txscolgfim(&mut self) -> TXSCOLGFIM_W { + TXSCOLGFIM_W { w: self } + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txuflowerfim(&mut self) -> TXUFLOWERFIM_W { + TXUFLOWERFIM_W { w: self } + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgbfim(&mut self) -> TXBCGBFIM_W { + TXBCGBFIM_W { w: self } + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgbfim(&mut self) -> TXMCGBFIM_W { + TXMCGBFIM_W { w: self } + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txucgbfim(&mut self) -> TXUCGBFIM_W { + TXUCGBFIM_W { w: self } + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx1024tmaxoctgbfim(&mut self) -> TX1024TMAXOCTGBFIM_W { + TX1024TMAXOCTGBFIM_W { w: self } + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx512t1023octgbfim(&mut self) -> TX512T1023OCTGBFIM_W { + TX512T1023OCTGBFIM_W { w: self } + } + #[doc = "Bit 7 - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx256t511octgbfim(&mut self) -> TX256T511OCTGBFIM_W { + TX256T511OCTGBFIM_W { w: self } + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx128t255octgbfim(&mut self) -> TX128T255OCTGBFIM_W { + TX128T255OCTGBFIM_W { w: self } + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx65t127octgbfim(&mut self) -> TX65T127OCTGBFIM_W { + TX65T127OCTGBFIM_W { w: self } + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx64octgbfim(&mut self) -> TX64OCTGBFIM_W { + TX64OCTGBFIM_W { w: self } + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgfim(&mut self) -> TXMCGFIM_W { + TXMCGFIM_W { w: self } + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgfim(&mut self) -> TXBCGFIM_W { + TXBCGFIM_W { w: self } + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgbfrmim(&mut self) -> TXGBFRMIM_W { + TXGBFRMIM_W { w: self } + } + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgboctim(&mut self) -> TXGBOCTIM_W { + TXGBOCTIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MMC Transmit Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmc_intr_mask_tx](index.html) module"] +pub struct MMC_INTR_MASK_TX_SPEC; +impl crate::RegisterSpec for MMC_INTR_MASK_TX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mmc_intr_mask_tx::R](R) reader structure"] +impl crate::Readable for MMC_INTR_MASK_TX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mmc_intr_mask_tx::W](W) writer structure"] +impl crate::Writable for MMC_INTR_MASK_TX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MMC_INTR_MASK_TX to value 0"] +impl crate::Resettable for MMC_INTR_MASK_TX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mmc_intr_rx.rs b/src/eth/mmc_intr_rx.rs new file mode 100644 index 0000000..e2e0832 --- /dev/null +++ b/src/eth/mmc_intr_rx.rs @@ -0,0 +1,1288 @@ +#[doc = "Register `MMC_INTR_RX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MMC_INTR_RX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXCTRLFIS` reader - MMC Receive Control Frame Counter Interrupt Status"] +pub struct RXCTRLFIS_R(crate::FieldReader); +impl RXCTRLFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXCTRLFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXCTRLFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXCTRLFIS` writer - MMC Receive Control Frame Counter Interrupt Status"] +pub struct RXCTRLFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXCTRLFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `RXRCVERRFIS` reader - MMC Receive Error Frame Counter Interrupt Status"] +pub struct RXRCVERRFIS_R(crate::FieldReader); +impl RXRCVERRFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRCVERRFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRCVERRFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRCVERRFIS` writer - MMC Receive Error Frame Counter Interrupt Status"] +pub struct RXRCVERRFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXRCVERRFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `RXWDOGFIS` reader - MMC Receive Watchdog Error Frame Counter Interrupt Status"] +pub struct RXWDOGFIS_R(crate::FieldReader); +impl RXWDOGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXWDOGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXWDOGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXWDOGFIS` writer - MMC Receive Watchdog Error Frame Counter Interrupt Status"] +pub struct RXWDOGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXWDOGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `RXVLANGBFIS` reader - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] +pub struct RXVLANGBFIS_R(crate::FieldReader); +impl RXVLANGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXVLANGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXVLANGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXVLANGBFIS` writer - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] +pub struct RXVLANGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXVLANGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `RXFOVFIS` reader - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] +pub struct RXFOVFIS_R(crate::FieldReader); +impl RXFOVFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFOVFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFOVFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFOVFIS` writer - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] +pub struct RXFOVFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXFOVFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `RXPAUSFIS` reader - MMC Receive Pause Frame Counter Interrupt Status"] +pub struct RXPAUSFIS_R(crate::FieldReader); +impl RXPAUSFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXPAUSFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPAUSFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPAUSFIS` writer - MMC Receive Pause Frame Counter Interrupt Status"] +pub struct RXPAUSFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXPAUSFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `RXORANGEFIS` reader - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] +pub struct RXORANGEFIS_R(crate::FieldReader); +impl RXORANGEFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXORANGEFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXORANGEFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXORANGEFIS` writer - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] +pub struct RXORANGEFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXORANGEFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `RXLENERFIS` reader - MMC Receive Length Error Frame Counter Interrupt Status"] +pub struct RXLENERFIS_R(crate::FieldReader); +impl RXLENERFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXLENERFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXLENERFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXLENERFIS` writer - MMC Receive Length Error Frame Counter Interrupt Status"] +pub struct RXLENERFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXLENERFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `RXUCGFIS` reader - MMC Receive Unicast Good Frame Counter Interrupt Status"] +pub struct RXUCGFIS_R(crate::FieldReader); +impl RXUCGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXUCGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXUCGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXUCGFIS` writer - MMC Receive Unicast Good Frame Counter Interrupt Status"] +pub struct RXUCGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXUCGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `RX1024TMAXOCTGBFIS` reader - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] +pub struct RX1024TMAXOCTGBFIS_R(crate::FieldReader); +impl RX1024TMAXOCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX1024TMAXOCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX1024TMAXOCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX1024TMAXOCTGBFIS` writer - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] +pub struct RX1024TMAXOCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RX1024TMAXOCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `RX512T1023OCTGBFIS` reader - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX512T1023OCTGBFIS_R(crate::FieldReader); +impl RX512T1023OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX512T1023OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX512T1023OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX512T1023OCTGBFIS` writer - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX512T1023OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RX512T1023OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `RX256T511OCTGBFIS` reader - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX256T511OCTGBFIS_R(crate::FieldReader); +impl RX256T511OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX256T511OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX256T511OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX256T511OCTGBFIS` writer - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX256T511OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RX256T511OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RX128T255OCTGBFIS` reader - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX128T255OCTGBFIS_R(crate::FieldReader); +impl RX128T255OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX128T255OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX128T255OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX128T255OCTGBFIS` writer - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX128T255OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RX128T255OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `RX65T127OCTGBFIS` reader - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX65T127OCTGBFIS_R(crate::FieldReader); +impl RX65T127OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX65T127OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX65T127OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX65T127OCTGBFIS` writer - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX65T127OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RX65T127OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RX64OCTGBFIS` reader - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX64OCTGBFIS_R(crate::FieldReader); +impl RX64OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX64OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX64OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX64OCTGBFIS` writer - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] +pub struct RX64OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RX64OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `RXOSIZEGFIS` reader - MMC Receive Oversize Good Frame Counter Interrupt Status"] +pub struct RXOSIZEGFIS_R(crate::FieldReader); +impl RXOSIZEGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOSIZEGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOSIZEGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOSIZEGFIS` writer - MMC Receive Oversize Good Frame Counter Interrupt Status"] +pub struct RXOSIZEGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXOSIZEGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `RXUSIZEGFIS` reader - MMC Receive Undersize Good Frame Counter Interrupt Status"] +pub struct RXUSIZEGFIS_R(crate::FieldReader); +impl RXUSIZEGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXUSIZEGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXUSIZEGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXUSIZEGFIS` writer - MMC Receive Undersize Good Frame Counter Interrupt Status"] +pub struct RXUSIZEGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXUSIZEGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `RXJABERFIS` reader - MMC Receive Jabber Error Frame Counter Interrupt Status"] +pub struct RXJABERFIS_R(crate::FieldReader); +impl RXJABERFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXJABERFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXJABERFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXJABERFIS` writer - MMC Receive Jabber Error Frame Counter Interrupt Status"] +pub struct RXJABERFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXJABERFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RXRUNTFIS` reader - MMC Receive Runt Frame Counter Interrupt Status"] +pub struct RXRUNTFIS_R(crate::FieldReader); +impl RXRUNTFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRUNTFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRUNTFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRUNTFIS` writer - MMC Receive Runt Frame Counter Interrupt Status"] +pub struct RXRUNTFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXRUNTFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `RXALGNERFIS` reader - MMC Receive Alignment Error Frame Counter Interrupt Status"] +pub struct RXALGNERFIS_R(crate::FieldReader); +impl RXALGNERFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXALGNERFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXALGNERFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXALGNERFIS` writer - MMC Receive Alignment Error Frame Counter Interrupt Status"] +pub struct RXALGNERFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXALGNERFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RXCRCERFIS` reader - MMC Receive CRC Error Frame Counter Interrupt Status"] +pub struct RXCRCERFIS_R(crate::FieldReader); +impl RXCRCERFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXCRCERFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXCRCERFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXCRCERFIS` writer - MMC Receive CRC Error Frame Counter Interrupt Status"] +pub struct RXCRCERFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXCRCERFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `RXMCGFIS` reader - MMC Receive Multicast Good Frame Counter Interrupt Status"] +pub struct RXMCGFIS_R(crate::FieldReader); +impl RXMCGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXMCGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXMCGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXMCGFIS` writer - MMC Receive Multicast Good Frame Counter Interrupt Status"] +pub struct RXMCGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXMCGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RXBCGFIS` reader - MMC Receive Broadcast Good Frame Counter Interrupt Status"] +pub struct RXBCGFIS_R(crate::FieldReader); +impl RXBCGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBCGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBCGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBCGFIS` writer - MMC Receive Broadcast Good Frame Counter Interrupt Status"] +pub struct RXBCGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXBCGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXGOCTIS` reader - MMC Receive Good Octet Counter Interrupt Status"] +pub struct RXGOCTIS_R(crate::FieldReader); +impl RXGOCTIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXGOCTIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXGOCTIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXGOCTIS` writer - MMC Receive Good Octet Counter Interrupt Status"] +pub struct RXGOCTIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXGOCTIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RXGBOCTIS` reader - MMC Receive Good Bad Octet Counter Interrupt Status"] +pub struct RXGBOCTIS_R(crate::FieldReader); +impl RXGBOCTIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXGBOCTIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXGBOCTIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXGBOCTIS` writer - MMC Receive Good Bad Octet Counter Interrupt Status"] +pub struct RXGBOCTIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXGBOCTIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXGBFRMIS` reader - MMC Receive Good Bad Frame Counter Interrupt Status"] +pub struct RXGBFRMIS_R(crate::FieldReader); +impl RXGBFRMIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXGBFRMIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXGBFRMIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXGBFRMIS` writer - MMC Receive Good Bad Frame Counter Interrupt Status"] +pub struct RXGBFRMIS_W<'a> { + w: &'a mut W, +} +impl<'a> RXGBFRMIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxctrlfis(&self) -> RXCTRLFIS_R { + RXCTRLFIS_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxrcverrfis(&self) -> RXRCVERRFIS_R { + RXRCVERRFIS_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxwdogfis(&self) -> RXWDOGFIS_R { + RXWDOGFIS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxvlangbfis(&self) -> RXVLANGBFIS_R { + RXVLANGBFIS_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxfovfis(&self) -> RXFOVFIS_R { + RXFOVFIS_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxpausfis(&self) -> RXPAUSFIS_R { + RXPAUSFIS_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rxorangefis(&self) -> RXORANGEFIS_R { + RXORANGEFIS_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxlenerfis(&self) -> RXLENERFIS_R { + RXLENERFIS_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxucgfis(&self) -> RXUCGFIS_R { + RXUCGFIS_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rx1024tmaxoctgbfis(&self) -> RX1024TMAXOCTGBFIS_R { + RX1024TMAXOCTGBFIS_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx512t1023octgbfis(&self) -> RX512T1023OCTGBFIS_R { + RX512T1023OCTGBFIS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx256t511octgbfis(&self) -> RX256T511OCTGBFIS_R { + RX256T511OCTGBFIS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx128t255octgbfis(&self) -> RX128T255OCTGBFIS_R { + RX128T255OCTGBFIS_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx65t127octgbfis(&self) -> RX65T127OCTGBFIS_R { + RX65T127OCTGBFIS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx64octgbfis(&self) -> RX64OCTGBFIS_R { + RX64OCTGBFIS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxosizegfis(&self) -> RXOSIZEGFIS_R { + RXOSIZEGFIS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxusizegfis(&self) -> RXUSIZEGFIS_R { + RXUSIZEGFIS_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxjaberfis(&self) -> RXJABERFIS_R { + RXJABERFIS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxruntfis(&self) -> RXRUNTFIS_R { + RXRUNTFIS_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxalgnerfis(&self) -> RXALGNERFIS_R { + RXALGNERFIS_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxcrcerfis(&self) -> RXCRCERFIS_R { + RXCRCERFIS_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxmcgfis(&self) -> RXMCGFIS_R { + RXMCGFIS_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxbcgfis(&self) -> RXBCGFIS_R { + RXBCGFIS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgoctis(&self) -> RXGOCTIS_R { + RXGOCTIS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgboctis(&self) -> RXGBOCTIS_R { + RXGBOCTIS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxgbfrmis(&self) -> RXGBFRMIS_R { + RXGBFRMIS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxctrlfis(&mut self) -> RXCTRLFIS_W { + RXCTRLFIS_W { w: self } + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxrcverrfis(&mut self) -> RXRCVERRFIS_W { + RXRCVERRFIS_W { w: self } + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxwdogfis(&mut self) -> RXWDOGFIS_W { + RXWDOGFIS_W { w: self } + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxvlangbfis(&mut self) -> RXVLANGBFIS_W { + RXVLANGBFIS_W { w: self } + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxfovfis(&mut self) -> RXFOVFIS_W { + RXFOVFIS_W { w: self } + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxpausfis(&mut self) -> RXPAUSFIS_W { + RXPAUSFIS_W { w: self } + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rxorangefis(&mut self) -> RXORANGEFIS_W { + RXORANGEFIS_W { w: self } + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxlenerfis(&mut self) -> RXLENERFIS_W { + RXLENERFIS_W { w: self } + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxucgfis(&mut self) -> RXUCGFIS_W { + RXUCGFIS_W { w: self } + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rx1024tmaxoctgbfis(&mut self) -> RX1024TMAXOCTGBFIS_W { + RX1024TMAXOCTGBFIS_W { w: self } + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx512t1023octgbfis(&mut self) -> RX512T1023OCTGBFIS_W { + RX512T1023OCTGBFIS_W { w: self } + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx256t511octgbfis(&mut self) -> RX256T511OCTGBFIS_W { + RX256T511OCTGBFIS_W { w: self } + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx128t255octgbfis(&mut self) -> RX128T255OCTGBFIS_W { + RX128T255OCTGBFIS_W { w: self } + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx65t127octgbfis(&mut self) -> RX65T127OCTGBFIS_W { + RX65T127OCTGBFIS_W { w: self } + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx64octgbfis(&mut self) -> RX64OCTGBFIS_W { + RX64OCTGBFIS_W { w: self } + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxosizegfis(&mut self) -> RXOSIZEGFIS_W { + RXOSIZEGFIS_W { w: self } + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxusizegfis(&mut self) -> RXUSIZEGFIS_W { + RXUSIZEGFIS_W { w: self } + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxjaberfis(&mut self) -> RXJABERFIS_W { + RXJABERFIS_W { w: self } + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxruntfis(&mut self) -> RXRUNTFIS_W { + RXRUNTFIS_W { w: self } + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxalgnerfis(&mut self) -> RXALGNERFIS_W { + RXALGNERFIS_W { w: self } + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxcrcerfis(&mut self) -> RXCRCERFIS_W { + RXCRCERFIS_W { w: self } + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxmcgfis(&mut self) -> RXMCGFIS_W { + RXMCGFIS_W { w: self } + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxbcgfis(&mut self) -> RXBCGFIS_W { + RXBCGFIS_W { w: self } + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgoctis(&mut self) -> RXGOCTIS_W { + RXGOCTIS_W { w: self } + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgboctis(&mut self) -> RXGBOCTIS_W { + RXGBOCTIS_W { w: self } + } + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxgbfrmis(&mut self) -> RXGBFRMIS_W { + RXGBFRMIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MMC Receive Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmc_intr_rx](index.html) module"] +pub struct MMC_INTR_RX_SPEC; +impl crate::RegisterSpec for MMC_INTR_RX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mmc_intr_rx::R](R) reader structure"] +impl crate::Readable for MMC_INTR_RX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mmc_intr_rx::W](W) writer structure"] +impl crate::Writable for MMC_INTR_RX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MMC_INTR_RX to value 0"] +impl crate::Resettable for MMC_INTR_RX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/mmc_intr_tx.rs b/src/eth/mmc_intr_tx.rs new file mode 100644 index 0000000..1afae74 --- /dev/null +++ b/src/eth/mmc_intr_tx.rs @@ -0,0 +1,1288 @@ +#[doc = "Register `MMC_INTR_TX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MMC_INTR_TX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TXOSIZEGFIS` reader - MMC Transmit Oversize Good Frame Counter Interrupt Status"] +pub struct TXOSIZEGFIS_R(crate::FieldReader); +impl TXOSIZEGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXOSIZEGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXOSIZEGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXOSIZEGFIS` writer - MMC Transmit Oversize Good Frame Counter Interrupt Status"] +pub struct TXOSIZEGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXOSIZEGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `TXVLANGFIS` reader - MMC Transmit VLAN Good Frame Counter Interrupt Status"] +pub struct TXVLANGFIS_R(crate::FieldReader); +impl TXVLANGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXVLANGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXVLANGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXVLANGFIS` writer - MMC Transmit VLAN Good Frame Counter Interrupt Status"] +pub struct TXVLANGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXVLANGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `TXPAUSFIS` reader - MMC Transmit Pause Frame Counter Interrupt Status"] +pub struct TXPAUSFIS_R(crate::FieldReader); +impl TXPAUSFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXPAUSFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXPAUSFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXPAUSFIS` writer - MMC Transmit Pause Frame Counter Interrupt Status"] +pub struct TXPAUSFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXPAUSFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `TXEXDEFFIS` reader - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] +pub struct TXEXDEFFIS_R(crate::FieldReader); +impl TXEXDEFFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEXDEFFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEXDEFFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEXDEFFIS` writer - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] +pub struct TXEXDEFFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXEXDEFFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `TXGFRMIS` reader - MMC Transmit Good Frame Counter Interrupt Status"] +pub struct TXGFRMIS_R(crate::FieldReader); +impl TXGFRMIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXGFRMIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXGFRMIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXGFRMIS` writer - MMC Transmit Good Frame Counter Interrupt Status"] +pub struct TXGFRMIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXGFRMIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `TXGOCTIS` reader - MMC Transmit Good Octet Counter Interrupt Status"] +pub struct TXGOCTIS_R(crate::FieldReader); +impl TXGOCTIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXGOCTIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXGOCTIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXGOCTIS` writer - MMC Transmit Good Octet Counter Interrupt Status"] +pub struct TXGOCTIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXGOCTIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `TXCARERFIS` reader - MMC Transmit Carrier Error Frame Counter Interrupt Status"] +pub struct TXCARERFIS_R(crate::FieldReader); +impl TXCARERFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXCARERFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXCARERFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXCARERFIS` writer - MMC Transmit Carrier Error Frame Counter Interrupt Status"] +pub struct TXCARERFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXCARERFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `TXEXCOLFIS` reader - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] +pub struct TXEXCOLFIS_R(crate::FieldReader); +impl TXEXCOLFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEXCOLFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEXCOLFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEXCOLFIS` writer - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] +pub struct TXEXCOLFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXEXCOLFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `TXLATCOLFIS` reader - MMC Transmit Late Collision Frame Counter Interrupt Status"] +pub struct TXLATCOLFIS_R(crate::FieldReader); +impl TXLATCOLFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXLATCOLFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXLATCOLFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXLATCOLFIS` writer - MMC Transmit Late Collision Frame Counter Interrupt Status"] +pub struct TXLATCOLFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXLATCOLFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TXDEFFIS` reader - MMC Transmit Deferred Frame Counter Interrupt Status"] +pub struct TXDEFFIS_R(crate::FieldReader); +impl TXDEFFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXDEFFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXDEFFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXDEFFIS` writer - MMC Transmit Deferred Frame Counter Interrupt Status"] +pub struct TXDEFFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXDEFFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `TXMCOLGFIS` reader - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] +pub struct TXMCOLGFIS_R(crate::FieldReader); +impl TXMCOLGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXMCOLGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXMCOLGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXMCOLGFIS` writer - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] +pub struct TXMCOLGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXMCOLGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TXSCOLGFIS` reader - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] +pub struct TXSCOLGFIS_R(crate::FieldReader); +impl TXSCOLGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSCOLGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSCOLGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSCOLGFIS` writer - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] +pub struct TXSCOLGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXSCOLGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TXUFLOWERFIS` reader - MMC Transmit Underflow Error Frame Counter Interrupt Status"] +pub struct TXUFLOWERFIS_R(crate::FieldReader); +impl TXUFLOWERFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUFLOWERFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUFLOWERFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUFLOWERFIS` writer - MMC Transmit Underflow Error Frame Counter Interrupt Status"] +pub struct TXUFLOWERFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXUFLOWERFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXBCGBFIS` reader - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] +pub struct TXBCGBFIS_R(crate::FieldReader); +impl TXBCGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXBCGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXBCGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXBCGBFIS` writer - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] +pub struct TXBCGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXBCGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXMCGBFIS` reader - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] +pub struct TXMCGBFIS_R(crate::FieldReader); +impl TXMCGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXMCGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXMCGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXMCGBFIS` writer - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] +pub struct TXMCGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXMCGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TXUCGBFIS` reader - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] +pub struct TXUCGBFIS_R(crate::FieldReader); +impl TXUCGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUCGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUCGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUCGBFIS` writer - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] +pub struct TXUCGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXUCGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TX1024TMAXOCTGBFIS` reader - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] +pub struct TX1024TMAXOCTGBFIS_R(crate::FieldReader); +impl TX1024TMAXOCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX1024TMAXOCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX1024TMAXOCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX1024TMAXOCTGBFIS` writer - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] +pub struct TX1024TMAXOCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TX1024TMAXOCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TX512T1023OCTGBFIS` reader - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX512T1023OCTGBFIS_R(crate::FieldReader); +impl TX512T1023OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX512T1023OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX512T1023OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX512T1023OCTGBFIS` writer - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX512T1023OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TX512T1023OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TX256T511OCTGBFIS` reader - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX256T511OCTGBFIS_R(crate::FieldReader); +impl TX256T511OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX256T511OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX256T511OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX256T511OCTGBFIS` writer - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX256T511OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TX256T511OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TX128T255OCTGBFIS` reader - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX128T255OCTGBFIS_R(crate::FieldReader); +impl TX128T255OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX128T255OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX128T255OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX128T255OCTGBFIS` writer - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX128T255OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TX128T255OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TX65T127OCTGBFIS` reader - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX65T127OCTGBFIS_R(crate::FieldReader); +impl TX65T127OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX65T127OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX65T127OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX65T127OCTGBFIS` writer - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX65T127OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TX65T127OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TX64OCTGBFIS` reader - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX64OCTGBFIS_R(crate::FieldReader); +impl TX64OCTGBFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TX64OCTGBFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TX64OCTGBFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TX64OCTGBFIS` writer - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] +pub struct TX64OCTGBFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TX64OCTGBFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TXMCGFIS` reader - MMC Transmit Multicast Good Frame Counter Interrupt Status"] +pub struct TXMCGFIS_R(crate::FieldReader); +impl TXMCGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXMCGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXMCGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXMCGFIS` writer - MMC Transmit Multicast Good Frame Counter Interrupt Status"] +pub struct TXMCGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXMCGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TXBCGFIS` reader - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] +pub struct TXBCGFIS_R(crate::FieldReader); +impl TXBCGFIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXBCGFIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXBCGFIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXBCGFIS` writer - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] +pub struct TXBCGFIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXBCGFIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TXGBFRMIS` reader - MMC Transmit Good Bad Frame Counter Interrupt Status"] +pub struct TXGBFRMIS_R(crate::FieldReader); +impl TXGBFRMIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXGBFRMIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXGBFRMIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXGBFRMIS` writer - MMC Transmit Good Bad Frame Counter Interrupt Status"] +pub struct TXGBFRMIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXGBFRMIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TXGBOCTIS` reader - MMC Transmit Good Bad Octet Counter Interrupt Status"] +pub struct TXGBOCTIS_R(crate::FieldReader); +impl TXGBOCTIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXGBOCTIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXGBOCTIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXGBOCTIS` writer - MMC Transmit Good Bad Octet Counter Interrupt Status"] +pub struct TXGBOCTIS_W<'a> { + w: &'a mut W, +} +impl<'a> TXGBOCTIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txosizegfis(&self) -> TXOSIZEGFIS_R { + TXOSIZEGFIS_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txvlangfis(&self) -> TXVLANGFIS_R { + TXVLANGFIS_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txpausfis(&self) -> TXPAUSFIS_R { + TXPAUSFIS_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexdeffis(&self) -> TXEXDEFFIS_R { + TXEXDEFFIS_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgfrmis(&self) -> TXGFRMIS_R { + TXGFRMIS_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgoctis(&self) -> TXGOCTIS_R { + TXGOCTIS_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txcarerfis(&self) -> TXCARERFIS_R { + TXCARERFIS_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexcolfis(&self) -> TXEXCOLFIS_R { + TXEXCOLFIS_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txlatcolfis(&self) -> TXLATCOLFIS_R { + TXLATCOLFIS_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txdeffis(&self) -> TXDEFFIS_R { + TXDEFFIS_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcolgfis(&self) -> TXMCOLGFIS_R { + TXMCOLGFIS_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txscolgfis(&self) -> TXSCOLGFIS_R { + TXSCOLGFIS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txuflowerfis(&self) -> TXUFLOWERFIS_R { + TXUFLOWERFIS_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgbfis(&self) -> TXBCGBFIS_R { + TXBCGBFIS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgbfis(&self) -> TXMCGBFIS_R { + TXMCGBFIS_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txucgbfis(&self) -> TXUCGBFIS_R { + TXUCGBFIS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] + #[inline(always)] + pub fn tx1024tmaxoctgbfis(&self) -> TX1024TMAXOCTGBFIS_R { + TX1024TMAXOCTGBFIS_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx512t1023octgbfis(&self) -> TX512T1023OCTGBFIS_R { + TX512T1023OCTGBFIS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 7 - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx256t511octgbfis(&self) -> TX256T511OCTGBFIS_R { + TX256T511OCTGBFIS_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx128t255octgbfis(&self) -> TX128T255OCTGBFIS_R { + TX128T255OCTGBFIS_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx65t127octgbfis(&self) -> TX65T127OCTGBFIS_R { + TX65T127OCTGBFIS_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx64octgbfis(&self) -> TX64OCTGBFIS_R { + TX64OCTGBFIS_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgfis(&self) -> TXMCGFIS_R { + TXMCGFIS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgfis(&self) -> TXBCGFIS_R { + TXBCGFIS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgbfrmis(&self) -> TXGBFRMIS_R { + TXGBFRMIS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgboctis(&self) -> TXGBOCTIS_R { + TXGBOCTIS_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txosizegfis(&mut self) -> TXOSIZEGFIS_W { + TXOSIZEGFIS_W { w: self } + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txvlangfis(&mut self) -> TXVLANGFIS_W { + TXVLANGFIS_W { w: self } + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txpausfis(&mut self) -> TXPAUSFIS_W { + TXPAUSFIS_W { w: self } + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexdeffis(&mut self) -> TXEXDEFFIS_W { + TXEXDEFFIS_W { w: self } + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgfrmis(&mut self) -> TXGFRMIS_W { + TXGFRMIS_W { w: self } + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgoctis(&mut self) -> TXGOCTIS_W { + TXGOCTIS_W { w: self } + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txcarerfis(&mut self) -> TXCARERFIS_W { + TXCARERFIS_W { w: self } + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexcolfis(&mut self) -> TXEXCOLFIS_W { + TXEXCOLFIS_W { w: self } + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txlatcolfis(&mut self) -> TXLATCOLFIS_W { + TXLATCOLFIS_W { w: self } + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txdeffis(&mut self) -> TXDEFFIS_W { + TXDEFFIS_W { w: self } + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcolgfis(&mut self) -> TXMCOLGFIS_W { + TXMCOLGFIS_W { w: self } + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txscolgfis(&mut self) -> TXSCOLGFIS_W { + TXSCOLGFIS_W { w: self } + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txuflowerfis(&mut self) -> TXUFLOWERFIS_W { + TXUFLOWERFIS_W { w: self } + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgbfis(&mut self) -> TXBCGBFIS_W { + TXBCGBFIS_W { w: self } + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgbfis(&mut self) -> TXMCGBFIS_W { + TXMCGBFIS_W { w: self } + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txucgbfis(&mut self) -> TXUCGBFIS_W { + TXUCGBFIS_W { w: self } + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] + #[inline(always)] + pub fn tx1024tmaxoctgbfis(&mut self) -> TX1024TMAXOCTGBFIS_W { + TX1024TMAXOCTGBFIS_W { w: self } + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx512t1023octgbfis(&mut self) -> TX512T1023OCTGBFIS_W { + TX512T1023OCTGBFIS_W { w: self } + } + #[doc = "Bit 7 - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx256t511octgbfis(&mut self) -> TX256T511OCTGBFIS_W { + TX256T511OCTGBFIS_W { w: self } + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx128t255octgbfis(&mut self) -> TX128T255OCTGBFIS_W { + TX128T255OCTGBFIS_W { w: self } + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx65t127octgbfis(&mut self) -> TX65T127OCTGBFIS_W { + TX65T127OCTGBFIS_W { w: self } + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx64octgbfis(&mut self) -> TX64OCTGBFIS_W { + TX64OCTGBFIS_W { w: self } + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgfis(&mut self) -> TXMCGFIS_W { + TXMCGFIS_W { w: self } + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgfis(&mut self) -> TXBCGFIS_W { + TXBCGFIS_W { w: self } + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgbfrmis(&mut self) -> TXGBFRMIS_W { + TXGBFRMIS_W { w: self } + } + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgboctis(&mut self) -> TXGBOCTIS_W { + TXGBOCTIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MMC Transmit Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmc_intr_tx](index.html) module"] +pub struct MMC_INTR_TX_SPEC; +impl crate::RegisterSpec for MMC_INTR_TX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [mmc_intr_tx::R](R) reader structure"] +impl crate::Readable for MMC_INTR_TX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mmc_intr_tx::W](W) writer structure"] +impl crate::Writable for MMC_INTR_TX_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets MMC_INTR_TX to value 0"] +impl crate::Resettable for MMC_INTR_TX_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rx1024maxoct_gb.rs b/src/eth/rx1024maxoct_gb.rs new file mode 100644 index 0000000..30f8d7f --- /dev/null +++ b/src/eth/rx1024maxoct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RX1024MAXOCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good and bad frames received with length between 1024 and max size bytes\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx1024maxoct_gb](index.html) module"] +pub struct RX1024MAXOCT_GB_SPEC; +impl crate::RegisterSpec for RX1024MAXOCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rx1024maxoct_gb::R](R) reader structure"] +impl crate::Readable for RX1024MAXOCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RX1024MAXOCT_GB to value 0"] +impl crate::Resettable for RX1024MAXOCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rx128to255oct_gb.rs b/src/eth/rx128to255oct_gb.rs new file mode 100644 index 0000000..6fe172e --- /dev/null +++ b/src/eth/rx128to255oct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RX128TO255OCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good and bad frames received with length between 128 and 255 bytes\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx128to255oct_gb](index.html) module"] +pub struct RX128TO255OCT_GB_SPEC; +impl crate::RegisterSpec for RX128TO255OCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rx128to255oct_gb::R](R) reader structure"] +impl crate::Readable for RX128TO255OCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RX128TO255OCT_GB to value 0"] +impl crate::Resettable for RX128TO255OCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rx256to511oct_gb.rs b/src/eth/rx256to511oct_gb.rs new file mode 100644 index 0000000..1d9af65 --- /dev/null +++ b/src/eth/rx256to511oct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RX256TO511OCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good and bad frames received with length between 256 and 511 bytes\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx256to511oct_gb](index.html) module"] +pub struct RX256TO511OCT_GB_SPEC; +impl crate::RegisterSpec for RX256TO511OCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rx256to511oct_gb::R](R) reader structure"] +impl crate::Readable for RX256TO511OCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RX256TO511OCT_GB to value 0"] +impl crate::Resettable for RX256TO511OCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rx512to1023oct_gb.rs b/src/eth/rx512to1023oct_gb.rs new file mode 100644 index 0000000..91a95ec --- /dev/null +++ b/src/eth/rx512to1023oct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RX512TO1023OCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good and bad frames received with length between 512 and 1023 bytes\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx512to1023oct_gb](index.html) module"] +pub struct RX512TO1023OCT_GB_SPEC; +impl crate::RegisterSpec for RX512TO1023OCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rx512to1023oct_gb::R](R) reader structure"] +impl crate::Readable for RX512TO1023OCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RX512TO1023OCT_GB to value 0"] +impl crate::Resettable for RX512TO1023OCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rx64octets_gb.rs b/src/eth/rx64octets_gb.rs new file mode 100644 index 0000000..1a363d2 --- /dev/null +++ b/src/eth/rx64octets_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RX64OCTETS_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good and bad frames received with length 64 bytes\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx64octets_gb](index.html) module"] +pub struct RX64OCTETS_GB_SPEC; +impl crate::RegisterSpec for RX64OCTETS_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rx64octets_gb::R](R) reader structure"] +impl crate::Readable for RX64OCTETS_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RX64OCTETS_GB to value 0"] +impl crate::Resettable for RX64OCTETS_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rx65to127oct_gb.rs b/src/eth/rx65to127oct_gb.rs new file mode 100644 index 0000000..eb80dca --- /dev/null +++ b/src/eth/rx65to127oct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RX65TO127OCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good and bad frames received with length between 65 and 127 bytes\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx65to127oct_gb](index.html) module"] +pub struct RX65TO127OCT_GB_SPEC; +impl crate::RegisterSpec for RX65TO127OCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rx65to127oct_gb::R](R) reader structure"] +impl crate::Readable for RX65TO127OCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RX65TO127OCT_GB to value 0"] +impl crate::Resettable for RX65TO127OCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxalignerror.rs b/src/eth/rxalignerror.rs new file mode 100644 index 0000000..586a5e2 --- /dev/null +++ b/src/eth/rxalignerror.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXALIGNERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames received with alignment error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxalignerror](index.html) module"] +pub struct RXALIGNERROR_SPEC; +impl crate::RegisterSpec for RXALIGNERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxalignerror::R](R) reader structure"] +impl crate::Readable for RXALIGNERROR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXALIGNERROR to value 0"] +impl crate::Resettable for RXALIGNERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxbcastframes_g.rs b/src/eth/rxbcastframes_g.rs new file mode 100644 index 0000000..37ebc88 --- /dev/null +++ b/src/eth/rxbcastframes_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXBCASTFRAMES_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good broadcast frames received\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxbcastframes_g](index.html) module"] +pub struct RXBCASTFRAMES_G_SPEC; +impl crate::RegisterSpec for RXBCASTFRAMES_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxbcastframes_g::R](R) reader structure"] +impl crate::Readable for RXBCASTFRAMES_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXBCASTFRAMES_G to value 0"] +impl crate::Resettable for RXBCASTFRAMES_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxcrcerror.rs b/src/eth/rxcrcerror.rs new file mode 100644 index 0000000..b6efba7 --- /dev/null +++ b/src/eth/rxcrcerror.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXCRCERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames received with CRC error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxcrcerror](index.html) module"] +pub struct RXCRCERROR_SPEC; +impl crate::RegisterSpec for RXCRCERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxcrcerror::R](R) reader structure"] +impl crate::Readable for RXCRCERROR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXCRCERROR to value 0"] +impl crate::Resettable for RXCRCERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxctrlframes_g.rs b/src/eth/rxctrlframes_g.rs new file mode 100644 index 0000000..5fdae6c --- /dev/null +++ b/src/eth/rxctrlframes_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXCTRLFRAMES_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of received good control frames\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxctrlframes_g](index.html) module"] +pub struct RXCTRLFRAMES_G_SPEC; +impl crate::RegisterSpec for RXCTRLFRAMES_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxctrlframes_g::R](R) reader structure"] +impl crate::Readable for RXCTRLFRAMES_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXCTRLFRAMES_G to value 0"] +impl crate::Resettable for RXCTRLFRAMES_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxfifooverflow.rs b/src/eth/rxfifooverflow.rs new file mode 100644 index 0000000..c7f8606 --- /dev/null +++ b/src/eth/rxfifooverflow.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXFIFOOVERFLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of missed received frames because of FIFO overflow\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifooverflow](index.html) module"] +pub struct RXFIFOOVERFLOW_SPEC; +impl crate::RegisterSpec for RXFIFOOVERFLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxfifooverflow::R](R) reader structure"] +impl crate::Readable for RXFIFOOVERFLOW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXFIFOOVERFLOW to value 0"] +impl crate::Resettable for RXFIFOOVERFLOW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxframecount_gb.rs b/src/eth/rxframecount_gb.rs new file mode 100644 index 0000000..c81a6c4 --- /dev/null +++ b/src/eth/rxframecount_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXFRAMECOUNT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good and bad frames received\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxframecount_gb](index.html) module"] +pub struct RXFRAMECOUNT_GB_SPEC; +impl crate::RegisterSpec for RXFRAMECOUNT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxframecount_gb::R](R) reader structure"] +impl crate::Readable for RXFRAMECOUNT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXFRAMECOUNT_GB to value 0"] +impl crate::Resettable for RXFRAMECOUNT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxjabbererror.rs b/src/eth/rxjabbererror.rs new file mode 100644 index 0000000..10e87e0 --- /dev/null +++ b/src/eth/rxjabbererror.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXJABBERERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of giant frames received with length greater than 1518 bytes and with CRC error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxjabbererror](index.html) module"] +pub struct RXJABBERERROR_SPEC; +impl crate::RegisterSpec for RXJABBERERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxjabbererror::R](R) reader structure"] +impl crate::Readable for RXJABBERERROR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXJABBERERROR to value 0"] +impl crate::Resettable for RXJABBERERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxlengtherror.rs b/src/eth/rxlengtherror.rs new file mode 100644 index 0000000..e065d01 --- /dev/null +++ b/src/eth/rxlengtherror.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXLENGTHERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames received with length error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxlengtherror](index.html) module"] +pub struct RXLENGTHERROR_SPEC; +impl crate::RegisterSpec for RXLENGTHERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxlengtherror::R](R) reader structure"] +impl crate::Readable for RXLENGTHERROR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXLENGTHERROR to value 0"] +impl crate::Resettable for RXLENGTHERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxmcastframes_g.rs b/src/eth/rxmcastframes_g.rs new file mode 100644 index 0000000..9938e99 --- /dev/null +++ b/src/eth/rxmcastframes_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXMCASTFRAMES_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good multicast frames received\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxmcastframes_g](index.html) module"] +pub struct RXMCASTFRAMES_G_SPEC; +impl crate::RegisterSpec for RXMCASTFRAMES_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxmcastframes_g::R](R) reader structure"] +impl crate::Readable for RXMCASTFRAMES_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXMCASTFRAMES_G to value 0"] +impl crate::Resettable for RXMCASTFRAMES_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxoctetcount_g.rs b/src/eth/rxoctetcount_g.rs new file mode 100644 index 0000000..f57bbad --- /dev/null +++ b/src/eth/rxoctetcount_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXOCTETCOUNT_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of bytes"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of bytes received in good frames only\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxoctetcount_g](index.html) module"] +pub struct RXOCTETCOUNT_G_SPEC; +impl crate::RegisterSpec for RXOCTETCOUNT_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxoctetcount_g::R](R) reader structure"] +impl crate::Readable for RXOCTETCOUNT_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXOCTETCOUNT_G to value 0"] +impl crate::Resettable for RXOCTETCOUNT_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxoctetcount_gb.rs b/src/eth/rxoctetcount_gb.rs new file mode 100644 index 0000000..7d5e277 --- /dev/null +++ b/src/eth/rxoctetcount_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXOCTETCOUNT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of bytes"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of bytes received in good and bad frames\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxoctetcount_gb](index.html) module"] +pub struct RXOCTETCOUNT_GB_SPEC; +impl crate::RegisterSpec for RXOCTETCOUNT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxoctetcount_gb::R](R) reader structure"] +impl crate::Readable for RXOCTETCOUNT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXOCTETCOUNT_GB to value 0"] +impl crate::Resettable for RXOCTETCOUNT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxoutrangetype.rs b/src/eth/rxoutrangetype.rs new file mode 100644 index 0000000..18e1d13 --- /dev/null +++ b/src/eth/rxoutrangetype.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXOUTRANGETYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames received with length field not equal to the valid frame size\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxoutrangetype](index.html) module"] +pub struct RXOUTRANGETYPE_SPEC; +impl crate::RegisterSpec for RXOUTRANGETYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxoutrangetype::R](R) reader structure"] +impl crate::Readable for RXOUTRANGETYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXOUTRANGETYPE to value 0"] +impl crate::Resettable for RXOUTRANGETYPE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxoversize_g.rs b/src/eth/rxoversize_g.rs new file mode 100644 index 0000000..9fedcb2 --- /dev/null +++ b/src/eth/rxoversize_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXOVERSIZE_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames received without errors with length greater than the max size\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxoversize_g](index.html) module"] +pub struct RXOVERSIZE_G_SPEC; +impl crate::RegisterSpec for RXOVERSIZE_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxoversize_g::R](R) reader structure"] +impl crate::Readable for RXOVERSIZE_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXOVERSIZE_G to value 0"] +impl crate::Resettable for RXOVERSIZE_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxpauseframes.rs b/src/eth/rxpauseframes.rs new file mode 100644 index 0000000..28c7d2a --- /dev/null +++ b/src/eth/rxpauseframes.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXPAUSEFRAMES` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good and valid Pause frames received\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpauseframes](index.html) module"] +pub struct RXPAUSEFRAMES_SPEC; +impl crate::RegisterSpec for RXPAUSEFRAMES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxpauseframes::R](R) reader structure"] +impl crate::Readable for RXPAUSEFRAMES_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXPAUSEFRAMES to value 0"] +impl crate::Resettable for RXPAUSEFRAMES_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxrcverror.rs b/src/eth/rxrcverror.rs new file mode 100644 index 0000000..7f170ef --- /dev/null +++ b/src/eth/rxrcverror.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXRCVERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames received with Receive error or Frame Extension error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxrcverror](index.html) module"] +pub struct RXRCVERROR_SPEC; +impl crate::RegisterSpec for RXRCVERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxrcverror::R](R) reader structure"] +impl crate::Readable for RXRCVERROR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXRCVERROR to value 0"] +impl crate::Resettable for RXRCVERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxrunterror.rs b/src/eth/rxrunterror.rs new file mode 100644 index 0000000..60766fe --- /dev/null +++ b/src/eth/rxrunterror.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXRUNTERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames received with runt error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxrunterror](index.html) module"] +pub struct RXRUNTERROR_SPEC; +impl crate::RegisterSpec for RXRUNTERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxrunterror::R](R) reader structure"] +impl crate::Readable for RXRUNTERROR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXRUNTERROR to value 0"] +impl crate::Resettable for RXRUNTERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxucastframes_g.rs b/src/eth/rxucastframes_g.rs new file mode 100644 index 0000000..dd482f8 --- /dev/null +++ b/src/eth/rxucastframes_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXUCASTFRAMES_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of received good unicast frames\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxucastframes_g](index.html) module"] +pub struct RXUCASTFRAMES_G_SPEC; +impl crate::RegisterSpec for RXUCASTFRAMES_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxucastframes_g::R](R) reader structure"] +impl crate::Readable for RXUCASTFRAMES_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXUCASTFRAMES_G to value 0"] +impl crate::Resettable for RXUCASTFRAMES_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxundersize_g.rs b/src/eth/rxundersize_g.rs new file mode 100644 index 0000000..c397a3b --- /dev/null +++ b/src/eth/rxundersize_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXUNDERSIZE_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames received with length less than 64 bytes\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxundersize_g](index.html) module"] +pub struct RXUNDERSIZE_G_SPEC; +impl crate::RegisterSpec for RXUNDERSIZE_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxundersize_g::R](R) reader structure"] +impl crate::Readable for RXUNDERSIZE_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXUNDERSIZE_G to value 0"] +impl crate::Resettable for RXUNDERSIZE_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxvlanframes_gb.rs b/src/eth/rxvlanframes_gb.rs new file mode 100644 index 0000000..26eab6e --- /dev/null +++ b/src/eth/rxvlanframes_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXVLANFRAMES_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good and bad VLAN frames received\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxvlanframes_gb](index.html) module"] +pub struct RXVLANFRAMES_GB_SPEC; +impl crate::RegisterSpec for RXVLANFRAMES_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxvlanframes_gb::R](R) reader structure"] +impl crate::Readable for RXVLANFRAMES_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXVLANFRAMES_GB to value 0"] +impl crate::Resettable for RXVLANFRAMES_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/rxwdogerror.rs b/src/eth/rxwdogerror.rs new file mode 100644 index 0000000..4a78ac0 --- /dev/null +++ b/src/eth/rxwdogerror.rs @@ -0,0 +1,53 @@ +#[doc = "Register `RXWDOGERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames received with error because of watchdog timeout error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxwdogerror](index.html) module"] +pub struct RXWDOGERROR_SPEC; +impl crate::RegisterSpec for RXWDOGERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxwdogerror::R](R) reader structure"] +impl crate::Readable for RXWDOGERROR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXWDOGERROR to value 0"] +impl crate::Resettable for RXWDOGERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/subsec_inc.rs b/src/eth/subsec_inc.rs new file mode 100644 index 0000000..a96e3f8 --- /dev/null +++ b/src/eth/subsec_inc.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SUBSEC_INC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SUBSEC_INC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SSINC` reader - Sub-Second Increment Valuee"] +pub struct SSINC_R(crate::FieldReader); +impl SSINC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SSINC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSINC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSINC` writer - Sub-Second Increment Valuee"] +pub struct SSINC_W<'a> { + w: &'a mut W, +} +impl<'a> SSINC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Sub-Second Increment Valuee"] + #[inline(always)] + pub fn ssinc(&self) -> SSINC_R { + SSINC_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Sub-Second Increment Valuee"] + #[inline(always)] + pub fn ssinc(&mut self) -> SSINC_W { + SSINC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Holds the 8-bit value by which the Sub-Second register is incremented\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subsec_inc](index.html) module"] +pub struct SUBSEC_INC_SPEC; +impl crate::RegisterSpec for SUBSEC_INC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [subsec_inc::R](R) reader structure"] +impl crate::Readable for SUBSEC_INC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [subsec_inc::W](W) writer structure"] +impl crate::Writable for SUBSEC_INC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SUBSEC_INC to value 0"] +impl crate::Resettable for SUBSEC_INC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/systime_nanosec.rs b/src/eth/systime_nanosec.rs new file mode 100644 index 0000000..d93d159 --- /dev/null +++ b/src/eth/systime_nanosec.rs @@ -0,0 +1,53 @@ +#[doc = "Register `SYSTIME_NANOSEC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TSSS` reader - Timestamp Sub Seconds"] +pub struct TSSS_R(crate::FieldReader); +impl TSSS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TSSS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:30 - Timestamp Sub Seconds"] + #[inline(always)] + pub fn tsss(&self) -> TSSS_R { + TSSS_R::new((self.bits & 0x7fff_ffff) as u32) + } +} +#[doc = "Holds 32 bits of the nano-second field of the system time\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systime_nanosec](index.html) module"] +pub struct SYSTIME_NANOSEC_SPEC; +impl crate::RegisterSpec for SYSTIME_NANOSEC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [systime_nanosec::R](R) reader structure"] +impl crate::Readable for SYSTIME_NANOSEC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYSTIME_NANOSEC to value 0"] +impl crate::Resettable for SYSTIME_NANOSEC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/systime_nsecup.rs b/src/eth/systime_nsecup.rs new file mode 100644 index 0000000..3f9c828 --- /dev/null +++ b/src/eth/systime_nsecup.rs @@ -0,0 +1,150 @@ +#[doc = "Register `SYSTIME_NSECUP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SYSTIME_NSECUP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDSUB` reader - Add or Subtract Time"] +pub struct ADDSUB_R(crate::FieldReader); +impl ADDSUB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADDSUB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDSUB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDSUB` writer - Add or Subtract Time"] +pub struct ADDSUB_W<'a> { + w: &'a mut W, +} +impl<'a> ADDSUB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +#[doc = "Field `TSSS` reader - Timestamp Sub Seconds"] +pub struct TSSS_R(crate::FieldReader); +impl TSSS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TSSS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSSS` writer - Timestamp Sub Seconds"] +pub struct TSSS_W<'a> { + w: &'a mut W, +} +impl<'a> TSSS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7fff_ffff) | (value as u32 & 0x7fff_ffff); + self.w + } +} +impl R { + #[doc = "Bit 31 - Add or Subtract Time"] + #[inline(always)] + pub fn addsub(&self) -> ADDSUB_R { + ADDSUB_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bits 0:30 - Timestamp Sub Seconds"] + #[inline(always)] + pub fn tsss(&self) -> TSSS_R { + TSSS_R::new((self.bits & 0x7fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 31 - Add or Subtract Time"] + #[inline(always)] + pub fn addsub(&mut self) -> ADDSUB_W { + ADDSUB_W { w: self } + } + #[doc = "Bits 0:30 - Timestamp Sub Seconds"] + #[inline(always)] + pub fn tsss(&mut self) -> TSSS_W { + TSSS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systime_nsecup](index.html) module"] +pub struct SYSTIME_NSECUP_SPEC; +impl crate::RegisterSpec for SYSTIME_NSECUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [systime_nsecup::R](R) reader structure"] +impl crate::Readable for SYSTIME_NSECUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [systime_nsecup::W](W) writer structure"] +impl crate::Writable for SYSTIME_NSECUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SYSTIME_NSECUP to value 0"] +impl crate::Resettable for SYSTIME_NSECUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/systime_seconds.rs b/src/eth/systime_seconds.rs new file mode 100644 index 0000000..fde442c --- /dev/null +++ b/src/eth/systime_seconds.rs @@ -0,0 +1,53 @@ +#[doc = "Register `SYSTIME_SECONDS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TSS` reader - Timestamp Second"] +pub struct TSS_R(crate::FieldReader); +impl TSS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TSS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Timestamp Second"] + #[inline(always)] + pub fn tss(&self) -> TSS_R { + TSS_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "Holds the lower 32 bits of the second field of the system time\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systime_seconds](index.html) module"] +pub struct SYSTIME_SECONDS_SPEC; +impl crate::RegisterSpec for SYSTIME_SECONDS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [systime_seconds::R](R) reader structure"] +impl crate::Readable for SYSTIME_SECONDS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYSTIME_SECONDS to value 0"] +impl crate::Resettable for SYSTIME_SECONDS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/systime_secsupdat.rs b/src/eth/systime_secsupdat.rs new file mode 100644 index 0000000..3d1fc21 --- /dev/null +++ b/src/eth/systime_secsupdat.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SYSTIME_SECSUPDAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SYSTIME_SECSUPDAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSS` reader - Timestamp Second"] +pub struct TSS_R(crate::FieldReader); +impl TSS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TSS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSS` writer - Timestamp Second"] +pub struct TSS_W<'a> { + w: &'a mut W, +} +impl<'a> TSS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Timestamp Second"] + #[inline(always)] + pub fn tss(&self) -> TSS_R { + TSS_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Timestamp Second"] + #[inline(always)] + pub fn tss(&mut self) -> TSS_W { + TSS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [systime_secsupdat](index.html) module"] +pub struct SYSTIME_SECSUPDAT_SPEC; +impl crate::RegisterSpec for SYSTIME_SECSUPDAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [systime_secsupdat::R](R) reader structure"] +impl crate::Readable for SYSTIME_SECSUPDAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [systime_secsupdat::W](W) writer structure"] +impl crate::Writable for SYSTIME_SECSUPDAT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SYSTIME_SECSUPDAT to value 0"] +impl crate::Resettable for SYSTIME_SECSUPDAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/target_time_nsec.rs b/src/eth/target_time_nsec.rs new file mode 100644 index 0000000..277d4a0 --- /dev/null +++ b/src/eth/target_time_nsec.rs @@ -0,0 +1,150 @@ +#[doc = "Register `TARGET_TIME_NSEC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TARGET_TIME_NSEC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRGTBUSY` reader - 32 Bits of Hash Table"] +pub struct TRGTBUSY_R(crate::FieldReader); +impl TRGTBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRGTBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRGTBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRGTBUSY` writer - 32 Bits of Hash Table"] +pub struct TRGTBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> TRGTBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +#[doc = "Field `TTSLO` reader - Target Timestamp Low Register"] +pub struct TTSLO_R(crate::FieldReader); +impl TTSLO_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TTSLO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TTSLO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TTSLO` writer - Target Timestamp Low Register"] +pub struct TTSLO_W<'a> { + w: &'a mut W, +} +impl<'a> TTSLO_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7fff_ffff) | (value as u32 & 0x7fff_ffff); + self.w + } +} +impl R { + #[doc = "Bit 31 - 32 Bits of Hash Table"] + #[inline(always)] + pub fn trgtbusy(&self) -> TRGTBUSY_R { + TRGTBUSY_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bits 0:30 - Target Timestamp Low Register"] + #[inline(always)] + pub fn ttslo(&self) -> TTSLO_R { + TTSLO_R::new((self.bits & 0x7fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 31 - 32 Bits of Hash Table"] + #[inline(always)] + pub fn trgtbusy(&mut self) -> TRGTBUSY_W { + TRGTBUSY_W { w: self } + } + #[doc = "Bits 0:30 - Target Timestamp Low Register"] + #[inline(always)] + pub fn ttslo(&mut self) -> TTSLO_W { + TTSLO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Holds the lower 32-bits of time to be compared with the system time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [target_time_nsec](index.html) module"] +pub struct TARGET_TIME_NSEC_SPEC; +impl crate::RegisterSpec for TARGET_TIME_NSEC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [target_time_nsec::R](R) reader structure"] +impl crate::Readable for TARGET_TIME_NSEC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [target_time_nsec::W](W) writer structure"] +impl crate::Writable for TARGET_TIME_NSEC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TARGET_TIME_NSEC to value 0"] +impl crate::Resettable for TARGET_TIME_NSEC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/target_time_secs.rs b/src/eth/target_time_secs.rs new file mode 100644 index 0000000..19ce4e1 --- /dev/null +++ b/src/eth/target_time_secs.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TARGET_TIME_SECS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TARGET_TIME_SECS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSTR` reader - Target Time Seconds Registe"] +pub struct TSTR_R(crate::FieldReader); +impl TSTR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TSTR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTR` writer - Target Time Seconds Registe"] +pub struct TSTR_W<'a> { + w: &'a mut W, +} +impl<'a> TSTR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Target Time Seconds Registe"] + #[inline(always)] + pub fn tstr(&self) -> TSTR_R { + TSTR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Target Time Seconds Registe"] + #[inline(always)] + pub fn tstr(&mut self) -> TSTR_W { + TSTR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Holds the high 32-bits of time to be compared with the system time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [target_time_secs](index.html) module"] +pub struct TARGET_TIME_SECS_SPEC; +impl crate::RegisterSpec for TARGET_TIME_SECS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [target_time_secs::R](R) reader structure"] +impl crate::Readable for TARGET_TIME_SECS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [target_time_secs::W](W) writer structure"] +impl crate::Writable for TARGET_TIME_SECS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TARGET_TIME_SECS to value 0"] +impl crate::Resettable for TARGET_TIME_SECS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/timestamp_ctrl.rs b/src/eth/timestamp_ctrl.rs new file mode 100644 index 0000000..8b5c6d1 --- /dev/null +++ b/src/eth/timestamp_ctrl.rs @@ -0,0 +1,1043 @@ +#[doc = "Register `TIMESTAMP_CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TIMESTAMP_CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ATSEN3` reader - Auxiliary Snapshot 3 Enable"] +pub struct ATSEN3_R(crate::FieldReader); +impl ATSEN3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ATSEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ATSEN3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ATSEN3` writer - Auxiliary Snapshot 3 Enable"] +pub struct ATSEN3_W<'a> { + w: &'a mut W, +} +impl<'a> ATSEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `ATSEN2` reader - Auxiliary Snapshot 2 Enable"] +pub struct ATSEN2_R(crate::FieldReader); +impl ATSEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ATSEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ATSEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ATSEN2` writer - Auxiliary Snapshot 2 Enable"] +pub struct ATSEN2_W<'a> { + w: &'a mut W, +} +impl<'a> ATSEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `ATSEN1` reader - Auxiliary Snapshot 1 Enable"] +pub struct ATSEN1_R(crate::FieldReader); +impl ATSEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ATSEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ATSEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ATSEN1` writer - Auxiliary Snapshot 1 Enable"] +pub struct ATSEN1_W<'a> { + w: &'a mut W, +} +impl<'a> ATSEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `ATSEN0` reader - Auxiliary Snapshot 0 Enable"] +pub struct ATSEN0_R(crate::FieldReader); +impl ATSEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ATSEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ATSEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ATSEN0` writer - Auxiliary Snapshot 0 Enable"] +pub struct ATSEN0_W<'a> { + w: &'a mut W, +} +impl<'a> ATSEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `ATSFC` reader - Auxiliary Snapshot FIFO Clear"] +pub struct ATSFC_R(crate::FieldReader); +impl ATSFC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ATSFC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ATSFC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ATSFC` writer - Auxiliary Snapshot FIFO Clear"] +pub struct ATSFC_W<'a> { + w: &'a mut W, +} +impl<'a> ATSFC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `TSENMACADDR` reader - Enable MAC address for PTP Frame Filtering"] +pub struct TSENMACADDR_R(crate::FieldReader); +impl TSENMACADDR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENMACADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENMACADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENMACADDR` writer - Enable MAC address for PTP Frame Filtering"] +pub struct TSENMACADDR_W<'a> { + w: &'a mut W, +} +impl<'a> TSENMACADDR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SNAPTYPSEL` reader - Select PTP packets for Taking Snapshots"] +pub struct SNAPTYPSEL_R(crate::FieldReader); +impl SNAPTYPSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SNAPTYPSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SNAPTYPSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SNAPTYPSEL` writer - Select PTP packets for Taking Snapshots"] +pub struct SNAPTYPSEL_W<'a> { + w: &'a mut W, +} +impl<'a> SNAPTYPSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `TSMSTRENA` reader - Enable Snapshot for Messages Relevant to Master"] +pub struct TSMSTRENA_R(crate::FieldReader); +impl TSMSTRENA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSMSTRENA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSMSTRENA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSMSTRENA` writer - Enable Snapshot for Messages Relevant to Master"] +pub struct TSMSTRENA_W<'a> { + w: &'a mut W, +} +impl<'a> TSMSTRENA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TSEVNTENA` reader - Enable Timestamp Snapshot for Event Messages"] +pub struct TSEVNTENA_R(crate::FieldReader); +impl TSEVNTENA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSEVNTENA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSEVNTENA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSEVNTENA` writer - Enable Timestamp Snapshot for Event Messages"] +pub struct TSEVNTENA_W<'a> { + w: &'a mut W, +} +impl<'a> TSEVNTENA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TSIPV4ENA` reader - Enable Processing of PTP Frames Sent over IPv4-UDP"] +pub struct TSIPV4ENA_R(crate::FieldReader); +impl TSIPV4ENA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSIPV4ENA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSIPV4ENA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSIPV4ENA` writer - Enable Processing of PTP Frames Sent over IPv4-UDP"] +pub struct TSIPV4ENA_W<'a> { + w: &'a mut W, +} +impl<'a> TSIPV4ENA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TSIPV6ENA` reader - Enable Processing of PTP Frames Sent over IPv6-UDP"] +pub struct TSIPV6ENA_R(crate::FieldReader); +impl TSIPV6ENA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSIPV6ENA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSIPV6ENA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSIPV6ENA` writer - Enable Processing of PTP Frames Sent over IPv6-UDP"] +pub struct TSIPV6ENA_W<'a> { + w: &'a mut W, +} +impl<'a> TSIPV6ENA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TSIPENA` reader - Enable Processing of PTP over Ethernet Frames"] +pub struct TSIPENA_R(crate::FieldReader); +impl TSIPENA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSIPENA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSIPENA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSIPENA` writer - Enable Processing of PTP over Ethernet Frames"] +pub struct TSIPENA_W<'a> { + w: &'a mut W, +} +impl<'a> TSIPENA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSVER2ENA` reader - Enable PTP packet Processing for Version 2 Format"] +pub struct TSVER2ENA_R(crate::FieldReader); +impl TSVER2ENA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSVER2ENA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSVER2ENA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSVER2ENA` writer - Enable PTP packet Processing for Version 2 Format"] +pub struct TSVER2ENA_W<'a> { + w: &'a mut W, +} +impl<'a> TSVER2ENA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TSCTRLSSR` reader - Timestamp Digital or Binary Rollover Control"] +pub struct TSCTRLSSR_R(crate::FieldReader); +impl TSCTRLSSR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSCTRLSSR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSCTRLSSR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSCTRLSSR` writer - Timestamp Digital or Binary Rollover Control"] +pub struct TSCTRLSSR_W<'a> { + w: &'a mut W, +} +impl<'a> TSCTRLSSR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TSENALL` reader - Enable Timestamp for All Frames"] +pub struct TSENALL_R(crate::FieldReader); +impl TSENALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENALL` writer - Enable Timestamp for All Frames"] +pub struct TSENALL_W<'a> { + w: &'a mut W, +} +impl<'a> TSENALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TSADDRREG` reader - Addend Reg Update"] +pub struct TSADDRREG_R(crate::FieldReader); +impl TSADDRREG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSADDRREG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSADDRREG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSADDRREG` writer - Addend Reg Update"] +pub struct TSADDRREG_W<'a> { + w: &'a mut W, +} +impl<'a> TSADDRREG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TSTRIG` reader - Timestamp Interrupt Trigger Enable"] +pub struct TSTRIG_R(crate::FieldReader); +impl TSTRIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSTRIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSTRIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSTRIG` writer - Timestamp Interrupt Trigger Enable"] +pub struct TSTRIG_W<'a> { + w: &'a mut W, +} +impl<'a> TSTRIG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TSUPDT` reader - Timestamp Update"] +pub struct TSUPDT_R(crate::FieldReader); +impl TSUPDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSUPDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSUPDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSUPDT` writer - Timestamp Update"] +pub struct TSUPDT_W<'a> { + w: &'a mut W, +} +impl<'a> TSUPDT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TSINIT` reader - Timestamp Initialize"] +pub struct TSINIT_R(crate::FieldReader); +impl TSINIT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSINIT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSINIT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSINIT` writer - Timestamp Initialize"] +pub struct TSINIT_W<'a> { + w: &'a mut W, +} +impl<'a> TSINIT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TSCFUPDT` reader - Timestamp Fine or Coarse Update"] +pub struct TSCFUPDT_R(crate::FieldReader); +impl TSCFUPDT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSCFUPDT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSCFUPDT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSCFUPDT` writer - Timestamp Fine or Coarse Update"] +pub struct TSCFUPDT_W<'a> { + w: &'a mut W, +} +impl<'a> TSCFUPDT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TSENA` reader - Timestamp Enable"] +pub struct TSENA_R(crate::FieldReader); +impl TSENA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TSENA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENA` writer - Timestamp Enable"] +pub struct TSENA_W<'a> { + w: &'a mut W, +} +impl<'a> TSENA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 28 - Auxiliary Snapshot 3 Enable"] + #[inline(always)] + pub fn atsen3(&self) -> ATSEN3_R { + ATSEN3_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 27 - Auxiliary Snapshot 2 Enable"] + #[inline(always)] + pub fn atsen2(&self) -> ATSEN2_R { + ATSEN2_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 26 - Auxiliary Snapshot 1 Enable"] + #[inline(always)] + pub fn atsen1(&self) -> ATSEN1_R { + ATSEN1_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 25 - Auxiliary Snapshot 0 Enable"] + #[inline(always)] + pub fn atsen0(&self) -> ATSEN0_R { + ATSEN0_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 24 - Auxiliary Snapshot FIFO Clear"] + #[inline(always)] + pub fn atsfc(&self) -> ATSFC_R { + ATSFC_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 18 - Enable MAC address for PTP Frame Filtering"] + #[inline(always)] + pub fn tsenmacaddr(&self) -> TSENMACADDR_R { + TSENMACADDR_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Select PTP packets for Taking Snapshots"] + #[inline(always)] + pub fn snaptypsel(&self) -> SNAPTYPSEL_R { + SNAPTYPSEL_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master"] + #[inline(always)] + pub fn tsmstrena(&self) -> TSMSTRENA_R { + TSMSTRENA_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 14 - Enable Timestamp Snapshot for Event Messages"] + #[inline(always)] + pub fn tsevntena(&self) -> TSEVNTENA_R { + TSEVNTENA_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - Enable Processing of PTP Frames Sent over IPv4-UDP"] + #[inline(always)] + pub fn tsipv4ena(&self) -> TSIPV4ENA_R { + TSIPV4ENA_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 12 - Enable Processing of PTP Frames Sent over IPv6-UDP"] + #[inline(always)] + pub fn tsipv6ena(&self) -> TSIPV6ENA_R { + TSIPV6ENA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable Processing of PTP over Ethernet Frames"] + #[inline(always)] + pub fn tsipena(&self) -> TSIPENA_R { + TSIPENA_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - Enable PTP packet Processing for Version 2 Format"] + #[inline(always)] + pub fn tsver2ena(&self) -> TSVER2ENA_R { + TSVER2ENA_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - Timestamp Digital or Binary Rollover Control"] + #[inline(always)] + pub fn tsctrlssr(&self) -> TSCTRLSSR_R { + TSCTRLSSR_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - Enable Timestamp for All Frames"] + #[inline(always)] + pub fn tsenall(&self) -> TSENALL_R { + TSENALL_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 5 - Addend Reg Update"] + #[inline(always)] + pub fn tsaddrreg(&self) -> TSADDRREG_R { + TSADDRREG_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - Timestamp Interrupt Trigger Enable"] + #[inline(always)] + pub fn tstrig(&self) -> TSTRIG_R { + TSTRIG_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Timestamp Update"] + #[inline(always)] + pub fn tsupdt(&self) -> TSUPDT_R { + TSUPDT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Timestamp Initialize"] + #[inline(always)] + pub fn tsinit(&self) -> TSINIT_R { + TSINIT_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Timestamp Fine or Coarse Update"] + #[inline(always)] + pub fn tscfupdt(&self) -> TSCFUPDT_R { + TSCFUPDT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Timestamp Enable"] + #[inline(always)] + pub fn tsena(&self) -> TSENA_R { + TSENA_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 28 - Auxiliary Snapshot 3 Enable"] + #[inline(always)] + pub fn atsen3(&mut self) -> ATSEN3_W { + ATSEN3_W { w: self } + } + #[doc = "Bit 27 - Auxiliary Snapshot 2 Enable"] + #[inline(always)] + pub fn atsen2(&mut self) -> ATSEN2_W { + ATSEN2_W { w: self } + } + #[doc = "Bit 26 - Auxiliary Snapshot 1 Enable"] + #[inline(always)] + pub fn atsen1(&mut self) -> ATSEN1_W { + ATSEN1_W { w: self } + } + #[doc = "Bit 25 - Auxiliary Snapshot 0 Enable"] + #[inline(always)] + pub fn atsen0(&mut self) -> ATSEN0_W { + ATSEN0_W { w: self } + } + #[doc = "Bit 24 - Auxiliary Snapshot FIFO Clear"] + #[inline(always)] + pub fn atsfc(&mut self) -> ATSFC_W { + ATSFC_W { w: self } + } + #[doc = "Bit 18 - Enable MAC address for PTP Frame Filtering"] + #[inline(always)] + pub fn tsenmacaddr(&mut self) -> TSENMACADDR_W { + TSENMACADDR_W { w: self } + } + #[doc = "Bits 16:17 - Select PTP packets for Taking Snapshots"] + #[inline(always)] + pub fn snaptypsel(&mut self) -> SNAPTYPSEL_W { + SNAPTYPSEL_W { w: self } + } + #[doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master"] + #[inline(always)] + pub fn tsmstrena(&mut self) -> TSMSTRENA_W { + TSMSTRENA_W { w: self } + } + #[doc = "Bit 14 - Enable Timestamp Snapshot for Event Messages"] + #[inline(always)] + pub fn tsevntena(&mut self) -> TSEVNTENA_W { + TSEVNTENA_W { w: self } + } + #[doc = "Bit 13 - Enable Processing of PTP Frames Sent over IPv4-UDP"] + #[inline(always)] + pub fn tsipv4ena(&mut self) -> TSIPV4ENA_W { + TSIPV4ENA_W { w: self } + } + #[doc = "Bit 12 - Enable Processing of PTP Frames Sent over IPv6-UDP"] + #[inline(always)] + pub fn tsipv6ena(&mut self) -> TSIPV6ENA_W { + TSIPV6ENA_W { w: self } + } + #[doc = "Bit 11 - Enable Processing of PTP over Ethernet Frames"] + #[inline(always)] + pub fn tsipena(&mut self) -> TSIPENA_W { + TSIPENA_W { w: self } + } + #[doc = "Bit 10 - Enable PTP packet Processing for Version 2 Format"] + #[inline(always)] + pub fn tsver2ena(&mut self) -> TSVER2ENA_W { + TSVER2ENA_W { w: self } + } + #[doc = "Bit 9 - Timestamp Digital or Binary Rollover Control"] + #[inline(always)] + pub fn tsctrlssr(&mut self) -> TSCTRLSSR_W { + TSCTRLSSR_W { w: self } + } + #[doc = "Bit 8 - Enable Timestamp for All Frames"] + #[inline(always)] + pub fn tsenall(&mut self) -> TSENALL_W { + TSENALL_W { w: self } + } + #[doc = "Bit 5 - Addend Reg Update"] + #[inline(always)] + pub fn tsaddrreg(&mut self) -> TSADDRREG_W { + TSADDRREG_W { w: self } + } + #[doc = "Bit 4 - Timestamp Interrupt Trigger Enable"] + #[inline(always)] + pub fn tstrig(&mut self) -> TSTRIG_W { + TSTRIG_W { w: self } + } + #[doc = "Bit 3 - Timestamp Update"] + #[inline(always)] + pub fn tsupdt(&mut self) -> TSUPDT_W { + TSUPDT_W { w: self } + } + #[doc = "Bit 2 - Timestamp Initialize"] + #[inline(always)] + pub fn tsinit(&mut self) -> TSINIT_W { + TSINIT_W { w: self } + } + #[doc = "Bit 1 - Timestamp Fine or Coarse Update"] + #[inline(always)] + pub fn tscfupdt(&mut self) -> TSCFUPDT_W { + TSCFUPDT_W { w: self } + } + #[doc = "Bit 0 - Timestamp Enable"] + #[inline(always)] + pub fn tsena(&mut self) -> TSENA_W { + TSENA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Controls the IEEE 1588 timestamp generation and update logic\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timestamp_ctrl](index.html) module"] +pub struct TIMESTAMP_CTRL_SPEC; +impl crate::RegisterSpec for TIMESTAMP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [timestamp_ctrl::R](R) reader structure"] +impl crate::Readable for TIMESTAMP_CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [timestamp_ctrl::W](W) writer structure"] +impl crate::Writable for TIMESTAMP_CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TIMESTAMP_CTRL to value 0"] +impl crate::Resettable for TIMESTAMP_CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/timestampaddend.rs b/src/eth/timestampaddend.rs new file mode 100644 index 0000000..e370b24 --- /dev/null +++ b/src/eth/timestampaddend.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TIMESTAMPADDEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TIMESTAMPADDEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSAR` reader - Timestamp Addend Register"] +pub struct TSAR_R(crate::FieldReader); +impl TSAR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TSAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSAR` writer - Timestamp Addend Register"] +pub struct TSAR_W<'a> { + w: &'a mut W, +} +impl<'a> TSAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Timestamp Addend Register"] + #[inline(always)] + pub fn tsar(&self) -> TSAR_R { + TSAR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Timestamp Addend Register"] + #[inline(always)] + pub fn tsar(&mut self) -> TSAR_W { + TSAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timestampaddend](index.html) module"] +pub struct TIMESTAMPADDEND_SPEC; +impl crate::RegisterSpec for TIMESTAMPADDEND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [timestampaddend::R](R) reader structure"] +impl crate::Readable for TIMESTAMPADDEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [timestampaddend::W](W) writer structure"] +impl crate::Writable for TIMESTAMPADDEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TIMESTAMPADDEND to value 0"] +impl crate::Resettable for TIMESTAMPADDEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/tx1024maxoct_gb.rs b/src/eth/tx1024maxoct_gb.rs new file mode 100644 index 0000000..9a01e6d --- /dev/null +++ b/src/eth/tx1024maxoct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TX1024MAXOCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 1024 to max bytes\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx1024maxoct_gb](index.html) module"] +pub struct TX1024MAXOCT_GB_SPEC; +impl crate::RegisterSpec for TX1024MAXOCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tx1024maxoct_gb::R](R) reader structure"] +impl crate::Readable for TX1024MAXOCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TX1024MAXOCT_GB to value 0"] +impl crate::Resettable for TX1024MAXOCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/tx128to255oct_gb.rs b/src/eth/tx128to255oct_gb.rs new file mode 100644 index 0000000..ebb543e --- /dev/null +++ b/src/eth/tx128to255oct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TX128TO255OCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 128 to 255\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx128to255oct_gb](index.html) module"] +pub struct TX128TO255OCT_GB_SPEC; +impl crate::RegisterSpec for TX128TO255OCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tx128to255oct_gb::R](R) reader structure"] +impl crate::Readable for TX128TO255OCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TX128TO255OCT_GB to value 0"] +impl crate::Resettable for TX128TO255OCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/tx256to511oct_gb.rs b/src/eth/tx256to511oct_gb.rs new file mode 100644 index 0000000..ba6762b --- /dev/null +++ b/src/eth/tx256to511oct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TX256TO511OCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 256 to 511\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx256to511oct_gb](index.html) module"] +pub struct TX256TO511OCT_GB_SPEC; +impl crate::RegisterSpec for TX256TO511OCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tx256to511oct_gb::R](R) reader structure"] +impl crate::Readable for TX256TO511OCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TX256TO511OCT_GB to value 0"] +impl crate::Resettable for TX256TO511OCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/tx512to1023oct_gb.rs b/src/eth/tx512to1023oct_gb.rs new file mode 100644 index 0000000..d7a0121 --- /dev/null +++ b/src/eth/tx512to1023oct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TX512TO1023OCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 512 to 1023\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx512to1023oct_gb](index.html) module"] +pub struct TX512TO1023OCT_GB_SPEC; +impl crate::RegisterSpec for TX512TO1023OCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tx512to1023oct_gb::R](R) reader structure"] +impl crate::Readable for TX512TO1023OCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TX512TO1023OCT_GB to value 0"] +impl crate::Resettable for TX512TO1023OCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/tx64oct_gb.rs b/src/eth/tx64oct_gb.rs new file mode 100644 index 0000000..beac064 --- /dev/null +++ b/src/eth/tx64oct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TX64OCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 64\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx64oct_gb](index.html) module"] +pub struct TX64OCT_GB_SPEC; +impl crate::RegisterSpec for TX64OCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tx64oct_gb::R](R) reader structure"] +impl crate::Readable for TX64OCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TX64OCT_GB to value 0"] +impl crate::Resettable for TX64OCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/tx65to127oct_gb.rs b/src/eth/tx65to127oct_gb.rs new file mode 100644 index 0000000..2bb4150 --- /dev/null +++ b/src/eth/tx65to127oct_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TX65TO127OCT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 65 to 127\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx65to127oct_gb](index.html) module"] +pub struct TX65TO127OCT_GB_SPEC; +impl crate::RegisterSpec for TX65TO127OCT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tx65to127oct_gb::R](R) reader structure"] +impl crate::Readable for TX65TO127OCT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TX65TO127OCT_GB to value 0"] +impl crate::Resettable for TX65TO127OCT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txbcastframe_gb.rs b/src/eth/txbcastframe_gb.rs new file mode 100644 index 0000000..2b249b3 --- /dev/null +++ b/src/eth/txbcastframe_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXBCASTFRAME_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC number of good and bad broadcast frames transmitted\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcastframe_gb](index.html) module"] +pub struct TXBCASTFRAME_GB_SPEC; +impl crate::RegisterSpec for TXBCASTFRAME_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcastframe_gb::R](R) reader structure"] +impl crate::Readable for TXBCASTFRAME_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBCASTFRAME_GB to value 0"] +impl crate::Resettable for TXBCASTFRAME_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txbcastframes_g.rs b/src/eth/txbcastframes_g.rs new file mode 100644 index 0000000..2af75d9 --- /dev/null +++ b/src/eth/txbcastframes_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXBCASTFRAMES_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Good Broadcast Frames Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcastframes_g](index.html) module"] +pub struct TXBCASTFRAMES_G_SPEC; +impl crate::RegisterSpec for TXBCASTFRAMES_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txbcastframes_g::R](R) reader structure"] +impl crate::Readable for TXBCASTFRAMES_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXBCASTFRAMES_G to value 0"] +impl crate::Resettable for TXBCASTFRAMES_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txcarriererror.rs b/src/eth/txcarriererror.rs new file mode 100644 index 0000000..9d70625 --- /dev/null +++ b/src/eth/txcarriererror.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXCARRIERERROR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of aborted frames because of carrier sense error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txcarriererror](index.html) module"] +pub struct TXCARRIERERROR_SPEC; +impl crate::RegisterSpec for TXCARRIERERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txcarriererror::R](R) reader structure"] +impl crate::Readable for TXCARRIERERROR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXCARRIERERROR to value 0"] +impl crate::Resettable for TXCARRIERERROR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txdeferred.rs b/src/eth/txdeferred.rs new file mode 100644 index 0000000..6bd6348 --- /dev/null +++ b/src/eth/txdeferred.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXDEFERRED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of successfully transmitted frames after a deferral\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txdeferred](index.html) module"] +pub struct TXDEFERRED_SPEC; +impl crate::RegisterSpec for TXDEFERRED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txdeferred::R](R) reader structure"] +impl crate::Readable for TXDEFERRED_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXDEFERRED to value 0"] +impl crate::Resettable for TXDEFERRED_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txexcessdef.rs b/src/eth/txexcessdef.rs new file mode 100644 index 0000000..884f65d --- /dev/null +++ b/src/eth/txexcessdef.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXEXCESSDEF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames aborted because of excessive deferral error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txexcessdef](index.html) module"] +pub struct TXEXCESSDEF_SPEC; +impl crate::RegisterSpec for TXEXCESSDEF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txexcessdef::R](R) reader structure"] +impl crate::Readable for TXEXCESSDEF_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXEXCESSDEF to value 0"] +impl crate::Resettable for TXEXCESSDEF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txexesscol.rs b/src/eth/txexesscol.rs new file mode 100644 index 0000000..2fb319b --- /dev/null +++ b/src/eth/txexesscol.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXEXESSCOL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of aborted frames because of excessive collision errors\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txexesscol](index.html) module"] +pub struct TXEXESSCOL_SPEC; +impl crate::RegisterSpec for TXEXESSCOL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txexesscol::R](R) reader structure"] +impl crate::Readable for TXEXESSCOL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXEXESSCOL to value 0"] +impl crate::Resettable for TXEXESSCOL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txframecount_g.rs b/src/eth/txframecount_g.rs new file mode 100644 index 0000000..fb091c1 --- /dev/null +++ b/src/eth/txframecount_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXFRAMECOUNT_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good frames transmitted\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txframecount_g](index.html) module"] +pub struct TXFRAMECOUNT_G_SPEC; +impl crate::RegisterSpec for TXFRAMECOUNT_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txframecount_g::R](R) reader structure"] +impl crate::Readable for TXFRAMECOUNT_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXFRAMECOUNT_G to value 0"] +impl crate::Resettable for TXFRAMECOUNT_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txframecount_gb.rs b/src/eth/txframecount_gb.rs new file mode 100644 index 0000000..36e4fa6 --- /dev/null +++ b/src/eth/txframecount_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXFRAMECOUNT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Frame Count Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txframecount_gb](index.html) module"] +pub struct TXFRAMECOUNT_GB_SPEC; +impl crate::RegisterSpec for TXFRAMECOUNT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txframecount_gb::R](R) reader structure"] +impl crate::Readable for TXFRAMECOUNT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXFRAMECOUNT_GB to value 0"] +impl crate::Resettable for TXFRAMECOUNT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txlanframes_g.rs b/src/eth/txlanframes_g.rs new file mode 100644 index 0000000..7d55d4a --- /dev/null +++ b/src/eth/txlanframes_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXLANFRAMES_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good VLAN frames transmitted\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txlanframes_g](index.html) module"] +pub struct TXLANFRAMES_G_SPEC; +impl crate::RegisterSpec for TXLANFRAMES_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txlanframes_g::R](R) reader structure"] +impl crate::Readable for TXLANFRAMES_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXLANFRAMES_G to value 0"] +impl crate::Resettable for TXLANFRAMES_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txlatecol.rs b/src/eth/txlatecol.rs new file mode 100644 index 0000000..4572fac --- /dev/null +++ b/src/eth/txlatecol.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXLATECOL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of aborted frames because of late collision error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txlatecol](index.html) module"] +pub struct TXLATECOL_SPEC; +impl crate::RegisterSpec for TXLATECOL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txlatecol::R](R) reader structure"] +impl crate::Readable for TXLATECOL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXLATECOL to value 0"] +impl crate::Resettable for TXLATECOL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txmcastframe_gb.rs b/src/eth/txmcastframe_gb.rs new file mode 100644 index 0000000..a7032a6 --- /dev/null +++ b/src/eth/txmcastframe_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXMCASTFRAME_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC number of good and bad MULTIcast frames transmitted\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txmcastframe_gb](index.html) module"] +pub struct TXMCASTFRAME_GB_SPEC; +impl crate::RegisterSpec for TXMCASTFRAME_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txmcastframe_gb::R](R) reader structure"] +impl crate::Readable for TXMCASTFRAME_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXMCASTFRAME_GB to value 0"] +impl crate::Resettable for TXMCASTFRAME_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txmcastframes_g.rs b/src/eth/txmcastframes_g.rs new file mode 100644 index 0000000..02d8306 --- /dev/null +++ b/src/eth/txmcastframes_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXMCASTFRAMES_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Good Multicast Frames Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txmcastframes_g](index.html) module"] +pub struct TXMCASTFRAMES_G_SPEC; +impl crate::RegisterSpec for TXMCASTFRAMES_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txmcastframes_g::R](R) reader structure"] +impl crate::Readable for TXMCASTFRAMES_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXMCASTFRAMES_G to value 0"] +impl crate::Resettable for TXMCASTFRAMES_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txmulticol_g.rs b/src/eth/txmulticol_g.rs new file mode 100644 index 0000000..8fe9b1e --- /dev/null +++ b/src/eth/txmulticol_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXMULTICOL_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of successfully transmitted frames after multiple collisions\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txmulticol_g](index.html) module"] +pub struct TXMULTICOL_G_SPEC; +impl crate::RegisterSpec for TXMULTICOL_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txmulticol_g::R](R) reader structure"] +impl crate::Readable for TXMULTICOL_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXMULTICOL_G to value 0"] +impl crate::Resettable for TXMULTICOL_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txoctetcount_g.rs b/src/eth/txoctetcount_g.rs new file mode 100644 index 0000000..d156c1f --- /dev/null +++ b/src/eth/txoctetcount_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXOCTETCOUNT_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of bytes"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of bytes transmitted frames only in good frames\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txoctetcount_g](index.html) module"] +pub struct TXOCTETCOUNT_G_SPEC; +impl crate::RegisterSpec for TXOCTETCOUNT_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txoctetcount_g::R](R) reader structure"] +impl crate::Readable for TXOCTETCOUNT_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXOCTETCOUNT_G to value 0"] +impl crate::Resettable for TXOCTETCOUNT_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txoctetcount_gb.rs b/src/eth/txoctetcount_gb.rs new file mode 100644 index 0000000..9f2dead --- /dev/null +++ b/src/eth/txoctetcount_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXOCTETCOUNT_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of bytes"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Transmit Count\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txoctetcount_gb](index.html) module"] +pub struct TXOCTETCOUNT_GB_SPEC; +impl crate::RegisterSpec for TXOCTETCOUNT_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txoctetcount_gb::R](R) reader structure"] +impl crate::Readable for TXOCTETCOUNT_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXOCTETCOUNT_GB to value 0"] +impl crate::Resettable for TXOCTETCOUNT_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txoversize_g.rs b/src/eth/txoversize_g.rs new file mode 100644 index 0000000..782d7df --- /dev/null +++ b/src/eth/txoversize_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXOVERSIZE_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of frames transmitted without errors\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txoversize_g](index.html) module"] +pub struct TXOVERSIZE_G_SPEC; +impl crate::RegisterSpec for TXOVERSIZE_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txoversize_g::R](R) reader structure"] +impl crate::Readable for TXOVERSIZE_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXOVERSIZE_G to value 0"] +impl crate::Resettable for TXOVERSIZE_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txpauseframes.rs b/src/eth/txpauseframes.rs new file mode 100644 index 0000000..ec6aa42 --- /dev/null +++ b/src/eth/txpauseframes.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXPAUSEFRAMES` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of good pause frames transmitted\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txpauseframes](index.html) module"] +pub struct TXPAUSEFRAMES_SPEC; +impl crate::RegisterSpec for TXPAUSEFRAMES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txpauseframes::R](R) reader structure"] +impl crate::Readable for TXPAUSEFRAMES_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXPAUSEFRAMES to value 0"] +impl crate::Resettable for TXPAUSEFRAMES_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txsinglecol_g.rs b/src/eth/txsinglecol_g.rs new file mode 100644 index 0000000..88bf681 --- /dev/null +++ b/src/eth/txsinglecol_g.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXSINGLECOL_G` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC Number of successfully transmitted frames after a single collision\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txsinglecol_g](index.html) module"] +pub struct TXSINGLECOL_G_SPEC; +impl crate::RegisterSpec for TXSINGLECOL_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txsinglecol_g::R](R) reader structure"] +impl crate::Readable for TXSINGLECOL_G_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXSINGLECOL_G to value 0"] +impl crate::Resettable for TXSINGLECOL_G_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txucastframe_gb.rs b/src/eth/txucastframe_gb.rs new file mode 100644 index 0000000..27f4c10 --- /dev/null +++ b/src/eth/txucastframe_gb.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXUCASTFRAME_GB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC number of good and bad unicast frames transmitted\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txucastframe_gb](index.html) module"] +pub struct TXUCASTFRAME_GB_SPEC; +impl crate::RegisterSpec for TXUCASTFRAME_GB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txucastframe_gb::R](R) reader structure"] +impl crate::Readable for TXUCASTFRAME_GB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXUCASTFRAME_GB to value 0"] +impl crate::Resettable for TXUCASTFRAME_GB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/txundererr.rs b/src/eth/txundererr.rs new file mode 100644 index 0000000..5f9c1f9 --- /dev/null +++ b/src/eth/txundererr.rs @@ -0,0 +1,53 @@ +#[doc = "Register `TXUNDERERR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Number of frames"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "MMC number of frames aborted because of frame underflow error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txundererr](index.html) module"] +pub struct TXUNDERERR_SPEC; +impl crate::RegisterSpec for TXUNDERERR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txundererr::R](R) reader structure"] +impl crate::Readable for TXUNDERERR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXUNDERERR to value 0"] +impl crate::Resettable for TXUNDERERR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/vlan_hashtable.rs b/src/eth/vlan_hashtable.rs new file mode 100644 index 0000000..9dc2ee4 --- /dev/null +++ b/src/eth/vlan_hashtable.rs @@ -0,0 +1,103 @@ +#[doc = "Register `VLAN_HASHTABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VLAN_HASHTABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VLHT` reader - VLAN Hash Table"] +pub struct VLHT_R(crate::FieldReader); +impl VLHT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VLHT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VLHT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VLHT` writer - VLAN Hash Table"] +pub struct VLHT_W<'a> { + w: &'a mut W, +} +impl<'a> VLHT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - VLAN Hash Table"] + #[inline(always)] + pub fn vlht(&self) -> VLHT_R { + VLHT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - VLAN Hash Table"] + #[inline(always)] + pub fn vlht(&mut self) -> VLHT_W { + VLHT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Holds the VLAN Hash Table\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vlan_hashtable](index.html) module"] +pub struct VLAN_HASHTABLE_SPEC; +impl crate::RegisterSpec for VLAN_HASHTABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vlan_hashtable::R](R) reader structure"] +impl crate::Readable for VLAN_HASHTABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vlan_hashtable::W](W) writer structure"] +impl crate::Writable for VLAN_HASHTABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VLAN_HASHTABLE to value 0"] +impl crate::Resettable for VLAN_HASHTABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/eth/vlan_increplace.rs b/src/eth/vlan_increplace.rs new file mode 100644 index 0000000..45a45c2 --- /dev/null +++ b/src/eth/vlan_increplace.rs @@ -0,0 +1,234 @@ +#[doc = "Register `VLAN_INCREPLACE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VLAN_INCREPLACE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CSVL` reader - C-VLAN or S-VLAN"] +pub struct CSVL_R(crate::FieldReader); +impl CSVL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSVL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSVL` writer - C-VLAN or S-VLAN"] +pub struct CSVL_W<'a> { + w: &'a mut W, +} +impl<'a> CSVL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `VLP` reader - VLAN Priority Control"] +pub struct VLP_R(crate::FieldReader); +impl VLP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VLP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VLP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VLP` writer - VLAN Priority Control"] +pub struct VLP_W<'a> { + w: &'a mut W, +} +impl<'a> VLP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `VLC` reader - VLAN Tag Control in Transmit Frames"] +pub struct VLC_R(crate::FieldReader); +impl VLC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VLC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VLC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VLC` writer - VLAN Tag Control in Transmit Frames"] +pub struct VLC_W<'a> { + w: &'a mut W, +} +impl<'a> VLC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `VLT` reader - VLAN Tag for Transmit Frames"] +pub struct VLT_R(crate::FieldReader); +impl VLT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VLT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VLT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VLT` writer - VLAN Tag for Transmit Frames"] +pub struct VLT_W<'a> { + w: &'a mut W, +} +impl<'a> VLT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bit 19 - C-VLAN or S-VLAN"] + #[inline(always)] + pub fn csvl(&self) -> CSVL_R { + CSVL_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 18 - VLAN Priority Control"] + #[inline(always)] + pub fn vlp(&self) -> VLP_R { + VLP_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bits 16:17 - VLAN Tag Control in Transmit Frames"] + #[inline(always)] + pub fn vlc(&self) -> VLC_R { + VLC_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 0:15 - VLAN Tag for Transmit Frames"] + #[inline(always)] + pub fn vlt(&self) -> VLT_R { + VLT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 19 - C-VLAN or S-VLAN"] + #[inline(always)] + pub fn csvl(&mut self) -> CSVL_W { + CSVL_W { w: self } + } + #[doc = "Bit 18 - VLAN Priority Control"] + #[inline(always)] + pub fn vlp(&mut self) -> VLP_W { + VLP_W { w: self } + } + #[doc = "Bits 16:17 - VLAN Tag Control in Transmit Frames"] + #[inline(always)] + pub fn vlc(&mut self) -> VLC_W { + VLC_W { w: self } + } + #[doc = "Bits 0:15 - VLAN Tag for Transmit Frames"] + #[inline(always)] + pub fn vlt(&mut self) -> VLT_W { + VLT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Holds the VLAN Tag for insertion into or replacement in the transmit frames\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vlan_increplace](index.html) module"] +pub struct VLAN_INCREPLACE_SPEC; +impl crate::RegisterSpec for VLAN_INCREPLACE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vlan_increplace::R](R) reader structure"] +impl crate::Readable for VLAN_INCREPLACE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vlan_increplace::W](W) writer structure"] +impl crate::Writable for VLAN_INCREPLACE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets VLAN_INCREPLACE to value 0"] +impl crate::Resettable for VLAN_INCREPLACE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/generic.rs b/src/generic.rs new file mode 100644 index 0000000..7615964 --- /dev/null +++ b/src/generic.rs @@ -0,0 +1,260 @@ +use core::marker; +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + fn reset_value() -> Self::Ux; +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::reset_value()) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::reset_value(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg +where + REG::Ux: Default, +{ + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + (*f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }))) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub struct FieldReader { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReader +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy + Into, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&(*other).into()) + } +} +impl FieldReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} diff --git a/src/i2c0.rs b/src/i2c0.rs new file mode 100644 index 0000000..57f5c7f --- /dev/null +++ b/src/i2c0.rs @@ -0,0 +1,240 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control Register"] + pub ctrl: crate::Reg, + #[doc = "0x04 - Clock Scale divide value"] + pub clkscale: crate::Reg, + #[doc = "0x08 - Word Count value"] + pub words: crate::Reg, + #[doc = "0x0c - I2C Address value"] + pub address: crate::Reg, + #[doc = "0x10 - Data Input/Output"] + pub data: crate::Reg, + #[doc = "0x14 - Command Register"] + pub cmd: crate::Reg, + #[doc = "0x18 - I2C Controller Status Register"] + pub status: crate::Reg, + #[doc = "0x1c - Internal STATE of I2C Master Controller"] + pub state: crate::Reg, + #[doc = "0x20 - TX Count Register"] + pub txcount: crate::Reg, + #[doc = "0x24 - RX Count Register"] + pub rxcount: crate::Reg, + #[doc = "0x28 - Interrupt Enable Register"] + pub irq_enb: crate::Reg, + #[doc = "0x2c - Raw Interrupt Status Register"] + pub irq_raw: crate::Reg, + #[doc = "0x30 - Enabled Interrupt Status Register"] + pub irq_end: crate::Reg, + #[doc = "0x34 - Clear Interrupt Status Register"] + pub irq_clr: crate::Reg, + #[doc = "0x38 - Rx FIFO IRQ Trigger Level"] + pub rxfifoirqtrg: crate::Reg, + #[doc = "0x3c - Tx FIFO IRQ Trigger Level"] + pub txfifoirqtrg: crate::Reg, + #[doc = "0x40 - Clear FIFO Register"] + pub fifo_clr: crate::Reg, + #[doc = "0x44 - Timing Config Register"] + pub tmconfig: crate::Reg, + #[doc = "0x48 - Clock Low Timeout Limit Register"] + pub clktolimit: crate::Reg, + _reserved19: [u8; 0xb4], + #[doc = "0x100 - Slave Control Register"] + pub s0_ctrl: crate::Reg, + #[doc = "0x104 - Slave MaxWords Register"] + pub s0_maxwords: crate::Reg, + #[doc = "0x108 - Slave I2C Address Value"] + pub s0_address: crate::Reg, + #[doc = "0x10c - Slave I2C Address Mask value"] + pub s0_addressmask: crate::Reg, + #[doc = "0x110 - Slave Data Input/Output"] + pub s0_data: crate::Reg, + #[doc = "0x114 - Slave I2C Last Address value"] + pub s0_lastaddress: crate::Reg, + #[doc = "0x118 - Slave I2C Controller Status Register"] + pub s0_status: crate::Reg, + #[doc = "0x11c - Internal STATE of I2C Slave Controller"] + pub s0_state: crate::Reg, + #[doc = "0x120 - Slave TX Count Register"] + pub s0_txcount: crate::Reg, + #[doc = "0x124 - Slave RX Count Register"] + pub s0_rxcount: crate::Reg, + #[doc = "0x128 - Slave Interrupt Enable Register"] + pub s0_irq_enb: crate::Reg, + #[doc = "0x12c - Slave Raw Interrupt Status Register"] + pub s0_irq_raw: crate::Reg, + #[doc = "0x130 - Slave Enabled Interrupt Status Register"] + pub s0_irq_end: crate::Reg, + #[doc = "0x134 - Slave Clear Interrupt Status Register"] + pub s0_irq_clr: crate::Reg, + #[doc = "0x138 - Slave Rx FIFO IRQ Trigger Level"] + pub s0_rxfifoirqtrg: crate::Reg, + #[doc = "0x13c - Slave Tx FIFO IRQ Trigger Level"] + pub s0_txfifoirqtrg: crate::Reg, + #[doc = "0x140 - Slave Clear FIFO Register"] + pub s0_fifo_clr: crate::Reg, + #[doc = "0x144 - Slave I2C Address B Value"] + pub s0_addressb: crate::Reg, + #[doc = "0x148 - Slave I2C Address B Mask value"] + pub s0_addressmaskb: crate::Reg, + _reserved38: [u8; 0x02b0], + #[doc = "0x3fc - Peripheral ID Register"] + pub perid: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "CLKSCALE register accessor: an alias for `Reg`"] +pub type CLKSCALE = crate::Reg; +#[doc = "Clock Scale divide value"] +pub mod clkscale; +#[doc = "WORDS register accessor: an alias for `Reg`"] +pub type WORDS = crate::Reg; +#[doc = "Word Count value"] +pub mod words; +#[doc = "ADDRESS register accessor: an alias for `Reg`"] +pub type ADDRESS = crate::Reg; +#[doc = "I2C Address value"] +pub mod address; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data Input/Output"] +pub mod data; +#[doc = "CMD register accessor: an alias for `Reg`"] +pub type CMD = crate::Reg; +#[doc = "Command Register"] +pub mod cmd; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2C Controller Status Register"] +pub mod status; +#[doc = "STATE register accessor: an alias for `Reg`"] +pub type STATE = crate::Reg; +#[doc = "Internal STATE of I2C Master Controller"] +pub mod state; +#[doc = "TXCOUNT register accessor: an alias for `Reg`"] +pub type TXCOUNT = crate::Reg; +#[doc = "TX Count Register"] +pub mod txcount; +#[doc = "RXCOUNT register accessor: an alias for `Reg`"] +pub type RXCOUNT = crate::Reg; +#[doc = "RX Count Register"] +pub mod rxcount; +#[doc = "IRQ_ENB register accessor: an alias for `Reg`"] +pub type IRQ_ENB = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +#[doc = "IRQ_RAW register accessor: an alias for `Reg`"] +pub type IRQ_RAW = crate::Reg; +#[doc = "Raw Interrupt Status Register"] +pub mod irq_raw; +#[doc = "IRQ_END register accessor: an alias for `Reg`"] +pub type IRQ_END = crate::Reg; +#[doc = "Enabled Interrupt Status Register"] +pub mod irq_end; +#[doc = "IRQ_CLR register accessor: an alias for `Reg`"] +pub type IRQ_CLR = crate::Reg; +#[doc = "Clear Interrupt Status Register"] +pub mod irq_clr; +#[doc = "RXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type RXFIFOIRQTRG = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type TXFIFOIRQTRG = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR register accessor: an alias for `Reg`"] +pub type FIFO_CLR = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "TMCONFIG register accessor: an alias for `Reg`"] +pub type TMCONFIG = crate::Reg; +#[doc = "Timing Config Register"] +pub mod tmconfig; +#[doc = "CLKTOLIMIT register accessor: an alias for `Reg`"] +pub type CLKTOLIMIT = crate::Reg; +#[doc = "Clock Low Timeout Limit Register"] +pub mod clktolimit; +#[doc = "S0_CTRL register accessor: an alias for `Reg`"] +pub type S0_CTRL = crate::Reg; +#[doc = "Slave Control Register"] +pub mod s0_ctrl; +#[doc = "S0_MAXWORDS register accessor: an alias for `Reg`"] +pub type S0_MAXWORDS = crate::Reg; +#[doc = "Slave MaxWords Register"] +pub mod s0_maxwords; +#[doc = "S0_ADDRESS register accessor: an alias for `Reg`"] +pub type S0_ADDRESS = crate::Reg; +#[doc = "Slave I2C Address Value"] +pub mod s0_address; +#[doc = "S0_ADDRESSMASK register accessor: an alias for `Reg`"] +pub type S0_ADDRESSMASK = crate::Reg; +#[doc = "Slave I2C Address Mask value"] +pub mod s0_addressmask; +#[doc = "S0_DATA register accessor: an alias for `Reg`"] +pub type S0_DATA = crate::Reg; +#[doc = "Slave Data Input/Output"] +pub mod s0_data; +#[doc = "S0_LASTADDRESS register accessor: an alias for `Reg`"] +pub type S0_LASTADDRESS = crate::Reg; +#[doc = "Slave I2C Last Address value"] +pub mod s0_lastaddress; +#[doc = "S0_STATUS register accessor: an alias for `Reg`"] +pub type S0_STATUS = crate::Reg; +#[doc = "Slave I2C Controller Status Register"] +pub mod s0_status; +#[doc = "S0_STATE register accessor: an alias for `Reg`"] +pub type S0_STATE = crate::Reg; +#[doc = "Internal STATE of I2C Slave Controller"] +pub mod s0_state; +#[doc = "S0_TXCOUNT register accessor: an alias for `Reg`"] +pub type S0_TXCOUNT = crate::Reg; +#[doc = "Slave TX Count Register"] +pub mod s0_txcount; +#[doc = "S0_RXCOUNT register accessor: an alias for `Reg`"] +pub type S0_RXCOUNT = crate::Reg; +#[doc = "Slave RX Count Register"] +pub mod s0_rxcount; +#[doc = "S0_IRQ_ENB register accessor: an alias for `Reg`"] +pub type S0_IRQ_ENB = crate::Reg; +#[doc = "Slave Interrupt Enable Register"] +pub mod s0_irq_enb; +#[doc = "S0_IRQ_RAW register accessor: an alias for `Reg`"] +pub type S0_IRQ_RAW = crate::Reg; +#[doc = "Slave Raw Interrupt Status Register"] +pub mod s0_irq_raw; +#[doc = "S0_IRQ_END register accessor: an alias for `Reg`"] +pub type S0_IRQ_END = crate::Reg; +#[doc = "Slave Enabled Interrupt Status Register"] +pub mod s0_irq_end; +#[doc = "S0_IRQ_CLR register accessor: an alias for `Reg`"] +pub type S0_IRQ_CLR = crate::Reg; +#[doc = "Slave Clear Interrupt Status Register"] +pub mod s0_irq_clr; +#[doc = "S0_RXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type S0_RXFIFOIRQTRG = crate::Reg; +#[doc = "Slave Rx FIFO IRQ Trigger Level"] +pub mod s0_rxfifoirqtrg; +#[doc = "S0_TXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type S0_TXFIFOIRQTRG = crate::Reg; +#[doc = "Slave Tx FIFO IRQ Trigger Level"] +pub mod s0_txfifoirqtrg; +#[doc = "S0_FIFO_CLR register accessor: an alias for `Reg`"] +pub type S0_FIFO_CLR = crate::Reg; +#[doc = "Slave Clear FIFO Register"] +pub mod s0_fifo_clr; +#[doc = "S0_ADDRESSB register accessor: an alias for `Reg`"] +pub type S0_ADDRESSB = crate::Reg; +#[doc = "Slave I2C Address B Value"] +pub mod s0_addressb; +#[doc = "S0_ADDRESSMASKB register accessor: an alias for `Reg`"] +pub type S0_ADDRESSMASKB = crate::Reg; +#[doc = "Slave I2C Address B Mask value"] +pub mod s0_addressmaskb; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/i2c0/address.rs b/src/i2c0/address.rs new file mode 100644 index 0000000..676d23e --- /dev/null +++ b/src/i2c0/address.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ADDRESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDRESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2C Address value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [address](index.html) module"] +pub struct ADDRESS_SPEC; +impl crate::RegisterSpec for ADDRESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [address::R](R) reader structure"] +impl crate::Readable for ADDRESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [address::W](W) writer structure"] +impl crate::Writable for ADDRESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDRESS to value 0"] +impl crate::Resettable for ADDRESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/clkscale.rs b/src/i2c0/clkscale.rs new file mode 100644 index 0000000..5b221e4 --- /dev/null +++ b/src/i2c0/clkscale.rs @@ -0,0 +1,150 @@ +#[doc = "Register `CLKSCALE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKSCALE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Enable FastMode"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Enable FastMode"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7fff_ffff) | (value as u32 & 0x7fff_ffff); + self.w + } +} +#[doc = "Field `FASTMODE` reader - Enable FastMode"] +pub struct FASTMODE_R(crate::FieldReader); +impl FASTMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + FASTMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FASTMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FASTMODE` writer - Enable FastMode"] +pub struct FASTMODE_W<'a> { + w: &'a mut W, +} +impl<'a> FASTMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:30 - Enable FastMode"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x7fff_ffff) as u32) + } + #[doc = "Bit 31 - Enable FastMode"] + #[inline(always)] + pub fn fastmode(&self) -> FASTMODE_R { + FASTMODE_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:30 - Enable FastMode"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 31 - Enable FastMode"] + #[inline(always)] + pub fn fastmode(&mut self) -> FASTMODE_W { + FASTMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Scale divide value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkscale](index.html) module"] +pub struct CLKSCALE_SPEC; +impl crate::RegisterSpec for CLKSCALE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkscale::R](R) reader structure"] +impl crate::Readable for CLKSCALE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkscale::W](W) writer structure"] +impl crate::Writable for CLKSCALE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKSCALE to value 0"] +impl crate::Resettable for CLKSCALE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/clktolimit.rs b/src/i2c0/clktolimit.rs new file mode 100644 index 0000000..884cf3c --- /dev/null +++ b/src/i2c0/clktolimit.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLKTOLIMIT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKTOLIMIT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Low Timeout Limit Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clktolimit](index.html) module"] +pub struct CLKTOLIMIT_SPEC; +impl crate::RegisterSpec for CLKTOLIMIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clktolimit::R](R) reader structure"] +impl crate::Readable for CLKTOLIMIT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clktolimit::W](W) writer structure"] +impl crate::Writable for CLKTOLIMIT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKTOLIMIT to value 0"] +impl crate::Resettable for CLKTOLIMIT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/cmd.rs b/src/i2c0/cmd.rs new file mode 100644 index 0000000..4e65290 --- /dev/null +++ b/src/i2c0/cmd.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CMD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CMD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Command Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmd](index.html) module"] +pub struct CMD_SPEC; +impl crate::RegisterSpec for CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cmd::R](R) reader structure"] +impl crate::Readable for CMD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cmd::W](W) writer structure"] +impl crate::Writable for CMD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CMD to value 0"] +impl crate::Resettable for CMD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/ctrl.rs b/src/i2c0/ctrl.rs new file mode 100644 index 0000000..0c6cbb1 --- /dev/null +++ b/src/i2c0/ctrl.rs @@ -0,0 +1,489 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLKENABLED` reader - I2C CLK Enabled"] +pub struct CLKENABLED_R(crate::FieldReader); +impl CLKENABLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKENABLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKENABLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKENABLED` writer - I2C CLK Enabled"] +pub struct CLKENABLED_W<'a> { + w: &'a mut W, +} +impl<'a> CLKENABLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLED` reader - I2C Activated"] +pub struct ENABLED_R(crate::FieldReader); +impl ENABLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLED` writer - I2C Activated"] +pub struct ENABLED_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ENABLE` reader - I2C Active"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - I2C Active"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"] +pub struct TXFEMD_R(crate::FieldReader); +impl TXFEMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXFEMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXFEMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"] +pub struct TXFEMD_W<'a> { + w: &'a mut W, +} +impl<'a> TXFEMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"] +pub struct RXFFMD_R(crate::FieldReader); +impl RXFFMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFFMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFFMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"] +pub struct RXFFMD_W<'a> { + w: &'a mut W, +} +impl<'a> RXFFMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ALGFILTER` reader - Enable Input Analog Glitch Filter"] +pub struct ALGFILTER_R(crate::FieldReader); +impl ALGFILTER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ALGFILTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ALGFILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ALGFILTER` writer - Enable Input Analog Glitch Filter"] +pub struct ALGFILTER_W<'a> { + w: &'a mut W, +} +impl<'a> ALGFILTER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `DLGFILTER` reader - Enable Input Digital Glitch Filter"] +pub struct DLGFILTER_R(crate::FieldReader); +impl DLGFILTER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DLGFILTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DLGFILTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DLGFILTER` writer - Enable Input Digital Glitch Filter"] +pub struct DLGFILTER_W<'a> { + w: &'a mut W, +} +impl<'a> DLGFILTER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `LOOPBACK` reader - Enable LoopBack Mode"] +pub struct LOOPBACK_R(crate::FieldReader); +impl LOOPBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOOPBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOOPBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOOPBACK` writer - Enable LoopBack Mode"] +pub struct LOOPBACK_W<'a> { + w: &'a mut W, +} +impl<'a> LOOPBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TMCONFIGENB` reader - Enable Timing Config Register"] +pub struct TMCONFIGENB_R(crate::FieldReader); +impl TMCONFIGENB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TMCONFIGENB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TMCONFIGENB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TMCONFIGENB` writer - Enable Timing Config Register"] +pub struct TMCONFIGENB_W<'a> { + w: &'a mut W, +} +impl<'a> TMCONFIGENB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - I2C CLK Enabled"] + #[inline(always)] + pub fn clkenabled(&self) -> CLKENABLED_R { + CLKENABLED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&self) -> TXFEMD_R { + TXFEMD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&self) -> RXFFMD_R { + RXFFMD_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Enable Input Analog Glitch Filter"] + #[inline(always)] + pub fn algfilter(&self) -> ALGFILTER_R { + ALGFILTER_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Enable Input Digital Glitch Filter"] + #[inline(always)] + pub fn dlgfilter(&self) -> DLGFILTER_R { + DLGFILTER_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - Enable LoopBack Mode"] + #[inline(always)] + pub fn loopback(&self) -> LOOPBACK_R { + LOOPBACK_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Enable Timing Config Register"] + #[inline(always)] + pub fn tmconfigenb(&self) -> TMCONFIGENB_R { + TMCONFIGENB_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C CLK Enabled"] + #[inline(always)] + pub fn clkenabled(&mut self) -> CLKENABLED_W { + CLKENABLED_W { w: self } + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&mut self) -> ENABLED_W { + ENABLED_W { w: self } + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&mut self) -> TXFEMD_W { + TXFEMD_W { w: self } + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&mut self) -> RXFFMD_W { + RXFFMD_W { w: self } + } + #[doc = "Bit 5 - Enable Input Analog Glitch Filter"] + #[inline(always)] + pub fn algfilter(&mut self) -> ALGFILTER_W { + ALGFILTER_W { w: self } + } + #[doc = "Bit 6 - Enable Input Digital Glitch Filter"] + #[inline(always)] + pub fn dlgfilter(&mut self) -> DLGFILTER_W { + DLGFILTER_W { w: self } + } + #[doc = "Bit 8 - Enable LoopBack Mode"] + #[inline(always)] + pub fn loopback(&mut self) -> LOOPBACK_W { + LOOPBACK_W { w: self } + } + #[doc = "Bit 9 - Enable Timing Config Register"] + #[inline(always)] + pub fn tmconfigenb(&mut self) -> TMCONFIGENB_W { + TMCONFIGENB_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/data.rs b/src/i2c0/data.rs new file mode 100644 index 0000000..31777b9 --- /dev/null +++ b/src/i2c0/data.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Input/Output\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/fifo_clr.rs b/src/i2c0/fifo_clr.rs new file mode 100644 index 0000000..3d95fdd --- /dev/null +++ b/src/i2c0/fifo_clr.rs @@ -0,0 +1,99 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub struct RXFIFO_W<'a> { + w: &'a mut W, +} +impl<'a> RXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub struct TXFIFO_W<'a> { + w: &'a mut W, +} +impl<'a> TXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RXFIFO_W { + RXFIFO_W { w: self } + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TXFIFO_W { + TXFIFO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear FIFO Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_clr](index.html) module"] +pub struct FIFO_CLR_SPEC; +impl crate::RegisterSpec for FIFO_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [fifo_clr::W](W) writer structure"] +impl crate::Writable for FIFO_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FIFO_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/irq_clr.rs b/src/i2c0/irq_clr.rs new file mode 100644 index 0000000..fad92d0 --- /dev/null +++ b/src/i2c0/irq_clr.rs @@ -0,0 +1,423 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `I2CIDLE` writer - I2C Bus is Idle"] +pub struct I2CIDLE_W<'a> { + w: &'a mut W, +} +impl<'a> I2CIDLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub struct IDLE_W<'a> { + w: &'a mut W, +} +impl<'a> IDLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub struct WAITING_W<'a> { + w: &'a mut W, +} +impl<'a> WAITING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STALLED` writer - Controller is Stalled"] +pub struct STALLED_W<'a> { + w: &'a mut W, +} +impl<'a> STALLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"] +pub struct NACKADDR_W<'a> { + w: &'a mut W, +} +impl<'a> NACKADDR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub struct NACKDATA_W<'a> { + w: &'a mut W, +} +impl<'a> NACKDATA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKLOTO` writer - I2C Clock Low Timeout"] +pub struct CLKLOTO_W<'a> { + w: &'a mut W, +} +impl<'a> CLKLOTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TXOVERFLOW` writer - TX FIFO Overflowed"] +pub struct TXOVERFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> TXOVERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub struct RXOVERFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> RXOVERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub struct TXREADY_W<'a> { + w: &'a mut W, +} +impl<'a> TXREADY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub struct RXREADY_W<'a> { + w: &'a mut W, +} +impl<'a> RXREADY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub struct TXEMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> TXEMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub struct RXFULL_W<'a> { + w: &'a mut W, +} +impl<'a> RXFULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl W { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&mut self) -> I2CIDLE_W { + I2CIDLE_W { w: self } + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W { w: self } + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WAITING_W { + WAITING_W { w: self } + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&mut self) -> STALLED_W { + STALLED_W { w: self } + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&mut self) -> NACKADDR_W { + NACKADDR_W { w: self } + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NACKDATA_W { + NACKDATA_W { w: self } + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&mut self) -> CLKLOTO_W { + CLKLOTO_W { w: self } + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&mut self) -> TXOVERFLOW_W { + TXOVERFLOW_W { w: self } + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&mut self) -> RXOVERFLOW_W { + RXOVERFLOW_W { w: self } + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&mut self) -> TXREADY_W { + TXREADY_W { w: self } + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&mut self) -> RXREADY_W { + RXREADY_W { w: self } + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TXEMPTY_W { + TXEMPTY_W { w: self } + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RXFULL_W { + RXFULL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear Interrupt Status Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"] +pub struct IRQ_CLR_SPEC; +impl crate::RegisterSpec for IRQ_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"] +impl crate::Writable for IRQ_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IRQ_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/irq_enb.rs b/src/i2c0/irq_enb.rs new file mode 100644 index 0000000..eab46a4 --- /dev/null +++ b/src/i2c0/irq_enb.rs @@ -0,0 +1,724 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_ENB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"] +pub struct I2CIDLE_R(crate::FieldReader); +impl I2CIDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2CIDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2CIDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2CIDLE` writer - I2C Bus is Idle"] +pub struct I2CIDLE_W<'a> { + w: &'a mut W, +} +impl<'a> I2CIDLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub struct IDLE_W<'a> { + w: &'a mut W, +} +impl<'a> IDLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub struct WAITING_R(crate::FieldReader); +impl WAITING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub struct WAITING_W<'a> { + w: &'a mut W, +} +impl<'a> WAITING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub struct STALLED_R(crate::FieldReader); +impl STALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLED` writer - Controller is Stalled"] +pub struct STALLED_W<'a> { + w: &'a mut W, +} +impl<'a> STALLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub struct NACKADDR_R(crate::FieldReader); +impl NACKADDR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"] +pub struct NACKADDR_W<'a> { + w: &'a mut W, +} +impl<'a> NACKADDR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub struct NACKDATA_R(crate::FieldReader); +impl NACKDATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKDATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKDATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub struct NACKDATA_W<'a> { + w: &'a mut W, +} +impl<'a> NACKDATA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"] +pub struct CLKLOTO_R(crate::FieldReader); +impl CLKLOTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKLOTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKLOTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKLOTO` writer - I2C Clock Low Timeout"] +pub struct CLKLOTO_W<'a> { + w: &'a mut W, +} +impl<'a> CLKLOTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"] +pub struct TXOVERFLOW_R(crate::FieldReader); +impl TXOVERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXOVERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXOVERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXOVERFLOW` writer - TX FIFO Overflowed"] +pub struct TXOVERFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> TXOVERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub struct RXOVERFLOW_R(crate::FieldReader); +impl RXOVERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOVERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOVERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub struct RXOVERFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> RXOVERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub struct TXREADY_R(crate::FieldReader); +impl TXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub struct TXREADY_W<'a> { + w: &'a mut W, +} +impl<'a> TXREADY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub struct RXREADY_R(crate::FieldReader); +impl RXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub struct RXREADY_W<'a> { + w: &'a mut W, +} +impl<'a> RXREADY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub struct TXEMPTY_R(crate::FieldReader); +impl TXEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub struct TXEMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> TXEMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub struct RXFULL_R(crate::FieldReader); +impl RXFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub struct RXFULL_W<'a> { + w: &'a mut W, +} +impl<'a> RXFULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&self) -> I2CIDLE_R { + I2CIDLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> STALLED_R { + STALLED_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NACKADDR_R { + NACKADDR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NACKDATA_R { + NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&self) -> CLKLOTO_R { + CLKLOTO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&self) -> TXOVERFLOW_R { + TXOVERFLOW_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RXOVERFLOW_R { + RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TXREADY_R { + TXREADY_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RXREADY_R { + RXREADY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&mut self) -> I2CIDLE_W { + I2CIDLE_W { w: self } + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W { w: self } + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WAITING_W { + WAITING_W { w: self } + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&mut self) -> STALLED_W { + STALLED_W { w: self } + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&mut self) -> NACKADDR_W { + NACKADDR_W { w: self } + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NACKDATA_W { + NACKDATA_W { w: self } + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&mut self) -> CLKLOTO_W { + CLKLOTO_W { w: self } + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&mut self) -> TXOVERFLOW_W { + TXOVERFLOW_W { w: self } + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&mut self) -> RXOVERFLOW_W { + RXOVERFLOW_W { w: self } + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&mut self) -> TXREADY_W { + TXREADY_W { w: self } + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&mut self) -> RXREADY_W { + RXREADY_W { w: self } + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TXEMPTY_W { + TXEMPTY_W { w: self } + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RXFULL_W { + RXFULL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"] +pub struct IRQ_ENB_SPEC; +impl crate::RegisterSpec for IRQ_ENB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_enb::R](R) reader structure"] +impl crate::Readable for IRQ_ENB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"] +impl crate::Writable for IRQ_ENB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IRQ_ENB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/irq_end.rs b/src/i2c0/irq_end.rs new file mode 100644 index 0000000..6a0ac28 --- /dev/null +++ b/src/i2c0/irq_end.rs @@ -0,0 +1,313 @@ +#[doc = "Register `IRQ_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"] +pub struct I2CIDLE_R(crate::FieldReader); +impl I2CIDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2CIDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2CIDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub struct WAITING_R(crate::FieldReader); +impl WAITING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub struct STALLED_R(crate::FieldReader); +impl STALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub struct NACKADDR_R(crate::FieldReader); +impl NACKADDR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub struct NACKDATA_R(crate::FieldReader); +impl NACKDATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKDATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKDATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"] +pub struct CLKLOTO_R(crate::FieldReader); +impl CLKLOTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKLOTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKLOTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"] +pub struct TXOVERFLOW_R(crate::FieldReader); +impl TXOVERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXOVERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXOVERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub struct RXOVERFLOW_R(crate::FieldReader); +impl RXOVERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOVERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOVERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub struct TXREADY_R(crate::FieldReader); +impl TXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub struct RXREADY_R(crate::FieldReader); +impl RXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub struct TXEMPTY_R(crate::FieldReader); +impl TXEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub struct RXFULL_R(crate::FieldReader); +impl RXFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&self) -> I2CIDLE_R { + I2CIDLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> STALLED_R { + STALLED_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NACKADDR_R { + NACKADDR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NACKDATA_R { + NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&self) -> CLKLOTO_R { + CLKLOTO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&self) -> TXOVERFLOW_R { + TXOVERFLOW_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RXOVERFLOW_R { + RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TXREADY_R { + TXREADY_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RXREADY_R { + RXREADY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "Enabled Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"] +pub struct IRQ_END_SPEC; +impl crate::RegisterSpec for IRQ_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_end::R](R) reader structure"] +impl crate::Readable for IRQ_END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IRQ_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/irq_raw.rs b/src/i2c0/irq_raw.rs new file mode 100644 index 0000000..e164ea0 --- /dev/null +++ b/src/i2c0/irq_raw.rs @@ -0,0 +1,313 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"] +pub struct I2CIDLE_R(crate::FieldReader); +impl I2CIDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2CIDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2CIDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub struct WAITING_R(crate::FieldReader); +impl WAITING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub struct STALLED_R(crate::FieldReader); +impl STALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub struct NACKADDR_R(crate::FieldReader); +impl NACKADDR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub struct NACKDATA_R(crate::FieldReader); +impl NACKDATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKDATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKDATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"] +pub struct CLKLOTO_R(crate::FieldReader); +impl CLKLOTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKLOTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKLOTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"] +pub struct TXOVERFLOW_R(crate::FieldReader); +impl TXOVERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXOVERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXOVERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub struct RXOVERFLOW_R(crate::FieldReader); +impl RXOVERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOVERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOVERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub struct TXREADY_R(crate::FieldReader); +impl TXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub struct RXREADY_R(crate::FieldReader); +impl RXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub struct TXEMPTY_R(crate::FieldReader); +impl TXEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub struct RXFULL_R(crate::FieldReader); +impl RXFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&self) -> I2CIDLE_R { + I2CIDLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> STALLED_R { + STALLED_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NACKADDR_R { + NACKADDR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NACKDATA_R { + NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&self) -> CLKLOTO_R { + CLKLOTO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&self) -> TXOVERFLOW_R { + TXOVERFLOW_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RXOVERFLOW_R { + RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TXREADY_R { + TXREADY_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RXREADY_R { + RXREADY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"] +pub struct IRQ_RAW_SPEC; +impl crate::RegisterSpec for IRQ_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_raw::R](R) reader structure"] +impl crate::Readable for IRQ_RAW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_RAW to value 0"] +impl crate::Resettable for IRQ_RAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/perid.rs b/src/i2c0/perid.rs new file mode 100644 index 0000000..7c969be --- /dev/null +++ b/src/i2c0/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0214_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0214_07e9 + } +} diff --git a/src/i2c0/rxcount.rs b/src/i2c0/rxcount.rs new file mode 100644 index 0000000..7feb8bc --- /dev/null +++ b/src/i2c0/rxcount.rs @@ -0,0 +1,31 @@ +#[doc = "Register `RXCOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "RX Count Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxcount](index.html) module"] +pub struct RXCOUNT_SPEC; +impl crate::RegisterSpec for RXCOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxcount::R](R) reader structure"] +impl crate::Readable for RXCOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXCOUNT to value 0"] +impl crate::Resettable for RXCOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/rxfifoirqtrg.rs b/src/i2c0/rxfifoirqtrg.rs new file mode 100644 index 0000000..fb4d239 --- /dev/null +++ b/src/i2c0/rxfifoirqtrg.rs @@ -0,0 +1,64 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifoirqtrg](index.html) module"] +pub struct RXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for RXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxfifoirqtrg::R](R) reader structure"] +impl crate::Readable for RXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxfifoirqtrg::W](W) writer structure"] +impl crate::Writable for RXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_address.rs b/src/i2c0/s0_address.rs new file mode 100644 index 0000000..87e9f74 --- /dev/null +++ b/src/i2c0/s0_address.rs @@ -0,0 +1,197 @@ +#[doc = "Register `S0_ADDRESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_ADDRESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `A10MODE` reader - Enable 10b address mode"] +pub struct A10MODE_R(crate::FieldReader); +impl A10MODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + A10MODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for A10MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `A10MODE` writer - Enable 10b address mode"] +pub struct A10MODE_W<'a> { + w: &'a mut W, +} +impl<'a> A10MODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `ADDRESS` reader - Address value"] +pub struct ADDRESS_R(crate::FieldReader); +impl ADDRESS_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRESS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRESS` writer - Address value"] +pub struct ADDRESS_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `RW` reader - Read/Write value"] +pub struct RW_R(crate::FieldReader); +impl RW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RW` writer - Read/Write value"] +pub struct RW_W<'a> { + w: &'a mut W, +} +impl<'a> RW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 15 - Enable 10b address mode"] + #[inline(always)] + pub fn a10mode(&self) -> A10MODE_R { + A10MODE_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 0 - Read/Write value"] + #[inline(always)] + pub fn rw(&self) -> RW_R { + RW_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 15 - Enable 10b address mode"] + #[inline(always)] + pub fn a10mode(&mut self) -> A10MODE_W { + A10MODE_W { w: self } + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W { w: self } + } + #[doc = "Bit 0 - Read/Write value"] + #[inline(always)] + pub fn rw(&mut self) -> RW_W { + RW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave I2C Address Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_address](index.html) module"] +pub struct S0_ADDRESS_SPEC; +impl crate::RegisterSpec for S0_ADDRESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_address::R](R) reader structure"] +impl crate::Readable for S0_ADDRESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_address::W](W) writer structure"] +impl crate::Writable for S0_ADDRESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_ADDRESS to value 0"] +impl crate::Resettable for S0_ADDRESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_addressb.rs b/src/i2c0/s0_addressb.rs new file mode 100644 index 0000000..5d74434 --- /dev/null +++ b/src/i2c0/s0_addressb.rs @@ -0,0 +1,197 @@ +#[doc = "Register `S0_ADDRESSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_ADDRESSB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RW` reader - Read write value"] +pub struct RW_R(crate::FieldReader); +impl RW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RW` writer - Read write value"] +pub struct RW_W<'a> { + w: &'a mut W, +} +impl<'a> RW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ADDRESS` reader - Address value"] +pub struct ADDRESS_R(crate::FieldReader); +impl ADDRESS_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRESS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRESS` writer - Address value"] +pub struct ADDRESS_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRESS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `ADDRESSBEN` reader - Enable Address B"] +pub struct ADDRESSBEN_R(crate::FieldReader); +impl ADDRESSBEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADDRESSBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRESSBEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRESSBEN` writer - Enable Address B"] +pub struct ADDRESSBEN_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRESSBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Read write value"] + #[inline(always)] + pub fn rw(&self) -> RW_R { + RW_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Enable Address B"] + #[inline(always)] + pub fn addressben(&self) -> ADDRESSBEN_R { + ADDRESSBEN_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Read write value"] + #[inline(always)] + pub fn rw(&mut self) -> RW_W { + RW_W { w: self } + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W { w: self } + } + #[doc = "Bit 15 - Enable Address B"] + #[inline(always)] + pub fn addressben(&mut self) -> ADDRESSBEN_W { + ADDRESSBEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave I2C Address B Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_addressb](index.html) module"] +pub struct S0_ADDRESSB_SPEC; +impl crate::RegisterSpec for S0_ADDRESSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_addressb::R](R) reader structure"] +impl crate::Readable for S0_ADDRESSB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_addressb::W](W) writer structure"] +impl crate::Writable for S0_ADDRESSB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_ADDRESSB to value 0"] +impl crate::Resettable for S0_ADDRESSB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_addressmask.rs b/src/i2c0/s0_addressmask.rs new file mode 100644 index 0000000..038fd85 --- /dev/null +++ b/src/i2c0/s0_addressmask.rs @@ -0,0 +1,150 @@ +#[doc = "Register `S0_ADDRESSMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_ADDRESSMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Address mask value"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Address mask value"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +#[doc = "Field `RWMASK` reader - Read/Write mask"] +pub struct RWMASK_R(crate::FieldReader); +impl RWMASK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RWMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWMASK` writer - Read/Write mask"] +pub struct RWMASK_W<'a> { + w: &'a mut W, +} +impl<'a> RWMASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 0 - Read/Write mask"] + #[inline(always)] + pub fn rwmask(&self) -> RWMASK_R { + RWMASK_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bit 0 - Read/Write mask"] + #[inline(always)] + pub fn rwmask(&mut self) -> RWMASK_W { + RWMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave I2C Address Mask value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_addressmask](index.html) module"] +pub struct S0_ADDRESSMASK_SPEC; +impl crate::RegisterSpec for S0_ADDRESSMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_addressmask::R](R) reader structure"] +impl crate::Readable for S0_ADDRESSMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_addressmask::W](W) writer structure"] +impl crate::Writable for S0_ADDRESSMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"] +impl crate::Resettable for S0_ADDRESSMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_addressmaskb.rs b/src/i2c0/s0_addressmaskb.rs new file mode 100644 index 0000000..b3af7b4 --- /dev/null +++ b/src/i2c0/s0_addressmaskb.rs @@ -0,0 +1,150 @@ +#[doc = "Register `S0_ADDRESSMASKB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_ADDRESSMASKB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RWMASK` reader - Read write mask"] +pub struct RWMASK_R(crate::FieldReader); +impl RWMASK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RWMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RWMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RWMASK` writer - Read write mask"] +pub struct RWMASK_W<'a> { + w: &'a mut W, +} +impl<'a> RWMASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `MASK` reader - Address mask value"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Address mask value"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03ff << 1)) | ((value as u32 & 0x03ff) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Read write mask"] + #[inline(always)] + pub fn rwmask(&self) -> RWMASK_R { + RWMASK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new(((self.bits >> 1) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Read write mask"] + #[inline(always)] + pub fn rwmask(&mut self) -> RWMASK_W { + RWMASK_W { w: self } + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave I2C Address B Mask value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_addressmaskb](index.html) module"] +pub struct S0_ADDRESSMASKB_SPEC; +impl crate::RegisterSpec for S0_ADDRESSMASKB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_addressmaskb::R](R) reader structure"] +impl crate::Readable for S0_ADDRESSMASKB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_addressmaskb::W](W) writer structure"] +impl crate::Writable for S0_ADDRESSMASKB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0x07fe"] +impl crate::Resettable for S0_ADDRESSMASKB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07fe + } +} diff --git a/src/i2c0/s0_ctrl.rs b/src/i2c0/s0_ctrl.rs new file mode 100644 index 0000000..9cb3965 --- /dev/null +++ b/src/i2c0/s0_ctrl.rs @@ -0,0 +1,301 @@ +#[doc = "Register `S0_CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLKENABLED` reader - I2C Enabled"] +pub struct CLKENABLED_R(crate::FieldReader); +impl CLKENABLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKENABLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKENABLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKENABLED` writer - I2C Enabled"] +pub struct CLKENABLED_W<'a> { + w: &'a mut W, +} +impl<'a> CLKENABLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLED` reader - I2C Activated"] +pub struct ENABLED_R(crate::FieldReader); +impl ENABLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLED` writer - I2C Activated"] +pub struct ENABLED_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ENABLE` reader - I2C Active"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - I2C Active"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"] +pub struct TXFEMD_R(crate::FieldReader); +impl TXFEMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXFEMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXFEMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"] +pub struct TXFEMD_W<'a> { + w: &'a mut W, +} +impl<'a> TXFEMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"] +pub struct RXFFMD_R(crate::FieldReader); +impl RXFFMD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFFMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFFMD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"] +pub struct RXFFMD_W<'a> { + w: &'a mut W, +} +impl<'a> RXFFMD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - I2C Enabled"] + #[inline(always)] + pub fn clkenabled(&self) -> CLKENABLED_R { + CLKENABLED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&self) -> TXFEMD_R { + TXFEMD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&self) -> RXFFMD_R { + RXFFMD_R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C Enabled"] + #[inline(always)] + pub fn clkenabled(&mut self) -> CLKENABLED_W { + CLKENABLED_W { w: self } + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&mut self) -> ENABLED_W { + ENABLED_W { w: self } + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&mut self) -> TXFEMD_W { + TXFEMD_W { w: self } + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&mut self) -> RXFFMD_W { + RXFFMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_ctrl](index.html) module"] +pub struct S0_CTRL_SPEC; +impl crate::RegisterSpec for S0_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_ctrl::R](R) reader structure"] +impl crate::Readable for S0_CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_ctrl::W](W) writer structure"] +impl crate::Writable for S0_CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_CTRL to value 0"] +impl crate::Resettable for S0_CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_data.rs b/src/i2c0/s0_data.rs new file mode 100644 index 0000000..d8229cc --- /dev/null +++ b/src/i2c0/s0_data.rs @@ -0,0 +1,103 @@ +#[doc = "Register `S0_DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - I2C data value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - I2C data value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - I2C data value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - I2C data value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Data Input/Output\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_data](index.html) module"] +pub struct S0_DATA_SPEC; +impl crate::RegisterSpec for S0_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_data::R](R) reader structure"] +impl crate::Readable for S0_DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_data::W](W) writer structure"] +impl crate::Writable for S0_DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_DATA to value 0"] +impl crate::Resettable for S0_DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_fifo_clr.rs b/src/i2c0/s0_fifo_clr.rs new file mode 100644 index 0000000..f9cc956 --- /dev/null +++ b/src/i2c0/s0_fifo_clr.rs @@ -0,0 +1,99 @@ +#[doc = "Register `S0_FIFO_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub struct RXFIFO_W<'a> { + w: &'a mut W, +} +impl<'a> RXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub struct TXFIFO_W<'a> { + w: &'a mut W, +} +impl<'a> TXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RXFIFO_W { + RXFIFO_W { w: self } + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TXFIFO_W { + TXFIFO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Clear FIFO Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_fifo_clr](index.html) module"] +pub struct S0_FIFO_CLR_SPEC; +impl crate::RegisterSpec for S0_FIFO_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [s0_fifo_clr::W](W) writer structure"] +impl crate::Writable for S0_FIFO_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_FIFO_CLR to value 0"] +impl crate::Resettable for S0_FIFO_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_irq_clr.rs b/src/i2c0/s0_irq_clr.rs new file mode 100644 index 0000000..0024cd9 --- /dev/null +++ b/src/i2c0/s0_irq_clr.rs @@ -0,0 +1,477 @@ +#[doc = "Register `S0_IRQ_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"] +pub struct COMPLETED_W<'a> { + w: &'a mut W, +} +impl<'a> COMPLETED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub struct IDLE_W<'a> { + w: &'a mut W, +} +impl<'a> IDLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub struct WAITING_W<'a> { + w: &'a mut W, +} +impl<'a> WAITING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"] +pub struct TXSTALLED_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTALLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"] +pub struct RXSTALLED_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTALLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"] +pub struct ADDRESSMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRESSMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub struct NACKDATA_W<'a> { + w: &'a mut W, +} +impl<'a> NACKDATA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"] +pub struct RXDATAFIRST_W<'a> { + w: &'a mut W, +} +impl<'a> RXDATAFIRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `I2C_START` writer - I2C Start Condition"] +pub struct I2C_START_W<'a> { + w: &'a mut W, +} +impl<'a> I2C_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"] +pub struct I2C_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> I2C_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"] +pub struct TXUNDERFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> TXUNDERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub struct RXOVERFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> RXOVERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub struct TXREADY_W<'a> { + w: &'a mut W, +} +impl<'a> TXREADY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub struct RXREADY_W<'a> { + w: &'a mut W, +} +impl<'a> RXREADY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub struct TXEMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> TXEMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub struct RXFULL_W<'a> { + w: &'a mut W, +} +impl<'a> RXFULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl W { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&mut self) -> COMPLETED_W { + COMPLETED_W { w: self } + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W { w: self } + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WAITING_W { + WAITING_W { w: self } + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&mut self) -> TXSTALLED_W { + TXSTALLED_W { w: self } + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&mut self) -> RXSTALLED_W { + RXSTALLED_W { w: self } + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&mut self) -> ADDRESSMATCH_W { + ADDRESSMATCH_W { w: self } + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NACKDATA_W { + NACKDATA_W { w: self } + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&mut self) -> RXDATAFIRST_W { + RXDATAFIRST_W { w: self } + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&mut self) -> I2C_START_W { + I2C_START_W { w: self } + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&mut self) -> I2C_STOP_W { + I2C_STOP_W { w: self } + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&mut self) -> TXUNDERFLOW_W { + TXUNDERFLOW_W { w: self } + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&mut self) -> RXOVERFLOW_W { + RXOVERFLOW_W { w: self } + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&mut self) -> TXREADY_W { + TXREADY_W { w: self } + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&mut self) -> RXREADY_W { + RXREADY_W { w: self } + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TXEMPTY_W { + TXEMPTY_W { w: self } + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RXFULL_W { + RXFULL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Clear Interrupt Status Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_irq_clr](index.html) module"] +pub struct S0_IRQ_CLR_SPEC; +impl crate::RegisterSpec for S0_IRQ_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [s0_irq_clr::W](W) writer structure"] +impl crate::Writable for S0_IRQ_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_IRQ_CLR to value 0"] +impl crate::Resettable for S0_IRQ_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_irq_enb.rs b/src/i2c0/s0_irq_enb.rs new file mode 100644 index 0000000..bd93ee9 --- /dev/null +++ b/src/i2c0/s0_irq_enb.rs @@ -0,0 +1,818 @@ +#[doc = "Register `S0_IRQ_ENB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_IRQ_ENB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub struct COMPLETED_R(crate::FieldReader); +impl COMPLETED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPLETED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPLETED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"] +pub struct COMPLETED_W<'a> { + w: &'a mut W, +} +impl<'a> COMPLETED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub struct IDLE_W<'a> { + w: &'a mut W, +} +impl<'a> IDLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub struct WAITING_R(crate::FieldReader); +impl WAITING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub struct WAITING_W<'a> { + w: &'a mut W, +} +impl<'a> WAITING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub struct TXSTALLED_R(crate::FieldReader); +impl TXSTALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"] +pub struct TXSTALLED_W<'a> { + w: &'a mut W, +} +impl<'a> TXSTALLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub struct RXSTALLED_R(crate::FieldReader); +impl RXSTALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"] +pub struct RXSTALLED_W<'a> { + w: &'a mut W, +} +impl<'a> RXSTALLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub struct ADDRESSMATCH_R(crate::FieldReader); +impl ADDRESSMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADDRESSMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRESSMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"] +pub struct ADDRESSMATCH_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRESSMATCH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub struct NACKDATA_R(crate::FieldReader); +impl NACKDATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKDATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKDATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub struct NACKDATA_W<'a> { + w: &'a mut W, +} +impl<'a> NACKDATA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub struct RXDATAFIRST_R(crate::FieldReader); +impl RXDATAFIRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXDATAFIRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXDATAFIRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"] +pub struct RXDATAFIRST_W<'a> { + w: &'a mut W, +} +impl<'a> RXDATAFIRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `I2C_START` reader - I2C Start Condition"] +pub struct I2C_START_R(crate::FieldReader); +impl I2C_START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C_START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C_START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C_START` writer - I2C Start Condition"] +pub struct I2C_START_W<'a> { + w: &'a mut W, +} +impl<'a> I2C_START_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"] +pub struct I2C_STOP_R(crate::FieldReader); +impl I2C_STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C_STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C_STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"] +pub struct I2C_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> I2C_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"] +pub struct TXUNDERFLOW_R(crate::FieldReader); +impl TXUNDERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUNDERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUNDERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"] +pub struct TXUNDERFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> TXUNDERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub struct RXOVERFLOW_R(crate::FieldReader); +impl RXOVERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOVERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOVERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub struct RXOVERFLOW_W<'a> { + w: &'a mut W, +} +impl<'a> RXOVERFLOW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub struct TXREADY_R(crate::FieldReader); +impl TXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub struct TXREADY_W<'a> { + w: &'a mut W, +} +impl<'a> TXREADY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub struct RXREADY_R(crate::FieldReader); +impl RXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub struct RXREADY_W<'a> { + w: &'a mut W, +} +impl<'a> RXREADY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub struct TXEMPTY_R(crate::FieldReader); +impl TXEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub struct TXEMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> TXEMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub struct RXFULL_R(crate::FieldReader); +impl RXFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub struct RXFULL_W<'a> { + w: &'a mut W, +} +impl<'a> RXFULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> COMPLETED_R { + COMPLETED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TXSTALLED_R { + TXSTALLED_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RXSTALLED_R { + RXSTALLED_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> ADDRESSMATCH_R { + ADDRESSMATCH_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NACKDATA_R { + NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RXDATAFIRST_R { + RXDATAFIRST_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&self) -> I2C_START_R { + I2C_START_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&self) -> I2C_STOP_R { + I2C_STOP_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&self) -> TXUNDERFLOW_R { + TXUNDERFLOW_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RXOVERFLOW_R { + RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TXREADY_R { + TXREADY_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RXREADY_R { + RXREADY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&mut self) -> COMPLETED_W { + COMPLETED_W { w: self } + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W { w: self } + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WAITING_W { + WAITING_W { w: self } + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&mut self) -> TXSTALLED_W { + TXSTALLED_W { w: self } + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&mut self) -> RXSTALLED_W { + RXSTALLED_W { w: self } + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&mut self) -> ADDRESSMATCH_W { + ADDRESSMATCH_W { w: self } + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NACKDATA_W { + NACKDATA_W { w: self } + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&mut self) -> RXDATAFIRST_W { + RXDATAFIRST_W { w: self } + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&mut self) -> I2C_START_W { + I2C_START_W { w: self } + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&mut self) -> I2C_STOP_W { + I2C_STOP_W { w: self } + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&mut self) -> TXUNDERFLOW_W { + TXUNDERFLOW_W { w: self } + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&mut self) -> RXOVERFLOW_W { + RXOVERFLOW_W { w: self } + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&mut self) -> TXREADY_W { + TXREADY_W { w: self } + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&mut self) -> RXREADY_W { + RXREADY_W { w: self } + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TXEMPTY_W { + TXEMPTY_W { w: self } + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RXFULL_W { + RXFULL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_irq_enb](index.html) module"] +pub struct S0_IRQ_ENB_SPEC; +impl crate::RegisterSpec for S0_IRQ_ENB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_irq_enb::R](R) reader structure"] +impl crate::Readable for S0_IRQ_ENB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_irq_enb::W](W) writer structure"] +impl crate::Writable for S0_IRQ_ENB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_IRQ_ENB to value 0"] +impl crate::Resettable for S0_IRQ_ENB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_irq_end.rs b/src/i2c0/s0_irq_end.rs new file mode 100644 index 0000000..56d29fe --- /dev/null +++ b/src/i2c0/s0_irq_end.rs @@ -0,0 +1,353 @@ +#[doc = "Register `S0_IRQ_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub struct COMPLETED_R(crate::FieldReader); +impl COMPLETED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPLETED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPLETED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub struct WAITING_R(crate::FieldReader); +impl WAITING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub struct TXSTALLED_R(crate::FieldReader); +impl TXSTALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub struct RXSTALLED_R(crate::FieldReader); +impl RXSTALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub struct ADDRESSMATCH_R(crate::FieldReader); +impl ADDRESSMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADDRESSMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRESSMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub struct NACKDATA_R(crate::FieldReader); +impl NACKDATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKDATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKDATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub struct RXDATAFIRST_R(crate::FieldReader); +impl RXDATAFIRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXDATAFIRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXDATAFIRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C_START` reader - I2C Start Condition"] +pub struct I2C_START_R(crate::FieldReader); +impl I2C_START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C_START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C_START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"] +pub struct I2C_STOP_R(crate::FieldReader); +impl I2C_STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C_STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C_STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"] +pub struct TXUNDERFLOW_R(crate::FieldReader); +impl TXUNDERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUNDERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUNDERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub struct RXOVERFLOW_R(crate::FieldReader); +impl RXOVERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOVERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOVERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub struct TXREADY_R(crate::FieldReader); +impl TXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub struct RXREADY_R(crate::FieldReader); +impl RXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub struct TXEMPTY_R(crate::FieldReader); +impl TXEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub struct RXFULL_R(crate::FieldReader); +impl RXFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> COMPLETED_R { + COMPLETED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TXSTALLED_R { + TXSTALLED_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RXSTALLED_R { + RXSTALLED_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> ADDRESSMATCH_R { + ADDRESSMATCH_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NACKDATA_R { + NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RXDATAFIRST_R { + RXDATAFIRST_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&self) -> I2C_START_R { + I2C_START_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&self) -> I2C_STOP_R { + I2C_STOP_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&self) -> TXUNDERFLOW_R { + TXUNDERFLOW_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RXOVERFLOW_R { + RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TXREADY_R { + TXREADY_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RXREADY_R { + RXREADY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "Slave Enabled Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_irq_end](index.html) module"] +pub struct S0_IRQ_END_SPEC; +impl crate::RegisterSpec for S0_IRQ_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_irq_end::R](R) reader structure"] +impl crate::Readable for S0_IRQ_END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets S0_IRQ_END to value 0"] +impl crate::Resettable for S0_IRQ_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_irq_raw.rs b/src/i2c0/s0_irq_raw.rs new file mode 100644 index 0000000..601b3b1 --- /dev/null +++ b/src/i2c0/s0_irq_raw.rs @@ -0,0 +1,353 @@ +#[doc = "Register `S0_IRQ_RAW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub struct COMPLETED_R(crate::FieldReader); +impl COMPLETED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPLETED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPLETED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub struct WAITING_R(crate::FieldReader); +impl WAITING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub struct TXSTALLED_R(crate::FieldReader); +impl TXSTALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub struct RXSTALLED_R(crate::FieldReader); +impl RXSTALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub struct ADDRESSMATCH_R(crate::FieldReader); +impl ADDRESSMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADDRESSMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRESSMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub struct NACKDATA_R(crate::FieldReader); +impl NACKDATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKDATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKDATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub struct RXDATAFIRST_R(crate::FieldReader); +impl RXDATAFIRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXDATAFIRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXDATAFIRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C_START` reader - I2C Start Condition"] +pub struct I2C_START_R(crate::FieldReader); +impl I2C_START_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C_START_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C_START_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"] +pub struct I2C_STOP_R(crate::FieldReader); +impl I2C_STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C_STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C_STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"] +pub struct TXUNDERFLOW_R(crate::FieldReader); +impl TXUNDERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXUNDERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXUNDERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub struct RXOVERFLOW_R(crate::FieldReader); +impl RXOVERFLOW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOVERFLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOVERFLOW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub struct TXREADY_R(crate::FieldReader); +impl TXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub struct RXREADY_R(crate::FieldReader); +impl RXREADY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXREADY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXREADY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub struct TXEMPTY_R(crate::FieldReader); +impl TXEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub struct RXFULL_R(crate::FieldReader); +impl RXFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> COMPLETED_R { + COMPLETED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TXSTALLED_R { + TXSTALLED_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RXSTALLED_R { + RXSTALLED_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> ADDRESSMATCH_R { + ADDRESSMATCH_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NACKDATA_R { + NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RXDATAFIRST_R { + RXDATAFIRST_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&self) -> I2C_START_R { + I2C_START_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&self) -> I2C_STOP_R { + I2C_STOP_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&self) -> TXUNDERFLOW_R { + TXUNDERFLOW_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RXOVERFLOW_R { + RXOVERFLOW_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TXREADY_R { + TXREADY_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RXREADY_R { + RXREADY_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "Slave Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_irq_raw](index.html) module"] +pub struct S0_IRQ_RAW_SPEC; +impl crate::RegisterSpec for S0_IRQ_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_irq_raw::R](R) reader structure"] +impl crate::Readable for S0_IRQ_RAW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets S0_IRQ_RAW to value 0"] +impl crate::Resettable for S0_IRQ_RAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_lastaddress.rs b/src/i2c0/s0_lastaddress.rs new file mode 100644 index 0000000..c264426 --- /dev/null +++ b/src/i2c0/s0_lastaddress.rs @@ -0,0 +1,73 @@ +#[doc = "Register `S0_LASTADDRESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ADDRESS` reader - Address value"] +pub struct ADDRESS_R(crate::FieldReader); +impl ADDRESS_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + ADDRESS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIRECTION` reader - Transaction direction 0=master send, 1=master receive"] +pub struct DIRECTION_R(crate::FieldReader); +impl DIRECTION_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DIRECTION_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIRECTION_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 0 - Transaction direction 0=master send, 1=master receive"] + #[inline(always)] + pub fn direction(&self) -> DIRECTION_R { + DIRECTION_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Slave I2C Last Address value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_lastaddress](index.html) module"] +pub struct S0_LASTADDRESS_SPEC; +impl crate::RegisterSpec for S0_LASTADDRESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_lastaddress::R](R) reader structure"] +impl crate::Readable for S0_LASTADDRESS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets S0_LASTADDRESS to value 0"] +impl crate::Resettable for S0_LASTADDRESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_maxwords.rs b/src/i2c0/s0_maxwords.rs new file mode 100644 index 0000000..e86869e --- /dev/null +++ b/src/i2c0/s0_maxwords.rs @@ -0,0 +1,150 @@ +#[doc = "Register `S0_MAXWORDS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_MAXWORDS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MAXWORD` reader - Max Word Count"] +pub struct MAXWORD_R(crate::FieldReader); +impl MAXWORD_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + MAXWORD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MAXWORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MAXWORD` writer - Max Word Count"] +pub struct MAXWORD_W<'a> { + w: &'a mut W, +} +impl<'a> MAXWORD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enables the max word count"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enables the max word count"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Max Word Count"] + #[inline(always)] + pub fn maxword(&self) -> MAXWORD_R { + MAXWORD_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 31 - Enables the max word count"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Max Word Count"] + #[inline(always)] + pub fn maxword(&mut self) -> MAXWORD_W { + MAXWORD_W { w: self } + } + #[doc = "Bit 31 - Enables the max word count"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave MaxWords Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_maxwords](index.html) module"] +pub struct S0_MAXWORDS_SPEC; +impl crate::RegisterSpec for S0_MAXWORDS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_maxwords::R](R) reader structure"] +impl crate::Readable for S0_MAXWORDS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_maxwords::W](W) writer structure"] +impl crate::Writable for S0_MAXWORDS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_MAXWORDS to value 0"] +impl crate::Resettable for S0_MAXWORDS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_rxcount.rs b/src/i2c0/s0_rxcount.rs new file mode 100644 index 0000000..91b57b5 --- /dev/null +++ b/src/i2c0/s0_rxcount.rs @@ -0,0 +1,53 @@ +#[doc = "Register `S0_RXCOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Count value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:10 - Count value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07ff) as u16) + } +} +#[doc = "Slave RX Count Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_rxcount](index.html) module"] +pub struct S0_RXCOUNT_SPEC; +impl crate::RegisterSpec for S0_RXCOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_rxcount::R](R) reader structure"] +impl crate::Readable for S0_RXCOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets S0_RXCOUNT to value 0"] +impl crate::Resettable for S0_RXCOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_rxfifoirqtrg.rs b/src/i2c0/s0_rxfifoirqtrg.rs new file mode 100644 index 0000000..8a1f859 --- /dev/null +++ b/src/i2c0/s0_rxfifoirqtrg.rs @@ -0,0 +1,103 @@ +#[doc = "Register `S0_RXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_RXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEVEL` reader - Half full level for the Rx FIFO"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Half full level for the Rx FIFO"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_rxfifoirqtrg](index.html) module"] +pub struct S0_RXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for S0_RXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_rxfifoirqtrg::R](R) reader structure"] +impl crate::Readable for S0_RXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_rxfifoirqtrg::W](W) writer structure"] +impl crate::Writable for S0_RXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"] +impl crate::Resettable for S0_RXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_state.rs b/src/i2c0/s0_state.rs new file mode 100644 index 0000000..6d4c6df --- /dev/null +++ b/src/i2c0/s0_state.rs @@ -0,0 +1,31 @@ +#[doc = "Register `S0_STATE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Internal STATE of I2C Slave Controller\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_state](index.html) module"] +pub struct S0_STATE_SPEC; +impl crate::RegisterSpec for S0_STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_state::R](R) reader structure"] +impl crate::Readable for S0_STATE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets S0_STATE to value 0"] +impl crate::Resettable for S0_STATE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_status.rs b/src/i2c0/s0_status.rs new file mode 100644 index 0000000..9324f04 --- /dev/null +++ b/src/i2c0/s0_status.rs @@ -0,0 +1,373 @@ +#[doc = "Register `S0_STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub struct COMPLETED_R(crate::FieldReader); +impl COMPLETED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + COMPLETED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COMPLETED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub struct WAITING_R(crate::FieldReader); +impl WAITING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub struct TXSTALLED_R(crate::FieldReader); +impl TXSTALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXSTALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXSTALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub struct RXSTALLED_R(crate::FieldReader); +impl RXSTALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXSTALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXSTALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub struct ADDRESSMATCH_R(crate::FieldReader); +impl ADDRESSMATCH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADDRESSMATCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRESSMATCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub struct NACKDATA_R(crate::FieldReader); +impl NACKDATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKDATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKDATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub struct RXDATAFIRST_R(crate::FieldReader); +impl RXDATAFIRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXDATAFIRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXDATAFIRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"] +pub struct RXNEMPTY_R(crate::FieldReader); +impl RXNEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFULL` reader - RX FIFO is Full"] +pub struct RXFULL_R(crate::FieldReader); +impl RXFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub struct RXTRIGGER_R(crate::FieldReader); +impl RXTRIGGER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXTRIGGER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXTRIGGER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"] +pub struct TXEMPTY_R(crate::FieldReader); +impl TXEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXNFULL` reader - TX FIFO is Full"] +pub struct TXNFULL_R(crate::FieldReader); +impl TXNFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXNFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXNFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub struct TXTRIGGER_R(crate::FieldReader); +impl TXTRIGGER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXTRIGGER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXTRIGGER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAW_BUSY` reader - I2C Raw Busy value"] +pub struct RAW_BUSY_R(crate::FieldReader); +impl RAW_BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAW_BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAW_BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"] +pub struct RAW_SDA_R(crate::FieldReader); +impl RAW_SDA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAW_SDA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAW_SDA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"] +pub struct RAW_SCL_R(crate::FieldReader); +impl RAW_SCL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAW_SCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAW_SCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> COMPLETED_R { + COMPLETED_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TXSTALLED_R { + TXSTALLED_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RXSTALLED_R { + RXSTALLED_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> ADDRESSMATCH_R { + ADDRESSMATCH_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NACKDATA_R { + NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RXDATAFIRST_R { + RXDATAFIRST_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&self) -> RXNEMPTY_R { + RXNEMPTY_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RXTRIGGER_R { + RXTRIGGER_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&self) -> TXNFULL_R { + TXNFULL_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TXTRIGGER_R { + TXTRIGGER_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 29 - I2C Raw Busy value"] + #[inline(always)] + pub fn raw_busy(&self) -> RAW_BUSY_R { + RAW_BUSY_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&self) -> RAW_SDA_R { + RAW_SDA_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&self) -> RAW_SCL_R { + RAW_SCL_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +#[doc = "Slave I2C Controller Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_status](index.html) module"] +pub struct S0_STATUS_SPEC; +impl crate::RegisterSpec for S0_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_status::R](R) reader structure"] +impl crate::Readable for S0_STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets S0_STATUS to value 0"] +impl crate::Resettable for S0_STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_txcount.rs b/src/i2c0/s0_txcount.rs new file mode 100644 index 0000000..a7307c3 --- /dev/null +++ b/src/i2c0/s0_txcount.rs @@ -0,0 +1,53 @@ +#[doc = "Register `S0_TXCOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Count value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:10 - Count value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x07ff) as u16) + } +} +#[doc = "Slave TX Count Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_txcount](index.html) module"] +pub struct S0_TXCOUNT_SPEC; +impl crate::RegisterSpec for S0_TXCOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_txcount::R](R) reader structure"] +impl crate::Readable for S0_TXCOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets S0_TXCOUNT to value 0"] +impl crate::Resettable for S0_TXCOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/s0_txfifoirqtrg.rs b/src/i2c0/s0_txfifoirqtrg.rs new file mode 100644 index 0000000..568c4fe --- /dev/null +++ b/src/i2c0/s0_txfifoirqtrg.rs @@ -0,0 +1,103 @@ +#[doc = "Register `S0_TXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `S0_TXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LEVEL` reader - Half full level for the Rx FIFO"] +pub struct LEVEL_R(crate::FieldReader); +impl LEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEVEL` writer - Half full level for the Rx FIFO"] +pub struct LEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> LEVEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [s0_txfifoirqtrg](index.html) module"] +pub struct S0_TXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for S0_TXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [s0_txfifoirqtrg::R](R) reader structure"] +impl crate::Readable for S0_TXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [s0_txfifoirqtrg::W](W) writer structure"] +impl crate::Writable for S0_TXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0x08"] +impl crate::Resettable for S0_TXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x08 + } +} diff --git a/src/i2c0/state.rs b/src/i2c0/state.rs new file mode 100644 index 0000000..c2a5924 --- /dev/null +++ b/src/i2c0/state.rs @@ -0,0 +1,31 @@ +#[doc = "Register `STATE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Internal STATE of I2C Master Controller\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [state](index.html) module"] +pub struct STATE_SPEC; +impl crate::RegisterSpec for STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [state::R](R) reader structure"] +impl crate::Readable for STATE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for STATE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/status.rs b/src/i2c0/status.rs new file mode 100644 index 0000000..ee680e4 --- /dev/null +++ b/src/i2c0/status.rs @@ -0,0 +1,771 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `I2CIDLE` reader - I2C bus is idle"] +pub struct I2CIDLE_R(crate::FieldReader); +impl I2CIDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2CIDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2CIDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2CIDLE` writer - I2C bus is idle"] +pub struct I2CIDLE_W<'a> { + w: &'a mut W, +} +impl<'a> I2CIDLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IDLE` reader - I2C controller is Idle"] +pub struct IDLE_R(crate::FieldReader); +impl IDLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IDLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IDLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IDLE` writer - I2C controller is Idle"] +pub struct IDLE_W<'a> { + w: &'a mut W, +} +impl<'a> IDLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub struct WAITING_R(crate::FieldReader); +impl WAITING_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WAITING_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WAITING_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub struct WAITING_W<'a> { + w: &'a mut W, +} +impl<'a> WAITING_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub struct STALLED_R(crate::FieldReader); +impl STALLED_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STALLED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STALLED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STALLED` writer - Controller is Stalled"] +pub struct STALLED_W<'a> { + w: &'a mut W, +} +impl<'a> STALLED_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub struct ARBLOST_R(crate::FieldReader); +impl ARBLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub struct NACKADDR_R(crate::FieldReader); +impl NACKADDR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"] +pub struct NACKADDR_W<'a> { + w: &'a mut W, +} +impl<'a> NACKADDR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub struct NACKDATA_R(crate::FieldReader); +impl NACKDATA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NACKDATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NACKDATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub struct NACKDATA_W<'a> { + w: &'a mut W, +} +impl<'a> NACKDATA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"] +pub struct RXNEMPTY_R(crate::FieldReader); +impl RXNEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXNEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNEMPTY` writer - RX FIFO is Not Empty"] +pub struct RXNEMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> RXNEMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RXFULL` reader - RX FIFO is Full"] +pub struct RXFULL_R(crate::FieldReader); +impl RXFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFULL` writer - RX FIFO is Full"] +pub struct RXFULL_W<'a> { + w: &'a mut W, +} +impl<'a> RXFULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub struct RXTRIGGER_R(crate::FieldReader); +impl RXTRIGGER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXTRIGGER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXTRIGGER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXTRIGGER` writer - RX FIFO Above Trigger Level"] +pub struct RXTRIGGER_W<'a> { + w: &'a mut W, +} +impl<'a> RXTRIGGER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"] +pub struct TXEMPTY_R(crate::FieldReader); +impl TXEMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXEMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXEMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXEMPTY` writer - TX FIFO is Empty"] +pub struct TXEMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> TXEMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TXNFULL` reader - TX FIFO is Full"] +pub struct TXNFULL_R(crate::FieldReader); +impl TXNFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXNFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXNFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXNFULL` writer - TX FIFO is Full"] +pub struct TXNFULL_W<'a> { + w: &'a mut W, +} +impl<'a> TXNFULL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub struct TXTRIGGER_R(crate::FieldReader); +impl TXTRIGGER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXTRIGGER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXTRIGGER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXTRIGGER` writer - TX FIFO Below Trigger Level"] +pub struct TXTRIGGER_W<'a> { + w: &'a mut W, +} +impl<'a> TXTRIGGER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"] +pub struct RAW_SDA_R(crate::FieldReader); +impl RAW_SDA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAW_SDA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAW_SDA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAW_SDA` writer - I2C Raw SDA value"] +pub struct RAW_SDA_W<'a> { + w: &'a mut W, +} +impl<'a> RAW_SDA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"] +pub struct RAW_SCL_R(crate::FieldReader); +impl RAW_SCL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAW_SCL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAW_SCL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAW_SCL` writer - I2C Raw SCL value"] +pub struct RAW_SCL_W<'a> { + w: &'a mut W, +} +impl<'a> RAW_SCL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bit 0 - I2C bus is idle"] + #[inline(always)] + pub fn i2cidle(&self) -> I2CIDLE_R { + I2CIDLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - I2C controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> STALLED_R { + STALLED_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NACKADDR_R { + NACKADDR_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NACKDATA_R { + NACKDATA_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&self) -> RXNEMPTY_R { + RXNEMPTY_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RXTRIGGER_R { + RXTRIGGER_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&self) -> TXNFULL_R { + TXNFULL_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TXTRIGGER_R { + TXTRIGGER_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&self) -> RAW_SDA_R { + RAW_SDA_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&self) -> RAW_SCL_R { + RAW_SCL_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C bus is idle"] + #[inline(always)] + pub fn i2cidle(&mut self) -> I2CIDLE_W { + I2CIDLE_W { w: self } + } + #[doc = "Bit 1 - I2C controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IDLE_W { + IDLE_W { w: self } + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WAITING_W { + WAITING_W { w: self } + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&mut self) -> STALLED_W { + STALLED_W { w: self } + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&mut self) -> NACKADDR_W { + NACKADDR_W { w: self } + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NACKDATA_W { + NACKDATA_W { w: self } + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&mut self) -> RXNEMPTY_W { + RXNEMPTY_W { w: self } + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RXFULL_W { + RXFULL_W { w: self } + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&mut self) -> RXTRIGGER_W { + RXTRIGGER_W { w: self } + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TXEMPTY_W { + TXEMPTY_W { w: self } + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&mut self) -> TXNFULL_W { + TXNFULL_W { w: self } + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&mut self) -> TXTRIGGER_W { + TXTRIGGER_W { w: self } + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&mut self) -> RAW_SDA_W { + RAW_SDA_W { w: self } + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&mut self) -> RAW_SCL_W { + RAW_SCL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2C Controller Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/tmconfig.rs b/src/i2c0/tmconfig.rs new file mode 100644 index 0000000..c9700c3 --- /dev/null +++ b/src/i2c0/tmconfig.rs @@ -0,0 +1,64 @@ +#[doc = "Register `TMCONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TMCONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Timing Config Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tmconfig](index.html) module"] +pub struct TMCONFIG_SPEC; +impl crate::RegisterSpec for TMCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tmconfig::R](R) reader structure"] +impl crate::Readable for TMCONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tmconfig::W](W) writer structure"] +impl crate::Writable for TMCONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TMCONFIG to value 0"] +impl crate::Resettable for TMCONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/txcount.rs b/src/i2c0/txcount.rs new file mode 100644 index 0000000..59db92b --- /dev/null +++ b/src/i2c0/txcount.rs @@ -0,0 +1,31 @@ +#[doc = "Register `TXCOUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "TX Count Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txcount](index.html) module"] +pub struct TXCOUNT_SPEC; +impl crate::RegisterSpec for TXCOUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txcount::R](R) reader structure"] +impl crate::Readable for TXCOUNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXCOUNT to value 0"] +impl crate::Resettable for TXCOUNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/txfifoirqtrg.rs b/src/i2c0/txfifoirqtrg.rs new file mode 100644 index 0000000..a88c823 --- /dev/null +++ b/src/i2c0/txfifoirqtrg.rs @@ -0,0 +1,64 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfifoirqtrg](index.html) module"] +pub struct TXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for TXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txfifoirqtrg::R](R) reader structure"] +impl crate::Readable for TXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txfifoirqtrg::W](W) writer structure"] +impl crate::Writable for TXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/i2c0/words.rs b/src/i2c0/words.rs new file mode 100644 index 0000000..04e1ee5 --- /dev/null +++ b/src/i2c0/words.rs @@ -0,0 +1,64 @@ +#[doc = "Register `WORDS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WORDS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Word Count value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [words](index.html) module"] +pub struct WORDS_SPEC; +impl crate::RegisterSpec for WORDS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [words::R](R) reader structure"] +impl crate::Readable for WORDS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [words::W](W) writer structure"] +impl crate::Writable for WORDS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WORDS to value 0"] +impl crate::Resettable for WORDS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig.rs b/src/ioconfig.rs new file mode 100644 index 0000000..477ed2c --- /dev/null +++ b/src/ioconfig.rs @@ -0,0 +1,102 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x40 - PORTA Pin Configuration Register"] + pub porta: [crate::Reg; 16], + #[doc = "0x40..0x80 - PORTB Pin Configuration Register"] + pub portb: [crate::Reg; 16], + #[doc = "0x80..0xc0 - PORTC Pin Configuration Register"] + pub portc: [crate::Reg; 16], + #[doc = "0xc0..0x100 - PORTD Pin Configuration Register"] + pub portd: [crate::Reg; 16], + #[doc = "0x100..0x140 - PORTE Pin Configuration Register"] + pub porte: [crate::Reg; 16], + #[doc = "0x140..0x180 - PORTF Pin Configuration Register"] + pub portf: [crate::Reg; 16], + #[doc = "0x180..0x1a0 - PORTG Pin Configuration Register"] + pub portg: [crate::Reg; 8], + _reserved7: [u8; 0x20], + #[doc = "0x1c0 - Clock divide value. 0 will disable the clock"] + pub clkdiv0: crate::Reg, + #[doc = "0x1c4 - Clock divide value. 0 will disable the clock"] + pub clkdiv1: crate::Reg, + #[doc = "0x1c8 - Clock divide value. 0 will disable the clock"] + pub clkdiv2: crate::Reg, + #[doc = "0x1cc - Clock divide value. 0 will disable the clock"] + pub clkdiv3: crate::Reg, + #[doc = "0x1d0 - Clock divide value. 0 will disable the clock"] + pub clkdiv4: crate::Reg, + #[doc = "0x1d4 - Clock divide value. 0 will disable the clock"] + pub clkdiv5: crate::Reg, + #[doc = "0x1d8 - Clock divide value. 0 will disable the clock"] + pub clkdiv6: crate::Reg, + #[doc = "0x1dc - Clock divide value. 0 will disable the clock"] + pub clkdiv7: crate::Reg, + _reserved15: [u8; 0x0e1c], + #[doc = "0xffc - Peripheral ID Register"] + pub perid: crate::Reg, +} +#[doc = "PORTA register accessor: an alias for `Reg`"] +pub type PORTA = crate::Reg; +#[doc = "PORTA Pin Configuration Register"] +pub mod porta; +#[doc = "PORTB register accessor: an alias for `Reg`"] +pub type PORTB = crate::Reg; +#[doc = "PORTB Pin Configuration Register"] +pub mod portb; +#[doc = "PORTC register accessor: an alias for `Reg`"] +pub type PORTC = crate::Reg; +#[doc = "PORTC Pin Configuration Register"] +pub mod portc; +#[doc = "PORTD register accessor: an alias for `Reg`"] +pub type PORTD = crate::Reg; +#[doc = "PORTD Pin Configuration Register"] +pub mod portd; +#[doc = "PORTE register accessor: an alias for `Reg`"] +pub type PORTE = crate::Reg; +#[doc = "PORTE Pin Configuration Register"] +pub mod porte; +#[doc = "PORTF register accessor: an alias for `Reg`"] +pub type PORTF = crate::Reg; +#[doc = "PORTF Pin Configuration Register"] +pub mod portf; +#[doc = "PORTG register accessor: an alias for `Reg`"] +pub type PORTG = crate::Reg; +#[doc = "PORTG Pin Configuration Register"] +pub mod portg; +#[doc = "CLKDIV0 register accessor: an alias for `Reg`"] +pub type CLKDIV0 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv0; +#[doc = "CLKDIV1 register accessor: an alias for `Reg`"] +pub type CLKDIV1 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv1; +#[doc = "CLKDIV2 register accessor: an alias for `Reg`"] +pub type CLKDIV2 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv2; +#[doc = "CLKDIV3 register accessor: an alias for `Reg`"] +pub type CLKDIV3 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv3; +#[doc = "CLKDIV4 register accessor: an alias for `Reg`"] +pub type CLKDIV4 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv4; +#[doc = "CLKDIV5 register accessor: an alias for `Reg`"] +pub type CLKDIV5 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv5; +#[doc = "CLKDIV6 register accessor: an alias for `Reg`"] +pub type CLKDIV6 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv6; +#[doc = "CLKDIV7 register accessor: an alias for `Reg`"] +pub type CLKDIV7 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv7; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/ioconfig/clkdiv0.rs b/src/ioconfig/clkdiv0.rs new file mode 100644 index 0000000..337076b --- /dev/null +++ b/src/ioconfig/clkdiv0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CLKDIV0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkdiv0](index.html) module"] +pub struct CLKDIV0_SPEC; +impl crate::RegisterSpec for CLKDIV0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkdiv0::R](R) reader structure"] +impl crate::Readable for CLKDIV0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CLKDIV0 to value 0"] +impl crate::Resettable for CLKDIV0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/clkdiv1.rs b/src/ioconfig/clkdiv1.rs new file mode 100644 index 0000000..553a9b7 --- /dev/null +++ b/src/ioconfig/clkdiv1.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLKDIV1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKDIV1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkdiv1](index.html) module"] +pub struct CLKDIV1_SPEC; +impl crate::RegisterSpec for CLKDIV1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkdiv1::R](R) reader structure"] +impl crate::Readable for CLKDIV1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkdiv1::W](W) writer structure"] +impl crate::Writable for CLKDIV1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKDIV1 to value 0"] +impl crate::Resettable for CLKDIV1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/clkdiv2.rs b/src/ioconfig/clkdiv2.rs new file mode 100644 index 0000000..3fdbbf5 --- /dev/null +++ b/src/ioconfig/clkdiv2.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLKDIV2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKDIV2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkdiv2](index.html) module"] +pub struct CLKDIV2_SPEC; +impl crate::RegisterSpec for CLKDIV2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkdiv2::R](R) reader structure"] +impl crate::Readable for CLKDIV2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkdiv2::W](W) writer structure"] +impl crate::Writable for CLKDIV2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKDIV2 to value 0"] +impl crate::Resettable for CLKDIV2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/clkdiv3.rs b/src/ioconfig/clkdiv3.rs new file mode 100644 index 0000000..f5763a2 --- /dev/null +++ b/src/ioconfig/clkdiv3.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLKDIV3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKDIV3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkdiv3](index.html) module"] +pub struct CLKDIV3_SPEC; +impl crate::RegisterSpec for CLKDIV3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkdiv3::R](R) reader structure"] +impl crate::Readable for CLKDIV3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkdiv3::W](W) writer structure"] +impl crate::Writable for CLKDIV3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKDIV3 to value 0"] +impl crate::Resettable for CLKDIV3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/clkdiv4.rs b/src/ioconfig/clkdiv4.rs new file mode 100644 index 0000000..38989da --- /dev/null +++ b/src/ioconfig/clkdiv4.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLKDIV4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKDIV4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkdiv4](index.html) module"] +pub struct CLKDIV4_SPEC; +impl crate::RegisterSpec for CLKDIV4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkdiv4::R](R) reader structure"] +impl crate::Readable for CLKDIV4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkdiv4::W](W) writer structure"] +impl crate::Writable for CLKDIV4_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKDIV4 to value 0"] +impl crate::Resettable for CLKDIV4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/clkdiv5.rs b/src/ioconfig/clkdiv5.rs new file mode 100644 index 0000000..e55ca19 --- /dev/null +++ b/src/ioconfig/clkdiv5.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLKDIV5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKDIV5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkdiv5](index.html) module"] +pub struct CLKDIV5_SPEC; +impl crate::RegisterSpec for CLKDIV5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkdiv5::R](R) reader structure"] +impl crate::Readable for CLKDIV5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkdiv5::W](W) writer structure"] +impl crate::Writable for CLKDIV5_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKDIV5 to value 0"] +impl crate::Resettable for CLKDIV5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/clkdiv6.rs b/src/ioconfig/clkdiv6.rs new file mode 100644 index 0000000..9527e28 --- /dev/null +++ b/src/ioconfig/clkdiv6.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLKDIV6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKDIV6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkdiv6](index.html) module"] +pub struct CLKDIV6_SPEC; +impl crate::RegisterSpec for CLKDIV6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkdiv6::R](R) reader structure"] +impl crate::Readable for CLKDIV6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkdiv6::W](W) writer structure"] +impl crate::Writable for CLKDIV6_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKDIV6 to value 0"] +impl crate::Resettable for CLKDIV6_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/clkdiv7.rs b/src/ioconfig/clkdiv7.rs new file mode 100644 index 0000000..09ac34b --- /dev/null +++ b/src/ioconfig/clkdiv7.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLKDIV7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKDIV7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkdiv7](index.html) module"] +pub struct CLKDIV7_SPEC; +impl crate::RegisterSpec for CLKDIV7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkdiv7::R](R) reader structure"] +impl crate::Readable for CLKDIV7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkdiv7::W](W) writer structure"] +impl crate::Writable for CLKDIV7_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKDIV7 to value 0"] +impl crate::Resettable for CLKDIV7_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/perid.rs b/src/ioconfig/perid.rs new file mode 100644 index 0000000..9bc7997 --- /dev/null +++ b/src/ioconfig/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0282_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0282_07e9 + } +} diff --git a/src/ioconfig/porta.rs b/src/ioconfig/porta.rs new file mode 100644 index 0000000..13d1444 --- /dev/null +++ b/src/ioconfig/porta.rs @@ -0,0 +1,655 @@ +#[doc = "Register `PORTA[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PORTA[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLTTYPE_A { + #[doc = "0: Synchronize to system clock"] + SYNC = 0, + #[doc = "1: Direct input, no synchronization"] + DIRECT = 1, + #[doc = "2: Require 2 samples to have the same value"] + FILTER1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + FILTER2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + FILTER3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + FILTER4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLTTYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub struct FLTTYPE_R(crate::FieldReader); +impl FLTTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTTYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLTTYPE_A::SYNC), + 1 => Some(FLTTYPE_A::DIRECT), + 2 => Some(FLTTYPE_A::FILTER1), + 3 => Some(FLTTYPE_A::FILTER2), + 4 => Some(FLTTYPE_A::FILTER3), + 5 => Some(FLTTYPE_A::FILTER4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == FLTTYPE_A::SYNC + } + #[doc = "Checks if the value of the field is `DIRECT`"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + **self == FLTTYPE_A::DIRECT + } + #[doc = "Checks if the value of the field is `FILTER1`"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + **self == FLTTYPE_A::FILTER1 + } + #[doc = "Checks if the value of the field is `FILTER2`"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + **self == FLTTYPE_A::FILTER2 + } + #[doc = "Checks if the value of the field is `FILTER3`"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + **self == FLTTYPE_A::FILTER3 + } + #[doc = "Checks if the value of the field is `FILTER4`"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + **self == FLTTYPE_A::FILTER4 + } +} +impl core::ops::Deref for FLTTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub struct FLTTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> FLTTYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLTTYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(FLTTYPE_A::SYNC) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut W { + self.variant(FLTTYPE_A::DIRECT) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub struct FLTCLK_R(crate::FieldReader); +impl FLTCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTCLK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLTCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub struct FLTCLK_W<'a> { + w: &'a mut W, +} +impl<'a> FLTCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub struct INVINP_R(crate::FieldReader); +impl INVINP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVINP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVINP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub struct INVINP_W<'a> { + w: &'a mut W, +} +impl<'a> INVINP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub struct IEWO_R(crate::FieldReader); +impl IEWO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IEWO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IEWO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub struct IEWO_W<'a> { + w: &'a mut W, +} +impl<'a> IEWO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub struct OPENDRN_R(crate::FieldReader); +impl OPENDRN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPENDRN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPENDRN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub struct OPENDRN_W<'a> { + w: &'a mut W, +} +impl<'a> OPENDRN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub struct INVOUT_R(crate::FieldReader); +impl INVOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub struct INVOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INVOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub struct PLEVEL_R(crate::FieldReader); +impl PLEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub struct PLEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> PLEVEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub struct PEN_R(crate::FieldReader); +impl PEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub struct PEN_W<'a> { + w: &'a mut W, +} +impl<'a> PEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub struct PWOA_R(crate::FieldReader); +impl PWOA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PWOA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PWOA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub struct PWOA_W<'a> { + w: &'a mut W, +} +impl<'a> PWOA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub struct FUNSEL_R(crate::FieldReader); +impl FUNSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FUNSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FUNSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub struct FUNSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FUNSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub struct IODIS_R(crate::FieldReader); +impl IODIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IODIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IODIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub struct IODIS_W<'a> { + w: &'a mut W, +} +impl<'a> IODIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FLTTYPE_R { + FLTTYPE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FLTCLK_R { + FLTCLK_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> INVINP_R { + INVINP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IEWO_R { + IEWO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OPENDRN_R { + OPENDRN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> INVOUT_R { + INVOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PLEVEL_R { + PLEVEL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PWOA_R { + PWOA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FUNSEL_R { + FUNSEL_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IODIS_R { + IODIS_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&mut self) -> FLTTYPE_W { + FLTTYPE_W { w: self } + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&mut self) -> FLTCLK_W { + FLTCLK_W { w: self } + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&mut self) -> INVINP_W { + INVINP_W { w: self } + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&mut self) -> IEWO_W { + IEWO_W { w: self } + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&mut self) -> OPENDRN_W { + OPENDRN_W { w: self } + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&mut self) -> INVOUT_W { + INVOUT_W { w: self } + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&mut self) -> PLEVEL_W { + PLEVEL_W { w: self } + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&mut self) -> PEN_W { + PEN_W { w: self } + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&mut self) -> PWOA_W { + PWOA_W { w: self } + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&mut self) -> FUNSEL_W { + FUNSEL_W { w: self } + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&mut self) -> IODIS_W { + IODIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PORTA Pin Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [porta](index.html) module"] +pub struct PORTA_SPEC; +impl crate::RegisterSpec for PORTA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [porta::R](R) reader structure"] +impl crate::Readable for PORTA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [porta::W](W) writer structure"] +impl crate::Writable for PORTA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PORTA[%s] +to value 0"] +impl crate::Resettable for PORTA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/portb.rs b/src/ioconfig/portb.rs new file mode 100644 index 0000000..3d70286 --- /dev/null +++ b/src/ioconfig/portb.rs @@ -0,0 +1,655 @@ +#[doc = "Register `PORTB[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PORTB[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLTTYPE_A { + #[doc = "0: Synchronize to system clock"] + SYNC = 0, + #[doc = "1: Direct input, no synchronization"] + DIRECT = 1, + #[doc = "2: Require 2 samples to have the same value"] + FILTER1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + FILTER2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + FILTER3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + FILTER4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLTTYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub struct FLTTYPE_R(crate::FieldReader); +impl FLTTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTTYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLTTYPE_A::SYNC), + 1 => Some(FLTTYPE_A::DIRECT), + 2 => Some(FLTTYPE_A::FILTER1), + 3 => Some(FLTTYPE_A::FILTER2), + 4 => Some(FLTTYPE_A::FILTER3), + 5 => Some(FLTTYPE_A::FILTER4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == FLTTYPE_A::SYNC + } + #[doc = "Checks if the value of the field is `DIRECT`"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + **self == FLTTYPE_A::DIRECT + } + #[doc = "Checks if the value of the field is `FILTER1`"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + **self == FLTTYPE_A::FILTER1 + } + #[doc = "Checks if the value of the field is `FILTER2`"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + **self == FLTTYPE_A::FILTER2 + } + #[doc = "Checks if the value of the field is `FILTER3`"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + **self == FLTTYPE_A::FILTER3 + } + #[doc = "Checks if the value of the field is `FILTER4`"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + **self == FLTTYPE_A::FILTER4 + } +} +impl core::ops::Deref for FLTTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub struct FLTTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> FLTTYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLTTYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(FLTTYPE_A::SYNC) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut W { + self.variant(FLTTYPE_A::DIRECT) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub struct FLTCLK_R(crate::FieldReader); +impl FLTCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTCLK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLTCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub struct FLTCLK_W<'a> { + w: &'a mut W, +} +impl<'a> FLTCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub struct INVINP_R(crate::FieldReader); +impl INVINP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVINP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVINP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub struct INVINP_W<'a> { + w: &'a mut W, +} +impl<'a> INVINP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub struct IEWO_R(crate::FieldReader); +impl IEWO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IEWO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IEWO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub struct IEWO_W<'a> { + w: &'a mut W, +} +impl<'a> IEWO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub struct OPENDRN_R(crate::FieldReader); +impl OPENDRN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPENDRN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPENDRN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub struct OPENDRN_W<'a> { + w: &'a mut W, +} +impl<'a> OPENDRN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub struct INVOUT_R(crate::FieldReader); +impl INVOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub struct INVOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INVOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub struct PLEVEL_R(crate::FieldReader); +impl PLEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub struct PLEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> PLEVEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub struct PEN_R(crate::FieldReader); +impl PEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub struct PEN_W<'a> { + w: &'a mut W, +} +impl<'a> PEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub struct PWOA_R(crate::FieldReader); +impl PWOA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PWOA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PWOA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub struct PWOA_W<'a> { + w: &'a mut W, +} +impl<'a> PWOA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub struct FUNSEL_R(crate::FieldReader); +impl FUNSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FUNSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FUNSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub struct FUNSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FUNSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub struct IODIS_R(crate::FieldReader); +impl IODIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IODIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IODIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub struct IODIS_W<'a> { + w: &'a mut W, +} +impl<'a> IODIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FLTTYPE_R { + FLTTYPE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FLTCLK_R { + FLTCLK_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> INVINP_R { + INVINP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IEWO_R { + IEWO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OPENDRN_R { + OPENDRN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> INVOUT_R { + INVOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PLEVEL_R { + PLEVEL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PWOA_R { + PWOA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FUNSEL_R { + FUNSEL_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IODIS_R { + IODIS_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&mut self) -> FLTTYPE_W { + FLTTYPE_W { w: self } + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&mut self) -> FLTCLK_W { + FLTCLK_W { w: self } + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&mut self) -> INVINP_W { + INVINP_W { w: self } + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&mut self) -> IEWO_W { + IEWO_W { w: self } + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&mut self) -> OPENDRN_W { + OPENDRN_W { w: self } + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&mut self) -> INVOUT_W { + INVOUT_W { w: self } + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&mut self) -> PLEVEL_W { + PLEVEL_W { w: self } + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&mut self) -> PEN_W { + PEN_W { w: self } + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&mut self) -> PWOA_W { + PWOA_W { w: self } + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&mut self) -> FUNSEL_W { + FUNSEL_W { w: self } + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&mut self) -> IODIS_W { + IODIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PORTB Pin Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [portb](index.html) module"] +pub struct PORTB_SPEC; +impl crate::RegisterSpec for PORTB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [portb::R](R) reader structure"] +impl crate::Readable for PORTB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [portb::W](W) writer structure"] +impl crate::Writable for PORTB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PORTB[%s] +to value 0"] +impl crate::Resettable for PORTB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/portc.rs b/src/ioconfig/portc.rs new file mode 100644 index 0000000..752f437 --- /dev/null +++ b/src/ioconfig/portc.rs @@ -0,0 +1,655 @@ +#[doc = "Register `PORTC[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PORTC[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLTTYPE_A { + #[doc = "0: Synchronize to system clock"] + SYNC = 0, + #[doc = "1: Direct input, no synchronization"] + DIRECT = 1, + #[doc = "2: Require 2 samples to have the same value"] + FILTER1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + FILTER2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + FILTER3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + FILTER4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLTTYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub struct FLTTYPE_R(crate::FieldReader); +impl FLTTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTTYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLTTYPE_A::SYNC), + 1 => Some(FLTTYPE_A::DIRECT), + 2 => Some(FLTTYPE_A::FILTER1), + 3 => Some(FLTTYPE_A::FILTER2), + 4 => Some(FLTTYPE_A::FILTER3), + 5 => Some(FLTTYPE_A::FILTER4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == FLTTYPE_A::SYNC + } + #[doc = "Checks if the value of the field is `DIRECT`"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + **self == FLTTYPE_A::DIRECT + } + #[doc = "Checks if the value of the field is `FILTER1`"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + **self == FLTTYPE_A::FILTER1 + } + #[doc = "Checks if the value of the field is `FILTER2`"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + **self == FLTTYPE_A::FILTER2 + } + #[doc = "Checks if the value of the field is `FILTER3`"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + **self == FLTTYPE_A::FILTER3 + } + #[doc = "Checks if the value of the field is `FILTER4`"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + **self == FLTTYPE_A::FILTER4 + } +} +impl core::ops::Deref for FLTTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub struct FLTTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> FLTTYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLTTYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(FLTTYPE_A::SYNC) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut W { + self.variant(FLTTYPE_A::DIRECT) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub struct FLTCLK_R(crate::FieldReader); +impl FLTCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTCLK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLTCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub struct FLTCLK_W<'a> { + w: &'a mut W, +} +impl<'a> FLTCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub struct INVINP_R(crate::FieldReader); +impl INVINP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVINP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVINP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub struct INVINP_W<'a> { + w: &'a mut W, +} +impl<'a> INVINP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub struct IEWO_R(crate::FieldReader); +impl IEWO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IEWO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IEWO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub struct IEWO_W<'a> { + w: &'a mut W, +} +impl<'a> IEWO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub struct OPENDRN_R(crate::FieldReader); +impl OPENDRN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPENDRN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPENDRN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub struct OPENDRN_W<'a> { + w: &'a mut W, +} +impl<'a> OPENDRN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub struct INVOUT_R(crate::FieldReader); +impl INVOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub struct INVOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INVOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub struct PLEVEL_R(crate::FieldReader); +impl PLEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub struct PLEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> PLEVEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub struct PEN_R(crate::FieldReader); +impl PEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub struct PEN_W<'a> { + w: &'a mut W, +} +impl<'a> PEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub struct PWOA_R(crate::FieldReader); +impl PWOA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PWOA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PWOA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub struct PWOA_W<'a> { + w: &'a mut W, +} +impl<'a> PWOA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub struct FUNSEL_R(crate::FieldReader); +impl FUNSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FUNSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FUNSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub struct FUNSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FUNSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub struct IODIS_R(crate::FieldReader); +impl IODIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IODIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IODIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub struct IODIS_W<'a> { + w: &'a mut W, +} +impl<'a> IODIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FLTTYPE_R { + FLTTYPE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FLTCLK_R { + FLTCLK_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> INVINP_R { + INVINP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IEWO_R { + IEWO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OPENDRN_R { + OPENDRN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> INVOUT_R { + INVOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PLEVEL_R { + PLEVEL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PWOA_R { + PWOA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FUNSEL_R { + FUNSEL_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IODIS_R { + IODIS_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&mut self) -> FLTTYPE_W { + FLTTYPE_W { w: self } + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&mut self) -> FLTCLK_W { + FLTCLK_W { w: self } + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&mut self) -> INVINP_W { + INVINP_W { w: self } + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&mut self) -> IEWO_W { + IEWO_W { w: self } + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&mut self) -> OPENDRN_W { + OPENDRN_W { w: self } + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&mut self) -> INVOUT_W { + INVOUT_W { w: self } + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&mut self) -> PLEVEL_W { + PLEVEL_W { w: self } + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&mut self) -> PEN_W { + PEN_W { w: self } + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&mut self) -> PWOA_W { + PWOA_W { w: self } + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&mut self) -> FUNSEL_W { + FUNSEL_W { w: self } + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&mut self) -> IODIS_W { + IODIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PORTC Pin Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [portc](index.html) module"] +pub struct PORTC_SPEC; +impl crate::RegisterSpec for PORTC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [portc::R](R) reader structure"] +impl crate::Readable for PORTC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [portc::W](W) writer structure"] +impl crate::Writable for PORTC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PORTC[%s] +to value 0"] +impl crate::Resettable for PORTC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/portd.rs b/src/ioconfig/portd.rs new file mode 100644 index 0000000..96e825b --- /dev/null +++ b/src/ioconfig/portd.rs @@ -0,0 +1,655 @@ +#[doc = "Register `PORTD[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PORTD[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLTTYPE_A { + #[doc = "0: Synchronize to system clock"] + SYNC = 0, + #[doc = "1: Direct input, no synchronization"] + DIRECT = 1, + #[doc = "2: Require 2 samples to have the same value"] + FILTER1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + FILTER2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + FILTER3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + FILTER4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLTTYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub struct FLTTYPE_R(crate::FieldReader); +impl FLTTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTTYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLTTYPE_A::SYNC), + 1 => Some(FLTTYPE_A::DIRECT), + 2 => Some(FLTTYPE_A::FILTER1), + 3 => Some(FLTTYPE_A::FILTER2), + 4 => Some(FLTTYPE_A::FILTER3), + 5 => Some(FLTTYPE_A::FILTER4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == FLTTYPE_A::SYNC + } + #[doc = "Checks if the value of the field is `DIRECT`"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + **self == FLTTYPE_A::DIRECT + } + #[doc = "Checks if the value of the field is `FILTER1`"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + **self == FLTTYPE_A::FILTER1 + } + #[doc = "Checks if the value of the field is `FILTER2`"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + **self == FLTTYPE_A::FILTER2 + } + #[doc = "Checks if the value of the field is `FILTER3`"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + **self == FLTTYPE_A::FILTER3 + } + #[doc = "Checks if the value of the field is `FILTER4`"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + **self == FLTTYPE_A::FILTER4 + } +} +impl core::ops::Deref for FLTTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub struct FLTTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> FLTTYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLTTYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(FLTTYPE_A::SYNC) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut W { + self.variant(FLTTYPE_A::DIRECT) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub struct FLTCLK_R(crate::FieldReader); +impl FLTCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTCLK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLTCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub struct FLTCLK_W<'a> { + w: &'a mut W, +} +impl<'a> FLTCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub struct INVINP_R(crate::FieldReader); +impl INVINP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVINP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVINP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub struct INVINP_W<'a> { + w: &'a mut W, +} +impl<'a> INVINP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub struct IEWO_R(crate::FieldReader); +impl IEWO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IEWO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IEWO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub struct IEWO_W<'a> { + w: &'a mut W, +} +impl<'a> IEWO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub struct OPENDRN_R(crate::FieldReader); +impl OPENDRN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPENDRN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPENDRN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub struct OPENDRN_W<'a> { + w: &'a mut W, +} +impl<'a> OPENDRN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub struct INVOUT_R(crate::FieldReader); +impl INVOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub struct INVOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INVOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub struct PLEVEL_R(crate::FieldReader); +impl PLEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub struct PLEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> PLEVEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub struct PEN_R(crate::FieldReader); +impl PEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub struct PEN_W<'a> { + w: &'a mut W, +} +impl<'a> PEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub struct PWOA_R(crate::FieldReader); +impl PWOA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PWOA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PWOA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub struct PWOA_W<'a> { + w: &'a mut W, +} +impl<'a> PWOA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub struct FUNSEL_R(crate::FieldReader); +impl FUNSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FUNSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FUNSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub struct FUNSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FUNSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub struct IODIS_R(crate::FieldReader); +impl IODIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IODIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IODIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub struct IODIS_W<'a> { + w: &'a mut W, +} +impl<'a> IODIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FLTTYPE_R { + FLTTYPE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FLTCLK_R { + FLTCLK_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> INVINP_R { + INVINP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IEWO_R { + IEWO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OPENDRN_R { + OPENDRN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> INVOUT_R { + INVOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PLEVEL_R { + PLEVEL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PWOA_R { + PWOA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FUNSEL_R { + FUNSEL_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IODIS_R { + IODIS_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&mut self) -> FLTTYPE_W { + FLTTYPE_W { w: self } + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&mut self) -> FLTCLK_W { + FLTCLK_W { w: self } + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&mut self) -> INVINP_W { + INVINP_W { w: self } + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&mut self) -> IEWO_W { + IEWO_W { w: self } + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&mut self) -> OPENDRN_W { + OPENDRN_W { w: self } + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&mut self) -> INVOUT_W { + INVOUT_W { w: self } + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&mut self) -> PLEVEL_W { + PLEVEL_W { w: self } + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&mut self) -> PEN_W { + PEN_W { w: self } + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&mut self) -> PWOA_W { + PWOA_W { w: self } + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&mut self) -> FUNSEL_W { + FUNSEL_W { w: self } + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&mut self) -> IODIS_W { + IODIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PORTD Pin Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [portd](index.html) module"] +pub struct PORTD_SPEC; +impl crate::RegisterSpec for PORTD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [portd::R](R) reader structure"] +impl crate::Readable for PORTD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [portd::W](W) writer structure"] +impl crate::Writable for PORTD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PORTD[%s] +to value 0"] +impl crate::Resettable for PORTD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/porte.rs b/src/ioconfig/porte.rs new file mode 100644 index 0000000..ef90faa --- /dev/null +++ b/src/ioconfig/porte.rs @@ -0,0 +1,655 @@ +#[doc = "Register `PORTE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PORTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLTTYPE_A { + #[doc = "0: Synchronize to system clock"] + SYNC = 0, + #[doc = "1: Direct input, no synchronization"] + DIRECT = 1, + #[doc = "2: Require 2 samples to have the same value"] + FILTER1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + FILTER2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + FILTER3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + FILTER4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLTTYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub struct FLTTYPE_R(crate::FieldReader); +impl FLTTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTTYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLTTYPE_A::SYNC), + 1 => Some(FLTTYPE_A::DIRECT), + 2 => Some(FLTTYPE_A::FILTER1), + 3 => Some(FLTTYPE_A::FILTER2), + 4 => Some(FLTTYPE_A::FILTER3), + 5 => Some(FLTTYPE_A::FILTER4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == FLTTYPE_A::SYNC + } + #[doc = "Checks if the value of the field is `DIRECT`"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + **self == FLTTYPE_A::DIRECT + } + #[doc = "Checks if the value of the field is `FILTER1`"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + **self == FLTTYPE_A::FILTER1 + } + #[doc = "Checks if the value of the field is `FILTER2`"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + **self == FLTTYPE_A::FILTER2 + } + #[doc = "Checks if the value of the field is `FILTER3`"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + **self == FLTTYPE_A::FILTER3 + } + #[doc = "Checks if the value of the field is `FILTER4`"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + **self == FLTTYPE_A::FILTER4 + } +} +impl core::ops::Deref for FLTTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub struct FLTTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> FLTTYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLTTYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(FLTTYPE_A::SYNC) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut W { + self.variant(FLTTYPE_A::DIRECT) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub struct FLTCLK_R(crate::FieldReader); +impl FLTCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTCLK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLTCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub struct FLTCLK_W<'a> { + w: &'a mut W, +} +impl<'a> FLTCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub struct INVINP_R(crate::FieldReader); +impl INVINP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVINP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVINP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub struct INVINP_W<'a> { + w: &'a mut W, +} +impl<'a> INVINP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub struct IEWO_R(crate::FieldReader); +impl IEWO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IEWO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IEWO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub struct IEWO_W<'a> { + w: &'a mut W, +} +impl<'a> IEWO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub struct OPENDRN_R(crate::FieldReader); +impl OPENDRN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPENDRN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPENDRN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub struct OPENDRN_W<'a> { + w: &'a mut W, +} +impl<'a> OPENDRN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub struct INVOUT_R(crate::FieldReader); +impl INVOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub struct INVOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INVOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub struct PLEVEL_R(crate::FieldReader); +impl PLEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub struct PLEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> PLEVEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub struct PEN_R(crate::FieldReader); +impl PEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub struct PEN_W<'a> { + w: &'a mut W, +} +impl<'a> PEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub struct PWOA_R(crate::FieldReader); +impl PWOA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PWOA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PWOA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub struct PWOA_W<'a> { + w: &'a mut W, +} +impl<'a> PWOA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub struct FUNSEL_R(crate::FieldReader); +impl FUNSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FUNSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FUNSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub struct FUNSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FUNSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub struct IODIS_R(crate::FieldReader); +impl IODIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IODIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IODIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub struct IODIS_W<'a> { + w: &'a mut W, +} +impl<'a> IODIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FLTTYPE_R { + FLTTYPE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FLTCLK_R { + FLTCLK_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> INVINP_R { + INVINP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IEWO_R { + IEWO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OPENDRN_R { + OPENDRN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> INVOUT_R { + INVOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PLEVEL_R { + PLEVEL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PWOA_R { + PWOA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FUNSEL_R { + FUNSEL_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IODIS_R { + IODIS_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&mut self) -> FLTTYPE_W { + FLTTYPE_W { w: self } + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&mut self) -> FLTCLK_W { + FLTCLK_W { w: self } + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&mut self) -> INVINP_W { + INVINP_W { w: self } + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&mut self) -> IEWO_W { + IEWO_W { w: self } + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&mut self) -> OPENDRN_W { + OPENDRN_W { w: self } + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&mut self) -> INVOUT_W { + INVOUT_W { w: self } + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&mut self) -> PLEVEL_W { + PLEVEL_W { w: self } + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&mut self) -> PEN_W { + PEN_W { w: self } + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&mut self) -> PWOA_W { + PWOA_W { w: self } + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&mut self) -> FUNSEL_W { + FUNSEL_W { w: self } + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&mut self) -> IODIS_W { + IODIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PORTE Pin Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [porte](index.html) module"] +pub struct PORTE_SPEC; +impl crate::RegisterSpec for PORTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [porte::R](R) reader structure"] +impl crate::Readable for PORTE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [porte::W](W) writer structure"] +impl crate::Writable for PORTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PORTE[%s] +to value 0"] +impl crate::Resettable for PORTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/portf.rs b/src/ioconfig/portf.rs new file mode 100644 index 0000000..2eb8b43 --- /dev/null +++ b/src/ioconfig/portf.rs @@ -0,0 +1,655 @@ +#[doc = "Register `PORTF[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PORTF[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLTTYPE_A { + #[doc = "0: Synchronize to system clock"] + SYNC = 0, + #[doc = "1: Direct input, no synchronization"] + DIRECT = 1, + #[doc = "2: Require 2 samples to have the same value"] + FILTER1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + FILTER2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + FILTER3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + FILTER4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLTTYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub struct FLTTYPE_R(crate::FieldReader); +impl FLTTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTTYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLTTYPE_A::SYNC), + 1 => Some(FLTTYPE_A::DIRECT), + 2 => Some(FLTTYPE_A::FILTER1), + 3 => Some(FLTTYPE_A::FILTER2), + 4 => Some(FLTTYPE_A::FILTER3), + 5 => Some(FLTTYPE_A::FILTER4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == FLTTYPE_A::SYNC + } + #[doc = "Checks if the value of the field is `DIRECT`"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + **self == FLTTYPE_A::DIRECT + } + #[doc = "Checks if the value of the field is `FILTER1`"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + **self == FLTTYPE_A::FILTER1 + } + #[doc = "Checks if the value of the field is `FILTER2`"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + **self == FLTTYPE_A::FILTER2 + } + #[doc = "Checks if the value of the field is `FILTER3`"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + **self == FLTTYPE_A::FILTER3 + } + #[doc = "Checks if the value of the field is `FILTER4`"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + **self == FLTTYPE_A::FILTER4 + } +} +impl core::ops::Deref for FLTTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub struct FLTTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> FLTTYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLTTYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(FLTTYPE_A::SYNC) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut W { + self.variant(FLTTYPE_A::DIRECT) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub struct FLTCLK_R(crate::FieldReader); +impl FLTCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTCLK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLTCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub struct FLTCLK_W<'a> { + w: &'a mut W, +} +impl<'a> FLTCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub struct INVINP_R(crate::FieldReader); +impl INVINP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVINP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVINP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub struct INVINP_W<'a> { + w: &'a mut W, +} +impl<'a> INVINP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub struct IEWO_R(crate::FieldReader); +impl IEWO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IEWO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IEWO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub struct IEWO_W<'a> { + w: &'a mut W, +} +impl<'a> IEWO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub struct OPENDRN_R(crate::FieldReader); +impl OPENDRN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPENDRN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPENDRN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub struct OPENDRN_W<'a> { + w: &'a mut W, +} +impl<'a> OPENDRN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub struct INVOUT_R(crate::FieldReader); +impl INVOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub struct INVOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INVOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub struct PLEVEL_R(crate::FieldReader); +impl PLEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub struct PLEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> PLEVEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub struct PEN_R(crate::FieldReader); +impl PEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub struct PEN_W<'a> { + w: &'a mut W, +} +impl<'a> PEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub struct PWOA_R(crate::FieldReader); +impl PWOA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PWOA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PWOA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub struct PWOA_W<'a> { + w: &'a mut W, +} +impl<'a> PWOA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub struct FUNSEL_R(crate::FieldReader); +impl FUNSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FUNSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FUNSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub struct FUNSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FUNSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub struct IODIS_R(crate::FieldReader); +impl IODIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IODIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IODIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub struct IODIS_W<'a> { + w: &'a mut W, +} +impl<'a> IODIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FLTTYPE_R { + FLTTYPE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FLTCLK_R { + FLTCLK_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> INVINP_R { + INVINP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IEWO_R { + IEWO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OPENDRN_R { + OPENDRN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> INVOUT_R { + INVOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PLEVEL_R { + PLEVEL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PWOA_R { + PWOA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FUNSEL_R { + FUNSEL_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IODIS_R { + IODIS_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&mut self) -> FLTTYPE_W { + FLTTYPE_W { w: self } + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&mut self) -> FLTCLK_W { + FLTCLK_W { w: self } + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&mut self) -> INVINP_W { + INVINP_W { w: self } + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&mut self) -> IEWO_W { + IEWO_W { w: self } + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&mut self) -> OPENDRN_W { + OPENDRN_W { w: self } + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&mut self) -> INVOUT_W { + INVOUT_W { w: self } + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&mut self) -> PLEVEL_W { + PLEVEL_W { w: self } + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&mut self) -> PEN_W { + PEN_W { w: self } + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&mut self) -> PWOA_W { + PWOA_W { w: self } + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&mut self) -> FUNSEL_W { + FUNSEL_W { w: self } + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&mut self) -> IODIS_W { + IODIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PORTF Pin Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [portf](index.html) module"] +pub struct PORTF_SPEC; +impl crate::RegisterSpec for PORTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [portf::R](R) reader structure"] +impl crate::Readable for PORTF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [portf::W](W) writer structure"] +impl crate::Writable for PORTF_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PORTF[%s] +to value 0"] +impl crate::Resettable for PORTF_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/ioconfig/portg.rs b/src/ioconfig/portg.rs new file mode 100644 index 0000000..15f9738 --- /dev/null +++ b/src/ioconfig/portg.rs @@ -0,0 +1,655 @@ +#[doc = "Register `PORTG[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PORTG[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FLTTYPE_A { + #[doc = "0: Synchronize to system clock"] + SYNC = 0, + #[doc = "1: Direct input, no synchronization"] + DIRECT = 1, + #[doc = "2: Require 2 samples to have the same value"] + FILTER1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + FILTER2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + FILTER3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + FILTER4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLTTYPE_A) -> Self { + variant as _ + } +} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub struct FLTTYPE_R(crate::FieldReader); +impl FLTTYPE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTTYPE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLTTYPE_A::SYNC), + 1 => Some(FLTTYPE_A::DIRECT), + 2 => Some(FLTTYPE_A::FILTER1), + 3 => Some(FLTTYPE_A::FILTER2), + 4 => Some(FLTTYPE_A::FILTER3), + 5 => Some(FLTTYPE_A::FILTER4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + **self == FLTTYPE_A::SYNC + } + #[doc = "Checks if the value of the field is `DIRECT`"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + **self == FLTTYPE_A::DIRECT + } + #[doc = "Checks if the value of the field is `FILTER1`"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + **self == FLTTYPE_A::FILTER1 + } + #[doc = "Checks if the value of the field is `FILTER2`"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + **self == FLTTYPE_A::FILTER2 + } + #[doc = "Checks if the value of the field is `FILTER3`"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + **self == FLTTYPE_A::FILTER3 + } + #[doc = "Checks if the value of the field is `FILTER4`"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + **self == FLTTYPE_A::FILTER4 + } +} +impl core::ops::Deref for FLTTYPE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub struct FLTTYPE_W<'a> { + w: &'a mut W, +} +impl<'a> FLTTYPE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FLTTYPE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(FLTTYPE_A::SYNC) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut W { + self.variant(FLTTYPE_A::DIRECT) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut W { + self.variant(FLTTYPE_A::FILTER4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub struct FLTCLK_R(crate::FieldReader); +impl FLTCLK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FLTCLK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FLTCLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub struct FLTCLK_W<'a> { + w: &'a mut W, +} +impl<'a> FLTCLK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3); + self.w + } +} +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub struct INVINP_R(crate::FieldReader); +impl INVINP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVINP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVINP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub struct INVINP_W<'a> { + w: &'a mut W, +} +impl<'a> INVINP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub struct IEWO_R(crate::FieldReader); +impl IEWO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IEWO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IEWO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub struct IEWO_W<'a> { + w: &'a mut W, +} +impl<'a> IEWO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub struct OPENDRN_R(crate::FieldReader); +impl OPENDRN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OPENDRN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OPENDRN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub struct OPENDRN_W<'a> { + w: &'a mut W, +} +impl<'a> OPENDRN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub struct INVOUT_R(crate::FieldReader); +impl INVOUT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INVOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INVOUT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub struct INVOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INVOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub struct PLEVEL_R(crate::FieldReader); +impl PLEVEL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PLEVEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLEVEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub struct PLEVEL_W<'a> { + w: &'a mut W, +} +impl<'a> PLEVEL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub struct PEN_R(crate::FieldReader); +impl PEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub struct PEN_W<'a> { + w: &'a mut W, +} +impl<'a> PEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub struct PWOA_R(crate::FieldReader); +impl PWOA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PWOA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PWOA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub struct PWOA_W<'a> { + w: &'a mut W, +} +impl<'a> PWOA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub struct FUNSEL_R(crate::FieldReader); +impl FUNSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FUNSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FUNSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub struct FUNSEL_W<'a> { + w: &'a mut W, +} +impl<'a> FUNSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 13)) | ((value as u32 & 0x07) << 13); + self.w + } +} +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub struct IODIS_R(crate::FieldReader); +impl IODIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IODIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IODIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub struct IODIS_W<'a> { + w: &'a mut W, +} +impl<'a> IODIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FLTTYPE_R { + FLTTYPE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FLTCLK_R { + FLTCLK_R::new(((self.bits >> 3) & 0x07) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> INVINP_R { + INVINP_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IEWO_R { + IEWO_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OPENDRN_R { + OPENDRN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> INVOUT_R { + INVOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PLEVEL_R { + PLEVEL_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PWOA_R { + PWOA_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FUNSEL_R { + FUNSEL_R::new(((self.bits >> 13) & 0x07) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IODIS_R { + IODIS_R::new(((self.bits >> 16) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&mut self) -> FLTTYPE_W { + FLTTYPE_W { w: self } + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&mut self) -> FLTCLK_W { + FLTCLK_W { w: self } + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&mut self) -> INVINP_W { + INVINP_W { w: self } + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&mut self) -> IEWO_W { + IEWO_W { w: self } + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&mut self) -> OPENDRN_W { + OPENDRN_W { w: self } + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&mut self) -> INVOUT_W { + INVOUT_W { w: self } + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&mut self) -> PLEVEL_W { + PLEVEL_W { w: self } + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&mut self) -> PEN_W { + PEN_W { w: self } + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&mut self) -> PWOA_W { + PWOA_W { w: self } + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&mut self) -> FUNSEL_W { + FUNSEL_W { w: self } + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&mut self) -> IODIS_W { + IODIS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PORTG Pin Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [portg](index.html) module"] +pub struct PORTG_SPEC; +impl crate::RegisterSpec for PORTG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [portg::R](R) reader structure"] +impl crate::Readable for PORTG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [portg::W](W) writer structure"] +impl crate::Writable for PORTG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PORTG[%s] +to value 0"] +impl crate::Resettable for PORTG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/irq_router.rs b/src/irq_router.rs new file mode 100644 index 0000000..08f5fd0 --- /dev/null +++ b/src/irq_router.rs @@ -0,0 +1,95 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt select for DMA channel 0"] + pub dmasel0: crate::Reg, + #[doc = "0x04 - Interrupt select for DMA channel 1"] + pub dmasel1: crate::Reg, + #[doc = "0x08 - Interrupt select for DMA channel 2"] + pub dmasel2: crate::Reg, + #[doc = "0x0c - Interrupt select for DMA channel 3"] + pub dmasel3: crate::Reg, + #[doc = "0x10 - Trigger select for the DMA channels"] + pub dmattsel: crate::Reg, + #[doc = "0x14 - Interrupt select for ADC"] + pub adcsel: crate::Reg, + #[doc = "0x18 - Interrupt select for DAC0"] + pub dacsel0: crate::Reg, + #[doc = "0x1c - Interrupt select for DAC1"] + pub dacsel1: crate::Reg, + #[doc = "0x20 - DEBUG IRQ_OUT\\[31:0\\]"] + pub irq_out0: crate::Reg, + #[doc = "0x24 - DEBUG IRQ_OUT\\[63:32\\]"] + pub irq_out1: crate::Reg, + #[doc = "0x28 - DEBUG IRQ_OUT\\[95:64\\]"] + pub irq_out2: crate::Reg, + #[doc = "0x2c - DEBUG IRQ_OUT\\[127:96\\]"] + pub irq_out3: crate::Reg, + #[doc = "0x30 - DEBUG IRQ_OUT\\[159:128\\]"] + pub irq_out4: crate::Reg, + #[doc = "0x34 - DEBUG IRQ_OUT\\[179:160\\]"] + pub irq_out5: crate::Reg, + _reserved14: [u8; 0x0fc4], + #[doc = "0xffc - Peripheral ID Register"] + pub perid: crate::Reg, +} +#[doc = "DMASEL0 register accessor: an alias for `Reg`"] +pub type DMASEL0 = crate::Reg; +#[doc = "Interrupt select for DMA channel 0"] +pub mod dmasel0; +#[doc = "DMASEL1 register accessor: an alias for `Reg`"] +pub type DMASEL1 = crate::Reg; +#[doc = "Interrupt select for DMA channel 1"] +pub mod dmasel1; +#[doc = "DMASEL2 register accessor: an alias for `Reg`"] +pub type DMASEL2 = crate::Reg; +#[doc = "Interrupt select for DMA channel 2"] +pub mod dmasel2; +#[doc = "DMASEL3 register accessor: an alias for `Reg`"] +pub type DMASEL3 = crate::Reg; +#[doc = "Interrupt select for DMA channel 3"] +pub mod dmasel3; +#[doc = "DMATTSEL register accessor: an alias for `Reg`"] +pub type DMATTSEL = crate::Reg; +#[doc = "Trigger select for the DMA channels"] +pub mod dmattsel; +#[doc = "ADCSEL register accessor: an alias for `Reg`"] +pub type ADCSEL = crate::Reg; +#[doc = "Interrupt select for ADC"] +pub mod adcsel; +#[doc = "DACSEL0 register accessor: an alias for `Reg`"] +pub type DACSEL0 = crate::Reg; +#[doc = "Interrupt select for DAC0"] +pub mod dacsel0; +#[doc = "DACSEL1 register accessor: an alias for `Reg`"] +pub type DACSEL1 = crate::Reg; +#[doc = "Interrupt select for DAC1"] +pub mod dacsel1; +#[doc = "IRQ_OUT0 register accessor: an alias for `Reg`"] +pub type IRQ_OUT0 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[31:0\\]"] +pub mod irq_out0; +#[doc = "IRQ_OUT1 register accessor: an alias for `Reg`"] +pub type IRQ_OUT1 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[63:32\\]"] +pub mod irq_out1; +#[doc = "IRQ_OUT2 register accessor: an alias for `Reg`"] +pub type IRQ_OUT2 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[95:64\\]"] +pub mod irq_out2; +#[doc = "IRQ_OUT3 register accessor: an alias for `Reg`"] +pub type IRQ_OUT3 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[127:96\\]"] +pub mod irq_out3; +#[doc = "IRQ_OUT4 register accessor: an alias for `Reg`"] +pub type IRQ_OUT4 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[159:128\\]"] +pub mod irq_out4; +#[doc = "IRQ_OUT5 register accessor: an alias for `Reg`"] +pub type IRQ_OUT5 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[179:160\\]"] +pub mod irq_out5; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/irq_router/adcsel.rs b/src/irq_router/adcsel.rs new file mode 100644 index 0000000..7aa1356 --- /dev/null +++ b/src/irq_router/adcsel.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ADCSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADCSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADCSEL` reader - ADC trigger source selection value"] +pub struct ADCSEL_R(crate::FieldReader); +impl ADCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADCSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADCSEL` writer - ADC trigger source selection value"] +pub struct ADCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> ADCSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - ADC trigger source selection value"] + #[inline(always)] + pub fn adcsel(&self) -> ADCSEL_R { + ADCSEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - ADC trigger source selection value"] + #[inline(always)] + pub fn adcsel(&mut self) -> ADCSEL_W { + ADCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt select for ADC\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcsel](index.html) module"] +pub struct ADCSEL_SPEC; +impl crate::RegisterSpec for ADCSEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [adcsel::R](R) reader structure"] +impl crate::Readable for ADCSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [adcsel::W](W) writer structure"] +impl crate::Writable for ADCSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADCSEL to value 0x1f"] +impl crate::Resettable for ADCSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1f + } +} diff --git a/src/irq_router/dacsel0.rs b/src/irq_router/dacsel0.rs new file mode 100644 index 0000000..4a247d7 --- /dev/null +++ b/src/irq_router/dacsel0.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DACSEL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DACSEL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DACSEL` reader - DAC trigger source selection value"] +pub struct DACSEL_R(crate::FieldReader); +impl DACSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DACSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DACSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DACSEL` writer - DAC trigger source selection value"] +pub struct DACSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DACSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&self) -> DACSEL_R { + DACSEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&mut self) -> DACSEL_W { + DACSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt select for DAC0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dacsel0](index.html) module"] +pub struct DACSEL0_SPEC; +impl crate::RegisterSpec for DACSEL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dacsel0::R](R) reader structure"] +impl crate::Readable for DACSEL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dacsel0::W](W) writer structure"] +impl crate::Writable for DACSEL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DACSEL0 to value 0x1f"] +impl crate::Resettable for DACSEL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1f + } +} diff --git a/src/irq_router/dacsel1.rs b/src/irq_router/dacsel1.rs new file mode 100644 index 0000000..4c86e57 --- /dev/null +++ b/src/irq_router/dacsel1.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DACSEL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DACSEL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DACSEL` reader - DAC trigger source selection value"] +pub struct DACSEL_R(crate::FieldReader); +impl DACSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DACSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DACSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DACSEL` writer - DAC trigger source selection value"] +pub struct DACSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DACSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f); + self.w + } +} +impl R { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&self) -> DACSEL_R { + DACSEL_R::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&mut self) -> DACSEL_W { + DACSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt select for DAC1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dacsel1](index.html) module"] +pub struct DACSEL1_SPEC; +impl crate::RegisterSpec for DACSEL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dacsel1::R](R) reader structure"] +impl crate::Readable for DACSEL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dacsel1::W](W) writer structure"] +impl crate::Writable for DACSEL1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DACSEL1 to value 0x1f"] +impl crate::Resettable for DACSEL1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1f + } +} diff --git a/src/irq_router/dmasel0.rs b/src/irq_router/dmasel0.rs new file mode 100644 index 0000000..fd464df --- /dev/null +++ b/src/irq_router/dmasel0.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMASEL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMASEL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub struct DMASEL_R(crate::FieldReader); +impl DMASEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DMASEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMASEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub struct DMASEL_W<'a> { + w: &'a mut W, +} +impl<'a> DMASEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DMASEL_R { + DMASEL_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&mut self) -> DMASEL_W { + DMASEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt select for DMA channel 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmasel0](index.html) module"] +pub struct DMASEL0_SPEC; +impl crate::RegisterSpec for DMASEL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmasel0::R](R) reader structure"] +impl crate::Readable for DMASEL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmasel0::W](W) writer structure"] +impl crate::Writable for DMASEL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMASEL0 to value 0x7f"] +impl crate::Resettable for DMASEL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/src/irq_router/dmasel1.rs b/src/irq_router/dmasel1.rs new file mode 100644 index 0000000..e3ce3aa --- /dev/null +++ b/src/irq_router/dmasel1.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMASEL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMASEL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub struct DMASEL_R(crate::FieldReader); +impl DMASEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DMASEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMASEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub struct DMASEL_W<'a> { + w: &'a mut W, +} +impl<'a> DMASEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DMASEL_R { + DMASEL_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&mut self) -> DMASEL_W { + DMASEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt select for DMA channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmasel1](index.html) module"] +pub struct DMASEL1_SPEC; +impl crate::RegisterSpec for DMASEL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmasel1::R](R) reader structure"] +impl crate::Readable for DMASEL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmasel1::W](W) writer structure"] +impl crate::Writable for DMASEL1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMASEL1 to value 0x7f"] +impl crate::Resettable for DMASEL1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/src/irq_router/dmasel2.rs b/src/irq_router/dmasel2.rs new file mode 100644 index 0000000..d3467bd --- /dev/null +++ b/src/irq_router/dmasel2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMASEL2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMASEL2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub struct DMASEL_R(crate::FieldReader); +impl DMASEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DMASEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMASEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub struct DMASEL_W<'a> { + w: &'a mut W, +} +impl<'a> DMASEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DMASEL_R { + DMASEL_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&mut self) -> DMASEL_W { + DMASEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt select for DMA channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmasel2](index.html) module"] +pub struct DMASEL2_SPEC; +impl crate::RegisterSpec for DMASEL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmasel2::R](R) reader structure"] +impl crate::Readable for DMASEL2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmasel2::W](W) writer structure"] +impl crate::Writable for DMASEL2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMASEL2 to value 0x7f"] +impl crate::Resettable for DMASEL2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/src/irq_router/dmasel3.rs b/src/irq_router/dmasel3.rs new file mode 100644 index 0000000..99561c4 --- /dev/null +++ b/src/irq_router/dmasel3.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMASEL3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMASEL3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub struct DMASEL_R(crate::FieldReader); +impl DMASEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DMASEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMASEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub struct DMASEL_W<'a> { + w: &'a mut W, +} +impl<'a> DMASEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x7f) | (value as u32 & 0x7f); + self.w + } +} +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DMASEL_R { + DMASEL_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&mut self) -> DMASEL_W { + DMASEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt select for DMA channel 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmasel3](index.html) module"] +pub struct DMASEL3_SPEC; +impl crate::RegisterSpec for DMASEL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmasel3::R](R) reader structure"] +impl crate::Readable for DMASEL3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmasel3::W](W) writer structure"] +impl crate::Writable for DMASEL3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMASEL3 to value 0x7f"] +impl crate::Resettable for DMASEL3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f + } +} diff --git a/src/irq_router/dmattsel.rs b/src/irq_router/dmattsel.rs new file mode 100644 index 0000000..43ad69a --- /dev/null +++ b/src/irq_router/dmattsel.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMATTSEL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMATTSEL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DMATTSEL` reader - DMA trigger type selection value"] +pub struct DMATTSEL_R(crate::FieldReader); +impl DMATTSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DMATTSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMATTSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMATTSEL` writer - DMA trigger type selection value"] +pub struct DMATTSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DMATTSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - DMA trigger type selection value"] + #[inline(always)] + pub fn dmattsel(&self) -> DMATTSEL_R { + DMATTSEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - DMA trigger type selection value"] + #[inline(always)] + pub fn dmattsel(&mut self) -> DMATTSEL_W { + DMATTSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Trigger select for the DMA channels\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmattsel](index.html) module"] +pub struct DMATTSEL_SPEC; +impl crate::RegisterSpec for DMATTSEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmattsel::R](R) reader structure"] +impl crate::Readable for DMATTSEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmattsel::W](W) writer structure"] +impl crate::Writable for DMATTSEL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMATTSEL to value 0"] +impl crate::Resettable for DMATTSEL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/irq_router/irq_out0.rs b/src/irq_router/irq_out0.rs new file mode 100644 index 0000000..330018b --- /dev/null +++ b/src/irq_router/irq_out0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `IRQ_OUT0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IRQ_OUT0` reader - IRQ_OUT\\[31:0\\]"] +pub struct IRQ_OUT0_R(crate::FieldReader); +impl IRQ_OUT0_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + IRQ_OUT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_OUT0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[31:0\\]"] + #[inline(always)] + pub fn irq_out0(&self) -> IRQ_OUT0_R { + IRQ_OUT0_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "DEBUG IRQ_OUT\\[31:0\\]\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_out0](index.html) module"] +pub struct IRQ_OUT0_SPEC; +impl crate::RegisterSpec for IRQ_OUT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_out0::R](R) reader structure"] +impl crate::Readable for IRQ_OUT0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_OUT0 to value 0"] +impl crate::Resettable for IRQ_OUT0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/irq_router/irq_out1.rs b/src/irq_router/irq_out1.rs new file mode 100644 index 0000000..582168d --- /dev/null +++ b/src/irq_router/irq_out1.rs @@ -0,0 +1,53 @@ +#[doc = "Register `IRQ_OUT1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IRQ_OUT1` reader - IRQ_OUT\\[63:32\\]"] +pub struct IRQ_OUT1_R(crate::FieldReader); +impl IRQ_OUT1_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + IRQ_OUT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_OUT1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[63:32\\]"] + #[inline(always)] + pub fn irq_out1(&self) -> IRQ_OUT1_R { + IRQ_OUT1_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "DEBUG IRQ_OUT\\[63:32\\]\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_out1](index.html) module"] +pub struct IRQ_OUT1_SPEC; +impl crate::RegisterSpec for IRQ_OUT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_out1::R](R) reader structure"] +impl crate::Readable for IRQ_OUT1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_OUT1 to value 0"] +impl crate::Resettable for IRQ_OUT1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/irq_router/irq_out2.rs b/src/irq_router/irq_out2.rs new file mode 100644 index 0000000..a374056 --- /dev/null +++ b/src/irq_router/irq_out2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `IRQ_OUT2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IRQ_OUT2` reader - IRQ_OUT\\[95:64\\]"] +pub struct IRQ_OUT2_R(crate::FieldReader); +impl IRQ_OUT2_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + IRQ_OUT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_OUT2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[95:64\\]"] + #[inline(always)] + pub fn irq_out2(&self) -> IRQ_OUT2_R { + IRQ_OUT2_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "DEBUG IRQ_OUT\\[95:64\\]\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_out2](index.html) module"] +pub struct IRQ_OUT2_SPEC; +impl crate::RegisterSpec for IRQ_OUT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_out2::R](R) reader structure"] +impl crate::Readable for IRQ_OUT2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_OUT2 to value 0"] +impl crate::Resettable for IRQ_OUT2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/irq_router/irq_out3.rs b/src/irq_router/irq_out3.rs new file mode 100644 index 0000000..997ac2c --- /dev/null +++ b/src/irq_router/irq_out3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `IRQ_OUT3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IRQ_OUT3` reader - IRQ_OUT\\[127:96\\]"] +pub struct IRQ_OUT3_R(crate::FieldReader); +impl IRQ_OUT3_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + IRQ_OUT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_OUT3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[127:96\\]"] + #[inline(always)] + pub fn irq_out3(&self) -> IRQ_OUT3_R { + IRQ_OUT3_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "DEBUG IRQ_OUT\\[127:96\\]\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_out3](index.html) module"] +pub struct IRQ_OUT3_SPEC; +impl crate::RegisterSpec for IRQ_OUT3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_out3::R](R) reader structure"] +impl crate::Readable for IRQ_OUT3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_OUT3 to value 0"] +impl crate::Resettable for IRQ_OUT3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/irq_router/irq_out4.rs b/src/irq_router/irq_out4.rs new file mode 100644 index 0000000..0717f38 --- /dev/null +++ b/src/irq_router/irq_out4.rs @@ -0,0 +1,53 @@ +#[doc = "Register `IRQ_OUT4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IRQ_OUT4` reader - IRQ_OUT\\[159:128\\]"] +pub struct IRQ_OUT4_R(crate::FieldReader); +impl IRQ_OUT4_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + IRQ_OUT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_OUT4_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[159:128\\]"] + #[inline(always)] + pub fn irq_out4(&self) -> IRQ_OUT4_R { + IRQ_OUT4_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "DEBUG IRQ_OUT\\[159:128\\]\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_out4](index.html) module"] +pub struct IRQ_OUT4_SPEC; +impl crate::RegisterSpec for IRQ_OUT4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_out4::R](R) reader structure"] +impl crate::Readable for IRQ_OUT4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_OUT4 to value 0"] +impl crate::Resettable for IRQ_OUT4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/irq_router/irq_out5.rs b/src/irq_router/irq_out5.rs new file mode 100644 index 0000000..2af1424 --- /dev/null +++ b/src/irq_router/irq_out5.rs @@ -0,0 +1,53 @@ +#[doc = "Register `IRQ_OUT5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IRQ_OUT5` reader - IRQ_OUT\\[179:160\\]"] +pub struct IRQ_OUT5_R(crate::FieldReader); +impl IRQ_OUT5_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + IRQ_OUT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_OUT5_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:19 - IRQ_OUT\\[179:160\\]"] + #[inline(always)] + pub fn irq_out5(&self) -> IRQ_OUT5_R { + IRQ_OUT5_R::new((self.bits & 0x000f_ffff) as u32) + } +} +#[doc = "DEBUG IRQ_OUT\\[179:160\\]\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_out5](index.html) module"] +pub struct IRQ_OUT5_SPEC; +impl crate::RegisterSpec for IRQ_OUT5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_out5::R](R) reader structure"] +impl crate::Readable for IRQ_OUT5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_OUT5 to value 0"] +impl crate::Resettable for IRQ_OUT5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/irq_router/perid.rs b/src/irq_router/perid.rs new file mode 100644 index 0000000..7c79c88 --- /dev/null +++ b/src/irq_router/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0281_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0281_07e9 + } +} diff --git a/src/lib.rs b/src/lib.rs index 1b4a90c..e877b67 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,8 +1,2759 @@ -#[cfg(test)] -mod tests { - #[test] - fn it_works() { - let result = 2 + 2; - assert_eq!(result, 4); +#![doc = "Peripheral access API for VA416XX microcontrollers (generated using svd2rust v0.19.0 (877196f 2021-11-14))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(const_err)] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 4; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn U0(); + fn U1(); + fn U2(); + fn U3(); + fn U4(); + fn U5(); + fn U6(); + fn U7(); + fn U8(); + fn U9(); + fn U10(); + fn U11(); + fn U12(); + fn U13(); + fn U14(); + fn U15(); + fn SPI0_TX(); + fn SPI0_RX(); + fn SPI1_TX(); + fn SPI1_RX(); + fn SPI2_TX(); + fn SPI2_RX(); + fn SPI3_TX(); + fn SPI3_RX(); + fn UART0_TX(); + fn UART0_RX(); + fn UART1_TX(); + fn UART1_RX(); + fn UART2_TX(); + fn UART2_RX(); + fn I2C0_MS(); + fn I2C0_SL(); + fn I2C1_MS(); + fn I2C1_SL(); + fn I2C2_MS(); + fn I2C2_SL(); + fn ETHERNET(); + fn U37(); + fn SPW(); + fn U39(); + fn DAC0(); + fn DAC1(); + fn TRNG(); + fn DMA_ERROR(); + fn ADC(); + fn LOCLK(); + fn LVD(); + fn WATCHDOG(); + fn TIM0(); + fn TIM1(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8(); + fn TIM9(); + fn TIM10(); + fn TIM11(); + fn TIM12(); + fn TIM13(); + fn TIM14(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM18(); + fn TIM19(); + fn TIM20(); + fn TIM21(); + fn TIM22(); + fn TIM23(); + fn CAN0(); + fn U73(); + fn CAN1(); + fn U75(); + fn EDAC_MBE(); + fn EDAC_SBE(); + fn PORTA0(); + fn PORTA1(); + fn PORTA2(); + fn PORTA3(); + fn PORTA4(); + fn PORTA5(); + fn PORTA6(); + fn PORTA7(); + fn PORTA8(); + fn PORTA9(); + fn PORTA10(); + fn PORTA11(); + fn PORTA12(); + fn PORTA13(); + fn PORTA14(); + fn PORTA15(); + fn PORTB0(); + fn PORTB1(); + fn PORTB2(); + fn PORTB3(); + fn PORTB4(); + fn PORTB5(); + fn PORTB6(); + fn PORTB7(); + fn PORTB8(); + fn PORTB9(); + fn PORTB10(); + fn PORTB11(); + fn PORTB12(); + fn PORTB13(); + fn PORTB14(); + fn PORTB15(); + fn PORTC0(); + fn PORTC1(); + fn PORTC2(); + fn PORTC3(); + fn PORTC4(); + fn PORTC5(); + fn PORTC6(); + fn PORTC7(); + fn PORTC8(); + fn PORTC9(); + fn PORTC10(); + fn PORTC11(); + fn PORTC12(); + fn PORTC13(); + fn PORTC14(); + fn PORTC15(); + fn PORTD0(); + fn PORTD1(); + fn PORTD2(); + fn PORTD3(); + fn PORTD4(); + fn PORTD5(); + fn PORTD6(); + fn PORTD7(); + fn PORTD8(); + fn PORTD9(); + fn PORTD10(); + fn PORTD11(); + fn PORTD12(); + fn PORTD13(); + fn PORTD14(); + fn PORTD15(); + fn PORTE0(); + fn PORTE1(); + fn PORTE2(); + fn PORTE3(); + fn PORTE4(); + fn PORTE5(); + fn PORTE6(); + fn PORTE7(); + fn PORTE8(); + fn PORTE9(); + fn PORTE10(); + fn PORTE11(); + fn PORTE12(); + fn PORTE13(); + fn PORTE14(); + fn PORTE15(); + fn PORTF0(); + fn PORTF1(); + fn PORTF2(); + fn PORTF3(); + fn PORTF4(); + fn PORTF5(); + fn PORTF6(); + fn PORTF7(); + fn PORTF8(); + fn PORTF9(); + fn PORTF10(); + fn PORTF11(); + fn PORTF12(); + fn PORTF13(); + fn PORTF14(); + fn PORTF15(); + fn DMA_ACTIVE0(); + fn DMA_ACTIVE1(); + fn DMA_ACTIVE2(); + fn DMA_ACTIVE3(); + fn DMA_DONE0(); + fn DMA_DONE1(); + fn DMA_DONE2(); + fn DMA_DONE3(); + fn I2C0_MS_RX(); + fn I2C0_MS_TX(); + fn I2C0_SL_RX(); + fn I2C0_SL_TX(); + fn I2C1_MS_RX(); + fn I2C1_MS_TX(); + fn I2C1_SL_RX(); + fn I2C1_SL_TX(); + fn I2C2_MS_RX(); + fn I2C2_MS_TX(); + fn I2C2_SL_RX(); + fn I2C2_SL_TX(); + fn FPU(); + fn TXEV(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 196] = [ + Vector { _handler: U0 }, + Vector { _handler: U1 }, + Vector { _handler: U2 }, + Vector { _handler: U3 }, + Vector { _handler: U4 }, + Vector { _handler: U5 }, + Vector { _handler: U6 }, + Vector { _handler: U7 }, + Vector { _handler: U8 }, + Vector { _handler: U9 }, + Vector { _handler: U10 }, + Vector { _handler: U11 }, + Vector { _handler: U12 }, + Vector { _handler: U13 }, + Vector { _handler: U14 }, + Vector { _handler: U15 }, + Vector { _handler: SPI0_TX }, + Vector { _handler: SPI0_RX }, + Vector { _handler: SPI1_TX }, + Vector { _handler: SPI1_RX }, + Vector { _handler: SPI2_TX }, + Vector { _handler: SPI2_RX }, + Vector { _handler: SPI3_TX }, + Vector { _handler: SPI3_RX }, + Vector { _handler: UART0_TX }, + Vector { _handler: UART0_RX }, + Vector { _handler: UART1_TX }, + Vector { _handler: UART1_RX }, + Vector { _handler: UART2_TX }, + Vector { _handler: UART2_RX }, + Vector { _handler: I2C0_MS }, + Vector { _handler: I2C0_SL }, + Vector { _handler: I2C1_MS }, + Vector { _handler: I2C1_SL }, + Vector { _handler: I2C2_MS }, + Vector { _handler: I2C2_SL }, + Vector { _handler: ETHERNET }, + Vector { _handler: U37 }, + Vector { _handler: SPW }, + Vector { _handler: U39 }, + Vector { _handler: DAC0 }, + Vector { _handler: DAC1 }, + Vector { _handler: TRNG }, + Vector { + _handler: DMA_ERROR, + }, + Vector { _handler: ADC }, + Vector { _handler: LOCLK }, + Vector { _handler: LVD }, + Vector { _handler: WATCHDOG }, + Vector { _handler: TIM0 }, + Vector { _handler: TIM1 }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: TIM5 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { _handler: TIM8 }, + Vector { _handler: TIM9 }, + Vector { _handler: TIM10 }, + Vector { _handler: TIM11 }, + Vector { _handler: TIM12 }, + Vector { _handler: TIM13 }, + Vector { _handler: TIM14 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { _handler: TIM18 }, + Vector { _handler: TIM19 }, + Vector { _handler: TIM20 }, + Vector { _handler: TIM21 }, + Vector { _handler: TIM22 }, + Vector { _handler: TIM23 }, + Vector { _handler: CAN0 }, + Vector { _handler: U73 }, + Vector { _handler: CAN1 }, + Vector { _handler: U75 }, + Vector { _handler: EDAC_MBE }, + Vector { _handler: EDAC_SBE }, + Vector { _handler: PORTA0 }, + Vector { _handler: PORTA1 }, + Vector { _handler: PORTA2 }, + Vector { _handler: PORTA3 }, + Vector { _handler: PORTA4 }, + Vector { _handler: PORTA5 }, + Vector { _handler: PORTA6 }, + Vector { _handler: PORTA7 }, + Vector { _handler: PORTA8 }, + Vector { _handler: PORTA9 }, + Vector { _handler: PORTA10 }, + Vector { _handler: PORTA11 }, + Vector { _handler: PORTA12 }, + Vector { _handler: PORTA13 }, + Vector { _handler: PORTA14 }, + Vector { _handler: PORTA15 }, + Vector { _handler: PORTB0 }, + Vector { _handler: PORTB1 }, + Vector { _handler: PORTB2 }, + Vector { _handler: PORTB3 }, + Vector { _handler: PORTB4 }, + Vector { _handler: PORTB5 }, + Vector { _handler: PORTB6 }, + Vector { _handler: PORTB7 }, + Vector { _handler: PORTB8 }, + Vector { _handler: PORTB9 }, + Vector { _handler: PORTB10 }, + Vector { _handler: PORTB11 }, + Vector { _handler: PORTB12 }, + Vector { _handler: PORTB13 }, + Vector { _handler: PORTB14 }, + Vector { _handler: PORTB15 }, + Vector { _handler: PORTC0 }, + Vector { _handler: PORTC1 }, + Vector { _handler: PORTC2 }, + Vector { _handler: PORTC3 }, + Vector { _handler: PORTC4 }, + Vector { _handler: PORTC5 }, + Vector { _handler: PORTC6 }, + Vector { _handler: PORTC7 }, + Vector { _handler: PORTC8 }, + Vector { _handler: PORTC9 }, + Vector { _handler: PORTC10 }, + Vector { _handler: PORTC11 }, + Vector { _handler: PORTC12 }, + Vector { _handler: PORTC13 }, + Vector { _handler: PORTC14 }, + Vector { _handler: PORTC15 }, + Vector { _handler: PORTD0 }, + Vector { _handler: PORTD1 }, + Vector { _handler: PORTD2 }, + Vector { _handler: PORTD3 }, + Vector { _handler: PORTD4 }, + Vector { _handler: PORTD5 }, + Vector { _handler: PORTD6 }, + Vector { _handler: PORTD7 }, + Vector { _handler: PORTD8 }, + Vector { _handler: PORTD9 }, + Vector { _handler: PORTD10 }, + Vector { _handler: PORTD11 }, + Vector { _handler: PORTD12 }, + Vector { _handler: PORTD13 }, + Vector { _handler: PORTD14 }, + Vector { _handler: PORTD15 }, + Vector { _handler: PORTE0 }, + Vector { _handler: PORTE1 }, + Vector { _handler: PORTE2 }, + Vector { _handler: PORTE3 }, + Vector { _handler: PORTE4 }, + Vector { _handler: PORTE5 }, + Vector { _handler: PORTE6 }, + Vector { _handler: PORTE7 }, + Vector { _handler: PORTE8 }, + Vector { _handler: PORTE9 }, + Vector { _handler: PORTE10 }, + Vector { _handler: PORTE11 }, + Vector { _handler: PORTE12 }, + Vector { _handler: PORTE13 }, + Vector { _handler: PORTE14 }, + Vector { _handler: PORTE15 }, + Vector { _handler: PORTF0 }, + Vector { _handler: PORTF1 }, + Vector { _handler: PORTF2 }, + Vector { _handler: PORTF3 }, + Vector { _handler: PORTF4 }, + Vector { _handler: PORTF5 }, + Vector { _handler: PORTF6 }, + Vector { _handler: PORTF7 }, + Vector { _handler: PORTF8 }, + Vector { _handler: PORTF9 }, + Vector { _handler: PORTF10 }, + Vector { _handler: PORTF11 }, + Vector { _handler: PORTF12 }, + Vector { _handler: PORTF13 }, + Vector { _handler: PORTF14 }, + Vector { _handler: PORTF15 }, + Vector { + _handler: DMA_ACTIVE0, + }, + Vector { + _handler: DMA_ACTIVE1, + }, + Vector { + _handler: DMA_ACTIVE2, + }, + Vector { + _handler: DMA_ACTIVE3, + }, + Vector { + _handler: DMA_DONE0, + }, + Vector { + _handler: DMA_DONE1, + }, + Vector { + _handler: DMA_DONE2, + }, + Vector { + _handler: DMA_DONE3, + }, + Vector { + _handler: I2C0_MS_RX, + }, + Vector { + _handler: I2C0_MS_TX, + }, + Vector { + _handler: I2C0_SL_RX, + }, + Vector { + _handler: I2C0_SL_TX, + }, + Vector { + _handler: I2C1_MS_RX, + }, + Vector { + _handler: I2C1_MS_TX, + }, + Vector { + _handler: I2C1_SL_RX, + }, + Vector { + _handler: I2C1_SL_TX, + }, + Vector { + _handler: I2C2_MS_RX, + }, + Vector { + _handler: I2C2_MS_TX, + }, + Vector { + _handler: I2C2_SL_RX, + }, + Vector { + _handler: I2C2_SL_TX, + }, + Vector { _handler: FPU }, + Vector { _handler: TXEV }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - U0"] + U0 = 0, + #[doc = "1 - U1"] + U1 = 1, + #[doc = "2 - U2"] + U2 = 2, + #[doc = "3 - U3"] + U3 = 3, + #[doc = "4 - U4"] + U4 = 4, + #[doc = "5 - U5"] + U5 = 5, + #[doc = "6 - U6"] + U6 = 6, + #[doc = "7 - U7"] + U7 = 7, + #[doc = "8 - U8"] + U8 = 8, + #[doc = "9 - U9"] + U9 = 9, + #[doc = "10 - U10"] + U10 = 10, + #[doc = "11 - U11"] + U11 = 11, + #[doc = "12 - U12"] + U12 = 12, + #[doc = "13 - U13"] + U13 = 13, + #[doc = "14 - U14"] + U14 = 14, + #[doc = "15 - U15"] + U15 = 15, + #[doc = "16 - SPI0_TX"] + SPI0_TX = 16, + #[doc = "17 - SPI0_RX"] + SPI0_RX = 17, + #[doc = "18 - SPI1_TX"] + SPI1_TX = 18, + #[doc = "19 - SPI1_RX"] + SPI1_RX = 19, + #[doc = "20 - SPI2_TX"] + SPI2_TX = 20, + #[doc = "21 - SPI2_RX"] + SPI2_RX = 21, + #[doc = "22 - SPI3_TX"] + SPI3_TX = 22, + #[doc = "23 - SPI3_RX"] + SPI3_RX = 23, + #[doc = "24 - UART0_TX"] + UART0_TX = 24, + #[doc = "25 - UART0_RX"] + UART0_RX = 25, + #[doc = "26 - UART1_TX"] + UART1_TX = 26, + #[doc = "27 - UART1_RX"] + UART1_RX = 27, + #[doc = "28 - UART2_TX"] + UART2_TX = 28, + #[doc = "29 - UART2_RX"] + UART2_RX = 29, + #[doc = "30 - I2C0_MS"] + I2C0_MS = 30, + #[doc = "31 - I2C0_SL"] + I2C0_SL = 31, + #[doc = "32 - I2C1_MS"] + I2C1_MS = 32, + #[doc = "33 - I2C1_SL"] + I2C1_SL = 33, + #[doc = "34 - I2C2_MS"] + I2C2_MS = 34, + #[doc = "35 - I2C2_SL"] + I2C2_SL = 35, + #[doc = "36 - Ethernet"] + ETHERNET = 36, + #[doc = "37 - U37"] + U37 = 37, + #[doc = "38 - SpW"] + SPW = 38, + #[doc = "39 - U39"] + U39 = 39, + #[doc = "40 - DAC0"] + DAC0 = 40, + #[doc = "41 - DAC1"] + DAC1 = 41, + #[doc = "42 - TRNG"] + TRNG = 42, + #[doc = "43 - DMA_ERROR"] + DMA_ERROR = 43, + #[doc = "44 - ADC"] + ADC = 44, + #[doc = "45 - LoCLK"] + LOCLK = 45, + #[doc = "46 - LVD"] + LVD = 46, + #[doc = "47 - WATCHDOG"] + WATCHDOG = 47, + #[doc = "48 - TIM0"] + TIM0 = 48, + #[doc = "49 - TIM1"] + TIM1 = 49, + #[doc = "50 - TIM2"] + TIM2 = 50, + #[doc = "51 - TIM3"] + TIM3 = 51, + #[doc = "52 - TIM4"] + TIM4 = 52, + #[doc = "53 - TIM5"] + TIM5 = 53, + #[doc = "54 - TIM6"] + TIM6 = 54, + #[doc = "55 - TIM7"] + TIM7 = 55, + #[doc = "56 - TIM8"] + TIM8 = 56, + #[doc = "57 - TIM9"] + TIM9 = 57, + #[doc = "58 - TIM10"] + TIM10 = 58, + #[doc = "59 - TIM11"] + TIM11 = 59, + #[doc = "60 - TIM12"] + TIM12 = 60, + #[doc = "61 - TIM13"] + TIM13 = 61, + #[doc = "62 - TIM14"] + TIM14 = 62, + #[doc = "63 - TIM15"] + TIM15 = 63, + #[doc = "64 - TIM16"] + TIM16 = 64, + #[doc = "65 - TIM17"] + TIM17 = 65, + #[doc = "66 - TIM18"] + TIM18 = 66, + #[doc = "67 - TIM19"] + TIM19 = 67, + #[doc = "68 - TIM20"] + TIM20 = 68, + #[doc = "69 - TIM21"] + TIM21 = 69, + #[doc = "70 - TIM22"] + TIM22 = 70, + #[doc = "71 - TIM23"] + TIM23 = 71, + #[doc = "72 - CAN0"] + CAN0 = 72, + #[doc = "73 - U73"] + U73 = 73, + #[doc = "74 - CAN1"] + CAN1 = 74, + #[doc = "75 - U75"] + U75 = 75, + #[doc = "76 - EDAC_MBE"] + EDAC_MBE = 76, + #[doc = "77 - EDAC_SBE"] + EDAC_SBE = 77, + #[doc = "78 - PORTA0"] + PORTA0 = 78, + #[doc = "79 - PORTA1"] + PORTA1 = 79, + #[doc = "80 - PORTA2"] + PORTA2 = 80, + #[doc = "81 - PORTA3"] + PORTA3 = 81, + #[doc = "82 - PORTA4"] + PORTA4 = 82, + #[doc = "83 - PORTA5"] + PORTA5 = 83, + #[doc = "84 - PORTA6"] + PORTA6 = 84, + #[doc = "85 - PORTA7"] + PORTA7 = 85, + #[doc = "86 - PORTA8"] + PORTA8 = 86, + #[doc = "87 - PORTA9"] + PORTA9 = 87, + #[doc = "88 - PORTA10"] + PORTA10 = 88, + #[doc = "89 - PORTA11"] + PORTA11 = 89, + #[doc = "90 - PORTA12"] + PORTA12 = 90, + #[doc = "91 - PORTA13"] + PORTA13 = 91, + #[doc = "92 - PORTA14"] + PORTA14 = 92, + #[doc = "93 - PORTA15"] + PORTA15 = 93, + #[doc = "94 - PORTB0"] + PORTB0 = 94, + #[doc = "95 - PORTB1"] + PORTB1 = 95, + #[doc = "96 - PORTB2"] + PORTB2 = 96, + #[doc = "97 - PORTB3"] + PORTB3 = 97, + #[doc = "98 - PORTB4"] + PORTB4 = 98, + #[doc = "99 - PORTB5"] + PORTB5 = 99, + #[doc = "100 - PORTB6"] + PORTB6 = 100, + #[doc = "101 - PORTB7"] + PORTB7 = 101, + #[doc = "102 - PORTB8"] + PORTB8 = 102, + #[doc = "103 - PORTB9"] + PORTB9 = 103, + #[doc = "104 - PORTB10"] + PORTB10 = 104, + #[doc = "105 - PORTB11"] + PORTB11 = 105, + #[doc = "106 - PORTB12"] + PORTB12 = 106, + #[doc = "107 - PORTB13"] + PORTB13 = 107, + #[doc = "108 - PORTB14"] + PORTB14 = 108, + #[doc = "109 - PORTB15"] + PORTB15 = 109, + #[doc = "110 - PORTC0"] + PORTC0 = 110, + #[doc = "111 - PORTC1"] + PORTC1 = 111, + #[doc = "112 - PORTC2"] + PORTC2 = 112, + #[doc = "113 - PORTC3"] + PORTC3 = 113, + #[doc = "114 - PORTC4"] + PORTC4 = 114, + #[doc = "115 - PORTC5"] + PORTC5 = 115, + #[doc = "116 - PORTC6"] + PORTC6 = 116, + #[doc = "117 - PORTC7"] + PORTC7 = 117, + #[doc = "118 - PORTC8"] + PORTC8 = 118, + #[doc = "119 - PORTC9"] + PORTC9 = 119, + #[doc = "120 - PORTC10"] + PORTC10 = 120, + #[doc = "121 - PORTC11"] + PORTC11 = 121, + #[doc = "122 - PORTC12"] + PORTC12 = 122, + #[doc = "123 - PORTC13"] + PORTC13 = 123, + #[doc = "124 - PORTC14"] + PORTC14 = 124, + #[doc = "125 - PORTC15"] + PORTC15 = 125, + #[doc = "126 - PORTD0"] + PORTD0 = 126, + #[doc = "127 - PORTD1"] + PORTD1 = 127, + #[doc = "128 - PORTD2"] + PORTD2 = 128, + #[doc = "129 - PORTD3"] + PORTD3 = 129, + #[doc = "130 - PORTD4"] + PORTD4 = 130, + #[doc = "131 - PORTD5"] + PORTD5 = 131, + #[doc = "132 - PORTD6"] + PORTD6 = 132, + #[doc = "133 - PORTD7"] + PORTD7 = 133, + #[doc = "134 - PORTD8"] + PORTD8 = 134, + #[doc = "135 - PORTD9"] + PORTD9 = 135, + #[doc = "136 - PORTD10"] + PORTD10 = 136, + #[doc = "137 - PORTD11"] + PORTD11 = 137, + #[doc = "138 - PORTD12"] + PORTD12 = 138, + #[doc = "139 - PORTD13"] + PORTD13 = 139, + #[doc = "140 - PORTD14"] + PORTD14 = 140, + #[doc = "141 - PORTD15"] + PORTD15 = 141, + #[doc = "142 - PORTE0"] + PORTE0 = 142, + #[doc = "143 - PORTE1"] + PORTE1 = 143, + #[doc = "144 - PORTE2"] + PORTE2 = 144, + #[doc = "145 - PORTE3"] + PORTE3 = 145, + #[doc = "146 - PORTE4"] + PORTE4 = 146, + #[doc = "147 - PORTE5"] + PORTE5 = 147, + #[doc = "148 - PORTE6"] + PORTE6 = 148, + #[doc = "149 - PORTE7"] + PORTE7 = 149, + #[doc = "150 - PORTE8"] + PORTE8 = 150, + #[doc = "151 - PORTE9"] + PORTE9 = 151, + #[doc = "152 - PORTE10"] + PORTE10 = 152, + #[doc = "153 - PORTE11"] + PORTE11 = 153, + #[doc = "154 - PORTE12"] + PORTE12 = 154, + #[doc = "155 - PORTE13"] + PORTE13 = 155, + #[doc = "156 - PORTE14"] + PORTE14 = 156, + #[doc = "157 - PORTE15"] + PORTE15 = 157, + #[doc = "158 - PORTF0"] + PORTF0 = 158, + #[doc = "159 - PORTF1"] + PORTF1 = 159, + #[doc = "160 - PORTF2"] + PORTF2 = 160, + #[doc = "161 - PORTF3"] + PORTF3 = 161, + #[doc = "162 - PORTF4"] + PORTF4 = 162, + #[doc = "163 - PORTF5"] + PORTF5 = 163, + #[doc = "164 - PORTF6"] + PORTF6 = 164, + #[doc = "165 - PORTF7"] + PORTF7 = 165, + #[doc = "166 - PORTF8"] + PORTF8 = 166, + #[doc = "167 - PORTF9"] + PORTF9 = 167, + #[doc = "168 - PORTF10"] + PORTF10 = 168, + #[doc = "169 - PORTF11"] + PORTF11 = 169, + #[doc = "170 - PORTF12"] + PORTF12 = 170, + #[doc = "171 - PORTF13"] + PORTF13 = 171, + #[doc = "172 - PORTF14"] + PORTF14 = 172, + #[doc = "173 - PORTF15"] + PORTF15 = 173, + #[doc = "174 - DMA_ACTIVE0"] + DMA_ACTIVE0 = 174, + #[doc = "175 - DMA_ACTIVE1"] + DMA_ACTIVE1 = 175, + #[doc = "176 - DMA_ACTIVE2"] + DMA_ACTIVE2 = 176, + #[doc = "177 - DMA_ACTIVE3"] + DMA_ACTIVE3 = 177, + #[doc = "178 - DMA_DONE0"] + DMA_DONE0 = 178, + #[doc = "179 - DMA_DONE1"] + DMA_DONE1 = 179, + #[doc = "180 - DMA_DONE2"] + DMA_DONE2 = 180, + #[doc = "181 - DMA_DONE3"] + DMA_DONE3 = 181, + #[doc = "182 - I2C0_MS_RX"] + I2C0_MS_RX = 182, + #[doc = "183 - I2C0_MS_TX"] + I2C0_MS_TX = 183, + #[doc = "184 - I2C0_SL_RX"] + I2C0_SL_RX = 184, + #[doc = "185 - I2C0_SL_TX"] + I2C0_SL_TX = 185, + #[doc = "186 - I2C1_MS_RX"] + I2C1_MS_RX = 186, + #[doc = "187 - I2C1_MS_TX"] + I2C1_MS_TX = 187, + #[doc = "188 - I2C1_SL_RX"] + I2C1_SL_RX = 188, + #[doc = "189 - I2C1_SL_TX"] + I2C1_SL_TX = 189, + #[doc = "190 - I2C2_MS_RX"] + I2C2_MS_RX = 190, + #[doc = "191 - I2C2_MS_TX"] + I2C2_MS_TX = 191, + #[doc = "192 - I2C2_SL_RX"] + I2C2_SL_RX = 192, + #[doc = "193 - I2C2_SL_TX"] + I2C2_SL_TX = 193, + #[doc = "194 - FPU"] + FPU = 194, + #[doc = "195 - TXEV"] + TXEV = 195, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Clock Generation Peripheral"] +pub struct CLKGEN { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CLKGEN {} +impl CLKGEN { + #[doc = r"Pointer to the register block"] + pub const PTR: *const clkgen::RegisterBlock = 0x4000_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clkgen::RegisterBlock { + Self::PTR + } +} +impl Deref for CLKGEN { + type Target = clkgen::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CLKGEN { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKGEN").finish() + } +} +#[doc = "Clock Generation Peripheral"] +pub mod clkgen; +#[doc = "System Configuration Peripheral"] +pub struct SYSCONFIG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSCONFIG {} +impl SYSCONFIG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sysconfig::RegisterBlock = 0x4001_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysconfig::RegisterBlock { + Self::PTR + } +} +impl Deref for SYSCONFIG { + type Target = sysconfig::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSCONFIG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSCONFIG").finish() + } +} +#[doc = "System Configuration Peripheral"] +pub mod sysconfig; +#[doc = "DMA Controller Block"] +pub struct DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMA {} +impl DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dma::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dma::RegisterBlock { + Self::PTR + } +} +impl Deref for DMA { + type Target = dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA").finish() + } +} +#[doc = "DMA Controller Block"] +pub mod dma; +#[doc = "IO Pin Configuration Peripheral"] +pub struct IOCONFIG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IOCONFIG {} +impl IOCONFIG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ioconfig::RegisterBlock = 0x4001_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ioconfig::RegisterBlock { + Self::PTR + } +} +impl Deref for IOCONFIG { + type Target = ioconfig::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IOCONFIG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IOCONFIG").finish() + } +} +#[doc = "IO Pin Configuration Peripheral"] +pub mod ioconfig; +#[doc = "Utility Peripheral"] +pub struct UTILITY { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UTILITY {} +impl UTILITY { + #[doc = r"Pointer to the register block"] + pub const PTR: *const utility::RegisterBlock = 0x4002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const utility::RegisterBlock { + Self::PTR + } +} +impl Deref for UTILITY { + type Target = utility::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UTILITY { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UTILITY").finish() + } +} +#[doc = "Utility Peripheral"] +pub mod utility; +#[doc = "GPIO Peripheral"] +pub struct PORTA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORTA {} +impl PORTA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } +} +impl Deref for PORTA { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORTA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORTA").finish() + } +} +#[doc = "GPIO Peripheral"] +pub mod porta; +#[doc = "GPIO Peripheral"] +pub struct PORTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORTB {} +impl PORTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } +} +impl Deref for PORTB { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORTB").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use porta as portb; +#[doc = "GPIO Peripheral"] +pub struct PORTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORTC {} +impl PORTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } +} +impl Deref for PORTC { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORTC").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use porta as portc; +#[doc = "GPIO Peripheral"] +pub struct PORTD { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORTD {} +impl PORTD { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } +} +impl Deref for PORTD { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORTD { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORTD").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use porta as portd; +#[doc = "GPIO Peripheral"] +pub struct PORTE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORTE {} +impl PORTE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } +} +impl Deref for PORTE { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORTE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORTE").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use porta as porte; +#[doc = "GPIO Peripheral"] +pub struct PORTF { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORTF {} +impl PORTF { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } +} +impl Deref for PORTF { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORTF { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORTF").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use porta as portf; +#[doc = "GPIO Peripheral"] +pub struct PORTG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORTG {} +impl PORTG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } +} +impl Deref for PORTG { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORTG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORTG").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use porta as portg; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM0 {} +impl TIM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM0 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM0").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub mod tim0; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM1 {} +impl TIM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_8400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM1 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM1").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim1; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM2 {} +impl TIM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_8800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM2 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM2").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim2; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM3 {} +impl TIM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_8c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM3 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM3").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim3; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM4 {} +impl TIM4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM4 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM4").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim4; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM5 {} +impl TIM5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_9400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM5 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM5").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim5; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM6 {} +impl TIM6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_9800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM6 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM6").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim6; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM7 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM7 {} +impl TIM7 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_9c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM7 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM7").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim7; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM8 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM8 {} +impl TIM8 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM8 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM8 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM8").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim8; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM9 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM9 {} +impl TIM9 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_a400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM9 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM9 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM9").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim9; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM10 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM10 {} +impl TIM10 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_a800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM10 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM10 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM10").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim10; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM11 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM11 {} +impl TIM11 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_ac00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM11 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM11 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM11").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim11; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM12 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM12 {} +impl TIM12 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM12 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM12 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM12").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim12; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM13 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM13 {} +impl TIM13 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_b400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM13 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM13 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM13").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim13; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM14 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM14 {} +impl TIM14 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_b800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM14 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM14 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM14").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim14; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM15 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM15 {} +impl TIM15 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_bc00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM15 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM15 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM15").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim15; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM16 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM16 {} +impl TIM16 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM16 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM16 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM16").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim16; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM17 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM17 {} +impl TIM17 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_8400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM17 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM17 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM17").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim17; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM18 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM18 {} +impl TIM18 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_8800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM18 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM18 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM18").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim18; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM19 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM19 {} +impl TIM19 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_8c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM19 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM19 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM19").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim19; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM20 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM20 {} +impl TIM20 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM20 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM20 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM20").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim20; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM21 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM21 {} +impl TIM21 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_9400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM21 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM21 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM21").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim21; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM22 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM22 {} +impl TIM22 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_9800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM22 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM22 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM22").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim22; +#[doc = "Timer/Counter Peripheral"] +pub struct TIM23 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIM23 {} +impl TIM23 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_9c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } +} +impl Deref for TIM23 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIM23 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIM23").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use tim0 as tim23; +#[doc = "UART Peripheral"] +pub struct UART0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART0 {} +impl UART0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4002_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART0 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0").finish() + } +} +#[doc = "UART Peripheral"] +pub mod uart0; +#[doc = "UART Peripheral"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4002_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART1 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1").finish() + } +} +#[doc = "UART Peripheral"] +pub use uart0 as uart1; +#[doc = "UART Peripheral"] +pub struct UART2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART2 {} +impl UART2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4001_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } +} +impl Deref for UART2 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART2").finish() + } +} +#[doc = "UART Peripheral"] +pub use uart0 as uart2; +#[doc = "SPI Peripheral"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4001_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI0").finish() + } +} +#[doc = "SPI Peripheral"] +pub mod spi0; +#[doc = "SPI Peripheral"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4001_5400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI1 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI1").finish() + } +} +#[doc = "SPI Peripheral"] +pub use spi0 as spi1; +#[doc = "SPI Peripheral"] +pub struct SPI2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI2 {} +impl SPI2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4001_5800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI2 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI2").finish() + } +} +#[doc = "SPI Peripheral"] +pub use spi0 as spi2; +#[doc = "SPI Peripheral"] +pub struct SPI3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI3 {} +impl SPI3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4001_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } +} +impl Deref for SPI3 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI3").finish() + } +} +#[doc = "SPI Peripheral"] +pub use spi0 as spi3; +#[doc = "I2C Peripheral"] +pub struct I2C0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C0 {} +impl I2C0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4001_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } +} +impl Deref for I2C0 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0").finish() + } +} +#[doc = "I2C Peripheral"] +pub mod i2c0; +#[doc = "I2C Peripheral"] +pub struct I2C1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C1 {} +impl I2C1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4001_6400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } +} +impl Deref for I2C1 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1").finish() + } +} +#[doc = "I2C Peripheral"] +pub use i2c0 as i2c1; +#[doc = "I2C Peripheral"] +pub struct I2C2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C2 {} +impl I2C2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4001_6800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } +} +impl Deref for I2C2 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C2").finish() + } +} +#[doc = "I2C Peripheral"] +pub use i2c0 as i2c2; +#[doc = "CAN Peripheral"] +pub struct CAN0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CAN0 {} +impl CAN0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4001_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } +} +impl Deref for CAN0 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CAN0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN0").finish() + } +} +#[doc = "CAN Peripheral"] +pub mod can0; +#[doc = "CAN Peripheral"] +pub struct CAN1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CAN1 {} +impl CAN1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4001_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } +} +impl Deref for CAN1 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CAN1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN1").finish() + } +} +#[doc = "CAN Peripheral"] +pub use can0 as can1; +#[doc = "Analog to Digital Converter Peripheral"] +pub struct ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC {} +impl ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x4002_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC").finish() + } +} +#[doc = "Analog to Digital Converter Peripheral"] +pub mod adc; +#[doc = "Digital to Analog Converter Peripheral"] +pub struct DAC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DAC0 {} +impl DAC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac0::RegisterBlock = 0x4002_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac0::RegisterBlock { + Self::PTR + } +} +impl Deref for DAC0 { + type Target = dac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DAC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC0").finish() + } +} +#[doc = "Digital to Analog Converter Peripheral"] +pub mod dac0; +#[doc = "Digital to Analog Converter Peripheral"] +pub struct DAC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DAC1 {} +impl DAC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac0::RegisterBlock = 0x4002_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac0::RegisterBlock { + Self::PTR + } +} +impl Deref for DAC1 { + type Target = dac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DAC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC1").finish() + } +} +#[doc = "Digital to Analog Converter Peripheral"] +pub use dac0 as dac1; +#[doc = "SpaceWire Peripheral"] +pub struct SPW { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPW {} +impl SPW { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spw::RegisterBlock = 0x4000_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spw::RegisterBlock { + Self::PTR + } +} +impl Deref for SPW { + type Target = spw::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPW { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPW").finish() + } +} +#[doc = "SpaceWire Peripheral"] +pub mod spw; +#[doc = "Interrupt Router Peripheral"] +pub struct IRQ_ROUTER { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IRQ_ROUTER {} +impl IRQ_ROUTER { + #[doc = r"Pointer to the register block"] + pub const PTR: *const irq_router::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const irq_router::RegisterBlock { + Self::PTR + } +} +impl Deref for IRQ_ROUTER { + type Target = irq_router::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IRQ_ROUTER { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRQ_ROUTER").finish() + } +} +#[doc = "Interrupt Router Peripheral"] +pub mod irq_router; +#[doc = "Watchdog Block Peripheral"] +pub struct WATCH_DOG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WATCH_DOG {} +impl WATCH_DOG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const watch_dog::RegisterBlock = 0x4002_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const watch_dog::RegisterBlock { + Self::PTR + } +} +impl Deref for WATCH_DOG { + type Target = watch_dog::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WATCH_DOG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WATCH_DOG").finish() + } +} +#[doc = "Watchdog Block Peripheral"] +pub mod watch_dog; +#[doc = "True Random Number Generator"] +pub struct TRNG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TRNG {} +impl TRNG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const trng::RegisterBlock = 0x4002_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const trng::RegisterBlock { + Self::PTR + } +} +impl Deref for TRNG { + type Target = trng::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TRNG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TRNG").finish() + } +} +#[doc = "True Random Number Generator"] +pub mod trng; +#[doc = "Ethernet Block"] +pub struct ETH { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ETH {} +impl ETH { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eth::RegisterBlock = 0x4000_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eth::RegisterBlock { + Self::PTR + } +} +impl Deref for ETH { + type Target = eth::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ETH { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETH").finish() + } +} +#[doc = "Ethernet Block"] +pub mod eth; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r"All the peripherals"] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "CLKGEN"] + pub CLKGEN: CLKGEN, + #[doc = "SYSCONFIG"] + pub SYSCONFIG: SYSCONFIG, + #[doc = "DMA"] + pub DMA: DMA, + #[doc = "IOCONFIG"] + pub IOCONFIG: IOCONFIG, + #[doc = "UTILITY"] + pub UTILITY: UTILITY, + #[doc = "PORTA"] + pub PORTA: PORTA, + #[doc = "PORTB"] + pub PORTB: PORTB, + #[doc = "PORTC"] + pub PORTC: PORTC, + #[doc = "PORTD"] + pub PORTD: PORTD, + #[doc = "PORTE"] + pub PORTE: PORTE, + #[doc = "PORTF"] + pub PORTF: PORTF, + #[doc = "PORTG"] + pub PORTG: PORTG, + #[doc = "TIM0"] + pub TIM0: TIM0, + #[doc = "TIM1"] + pub TIM1: TIM1, + #[doc = "TIM2"] + pub TIM2: TIM2, + #[doc = "TIM3"] + pub TIM3: TIM3, + #[doc = "TIM4"] + pub TIM4: TIM4, + #[doc = "TIM5"] + pub TIM5: TIM5, + #[doc = "TIM6"] + pub TIM6: TIM6, + #[doc = "TIM7"] + pub TIM7: TIM7, + #[doc = "TIM8"] + pub TIM8: TIM8, + #[doc = "TIM9"] + pub TIM9: TIM9, + #[doc = "TIM10"] + pub TIM10: TIM10, + #[doc = "TIM11"] + pub TIM11: TIM11, + #[doc = "TIM12"] + pub TIM12: TIM12, + #[doc = "TIM13"] + pub TIM13: TIM13, + #[doc = "TIM14"] + pub TIM14: TIM14, + #[doc = "TIM15"] + pub TIM15: TIM15, + #[doc = "TIM16"] + pub TIM16: TIM16, + #[doc = "TIM17"] + pub TIM17: TIM17, + #[doc = "TIM18"] + pub TIM18: TIM18, + #[doc = "TIM19"] + pub TIM19: TIM19, + #[doc = "TIM20"] + pub TIM20: TIM20, + #[doc = "TIM21"] + pub TIM21: TIM21, + #[doc = "TIM22"] + pub TIM22: TIM22, + #[doc = "TIM23"] + pub TIM23: TIM23, + #[doc = "UART0"] + pub UART0: UART0, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "UART2"] + pub UART2: UART2, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SPI2"] + pub SPI2: SPI2, + #[doc = "SPI3"] + pub SPI3: SPI3, + #[doc = "I2C0"] + pub I2C0: I2C0, + #[doc = "I2C1"] + pub I2C1: I2C1, + #[doc = "I2C2"] + pub I2C2: I2C2, + #[doc = "CAN0"] + pub CAN0: CAN0, + #[doc = "CAN1"] + pub CAN1: CAN1, + #[doc = "ADC"] + pub ADC: ADC, + #[doc = "DAC0"] + pub DAC0: DAC0, + #[doc = "DAC1"] + pub DAC1: DAC1, + #[doc = "SPW"] + pub SPW: SPW, + #[doc = "IRQ_ROUTER"] + pub IRQ_ROUTER: IRQ_ROUTER, + #[doc = "WATCH_DOG"] + pub WATCH_DOG: WATCH_DOG, + #[doc = "TRNG"] + pub TRNG: TRNG, + #[doc = "ETH"] + pub ETH: ETH, +} +impl Peripherals { + #[doc = r"Returns all the peripherals *once*"] + #[inline] + pub fn take() -> Option { + cortex_m::interrupt::free(|_| { + if unsafe { DEVICE_PERIPHERALS } { + None + } else { + Some(unsafe { Peripherals::steal() }) + } + }) + } + #[doc = r"Unchecked version of `Peripherals::take`"] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + CLKGEN: CLKGEN { + _marker: PhantomData, + }, + SYSCONFIG: SYSCONFIG { + _marker: PhantomData, + }, + DMA: DMA { + _marker: PhantomData, + }, + IOCONFIG: IOCONFIG { + _marker: PhantomData, + }, + UTILITY: UTILITY { + _marker: PhantomData, + }, + PORTA: PORTA { + _marker: PhantomData, + }, + PORTB: PORTB { + _marker: PhantomData, + }, + PORTC: PORTC { + _marker: PhantomData, + }, + PORTD: PORTD { + _marker: PhantomData, + }, + PORTE: PORTE { + _marker: PhantomData, + }, + PORTF: PORTF { + _marker: PhantomData, + }, + PORTG: PORTG { + _marker: PhantomData, + }, + TIM0: TIM0 { + _marker: PhantomData, + }, + TIM1: TIM1 { + _marker: PhantomData, + }, + TIM2: TIM2 { + _marker: PhantomData, + }, + TIM3: TIM3 { + _marker: PhantomData, + }, + TIM4: TIM4 { + _marker: PhantomData, + }, + TIM5: TIM5 { + _marker: PhantomData, + }, + TIM6: TIM6 { + _marker: PhantomData, + }, + TIM7: TIM7 { + _marker: PhantomData, + }, + TIM8: TIM8 { + _marker: PhantomData, + }, + TIM9: TIM9 { + _marker: PhantomData, + }, + TIM10: TIM10 { + _marker: PhantomData, + }, + TIM11: TIM11 { + _marker: PhantomData, + }, + TIM12: TIM12 { + _marker: PhantomData, + }, + TIM13: TIM13 { + _marker: PhantomData, + }, + TIM14: TIM14 { + _marker: PhantomData, + }, + TIM15: TIM15 { + _marker: PhantomData, + }, + TIM16: TIM16 { + _marker: PhantomData, + }, + TIM17: TIM17 { + _marker: PhantomData, + }, + TIM18: TIM18 { + _marker: PhantomData, + }, + TIM19: TIM19 { + _marker: PhantomData, + }, + TIM20: TIM20 { + _marker: PhantomData, + }, + TIM21: TIM21 { + _marker: PhantomData, + }, + TIM22: TIM22 { + _marker: PhantomData, + }, + TIM23: TIM23 { + _marker: PhantomData, + }, + UART0: UART0 { + _marker: PhantomData, + }, + UART1: UART1 { + _marker: PhantomData, + }, + UART2: UART2 { + _marker: PhantomData, + }, + SPI0: SPI0 { + _marker: PhantomData, + }, + SPI1: SPI1 { + _marker: PhantomData, + }, + SPI2: SPI2 { + _marker: PhantomData, + }, + SPI3: SPI3 { + _marker: PhantomData, + }, + I2C0: I2C0 { + _marker: PhantomData, + }, + I2C1: I2C1 { + _marker: PhantomData, + }, + I2C2: I2C2 { + _marker: PhantomData, + }, + CAN0: CAN0 { + _marker: PhantomData, + }, + CAN1: CAN1 { + _marker: PhantomData, + }, + ADC: ADC { + _marker: PhantomData, + }, + DAC0: DAC0 { + _marker: PhantomData, + }, + DAC1: DAC1 { + _marker: PhantomData, + }, + SPW: SPW { + _marker: PhantomData, + }, + IRQ_ROUTER: IRQ_ROUTER { + _marker: PhantomData, + }, + WATCH_DOG: WATCH_DOG { + _marker: PhantomData, + }, + TRNG: TRNG { + _marker: PhantomData, + }, + ETH: ETH { + _marker: PhantomData, + }, + } } } diff --git a/src/porta.rs b/src/porta.rs new file mode 100644 index 0000000..d0a4207 --- /dev/null +++ b/src/porta.rs @@ -0,0 +1,380 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_datain: [u8; 0x04], + _reserved_1_datainraw: [u8; 0x04], + _reserved_2_dataout: [u8; 0x04], + _reserved_3_dataoutraw: [u8; 0x04], + _reserved_4_setout: [u8; 0x04], + _reserved_5_clrout: [u8; 0x04], + _reserved_6_togout: [u8; 0x04], + _reserved_7_datamask: [u8; 0x04], + _reserved_8_dir: [u8; 0x04], + _reserved_9_pulse: [u8; 0x04], + _reserved_10_pulsebase: [u8; 0x04], + _reserved_11_delay: [u8; 0x04], + _reserved_12_delay: [u8; 0x04], + #[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] + pub irq_sen: crate::Reg, + #[doc = "0x38 - Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] + pub irq_edge: crate::Reg, + #[doc = "0x3c - Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] + pub irq_evt: crate::Reg, + #[doc = "0x40 - Interrupt Enable Register"] + pub irq_enb: crate::Reg, + #[doc = "0x44 - Raw Interrupt Status"] + pub irq_raw: crate::Reg, + #[doc = "0x48 - Masked Interrupt Status"] + pub irq_end: crate::Reg, + #[doc = "0x4c - Edge Status Register"] + pub edge_status: crate::Reg, + _reserved20: [u8; 0x03ac], + #[doc = "0x3fc - Peripheral ID Register"] + pub perid: crate::Reg, +} +impl RegisterBlock { + #[doc = "0x00 - Data In Register by Byte"] + #[inline(always)] + pub fn datainbyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(0usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x00 - Data In Register"] + #[inline(always)] + pub fn datain(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(0usize) + as *const crate::Reg) + } + } + #[doc = "0x04 - Data In Raw Register by Byte"] + #[inline(always)] + pub fn datainrawbyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(4usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x04 - Data In Raw Register"] + #[inline(always)] + pub fn datainraw(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(4usize) + as *const crate::Reg) + } + } + #[doc = "0x08 - Data Out Register by Byte"] + #[inline(always)] + pub fn dataoutbyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(8usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x08 - Data Out Register"] + #[inline(always)] + pub fn dataout(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(8usize) + as *const crate::Reg) + } + } + #[doc = "0x0c - Data Out Register by Byte"] + #[inline(always)] + pub fn dataoutrawbyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x0c - Data Out Register"] + #[inline(always)] + pub fn dataoutraw(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(12usize) + as *const crate::Reg) + } + } + #[doc = "0x10 - Set Out Register by Byte"] + #[inline(always)] + pub fn setoutbyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(16usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x10 - Set Out Register"] + #[inline(always)] + pub fn setout(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(16usize) + as *const crate::Reg) + } + } + #[doc = "0x14 - Clear Out Register by Byte"] + #[inline(always)] + pub fn clroutbyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(20usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x14 - Clear Out Register"] + #[inline(always)] + pub fn clrout(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(20usize) + as *const crate::Reg) + } + } + #[doc = "0x18 - Toggle Out Register by Byte"] + #[inline(always)] + pub fn togoutbyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(24usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x18 - Toggle Out Register"] + #[inline(always)] + pub fn togout(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(24usize) + as *const crate::Reg) + } + } + #[doc = "0x1c - Data Out Register by Byte"] + #[inline(always)] + pub fn datamaskbyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(28usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x1c - Data mask Register"] + #[inline(always)] + pub fn datamask(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(28usize) + as *const crate::Reg) + } + } + #[doc = "0x20 - Direction Register by Byte"] + #[inline(always)] + pub fn dirbyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(32usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x20 - Direction Register (1:Output, 0:Input)"] + #[inline(always)] + pub fn dir(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(32usize) + as *const crate::Reg) + } + } + #[doc = "0x24 - Pulse Mode Register by Byte"] + #[inline(always)] + pub fn pulsebyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(36usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x24 - Pulse Mode Register"] + #[inline(always)] + pub fn pulse(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(36usize) + as *const crate::Reg) + } + } + #[doc = "0x28 - Pulse Base Mode Register by Byte"] + #[inline(always)] + pub fn pulsebasebyte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(40usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x28 - Pulse Base Value Register"] + #[inline(always)] + pub fn pulsebase(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(40usize) + as *const crate::Reg) + } + } + #[doc = "0x2c - Delay1 Register by Byte"] + #[inline(always)] + pub fn delay1byte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(44usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x2c - Delay1 Register"] + #[inline(always)] + pub fn delay1(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(44usize) + as *const crate::Reg) + } + } + #[doc = "0x30 - Delay2 Register by Byte"] + #[inline(always)] + pub fn delay2byte(&self) -> &[crate::Reg; 4] { + unsafe { + &*(((self as *const Self) as *const u8).add(48usize) + as *const [crate::Reg; 4]) + } + } + #[doc = "0x30 - Delay2 Register"] + #[inline(always)] + pub fn delay2(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(48usize) + as *const crate::Reg) + } + } +} +#[doc = "DATAIN register accessor: an alias for `Reg`"] +pub type DATAIN = crate::Reg; +#[doc = "Data In Register"] +pub mod datain; +#[doc = "DATAINBYTE register accessor: an alias for `Reg`"] +pub type DATAINBYTE = crate::Reg; +#[doc = "Data In Register by Byte"] +pub mod datainbyte; +#[doc = "DATAINRAW register accessor: an alias for `Reg`"] +pub type DATAINRAW = crate::Reg; +#[doc = "Data In Raw Register"] +pub mod datainraw; +#[doc = "DATAINRAWBYTE register accessor: an alias for `Reg`"] +pub type DATAINRAWBYTE = crate::Reg; +#[doc = "Data In Raw Register by Byte"] +pub mod datainrawbyte; +#[doc = "DATAOUT register accessor: an alias for `Reg`"] +pub type DATAOUT = crate::Reg; +#[doc = "Data Out Register"] +pub mod dataout; +#[doc = "DATAOUTBYTE register accessor: an alias for `Reg`"] +pub type DATAOUTBYTE = crate::Reg; +#[doc = "Data Out Register by Byte"] +pub mod dataoutbyte; +#[doc = "DATAOUTRAW register accessor: an alias for `Reg`"] +pub type DATAOUTRAW = crate::Reg; +#[doc = "Data Out Register"] +pub mod dataoutraw; +#[doc = "DATAOUTRAWBYTE register accessor: an alias for `Reg`"] +pub type DATAOUTRAWBYTE = crate::Reg; +#[doc = "Data Out Register by Byte"] +pub mod dataoutrawbyte; +#[doc = "SETOUT register accessor: an alias for `Reg`"] +pub type SETOUT = crate::Reg; +#[doc = "Set Out Register"] +pub mod setout; +#[doc = "SETOUTBYTE register accessor: an alias for `Reg`"] +pub type SETOUTBYTE = crate::Reg; +#[doc = "Set Out Register by Byte"] +pub mod setoutbyte; +#[doc = "CLROUT register accessor: an alias for `Reg`"] +pub type CLROUT = crate::Reg; +#[doc = "Clear Out Register"] +pub mod clrout; +#[doc = "CLROUTBYTE register accessor: an alias for `Reg`"] +pub type CLROUTBYTE = crate::Reg; +#[doc = "Clear Out Register by Byte"] +pub mod clroutbyte; +#[doc = "TOGOUT register accessor: an alias for `Reg`"] +pub type TOGOUT = crate::Reg; +#[doc = "Toggle Out Register"] +pub mod togout; +#[doc = "TOGOUTBYTE register accessor: an alias for `Reg`"] +pub type TOGOUTBYTE = crate::Reg; +#[doc = "Toggle Out Register by Byte"] +pub mod togoutbyte; +#[doc = "DATAMASK register accessor: an alias for `Reg`"] +pub type DATAMASK = crate::Reg; +#[doc = "Data mask Register"] +pub mod datamask; +#[doc = "DATAMASKBYTE register accessor: an alias for `Reg`"] +pub type DATAMASKBYTE = crate::Reg; +#[doc = "Data Out Register by Byte"] +pub mod datamaskbyte; +#[doc = "DIR register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Direction Register (1:Output, 0:Input)"] +pub mod dir; +#[doc = "DIRBYTE register accessor: an alias for `Reg`"] +pub type DIRBYTE = crate::Reg; +#[doc = "Direction Register by Byte"] +pub mod dirbyte; +#[doc = "PULSE register accessor: an alias for `Reg`"] +pub type PULSE = crate::Reg; +#[doc = "Pulse Mode Register"] +pub mod pulse; +#[doc = "PULSEBYTE register accessor: an alias for `Reg`"] +pub type PULSEBYTE = crate::Reg; +#[doc = "Pulse Mode Register by Byte"] +pub mod pulsebyte; +#[doc = "PULSEBASE register accessor: an alias for `Reg`"] +pub type PULSEBASE = crate::Reg; +#[doc = "Pulse Base Value Register"] +pub mod pulsebase; +#[doc = "PULSEBASEBYTE register accessor: an alias for `Reg`"] +pub type PULSEBASEBYTE = crate::Reg; +#[doc = "Pulse Base Mode Register by Byte"] +pub mod pulsebasebyte; +#[doc = "DELAY1 register accessor: an alias for `Reg`"] +pub type DELAY1 = crate::Reg; +#[doc = "Delay1 Register"] +pub mod delay1; +#[doc = "DELAY1BYTE register accessor: an alias for `Reg`"] +pub type DELAY1BYTE = crate::Reg; +#[doc = "Delay1 Register by Byte"] +pub mod delay1byte; +#[doc = "DELAY2 register accessor: an alias for `Reg`"] +pub type DELAY2 = crate::Reg; +#[doc = "Delay2 Register"] +pub mod delay2; +#[doc = "DELAY2BYTE register accessor: an alias for `Reg`"] +pub type DELAY2BYTE = crate::Reg; +#[doc = "Delay2 Register by Byte"] +pub mod delay2byte; +#[doc = "IRQ_SEN register accessor: an alias for `Reg`"] +pub type IRQ_SEN = crate::Reg; +#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] +pub mod irq_sen; +#[doc = "IRQ_EDGE register accessor: an alias for `Reg`"] +pub type IRQ_EDGE = crate::Reg; +#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] +pub mod irq_edge; +#[doc = "IRQ_EVT register accessor: an alias for `Reg`"] +pub type IRQ_EVT = crate::Reg; +#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] +pub mod irq_evt; +#[doc = "IRQ_ENB register accessor: an alias for `Reg`"] +pub type IRQ_ENB = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +#[doc = "IRQ_RAW register accessor: an alias for `Reg`"] +pub type IRQ_RAW = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END register accessor: an alias for `Reg`"] +pub type IRQ_END = crate::Reg; +#[doc = "Masked Interrupt Status"] +pub mod irq_end; +#[doc = "EDGE_STATUS register accessor: an alias for `Reg`"] +pub type EDGE_STATUS = crate::Reg; +#[doc = "Edge Status Register"] +pub mod edge_status; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/porta/clrout.rs b/src/porta/clrout.rs new file mode 100644 index 0000000..5403a54 --- /dev/null +++ b/src/porta/clrout.rs @@ -0,0 +1,45 @@ +#[doc = "Register `CLROUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear Out Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clrout](index.html) module"] +pub struct CLROUT_SPEC; +impl crate::RegisterSpec for CLROUT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [clrout::W](W) writer structure"] +impl crate::Writable for CLROUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLROUT to value 0"] +impl crate::Resettable for CLROUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/clroutbyte.rs b/src/porta/clroutbyte.rs new file mode 100644 index 0000000..37425a8 --- /dev/null +++ b/src/porta/clroutbyte.rs @@ -0,0 +1,46 @@ +#[doc = "Register `CLROUTBYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear Out Register by Byte\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clroutbyte](index.html) module"] +pub struct CLROUTBYTE_SPEC; +impl crate::RegisterSpec for CLROUTBYTE_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clroutbyte::W](W) writer structure"] +impl crate::Writable for CLROUTBYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLROUTBYTE[%s] +to value 0"] +impl crate::Resettable for CLROUTBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/datain.rs b/src/porta/datain.rs new file mode 100644 index 0000000..0516acf --- /dev/null +++ b/src/porta/datain.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data In Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datain](index.html) module"] +pub struct DATAIN_SPEC; +impl crate::RegisterSpec for DATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [datain::R](R) reader structure"] +impl crate::Readable for DATAIN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DATAIN to value 0"] +impl crate::Resettable for DATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/datainbyte.rs b/src/porta/datainbyte.rs new file mode 100644 index 0000000..f738545 --- /dev/null +++ b/src/porta/datainbyte.rs @@ -0,0 +1,32 @@ +#[doc = "Register `DATAINBYTE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data In Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datainbyte](index.html) module"] +pub struct DATAINBYTE_SPEC; +impl crate::RegisterSpec for DATAINBYTE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [datainbyte::R](R) reader structure"] +impl crate::Readable for DATAINBYTE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DATAINBYTE[%s] +to value 0"] +impl crate::Resettable for DATAINBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/datainraw.rs b/src/porta/datainraw.rs new file mode 100644 index 0000000..5956914 --- /dev/null +++ b/src/porta/datainraw.rs @@ -0,0 +1,31 @@ +#[doc = "Register `DATAINRAW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data In Raw Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datainraw](index.html) module"] +pub struct DATAINRAW_SPEC; +impl crate::RegisterSpec for DATAINRAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [datainraw::R](R) reader structure"] +impl crate::Readable for DATAINRAW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DATAINRAW to value 0"] +impl crate::Resettable for DATAINRAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/datainrawbyte.rs b/src/porta/datainrawbyte.rs new file mode 100644 index 0000000..f88f98f --- /dev/null +++ b/src/porta/datainrawbyte.rs @@ -0,0 +1,32 @@ +#[doc = "Register `DATAINRAWBYTE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data In Raw Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datainrawbyte](index.html) module"] +pub struct DATAINRAWBYTE_SPEC; +impl crate::RegisterSpec for DATAINRAWBYTE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [datainrawbyte::R](R) reader structure"] +impl crate::Readable for DATAINRAWBYTE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DATAINRAWBYTE[%s] +to value 0"] +impl crate::Resettable for DATAINRAWBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/datamask.rs b/src/porta/datamask.rs new file mode 100644 index 0000000..c40ee37 --- /dev/null +++ b/src/porta/datamask.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DATAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datamask](index.html) module"] +pub struct DATAMASK_SPEC; +impl crate::RegisterSpec for DATAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [datamask::R](R) reader structure"] +impl crate::Readable for DATAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [datamask::W](W) writer structure"] +impl crate::Writable for DATAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATAMASK to value 0"] +impl crate::Resettable for DATAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/datamaskbyte.rs b/src/porta/datamaskbyte.rs new file mode 100644 index 0000000..7f31ded --- /dev/null +++ b/src/porta/datamaskbyte.rs @@ -0,0 +1,65 @@ +#[doc = "Register `DATAMASKBYTE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATAMASKBYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Out Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [datamaskbyte](index.html) module"] +pub struct DATAMASKBYTE_SPEC; +impl crate::RegisterSpec for DATAMASKBYTE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [datamaskbyte::R](R) reader structure"] +impl crate::Readable for DATAMASKBYTE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [datamaskbyte::W](W) writer structure"] +impl crate::Writable for DATAMASKBYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATAMASKBYTE[%s] +to value 0"] +impl crate::Resettable for DATAMASKBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/dataout.rs b/src/porta/dataout.rs new file mode 100644 index 0000000..c1f270f --- /dev/null +++ b/src/porta/dataout.rs @@ -0,0 +1,45 @@ +#[doc = "Register `DATAOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Out Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dataout](index.html) module"] +pub struct DATAOUT_SPEC; +impl crate::RegisterSpec for DATAOUT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [dataout::W](W) writer structure"] +impl crate::Writable for DATAOUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATAOUT to value 0"] +impl crate::Resettable for DATAOUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/dataoutbyte.rs b/src/porta/dataoutbyte.rs new file mode 100644 index 0000000..df478cd --- /dev/null +++ b/src/porta/dataoutbyte.rs @@ -0,0 +1,46 @@ +#[doc = "Register `DATAOUTBYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Out Register by Byte\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dataoutbyte](index.html) module"] +pub struct DATAOUTBYTE_SPEC; +impl crate::RegisterSpec for DATAOUTBYTE_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [dataoutbyte::W](W) writer structure"] +impl crate::Writable for DATAOUTBYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATAOUTBYTE[%s] +to value 0"] +impl crate::Resettable for DATAOUTBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/dataoutraw.rs b/src/porta/dataoutraw.rs new file mode 100644 index 0000000..f0535c6 --- /dev/null +++ b/src/porta/dataoutraw.rs @@ -0,0 +1,45 @@ +#[doc = "Register `DATAOUTRAW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Out Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dataoutraw](index.html) module"] +pub struct DATAOUTRAW_SPEC; +impl crate::RegisterSpec for DATAOUTRAW_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [dataoutraw::W](W) writer structure"] +impl crate::Writable for DATAOUTRAW_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATAOUTRAW to value 0"] +impl crate::Resettable for DATAOUTRAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/dataoutrawbyte.rs b/src/porta/dataoutrawbyte.rs new file mode 100644 index 0000000..09b971d --- /dev/null +++ b/src/porta/dataoutrawbyte.rs @@ -0,0 +1,46 @@ +#[doc = "Register `DATAOUTRAWBYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Out Register by Byte\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dataoutrawbyte](index.html) module"] +pub struct DATAOUTRAWBYTE_SPEC; +impl crate::RegisterSpec for DATAOUTRAWBYTE_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [dataoutrawbyte::W](W) writer structure"] +impl crate::Writable for DATAOUTRAWBYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATAOUTRAWBYTE[%s] +to value 0"] +impl crate::Resettable for DATAOUTRAWBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/delay1.rs b/src/porta/delay1.rs new file mode 100644 index 0000000..643c113 --- /dev/null +++ b/src/porta/delay1.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DELAY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DELAY1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Delay1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [delay1](index.html) module"] +pub struct DELAY1_SPEC; +impl crate::RegisterSpec for DELAY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [delay1::R](R) reader structure"] +impl crate::Readable for DELAY1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [delay1::W](W) writer structure"] +impl crate::Writable for DELAY1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DELAY1 to value 0"] +impl crate::Resettable for DELAY1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/delay1byte.rs b/src/porta/delay1byte.rs new file mode 100644 index 0000000..4d3324e --- /dev/null +++ b/src/porta/delay1byte.rs @@ -0,0 +1,65 @@ +#[doc = "Register `DELAY1BYTE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DELAY1BYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Delay1 Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [delay1byte](index.html) module"] +pub struct DELAY1BYTE_SPEC; +impl crate::RegisterSpec for DELAY1BYTE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [delay1byte::R](R) reader structure"] +impl crate::Readable for DELAY1BYTE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [delay1byte::W](W) writer structure"] +impl crate::Writable for DELAY1BYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DELAY1BYTE[%s] +to value 0"] +impl crate::Resettable for DELAY1BYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/delay2.rs b/src/porta/delay2.rs new file mode 100644 index 0000000..adc7a7c --- /dev/null +++ b/src/porta/delay2.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DELAY2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DELAY2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Delay2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [delay2](index.html) module"] +pub struct DELAY2_SPEC; +impl crate::RegisterSpec for DELAY2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [delay2::R](R) reader structure"] +impl crate::Readable for DELAY2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [delay2::W](W) writer structure"] +impl crate::Writable for DELAY2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DELAY2 to value 0"] +impl crate::Resettable for DELAY2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/delay2byte.rs b/src/porta/delay2byte.rs new file mode 100644 index 0000000..f4025dc --- /dev/null +++ b/src/porta/delay2byte.rs @@ -0,0 +1,65 @@ +#[doc = "Register `DELAY2BYTE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DELAY2BYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Delay2 Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [delay2byte](index.html) module"] +pub struct DELAY2BYTE_SPEC; +impl crate::RegisterSpec for DELAY2BYTE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [delay2byte::R](R) reader structure"] +impl crate::Readable for DELAY2BYTE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [delay2byte::W](W) writer structure"] +impl crate::Writable for DELAY2BYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DELAY2BYTE[%s] +to value 0"] +impl crate::Resettable for DELAY2BYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/dir.rs b/src/porta/dir.rs new file mode 100644 index 0000000..eff9075 --- /dev/null +++ b/src/porta/dir.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DIR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Direction Register (1:Output, 0:Input)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DIR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/dirbyte.rs b/src/porta/dirbyte.rs new file mode 100644 index 0000000..1f161b4 --- /dev/null +++ b/src/porta/dirbyte.rs @@ -0,0 +1,65 @@ +#[doc = "Register `DIRBYTE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRBYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Direction Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirbyte](index.html) module"] +pub struct DIRBYTE_SPEC; +impl crate::RegisterSpec for DIRBYTE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dirbyte::R](R) reader structure"] +impl crate::Readable for DIRBYTE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirbyte::W](W) writer structure"] +impl crate::Writable for DIRBYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DIRBYTE[%s] +to value 0"] +impl crate::Resettable for DIRBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/edge_status.rs b/src/porta/edge_status.rs new file mode 100644 index 0000000..775bef3 --- /dev/null +++ b/src/porta/edge_status.rs @@ -0,0 +1,64 @@ +#[doc = "Register `EDGE_STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EDGE_STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Edge Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [edge_status](index.html) module"] +pub struct EDGE_STATUS_SPEC; +impl crate::RegisterSpec for EDGE_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [edge_status::R](R) reader structure"] +impl crate::Readable for EDGE_STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [edge_status::W](W) writer structure"] +impl crate::Writable for EDGE_STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EDGE_STATUS to value 0"] +impl crate::Resettable for EDGE_STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/irq_edge.rs b/src/porta/irq_edge.rs new file mode 100644 index 0000000..bfe3e68 --- /dev/null +++ b/src/porta/irq_edge.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_EDGE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_EDGE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_edge](index.html) module"] +pub struct IRQ_EDGE_SPEC; +impl crate::RegisterSpec for IRQ_EDGE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_edge::R](R) reader structure"] +impl crate::Readable for IRQ_EDGE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_edge::W](W) writer structure"] +impl crate::Writable for IRQ_EDGE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_EDGE to value 0"] +impl crate::Resettable for IRQ_EDGE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/irq_enb.rs b/src/porta/irq_enb.rs new file mode 100644 index 0000000..b915348 --- /dev/null +++ b/src/porta/irq_enb.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_ENB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"] +pub struct IRQ_ENB_SPEC; +impl crate::RegisterSpec for IRQ_ENB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_enb::R](R) reader structure"] +impl crate::Readable for IRQ_ENB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"] +impl crate::Writable for IRQ_ENB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IRQ_ENB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/irq_end.rs b/src/porta/irq_end.rs new file mode 100644 index 0000000..8afdac5 --- /dev/null +++ b/src/porta/irq_end.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IRQ_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Masked Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"] +pub struct IRQ_END_SPEC; +impl crate::RegisterSpec for IRQ_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_end::R](R) reader structure"] +impl crate::Readable for IRQ_END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IRQ_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/irq_evt.rs b/src/porta/irq_evt.rs new file mode 100644 index 0000000..a42470e --- /dev/null +++ b/src/porta/irq_evt.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_EVT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_EVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_evt](index.html) module"] +pub struct IRQ_EVT_SPEC; +impl crate::RegisterSpec for IRQ_EVT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_evt::R](R) reader structure"] +impl crate::Readable for IRQ_EVT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_evt::W](W) writer structure"] +impl crate::Writable for IRQ_EVT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_EVT to value 0"] +impl crate::Resettable for IRQ_EVT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/irq_raw.rs b/src/porta/irq_raw.rs new file mode 100644 index 0000000..bbcaafe --- /dev/null +++ b/src/porta/irq_raw.rs @@ -0,0 +1,31 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Raw Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"] +pub struct IRQ_RAW_SPEC; +impl crate::RegisterSpec for IRQ_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_raw::R](R) reader structure"] +impl crate::Readable for IRQ_RAW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_RAW to value 0"] +impl crate::Resettable for IRQ_RAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/irq_sen.rs b/src/porta/irq_sen.rs new file mode 100644 index 0000000..dc0e9c8 --- /dev/null +++ b/src/porta/irq_sen.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_SEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_SEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_sen](index.html) module"] +pub struct IRQ_SEN_SPEC; +impl crate::RegisterSpec for IRQ_SEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_sen::R](R) reader structure"] +impl crate::Readable for IRQ_SEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_sen::W](W) writer structure"] +impl crate::Writable for IRQ_SEN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_SEN to value 0"] +impl crate::Resettable for IRQ_SEN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/perid.rs b/src/porta/perid.rs new file mode 100644 index 0000000..edc93e2 --- /dev/null +++ b/src/porta/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0210_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0210_07e9 + } +} diff --git a/src/porta/pulse.rs b/src/porta/pulse.rs new file mode 100644 index 0000000..a9ac046 --- /dev/null +++ b/src/porta/pulse.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PULSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PULSE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pulse Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pulse](index.html) module"] +pub struct PULSE_SPEC; +impl crate::RegisterSpec for PULSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pulse::R](R) reader structure"] +impl crate::Readable for PULSE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pulse::W](W) writer structure"] +impl crate::Writable for PULSE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PULSE to value 0"] +impl crate::Resettable for PULSE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/pulsebase.rs b/src/porta/pulsebase.rs new file mode 100644 index 0000000..ce11f86 --- /dev/null +++ b/src/porta/pulsebase.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PULSEBASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PULSEBASE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pulse Base Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pulsebase](index.html) module"] +pub struct PULSEBASE_SPEC; +impl crate::RegisterSpec for PULSEBASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pulsebase::R](R) reader structure"] +impl crate::Readable for PULSEBASE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pulsebase::W](W) writer structure"] +impl crate::Writable for PULSEBASE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PULSEBASE to value 0"] +impl crate::Resettable for PULSEBASE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/pulsebasebyte.rs b/src/porta/pulsebasebyte.rs new file mode 100644 index 0000000..db18ec8 --- /dev/null +++ b/src/porta/pulsebasebyte.rs @@ -0,0 +1,65 @@ +#[doc = "Register `PULSEBASEBYTE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PULSEBASEBYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pulse Base Mode Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pulsebasebyte](index.html) module"] +pub struct PULSEBASEBYTE_SPEC; +impl crate::RegisterSpec for PULSEBASEBYTE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pulsebasebyte::R](R) reader structure"] +impl crate::Readable for PULSEBASEBYTE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pulsebasebyte::W](W) writer structure"] +impl crate::Writable for PULSEBASEBYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PULSEBASEBYTE[%s] +to value 0"] +impl crate::Resettable for PULSEBASEBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/pulsebyte.rs b/src/porta/pulsebyte.rs new file mode 100644 index 0000000..ce9fe16 --- /dev/null +++ b/src/porta/pulsebyte.rs @@ -0,0 +1,65 @@ +#[doc = "Register `PULSEBYTE[%s]` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PULSEBYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pulse Mode Register by Byte\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pulsebyte](index.html) module"] +pub struct PULSEBYTE_SPEC; +impl crate::RegisterSpec for PULSEBYTE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pulsebyte::R](R) reader structure"] +impl crate::Readable for PULSEBYTE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pulsebyte::W](W) writer structure"] +impl crate::Writable for PULSEBYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PULSEBYTE[%s] +to value 0"] +impl crate::Resettable for PULSEBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/setout.rs b/src/porta/setout.rs new file mode 100644 index 0000000..ada3742 --- /dev/null +++ b/src/porta/setout.rs @@ -0,0 +1,45 @@ +#[doc = "Register `SETOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Set Out Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [setout](index.html) module"] +pub struct SETOUT_SPEC; +impl crate::RegisterSpec for SETOUT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [setout::W](W) writer structure"] +impl crate::Writable for SETOUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SETOUT to value 0"] +impl crate::Resettable for SETOUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/setoutbyte.rs b/src/porta/setoutbyte.rs new file mode 100644 index 0000000..5cb0d7f --- /dev/null +++ b/src/porta/setoutbyte.rs @@ -0,0 +1,46 @@ +#[doc = "Register `SETOUTBYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Set Out Register by Byte\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [setoutbyte](index.html) module"] +pub struct SETOUTBYTE_SPEC; +impl crate::RegisterSpec for SETOUTBYTE_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [setoutbyte::W](W) writer structure"] +impl crate::Writable for SETOUTBYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SETOUTBYTE[%s] +to value 0"] +impl crate::Resettable for SETOUTBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/togout.rs b/src/porta/togout.rs new file mode 100644 index 0000000..bfad5d5 --- /dev/null +++ b/src/porta/togout.rs @@ -0,0 +1,45 @@ +#[doc = "Register `TOGOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Toggle Out Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [togout](index.html) module"] +pub struct TOGOUT_SPEC; +impl crate::RegisterSpec for TOGOUT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [togout::W](W) writer structure"] +impl crate::Writable for TOGOUT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOGOUT to value 0"] +impl crate::Resettable for TOGOUT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/porta/togoutbyte.rs b/src/porta/togoutbyte.rs new file mode 100644 index 0000000..4ca0528 --- /dev/null +++ b/src/porta/togoutbyte.rs @@ -0,0 +1,46 @@ +#[doc = "Register `TOGOUTBYTE[%s]` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Toggle Out Register by Byte\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [togoutbyte](index.html) module"] +pub struct TOGOUTBYTE_SPEC; +impl crate::RegisterSpec for TOGOUTBYTE_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [togoutbyte::W](W) writer structure"] +impl crate::Writable for TOGOUTBYTE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TOGOUTBYTE[%s] +to value 0"] +impl crate::Resettable for TOGOUTBYTE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0.rs b/src/spi0.rs new file mode 100644 index 0000000..8b7607e --- /dev/null +++ b/src/spi0.rs @@ -0,0 +1,89 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control Register 0"] + pub ctrl0: crate::Reg, + #[doc = "0x04 - Control Register 1"] + pub ctrl1: crate::Reg, + #[doc = "0x08 - Data Input/Output"] + pub data: crate::Reg, + #[doc = "0x0c - Status Register"] + pub status: crate::Reg, + #[doc = "0x10 - Clock Pre Scale divide value"] + pub clkprescale: crate::Reg, + #[doc = "0x14 - Interrupt Enable Register"] + pub irq_enb: crate::Reg, + #[doc = "0x18 - Raw Interrupt Status Register"] + pub irq_raw: crate::Reg, + #[doc = "0x1c - Enabled Interrupt Status Register"] + pub irq_end: crate::Reg, + #[doc = "0x20 - Clear Interrupt Status Register"] + pub irq_clr: crate::Reg, + #[doc = "0x24 - Rx FIFO IRQ Trigger Level"] + pub rxfifoirqtrg: crate::Reg, + #[doc = "0x28 - Tx FIFO IRQ Trigger Level"] + pub txfifoirqtrg: crate::Reg, + #[doc = "0x2c - Clear FIFO Register"] + pub fifo_clr: crate::Reg, + #[doc = "0x30 - Internal STATE of SPI Controller"] + pub state: crate::Reg, + _reserved13: [u8; 0x03c8], + #[doc = "0x3fc - Peripheral ID Register"] + pub perid: crate::Reg, +} +#[doc = "CTRL0 register accessor: an alias for `Reg`"] +pub type CTRL0 = crate::Reg; +#[doc = "Control Register 0"] +pub mod ctrl0; +#[doc = "CTRL1 register accessor: an alias for `Reg`"] +pub type CTRL1 = crate::Reg; +#[doc = "Control Register 1"] +pub mod ctrl1; +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data Input/Output"] +pub mod data; +#[doc = "STATUS register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "CLKPRESCALE register accessor: an alias for `Reg`"] +pub type CLKPRESCALE = crate::Reg; +#[doc = "Clock Pre Scale divide value"] +pub mod clkprescale; +#[doc = "IRQ_ENB register accessor: an alias for `Reg`"] +pub type IRQ_ENB = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +#[doc = "IRQ_RAW register accessor: an alias for `Reg`"] +pub type IRQ_RAW = crate::Reg; +#[doc = "Raw Interrupt Status Register"] +pub mod irq_raw; +#[doc = "IRQ_END register accessor: an alias for `Reg`"] +pub type IRQ_END = crate::Reg; +#[doc = "Enabled Interrupt Status Register"] +pub mod irq_end; +#[doc = "IRQ_CLR register accessor: an alias for `Reg`"] +pub type IRQ_CLR = crate::Reg; +#[doc = "Clear Interrupt Status Register"] +pub mod irq_clr; +#[doc = "RXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type RXFIFOIRQTRG = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type TXFIFOIRQTRG = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR register accessor: an alias for `Reg`"] +pub type FIFO_CLR = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "STATE register accessor: an alias for `Reg`"] +pub type STATE = crate::Reg; +#[doc = "Internal STATE of SPI Controller"] +pub mod state; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/spi0/clkprescale.rs b/src/spi0/clkprescale.rs new file mode 100644 index 0000000..7159517 --- /dev/null +++ b/src/spi0/clkprescale.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CLKPRESCALE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKPRESCALE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Pre Scale divide value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkprescale](index.html) module"] +pub struct CLKPRESCALE_SPEC; +impl crate::RegisterSpec for CLKPRESCALE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkprescale::R](R) reader structure"] +impl crate::Readable for CLKPRESCALE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkprescale::W](W) writer structure"] +impl crate::Writable for CLKPRESCALE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKPRESCALE to value 0"] +impl crate::Resettable for CLKPRESCALE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/ctrl0.rs b/src/spi0/ctrl0.rs new file mode 100644 index 0000000..143e388 --- /dev/null +++ b/src/spi0/ctrl0.rs @@ -0,0 +1,234 @@ +#[doc = "Register `CTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SIZE` reader - Data Size(0x3=>4, 0xf=>16)"] +pub struct SIZE_R(crate::FieldReader); +impl SIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SIZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SIZE` writer - Data Size(0x3=>4, 0xf=>16)"] +pub struct SIZE_W<'a> { + w: &'a mut W, +} +impl<'a> SIZE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Field `SPO` reader - SPI Clock Polarity"] +pub struct SPO_R(crate::FieldReader); +impl SPO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPO` writer - SPI Clock Polarity"] +pub struct SPO_W<'a> { + w: &'a mut W, +} +impl<'a> SPO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SPH` reader - SPI Clock Phase"] +pub struct SPH_R(crate::FieldReader); +impl SPH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPH` writer - SPI Clock Phase"] +pub struct SPH_W<'a> { + w: &'a mut W, +} +impl<'a> SPH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SCRDV` reader - Serial Clock Rate divide+1 value"] +pub struct SCRDV_R(crate::FieldReader); +impl SCRDV_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SCRDV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCRDV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCRDV` writer - Serial Clock Rate divide+1 value"] +pub struct SCRDV_W<'a> { + w: &'a mut W, +} +impl<'a> SCRDV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - SPI Clock Polarity"] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - SPI Clock Phase"] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] + #[inline(always)] + pub fn scrdv(&self) -> SCRDV_R { + SCRDV_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] + #[inline(always)] + pub fn size(&mut self) -> SIZE_W { + SIZE_W { w: self } + } + #[doc = "Bit 6 - SPI Clock Polarity"] + #[inline(always)] + pub fn spo(&mut self) -> SPO_W { + SPO_W { w: self } + } + #[doc = "Bit 7 - SPI Clock Phase"] + #[inline(always)] + pub fn sph(&mut self) -> SPH_W { + SPH_W { w: self } + } + #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] + #[inline(always)] + pub fn scrdv(&mut self) -> SCRDV_W { + SCRDV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl0](index.html) module"] +pub struct CTRL0_SPEC; +impl crate::RegisterSpec for CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl0::R](R) reader structure"] +impl crate::Readable for CTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl0::W](W) writer structure"] +impl crate::Writable for CTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL0 to value 0"] +impl crate::Resettable for CTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/ctrl1.rs b/src/spi0/ctrl1.rs new file mode 100644 index 0000000..fca0c46 --- /dev/null +++ b/src/spi0/ctrl1.rs @@ -0,0 +1,526 @@ +#[doc = "Register `CTRL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LBM` reader - Loop Back"] +pub struct LBM_R(crate::FieldReader); +impl LBM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LBM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBM` writer - Loop Back"] +pub struct LBM_W<'a> { + w: &'a mut W, +} +impl<'a> LBM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MS` reader - Master/Slave (0:Master, 1:Slave)"] +pub struct MS_R(crate::FieldReader); +impl MS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MS` writer - Master/Slave (0:Master, 1:Slave)"] +pub struct MS_W<'a> { + w: &'a mut W, +} +impl<'a> MS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SOD` reader - Slave output Disable"] +pub struct SOD_R(crate::FieldReader); +impl SOD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SOD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SOD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SOD` writer - Slave output Disable"] +pub struct SOD_W<'a> { + w: &'a mut W, +} +impl<'a> SOD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SS` reader - Slave Select"] +pub struct SS_R(crate::FieldReader); +impl SS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SS` writer - Slave Select"] +pub struct SS_W<'a> { + w: &'a mut W, +} +impl<'a> SS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4); + self.w + } +} +#[doc = "Field `BLOCKMODE` reader - Block Mode Enable"] +pub struct BLOCKMODE_R(crate::FieldReader); +impl BLOCKMODE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BLOCKMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BLOCKMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BLOCKMODE` writer - Block Mode Enable"] +pub struct BLOCKMODE_W<'a> { + w: &'a mut W, +} +impl<'a> BLOCKMODE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `BMSTART` reader - Block Mode Start Status Enable"] +pub struct BMSTART_R(crate::FieldReader); +impl BMSTART_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BMSTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BMSTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BMSTART` writer - Block Mode Start Status Enable"] +pub struct BMSTART_W<'a> { + w: &'a mut W, +} +impl<'a> BMSTART_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `BMSTALL` reader - Block Mode Stall Enable"] +pub struct BMSTALL_R(crate::FieldReader); +impl BMSTALL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BMSTALL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BMSTALL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BMSTALL` writer - Block Mode Stall Enable"] +pub struct BMSTALL_W<'a> { + w: &'a mut W, +} +impl<'a> BMSTALL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MDLYCAP` reader - Master Delayed Capture Enable"] +pub struct MDLYCAP_R(crate::FieldReader); +impl MDLYCAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MDLYCAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MDLYCAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MDLYCAP` writer - Master Delayed Capture Enable"] +pub struct MDLYCAP_W<'a> { + w: &'a mut W, +} +impl<'a> MDLYCAP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `MTXPAUSE` reader - Master Tx Pause Enable"] +pub struct MTXPAUSE_R(crate::FieldReader); +impl MTXPAUSE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MTXPAUSE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MTXPAUSE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MTXPAUSE` writer - Master Tx Pause Enable"] +pub struct MTXPAUSE_W<'a> { + w: &'a mut W, +} +impl<'a> MTXPAUSE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Loop Back"] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave output Disable"] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:6 - Slave Select"] + #[inline(always)] + pub fn ss(&self) -> SS_R { + SS_R::new(((self.bits >> 4) & 0x07) as u8) + } + #[doc = "Bit 7 - Block Mode Enable"] + #[inline(always)] + pub fn blockmode(&self) -> BLOCKMODE_R { + BLOCKMODE_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Block Mode Start Status Enable"] + #[inline(always)] + pub fn bmstart(&self) -> BMSTART_R { + BMSTART_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Block Mode Stall Enable"] + #[inline(always)] + pub fn bmstall(&self) -> BMSTALL_R { + BMSTALL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Master Delayed Capture Enable"] + #[inline(always)] + pub fn mdlycap(&self) -> MDLYCAP_R { + MDLYCAP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Master Tx Pause Enable"] + #[inline(always)] + pub fn mtxpause(&self) -> MTXPAUSE_R { + MTXPAUSE_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop Back"] + #[inline(always)] + pub fn lbm(&mut self) -> LBM_W { + LBM_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] + #[inline(always)] + pub fn ms(&mut self) -> MS_W { + MS_W { w: self } + } + #[doc = "Bit 3 - Slave output Disable"] + #[inline(always)] + pub fn sod(&mut self) -> SOD_W { + SOD_W { w: self } + } + #[doc = "Bits 4:6 - Slave Select"] + #[inline(always)] + pub fn ss(&mut self) -> SS_W { + SS_W { w: self } + } + #[doc = "Bit 7 - Block Mode Enable"] + #[inline(always)] + pub fn blockmode(&mut self) -> BLOCKMODE_W { + BLOCKMODE_W { w: self } + } + #[doc = "Bit 8 - Block Mode Start Status Enable"] + #[inline(always)] + pub fn bmstart(&mut self) -> BMSTART_W { + BMSTART_W { w: self } + } + #[doc = "Bit 9 - Block Mode Stall Enable"] + #[inline(always)] + pub fn bmstall(&mut self) -> BMSTALL_W { + BMSTALL_W { w: self } + } + #[doc = "Bit 10 - Master Delayed Capture Enable"] + #[inline(always)] + pub fn mdlycap(&mut self) -> MDLYCAP_W { + MDLYCAP_W { w: self } + } + #[doc = "Bit 11 - Master Tx Pause Enable"] + #[inline(always)] + pub fn mtxpause(&mut self) -> MTXPAUSE_W { + MTXPAUSE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl1](index.html) module"] +pub struct CTRL1_SPEC; +impl crate::RegisterSpec for CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl1::R](R) reader structure"] +impl crate::Readable for CTRL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl1::W](W) writer structure"] +impl crate::Writable for CTRL1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for CTRL1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/data.rs b/src/spi0/data.rs new file mode 100644 index 0000000..31777b9 --- /dev/null +++ b/src/spi0/data.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Input/Output\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/fifo_clr.rs b/src/spi0/fifo_clr.rs new file mode 100644 index 0000000..3d95fdd --- /dev/null +++ b/src/spi0/fifo_clr.rs @@ -0,0 +1,99 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub struct RXFIFO_W<'a> { + w: &'a mut W, +} +impl<'a> RXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub struct TXFIFO_W<'a> { + w: &'a mut W, +} +impl<'a> TXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RXFIFO_W { + RXFIFO_W { w: self } + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TXFIFO_W { + TXFIFO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear FIFO Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_clr](index.html) module"] +pub struct FIFO_CLR_SPEC; +impl crate::RegisterSpec for FIFO_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [fifo_clr::W](W) writer structure"] +impl crate::Writable for FIFO_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FIFO_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/irq_clr.rs b/src/spi0/irq_clr.rs new file mode 100644 index 0000000..14ca32b --- /dev/null +++ b/src/spi0/irq_clr.rs @@ -0,0 +1,153 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RORIM` writer - RX Overrun"] +pub struct RORIM_W<'a> { + w: &'a mut W, +} +impl<'a> RORIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RTIM` writer - RX Timeout"] +pub struct RTIM_W<'a> { + w: &'a mut W, +} +impl<'a> RTIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXIM` writer - RX Fifo is at least half full"] +pub struct RXIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TXIM` writer - TX Fifo is at least half empty"] +pub struct TXIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +impl W { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W { w: self } + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W { w: self } + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W { w: self } + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear Interrupt Status Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"] +pub struct IRQ_CLR_SPEC; +impl crate::RegisterSpec for IRQ_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"] +impl crate::Writable for IRQ_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IRQ_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/irq_enb.rs b/src/spi0/irq_enb.rs new file mode 100644 index 0000000..ebe47c6 --- /dev/null +++ b/src/spi0/irq_enb.rs @@ -0,0 +1,254 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_ENB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RORIM` reader - RX Overrun"] +pub struct RORIM_R(crate::FieldReader); +impl RORIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RORIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RORIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RORIM` writer - RX Overrun"] +pub struct RORIM_W<'a> { + w: &'a mut W, +} +impl<'a> RORIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `RTIM` reader - RX Timeout"] +pub struct RTIM_R(crate::FieldReader); +impl RTIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTIM` writer - RX Timeout"] +pub struct RTIM_W<'a> { + w: &'a mut W, +} +impl<'a> RTIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXIM` reader - RX Fifo is at least half full"] +pub struct RXIM_R(crate::FieldReader); +impl RXIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXIM` writer - RX Fifo is at least half full"] +pub struct RXIM_W<'a> { + w: &'a mut W, +} +impl<'a> RXIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"] +pub struct TXIM_R(crate::FieldReader); +impl TXIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXIM` writer - TX Fifo is at least half empty"] +pub struct TXIM_W<'a> { + w: &'a mut W, +} +impl<'a> TXIM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +impl R { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W { w: self } + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W { w: self } + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W { w: self } + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"] +pub struct IRQ_ENB_SPEC; +impl crate::RegisterSpec for IRQ_ENB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_enb::R](R) reader structure"] +impl crate::Readable for IRQ_ENB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"] +impl crate::Writable for IRQ_ENB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IRQ_ENB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/irq_end.rs b/src/spi0/irq_end.rs new file mode 100644 index 0000000..22b34dc --- /dev/null +++ b/src/spi0/irq_end.rs @@ -0,0 +1,113 @@ +#[doc = "Register `IRQ_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RORIM` reader - RX Overrun"] +pub struct RORIM_R(crate::FieldReader); +impl RORIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RORIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RORIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTIM` reader - RX Timeout"] +pub struct RTIM_R(crate::FieldReader); +impl RTIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXIM` reader - RX Fifo is at least half full"] +pub struct RXIM_R(crate::FieldReader); +impl RXIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"] +pub struct TXIM_R(crate::FieldReader); +impl TXIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Enabled Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"] +pub struct IRQ_END_SPEC; +impl crate::RegisterSpec for IRQ_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_end::R](R) reader structure"] +impl crate::Readable for IRQ_END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IRQ_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/irq_raw.rs b/src/spi0/irq_raw.rs new file mode 100644 index 0000000..bc608c7 --- /dev/null +++ b/src/spi0/irq_raw.rs @@ -0,0 +1,113 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RORIM` reader - RX Overrun"] +pub struct RORIM_R(crate::FieldReader); +impl RORIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RORIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RORIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTIM` reader - RX Timeout"] +pub struct RTIM_R(crate::FieldReader); +impl RTIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RTIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXIM` reader - RX Fifo is at least half full"] +pub struct RXIM_R(crate::FieldReader); +impl RXIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"] +pub struct TXIM_R(crate::FieldReader); +impl TXIM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXIM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXIM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"] +pub struct IRQ_RAW_SPEC; +impl crate::RegisterSpec for IRQ_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_raw::R](R) reader structure"] +impl crate::Readable for IRQ_RAW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_RAW to value 0"] +impl crate::Resettable for IRQ_RAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/perid.rs b/src/spi0/perid.rs new file mode 100644 index 0000000..080145f --- /dev/null +++ b/src/spi0/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0213_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0213_07e9 + } +} diff --git a/src/spi0/rxfifoirqtrg.rs b/src/spi0/rxfifoirqtrg.rs new file mode 100644 index 0000000..fb4d239 --- /dev/null +++ b/src/spi0/rxfifoirqtrg.rs @@ -0,0 +1,64 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifoirqtrg](index.html) module"] +pub struct RXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for RXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxfifoirqtrg::R](R) reader structure"] +impl crate::Readable for RXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxfifoirqtrg::W](W) writer structure"] +impl crate::Writable for RXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/state.rs b/src/spi0/state.rs new file mode 100644 index 0000000..266b71a --- /dev/null +++ b/src/spi0/state.rs @@ -0,0 +1,31 @@ +#[doc = "Register `STATE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Internal STATE of SPI Controller\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [state](index.html) module"] +pub struct STATE_SPEC; +impl crate::RegisterSpec for STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [state::R](R) reader structure"] +impl crate::Readable for STATE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for STATE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/status.rs b/src/spi0/status.rs new file mode 100644 index 0000000..916b025 --- /dev/null +++ b/src/spi0/status.rs @@ -0,0 +1,193 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `TFE` reader - Transmit FIFO empty"] +pub struct TFE_R(crate::FieldReader); +impl TFE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TFE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TFE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TNF` reader - Transmit FIFO not full"] +pub struct TNF_R(crate::FieldReader); +impl TNF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TNF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TNF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RNE` reader - Receive FIFO not empty"] +pub struct RNE_R(crate::FieldReader); +impl RNE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RNE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RNE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RFF` reader - Receive FIFO Full"] +pub struct RFF_R(crate::FieldReader); +impl RFF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RFF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RFF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte in BLOCKMODE"] +pub struct RXDATAFIRST_R(crate::FieldReader); +impl RXDATAFIRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXDATAFIRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXDATAFIRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub struct RXTRIGGER_R(crate::FieldReader); +impl RXTRIGGER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXTRIGGER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXTRIGGER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub struct TXTRIGGER_R(crate::FieldReader); +impl TXTRIGGER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXTRIGGER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXTRIGGER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Transmit FIFO empty"] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full"] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty"] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Receive FIFO Full"] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Data is first Byte in BLOCKMODE"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RXDATAFIRST_R { + RXDATAFIRST_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RXTRIGGER_R { + RXTRIGGER_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TXTRIGGER_R { + TXTRIGGER_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spi0/txfifoirqtrg.rs b/src/spi0/txfifoirqtrg.rs new file mode 100644 index 0000000..a88c823 --- /dev/null +++ b/src/spi0/txfifoirqtrg.rs @@ -0,0 +1,64 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfifoirqtrg](index.html) module"] +pub struct TXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for TXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txfifoirqtrg::R](R) reader structure"] +impl crate::Readable for TXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txfifoirqtrg::W](W) writer structure"] +impl crate::Writable for TXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spw.rs b/src/spw.rs new file mode 100644 index 0000000..480153d --- /dev/null +++ b/src/spw.rs @@ -0,0 +1,77 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control Register"] + pub ctrl: crate::Reg, + #[doc = "0x04 - Status/Interrupt Source Register"] + pub sts: crate::Reg, + #[doc = "0x08 - Node Address Register"] + pub defaddr: crate::Reg, + #[doc = "0x0c - Clock Divisor Register"] + pub clkdiv: crate::Reg, + #[doc = "0x10 - Destination Key"] + pub dkey: crate::Reg, + #[doc = "0x14 - Time Code Register"] + pub tc: crate::Reg, + #[doc = "0x18 - Timer and Disconnect Register"] + pub tdr: crate::Reg, + _reserved7: [u8; 0x04], + #[doc = "0x20 - DMA Control Register"] + pub dmactrl0: crate::Reg, + #[doc = "0x24 - DMA RX Maximum Length Register"] + pub dmamaxlen0: crate::Reg, + #[doc = "0x28 - DMA Transmitter Descriptor Table Address Register"] + pub dmatxdesc0: crate::Reg, + #[doc = "0x2c - DMA Receiver Table Destination Register"] + pub dmarxdesc0: crate::Reg, + #[doc = "0x30 - DMA Receiver Table Address Register"] + pub dmaaddr0: crate::Reg, +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "STS register accessor: an alias for `Reg`"] +pub type STS = crate::Reg; +#[doc = "Status/Interrupt Source Register"] +pub mod sts; +#[doc = "DEFADDR register accessor: an alias for `Reg`"] +pub type DEFADDR = crate::Reg; +#[doc = "Node Address Register"] +pub mod defaddr; +#[doc = "CLKDIV register accessor: an alias for `Reg`"] +pub type CLKDIV = crate::Reg; +#[doc = "Clock Divisor Register"] +pub mod clkdiv; +#[doc = "DKEY register accessor: an alias for `Reg`"] +pub type DKEY = crate::Reg; +#[doc = "Destination Key"] +pub mod dkey; +#[doc = "TC register accessor: an alias for `Reg`"] +pub type TC = crate::Reg; +#[doc = "Time Code Register"] +pub mod tc; +#[doc = "TDR register accessor: an alias for `Reg`"] +pub type TDR = crate::Reg; +#[doc = "Timer and Disconnect Register"] +pub mod tdr; +#[doc = "DMACTRL0 register accessor: an alias for `Reg`"] +pub type DMACTRL0 = crate::Reg; +#[doc = "DMA Control Register"] +pub mod dmactrl0; +#[doc = "DMAMAXLEN0 register accessor: an alias for `Reg`"] +pub type DMAMAXLEN0 = crate::Reg; +#[doc = "DMA RX Maximum Length Register"] +pub mod dmamaxlen0; +#[doc = "DMATXDESC0 register accessor: an alias for `Reg`"] +pub type DMATXDESC0 = crate::Reg; +#[doc = "DMA Transmitter Descriptor Table Address Register"] +pub mod dmatxdesc0; +#[doc = "DMARXDESC0 register accessor: an alias for `Reg`"] +pub type DMARXDESC0 = crate::Reg; +#[doc = "DMA Receiver Table Destination Register"] +pub mod dmarxdesc0; +#[doc = "DMAADDR0 register accessor: an alias for `Reg`"] +pub type DMAADDR0 = crate::Reg; +#[doc = "DMA Receiver Table Address Register"] +pub mod dmaaddr0; diff --git a/src/spw/clkdiv.rs b/src/spw/clkdiv.rs new file mode 100644 index 0000000..3fa3603 --- /dev/null +++ b/src/spw/clkdiv.rs @@ -0,0 +1,140 @@ +#[doc = "Register `CLKDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLKDIVSTART` reader - 8-bit Clock divisor value used for the clock-divider during startup"] +pub struct CLKDIVSTART_R(crate::FieldReader); +impl CLKDIVSTART_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CLKDIVSTART_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKDIVSTART_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKDIVSTART` writer - 8-bit Clock divisor value used for the clock-divider during startup"] +pub struct CLKDIVSTART_W<'a> { + w: &'a mut W, +} +impl<'a> CLKDIVSTART_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `CLKDIVRUN` reader - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] +pub struct CLKDIVRUN_R(crate::FieldReader); +impl CLKDIVRUN_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CLKDIVRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKDIVRUN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKDIVRUN` writer - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] +pub struct CLKDIVRUN_W<'a> { + w: &'a mut W, +} +impl<'a> CLKDIVRUN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - 8-bit Clock divisor value used for the clock-divider during startup"] + #[inline(always)] + pub fn clkdivstart(&self) -> CLKDIVSTART_R { + CLKDIVSTART_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] + #[inline(always)] + pub fn clkdivrun(&self) -> CLKDIVRUN_R { + CLKDIVRUN_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - 8-bit Clock divisor value used for the clock-divider during startup"] + #[inline(always)] + pub fn clkdivstart(&mut self) -> CLKDIVSTART_W { + CLKDIVSTART_W { w: self } + } + #[doc = "Bits 0:7 - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] + #[inline(always)] + pub fn clkdivrun(&mut self) -> CLKDIVRUN_W { + CLKDIVRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Divisor Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkdiv](index.html) module"] +pub struct CLKDIV_SPEC; +impl crate::RegisterSpec for CLKDIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkdiv::R](R) reader structure"] +impl crate::Readable for CLKDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkdiv::W](W) writer structure"] +impl crate::Writable for CLKDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKDIV to value 0x0909"] +impl crate::Resettable for CLKDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0909 + } +} diff --git a/src/spw/ctrl.rs b/src/spw/ctrl.rs new file mode 100644 index 0000000..cd00e1b --- /dev/null +++ b/src/spw/ctrl.rs @@ -0,0 +1,1119 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RA` reader - Reads as 1 if the RMAP command handler is available"] +pub struct RA_R(crate::FieldReader); +impl RA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RX` reader - Reads as 1 if unaligned writes are available for the receiver"] +pub struct RX_R(crate::FieldReader); +impl RX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RC` reader - Reads as 1 if RMAP CRC is enabled in the core"] +pub struct RC_R(crate::FieldReader); +impl RC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NCH` reader - Number of DMA Channels minus one"] +pub struct NCH_R(crate::FieldReader); +impl NCH_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NCH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NCH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PO` reader - The number of available SpaceWire ports minus one"] +pub struct PO_R(crate::FieldReader); +impl PO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CC` reader - CCSDS/CCITT CRC-16"] +pub struct CC_R(crate::FieldReader); +impl CC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Interrupt distribution available"] +pub struct ID_R(crate::FieldReader); +impl ID_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LE` reader - Loop-back Enable"] +pub struct LE_R(crate::FieldReader); +impl LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LE` writer - Loop-back Enable"] +pub struct LE_W<'a> { + w: &'a mut W, +} +impl<'a> LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `PS` reader - Selects the active port when the no port force bit is zero"] +pub struct PS_R(crate::FieldReader); +impl PS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PS` writer - Selects the active port when the no port force bit is zero"] +pub struct PS_W<'a> { + w: &'a mut W, +} +impl<'a> PS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `NP` reader - Disable port force"] +pub struct NP_R(crate::FieldReader); +impl NP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NP` writer - Disable port force"] +pub struct NP_W<'a> { + w: &'a mut W, +} +impl<'a> NP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `PNPA` reader - SpW Plug-and-Play Available"] +pub struct PNPA_R(crate::FieldReader); +impl PNPA_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PNPA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PNPA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RD` reader - If set only one RMAP buffer is used"] +pub struct RD_R(crate::FieldReader); +impl RD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RD` writer - If set only one RMAP buffer is used"] +pub struct RD_W<'a> { + w: &'a mut W, +} +impl<'a> RD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `RE` reader - Enable RMAP command handler"] +pub struct RE_R(crate::FieldReader); +impl RE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RE` writer - Enable RMAP command handler"] +pub struct RE_W<'a> { + w: &'a mut W, +} +impl<'a> RE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `PE` reader - SpW Plug-and-Play Enable"] +pub struct PE_R(crate::FieldReader); +impl PE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PE` writer - SpW Plug-and-Play Enable"] +pub struct PE_W<'a> { + w: &'a mut W, +} +impl<'a> PE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TL` reader - Transmitter Enable Lock Control"] +pub struct TL_R(crate::FieldReader); +impl TL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TL` writer - Transmitter Enable Lock Control"] +pub struct TL_W<'a> { + w: &'a mut W, +} +impl<'a> TL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TF` reader - Time-code Flag Filter"] +pub struct TF_R(crate::FieldReader); +impl TF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TF` writer - Time-code Flag Filter"] +pub struct TF_W<'a> { + w: &'a mut W, +} +impl<'a> TF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TR` reader - Enable time-code receptions"] +pub struct TR_R(crate::FieldReader); +impl TR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TR` writer - Enable time-code receptions"] +pub struct TR_W<'a> { + w: &'a mut W, +} +impl<'a> TR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TT` reader - Enable time-code transmissions"] +pub struct TT_R(crate::FieldReader); +impl TT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TT` writer - Enable time-code transmissions"] +pub struct TT_W<'a> { + w: &'a mut W, +} +impl<'a> TT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LI` reader - Generate interrupt when link error occurs"] +pub struct LI_R(crate::FieldReader); +impl LI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LI` writer - Generate interrupt when link error occurs"] +pub struct LI_W<'a> { + w: &'a mut W, +} +impl<'a> LI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TQ` reader - Generate interrupt when a valid time-code is received"] +pub struct TQ_R(crate::FieldReader); +impl TQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TQ` writer - Generate interrupt when a valid time-code is received"] +pub struct TQ_W<'a> { + w: &'a mut W, +} +impl<'a> TQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RS` reader - Make complete reset of the SpaceWire node. Self-clearing"] +pub struct RS_R(crate::FieldReader); +impl RS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RS` writer - Make complete reset of the SpaceWire node. Self-clearing"] +pub struct RS_W<'a> { + w: &'a mut W, +} +impl<'a> RS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PM` reader - Enable Promiscuous mode"] +pub struct PM_R(crate::FieldReader); +impl PM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM` writer - Enable Promiscuous mode"] +pub struct PM_W<'a> { + w: &'a mut W, +} +impl<'a> PM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `TI` reader - The host can generate a tick by writing a one to this field"] +pub struct TI_R(crate::FieldReader); +impl TI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TI` writer - The host can generate a tick by writing a one to this field"] +pub struct TI_W<'a> { + w: &'a mut W, +} +impl<'a> TI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `IE` reader - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] +pub struct IE_R(crate::FieldReader); +impl IE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IE` writer - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] +pub struct IE_W<'a> { + w: &'a mut W, +} +impl<'a> IE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `AS` reader - Automatically start the link when a NULL has been received"] +pub struct AS_R(crate::FieldReader); +impl AS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AS` writer - Automatically start the link when a NULL has been received"] +pub struct AS_W<'a> { + w: &'a mut W, +} +impl<'a> AS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LS` reader - Start the link"] +pub struct LS_R(crate::FieldReader); +impl LS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LS` writer - Start the link"] +pub struct LS_W<'a> { + w: &'a mut W, +} +impl<'a> LS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `LD` reader - Disable the SpaceWire CODEC"] +pub struct LD_R(crate::FieldReader); +impl LD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LD` writer - Disable the SpaceWire CODEC"] +pub struct LD_W<'a> { + w: &'a mut W, +} +impl<'a> LD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 31 - Reads as 1 if the RMAP command handler is available"] + #[inline(always)] + pub fn ra(&self) -> RA_R { + RA_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bit 30 - Reads as 1 if unaligned writes are available for the receiver"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 30) & 0x01) != 0) + } + #[doc = "Bit 29 - Reads as 1 if RMAP CRC is enabled in the core"] + #[inline(always)] + pub fn rc(&self) -> RC_R { + RC_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bits 27:28 - Number of DMA Channels minus one"] + #[inline(always)] + pub fn nch(&self) -> NCH_R { + NCH_R::new(((self.bits >> 27) & 0x03) as u8) + } + #[doc = "Bit 26 - The number of available SpaceWire ports minus one"] + #[inline(always)] + pub fn po(&self) -> PO_R { + PO_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 25 - CCSDS/CCITT CRC-16"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 24 - Interrupt distribution available"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 22 - Loop-back Enable"] + #[inline(always)] + pub fn le(&self) -> LE_R { + LE_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 21 - Selects the active port when the no port force bit is zero"] + #[inline(always)] + pub fn ps(&self) -> PS_R { + PS_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 20 - Disable port force"] + #[inline(always)] + pub fn np(&self) -> NP_R { + NP_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bits 18:19 - SpW Plug-and-Play Available"] + #[inline(always)] + pub fn pnpa(&self) -> PNPA_R { + PNPA_R::new(((self.bits >> 18) & 0x03) as u8) + } + #[doc = "Bit 17 - If set only one RMAP buffer is used"] + #[inline(always)] + pub fn rd(&self) -> RD_R { + RD_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 16 - Enable RMAP command handler"] + #[inline(always)] + pub fn re(&self) -> RE_R { + RE_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 15 - SpW Plug-and-Play Enable"] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 13 - Transmitter Enable Lock Control"] + #[inline(always)] + pub fn tl(&self) -> TL_R { + TL_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 12 - Time-code Flag Filter"] + #[inline(always)] + pub fn tf(&self) -> TF_R { + TF_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable time-code receptions"] + #[inline(always)] + pub fn tr(&self) -> TR_R { + TR_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - Enable time-code transmissions"] + #[inline(always)] + pub fn tt(&self) -> TT_R { + TT_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - Generate interrupt when link error occurs"] + #[inline(always)] + pub fn li(&self) -> LI_R { + LI_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - Generate interrupt when a valid time-code is received"] + #[inline(always)] + pub fn tq(&self) -> TQ_R { + TQ_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 6 - Make complete reset of the SpaceWire node. Self-clearing"] + #[inline(always)] + pub fn rs(&self) -> RS_R { + RS_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Enable Promiscuous mode"] + #[inline(always)] + pub fn pm(&self) -> PM_R { + PM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - The host can generate a tick by writing a one to this field"] + #[inline(always)] + pub fn ti(&self) -> TI_R { + TI_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Automatically start the link when a NULL has been received"] + #[inline(always)] + pub fn as_(&self) -> AS_R { + AS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Start the link"] + #[inline(always)] + pub fn ls(&self) -> LS_R { + LS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Disable the SpaceWire CODEC"] + #[inline(always)] + pub fn ld(&self) -> LD_R { + LD_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 22 - Loop-back Enable"] + #[inline(always)] + pub fn le(&mut self) -> LE_W { + LE_W { w: self } + } + #[doc = "Bit 21 - Selects the active port when the no port force bit is zero"] + #[inline(always)] + pub fn ps(&mut self) -> PS_W { + PS_W { w: self } + } + #[doc = "Bit 20 - Disable port force"] + #[inline(always)] + pub fn np(&mut self) -> NP_W { + NP_W { w: self } + } + #[doc = "Bit 17 - If set only one RMAP buffer is used"] + #[inline(always)] + pub fn rd(&mut self) -> RD_W { + RD_W { w: self } + } + #[doc = "Bit 16 - Enable RMAP command handler"] + #[inline(always)] + pub fn re(&mut self) -> RE_W { + RE_W { w: self } + } + #[doc = "Bit 15 - SpW Plug-and-Play Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PE_W { + PE_W { w: self } + } + #[doc = "Bit 13 - Transmitter Enable Lock Control"] + #[inline(always)] + pub fn tl(&mut self) -> TL_W { + TL_W { w: self } + } + #[doc = "Bit 12 - Time-code Flag Filter"] + #[inline(always)] + pub fn tf(&mut self) -> TF_W { + TF_W { w: self } + } + #[doc = "Bit 11 - Enable time-code receptions"] + #[inline(always)] + pub fn tr(&mut self) -> TR_W { + TR_W { w: self } + } + #[doc = "Bit 10 - Enable time-code transmissions"] + #[inline(always)] + pub fn tt(&mut self) -> TT_W { + TT_W { w: self } + } + #[doc = "Bit 9 - Generate interrupt when link error occurs"] + #[inline(always)] + pub fn li(&mut self) -> LI_W { + LI_W { w: self } + } + #[doc = "Bit 8 - Generate interrupt when a valid time-code is received"] + #[inline(always)] + pub fn tq(&mut self) -> TQ_W { + TQ_W { w: self } + } + #[doc = "Bit 6 - Make complete reset of the SpaceWire node. Self-clearing"] + #[inline(always)] + pub fn rs(&mut self) -> RS_W { + RS_W { w: self } + } + #[doc = "Bit 5 - Enable Promiscuous mode"] + #[inline(always)] + pub fn pm(&mut self) -> PM_W { + PM_W { w: self } + } + #[doc = "Bit 4 - The host can generate a tick by writing a one to this field"] + #[inline(always)] + pub fn ti(&mut self) -> TI_W { + TI_W { w: self } + } + #[doc = "Bit 3 - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] + #[inline(always)] + pub fn ie(&mut self) -> IE_W { + IE_W { w: self } + } + #[doc = "Bit 2 - Automatically start the link when a NULL has been received"] + #[inline(always)] + pub fn as_(&mut self) -> AS_W { + AS_W { w: self } + } + #[doc = "Bit 1 - Start the link"] + #[inline(always)] + pub fn ls(&mut self) -> LS_W { + LS_W { w: self } + } + #[doc = "Bit 0 - Disable the SpaceWire CODEC"] + #[inline(always)] + pub fn ld(&mut self) -> LD_W { + LD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0xa201_0004"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xa201_0004 + } +} diff --git a/src/spw/defaddr.rs b/src/spw/defaddr.rs new file mode 100644 index 0000000..a746c11 --- /dev/null +++ b/src/spw/defaddr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DEFADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEFADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DEFMASK` reader - 8-bit default mask used for node identification on the SpaceWire network"] +pub struct DEFMASK_R(crate::FieldReader); +impl DEFMASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEFMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFMASK` writer - 8-bit default mask used for node identification on the SpaceWire network"] +pub struct DEFMASK_W<'a> { + w: &'a mut W, +} +impl<'a> DEFMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `DEFADDR` reader - 8-bit node address used for node identification on the SpaceWire network"] +pub struct DEFADDR_R(crate::FieldReader); +impl DEFADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DEFADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEFADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFADDR` writer - 8-bit node address used for node identification on the SpaceWire network"] +pub struct DEFADDR_W<'a> { + w: &'a mut W, +} +impl<'a> DEFADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - 8-bit default mask used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defmask(&self) -> DEFMASK_R { + DEFMASK_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - 8-bit node address used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defaddr(&self) -> DEFADDR_R { + DEFADDR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - 8-bit default mask used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defmask(&mut self) -> DEFMASK_W { + DEFMASK_W { w: self } + } + #[doc = "Bits 0:7 - 8-bit node address used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defaddr(&mut self) -> DEFADDR_W { + DEFADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Node Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [defaddr](index.html) module"] +pub struct DEFADDR_SPEC; +impl crate::RegisterSpec for DEFADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [defaddr::R](R) reader structure"] +impl crate::Readable for DEFADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [defaddr::W](W) writer structure"] +impl crate::Writable for DEFADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DEFADDR to value 0xfe"] +impl crate::Resettable for DEFADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xfe + } +} diff --git a/src/spw/dkey.rs b/src/spw/dkey.rs new file mode 100644 index 0000000..a9543e3 --- /dev/null +++ b/src/spw/dkey.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DKEY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DKEY` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESTKEY` reader - RMAP destination key"] +pub struct DESTKEY_R(crate::FieldReader); +impl DESTKEY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DESTKEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESTKEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESTKEY` writer - RMAP destination key"] +pub struct DESTKEY_W<'a> { + w: &'a mut W, +} +impl<'a> DESTKEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - RMAP destination key"] + #[inline(always)] + pub fn destkey(&self) -> DESTKEY_R { + DESTKEY_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - RMAP destination key"] + #[inline(always)] + pub fn destkey(&mut self) -> DESTKEY_W { + DESTKEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Destination Key\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dkey](index.html) module"] +pub struct DKEY_SPEC; +impl crate::RegisterSpec for DKEY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dkey::R](R) reader structure"] +impl crate::Readable for DKEY_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dkey::W](W) writer structure"] +impl crate::Writable for DKEY_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DKEY to value 0"] +impl crate::Resettable for DKEY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spw/dmaaddr0.rs b/src/spw/dmaaddr0.rs new file mode 100644 index 0000000..b783df4 --- /dev/null +++ b/src/spw/dmaaddr0.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DMAADDR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMAADDR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Mask"] +pub struct MASK_R(crate::FieldReader); +impl MASK_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MASK` writer - Mask"] +pub struct MASK_W<'a> { + w: &'a mut W, +} +impl<'a> MASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `ADDR` reader - Address"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 8:15 - Mask"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 0:7 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 8:15 - Mask"] + #[inline(always)] + pub fn mask(&mut self) -> MASK_W { + MASK_W { w: self } + } + #[doc = "Bits 0:7 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Receiver Table Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmaaddr0](index.html) module"] +pub struct DMAADDR0_SPEC; +impl crate::RegisterSpec for DMAADDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmaaddr0::R](R) reader structure"] +impl crate::Readable for DMAADDR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmaaddr0::W](W) writer structure"] +impl crate::Writable for DMAADDR0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMAADDR0 to value 0"] +impl crate::Resettable for DMAADDR0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spw/dmactrl0.rs b/src/spw/dmactrl0.rs new file mode 100644 index 0000000..5a76a63 --- /dev/null +++ b/src/spw/dmactrl0.rs @@ -0,0 +1,1177 @@ +#[doc = "Register `DMACTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMACTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INTNUM` reader - Interrupt number used for this channel"] +pub struct INTNUM_R(crate::FieldReader); +impl INTNUM_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + INTNUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INTNUM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTNUM` writer - Interrupt number used for this channel"] +pub struct INTNUM_W<'a> { + w: &'a mut W, +} +impl<'a> INTNUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 26)) | ((value as u32 & 0x3f) << 26); + self.w + } +} +#[doc = "Field `EP` reader - EEP Termination"] +pub struct EP_R(crate::FieldReader); +impl EP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EP` writer - EEP Termination"] +pub struct EP_W<'a> { + w: &'a mut W, +} +impl<'a> EP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `TR` reader - Truncated"] +pub struct TR_R(crate::FieldReader); +impl TR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TR` writer - Truncated"] +pub struct TR_W<'a> { + w: &'a mut W, +} +impl<'a> TR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `IE` reader - Interrupt code transmit enable on EEP"] +pub struct IE_R(crate::FieldReader); +impl IE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IE` writer - Interrupt code transmit enable on EEP"] +pub struct IE_W<'a> { + w: &'a mut W, +} +impl<'a> IE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `IT` reader - Interrupt code transmit enable on truncation"] +pub struct IT_R(crate::FieldReader); +impl IT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IT` writer - Interrupt code transmit enable on truncation"] +pub struct IT_W<'a> { + w: &'a mut W, +} +impl<'a> IT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `RP` reader - Receive Packet IRQ"] +pub struct RP_R(crate::FieldReader); +impl RP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RP` writer - Receive Packet IRQ"] +pub struct RP_W<'a> { + w: &'a mut W, +} +impl<'a> RP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `TP` reader - Transmit Packet IRQ"] +pub struct TP_R(crate::FieldReader); +impl TP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TP` writer - Transmit Packet IRQ"] +pub struct TP_W<'a> { + w: &'a mut W, +} +impl<'a> TP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `TL` reader - Transmit Enable Lock"] +pub struct TL_R(crate::FieldReader); +impl TL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TL` writer - Transmit Enable Lock"] +pub struct TL_W<'a> { + w: &'a mut W, +} +impl<'a> TL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `LE` reader - Disable transmitter when a link error occurs"] +pub struct LE_R(crate::FieldReader); +impl LE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LE` writer - Disable transmitter when a link error occurs"] +pub struct LE_W<'a> { + w: &'a mut W, +} +impl<'a> LE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `SP` reader - Strip PID"] +pub struct SP_R(crate::FieldReader); +impl SP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SP` writer - Strip PID"] +pub struct SP_W<'a> { + w: &'a mut W, +} +impl<'a> SP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `SA` reader - Strip Address"] +pub struct SA_R(crate::FieldReader); +impl SA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SA` writer - Strip Address"] +pub struct SA_W<'a> { + w: &'a mut W, +} +impl<'a> SA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `EN` reader - Enable Address"] +pub struct EN_R(crate::FieldReader); +impl EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EN` writer - Enable Address"] +pub struct EN_W<'a> { + w: &'a mut W, +} +impl<'a> EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `NS` reader - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] +pub struct NS_R(crate::FieldReader); +impl NS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + NS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NS` writer - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] +pub struct NS_W<'a> { + w: &'a mut W, +} +impl<'a> NS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `RD` reader - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] +pub struct RD_R(crate::FieldReader); +impl RD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RD` writer - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] +pub struct RD_W<'a> { + w: &'a mut W, +} +impl<'a> RD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `RX` reader - Reception to the DMA channel is currently active"] +pub struct RX_R(crate::FieldReader); +impl RX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AT` reader - Abort the currently transmitting packet and disable transmissions"] +pub struct AT_R(crate::FieldReader); +impl AT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RA` reader - An error response was detected on the AHB bus - DMA receive"] +pub struct RA_R(crate::FieldReader); +impl RA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RA` writer - An error response was detected on the AHB bus - DMA receive"] +pub struct RA_W<'a> { + w: &'a mut W, +} +impl<'a> RA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TA` reader - An error response was detected on the AHB bus - DMA transmit"] +pub struct TA_R(crate::FieldReader); +impl TA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TA` writer - An error response was detected on the AHB bus - DMA transmit"] +pub struct TA_W<'a> { + w: &'a mut W, +} +impl<'a> TA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PR` reader - Set each time a packet has been received"] +pub struct PR_R(crate::FieldReader); +impl PR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PR` writer - Set each time a packet has been received"] +pub struct PR_W<'a> { + w: &'a mut W, +} +impl<'a> PR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PS` reader - Set each time a packet has been sent"] +pub struct PS_R(crate::FieldReader); +impl PS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PS` writer - Set each time a packet has been sent"] +pub struct PS_W<'a> { + w: &'a mut W, +} +impl<'a> PS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `AI` reader - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] +pub struct AI_R(crate::FieldReader); +impl AI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AI` writer - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] +pub struct AI_W<'a> { + w: &'a mut W, +} +impl<'a> AI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RI` reader - An interrupt will be generated each time a packet has been received"] +pub struct RI_R(crate::FieldReader); +impl RI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RI` writer - An interrupt will be generated each time a packet has been received"] +pub struct RI_W<'a> { + w: &'a mut W, +} +impl<'a> RI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TI` reader - An interrupt will be generated each time a packet is transmitted"] +pub struct TI_R(crate::FieldReader); +impl TI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TI` writer - An interrupt will be generated each time a packet is transmitted"] +pub struct TI_W<'a> { + w: &'a mut W, +} +impl<'a> TI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RE` reader - Packets are allowed to be received to this channel"] +pub struct RE_R(crate::FieldReader); +impl RE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RE` writer - Packets are allowed to be received to this channel"] +pub struct RE_W<'a> { + w: &'a mut W, +} +impl<'a> RE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TE` reader - Write a one to this bit each time new descriptors are activated in the table"] +pub struct TE_R(crate::FieldReader); +impl TE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TE` writer - Write a one to this bit each time new descriptors are activated in the table"] +pub struct TE_W<'a> { + w: &'a mut W, +} +impl<'a> TE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bits 26:31 - Interrupt number used for this channel"] + #[inline(always)] + pub fn intnum(&self) -> INTNUM_R { + INTNUM_R::new(((self.bits >> 26) & 0x3f) as u8) + } + #[doc = "Bit 23 - EEP Termination"] + #[inline(always)] + pub fn ep(&self) -> EP_R { + EP_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 22 - Truncated"] + #[inline(always)] + pub fn tr(&self) -> TR_R { + TR_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 21 - Interrupt code transmit enable on EEP"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 20 - Interrupt code transmit enable on truncation"] + #[inline(always)] + pub fn it(&self) -> IT_R { + IT_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 19 - Receive Packet IRQ"] + #[inline(always)] + pub fn rp(&self) -> RP_R { + RP_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 18 - Transmit Packet IRQ"] + #[inline(always)] + pub fn tp(&self) -> TP_R { + TP_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 17 - Transmit Enable Lock"] + #[inline(always)] + pub fn tl(&self) -> TL_R { + TL_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 16 - Disable transmitter when a link error occurs"] + #[inline(always)] + pub fn le(&self) -> LE_R { + LE_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 15 - Strip PID"] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 14 - Strip Address"] + #[inline(always)] + pub fn sa(&self) -> SA_R { + SA_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 13 - Enable Address"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 12 - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] + #[inline(always)] + pub fn ns(&self) -> NS_R { + NS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 11 - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] + #[inline(always)] + pub fn rd(&self) -> RD_R { + RD_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 10 - Reception to the DMA channel is currently active"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 9 - Abort the currently transmitting packet and disable transmissions"] + #[inline(always)] + pub fn at(&self) -> AT_R { + AT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - An error response was detected on the AHB bus - DMA receive"] + #[inline(always)] + pub fn ra(&self) -> RA_R { + RA_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 7 - An error response was detected on the AHB bus - DMA transmit"] + #[inline(always)] + pub fn ta(&self) -> TA_R { + TA_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - Set each time a packet has been received"] + #[inline(always)] + pub fn pr(&self) -> PR_R { + PR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 5 - Set each time a packet has been sent"] + #[inline(always)] + pub fn ps(&self) -> PS_R { + PS_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 4 - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] + #[inline(always)] + pub fn ai(&self) -> AI_R { + AI_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - An interrupt will be generated each time a packet has been received"] + #[inline(always)] + pub fn ri(&self) -> RI_R { + RI_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - An interrupt will be generated each time a packet is transmitted"] + #[inline(always)] + pub fn ti(&self) -> TI_R { + TI_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Packets are allowed to be received to this channel"] + #[inline(always)] + pub fn re(&self) -> RE_R { + RE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Write a one to this bit each time new descriptors are activated in the table"] + #[inline(always)] + pub fn te(&self) -> TE_R { + TE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 26:31 - Interrupt number used for this channel"] + #[inline(always)] + pub fn intnum(&mut self) -> INTNUM_W { + INTNUM_W { w: self } + } + #[doc = "Bit 23 - EEP Termination"] + #[inline(always)] + pub fn ep(&mut self) -> EP_W { + EP_W { w: self } + } + #[doc = "Bit 22 - Truncated"] + #[inline(always)] + pub fn tr(&mut self) -> TR_W { + TR_W { w: self } + } + #[doc = "Bit 21 - Interrupt code transmit enable on EEP"] + #[inline(always)] + pub fn ie(&mut self) -> IE_W { + IE_W { w: self } + } + #[doc = "Bit 20 - Interrupt code transmit enable on truncation"] + #[inline(always)] + pub fn it(&mut self) -> IT_W { + IT_W { w: self } + } + #[doc = "Bit 19 - Receive Packet IRQ"] + #[inline(always)] + pub fn rp(&mut self) -> RP_W { + RP_W { w: self } + } + #[doc = "Bit 18 - Transmit Packet IRQ"] + #[inline(always)] + pub fn tp(&mut self) -> TP_W { + TP_W { w: self } + } + #[doc = "Bit 17 - Transmit Enable Lock"] + #[inline(always)] + pub fn tl(&mut self) -> TL_W { + TL_W { w: self } + } + #[doc = "Bit 16 - Disable transmitter when a link error occurs"] + #[inline(always)] + pub fn le(&mut self) -> LE_W { + LE_W { w: self } + } + #[doc = "Bit 15 - Strip PID"] + #[inline(always)] + pub fn sp(&mut self) -> SP_W { + SP_W { w: self } + } + #[doc = "Bit 14 - Strip Address"] + #[inline(always)] + pub fn sa(&mut self) -> SA_W { + SA_W { w: self } + } + #[doc = "Bit 13 - Enable Address"] + #[inline(always)] + pub fn en(&mut self) -> EN_W { + EN_W { w: self } + } + #[doc = "Bit 12 - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] + #[inline(always)] + pub fn ns(&mut self) -> NS_W { + NS_W { w: self } + } + #[doc = "Bit 11 - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] + #[inline(always)] + pub fn rd(&mut self) -> RD_W { + RD_W { w: self } + } + #[doc = "Bit 8 - An error response was detected on the AHB bus - DMA receive"] + #[inline(always)] + pub fn ra(&mut self) -> RA_W { + RA_W { w: self } + } + #[doc = "Bit 7 - An error response was detected on the AHB bus - DMA transmit"] + #[inline(always)] + pub fn ta(&mut self) -> TA_W { + TA_W { w: self } + } + #[doc = "Bit 6 - Set each time a packet has been received"] + #[inline(always)] + pub fn pr(&mut self) -> PR_W { + PR_W { w: self } + } + #[doc = "Bit 5 - Set each time a packet has been sent"] + #[inline(always)] + pub fn ps(&mut self) -> PS_W { + PS_W { w: self } + } + #[doc = "Bit 4 - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] + #[inline(always)] + pub fn ai(&mut self) -> AI_W { + AI_W { w: self } + } + #[doc = "Bit 3 - An interrupt will be generated each time a packet has been received"] + #[inline(always)] + pub fn ri(&mut self) -> RI_W { + RI_W { w: self } + } + #[doc = "Bit 2 - An interrupt will be generated each time a packet is transmitted"] + #[inline(always)] + pub fn ti(&mut self) -> TI_W { + TI_W { w: self } + } + #[doc = "Bit 1 - Packets are allowed to be received to this channel"] + #[inline(always)] + pub fn re(&mut self) -> RE_W { + RE_W { w: self } + } + #[doc = "Bit 0 - Write a one to this bit each time new descriptors are activated in the table"] + #[inline(always)] + pub fn te(&mut self) -> TE_W { + TE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmactrl0](index.html) module"] +pub struct DMACTRL0_SPEC; +impl crate::RegisterSpec for DMACTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmactrl0::R](R) reader structure"] +impl crate::Readable for DMACTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmactrl0::W](W) writer structure"] +impl crate::Writable for DMACTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMACTRL0 to value 0"] +impl crate::Resettable for DMACTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spw/dmamaxlen0.rs b/src/spw/dmamaxlen0.rs new file mode 100644 index 0000000..0905abf --- /dev/null +++ b/src/spw/dmamaxlen0.rs @@ -0,0 +1,103 @@ +#[doc = "Register `DMAMAXLEN0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMAMAXLEN0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXMAXLEN` reader - Receiver packet maximum length in bytes"] +pub struct RXMAXLEN_R(crate::FieldReader); +impl RXMAXLEN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + RXMAXLEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXMAXLEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXMAXLEN` writer - Receiver packet maximum length in bytes"] +pub struct RXMAXLEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXMAXLEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x007f_ffff << 2)) | ((value as u32 & 0x007f_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bits 2:24 - Receiver packet maximum length in bytes"] + #[inline(always)] + pub fn rxmaxlen(&self) -> RXMAXLEN_R { + RXMAXLEN_R::new(((self.bits >> 2) & 0x007f_ffff) as u32) + } +} +impl W { + #[doc = "Bits 2:24 - Receiver packet maximum length in bytes"] + #[inline(always)] + pub fn rxmaxlen(&mut self) -> RXMAXLEN_W { + RXMAXLEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA RX Maximum Length Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmamaxlen0](index.html) module"] +pub struct DMAMAXLEN0_SPEC; +impl crate::RegisterSpec for DMAMAXLEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmamaxlen0::R](R) reader structure"] +impl crate::Readable for DMAMAXLEN0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmamaxlen0::W](W) writer structure"] +impl crate::Writable for DMAMAXLEN0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMAMAXLEN0 to value 0"] +impl crate::Resettable for DMAMAXLEN0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spw/dmarxdesc0.rs b/src/spw/dmarxdesc0.rs new file mode 100644 index 0000000..c9d564b --- /dev/null +++ b/src/spw/dmarxdesc0.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DMARXDESC0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMARXDESC0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESCBASEADDR` reader - Sets the base address of the descriptor table"] +pub struct DESCBASEADDR_R(crate::FieldReader); +impl DESCBASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DESCBASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCBASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCBASEADDR` writer - Sets the base address of the descriptor table"] +pub struct DESCBASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> DESCBASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x003f_ffff << 10)) | ((value as u32 & 0x003f_ffff) << 10); + self.w + } +} +#[doc = "Field `DESCSEL` reader - Offset into the descriptor table"] +pub struct DESCSEL_R(crate::FieldReader); +impl DESCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DESCSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCSEL` writer - Offset into the descriptor table"] +pub struct DESCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DESCSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x7f << 3)) | ((value as u32 & 0x7f) << 3); + self.w + } +} +impl R { + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&self) -> DESCBASEADDR_R { + DESCBASEADDR_R::new(((self.bits >> 10) & 0x003f_ffff) as u32) + } + #[doc = "Bits 3:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&self) -> DESCSEL_R { + DESCSEL_R::new(((self.bits >> 3) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&mut self) -> DESCBASEADDR_W { + DESCBASEADDR_W { w: self } + } + #[doc = "Bits 3:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&mut self) -> DESCSEL_W { + DESCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Receiver Table Destination Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmarxdesc0](index.html) module"] +pub struct DMARXDESC0_SPEC; +impl crate::RegisterSpec for DMARXDESC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmarxdesc0::R](R) reader structure"] +impl crate::Readable for DMARXDESC0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmarxdesc0::W](W) writer structure"] +impl crate::Writable for DMARXDESC0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMARXDESC0 to value 0"] +impl crate::Resettable for DMARXDESC0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spw/dmatxdesc0.rs b/src/spw/dmatxdesc0.rs new file mode 100644 index 0000000..0de1960 --- /dev/null +++ b/src/spw/dmatxdesc0.rs @@ -0,0 +1,140 @@ +#[doc = "Register `DMATXDESC0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DMATXDESC0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESCBASEADDR` reader - Sets the base address of the descriptor table"] +pub struct DESCBASEADDR_R(crate::FieldReader); +impl DESCBASEADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DESCBASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCBASEADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCBASEADDR` writer - Sets the base address of the descriptor table"] +pub struct DESCBASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> DESCBASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x003f_ffff << 10)) | ((value as u32 & 0x003f_ffff) << 10); + self.w + } +} +#[doc = "Field `DESCSEL` reader - Offset into the descriptor table"] +pub struct DESCSEL_R(crate::FieldReader); +impl DESCSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DESCSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DESCSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DESCSEL` writer - Offset into the descriptor table"] +pub struct DESCSEL_W<'a> { + w: &'a mut W, +} +impl<'a> DESCSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 4)) | ((value as u32 & 0x3f) << 4); + self.w + } +} +impl R { + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&self) -> DESCBASEADDR_R { + DESCBASEADDR_R::new(((self.bits >> 10) & 0x003f_ffff) as u32) + } + #[doc = "Bits 4:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&self) -> DESCSEL_R { + DESCSEL_R::new(((self.bits >> 4) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&mut self) -> DESCBASEADDR_W { + DESCBASEADDR_W { w: self } + } + #[doc = "Bits 4:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&mut self) -> DESCSEL_W { + DESCSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DMA Transmitter Descriptor Table Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatxdesc0](index.html) module"] +pub struct DMATXDESC0_SPEC; +impl crate::RegisterSpec for DMATXDESC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dmatxdesc0::R](R) reader structure"] +impl crate::Readable for DMATXDESC0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dmatxdesc0::W](W) writer structure"] +impl crate::Writable for DMATXDESC0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DMATXDESC0 to value 0"] +impl crate::Resettable for DMATXDESC0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spw/sts.rs b/src/spw/sts.rs new file mode 100644 index 0000000..930f6ba --- /dev/null +++ b/src/spw/sts.rs @@ -0,0 +1,600 @@ +#[doc = "Register `STS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRXD` reader - Number of Receive Descriptors"] +pub struct NRXD_R(crate::FieldReader); +impl NRXD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NRXD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NRXD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NRXD` writer - Number of Receive Descriptors"] +pub struct NRXD_W<'a> { + w: &'a mut W, +} +impl<'a> NRXD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 26)) | ((value as u32 & 0x03) << 26); + self.w + } +} +#[doc = "Field `NTXD` reader - Number of Transmit Descriptors"] +pub struct NTXD_R(crate::FieldReader); +impl NTXD_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + NTXD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NTXD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NTXD` writer - Number of Transmit Descriptors"] +pub struct NTXD_W<'a> { + w: &'a mut W, +} +impl<'a> NTXD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `LS` reader - Link State"] +pub struct LS_R(crate::FieldReader); +impl LS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LS` writer - Link State"] +pub struct LS_W<'a> { + w: &'a mut W, +} +impl<'a> LS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 21)) | ((value as u32 & 0x07) << 21); + self.w + } +} +#[doc = "Field `AP` reader - Active port"] +pub struct AP_R(crate::FieldReader); +impl AP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AP` writer - Active port"] +pub struct AP_W<'a> { + w: &'a mut W, +} +impl<'a> AP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EE` reader - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] +pub struct EE_R(crate::FieldReader); +impl EE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EE` writer - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] +pub struct EE_W<'a> { + w: &'a mut W, +} +impl<'a> EE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `IA` reader - Packet is received with an invalid destination address field"] +pub struct IA_R(crate::FieldReader); +impl IA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IA` writer - Packet is received with an invalid destination address field"] +pub struct IA_W<'a> { + w: &'a mut W, +} +impl<'a> IA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WE` reader - A synchronization problem has occurred when receiving NChars"] +pub struct WE_R(crate::FieldReader); +impl WE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WE` writer - A synchronization problem has occurred when receiving NChars"] +pub struct WE_W<'a> { + w: &'a mut W, +} +impl<'a> WE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `PE` reader - Parity error has occurred"] +pub struct PE_R(crate::FieldReader); +impl PE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PE` writer - Parity error has occurred"] +pub struct PE_W<'a> { + w: &'a mut W, +} +impl<'a> PE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DE` reader - Disconnection error has occurred"] +pub struct DE_R(crate::FieldReader); +impl DE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DE` writer - Disconnection error has occurred"] +pub struct DE_W<'a> { + w: &'a mut W, +} +impl<'a> DE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ER` reader - Escape error has occurred"] +pub struct ER_R(crate::FieldReader); +impl ER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ER` writer - Escape error has occurred"] +pub struct ER_W<'a> { + w: &'a mut W, +} +impl<'a> ER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CE` reader - Credit has occurred"] +pub struct CE_R(crate::FieldReader); +impl CE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CE` writer - Credit has occurred"] +pub struct CE_W<'a> { + w: &'a mut W, +} +impl<'a> CE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TO` reader - A new time count value was received"] +pub struct TO_R(crate::FieldReader); +impl TO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TO` writer - A new time count value was received"] +pub struct TO_W<'a> { + w: &'a mut W, +} +impl<'a> TO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bits 26:27 - Number of Receive Descriptors"] + #[inline(always)] + pub fn nrxd(&self) -> NRXD_R { + NRXD_R::new(((self.bits >> 26) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Number of Transmit Descriptors"] + #[inline(always)] + pub fn ntxd(&self) -> NTXD_R { + NTXD_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bits 21:23 - Link State"] + #[inline(always)] + pub fn ls(&self) -> LS_R { + LS_R::new(((self.bits >> 21) & 0x07) as u8) + } + #[doc = "Bit 9 - Active port"] + #[inline(always)] + pub fn ap(&self) -> AP_R { + AP_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 8 - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] + #[inline(always)] + pub fn ee(&self) -> EE_R { + EE_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 7 - Packet is received with an invalid destination address field"] + #[inline(always)] + pub fn ia(&self) -> IA_R { + IA_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 6 - A synchronization problem has occurred when receiving NChars"] + #[inline(always)] + pub fn we(&self) -> WE_R { + WE_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 4 - Parity error has occurred"] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 3 - Disconnection error has occurred"] + #[inline(always)] + pub fn de(&self) -> DE_R { + DE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Escape error has occurred"] + #[inline(always)] + pub fn er(&self) -> ER_R { + ER_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Credit has occurred"] + #[inline(always)] + pub fn ce(&self) -> CE_R { + CE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - A new time count value was received"] + #[inline(always)] + pub fn to(&self) -> TO_R { + TO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 26:27 - Number of Receive Descriptors"] + #[inline(always)] + pub fn nrxd(&mut self) -> NRXD_W { + NRXD_W { w: self } + } + #[doc = "Bits 24:25 - Number of Transmit Descriptors"] + #[inline(always)] + pub fn ntxd(&mut self) -> NTXD_W { + NTXD_W { w: self } + } + #[doc = "Bits 21:23 - Link State"] + #[inline(always)] + pub fn ls(&mut self) -> LS_W { + LS_W { w: self } + } + #[doc = "Bit 9 - Active port"] + #[inline(always)] + pub fn ap(&mut self) -> AP_W { + AP_W { w: self } + } + #[doc = "Bit 8 - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] + #[inline(always)] + pub fn ee(&mut self) -> EE_W { + EE_W { w: self } + } + #[doc = "Bit 7 - Packet is received with an invalid destination address field"] + #[inline(always)] + pub fn ia(&mut self) -> IA_W { + IA_W { w: self } + } + #[doc = "Bit 6 - A synchronization problem has occurred when receiving NChars"] + #[inline(always)] + pub fn we(&mut self) -> WE_W { + WE_W { w: self } + } + #[doc = "Bit 4 - Parity error has occurred"] + #[inline(always)] + pub fn pe(&mut self) -> PE_W { + PE_W { w: self } + } + #[doc = "Bit 3 - Disconnection error has occurred"] + #[inline(always)] + pub fn de(&mut self) -> DE_W { + DE_W { w: self } + } + #[doc = "Bit 2 - Escape error has occurred"] + #[inline(always)] + pub fn er(&mut self) -> ER_W { + ER_W { w: self } + } + #[doc = "Bit 1 - Credit has occurred"] + #[inline(always)] + pub fn ce(&mut self) -> CE_W { + CE_W { w: self } + } + #[doc = "Bit 0 - A new time count value was received"] + #[inline(always)] + pub fn to(&mut self) -> TO_W { + TO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status/Interrupt Source Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sts](index.html) module"] +pub struct STS_SPEC; +impl crate::RegisterSpec for STS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sts::R](R) reader structure"] +impl crate::Readable for STS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sts::W](W) writer structure"] +impl crate::Writable for STS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STS to value 0x0640_0000"] +impl crate::Resettable for STS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0640_0000 + } +} diff --git a/src/spw/tc.rs b/src/spw/tc.rs new file mode 100644 index 0000000..b3987cb --- /dev/null +++ b/src/spw/tc.rs @@ -0,0 +1,140 @@ +#[doc = "Register `TC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIRQ_END` reader - The current value of the time control flags"] +pub struct TIRQ_END_R(crate::FieldReader); +impl TIRQ_END_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TIRQ_END_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIRQ_END_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIRQ_END` writer - The current value of the time control flags"] +pub struct TIRQ_END_W<'a> { + w: &'a mut W, +} +impl<'a> TIRQ_END_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 6)) | ((value as u32 & 0x03) << 6); + self.w + } +} +#[doc = "Field `TIMECNT` reader - The current value of the system time counter"] +pub struct TIMECNT_R(crate::FieldReader); +impl TIMECNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TIMECNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMECNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMECNT` writer - The current value of the system time counter"] +pub struct TIMECNT_W<'a> { + w: &'a mut W, +} +impl<'a> TIMECNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 6:7 - The current value of the time control flags"] + #[inline(always)] + pub fn tirq_end(&self) -> TIRQ_END_R { + TIRQ_END_R::new(((self.bits >> 6) & 0x03) as u8) + } + #[doc = "Bits 0:5 - The current value of the system time counter"] + #[inline(always)] + pub fn timecnt(&self) -> TIMECNT_R { + TIMECNT_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 6:7 - The current value of the time control flags"] + #[inline(always)] + pub fn tirq_end(&mut self) -> TIRQ_END_W { + TIRQ_END_W { w: self } + } + #[doc = "Bits 0:5 - The current value of the system time counter"] + #[inline(always)] + pub fn timecnt(&mut self) -> TIMECNT_W { + TIMECNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Time Code Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tc](index.html) module"] +pub struct TC_SPEC; +impl crate::RegisterSpec for TC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tc::R](R) reader structure"] +impl crate::Readable for TC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tc::W](W) writer structure"] +impl crate::Writable for TC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TC to value 0"] +impl crate::Resettable for TC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/spw/tdr.rs b/src/spw/tdr.rs new file mode 100644 index 0000000..7b4e378 --- /dev/null +++ b/src/spw/tdr.rs @@ -0,0 +1,73 @@ +#[doc = "Register `TDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DISCONNECT` reader - Used to generate the 850 ns disconnect time period"] +pub struct DISCONNECT_R(crate::FieldReader); +impl DISCONNECT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DISCONNECT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DISCONNECT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMER64` reader - Used to generate the 6.4 and 12.8 us time periods"] +pub struct TIMER64_R(crate::FieldReader); +impl TIMER64_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + TIMER64_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMER64_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 12:21 - Used to generate the 850 ns disconnect time period"] + #[inline(always)] + pub fn disconnect(&self) -> DISCONNECT_R { + DISCONNECT_R::new(((self.bits >> 12) & 0x03ff) as u16) + } + #[doc = "Bits 0:11 - Used to generate the 6.4 and 12.8 us time periods"] + #[inline(always)] + pub fn timer64(&self) -> TIMER64_R { + TIMER64_R::new((self.bits & 0x0fff) as u16) + } +} +#[doc = "Timer and Disconnect Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdr](index.html) module"] +pub struct TDR_SPEC; +impl crate::RegisterSpec for TDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tdr::R](R) reader structure"] +impl crate::Readable for TDR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TDR to value 0"] +impl crate::Resettable for TDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig.rs b/src/sysconfig.rs new file mode 100644 index 0000000..9ebae59 --- /dev/null +++ b/src/sysconfig.rs @@ -0,0 +1,281 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - System Reset Status"] + pub rst_stat: crate::Reg, + #[doc = "0x04 - ROM Reset Control"] + pub rst_cntl_rom: crate::Reg, + #[doc = "0x08 - RAM Reset Control"] + pub rst_cntl_ram0: crate::Reg, + #[doc = "0x0c - RAM Reset Control"] + pub rst_cntl_ram1: crate::Reg, + #[doc = "0x10 - ROM Protection Configuration"] + pub rom_prot: crate::Reg, + #[doc = "0x14 - ROM Scrub Period Configuration"] + pub rom_scrub: crate::Reg, + #[doc = "0x18 - RAM0 Scrub Period Configuration"] + pub ram0_scrub: crate::Reg, + #[doc = "0x1c - RAM1 Scrub Period Configuration"] + pub ram1_scrub: crate::Reg, + #[doc = "0x20 - Enable EDAC Error Interrupt Register"] + pub irq_enb: crate::Reg, + #[doc = "0x24 - Raw EDAC Error Interrupt Status"] + pub irq_raw: crate::Reg, + #[doc = "0x28 - Enabled EDAC Error Interrupt Status"] + pub irq_end: crate::Reg, + #[doc = "0x2c - Clear EDAC Error Interrupt Status"] + pub irq_clr: crate::Reg, + #[doc = "0x30 - Count of RAM0 EDAC Single Bit Errors"] + pub ram0_sbe: crate::Reg, + #[doc = "0x34 - Count of RAM1 EDAC Single Bit Errors"] + pub ram1_sbe: crate::Reg, + #[doc = "0x38 - Count of RAM0 EDAC Multi Bit Errors"] + pub ram0_mbe: crate::Reg, + #[doc = "0x3c - Count of RAM1 EDAC Multi Bit Errors"] + pub ram1_mbe: crate::Reg, + #[doc = "0x40 - Count of ROM EDAC Single Bit Errors"] + pub rom_sbe: crate::Reg, + #[doc = "0x44 - Count of ROM EDAC Multi Bit Errors"] + pub rom_mbe: crate::Reg, + #[doc = "0x48 - ROM BOOT Retry count"] + pub rom_retries: crate::Reg, + #[doc = "0x4c - Register Refresh Rate for TMR registers"] + pub refresh_config_h: crate::Reg, + #[doc = "0x50 - TIM Reset Control"] + pub tim_reset: crate::Reg, + #[doc = "0x54 - TIM Enable Control"] + pub tim_clk_enable: crate::Reg, + #[doc = "0x58 - Peripheral Reset Control"] + pub peripheral_reset: crate::Reg, + #[doc = "0x5c - Peripheral Enable Control"] + pub peripheral_clk_enable: crate::Reg, + #[doc = "0x60 - SPW M4 control register"] + pub spw_m4_ctrl: crate::Reg, + #[doc = "0x64 - PMU Control Register"] + pub pmu_ctrl: crate::Reg, + #[doc = "0x68 - Wakeup Control"] + pub wakeup_cnt: crate::Reg, + #[doc = "0x6c - EBI Config Register 0"] + pub ebi_cfg0: crate::Reg, + #[doc = "0x70 - EBI Config Register 1"] + pub ebi_cfg1: crate::Reg, + #[doc = "0x74 - EBI Config Register 2"] + pub ebi_cfg2: crate::Reg, + #[doc = "0x78 - EBI Config Register 3"] + pub ebi_cfg3: crate::Reg, + #[doc = "0x7c - Analog Control Register"] + pub analog_cntl: crate::Reg, + #[doc = "0x80 - Initial SpW Clock Divider Value"] + pub sw_clkdiv10: crate::Reg, + #[doc = "0x84 - Register Refresh Rate for TMR registers"] + pub refresh_config_l: crate::Reg, + _reserved34: [u8; 0x0f48], + #[doc = "0xfd0 - DAC0 Calibration Register"] + pub dac0_cal: crate::Reg, + #[doc = "0xfd4 - DAC1 Calibration Register"] + pub dac1_cal: crate::Reg, + #[doc = "0xfd8 - ADC Calibration Register"] + pub adc_cal: crate::Reg, + #[doc = "0xfdc - Bandgap Calibration Register"] + pub bg_cal: crate::Reg, + #[doc = "0xfe0 - Digital LDO Regulator Calibration Register"] + pub dreg_cal: crate::Reg, + #[doc = "0xfe4 - Analog LDO Regulator Calibration Register"] + pub areg_cal: crate::Reg, + #[doc = "0xfe8 - Heart Beat OSC Calibration Register"] + pub hbo_cal: crate::Reg, + #[doc = "0xfec - EFuse Config Register"] + pub ef_config: crate::Reg, + #[doc = "0xff0 - EFuse ID0 Register"] + pub ef_id0: crate::Reg, + #[doc = "0xff4 - EFuse ID1 Register"] + pub ef_id1: crate::Reg, + #[doc = "0xff8 - Processor ID Register"] + pub procid: crate::Reg, + #[doc = "0xffc - Peripheral ID Register"] + pub perid: crate::Reg, +} +#[doc = "RST_STAT register accessor: an alias for `Reg`"] +pub type RST_STAT = crate::Reg; +#[doc = "System Reset Status"] +pub mod rst_stat; +#[doc = "RST_CNTL_ROM register accessor: an alias for `Reg`"] +pub type RST_CNTL_ROM = crate::Reg; +#[doc = "ROM Reset Control"] +pub mod rst_cntl_rom; +#[doc = "RST_CNTL_RAM0 register accessor: an alias for `Reg`"] +pub type RST_CNTL_RAM0 = crate::Reg; +#[doc = "RAM Reset Control"] +pub mod rst_cntl_ram0; +#[doc = "RST_CNTL_RAM1 register accessor: an alias for `Reg`"] +pub type RST_CNTL_RAM1 = crate::Reg; +#[doc = "RAM Reset Control"] +pub mod rst_cntl_ram1; +#[doc = "ROM_PROT register accessor: an alias for `Reg`"] +pub type ROM_PROT = crate::Reg; +#[doc = "ROM Protection Configuration"] +pub mod rom_prot; +#[doc = "ROM_SCRUB register accessor: an alias for `Reg`"] +pub type ROM_SCRUB = crate::Reg; +#[doc = "ROM Scrub Period Configuration"] +pub mod rom_scrub; +#[doc = "RAM0_SCRUB register accessor: an alias for `Reg`"] +pub type RAM0_SCRUB = crate::Reg; +#[doc = "RAM0 Scrub Period Configuration"] +pub mod ram0_scrub; +#[doc = "RAM1_SCRUB register accessor: an alias for `Reg`"] +pub type RAM1_SCRUB = crate::Reg; +#[doc = "RAM1 Scrub Period Configuration"] +pub mod ram1_scrub; +#[doc = "IRQ_ENB register accessor: an alias for `Reg`"] +pub type IRQ_ENB = crate::Reg; +#[doc = "Enable EDAC Error Interrupt Register"] +pub mod irq_enb; +#[doc = "IRQ_RAW register accessor: an alias for `Reg`"] +pub type IRQ_RAW = crate::Reg; +#[doc = "Raw EDAC Error Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END register accessor: an alias for `Reg`"] +pub type IRQ_END = crate::Reg; +#[doc = "Enabled EDAC Error Interrupt Status"] +pub mod irq_end; +#[doc = "IRQ_CLR register accessor: an alias for `Reg`"] +pub type IRQ_CLR = crate::Reg; +#[doc = "Clear EDAC Error Interrupt Status"] +pub mod irq_clr; +#[doc = "RAM0_SBE register accessor: an alias for `Reg`"] +pub type RAM0_SBE = crate::Reg; +#[doc = "Count of RAM0 EDAC Single Bit Errors"] +pub mod ram0_sbe; +#[doc = "RAM1_SBE register accessor: an alias for `Reg`"] +pub type RAM1_SBE = crate::Reg; +#[doc = "Count of RAM1 EDAC Single Bit Errors"] +pub mod ram1_sbe; +#[doc = "RAM0_MBE register accessor: an alias for `Reg`"] +pub type RAM0_MBE = crate::Reg; +#[doc = "Count of RAM0 EDAC Multi Bit Errors"] +pub mod ram0_mbe; +#[doc = "RAM1_MBE register accessor: an alias for `Reg`"] +pub type RAM1_MBE = crate::Reg; +#[doc = "Count of RAM1 EDAC Multi Bit Errors"] +pub mod ram1_mbe; +#[doc = "ROM_SBE register accessor: an alias for `Reg`"] +pub type ROM_SBE = crate::Reg; +#[doc = "Count of ROM EDAC Single Bit Errors"] +pub mod rom_sbe; +#[doc = "ROM_MBE register accessor: an alias for `Reg`"] +pub type ROM_MBE = crate::Reg; +#[doc = "Count of ROM EDAC Multi Bit Errors"] +pub mod rom_mbe; +#[doc = "ROM_RETRIES register accessor: an alias for `Reg`"] +pub type ROM_RETRIES = crate::Reg; +#[doc = "ROM BOOT Retry count"] +pub mod rom_retries; +#[doc = "REFRESH_CONFIG_H register accessor: an alias for `Reg`"] +pub type REFRESH_CONFIG_H = crate::Reg; +#[doc = "Register Refresh Rate for TMR registers"] +pub mod refresh_config_h; +#[doc = "TIM_RESET register accessor: an alias for `Reg`"] +pub type TIM_RESET = crate::Reg; +#[doc = "TIM Reset Control"] +pub mod tim_reset; +#[doc = "TIM_CLK_ENABLE register accessor: an alias for `Reg`"] +pub type TIM_CLK_ENABLE = crate::Reg; +#[doc = "TIM Enable Control"] +pub mod tim_clk_enable; +#[doc = "PERIPHERAL_RESET register accessor: an alias for `Reg`"] +pub type PERIPHERAL_RESET = crate::Reg; +#[doc = "Peripheral Reset Control"] +pub mod peripheral_reset; +#[doc = "PERIPHERAL_CLK_ENABLE register accessor: an alias for `Reg`"] +pub type PERIPHERAL_CLK_ENABLE = crate::Reg; +#[doc = "Peripheral Enable Control"] +pub mod peripheral_clk_enable; +#[doc = "SPW_M4_CTRL register accessor: an alias for `Reg`"] +pub type SPW_M4_CTRL = crate::Reg; +#[doc = "SPW M4 control register"] +pub mod spw_m4_ctrl; +#[doc = "PMU_CTRL register accessor: an alias for `Reg`"] +pub type PMU_CTRL = crate::Reg; +#[doc = "PMU Control Register"] +pub mod pmu_ctrl; +#[doc = "WAKEUP_CNT register accessor: an alias for `Reg`"] +pub type WAKEUP_CNT = crate::Reg; +#[doc = "Wakeup Control"] +pub mod wakeup_cnt; +#[doc = "EBI_CFG0 register accessor: an alias for `Reg`"] +pub type EBI_CFG0 = crate::Reg; +#[doc = "EBI Config Register 0"] +pub mod ebi_cfg0; +#[doc = "EBI_CFG1 register accessor: an alias for `Reg`"] +pub type EBI_CFG1 = crate::Reg; +#[doc = "EBI Config Register 1"] +pub mod ebi_cfg1; +#[doc = "EBI_CFG2 register accessor: an alias for `Reg`"] +pub type EBI_CFG2 = crate::Reg; +#[doc = "EBI Config Register 2"] +pub mod ebi_cfg2; +#[doc = "EBI_CFG3 register accessor: an alias for `Reg`"] +pub type EBI_CFG3 = crate::Reg; +#[doc = "EBI Config Register 3"] +pub mod ebi_cfg3; +#[doc = "ANALOG_CNTL register accessor: an alias for `Reg`"] +pub type ANALOG_CNTL = crate::Reg; +#[doc = "Analog Control Register"] +pub mod analog_cntl; +#[doc = "SW_CLKDIV10 register accessor: an alias for `Reg`"] +pub type SW_CLKDIV10 = crate::Reg; +#[doc = "Initial SpW Clock Divider Value"] +pub mod sw_clkdiv10; +#[doc = "REFRESH_CONFIG_L register accessor: an alias for `Reg`"] +pub type REFRESH_CONFIG_L = crate::Reg; +#[doc = "Register Refresh Rate for TMR registers"] +pub mod refresh_config_l; +#[doc = "DAC0_CAL register accessor: an alias for `Reg`"] +pub type DAC0_CAL = crate::Reg; +#[doc = "DAC0 Calibration Register"] +pub mod dac0_cal; +#[doc = "DAC1_CAL register accessor: an alias for `Reg`"] +pub type DAC1_CAL = crate::Reg; +#[doc = "DAC1 Calibration Register"] +pub mod dac1_cal; +#[doc = "ADC_CAL register accessor: an alias for `Reg`"] +pub type ADC_CAL = crate::Reg; +#[doc = "ADC Calibration Register"] +pub mod adc_cal; +#[doc = "BG_CAL register accessor: an alias for `Reg`"] +pub type BG_CAL = crate::Reg; +#[doc = "Bandgap Calibration Register"] +pub mod bg_cal; +#[doc = "DREG_CAL register accessor: an alias for `Reg`"] +pub type DREG_CAL = crate::Reg; +#[doc = "Digital LDO Regulator Calibration Register"] +pub mod dreg_cal; +#[doc = "AREG_CAL register accessor: an alias for `Reg`"] +pub type AREG_CAL = crate::Reg; +#[doc = "Analog LDO Regulator Calibration Register"] +pub mod areg_cal; +#[doc = "HBO_CAL register accessor: an alias for `Reg`"] +pub type HBO_CAL = crate::Reg; +#[doc = "Heart Beat OSC Calibration Register"] +pub mod hbo_cal; +#[doc = "EF_CONFIG register accessor: an alias for `Reg`"] +pub type EF_CONFIG = crate::Reg; +#[doc = "EFuse Config Register"] +pub mod ef_config; +#[doc = "EF_ID0 register accessor: an alias for `Reg`"] +pub type EF_ID0 = crate::Reg; +#[doc = "EFuse ID0 Register"] +pub mod ef_id0; +#[doc = "EF_ID1 register accessor: an alias for `Reg`"] +pub type EF_ID1 = crate::Reg; +#[doc = "EFuse ID1 Register"] +pub mod ef_id1; +#[doc = "PROCID register accessor: an alias for `Reg`"] +pub type PROCID = crate::Reg; +#[doc = "Processor ID Register"] +pub mod procid; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/sysconfig/adc_cal.rs b/src/sysconfig/adc_cal.rs new file mode 100644 index 0000000..4ba12f1 --- /dev/null +++ b/src/sysconfig/adc_cal.rs @@ -0,0 +1,53 @@ +#[doc = "Register `ADC_CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ADC_CAL` reader - ADC Calibration bits"] +pub struct ADC_CAL_R(crate::FieldReader); +impl ADC_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADC_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - ADC Calibration bits"] + #[inline(always)] + pub fn adc_cal(&self) -> ADC_CAL_R { + ADC_CAL_R::new((self.bits & 0x1f) as u8) + } +} +#[doc = "ADC Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adc_cal](index.html) module"] +pub struct ADC_CAL_SPEC; +impl crate::RegisterSpec for ADC_CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [adc_cal::R](R) reader structure"] +impl crate::Readable for ADC_CAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ADC_CAL to value 0"] +impl crate::Resettable for ADC_CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/analog_cntl.rs b/src/sysconfig/analog_cntl.rs new file mode 100644 index 0000000..08ff33e --- /dev/null +++ b/src/sysconfig/analog_cntl.rs @@ -0,0 +1,704 @@ +#[doc = "Register `ANALOG_CNTL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ANALOG_CNTL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TMOSC` reader - Test Mode"] +pub struct TMOSC_R(crate::FieldReader); +impl TMOSC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TMOSC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TMOSC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TMOSC` writer - Test Mode"] +pub struct TMOSC_W<'a> { + w: &'a mut W, +} +impl<'a> TMOSC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TMPOKDIS` reader - Test Mode"] +pub struct TMPOKDIS_R(crate::FieldReader); +impl TMPOKDIS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TMPOKDIS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TMPOKDIS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TMPOKDIS` writer - Test Mode"] +pub struct TMPOKDIS_W<'a> { + w: &'a mut W, +} +impl<'a> TMPOKDIS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TM_ADCMUX_N` reader - Test Mode"] +pub struct TM_ADCMUX_N_R(crate::FieldReader); +impl TM_ADCMUX_N_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TM_ADCMUX_N_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TM_ADCMUX_N_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TM_ADCMUX_N` writer - Test Mode"] +pub struct TM_ADCMUX_N_W<'a> { + w: &'a mut W, +} +impl<'a> TM_ADCMUX_N_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TM_ADCMUX_P` reader - Test Mode"] +pub struct TM_ADCMUX_P_R(crate::FieldReader); +impl TM_ADCMUX_P_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TM_ADCMUX_P_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TM_ADCMUX_P_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TM_ADCMUX_P` writer - Test Mode"] +pub struct TM_ADCMUX_P_W<'a> { + w: &'a mut W, +} +impl<'a> TM_ADCMUX_P_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TMRATIO` reader - Test Mode"] +pub struct TMRATIO_R(crate::FieldReader); +impl TMRATIO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TMRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TMRATIO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TMRATIO` writer - Test Mode"] +pub struct TMRATIO_W<'a> { + w: &'a mut W, +} +impl<'a> TMRATIO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `TMATOMUX` reader - Test Mode"] +pub struct TMATOMUX_R(crate::FieldReader); +impl TMATOMUX_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TMATOMUX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TMATOMUX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TMATOMUX` writer - Test Mode"] +pub struct TMATOMUX_W<'a> { + w: &'a mut W, +} +impl<'a> TMATOMUX_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Field `ADC_STEST` reader - Number of clocks for sample time"] +pub struct ADC_STEST_R(crate::FieldReader); +impl ADC_STEST_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADC_STEST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_STEST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC_STEST` writer - Number of clocks for sample time"] +pub struct ADC_STEST_W<'a> { + w: &'a mut W, +} +impl<'a> ADC_STEST_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 9)) | ((value as u32 & 0x0f) << 9); + self.w + } +} +#[doc = "Field `RCLK_POS_EN` reader - Enable normal test clock"] +pub struct RCLK_POS_EN_R(crate::FieldReader); +impl RCLK_POS_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCLK_POS_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCLK_POS_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCLK_POS_EN` writer - Enable normal test clock"] +pub struct RCLK_POS_EN_W<'a> { + w: &'a mut W, +} +impl<'a> RCLK_POS_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `RCLK_NEG_EN` reader - Enable inverted test clock"] +pub struct RCLK_NEG_EN_R(crate::FieldReader); +impl RCLK_NEG_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RCLK_NEG_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RCLK_NEG_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RCLK_NEG_EN` writer - Enable inverted test clock"] +pub struct RCLK_NEG_EN_W<'a> { + w: &'a mut W, +} +impl<'a> RCLK_NEG_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `APB2CLK_POS_EN` reader - Enable normal APB2CLK for test output"] +pub struct APB2CLK_POS_EN_R(crate::FieldReader); +impl APB2CLK_POS_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + APB2CLK_POS_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for APB2CLK_POS_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APB2CLK_POS_EN` writer - Enable normal APB2CLK for test output"] +pub struct APB2CLK_POS_EN_W<'a> { + w: &'a mut W, +} +impl<'a> APB2CLK_POS_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `APB2CLK_NEG_EN` reader - Enable inverted APB2CLK for test output"] +pub struct APB2CLK_NEG_EN_R(crate::FieldReader); +impl APB2CLK_NEG_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + APB2CLK_NEG_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for APB2CLK_NEG_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `APB2CLK_NEG_EN` writer - Enable inverted APB2CLK for test output"] +pub struct APB2CLK_NEG_EN_W<'a> { + w: &'a mut W, +} +impl<'a> APB2CLK_NEG_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `TM_ANALOG_PD_EN` reader - Enables pull down on analog pads"] +pub struct TM_ANALOG_PD_EN_R(crate::FieldReader); +impl TM_ANALOG_PD_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TM_ANALOG_PD_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TM_ANALOG_PD_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TM_ANALOG_PD_EN` writer - Enables pull down on analog pads"] +pub struct TM_ANALOG_PD_EN_W<'a> { + w: &'a mut W, +} +impl<'a> TM_ANALOG_PD_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `JMP2BOOT` reader - Enables a skip of all delay counters and eFuse read"] +pub struct JMP2BOOT_R(crate::FieldReader); +impl JMP2BOOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + JMP2BOOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for JMP2BOOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `JMP2BOOT` writer - Enables a skip of all delay counters and eFuse read"] +pub struct JMP2BOOT_W<'a> { + w: &'a mut W, +} +impl<'a> JMP2BOOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `SKIPBOOT` reader - Enables a skip of all delay counters, eFuse read, and boot"] +pub struct SKIPBOOT_R(crate::FieldReader); +impl SKIPBOOT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SKIPBOOT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SKIPBOOT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SKIPBOOT` writer - Enables a skip of all delay counters, eFuse read, and boot"] +pub struct SKIPBOOT_W<'a> { + w: &'a mut W, +} +impl<'a> SKIPBOOT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +impl R { + #[doc = "Bit 0 - Test Mode"] + #[inline(always)] + pub fn tmosc(&self) -> TMOSC_R { + TMOSC_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Test Mode"] + #[inline(always)] + pub fn tmpokdis(&self) -> TMPOKDIS_R { + TMPOKDIS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_n(&self) -> TM_ADCMUX_N_R { + TM_ADCMUX_N_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_p(&self) -> TM_ADCMUX_P_R { + TM_ADCMUX_P_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Test Mode"] + #[inline(always)] + pub fn tmratio(&self) -> TMRATIO_R { + TMRATIO_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Test Mode"] + #[inline(always)] + pub fn tmatomux(&self) -> TMATOMUX_R { + TMATOMUX_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 9:12 - Number of clocks for sample time"] + #[inline(always)] + pub fn adc_stest(&self) -> ADC_STEST_R { + ADC_STEST_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bit 14 - Enable normal test clock"] + #[inline(always)] + pub fn rclk_pos_en(&self) -> RCLK_POS_EN_R { + RCLK_POS_EN_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Enable inverted test clock"] + #[inline(always)] + pub fn rclk_neg_en(&self) -> RCLK_NEG_EN_R { + RCLK_NEG_EN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Enable normal APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_pos_en(&self) -> APB2CLK_POS_EN_R { + APB2CLK_POS_EN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Enable inverted APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_neg_en(&self) -> APB2CLK_NEG_EN_R { + APB2CLK_NEG_EN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Enables pull down on analog pads"] + #[inline(always)] + pub fn tm_analog_pd_en(&self) -> TM_ANALOG_PD_EN_R { + TM_ANALOG_PD_EN_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"] + #[inline(always)] + pub fn jmp2boot(&self) -> JMP2BOOT_R { + JMP2BOOT_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"] + #[inline(always)] + pub fn skipboot(&self) -> SKIPBOOT_R { + SKIPBOOT_R::new(((self.bits >> 20) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Test Mode"] + #[inline(always)] + pub fn tmosc(&mut self) -> TMOSC_W { + TMOSC_W { w: self } + } + #[doc = "Bit 1 - Test Mode"] + #[inline(always)] + pub fn tmpokdis(&mut self) -> TMPOKDIS_W { + TMPOKDIS_W { w: self } + } + #[doc = "Bit 2 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_n(&mut self) -> TM_ADCMUX_N_W { + TM_ADCMUX_N_W { w: self } + } + #[doc = "Bit 3 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_p(&mut self) -> TM_ADCMUX_P_W { + TM_ADCMUX_P_W { w: self } + } + #[doc = "Bit 4 - Test Mode"] + #[inline(always)] + pub fn tmratio(&mut self) -> TMRATIO_W { + TMRATIO_W { w: self } + } + #[doc = "Bits 5:6 - Test Mode"] + #[inline(always)] + pub fn tmatomux(&mut self) -> TMATOMUX_W { + TMATOMUX_W { w: self } + } + #[doc = "Bits 9:12 - Number of clocks for sample time"] + #[inline(always)] + pub fn adc_stest(&mut self) -> ADC_STEST_W { + ADC_STEST_W { w: self } + } + #[doc = "Bit 14 - Enable normal test clock"] + #[inline(always)] + pub fn rclk_pos_en(&mut self) -> RCLK_POS_EN_W { + RCLK_POS_EN_W { w: self } + } + #[doc = "Bit 15 - Enable inverted test clock"] + #[inline(always)] + pub fn rclk_neg_en(&mut self) -> RCLK_NEG_EN_W { + RCLK_NEG_EN_W { w: self } + } + #[doc = "Bit 16 - Enable normal APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_pos_en(&mut self) -> APB2CLK_POS_EN_W { + APB2CLK_POS_EN_W { w: self } + } + #[doc = "Bit 17 - Enable inverted APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_neg_en(&mut self) -> APB2CLK_NEG_EN_W { + APB2CLK_NEG_EN_W { w: self } + } + #[doc = "Bit 18 - Enables pull down on analog pads"] + #[inline(always)] + pub fn tm_analog_pd_en(&mut self) -> TM_ANALOG_PD_EN_W { + TM_ANALOG_PD_EN_W { w: self } + } + #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"] + #[inline(always)] + pub fn jmp2boot(&mut self) -> JMP2BOOT_W { + JMP2BOOT_W { w: self } + } + #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"] + #[inline(always)] + pub fn skipboot(&mut self) -> SKIPBOOT_W { + SKIPBOOT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Analog Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [analog_cntl](index.html) module"] +pub struct ANALOG_CNTL_SPEC; +impl crate::RegisterSpec for ANALOG_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [analog_cntl::R](R) reader structure"] +impl crate::Readable for ANALOG_CNTL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [analog_cntl::W](W) writer structure"] +impl crate::Writable for ANALOG_CNTL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ANALOG_CNTL to value 0"] +impl crate::Resettable for ANALOG_CNTL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/areg_cal.rs b/src/sysconfig/areg_cal.rs new file mode 100644 index 0000000..7ebbcb2 --- /dev/null +++ b/src/sysconfig/areg_cal.rs @@ -0,0 +1,53 @@ +#[doc = "Register `AREG_CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `AREG_CAL` reader - Analog LDO Regulator Calibration bits"] +pub struct AREG_CAL_R(crate::FieldReader); +impl AREG_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + AREG_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AREG_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:8 - Analog LDO Regulator Calibration bits"] + #[inline(always)] + pub fn areg_cal(&self) -> AREG_CAL_R { + AREG_CAL_R::new((self.bits & 0x01ff) as u16) + } +} +#[doc = "Analog LDO Regulator Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [areg_cal](index.html) module"] +pub struct AREG_CAL_SPEC; +impl crate::RegisterSpec for AREG_CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [areg_cal::R](R) reader structure"] +impl crate::Readable for AREG_CAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AREG_CAL to value 0"] +impl crate::Resettable for AREG_CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/bg_cal.rs b/src/sysconfig/bg_cal.rs new file mode 100644 index 0000000..a71569b --- /dev/null +++ b/src/sysconfig/bg_cal.rs @@ -0,0 +1,53 @@ +#[doc = "Register `BG_CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BG_CAL` reader - Bandgap Calibration bits"] +pub struct BG_CAL_R(crate::FieldReader); +impl BG_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BG_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BG_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:2 - Bandgap Calibration bits"] + #[inline(always)] + pub fn bg_cal(&self) -> BG_CAL_R { + BG_CAL_R::new((self.bits & 0x07) as u8) + } +} +#[doc = "Bandgap Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bg_cal](index.html) module"] +pub struct BG_CAL_SPEC; +impl crate::RegisterSpec for BG_CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bg_cal::R](R) reader structure"] +impl crate::Readable for BG_CAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BG_CAL to value 0"] +impl crate::Resettable for BG_CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/dac0_cal.rs b/src/sysconfig/dac0_cal.rs new file mode 100644 index 0000000..fdb5d14 --- /dev/null +++ b/src/sysconfig/dac0_cal.rs @@ -0,0 +1,53 @@ +#[doc = "Register `DAC0_CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DAC0_CAL` reader - DAC0 Calibration bits"] +pub struct DAC0_CAL_R(crate::FieldReader); +impl DAC0_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAC0_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC0_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - DAC0 Calibration bits"] + #[inline(always)] + pub fn dac0_cal(&self) -> DAC0_CAL_R { + DAC0_CAL_R::new((self.bits & 0x1f) as u8) + } +} +#[doc = "DAC0 Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dac0_cal](index.html) module"] +pub struct DAC0_CAL_SPEC; +impl crate::RegisterSpec for DAC0_CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dac0_cal::R](R) reader structure"] +impl crate::Readable for DAC0_CAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DAC0_CAL to value 0"] +impl crate::Resettable for DAC0_CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/dac1_cal.rs b/src/sysconfig/dac1_cal.rs new file mode 100644 index 0000000..90de722 --- /dev/null +++ b/src/sysconfig/dac1_cal.rs @@ -0,0 +1,53 @@ +#[doc = "Register `DAC1_CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DAC1_CAL` reader - DAC1 Calibration bits"] +pub struct DAC1_CAL_R(crate::FieldReader); +impl DAC1_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DAC1_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC1_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:4 - DAC1 Calibration bits"] + #[inline(always)] + pub fn dac1_cal(&self) -> DAC1_CAL_R { + DAC1_CAL_R::new((self.bits & 0x1f) as u8) + } +} +#[doc = "DAC1 Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dac1_cal](index.html) module"] +pub struct DAC1_CAL_SPEC; +impl crate::RegisterSpec for DAC1_CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dac1_cal::R](R) reader structure"] +impl crate::Readable for DAC1_CAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DAC1_CAL to value 0"] +impl crate::Resettable for DAC1_CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/dreg_cal.rs b/src/sysconfig/dreg_cal.rs new file mode 100644 index 0000000..538152c --- /dev/null +++ b/src/sysconfig/dreg_cal.rs @@ -0,0 +1,53 @@ +#[doc = "Register `DREG_CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DREG_CAL` reader - Digital LDO Regulator Calibration bits"] +pub struct DREG_CAL_R(crate::FieldReader); +impl DREG_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + DREG_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DREG_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:8 - Digital LDO Regulator Calibration bits"] + #[inline(always)] + pub fn dreg_cal(&self) -> DREG_CAL_R { + DREG_CAL_R::new((self.bits & 0x01ff) as u16) + } +} +#[doc = "Digital LDO Regulator Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dreg_cal](index.html) module"] +pub struct DREG_CAL_SPEC; +impl crate::RegisterSpec for DREG_CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dreg_cal::R](R) reader structure"] +impl crate::Readable for DREG_CAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DREG_CAL to value 0"] +impl crate::Resettable for DREG_CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ebi_cfg0.rs b/src/sysconfig/ebi_cfg0.rs new file mode 100644 index 0000000..688a1d3 --- /dev/null +++ b/src/sysconfig/ebi_cfg0.rs @@ -0,0 +1,298 @@ +#[doc = "Register `EBI_CFG0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EBI_CFG0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"] +pub struct ADDRLOW0_R(crate::FieldReader); +impl ADDRLOW0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRLOW0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRLOW0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"] +pub struct ADDRLOW0_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRLOW0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"] +pub struct ADDRHIGH0_R(crate::FieldReader); +impl ADDRHIGH0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRHIGH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRHIGH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"] +pub struct ADDRHIGH0_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRHIGH0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"] +pub struct CFGREADCYCLE_R(crate::FieldReader); +impl CFGREADCYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGREADCYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGREADCYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"] +pub struct CFGREADCYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGREADCYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"] +pub struct CFGWRITECYCLE_R(crate::FieldReader); +impl CFGWRITECYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGWRITECYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGWRITECYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"] +pub struct CFGWRITECYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGWRITECYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 19)) | ((value as u32 & 0x07) << 19); + self.w + } +} +#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"] +pub struct CFGTURNAROUNDCYCLE_R(crate::FieldReader); +impl CFGTURNAROUNDCYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGTURNAROUNDCYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGTURNAROUNDCYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"] +pub struct CFGTURNAROUNDCYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGTURNAROUNDCYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 22)) | ((value as u32 & 0x07) << 22); + self.w + } +} +#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"] +pub struct CFGSIZE_R(crate::FieldReader); +impl CFGSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFGSIZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"] +pub struct CFGSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGSIZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&self) -> ADDRLOW0_R { + ADDRLOW0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&self) -> ADDRHIGH0_R { + ADDRHIGH0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&self) -> CFGREADCYCLE_R { + CFGREADCYCLE_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&self) -> CFGWRITECYCLE_R { + CFGWRITECYCLE_R::new(((self.bits >> 19) & 0x07) as u8) + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&self) -> CFGTURNAROUNDCYCLE_R { + CFGTURNAROUNDCYCLE_R::new(((self.bits >> 22) & 0x07) as u8) + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&self) -> CFGSIZE_R { + CFGSIZE_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&mut self) -> ADDRLOW0_W { + ADDRLOW0_W { w: self } + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&mut self) -> ADDRHIGH0_W { + ADDRHIGH0_W { w: self } + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&mut self) -> CFGREADCYCLE_W { + CFGREADCYCLE_W { w: self } + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&mut self) -> CFGWRITECYCLE_W { + CFGWRITECYCLE_W { w: self } + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&mut self) -> CFGTURNAROUNDCYCLE_W { + CFGTURNAROUNDCYCLE_W { w: self } + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&mut self) -> CFGSIZE_W { + CFGSIZE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EBI Config Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ebi_cfg0](index.html) module"] +pub struct EBI_CFG0_SPEC; +impl crate::RegisterSpec for EBI_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ebi_cfg0::R](R) reader structure"] +impl crate::Readable for EBI_CFG0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ebi_cfg0::W](W) writer structure"] +impl crate::Writable for EBI_CFG0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EBI_CFG0 to value 0"] +impl crate::Resettable for EBI_CFG0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ebi_cfg1.rs b/src/sysconfig/ebi_cfg1.rs new file mode 100644 index 0000000..a6f8595 --- /dev/null +++ b/src/sysconfig/ebi_cfg1.rs @@ -0,0 +1,298 @@ +#[doc = "Register `EBI_CFG1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EBI_CFG1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"] +pub struct ADDRLOW0_R(crate::FieldReader); +impl ADDRLOW0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRLOW0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRLOW0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"] +pub struct ADDRLOW0_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRLOW0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"] +pub struct ADDRHIGH0_R(crate::FieldReader); +impl ADDRHIGH0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRHIGH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRHIGH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"] +pub struct ADDRHIGH0_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRHIGH0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"] +pub struct CFGREADCYCLE_R(crate::FieldReader); +impl CFGREADCYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGREADCYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGREADCYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"] +pub struct CFGREADCYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGREADCYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"] +pub struct CFGWRITECYCLE_R(crate::FieldReader); +impl CFGWRITECYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGWRITECYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGWRITECYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"] +pub struct CFGWRITECYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGWRITECYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 19)) | ((value as u32 & 0x07) << 19); + self.w + } +} +#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"] +pub struct CFGTURNAROUNDCYCLE_R(crate::FieldReader); +impl CFGTURNAROUNDCYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGTURNAROUNDCYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGTURNAROUNDCYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"] +pub struct CFGTURNAROUNDCYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGTURNAROUNDCYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 22)) | ((value as u32 & 0x07) << 22); + self.w + } +} +#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"] +pub struct CFGSIZE_R(crate::FieldReader); +impl CFGSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFGSIZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"] +pub struct CFGSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGSIZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&self) -> ADDRLOW0_R { + ADDRLOW0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&self) -> ADDRHIGH0_R { + ADDRHIGH0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&self) -> CFGREADCYCLE_R { + CFGREADCYCLE_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&self) -> CFGWRITECYCLE_R { + CFGWRITECYCLE_R::new(((self.bits >> 19) & 0x07) as u8) + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&self) -> CFGTURNAROUNDCYCLE_R { + CFGTURNAROUNDCYCLE_R::new(((self.bits >> 22) & 0x07) as u8) + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&self) -> CFGSIZE_R { + CFGSIZE_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&mut self) -> ADDRLOW0_W { + ADDRLOW0_W { w: self } + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&mut self) -> ADDRHIGH0_W { + ADDRHIGH0_W { w: self } + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&mut self) -> CFGREADCYCLE_W { + CFGREADCYCLE_W { w: self } + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&mut self) -> CFGWRITECYCLE_W { + CFGWRITECYCLE_W { w: self } + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&mut self) -> CFGTURNAROUNDCYCLE_W { + CFGTURNAROUNDCYCLE_W { w: self } + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&mut self) -> CFGSIZE_W { + CFGSIZE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EBI Config Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ebi_cfg1](index.html) module"] +pub struct EBI_CFG1_SPEC; +impl crate::RegisterSpec for EBI_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ebi_cfg1::R](R) reader structure"] +impl crate::Readable for EBI_CFG1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ebi_cfg1::W](W) writer structure"] +impl crate::Writable for EBI_CFG1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EBI_CFG1 to value 0"] +impl crate::Resettable for EBI_CFG1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ebi_cfg2.rs b/src/sysconfig/ebi_cfg2.rs new file mode 100644 index 0000000..165bdff --- /dev/null +++ b/src/sysconfig/ebi_cfg2.rs @@ -0,0 +1,298 @@ +#[doc = "Register `EBI_CFG2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EBI_CFG2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"] +pub struct ADDRLOW0_R(crate::FieldReader); +impl ADDRLOW0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRLOW0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRLOW0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"] +pub struct ADDRLOW0_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRLOW0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"] +pub struct ADDRHIGH0_R(crate::FieldReader); +impl ADDRHIGH0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRHIGH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRHIGH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"] +pub struct ADDRHIGH0_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRHIGH0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"] +pub struct CFGREADCYCLE_R(crate::FieldReader); +impl CFGREADCYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGREADCYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGREADCYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"] +pub struct CFGREADCYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGREADCYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"] +pub struct CFGWRITECYCLE_R(crate::FieldReader); +impl CFGWRITECYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGWRITECYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGWRITECYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"] +pub struct CFGWRITECYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGWRITECYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 19)) | ((value as u32 & 0x07) << 19); + self.w + } +} +#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"] +pub struct CFGTURNAROUNDCYCLE_R(crate::FieldReader); +impl CFGTURNAROUNDCYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGTURNAROUNDCYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGTURNAROUNDCYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"] +pub struct CFGTURNAROUNDCYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGTURNAROUNDCYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 22)) | ((value as u32 & 0x07) << 22); + self.w + } +} +#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"] +pub struct CFGSIZE_R(crate::FieldReader); +impl CFGSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFGSIZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"] +pub struct CFGSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGSIZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&self) -> ADDRLOW0_R { + ADDRLOW0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&self) -> ADDRHIGH0_R { + ADDRHIGH0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&self) -> CFGREADCYCLE_R { + CFGREADCYCLE_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&self) -> CFGWRITECYCLE_R { + CFGWRITECYCLE_R::new(((self.bits >> 19) & 0x07) as u8) + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&self) -> CFGTURNAROUNDCYCLE_R { + CFGTURNAROUNDCYCLE_R::new(((self.bits >> 22) & 0x07) as u8) + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&self) -> CFGSIZE_R { + CFGSIZE_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&mut self) -> ADDRLOW0_W { + ADDRLOW0_W { w: self } + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&mut self) -> ADDRHIGH0_W { + ADDRHIGH0_W { w: self } + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&mut self) -> CFGREADCYCLE_W { + CFGREADCYCLE_W { w: self } + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&mut self) -> CFGWRITECYCLE_W { + CFGWRITECYCLE_W { w: self } + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&mut self) -> CFGTURNAROUNDCYCLE_W { + CFGTURNAROUNDCYCLE_W { w: self } + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&mut self) -> CFGSIZE_W { + CFGSIZE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EBI Config Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ebi_cfg2](index.html) module"] +pub struct EBI_CFG2_SPEC; +impl crate::RegisterSpec for EBI_CFG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ebi_cfg2::R](R) reader structure"] +impl crate::Readable for EBI_CFG2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ebi_cfg2::W](W) writer structure"] +impl crate::Writable for EBI_CFG2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EBI_CFG2 to value 0"] +impl crate::Resettable for EBI_CFG2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ebi_cfg3.rs b/src/sysconfig/ebi_cfg3.rs new file mode 100644 index 0000000..9b8a2c1 --- /dev/null +++ b/src/sysconfig/ebi_cfg3.rs @@ -0,0 +1,298 @@ +#[doc = "Register `EBI_CFG3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EBI_CFG3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"] +pub struct ADDRLOW0_R(crate::FieldReader); +impl ADDRLOW0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRLOW0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRLOW0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"] +pub struct ADDRLOW0_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRLOW0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"] +pub struct ADDRHIGH0_R(crate::FieldReader); +impl ADDRHIGH0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ADDRHIGH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRHIGH0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"] +pub struct ADDRHIGH0_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRHIGH0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"] +pub struct CFGREADCYCLE_R(crate::FieldReader); +impl CFGREADCYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGREADCYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGREADCYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"] +pub struct CFGREADCYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGREADCYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 16)) | ((value as u32 & 0x07) << 16); + self.w + } +} +#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"] +pub struct CFGWRITECYCLE_R(crate::FieldReader); +impl CFGWRITECYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGWRITECYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGWRITECYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"] +pub struct CFGWRITECYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGWRITECYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 19)) | ((value as u32 & 0x07) << 19); + self.w + } +} +#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"] +pub struct CFGTURNAROUNDCYCLE_R(crate::FieldReader); +impl CFGTURNAROUNDCYCLE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CFGTURNAROUNDCYCLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGTURNAROUNDCYCLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"] +pub struct CFGTURNAROUNDCYCLE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGTURNAROUNDCYCLE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 22)) | ((value as u32 & 0x07) << 22); + self.w + } +} +#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"] +pub struct CFGSIZE_R(crate::FieldReader); +impl CFGSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CFGSIZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFGSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"] +pub struct CFGSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CFGSIZE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&self) -> ADDRLOW0_R { + ADDRLOW0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&self) -> ADDRHIGH0_R { + ADDRHIGH0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&self) -> CFGREADCYCLE_R { + CFGREADCYCLE_R::new(((self.bits >> 16) & 0x07) as u8) + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&self) -> CFGWRITECYCLE_R { + CFGWRITECYCLE_R::new(((self.bits >> 19) & 0x07) as u8) + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&self) -> CFGTURNAROUNDCYCLE_R { + CFGTURNAROUNDCYCLE_R::new(((self.bits >> 22) & 0x07) as u8) + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&self) -> CFGSIZE_R { + CFGSIZE_R::new(((self.bits >> 25) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&mut self) -> ADDRLOW0_W { + ADDRLOW0_W { w: self } + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&mut self) -> ADDRHIGH0_W { + ADDRHIGH0_W { w: self } + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&mut self) -> CFGREADCYCLE_W { + CFGREADCYCLE_W { w: self } + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&mut self) -> CFGWRITECYCLE_W { + CFGWRITECYCLE_W { w: self } + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&mut self) -> CFGTURNAROUNDCYCLE_W { + CFGTURNAROUNDCYCLE_W { w: self } + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&mut self) -> CFGSIZE_W { + CFGSIZE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EBI Config Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ebi_cfg3](index.html) module"] +pub struct EBI_CFG3_SPEC; +impl crate::RegisterSpec for EBI_CFG3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ebi_cfg3::R](R) reader structure"] +impl crate::Readable for EBI_CFG3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ebi_cfg3::W](W) writer structure"] +impl crate::Writable for EBI_CFG3_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EBI_CFG3 to value 0"] +impl crate::Resettable for EBI_CFG3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ef_config.rs b/src/sysconfig/ef_config.rs new file mode 100644 index 0000000..95a6587 --- /dev/null +++ b/src/sysconfig/ef_config.rs @@ -0,0 +1,253 @@ +#[doc = "Register `EF_CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROM_SPEED` reader - Specifies the speed of ROM_SCK"] +pub struct ROM_SPEED_R(crate::FieldReader); +impl ROM_SPEED_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ROM_SPEED_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROM_SPEED_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROM_SIZE` reader - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"] +pub struct ROM_SIZE_R(crate::FieldReader); +impl ROM_SIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ROM_SIZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROM_SIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROM_NOCHECK` reader - When set to 1, the ROM check is skipped"] +pub struct ROM_NOCHECK_R(crate::FieldReader); +impl ROM_NOCHECK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ROM_NOCHECK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROM_NOCHECK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BOOT_DELAY` reader - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"] +pub struct BOOT_DELAY_R(crate::FieldReader); +impl BOOT_DELAY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + BOOT_DELAY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BOOT_DELAY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROM_READ` reader - SPI ROM read instruction code"] +pub struct ROM_READ_R(crate::FieldReader); +impl ROM_READ_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ROM_READ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROM_READ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROM_LATENCY` reader - Number of bits of latency from Address until data from the SPI ROM"] +pub struct ROM_LATENCY_R(crate::FieldReader); +impl ROM_LATENCY_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ROM_LATENCY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROM_LATENCY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROM_ADDRESS` reader - ROM Address Mode"] +pub struct ROM_ADDRESS_R(crate::FieldReader); +impl ROM_ADDRESS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ROM_ADDRESS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROM_ADDRESS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROM_DLYCAP` reader - ROM SPI Delayed capture"] +pub struct ROM_DLYCAP_R(crate::FieldReader); +impl ROM_DLYCAP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ROM_DLYCAP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROM_DLYCAP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROM_STATUS` reader - The first data byte from the SPI ROM following an address is taken as a status byte"] +pub struct ROM_STATUS_R(crate::FieldReader); +impl ROM_STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ROM_STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROM_STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RM` reader - This bit controls the internal RAM read timing and must be maintained at this value"] +pub struct RM_R(crate::FieldReader); +impl RM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WM` reader - This bit controls the internal RAM write timing and must be maintained at this value"] +pub struct WM_R(crate::FieldReader); +impl WM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:1 - Specifies the speed of ROM_SCK"] + #[inline(always)] + pub fn rom_speed(&self) -> ROM_SPEED_R { + ROM_SPEED_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:5 - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"] + #[inline(always)] + pub fn rom_size(&self) -> ROM_SIZE_R { + ROM_SIZE_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - When set to 1, the ROM check is skipped"] + #[inline(always)] + pub fn rom_nocheck(&self) -> ROM_NOCHECK_R { + ROM_NOCHECK_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bits 7:9 - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"] + #[inline(always)] + pub fn boot_delay(&self) -> BOOT_DELAY_R { + BOOT_DELAY_R::new(((self.bits >> 7) & 0x07) as u8) + } + #[doc = "Bits 10:17 - SPI ROM read instruction code"] + #[inline(always)] + pub fn rom_read(&self) -> ROM_READ_R { + ROM_READ_R::new(((self.bits >> 10) & 0xff) as u8) + } + #[doc = "Bits 18:22 - Number of bits of latency from Address until data from the SPI ROM"] + #[inline(always)] + pub fn rom_latency(&self) -> ROM_LATENCY_R { + ROM_LATENCY_R::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bits 23:24 - ROM Address Mode"] + #[inline(always)] + pub fn rom_address(&self) -> ROM_ADDRESS_R { + ROM_ADDRESS_R::new(((self.bits >> 23) & 0x03) as u8) + } + #[doc = "Bit 25 - ROM SPI Delayed capture"] + #[inline(always)] + pub fn rom_dlycap(&self) -> ROM_DLYCAP_R { + ROM_DLYCAP_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - The first data byte from the SPI ROM following an address is taken as a status byte"] + #[inline(always)] + pub fn rom_status(&self) -> ROM_STATUS_R { + ROM_STATUS_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - This bit controls the internal RAM read timing and must be maintained at this value"] + #[inline(always)] + pub fn rm(&self) -> RM_R { + RM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - This bit controls the internal RAM write timing and must be maintained at this value"] + #[inline(always)] + pub fn wm(&self) -> WM_R { + WM_R::new(((self.bits >> 28) & 0x01) != 0) + } +} +#[doc = "EFuse Config Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ef_config](index.html) module"] +pub struct EF_CONFIG_SPEC; +impl crate::RegisterSpec for EF_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ef_config::R](R) reader structure"] +impl crate::Readable for EF_CONFIG_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EF_CONFIG to value 0x0a80_0c40"] +impl crate::Resettable for EF_CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0a80_0c40 + } +} diff --git a/src/sysconfig/ef_id0.rs b/src/sysconfig/ef_id0.rs new file mode 100644 index 0000000..9e37764 --- /dev/null +++ b/src/sysconfig/ef_id0.rs @@ -0,0 +1,31 @@ +#[doc = "Register `EF_ID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "EFuse ID0 Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ef_id0](index.html) module"] +pub struct EF_ID0_SPEC; +impl crate::RegisterSpec for EF_ID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ef_id0::R](R) reader structure"] +impl crate::Readable for EF_ID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EF_ID0 to value 0"] +impl crate::Resettable for EF_ID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ef_id1.rs b/src/sysconfig/ef_id1.rs new file mode 100644 index 0000000..23b00d8 --- /dev/null +++ b/src/sysconfig/ef_id1.rs @@ -0,0 +1,31 @@ +#[doc = "Register `EF_ID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "EFuse ID1 Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ef_id1](index.html) module"] +pub struct EF_ID1_SPEC; +impl crate::RegisterSpec for EF_ID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ef_id1::R](R) reader structure"] +impl crate::Readable for EF_ID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EF_ID1 to value 0"] +impl crate::Resettable for EF_ID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/hbo_cal.rs b/src/sysconfig/hbo_cal.rs new file mode 100644 index 0000000..9ab463a --- /dev/null +++ b/src/sysconfig/hbo_cal.rs @@ -0,0 +1,73 @@ +#[doc = "Register `HBO_CAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `OSC_CAL` reader - 1MHz OSC Calibration bit"] +pub struct OSC_CAL_R(crate::FieldReader); +impl OSC_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + OSC_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HBO_CAL` reader - Heart Beat OSC Calibration bits"] +pub struct HBO_CAL_R(crate::FieldReader); +impl HBO_CAL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + HBO_CAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HBO_CAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - 1MHz OSC Calibration bit"] + #[inline(always)] + pub fn osc_cal(&self) -> OSC_CAL_R { + OSC_CAL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 0:2 - Heart Beat OSC Calibration bits"] + #[inline(always)] + pub fn hbo_cal(&self) -> HBO_CAL_R { + HBO_CAL_R::new((self.bits & 0x07) as u8) + } +} +#[doc = "Heart Beat OSC Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hbo_cal](index.html) module"] +pub struct HBO_CAL_SPEC; +impl crate::RegisterSpec for HBO_CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hbo_cal::R](R) reader structure"] +impl crate::Readable for HBO_CAL_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets HBO_CAL to value 0"] +impl crate::Resettable for HBO_CAL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/irq_clr.rs b/src/sysconfig/irq_clr.rs new file mode 100644 index 0000000..705daf0 --- /dev/null +++ b/src/sysconfig/irq_clr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ROMMBE` writer - ROM Multi Bit Interrupt"] +pub struct ROMMBE_W<'a> { + w: &'a mut W, +} +impl<'a> ROMMBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ROMSBE` writer - ROM Single Bit Interrupt"] +pub struct ROMSBE_W<'a> { + w: &'a mut W, +} +impl<'a> ROMSBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RAM0MBE` writer - RAM0 Multi Bit Interrupt"] +pub struct RAM0MBE_W<'a> { + w: &'a mut W, +} +impl<'a> RAM0MBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RAM0SBE` writer - RAM0 Single Bit Interrupt"] +pub struct RAM0SBE_W<'a> { + w: &'a mut W, +} +impl<'a> RAM0SBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RAM1MBE` writer - RAM1 Multi Bit Interrupt"] +pub struct RAM1MBE_W<'a> { + w: &'a mut W, +} +impl<'a> RAM1MBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RAM1SBE` writer - RAM1 Single Bit Interrupt"] +pub struct RAM1SBE_W<'a> { + w: &'a mut W, +} +impl<'a> RAM1SBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl W { + #[doc = "Bit 0 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&mut self) -> ROMMBE_W { + ROMMBE_W { w: self } + } + #[doc = "Bit 1 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&mut self) -> ROMSBE_W { + ROMSBE_W { w: self } + } + #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram0mbe(&mut self) -> RAM0MBE_W { + RAM0MBE_W { w: self } + } + #[doc = "Bit 3 - RAM0 Single Bit Interrupt"] + #[inline(always)] + pub fn ram0sbe(&mut self) -> RAM0SBE_W { + RAM0SBE_W { w: self } + } + #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram1mbe(&mut self) -> RAM1MBE_W { + RAM1MBE_W { w: self } + } + #[doc = "Bit 5 - RAM1 Single Bit Interrupt"] + #[inline(always)] + pub fn ram1sbe(&mut self) -> RAM1SBE_W { + RAM1SBE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear EDAC Error Interrupt Status\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"] +pub struct IRQ_CLR_SPEC; +impl crate::RegisterSpec for IRQ_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"] +impl crate::Writable for IRQ_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IRQ_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/irq_enb.rs b/src/sysconfig/irq_enb.rs new file mode 100644 index 0000000..0eb2556 --- /dev/null +++ b/src/sysconfig/irq_enb.rs @@ -0,0 +1,348 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_ENB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"] +pub struct ROMMBE_R(crate::FieldReader); +impl ROMMBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ROMMBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROMMBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROMMBE` writer - ROM Multi Bit Interrupt"] +pub struct ROMMBE_W<'a> { + w: &'a mut W, +} +impl<'a> ROMMBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"] +pub struct ROMSBE_R(crate::FieldReader); +impl ROMSBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ROMSBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROMSBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROMSBE` writer - ROM Single Bit Interrupt"] +pub struct ROMSBE_W<'a> { + w: &'a mut W, +} +impl<'a> ROMSBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RAM0MBE` reader - RAM0 Multi Bit Interrupt"] +pub struct RAM0MBE_R(crate::FieldReader); +impl RAM0MBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM0MBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM0MBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM0MBE` writer - RAM0 Multi Bit Interrupt"] +pub struct RAM0MBE_W<'a> { + w: &'a mut W, +} +impl<'a> RAM0MBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RAM0SBE` reader - RAM0 Single Bit Interrupt"] +pub struct RAM0SBE_R(crate::FieldReader); +impl RAM0SBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM0SBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM0SBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM0SBE` writer - RAM0 Single Bit Interrupt"] +pub struct RAM0SBE_W<'a> { + w: &'a mut W, +} +impl<'a> RAM0SBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `RAM1MBE` reader - RAM1 Multi Bit Interrupt"] +pub struct RAM1MBE_R(crate::FieldReader); +impl RAM1MBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM1MBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM1MBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM1MBE` writer - RAM1 Multi Bit Interrupt"] +pub struct RAM1MBE_W<'a> { + w: &'a mut W, +} +impl<'a> RAM1MBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RAM1SBE` reader - RAM1 Single Bit Interrupt"] +pub struct RAM1SBE_R(crate::FieldReader); +impl RAM1SBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM1SBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM1SBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM1SBE` writer - RAM1 Single Bit Interrupt"] +pub struct RAM1SBE_W<'a> { + w: &'a mut W, +} +impl<'a> RAM1SBE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&self) -> ROMMBE_R { + ROMMBE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&self) -> ROMSBE_R { + ROMSBE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram0mbe(&self) -> RAM0MBE_R { + RAM0MBE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RAM0 Single Bit Interrupt"] + #[inline(always)] + pub fn ram0sbe(&self) -> RAM0SBE_R { + RAM0SBE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram1mbe(&self) -> RAM1MBE_R { + RAM1MBE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RAM1 Single Bit Interrupt"] + #[inline(always)] + pub fn ram1sbe(&self) -> RAM1SBE_R { + RAM1SBE_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&mut self) -> ROMMBE_W { + ROMMBE_W { w: self } + } + #[doc = "Bit 1 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&mut self) -> ROMSBE_W { + ROMSBE_W { w: self } + } + #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram0mbe(&mut self) -> RAM0MBE_W { + RAM0MBE_W { w: self } + } + #[doc = "Bit 3 - RAM0 Single Bit Interrupt"] + #[inline(always)] + pub fn ram0sbe(&mut self) -> RAM0SBE_W { + RAM0SBE_W { w: self } + } + #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram1mbe(&mut self) -> RAM1MBE_W { + RAM1MBE_W { w: self } + } + #[doc = "Bit 5 - RAM1 Single Bit Interrupt"] + #[inline(always)] + pub fn ram1sbe(&mut self) -> RAM1SBE_W { + RAM1SBE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable EDAC Error Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"] +pub struct IRQ_ENB_SPEC; +impl crate::RegisterSpec for IRQ_ENB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_enb::R](R) reader structure"] +impl crate::Readable for IRQ_ENB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"] +impl crate::Writable for IRQ_ENB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IRQ_ENB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/irq_end.rs b/src/sysconfig/irq_end.rs new file mode 100644 index 0000000..443bb3f --- /dev/null +++ b/src/sysconfig/irq_end.rs @@ -0,0 +1,153 @@ +#[doc = "Register `IRQ_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"] +pub struct ROMMBE_R(crate::FieldReader); +impl ROMMBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ROMMBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROMMBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"] +pub struct ROMSBE_R(crate::FieldReader); +impl ROMSBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ROMSBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROMSBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM0MBE` reader - RAM0 Multi Bit Interrupt"] +pub struct RAM0MBE_R(crate::FieldReader); +impl RAM0MBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM0MBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM0MBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM0SBE` reader - RAM0 Single Bit Interrupt"] +pub struct RAM0SBE_R(crate::FieldReader); +impl RAM0SBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM0SBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM0SBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM1MBE` reader - RAM1 Multi Bit Interrupt"] +pub struct RAM1MBE_R(crate::FieldReader); +impl RAM1MBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM1MBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM1MBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM1SBE` reader - RAM1 Single Bit Interrupt"] +pub struct RAM1SBE_R(crate::FieldReader); +impl RAM1SBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM1SBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM1SBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&self) -> ROMMBE_R { + ROMMBE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&self) -> ROMSBE_R { + ROMSBE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram0mbe(&self) -> RAM0MBE_R { + RAM0MBE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RAM0 Single Bit Interrupt"] + #[inline(always)] + pub fn ram0sbe(&self) -> RAM0SBE_R { + RAM0SBE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram1mbe(&self) -> RAM1MBE_R { + RAM1MBE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RAM1 Single Bit Interrupt"] + #[inline(always)] + pub fn ram1sbe(&self) -> RAM1SBE_R { + RAM1SBE_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Enabled EDAC Error Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"] +pub struct IRQ_END_SPEC; +impl crate::RegisterSpec for IRQ_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_end::R](R) reader structure"] +impl crate::Readable for IRQ_END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IRQ_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/irq_raw.rs b/src/sysconfig/irq_raw.rs new file mode 100644 index 0000000..83aa039 --- /dev/null +++ b/src/sysconfig/irq_raw.rs @@ -0,0 +1,153 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"] +pub struct ROMMBE_R(crate::FieldReader); +impl ROMMBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ROMMBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROMMBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"] +pub struct ROMSBE_R(crate::FieldReader); +impl ROMSBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ROMSBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROMSBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM0MBE` reader - RAM0 Multi Bit Interrupt"] +pub struct RAM0MBE_R(crate::FieldReader); +impl RAM0MBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM0MBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM0MBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM0SBE` reader - RAM0 Single Bit Interrupt"] +pub struct RAM0SBE_R(crate::FieldReader); +impl RAM0SBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM0SBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM0SBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM1MBE` reader - RAM1 Multi Bit Interrupt"] +pub struct RAM1MBE_R(crate::FieldReader); +impl RAM1MBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM1MBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM1MBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM1SBE` reader - RAM1 Single Bit Interrupt"] +pub struct RAM1SBE_R(crate::FieldReader); +impl RAM1SBE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RAM1SBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM1SBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&self) -> ROMMBE_R { + ROMMBE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&self) -> ROMSBE_R { + ROMSBE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram0mbe(&self) -> RAM0MBE_R { + RAM0MBE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RAM0 Single Bit Interrupt"] + #[inline(always)] + pub fn ram0sbe(&self) -> RAM0SBE_R { + RAM0SBE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram1mbe(&self) -> RAM1MBE_R { + RAM1MBE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RAM1 Single Bit Interrupt"] + #[inline(always)] + pub fn ram1sbe(&self) -> RAM1SBE_R { + RAM1SBE_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +#[doc = "Raw EDAC Error Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"] +pub struct IRQ_RAW_SPEC; +impl crate::RegisterSpec for IRQ_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_raw::R](R) reader structure"] +impl crate::Readable for IRQ_RAW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_RAW to value 0"] +impl crate::Resettable for IRQ_RAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/perid.rs b/src/sysconfig/perid.rs new file mode 100644 index 0000000..1003e2d --- /dev/null +++ b/src/sysconfig/perid.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `MANUFACTURER_ID` reader - MANUFACTURER_ID"] +pub struct MANUFACTURER_ID_R(crate::FieldReader); +impl MANUFACTURER_ID_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + MANUFACTURER_ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MANUFACTURER_ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERIPHERAL_ID` reader - PERIPHERAL_ID"] +pub struct PERIPHERAL_ID_R(crate::FieldReader); +impl PERIPHERAL_ID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERIPHERAL_ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERIPHERAL_ID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PERIPHERAL_VER` reader - PERIPHERAL_VER"] +pub struct PERIPHERAL_VER_R(crate::FieldReader); +impl PERIPHERAL_VER_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERIPHERAL_VER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERIPHERAL_VER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:11 - MANUFACTURER_ID"] + #[inline(always)] + pub fn manufacturer_id(&self) -> MANUFACTURER_ID_R { + MANUFACTURER_ID_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:23 - PERIPHERAL_ID"] + #[inline(always)] + pub fn peripheral_id(&self) -> PERIPHERAL_ID_R { + PERIPHERAL_ID_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - PERIPHERAL_VER"] + #[inline(always)] + pub fn peripheral_ver(&self) -> PERIPHERAL_VER_R { + PERIPHERAL_VER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0280_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0280_07e9 + } +} diff --git a/src/sysconfig/peripheral_clk_enable.rs b/src/sysconfig/peripheral_clk_enable.rs new file mode 100644 index 0000000..cc6c96b --- /dev/null +++ b/src/sysconfig/peripheral_clk_enable.rs @@ -0,0 +1,1523 @@ +#[doc = "Register `PERIPHERAL_CLK_ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERIPHERAL_CLK_ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SPI0` reader - Resetn of SPI0"] +pub struct SPI0_R(crate::FieldReader); +impl SPI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPI0` writer - Resetn of SPI0"] +pub struct SPI0_W<'a> { + w: &'a mut W, +} +impl<'a> SPI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SPI1` reader - Resetn of SPI1"] +pub struct SPI1_R(crate::FieldReader); +impl SPI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPI1` writer - Resetn of SPI1"] +pub struct SPI1_W<'a> { + w: &'a mut W, +} +impl<'a> SPI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SPI2` reader - Resetn of SPI2"] +pub struct SPI2_R(crate::FieldReader); +impl SPI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPI2` writer - Resetn of SPI2"] +pub struct SPI2_W<'a> { + w: &'a mut W, +} +impl<'a> SPI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SPI3` reader - Resetn of SPI3"] +pub struct SPI3_R(crate::FieldReader); +impl SPI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPI3` writer - Resetn of SPI3"] +pub struct SPI3_W<'a> { + w: &'a mut W, +} +impl<'a> SPI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UART0` reader - Resetn of UART0"] +pub struct UART0_R(crate::FieldReader); +impl UART0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UART0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UART0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UART0` writer - Resetn of UART0"] +pub struct UART0_W<'a> { + w: &'a mut W, +} +impl<'a> UART0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `UART1` reader - Resetn of UART1"] +pub struct UART1_R(crate::FieldReader); +impl UART1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UART1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UART1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UART1` writer - Resetn of UART1"] +pub struct UART1_W<'a> { + w: &'a mut W, +} +impl<'a> UART1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UART2` reader - Resetn of UART2"] +pub struct UART2_R(crate::FieldReader); +impl UART2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UART2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UART2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UART2` writer - Resetn of UART2"] +pub struct UART2_W<'a> { + w: &'a mut W, +} +impl<'a> UART2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `I2C0` reader - Resetn of I2C0"] +pub struct I2C0_R(crate::FieldReader); +impl I2C0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C0` writer - Resetn of I2C0"] +pub struct I2C0_W<'a> { + w: &'a mut W, +} +impl<'a> I2C0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `I2C1` reader - Resetn of I2C1"] +pub struct I2C1_R(crate::FieldReader); +impl I2C1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C1` writer - Resetn of I2C1"] +pub struct I2C1_W<'a> { + w: &'a mut W, +} +impl<'a> I2C1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `I2C2` reader - Resetn of I2C2"] +pub struct I2C2_R(crate::FieldReader); +impl I2C2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C2` writer - Resetn of I2C2"] +pub struct I2C2_W<'a> { + w: &'a mut W, +} +impl<'a> I2C2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CAN0` reader - Resetn of CAN0"] +pub struct CAN0_R(crate::FieldReader); +impl CAN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0` writer - Resetn of CAN0"] +pub struct CAN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CAN1` reader - Resetn of CAN1"] +pub struct CAN1_R(crate::FieldReader); +impl CAN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1` writer - Resetn of CAN1"] +pub struct CAN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TRNG` reader - Resetn of TRNG"] +pub struct TRNG_R(crate::FieldReader); +impl TRNG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRNG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRNG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRNG` writer - Resetn of TRNG"] +pub struct TRNG_W<'a> { + w: &'a mut W, +} +impl<'a> TRNG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ADC` reader - Resetn of ADC"] +pub struct ADC_R(crate::FieldReader); +impl ADC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC` writer - Resetn of ADC"] +pub struct ADC_W<'a> { + w: &'a mut W, +} +impl<'a> ADC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DAC` reader - Resetn of DAC"] +pub struct DAC_R(crate::FieldReader); +impl DAC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC` writer - Resetn of DAC"] +pub struct DAC_W<'a> { + w: &'a mut W, +} +impl<'a> DAC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `DMA` reader - Resetn of DMA"] +pub struct DMA_R(crate::FieldReader); +impl DMA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMA` writer - Resetn of DMA"] +pub struct DMA_W<'a> { + w: &'a mut W, +} +impl<'a> DMA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `EBI` reader - Resetn of EBI"] +pub struct EBI_R(crate::FieldReader); +impl EBI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EBI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EBI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EBI` writer - Resetn of EBI"] +pub struct EBI_W<'a> { + w: &'a mut W, +} +impl<'a> EBI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ETH` reader - Resetn of Ethernet"] +pub struct ETH_R(crate::FieldReader); +impl ETH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ETH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ETH` writer - Resetn of Ethernet"] +pub struct ETH_W<'a> { + w: &'a mut W, +} +impl<'a> ETH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `SPW` reader - Resetn of SpaceWire"] +pub struct SPW_R(crate::FieldReader); +impl SPW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPW` writer - Resetn of SpaceWire"] +pub struct SPW_W<'a> { + w: &'a mut W, +} +impl<'a> SPW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CLKGEN` reader - RESETn of PLL in Clock Generation Module"] +pub struct CLKGEN_R(crate::FieldReader); +impl CLKGEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKGEN` writer - RESETn of PLL in Clock Generation Module"] +pub struct CLKGEN_W<'a> { + w: &'a mut W, +} +impl<'a> CLKGEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `IRQ` reader - Resetn of IRQ Router"] +pub struct IRQ_R(crate::FieldReader); +impl IRQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ` writer - Resetn of IRQ Router"] +pub struct IRQ_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `IOCONFIG` reader - Resetn of IO CONFIG"] +pub struct IOCONFIG_R(crate::FieldReader); +impl IOCONFIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IOCONFIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IOCONFIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IOCONFIG` writer - Resetn of IO CONFIG"] +pub struct IOCONFIG_W<'a> { + w: &'a mut W, +} +impl<'a> IOCONFIG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `UTILITY` reader - Resetn of UTILITY peripheral"] +pub struct UTILITY_R(crate::FieldReader); +impl UTILITY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UTILITY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UTILITY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UTILITY` writer - Resetn of UTILITY peripheral"] +pub struct UTILITY_W<'a> { + w: &'a mut W, +} +impl<'a> UTILITY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `WDOG` reader - Resetn of WDOG"] +pub struct WDOG_R(crate::FieldReader); +impl WDOG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDOG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDOG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDOG` writer - Resetn of WDOG"] +pub struct WDOG_W<'a> { + w: &'a mut W, +} +impl<'a> WDOG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PORTA` reader - Resetn of PORTA"] +pub struct PORTA_R(crate::FieldReader); +impl PORTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTA` writer - Resetn of PORTA"] +pub struct PORTA_W<'a> { + w: &'a mut W, +} +impl<'a> PORTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `PORTB` reader - Resetn of PORTB"] +pub struct PORTB_R(crate::FieldReader); +impl PORTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTB` writer - Resetn of PORTB"] +pub struct PORTB_W<'a> { + w: &'a mut W, +} +impl<'a> PORTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `PORTC` reader - Resetn of PORTC"] +pub struct PORTC_R(crate::FieldReader); +impl PORTC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTC` writer - Resetn of PORTC"] +pub struct PORTC_W<'a> { + w: &'a mut W, +} +impl<'a> PORTC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PORTD` reader - Resetn of PORTD"] +pub struct PORTD_R(crate::FieldReader); +impl PORTD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTD` writer - Resetn of PORTD"] +pub struct PORTD_W<'a> { + w: &'a mut W, +} +impl<'a> PORTD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PORTE` reader - Resetn of PORTE"] +pub struct PORTE_R(crate::FieldReader); +impl PORTE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTE` writer - Resetn of PORTE"] +pub struct PORTE_W<'a> { + w: &'a mut W, +} +impl<'a> PORTE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `PORTF` reader - Resetn of PORTF"] +pub struct PORTF_R(crate::FieldReader); +impl PORTF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTF` writer - Resetn of PORTF"] +pub struct PORTF_W<'a> { + w: &'a mut W, +} +impl<'a> PORTF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `PORTG` reader - Resetn of PORTG"] +pub struct PORTG_R(crate::FieldReader); +impl PORTG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTG` writer - Resetn of PORTG"] +pub struct PORTG_W<'a> { + w: &'a mut W, +} +impl<'a> PORTG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Resetn of SPI0"] + #[inline(always)] + pub fn spi0(&self) -> SPI0_R { + SPI0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Resetn of SPI1"] + #[inline(always)] + pub fn spi1(&self) -> SPI1_R { + SPI1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Resetn of SPI2"] + #[inline(always)] + pub fn spi2(&self) -> SPI2_R { + SPI2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Resetn of SPI3"] + #[inline(always)] + pub fn spi3(&self) -> SPI3_R { + SPI3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Resetn of UART0"] + #[inline(always)] + pub fn uart0(&self) -> UART0_R { + UART0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Resetn of UART1"] + #[inline(always)] + pub fn uart1(&self) -> UART1_R { + UART1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Resetn of UART2"] + #[inline(always)] + pub fn uart2(&self) -> UART2_R { + UART2_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Resetn of I2C0"] + #[inline(always)] + pub fn i2c0(&self) -> I2C0_R { + I2C0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Resetn of I2C1"] + #[inline(always)] + pub fn i2c1(&self) -> I2C1_R { + I2C1_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Resetn of I2C2"] + #[inline(always)] + pub fn i2c2(&self) -> I2C2_R { + I2C2_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Resetn of CAN0"] + #[inline(always)] + pub fn can0(&self) -> CAN0_R { + CAN0_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Resetn of CAN1"] + #[inline(always)] + pub fn can1(&self) -> CAN1_R { + CAN1_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Resetn of TRNG"] + #[inline(always)] + pub fn trng(&self) -> TRNG_R { + TRNG_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Resetn of ADC"] + #[inline(always)] + pub fn adc(&self) -> ADC_R { + ADC_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Resetn of DAC"] + #[inline(always)] + pub fn dac(&self) -> DAC_R { + DAC_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Resetn of DMA"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Resetn of EBI"] + #[inline(always)] + pub fn ebi(&self) -> EBI_R { + EBI_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Resetn of Ethernet"] + #[inline(always)] + pub fn eth(&self) -> ETH_R { + ETH_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Resetn of SpaceWire"] + #[inline(always)] + pub fn spw(&self) -> SPW_R { + SPW_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"] + #[inline(always)] + pub fn clkgen(&self) -> CLKGEN_R { + CLKGEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Resetn of IRQ Router"] + #[inline(always)] + pub fn irq(&self) -> IRQ_R { + IRQ_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Resetn of IO CONFIG"] + #[inline(always)] + pub fn ioconfig(&self) -> IOCONFIG_R { + IOCONFIG_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Resetn of UTILITY peripheral"] + #[inline(always)] + pub fn utility(&self) -> UTILITY_R { + UTILITY_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Resetn of WDOG"] + #[inline(always)] + pub fn wdog(&self) -> WDOG_R { + WDOG_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Resetn of PORTA"] + #[inline(always)] + pub fn porta(&self) -> PORTA_R { + PORTA_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Resetn of PORTB"] + #[inline(always)] + pub fn portb(&self) -> PORTB_R { + PORTB_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Resetn of PORTC"] + #[inline(always)] + pub fn portc(&self) -> PORTC_R { + PORTC_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Resetn of PORTD"] + #[inline(always)] + pub fn portd(&self) -> PORTD_R { + PORTD_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Resetn of PORTE"] + #[inline(always)] + pub fn porte(&self) -> PORTE_R { + PORTE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Resetn of PORTF"] + #[inline(always)] + pub fn portf(&self) -> PORTF_R { + PORTF_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Resetn of PORTG"] + #[inline(always)] + pub fn portg(&self) -> PORTG_R { + PORTG_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Resetn of SPI0"] + #[inline(always)] + pub fn spi0(&mut self) -> SPI0_W { + SPI0_W { w: self } + } + #[doc = "Bit 1 - Resetn of SPI1"] + #[inline(always)] + pub fn spi1(&mut self) -> SPI1_W { + SPI1_W { w: self } + } + #[doc = "Bit 2 - Resetn of SPI2"] + #[inline(always)] + pub fn spi2(&mut self) -> SPI2_W { + SPI2_W { w: self } + } + #[doc = "Bit 3 - Resetn of SPI3"] + #[inline(always)] + pub fn spi3(&mut self) -> SPI3_W { + SPI3_W { w: self } + } + #[doc = "Bit 4 - Resetn of UART0"] + #[inline(always)] + pub fn uart0(&mut self) -> UART0_W { + UART0_W { w: self } + } + #[doc = "Bit 5 - Resetn of UART1"] + #[inline(always)] + pub fn uart1(&mut self) -> UART1_W { + UART1_W { w: self } + } + #[doc = "Bit 6 - Resetn of UART2"] + #[inline(always)] + pub fn uart2(&mut self) -> UART2_W { + UART2_W { w: self } + } + #[doc = "Bit 7 - Resetn of I2C0"] + #[inline(always)] + pub fn i2c0(&mut self) -> I2C0_W { + I2C0_W { w: self } + } + #[doc = "Bit 8 - Resetn of I2C1"] + #[inline(always)] + pub fn i2c1(&mut self) -> I2C1_W { + I2C1_W { w: self } + } + #[doc = "Bit 9 - Resetn of I2C2"] + #[inline(always)] + pub fn i2c2(&mut self) -> I2C2_W { + I2C2_W { w: self } + } + #[doc = "Bit 10 - Resetn of CAN0"] + #[inline(always)] + pub fn can0(&mut self) -> CAN0_W { + CAN0_W { w: self } + } + #[doc = "Bit 11 - Resetn of CAN1"] + #[inline(always)] + pub fn can1(&mut self) -> CAN1_W { + CAN1_W { w: self } + } + #[doc = "Bit 12 - Resetn of TRNG"] + #[inline(always)] + pub fn trng(&mut self) -> TRNG_W { + TRNG_W { w: self } + } + #[doc = "Bit 13 - Resetn of ADC"] + #[inline(always)] + pub fn adc(&mut self) -> ADC_W { + ADC_W { w: self } + } + #[doc = "Bit 14 - Resetn of DAC"] + #[inline(always)] + pub fn dac(&mut self) -> DAC_W { + DAC_W { w: self } + } + #[doc = "Bit 15 - Resetn of DMA"] + #[inline(always)] + pub fn dma(&mut self) -> DMA_W { + DMA_W { w: self } + } + #[doc = "Bit 16 - Resetn of EBI"] + #[inline(always)] + pub fn ebi(&mut self) -> EBI_W { + EBI_W { w: self } + } + #[doc = "Bit 17 - Resetn of Ethernet"] + #[inline(always)] + pub fn eth(&mut self) -> ETH_W { + ETH_W { w: self } + } + #[doc = "Bit 18 - Resetn of SpaceWire"] + #[inline(always)] + pub fn spw(&mut self) -> SPW_W { + SPW_W { w: self } + } + #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"] + #[inline(always)] + pub fn clkgen(&mut self) -> CLKGEN_W { + CLKGEN_W { w: self } + } + #[doc = "Bit 20 - Resetn of IRQ Router"] + #[inline(always)] + pub fn irq(&mut self) -> IRQ_W { + IRQ_W { w: self } + } + #[doc = "Bit 21 - Resetn of IO CONFIG"] + #[inline(always)] + pub fn ioconfig(&mut self) -> IOCONFIG_W { + IOCONFIG_W { w: self } + } + #[doc = "Bit 22 - Resetn of UTILITY peripheral"] + #[inline(always)] + pub fn utility(&mut self) -> UTILITY_W { + UTILITY_W { w: self } + } + #[doc = "Bit 23 - Resetn of WDOG"] + #[inline(always)] + pub fn wdog(&mut self) -> WDOG_W { + WDOG_W { w: self } + } + #[doc = "Bit 24 - Resetn of PORTA"] + #[inline(always)] + pub fn porta(&mut self) -> PORTA_W { + PORTA_W { w: self } + } + #[doc = "Bit 25 - Resetn of PORTB"] + #[inline(always)] + pub fn portb(&mut self) -> PORTB_W { + PORTB_W { w: self } + } + #[doc = "Bit 26 - Resetn of PORTC"] + #[inline(always)] + pub fn portc(&mut self) -> PORTC_W { + PORTC_W { w: self } + } + #[doc = "Bit 27 - Resetn of PORTD"] + #[inline(always)] + pub fn portd(&mut self) -> PORTD_W { + PORTD_W { w: self } + } + #[doc = "Bit 28 - Resetn of PORTE"] + #[inline(always)] + pub fn porte(&mut self) -> PORTE_W { + PORTE_W { w: self } + } + #[doc = "Bit 29 - Resetn of PORTF"] + #[inline(always)] + pub fn portf(&mut self) -> PORTF_W { + PORTF_W { w: self } + } + #[doc = "Bit 30 - Resetn of PORTG"] + #[inline(always)] + pub fn portg(&mut self) -> PORTG_W { + PORTG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Enable Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peripheral_clk_enable](index.html) module"] +pub struct PERIPHERAL_CLK_ENABLE_SPEC; +impl crate::RegisterSpec for PERIPHERAL_CLK_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peripheral_clk_enable::R](R) reader structure"] +impl crate::Readable for PERIPHERAL_CLK_ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [peripheral_clk_enable::W](W) writer structure"] +impl crate::Writable for PERIPHERAL_CLK_ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERIPHERAL_CLK_ENABLE to value 0x0088_0000"] +impl crate::Resettable for PERIPHERAL_CLK_ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0088_0000 + } +} diff --git a/src/sysconfig/peripheral_reset.rs b/src/sysconfig/peripheral_reset.rs new file mode 100644 index 0000000..4ba3ac8 --- /dev/null +++ b/src/sysconfig/peripheral_reset.rs @@ -0,0 +1,1523 @@ +#[doc = "Register `PERIPHERAL_RESET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERIPHERAL_RESET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SPI0` reader - Resetn of SPI0"] +pub struct SPI0_R(crate::FieldReader); +impl SPI0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPI0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPI0` writer - Resetn of SPI0"] +pub struct SPI0_W<'a> { + w: &'a mut W, +} +impl<'a> SPI0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SPI1` reader - Resetn of SPI1"] +pub struct SPI1_R(crate::FieldReader); +impl SPI1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPI1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPI1` writer - Resetn of SPI1"] +pub struct SPI1_W<'a> { + w: &'a mut W, +} +impl<'a> SPI1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SPI2` reader - Resetn of SPI2"] +pub struct SPI2_R(crate::FieldReader); +impl SPI2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPI2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPI2` writer - Resetn of SPI2"] +pub struct SPI2_W<'a> { + w: &'a mut W, +} +impl<'a> SPI2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SPI3` reader - Resetn of SPI3"] +pub struct SPI3_R(crate::FieldReader); +impl SPI3_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPI3_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPI3` writer - Resetn of SPI3"] +pub struct SPI3_W<'a> { + w: &'a mut W, +} +impl<'a> SPI3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `UART0` reader - Resetn of UART0"] +pub struct UART0_R(crate::FieldReader); +impl UART0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UART0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UART0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UART0` writer - Resetn of UART0"] +pub struct UART0_W<'a> { + w: &'a mut W, +} +impl<'a> UART0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `UART1` reader - Resetn of UART1"] +pub struct UART1_R(crate::FieldReader); +impl UART1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UART1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UART1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UART1` writer - Resetn of UART1"] +pub struct UART1_W<'a> { + w: &'a mut W, +} +impl<'a> UART1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `UART2` reader - Resetn of UART2"] +pub struct UART2_R(crate::FieldReader); +impl UART2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UART2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UART2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UART2` writer - Resetn of UART2"] +pub struct UART2_W<'a> { + w: &'a mut W, +} +impl<'a> UART2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `I2C0` reader - Resetn of I2C0"] +pub struct I2C0_R(crate::FieldReader); +impl I2C0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C0` writer - Resetn of I2C0"] +pub struct I2C0_W<'a> { + w: &'a mut W, +} +impl<'a> I2C0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `I2C1` reader - Resetn of I2C1"] +pub struct I2C1_R(crate::FieldReader); +impl I2C1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C1` writer - Resetn of I2C1"] +pub struct I2C1_W<'a> { + w: &'a mut W, +} +impl<'a> I2C1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `I2C2` reader - Resetn of I2C2"] +pub struct I2C2_R(crate::FieldReader); +impl I2C2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + I2C2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for I2C2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `I2C2` writer - Resetn of I2C2"] +pub struct I2C2_W<'a> { + w: &'a mut W, +} +impl<'a> I2C2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CAN0` reader - Resetn of CAN0"] +pub struct CAN0_R(crate::FieldReader); +impl CAN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0` writer - Resetn of CAN0"] +pub struct CAN0_W<'a> { + w: &'a mut W, +} +impl<'a> CAN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `CAN1` reader - Resetn of CAN1"] +pub struct CAN1_R(crate::FieldReader); +impl CAN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CAN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1` writer - Resetn of CAN1"] +pub struct CAN1_W<'a> { + w: &'a mut W, +} +impl<'a> CAN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TRNG` reader - Resetn of TRNG"] +pub struct TRNG_R(crate::FieldReader); +impl TRNG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TRNG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TRNG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRNG` writer - Resetn of TRNG"] +pub struct TRNG_W<'a> { + w: &'a mut W, +} +impl<'a> TRNG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `ADC` reader - Resetn of ADC"] +pub struct ADC_R(crate::FieldReader); +impl ADC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ADC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC` writer - Resetn of ADC"] +pub struct ADC_W<'a> { + w: &'a mut W, +} +impl<'a> ADC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `DAC` reader - Resetn of DAC"] +pub struct DAC_R(crate::FieldReader); +impl DAC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC` writer - Resetn of DAC"] +pub struct DAC_W<'a> { + w: &'a mut W, +} +impl<'a> DAC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `DMA` reader - Resetn of DMA"] +pub struct DMA_R(crate::FieldReader); +impl DMA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DMA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMA` writer - Resetn of DMA"] +pub struct DMA_W<'a> { + w: &'a mut W, +} +impl<'a> DMA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `EBI` reader - Resetn of EBI"] +pub struct EBI_R(crate::FieldReader); +impl EBI_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EBI_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EBI_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EBI` writer - Resetn of EBI"] +pub struct EBI_W<'a> { + w: &'a mut W, +} +impl<'a> EBI_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ETH` reader - Resetn of Ethernet"] +pub struct ETH_R(crate::FieldReader); +impl ETH_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ETH_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ETH_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ETH` writer - Resetn of Ethernet"] +pub struct ETH_W<'a> { + w: &'a mut W, +} +impl<'a> ETH_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `SPW` reader - Resetn of SpaceWire"] +pub struct SPW_R(crate::FieldReader); +impl SPW_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPW_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPW` writer - Resetn of SpaceWire"] +pub struct SPW_W<'a> { + w: &'a mut W, +} +impl<'a> SPW_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `CLKGEN` reader - RESETn of PLL in Clock Generation Module"] +pub struct CLKGEN_R(crate::FieldReader); +impl CLKGEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CLKGEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKGEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKGEN` writer - RESETn of PLL in Clock Generation Module"] +pub struct CLKGEN_W<'a> { + w: &'a mut W, +} +impl<'a> CLKGEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `IRQ` reader - Resetn of IRQ Router"] +pub struct IRQ_R(crate::FieldReader); +impl IRQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ` writer - Resetn of IRQ Router"] +pub struct IRQ_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `IOCONFIG` reader - Resetn of IO CONFIG"] +pub struct IOCONFIG_R(crate::FieldReader); +impl IOCONFIG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IOCONFIG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IOCONFIG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IOCONFIG` writer - Resetn of IO CONFIG"] +pub struct IOCONFIG_W<'a> { + w: &'a mut W, +} +impl<'a> IOCONFIG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `UTILITY` reader - Resetn of UTILITY peripheral"] +pub struct UTILITY_R(crate::FieldReader); +impl UTILITY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + UTILITY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for UTILITY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `UTILITY` writer - Resetn of UTILITY peripheral"] +pub struct UTILITY_W<'a> { + w: &'a mut W, +} +impl<'a> UTILITY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `WDOG` reader - Resetn of WDOG"] +pub struct WDOG_R(crate::FieldReader); +impl WDOG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDOG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDOG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDOG` writer - Resetn of WDOG"] +pub struct WDOG_W<'a> { + w: &'a mut W, +} +impl<'a> WDOG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `PORTA` reader - Resetn of PORTA"] +pub struct PORTA_R(crate::FieldReader); +impl PORTA_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTA` writer - Resetn of PORTA"] +pub struct PORTA_W<'a> { + w: &'a mut W, +} +impl<'a> PORTA_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24); + self.w + } +} +#[doc = "Field `PORTB` reader - Resetn of PORTB"] +pub struct PORTB_R(crate::FieldReader); +impl PORTB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTB` writer - Resetn of PORTB"] +pub struct PORTB_W<'a> { + w: &'a mut W, +} +impl<'a> PORTB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25); + self.w + } +} +#[doc = "Field `PORTC` reader - Resetn of PORTC"] +pub struct PORTC_R(crate::FieldReader); +impl PORTC_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTC` writer - Resetn of PORTC"] +pub struct PORTC_W<'a> { + w: &'a mut W, +} +impl<'a> PORTC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26); + self.w + } +} +#[doc = "Field `PORTD` reader - Resetn of PORTD"] +pub struct PORTD_R(crate::FieldReader); +impl PORTD_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTD` writer - Resetn of PORTD"] +pub struct PORTD_W<'a> { + w: &'a mut W, +} +impl<'a> PORTD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Field `PORTE` reader - Resetn of PORTE"] +pub struct PORTE_R(crate::FieldReader); +impl PORTE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTE` writer - Resetn of PORTE"] +pub struct PORTE_W<'a> { + w: &'a mut W, +} +impl<'a> PORTE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Field `PORTF` reader - Resetn of PORTF"] +pub struct PORTF_R(crate::FieldReader); +impl PORTF_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTF` writer - Resetn of PORTF"] +pub struct PORTF_W<'a> { + w: &'a mut W, +} +impl<'a> PORTF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Field `PORTG` reader - Resetn of PORTG"] +pub struct PORTG_R(crate::FieldReader); +impl PORTG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PORTG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORTG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORTG` writer - Resetn of PORTG"] +pub struct PORTG_W<'a> { + w: &'a mut W, +} +impl<'a> PORTG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Resetn of SPI0"] + #[inline(always)] + pub fn spi0(&self) -> SPI0_R { + SPI0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Resetn of SPI1"] + #[inline(always)] + pub fn spi1(&self) -> SPI1_R { + SPI1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Resetn of SPI2"] + #[inline(always)] + pub fn spi2(&self) -> SPI2_R { + SPI2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Resetn of SPI3"] + #[inline(always)] + pub fn spi3(&self) -> SPI3_R { + SPI3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Resetn of UART0"] + #[inline(always)] + pub fn uart0(&self) -> UART0_R { + UART0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Resetn of UART1"] + #[inline(always)] + pub fn uart1(&self) -> UART1_R { + UART1_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Resetn of UART2"] + #[inline(always)] + pub fn uart2(&self) -> UART2_R { + UART2_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Resetn of I2C0"] + #[inline(always)] + pub fn i2c0(&self) -> I2C0_R { + I2C0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Resetn of I2C1"] + #[inline(always)] + pub fn i2c1(&self) -> I2C1_R { + I2C1_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Resetn of I2C2"] + #[inline(always)] + pub fn i2c2(&self) -> I2C2_R { + I2C2_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Resetn of CAN0"] + #[inline(always)] + pub fn can0(&self) -> CAN0_R { + CAN0_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Resetn of CAN1"] + #[inline(always)] + pub fn can1(&self) -> CAN1_R { + CAN1_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - Resetn of TRNG"] + #[inline(always)] + pub fn trng(&self) -> TRNG_R { + TRNG_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - Resetn of ADC"] + #[inline(always)] + pub fn adc(&self) -> ADC_R { + ADC_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Resetn of DAC"] + #[inline(always)] + pub fn dac(&self) -> DAC_R { + DAC_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Resetn of DMA"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - Resetn of EBI"] + #[inline(always)] + pub fn ebi(&self) -> EBI_R { + EBI_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - Resetn of Ethernet"] + #[inline(always)] + pub fn eth(&self) -> ETH_R { + ETH_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - Resetn of SpaceWire"] + #[inline(always)] + pub fn spw(&self) -> SPW_R { + SPW_R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"] + #[inline(always)] + pub fn clkgen(&self) -> CLKGEN_R { + CLKGEN_R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - Resetn of IRQ Router"] + #[inline(always)] + pub fn irq(&self) -> IRQ_R { + IRQ_R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - Resetn of IO CONFIG"] + #[inline(always)] + pub fn ioconfig(&self) -> IOCONFIG_R { + IOCONFIG_R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - Resetn of UTILITY peripheral"] + #[inline(always)] + pub fn utility(&self) -> UTILITY_R { + UTILITY_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Resetn of WDOG"] + #[inline(always)] + pub fn wdog(&self) -> WDOG_R { + WDOG_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bit 24 - Resetn of PORTA"] + #[inline(always)] + pub fn porta(&self) -> PORTA_R { + PORTA_R::new(((self.bits >> 24) & 0x01) != 0) + } + #[doc = "Bit 25 - Resetn of PORTB"] + #[inline(always)] + pub fn portb(&self) -> PORTB_R { + PORTB_R::new(((self.bits >> 25) & 0x01) != 0) + } + #[doc = "Bit 26 - Resetn of PORTC"] + #[inline(always)] + pub fn portc(&self) -> PORTC_R { + PORTC_R::new(((self.bits >> 26) & 0x01) != 0) + } + #[doc = "Bit 27 - Resetn of PORTD"] + #[inline(always)] + pub fn portd(&self) -> PORTD_R { + PORTD_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bit 28 - Resetn of PORTE"] + #[inline(always)] + pub fn porte(&self) -> PORTE_R { + PORTE_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Resetn of PORTF"] + #[inline(always)] + pub fn portf(&self) -> PORTF_R { + PORTF_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Resetn of PORTG"] + #[inline(always)] + pub fn portg(&self) -> PORTG_R { + PORTG_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Resetn of SPI0"] + #[inline(always)] + pub fn spi0(&mut self) -> SPI0_W { + SPI0_W { w: self } + } + #[doc = "Bit 1 - Resetn of SPI1"] + #[inline(always)] + pub fn spi1(&mut self) -> SPI1_W { + SPI1_W { w: self } + } + #[doc = "Bit 2 - Resetn of SPI2"] + #[inline(always)] + pub fn spi2(&mut self) -> SPI2_W { + SPI2_W { w: self } + } + #[doc = "Bit 3 - Resetn of SPI3"] + #[inline(always)] + pub fn spi3(&mut self) -> SPI3_W { + SPI3_W { w: self } + } + #[doc = "Bit 4 - Resetn of UART0"] + #[inline(always)] + pub fn uart0(&mut self) -> UART0_W { + UART0_W { w: self } + } + #[doc = "Bit 5 - Resetn of UART1"] + #[inline(always)] + pub fn uart1(&mut self) -> UART1_W { + UART1_W { w: self } + } + #[doc = "Bit 6 - Resetn of UART2"] + #[inline(always)] + pub fn uart2(&mut self) -> UART2_W { + UART2_W { w: self } + } + #[doc = "Bit 7 - Resetn of I2C0"] + #[inline(always)] + pub fn i2c0(&mut self) -> I2C0_W { + I2C0_W { w: self } + } + #[doc = "Bit 8 - Resetn of I2C1"] + #[inline(always)] + pub fn i2c1(&mut self) -> I2C1_W { + I2C1_W { w: self } + } + #[doc = "Bit 9 - Resetn of I2C2"] + #[inline(always)] + pub fn i2c2(&mut self) -> I2C2_W { + I2C2_W { w: self } + } + #[doc = "Bit 10 - Resetn of CAN0"] + #[inline(always)] + pub fn can0(&mut self) -> CAN0_W { + CAN0_W { w: self } + } + #[doc = "Bit 11 - Resetn of CAN1"] + #[inline(always)] + pub fn can1(&mut self) -> CAN1_W { + CAN1_W { w: self } + } + #[doc = "Bit 12 - Resetn of TRNG"] + #[inline(always)] + pub fn trng(&mut self) -> TRNG_W { + TRNG_W { w: self } + } + #[doc = "Bit 13 - Resetn of ADC"] + #[inline(always)] + pub fn adc(&mut self) -> ADC_W { + ADC_W { w: self } + } + #[doc = "Bit 14 - Resetn of DAC"] + #[inline(always)] + pub fn dac(&mut self) -> DAC_W { + DAC_W { w: self } + } + #[doc = "Bit 15 - Resetn of DMA"] + #[inline(always)] + pub fn dma(&mut self) -> DMA_W { + DMA_W { w: self } + } + #[doc = "Bit 16 - Resetn of EBI"] + #[inline(always)] + pub fn ebi(&mut self) -> EBI_W { + EBI_W { w: self } + } + #[doc = "Bit 17 - Resetn of Ethernet"] + #[inline(always)] + pub fn eth(&mut self) -> ETH_W { + ETH_W { w: self } + } + #[doc = "Bit 18 - Resetn of SpaceWire"] + #[inline(always)] + pub fn spw(&mut self) -> SPW_W { + SPW_W { w: self } + } + #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"] + #[inline(always)] + pub fn clkgen(&mut self) -> CLKGEN_W { + CLKGEN_W { w: self } + } + #[doc = "Bit 20 - Resetn of IRQ Router"] + #[inline(always)] + pub fn irq(&mut self) -> IRQ_W { + IRQ_W { w: self } + } + #[doc = "Bit 21 - Resetn of IO CONFIG"] + #[inline(always)] + pub fn ioconfig(&mut self) -> IOCONFIG_W { + IOCONFIG_W { w: self } + } + #[doc = "Bit 22 - Resetn of UTILITY peripheral"] + #[inline(always)] + pub fn utility(&mut self) -> UTILITY_W { + UTILITY_W { w: self } + } + #[doc = "Bit 23 - Resetn of WDOG"] + #[inline(always)] + pub fn wdog(&mut self) -> WDOG_W { + WDOG_W { w: self } + } + #[doc = "Bit 24 - Resetn of PORTA"] + #[inline(always)] + pub fn porta(&mut self) -> PORTA_W { + PORTA_W { w: self } + } + #[doc = "Bit 25 - Resetn of PORTB"] + #[inline(always)] + pub fn portb(&mut self) -> PORTB_W { + PORTB_W { w: self } + } + #[doc = "Bit 26 - Resetn of PORTC"] + #[inline(always)] + pub fn portc(&mut self) -> PORTC_W { + PORTC_W { w: self } + } + #[doc = "Bit 27 - Resetn of PORTD"] + #[inline(always)] + pub fn portd(&mut self) -> PORTD_W { + PORTD_W { w: self } + } + #[doc = "Bit 28 - Resetn of PORTE"] + #[inline(always)] + pub fn porte(&mut self) -> PORTE_W { + PORTE_W { w: self } + } + #[doc = "Bit 29 - Resetn of PORTF"] + #[inline(always)] + pub fn portf(&mut self) -> PORTF_W { + PORTF_W { w: self } + } + #[doc = "Bit 30 - Resetn of PORTG"] + #[inline(always)] + pub fn portg(&mut self) -> PORTG_W { + PORTG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peripheral_reset](index.html) module"] +pub struct PERIPHERAL_RESET_SPEC; +impl crate::RegisterSpec for PERIPHERAL_RESET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [peripheral_reset::R](R) reader structure"] +impl crate::Readable for PERIPHERAL_RESET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [peripheral_reset::W](W) writer structure"] +impl crate::Writable for PERIPHERAL_RESET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PERIPHERAL_RESET to value 0x7f7b_efff"] +impl crate::Resettable for PERIPHERAL_RESET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x7f7b_efff + } +} diff --git a/src/sysconfig/pmu_ctrl.rs b/src/sysconfig/pmu_ctrl.rs new file mode 100644 index 0000000..1dae155 --- /dev/null +++ b/src/sysconfig/pmu_ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `PMU_CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMU_CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVL_SLCT` reader - Select the POK detect level"] +pub struct LVL_SLCT_R(crate::FieldReader); +impl LVL_SLCT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + LVL_SLCT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVL_SLCT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL_SLCT` writer - Select the POK detect level"] +pub struct LVL_SLCT_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_SLCT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Select the POK detect level"] + #[inline(always)] + pub fn lvl_slct(&self) -> LVL_SLCT_R { + LVL_SLCT_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Select the POK detect level"] + #[inline(always)] + pub fn lvl_slct(&mut self) -> LVL_SLCT_W { + LVL_SLCT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "PMU Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmu_ctrl](index.html) module"] +pub struct PMU_CTRL_SPEC; +impl crate::RegisterSpec for PMU_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pmu_ctrl::R](R) reader structure"] +impl crate::Readable for PMU_CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmu_ctrl::W](W) writer structure"] +impl crate::Writable for PMU_CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PMU_CTRL to value 0"] +impl crate::Resettable for PMU_CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/procid.rs b/src/sysconfig/procid.rs new file mode 100644 index 0000000..b72b68c --- /dev/null +++ b/src/sysconfig/procid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PROCID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Processor ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [procid](index.html) module"] +pub struct PROCID_SPEC; +impl crate::RegisterSpec for PROCID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [procid::R](R) reader structure"] +impl crate::Readable for PROCID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PROCID to value 0x0400_57e3"] +impl crate::Resettable for PROCID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0400_57e3 + } +} diff --git a/src/sysconfig/ram0_mbe.rs b/src/sysconfig/ram0_mbe.rs new file mode 100644 index 0000000..689a280 --- /dev/null +++ b/src/sysconfig/ram0_mbe.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RAM0_MBE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM0_MBE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - RAM0 Multi Bit Errors"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - RAM0 Multi Bit Errors"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count of RAM0 EDAC Multi Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram0_mbe](index.html) module"] +pub struct RAM0_MBE_SPEC; +impl crate::RegisterSpec for RAM0_MBE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram0_mbe::R](R) reader structure"] +impl crate::Readable for RAM0_MBE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram0_mbe::W](W) writer structure"] +impl crate::Writable for RAM0_MBE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM0_MBE to value 0"] +impl crate::Resettable for RAM0_MBE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ram0_sbe.rs b/src/sysconfig/ram0_sbe.rs new file mode 100644 index 0000000..50f9c54 --- /dev/null +++ b/src/sysconfig/ram0_sbe.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RAM0_SBE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM0_SBE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - RAM0 EDAC Single Bit Errors"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - RAM0 EDAC Single Bit Errors"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count of RAM0 EDAC Single Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram0_sbe](index.html) module"] +pub struct RAM0_SBE_SPEC; +impl crate::RegisterSpec for RAM0_SBE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram0_sbe::R](R) reader structure"] +impl crate::Readable for RAM0_SBE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram0_sbe::W](W) writer structure"] +impl crate::Writable for RAM0_SBE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM0_SBE to value 0"] +impl crate::Resettable for RAM0_SBE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ram0_scrub.rs b/src/sysconfig/ram0_scrub.rs new file mode 100644 index 0000000..0c2d96d --- /dev/null +++ b/src/sysconfig/ram0_scrub.rs @@ -0,0 +1,130 @@ +#[doc = "Register `RAM0_SCRUB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM0_SCRUB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Counter divide value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Counter divide value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +#[doc = "Field `RESET` writer - Reset Counter"] +pub struct RESET_W<'a> { + w: &'a mut W, +} +impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 31 - Reset Counter"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM0 Scrub Period Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram0_scrub](index.html) module"] +pub struct RAM0_SCRUB_SPEC; +impl crate::RegisterSpec for RAM0_SCRUB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram0_scrub::R](R) reader structure"] +impl crate::Readable for RAM0_SCRUB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram0_scrub::W](W) writer structure"] +impl crate::Writable for RAM0_SCRUB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM0_SCRUB to value 0"] +impl crate::Resettable for RAM0_SCRUB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ram1_mbe.rs b/src/sysconfig/ram1_mbe.rs new file mode 100644 index 0000000..2721916 --- /dev/null +++ b/src/sysconfig/ram1_mbe.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RAM1_MBE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM1_MBE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - RAM0 Multi Bit Errors"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - RAM0 Multi Bit Errors"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count of RAM1 EDAC Multi Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram1_mbe](index.html) module"] +pub struct RAM1_MBE_SPEC; +impl crate::RegisterSpec for RAM1_MBE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram1_mbe::R](R) reader structure"] +impl crate::Readable for RAM1_MBE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram1_mbe::W](W) writer structure"] +impl crate::Writable for RAM1_MBE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM1_MBE to value 0"] +impl crate::Resettable for RAM1_MBE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ram1_sbe.rs b/src/sysconfig/ram1_sbe.rs new file mode 100644 index 0000000..72a043b --- /dev/null +++ b/src/sysconfig/ram1_sbe.rs @@ -0,0 +1,103 @@ +#[doc = "Register `RAM1_SBE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM1_SBE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - RAM0 EDAC Single Bit Errors"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - RAM0 EDAC Single Bit Errors"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count of RAM1 EDAC Single Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram1_sbe](index.html) module"] +pub struct RAM1_SBE_SPEC; +impl crate::RegisterSpec for RAM1_SBE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram1_sbe::R](R) reader structure"] +impl crate::Readable for RAM1_SBE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram1_sbe::W](W) writer structure"] +impl crate::Writable for RAM1_SBE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM1_SBE to value 0"] +impl crate::Resettable for RAM1_SBE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/ram1_scrub.rs b/src/sysconfig/ram1_scrub.rs new file mode 100644 index 0000000..057c889 --- /dev/null +++ b/src/sysconfig/ram1_scrub.rs @@ -0,0 +1,130 @@ +#[doc = "Register `RAM1_SCRUB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM1_SCRUB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Counter divide value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Counter divide value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +#[doc = "Field `RESET` writer - Reset Counter"] +pub struct RESET_W<'a> { + w: &'a mut W, +} +impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 31 - Reset Counter"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM1 Scrub Period Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram1_scrub](index.html) module"] +pub struct RAM1_SCRUB_SPEC; +impl crate::RegisterSpec for RAM1_SCRUB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram1_scrub::R](R) reader structure"] +impl crate::Readable for RAM1_SCRUB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram1_scrub::W](W) writer structure"] +impl crate::Writable for RAM1_SCRUB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM1_SCRUB to value 0"] +impl crate::Resettable for RAM1_SCRUB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/refresh_config_h.rs b/src/sysconfig/refresh_config_h.rs new file mode 100644 index 0000000..59c2b6f --- /dev/null +++ b/src/sysconfig/refresh_config_h.rs @@ -0,0 +1,140 @@ +#[doc = "Register `REFRESH_CONFIG_H` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFRESH_CONFIG_H` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVCOUNT` reader - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub struct DIVCOUNT_R(crate::FieldReader); +impl DIVCOUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + DIVCOUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVCOUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVCOUNT` writer - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub struct DIVCOUNT_W<'a> { + w: &'a mut W, +} +impl<'a> DIVCOUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `TESTMODE` reader - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] +pub struct TESTMODE_R(crate::FieldReader); +impl TESTMODE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + TESTMODE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TESTMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TESTMODE` writer - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] +pub struct TESTMODE_W<'a> { + w: &'a mut W, +} +impl<'a> TESTMODE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 30)) | ((value as u32 & 0x03) << 30); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&self) -> DIVCOUNT_R { + DIVCOUNT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] + #[inline(always)] + pub fn testmode(&self) -> TESTMODE_R { + TESTMODE_R::new(((self.bits >> 30) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&mut self) -> DIVCOUNT_W { + DIVCOUNT_W { w: self } + } + #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] + #[inline(always)] + pub fn testmode(&mut self) -> TESTMODE_W { + TESTMODE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Register Refresh Rate for TMR registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refresh_config_h](index.html) module"] +pub struct REFRESH_CONFIG_H_SPEC; +impl crate::RegisterSpec for REFRESH_CONFIG_H_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [refresh_config_h::R](R) reader structure"] +impl crate::Readable for REFRESH_CONFIG_H_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refresh_config_h::W](W) writer structure"] +impl crate::Writable for REFRESH_CONFIG_H_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFRESH_CONFIG_H to value 0"] +impl crate::Resettable for REFRESH_CONFIG_H_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/refresh_config_l.rs b/src/sysconfig/refresh_config_l.rs new file mode 100644 index 0000000..07c106b --- /dev/null +++ b/src/sysconfig/refresh_config_l.rs @@ -0,0 +1,103 @@ +#[doc = "Register `REFRESH_CONFIG_L` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFRESH_CONFIG_L` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIVCOUNT` reader - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub struct DIVCOUNT_R(crate::FieldReader); +impl DIVCOUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + DIVCOUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVCOUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVCOUNT` writer - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub struct DIVCOUNT_W<'a> { + w: &'a mut W, +} +impl<'a> DIVCOUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&self) -> DIVCOUNT_R { + DIVCOUNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&mut self) -> DIVCOUNT_W { + DIVCOUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Register Refresh Rate for TMR registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refresh_config_l](index.html) module"] +pub struct REFRESH_CONFIG_L_SPEC; +impl crate::RegisterSpec for REFRESH_CONFIG_L_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [refresh_config_l::R](R) reader structure"] +impl crate::Readable for REFRESH_CONFIG_L_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refresh_config_l::W](W) writer structure"] +impl crate::Writable for REFRESH_CONFIG_L_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets REFRESH_CONFIG_L to value 0x0f"] +impl crate::Resettable for REFRESH_CONFIG_L_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0f + } +} diff --git a/src/sysconfig/rom_mbe.rs b/src/sysconfig/rom_mbe.rs new file mode 100644 index 0000000..4cc0a61 --- /dev/null +++ b/src/sysconfig/rom_mbe.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ROM_MBE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ROM_MBE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - RAM0 Multi Bit Errors"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - RAM0 Multi Bit Errors"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count of ROM EDAC Multi Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_mbe](index.html) module"] +pub struct ROM_MBE_SPEC; +impl crate::RegisterSpec for ROM_MBE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rom_mbe::R](R) reader structure"] +impl crate::Readable for ROM_MBE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rom_mbe::W](W) writer structure"] +impl crate::Writable for ROM_MBE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ROM_MBE to value 0"] +impl crate::Resettable for ROM_MBE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/rom_prot.rs b/src/sysconfig/rom_prot.rs new file mode 100644 index 0000000..60a550e --- /dev/null +++ b/src/sysconfig/rom_prot.rs @@ -0,0 +1,113 @@ +#[doc = "Register `ROM_PROT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ROM_PROT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WREN` reader - ROM Write Enable Bit"] +pub struct WREN_R(crate::FieldReader); +impl WREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WREN` writer - ROM Write Enable Bit"] +pub struct WREN_W<'a> { + w: &'a mut W, +} +impl<'a> WREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - ROM Write Enable Bit"] + #[inline(always)] + pub fn wren(&self) -> WREN_R { + WREN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - ROM Write Enable Bit"] + #[inline(always)] + pub fn wren(&mut self) -> WREN_W { + WREN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "ROM Protection Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_prot](index.html) module"] +pub struct ROM_PROT_SPEC; +impl crate::RegisterSpec for ROM_PROT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rom_prot::R](R) reader structure"] +impl crate::Readable for ROM_PROT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rom_prot::W](W) writer structure"] +impl crate::Writable for ROM_PROT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ROM_PROT to value 0"] +impl crate::Resettable for ROM_PROT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/rom_retries.rs b/src/sysconfig/rom_retries.rs new file mode 100644 index 0000000..3f89688 --- /dev/null +++ b/src/sysconfig/rom_retries.rs @@ -0,0 +1,53 @@ +#[doc = "Register `ROM_RETRIES` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Count of ROM block Retries"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Count of ROM block Retries"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "ROM BOOT Retry count\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_retries](index.html) module"] +pub struct ROM_RETRIES_SPEC; +impl crate::RegisterSpec for ROM_RETRIES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rom_retries::R](R) reader structure"] +impl crate::Readable for ROM_RETRIES_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ROM_RETRIES to value 0"] +impl crate::Resettable for ROM_RETRIES_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/rom_sbe.rs b/src/sysconfig/rom_sbe.rs new file mode 100644 index 0000000..9b9ac5c --- /dev/null +++ b/src/sysconfig/rom_sbe.rs @@ -0,0 +1,103 @@ +#[doc = "Register `ROM_SBE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ROM_SBE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - RAM0 EDAC Single Bit Errors"] +pub struct COUNT_R(crate::FieldReader); +impl COUNT_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + COUNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for COUNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `COUNT` writer - RAM0 EDAC Single Bit Errors"] +pub struct COUNT_W<'a> { + w: &'a mut W, +} +impl<'a> COUNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub fn count(&mut self) -> COUNT_W { + COUNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count of ROM EDAC Single Bit Errors\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_sbe](index.html) module"] +pub struct ROM_SBE_SPEC; +impl crate::RegisterSpec for ROM_SBE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rom_sbe::R](R) reader structure"] +impl crate::Readable for ROM_SBE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rom_sbe::W](W) writer structure"] +impl crate::Writable for ROM_SBE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ROM_SBE to value 0"] +impl crate::Resettable for ROM_SBE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/rom_scrub.rs b/src/sysconfig/rom_scrub.rs new file mode 100644 index 0000000..ba17dbb --- /dev/null +++ b/src/sysconfig/rom_scrub.rs @@ -0,0 +1,130 @@ +#[doc = "Register `ROM_SCRUB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ROM_SCRUB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Counter divide value"] +pub struct VALUE_R(crate::FieldReader); +impl VALUE_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + VALUE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VALUE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VALUE` writer - Counter divide value"] +pub struct VALUE_W<'a> { + w: &'a mut W, +} +impl<'a> VALUE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +#[doc = "Field `RESET` writer - Reset Counter"] +pub struct RESET_W<'a> { + w: &'a mut W, +} +impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&mut self) -> VALUE_W { + VALUE_W { w: self } + } + #[doc = "Bit 31 - Reset Counter"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "ROM Scrub Period Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_scrub](index.html) module"] +pub struct ROM_SCRUB_SPEC; +impl crate::RegisterSpec for ROM_SCRUB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rom_scrub::R](R) reader structure"] +impl crate::Readable for ROM_SCRUB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rom_scrub::W](W) writer structure"] +impl crate::Writable for ROM_SCRUB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ROM_SCRUB to value 0"] +impl crate::Resettable for ROM_SCRUB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/rst_cntl_ram0.rs b/src/sysconfig/rst_cntl_ram0.rs new file mode 100644 index 0000000..40b483c --- /dev/null +++ b/src/sysconfig/rst_cntl_ram0.rs @@ -0,0 +1,321 @@ +#[doc = "Register `RST_CNTL_RAM0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RST_CNTL_RAM0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `POR` reader - Power On Reset Status"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POR` writer - Power On Reset Status"] +pub struct POR_W<'a> { + w: &'a mut W, +} +impl<'a> POR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTRST` reader - External Reset Status"] +pub struct EXTRST_R(crate::FieldReader); +impl EXTRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTRST` writer - External Reset Status"] +pub struct EXTRST_W<'a> { + w: &'a mut W, +} +impl<'a> EXTRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"] +pub struct SYSRSTREQ_R(crate::FieldReader); +impl SYSRSTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRSTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSRSTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"] +pub struct SYSRSTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRSTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"] +pub struct LOOKUP_R(crate::FieldReader); +impl LOOKUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOOKUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOOKUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"] +pub struct LOOKUP_W<'a> { + w: &'a mut W, +} +impl<'a> LOOKUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"] +pub struct WATCHDOG_R(crate::FieldReader); +impl WATCHDOG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WATCHDOG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATCHDOG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"] +pub struct WATCHDOG_W<'a> { + w: &'a mut W, +} +impl<'a> WATCHDOG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MEMERR` reader - Memory Error Reset Status"] +pub struct MEMERR_R(crate::FieldReader); +impl MEMERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEMERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEMERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&self) -> EXTRST_R { + EXTRST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&self) -> SYSRSTREQ_R { + SYSRSTREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&self) -> LOOKUP_R { + LOOKUP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&self) -> WATCHDOG_R { + WATCHDOG_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Memory Error Reset Status"] + #[inline(always)] + pub fn memerr(&self) -> MEMERR_R { + MEMERR_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&mut self) -> POR_W { + POR_W { w: self } + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&mut self) -> EXTRST_W { + EXTRST_W { w: self } + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&mut self) -> SYSRSTREQ_W { + SYSRSTREQ_W { w: self } + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&mut self) -> LOOKUP_W { + LOOKUP_W { w: self } + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&mut self) -> WATCHDOG_W { + WATCHDOG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_cntl_ram0](index.html) module"] +pub struct RST_CNTL_RAM0_SPEC; +impl crate::RegisterSpec for RST_CNTL_RAM0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rst_cntl_ram0::R](R) reader structure"] +impl crate::Readable for RST_CNTL_RAM0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rst_cntl_ram0::W](W) writer structure"] +impl crate::Writable for RST_CNTL_RAM0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RST_CNTL_RAM0 to value 0x3f"] +impl crate::Resettable for RST_CNTL_RAM0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3f + } +} diff --git a/src/sysconfig/rst_cntl_ram1.rs b/src/sysconfig/rst_cntl_ram1.rs new file mode 100644 index 0000000..354e361 --- /dev/null +++ b/src/sysconfig/rst_cntl_ram1.rs @@ -0,0 +1,321 @@ +#[doc = "Register `RST_CNTL_RAM1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RST_CNTL_RAM1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `POR` reader - Power On Reset Status"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POR` writer - Power On Reset Status"] +pub struct POR_W<'a> { + w: &'a mut W, +} +impl<'a> POR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTRST` reader - External Reset Status"] +pub struct EXTRST_R(crate::FieldReader); +impl EXTRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTRST` writer - External Reset Status"] +pub struct EXTRST_W<'a> { + w: &'a mut W, +} +impl<'a> EXTRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"] +pub struct SYSRSTREQ_R(crate::FieldReader); +impl SYSRSTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRSTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSRSTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"] +pub struct SYSRSTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRSTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"] +pub struct LOOKUP_R(crate::FieldReader); +impl LOOKUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOOKUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOOKUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"] +pub struct LOOKUP_W<'a> { + w: &'a mut W, +} +impl<'a> LOOKUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"] +pub struct WATCHDOG_R(crate::FieldReader); +impl WATCHDOG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WATCHDOG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATCHDOG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"] +pub struct WATCHDOG_W<'a> { + w: &'a mut W, +} +impl<'a> WATCHDOG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MEMERR` reader - Memory Error Reset Status"] +pub struct MEMERR_R(crate::FieldReader); +impl MEMERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEMERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEMERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&self) -> EXTRST_R { + EXTRST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&self) -> SYSRSTREQ_R { + SYSRSTREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&self) -> LOOKUP_R { + LOOKUP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&self) -> WATCHDOG_R { + WATCHDOG_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Memory Error Reset Status"] + #[inline(always)] + pub fn memerr(&self) -> MEMERR_R { + MEMERR_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&mut self) -> POR_W { + POR_W { w: self } + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&mut self) -> EXTRST_W { + EXTRST_W { w: self } + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&mut self) -> SYSRSTREQ_W { + SYSRSTREQ_W { w: self } + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&mut self) -> LOOKUP_W { + LOOKUP_W { w: self } + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&mut self) -> WATCHDOG_W { + WATCHDOG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_cntl_ram1](index.html) module"] +pub struct RST_CNTL_RAM1_SPEC; +impl crate::RegisterSpec for RST_CNTL_RAM1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rst_cntl_ram1::R](R) reader structure"] +impl crate::Readable for RST_CNTL_RAM1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rst_cntl_ram1::W](W) writer structure"] +impl crate::Writable for RST_CNTL_RAM1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RST_CNTL_RAM1 to value 0x3f"] +impl crate::Resettable for RST_CNTL_RAM1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3f + } +} diff --git a/src/sysconfig/rst_cntl_rom.rs b/src/sysconfig/rst_cntl_rom.rs new file mode 100644 index 0000000..aee59df --- /dev/null +++ b/src/sysconfig/rst_cntl_rom.rs @@ -0,0 +1,321 @@ +#[doc = "Register `RST_CNTL_ROM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RST_CNTL_ROM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `POR` reader - Power On Reset Status"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POR` writer - Power On Reset Status"] +pub struct POR_W<'a> { + w: &'a mut W, +} +impl<'a> POR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTRST` reader - External Reset Status"] +pub struct EXTRST_R(crate::FieldReader); +impl EXTRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTRST` writer - External Reset Status"] +pub struct EXTRST_W<'a> { + w: &'a mut W, +} +impl<'a> EXTRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"] +pub struct SYSRSTREQ_R(crate::FieldReader); +impl SYSRSTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRSTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSRSTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"] +pub struct SYSRSTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRSTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"] +pub struct LOOKUP_R(crate::FieldReader); +impl LOOKUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOOKUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOOKUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"] +pub struct LOOKUP_W<'a> { + w: &'a mut W, +} +impl<'a> LOOKUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"] +pub struct WATCHDOG_R(crate::FieldReader); +impl WATCHDOG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WATCHDOG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATCHDOG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"] +pub struct WATCHDOG_W<'a> { + w: &'a mut W, +} +impl<'a> WATCHDOG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MEMERR` reader - Memory Error Reset Status"] +pub struct MEMERR_R(crate::FieldReader); +impl MEMERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEMERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEMERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&self) -> EXTRST_R { + EXTRST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&self) -> SYSRSTREQ_R { + SYSRSTREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&self) -> LOOKUP_R { + LOOKUP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&self) -> WATCHDOG_R { + WATCHDOG_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Memory Error Reset Status"] + #[inline(always)] + pub fn memerr(&self) -> MEMERR_R { + MEMERR_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&mut self) -> POR_W { + POR_W { w: self } + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&mut self) -> EXTRST_W { + EXTRST_W { w: self } + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&mut self) -> SYSRSTREQ_W { + SYSRSTREQ_W { w: self } + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&mut self) -> LOOKUP_W { + LOOKUP_W { w: self } + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&mut self) -> WATCHDOG_W { + WATCHDOG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "ROM Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_cntl_rom](index.html) module"] +pub struct RST_CNTL_ROM_SPEC; +impl crate::RegisterSpec for RST_CNTL_ROM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rst_cntl_rom::R](R) reader structure"] +impl crate::Readable for RST_CNTL_ROM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rst_cntl_rom::W](W) writer structure"] +impl crate::Writable for RST_CNTL_ROM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RST_CNTL_ROM to value 0x3f"] +impl crate::Resettable for RST_CNTL_ROM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3f + } +} diff --git a/src/sysconfig/rst_stat.rs b/src/sysconfig/rst_stat.rs new file mode 100644 index 0000000..d744136 --- /dev/null +++ b/src/sysconfig/rst_stat.rs @@ -0,0 +1,321 @@ +#[doc = "Register `RST_STAT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RST_STAT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `POR` reader - Power On Reset Status"] +pub struct POR_R(crate::FieldReader); +impl POR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + POR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for POR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `POR` writer - Power On Reset Status"] +pub struct POR_W<'a> { + w: &'a mut W, +} +impl<'a> POR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `EXTRST` reader - External Reset Status"] +pub struct EXTRST_R(crate::FieldReader); +impl EXTRST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EXTRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EXTRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EXTRST` writer - External Reset Status"] +pub struct EXTRST_W<'a> { + w: &'a mut W, +} +impl<'a> EXTRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"] +pub struct SYSRSTREQ_R(crate::FieldReader); +impl SYSRSTREQ_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SYSRSTREQ_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSRSTREQ_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"] +pub struct SYSRSTREQ_W<'a> { + w: &'a mut W, +} +impl<'a> SYSRSTREQ_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"] +pub struct LOOKUP_R(crate::FieldReader); +impl LOOKUP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOOKUP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOOKUP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"] +pub struct LOOKUP_W<'a> { + w: &'a mut W, +} +impl<'a> LOOKUP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"] +pub struct WATCHDOG_R(crate::FieldReader); +impl WATCHDOG_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WATCHDOG_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WATCHDOG_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"] +pub struct WATCHDOG_W<'a> { + w: &'a mut W, +} +impl<'a> WATCHDOG_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MEMERR` reader - Memory Error Reset Status"] +pub struct MEMERR_R(crate::FieldReader); +impl MEMERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + MEMERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEMERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&self) -> EXTRST_R { + EXTRST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&self) -> SYSRSTREQ_R { + SYSRSTREQ_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&self) -> LOOKUP_R { + LOOKUP_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&self) -> WATCHDOG_R { + WATCHDOG_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Memory Error Reset Status"] + #[inline(always)] + pub fn memerr(&self) -> MEMERR_R { + MEMERR_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&mut self) -> POR_W { + POR_W { w: self } + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&mut self) -> EXTRST_W { + EXTRST_W { w: self } + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&mut self) -> SYSRSTREQ_W { + SYSRSTREQ_W { w: self } + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&mut self) -> LOOKUP_W { + LOOKUP_W { w: self } + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&mut self) -> WATCHDOG_W { + WATCHDOG_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "System Reset Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_stat](index.html) module"] +pub struct RST_STAT_SPEC; +impl crate::RegisterSpec for RST_STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rst_stat::R](R) reader structure"] +impl crate::Readable for RST_STAT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rst_stat::W](W) writer structure"] +impl crate::Writable for RST_STAT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RST_STAT to value 0"] +impl crate::Resettable for RST_STAT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/spw_m4_ctrl.rs b/src/sysconfig/spw_m4_ctrl.rs new file mode 100644 index 0000000..7e4494d --- /dev/null +++ b/src/sysconfig/spw_m4_ctrl.rs @@ -0,0 +1,197 @@ +#[doc = "Register `SPW_M4_CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SPW_M4_CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LREN` reader - Lockup reset enable"] +pub struct LREN_R(crate::FieldReader); +impl LREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LREN` writer - Lockup reset enable"] +pub struct LREN_W<'a> { + w: &'a mut W, +} +impl<'a> LREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `SPW_PAD_EN` reader - SPW pad enable"] +pub struct SPW_PAD_EN_R(crate::FieldReader); +impl SPW_PAD_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SPW_PAD_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SPW_PAD_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPW_PAD_EN` writer - SPW pad enable"] +pub struct SPW_PAD_EN_W<'a> { + w: &'a mut W, +} +impl<'a> SPW_PAD_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `REG_WR_KEY` reader - Fuse-analog register writes enabled when key = 0xfeed"] +pub struct REG_WR_KEY_R(crate::FieldReader); +impl REG_WR_KEY_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + REG_WR_KEY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REG_WR_KEY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REG_WR_KEY` writer - Fuse-analog register writes enabled when key = 0xfeed"] +pub struct REG_WR_KEY_W<'a> { + w: &'a mut W, +} +impl<'a> REG_WR_KEY_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff); + self.w + } +} +impl R { + #[doc = "Bit 17 - Lockup reset enable"] + #[inline(always)] + pub fn lren(&self) -> LREN_R { + LREN_R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 16 - SPW pad enable"] + #[inline(always)] + pub fn spw_pad_en(&self) -> SPW_PAD_EN_R { + SPW_PAD_EN_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"] + #[inline(always)] + pub fn reg_wr_key(&self) -> REG_WR_KEY_R { + REG_WR_KEY_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 17 - Lockup reset enable"] + #[inline(always)] + pub fn lren(&mut self) -> LREN_W { + LREN_W { w: self } + } + #[doc = "Bit 16 - SPW pad enable"] + #[inline(always)] + pub fn spw_pad_en(&mut self) -> SPW_PAD_EN_W { + SPW_PAD_EN_W { w: self } + } + #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"] + #[inline(always)] + pub fn reg_wr_key(&mut self) -> REG_WR_KEY_W { + REG_WR_KEY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPW M4 control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spw_m4_ctrl](index.html) module"] +pub struct SPW_M4_CTRL_SPEC; +impl crate::RegisterSpec for SPW_M4_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [spw_m4_ctrl::R](R) reader structure"] +impl crate::Readable for SPW_M4_CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [spw_m4_ctrl::W](W) writer structure"] +impl crate::Writable for SPW_M4_CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SPW_M4_CTRL to value 0x0003_0000"] +impl crate::Resettable for SPW_M4_CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0003_0000 + } +} diff --git a/src/sysconfig/sw_clkdiv10.rs b/src/sysconfig/sw_clkdiv10.rs new file mode 100644 index 0000000..6182166 --- /dev/null +++ b/src/sysconfig/sw_clkdiv10.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SW_CLKDIV10` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SW_CLKDIV10` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SW_CLKDIV10` reader - Defines the initial value for the SpW clock, defaults to divide by ten"] +pub struct SW_CLKDIV10_R(crate::FieldReader); +impl SW_CLKDIV10_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SW_CLKDIV10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SW_CLKDIV10_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SW_CLKDIV10` writer - Defines the initial value for the SpW clock, defaults to divide by ten"] +pub struct SW_CLKDIV10_W<'a> { + w: &'a mut W, +} +impl<'a> SW_CLKDIV10_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"] + #[inline(always)] + pub fn sw_clkdiv10(&self) -> SW_CLKDIV10_R { + SW_CLKDIV10_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"] + #[inline(always)] + pub fn sw_clkdiv10(&mut self) -> SW_CLKDIV10_W { + SW_CLKDIV10_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Initial SpW Clock Divider Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sw_clkdiv10](index.html) module"] +pub struct SW_CLKDIV10_SPEC; +impl crate::RegisterSpec for SW_CLKDIV10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sw_clkdiv10::R](R) reader structure"] +impl crate::Readable for SW_CLKDIV10_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sw_clkdiv10::W](W) writer structure"] +impl crate::Writable for SW_CLKDIV10_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SW_CLKDIV10 to value 0x09"] +impl crate::Resettable for SW_CLKDIV10_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x09 + } +} diff --git a/src/sysconfig/tim_clk_enable.rs b/src/sysconfig/tim_clk_enable.rs new file mode 100644 index 0000000..2396067 --- /dev/null +++ b/src/sysconfig/tim_clk_enable.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TIM_CLK_ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TIM_CLK_ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIMERS` reader - Clock enable of a given TIMER"] +pub struct TIMERS_R(crate::FieldReader); +impl TIMERS_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TIMERS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIMERS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIMERS` writer - Clock enable of a given TIMER"] +pub struct TIMERS_W<'a> { + w: &'a mut W, +} +impl<'a> TIMERS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Clock enable of a given TIMER"] + #[inline(always)] + pub fn timers(&self) -> TIMERS_R { + TIMERS_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Clock enable of a given TIMER"] + #[inline(always)] + pub fn timers(&mut self) -> TIMERS_W { + TIMERS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "TIM Enable Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tim_clk_enable](index.html) module"] +pub struct TIM_CLK_ENABLE_SPEC; +impl crate::RegisterSpec for TIM_CLK_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tim_clk_enable::R](R) reader structure"] +impl crate::Readable for TIM_CLK_ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tim_clk_enable::W](W) writer structure"] +impl crate::Writable for TIM_CLK_ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TIM_CLK_ENABLE to value 0"] +impl crate::Resettable for TIM_CLK_ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sysconfig/tim_reset.rs b/src/sysconfig/tim_reset.rs new file mode 100644 index 0000000..f757e09 --- /dev/null +++ b/src/sysconfig/tim_reset.rs @@ -0,0 +1,103 @@ +#[doc = "Register `TIM_RESET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TIM_RESET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TIM_RESET` reader - Reset of a given TIMER"] +pub struct TIM_RESET_R(crate::FieldReader); +impl TIM_RESET_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + TIM_RESET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TIM_RESET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TIM_RESET` writer - Reset of a given TIMER"] +pub struct TIM_RESET_W<'a> { + w: &'a mut W, +} +impl<'a> TIM_RESET_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:23 - Reset of a given TIMER"] + #[inline(always)] + pub fn tim_reset(&self) -> TIM_RESET_R { + TIM_RESET_R::new((self.bits & 0x00ff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:23 - Reset of a given TIMER"] + #[inline(always)] + pub fn tim_reset(&mut self) -> TIM_RESET_W { + TIM_RESET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "TIM Reset Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tim_reset](index.html) module"] +pub struct TIM_RESET_SPEC; +impl crate::RegisterSpec for TIM_RESET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tim_reset::R](R) reader structure"] +impl crate::Readable for TIM_RESET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tim_reset::W](W) writer structure"] +impl crate::Writable for TIM_RESET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TIM_RESET to value 0xffff_ffff"] +impl crate::Resettable for TIM_RESET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/src/sysconfig/wakeup_cnt.rs b/src/sysconfig/wakeup_cnt.rs new file mode 100644 index 0000000..f64edfd --- /dev/null +++ b/src/sysconfig/wakeup_cnt.rs @@ -0,0 +1,150 @@ +#[doc = "Register `WAKEUP_CNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAKEUP_CNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CNTSTRT` reader - Launch SLP mode in analog block"] +pub struct CNTSTRT_R(crate::FieldReader); +impl CNTSTRT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CNTSTRT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNTSTRT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNTSTRT` writer - Launch SLP mode in analog block"] +pub struct CNTSTRT_W<'a> { + w: &'a mut W, +} +impl<'a> CNTSTRT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WKUP_CNT` reader - Used to set a time to wake up the processor after the device has been put in a low power state"] +pub struct WKUP_CNT_R(crate::FieldReader); +impl WKUP_CNT_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WKUP_CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WKUP_CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WKUP_CNT` writer - Used to set a time to wake up the processor after the device has been put in a low power state"] +pub struct WKUP_CNT_W<'a> { + w: &'a mut W, +} +impl<'a> WKUP_CNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +impl R { + #[doc = "Bit 3 - Launch SLP mode in analog block"] + #[inline(always)] + pub fn cntstrt(&self) -> CNTSTRT_R { + CNTSTRT_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"] + #[inline(always)] + pub fn wkup_cnt(&self) -> WKUP_CNT_R { + WKUP_CNT_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bit 3 - Launch SLP mode in analog block"] + #[inline(always)] + pub fn cntstrt(&mut self) -> CNTSTRT_W { + CNTSTRT_W { w: self } + } + #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"] + #[inline(always)] + pub fn wkup_cnt(&mut self) -> WKUP_CNT_W { + WKUP_CNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Wakeup Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wakeup_cnt](index.html) module"] +pub struct WAKEUP_CNT_SPEC; +impl crate::RegisterSpec for WAKEUP_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wakeup_cnt::R](R) reader structure"] +impl crate::Readable for WAKEUP_CNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wakeup_cnt::W](W) writer structure"] +impl crate::Writable for WAKEUP_CNT_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WAKEUP_CNT to value 0x07"] +impl crate::Resettable for WAKEUP_CNT_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/src/tim0.rs b/src/tim0.rs new file mode 100644 index 0000000..cf035f6 --- /dev/null +++ b/src/tim0.rs @@ -0,0 +1,92 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control Register"] + pub ctrl: crate::Reg, + #[doc = "0x04 - The value that counter start from after reaching 0."] + pub rst_value: crate::Reg, + #[doc = "0x08 - The current value of the counter"] + pub cnt_value: crate::Reg, + #[doc = "0x0c - Alternate access to the Counter ENABLE bit in the CTRL Register"] + pub enable: crate::Reg, + #[doc = "0x10 - The Cascade Control Register. Controls the counter external enable signals"] + pub csd_ctrl: crate::Reg, + #[doc = "0x14 - Cascade Enable Selection"] + pub cascade0: crate::Reg, + #[doc = "0x18 - Cascade Enable Selection"] + pub cascade1: crate::Reg, + #[doc = "0x1c - Cascade Enable Selection"] + pub cascade2: crate::Reg, + _reserved_8_pwm_value: [u8; 0x04], + #[doc = "0x24 - The Pulse Width Modulation ValueB"] + pub pwmb_value: crate::Reg, + _reserved10: [u8; 0x03d4], + #[doc = "0x3fc - Peripheral ID Register"] + pub perid: crate::Reg, +} +impl RegisterBlock { + #[doc = "0x20 - The Pulse Width Modulation ValueA"] + #[inline(always)] + pub fn pwma_value(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(32usize) + as *const crate::Reg) + } + } + #[doc = "0x20 - The Pulse Width Modulation Value"] + #[inline(always)] + pub fn pwm_value(&self) -> &crate::Reg { + unsafe { + &*(((self as *const Self) as *const u8).add(32usize) + as *const crate::Reg) + } + } +} +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "RST_VALUE register accessor: an alias for `Reg`"] +pub type RST_VALUE = crate::Reg; +#[doc = "The value that counter start from after reaching 0."] +pub mod rst_value; +#[doc = "CNT_VALUE register accessor: an alias for `Reg`"] +pub type CNT_VALUE = crate::Reg; +#[doc = "The current value of the counter"] +pub mod cnt_value; +#[doc = "ENABLE register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register"] +pub mod enable; +#[doc = "CSD_CTRL register accessor: an alias for `Reg`"] +pub type CSD_CTRL = crate::Reg; +#[doc = "The Cascade Control Register. Controls the counter external enable signals"] +pub mod csd_ctrl; +#[doc = "CASCADE0 register accessor: an alias for `Reg`"] +pub type CASCADE0 = crate::Reg; +#[doc = "Cascade Enable Selection"] +pub mod cascade0; +#[doc = "CASCADE1 register accessor: an alias for `Reg`"] +pub type CASCADE1 = crate::Reg; +#[doc = "Cascade Enable Selection"] +pub mod cascade1; +#[doc = "CASCADE2 register accessor: an alias for `Reg`"] +pub type CASCADE2 = crate::Reg; +#[doc = "Cascade Enable Selection"] +pub mod cascade2; +#[doc = "PWM_VALUE register accessor: an alias for `Reg`"] +pub type PWM_VALUE = crate::Reg; +#[doc = "The Pulse Width Modulation Value"] +pub mod pwm_value; +#[doc = "PWMA_VALUE register accessor: an alias for `Reg`"] +pub type PWMA_VALUE = crate::Reg; +#[doc = "The Pulse Width Modulation ValueA"] +pub mod pwma_value; +#[doc = "PWMB_VALUE register accessor: an alias for `Reg`"] +pub type PWMB_VALUE = crate::Reg; +#[doc = "The Pulse Width Modulation ValueB"] +pub mod pwmb_value; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/tim0/cascade0.rs b/src/tim0/cascade0.rs new file mode 100644 index 0000000..b3a8955 --- /dev/null +++ b/src/tim0/cascade0.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CASCADE0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CASCADE0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CASSEL` reader - Cascade Selection"] +pub struct CASSEL_R(crate::FieldReader); +impl CASSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CASSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CASSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CASSEL` writer - Cascade Selection"] +pub struct CASSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CASSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&self) -> CASSEL_R { + CASSEL_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&mut self) -> CASSEL_W { + CASSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Cascade Enable Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cascade0](index.html) module"] +pub struct CASCADE0_SPEC; +impl crate::RegisterSpec for CASCADE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cascade0::R](R) reader structure"] +impl crate::Readable for CASCADE0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cascade0::W](W) writer structure"] +impl crate::Writable for CASCADE0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CASCADE0 to value 0"] +impl crate::Resettable for CASCADE0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/cascade1.rs b/src/tim0/cascade1.rs new file mode 100644 index 0000000..6a962c0 --- /dev/null +++ b/src/tim0/cascade1.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CASCADE1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CASCADE1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CASSEL` reader - Cascade Selection"] +pub struct CASSEL_R(crate::FieldReader); +impl CASSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CASSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CASSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CASSEL` writer - Cascade Selection"] +pub struct CASSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CASSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&self) -> CASSEL_R { + CASSEL_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&mut self) -> CASSEL_W { + CASSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Cascade Enable Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cascade1](index.html) module"] +pub struct CASCADE1_SPEC; +impl crate::RegisterSpec for CASCADE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cascade1::R](R) reader structure"] +impl crate::Readable for CASCADE1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cascade1::W](W) writer structure"] +impl crate::Writable for CASCADE1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CASCADE1 to value 0"] +impl crate::Resettable for CASCADE1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/cascade2.rs b/src/tim0/cascade2.rs new file mode 100644 index 0000000..905d693 --- /dev/null +++ b/src/tim0/cascade2.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CASCADE2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CASCADE2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CASSEL` reader - Cascade Selection"] +pub struct CASSEL_R(crate::FieldReader); +impl CASSEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + CASSEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CASSEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CASSEL` writer - Cascade Selection"] +pub struct CASSEL_W<'a> { + w: &'a mut W, +} +impl<'a> CASSEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&self) -> CASSEL_R { + CASSEL_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&mut self) -> CASSEL_W { + CASSEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Cascade Enable Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cascade2](index.html) module"] +pub struct CASCADE2_SPEC; +impl crate::RegisterSpec for CASCADE2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cascade2::R](R) reader structure"] +impl crate::Readable for CASCADE2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cascade2::W](W) writer structure"] +impl crate::Writable for CASCADE2_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CASCADE2 to value 0"] +impl crate::Resettable for CASCADE2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/cnt_value.rs b/src/tim0/cnt_value.rs new file mode 100644 index 0000000..cd498bb --- /dev/null +++ b/src/tim0/cnt_value.rs @@ -0,0 +1,64 @@ +#[doc = "Register `CNT_VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CNT_VALUE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The current value of the counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt_value](index.html) module"] +pub struct CNT_VALUE_SPEC; +impl crate::RegisterSpec for CNT_VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cnt_value::R](R) reader structure"] +impl crate::Readable for CNT_VALUE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cnt_value::W](W) writer structure"] +impl crate::Writable for CNT_VALUE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CNT_VALUE to value 0"] +impl crate::Resettable for CNT_VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/csd_ctrl.rs b/src/tim0/csd_ctrl.rs new file mode 100644 index 0000000..7b2f36d --- /dev/null +++ b/src/tim0/csd_ctrl.rs @@ -0,0 +1,536 @@ +#[doc = "Register `CSD_CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSD_CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CSDEN0` reader - Cascade 0 Enable"] +pub struct CSDEN0_R(crate::FieldReader); +impl CSDEN0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSDEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSDEN0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSDEN0` writer - Cascade 0 Enable"] +pub struct CSDEN0_W<'a> { + w: &'a mut W, +} +impl<'a> CSDEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `CSDINV0` reader - Cascade 0 Invert"] +pub struct CSDINV0_R(crate::FieldReader); +impl CSDINV0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSDINV0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSDINV0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSDINV0` writer - Cascade 0 Invert"] +pub struct CSDINV0_W<'a> { + w: &'a mut W, +} +impl<'a> CSDINV0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CSDEN1` reader - Cascade 1 Enable"] +pub struct CSDEN1_R(crate::FieldReader); +impl CSDEN1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSDEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSDEN1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSDEN1` writer - Cascade 1 Enable"] +pub struct CSDEN1_W<'a> { + w: &'a mut W, +} +impl<'a> CSDEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CSDINV1` reader - Cascade 1 Invert"] +pub struct CSDINV1_R(crate::FieldReader); +impl CSDINV1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSDINV1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSDINV1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSDINV1` writer - Cascade 1 Invert"] +pub struct CSDINV1_W<'a> { + w: &'a mut W, +} +impl<'a> CSDINV1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `DCASOP` reader - Dual Cascade Operation (0:AND, 1:OR)"] +pub struct DCASOP_R(crate::FieldReader); +impl DCASOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DCASOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DCASOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DCASOP` writer - Dual Cascade Operation (0:AND, 1:OR)"] +pub struct DCASOP_W<'a> { + w: &'a mut W, +} +impl<'a> DCASOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `CSDTRG0` reader - Cascade 0 Enabled as Trigger"] +pub struct CSDTRG0_R(crate::FieldReader); +impl CSDTRG0_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSDTRG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSDTRG0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSDTRG0` writer - Cascade 0 Enabled as Trigger"] +pub struct CSDTRG0_W<'a> { + w: &'a mut W, +} +impl<'a> CSDTRG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CSDTRG1` reader - Cascade 1 Enabled as Trigger"] +pub struct CSDTRG1_R(crate::FieldReader); +impl CSDTRG1_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSDTRG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSDTRG1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSDTRG1` writer - Cascade 1 Enabled as Trigger"] +pub struct CSDTRG1_W<'a> { + w: &'a mut W, +} +impl<'a> CSDTRG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CSDEN2` reader - Cascade 2 Enable"] +pub struct CSDEN2_R(crate::FieldReader); +impl CSDEN2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSDEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSDEN2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSDEN2` writer - Cascade 2 Enable"] +pub struct CSDEN2_W<'a> { + w: &'a mut W, +} +impl<'a> CSDEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CSDINV2` reader - Cascade 2 Invert"] +pub struct CSDINV2_R(crate::FieldReader); +impl CSDINV2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSDINV2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSDINV2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSDINV2` writer - Cascade 2 Invert"] +pub struct CSDINV2_W<'a> { + w: &'a mut W, +} +impl<'a> CSDINV2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CSDTRG2` reader - Cascade 2 Trigger mode"] +pub struct CSDTRG2_R(crate::FieldReader); +impl CSDTRG2_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CSDTRG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CSDTRG2_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CSDTRG2` writer - Cascade 2 Trigger mode"] +pub struct CSDTRG2_W<'a> { + w: &'a mut W, +} +impl<'a> CSDTRG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Cascade 0 Enable"] + #[inline(always)] + pub fn csden0(&self) -> CSDEN0_R { + CSDEN0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Cascade 0 Invert"] + #[inline(always)] + pub fn csdinv0(&self) -> CSDINV0_R { + CSDINV0_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Cascade 1 Enable"] + #[inline(always)] + pub fn csden1(&self) -> CSDEN1_R { + CSDEN1_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Cascade 1 Invert"] + #[inline(always)] + pub fn csdinv1(&self) -> CSDINV1_R { + CSDINV1_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"] + #[inline(always)] + pub fn dcasop(&self) -> DCASOP_R { + DCASOP_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg0(&self) -> CSDTRG0_R { + CSDTRG0_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg1(&self) -> CSDTRG1_R { + CSDTRG1_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Cascade 2 Enable"] + #[inline(always)] + pub fn csden2(&self) -> CSDEN2_R { + CSDEN2_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Cascade 2 Invert"] + #[inline(always)] + pub fn csdinv2(&self) -> CSDINV2_R { + CSDINV2_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Cascade 2 Trigger mode"] + #[inline(always)] + pub fn csdtrg2(&self) -> CSDTRG2_R { + CSDTRG2_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cascade 0 Enable"] + #[inline(always)] + pub fn csden0(&mut self) -> CSDEN0_W { + CSDEN0_W { w: self } + } + #[doc = "Bit 1 - Cascade 0 Invert"] + #[inline(always)] + pub fn csdinv0(&mut self) -> CSDINV0_W { + CSDINV0_W { w: self } + } + #[doc = "Bit 2 - Cascade 1 Enable"] + #[inline(always)] + pub fn csden1(&mut self) -> CSDEN1_W { + CSDEN1_W { w: self } + } + #[doc = "Bit 3 - Cascade 1 Invert"] + #[inline(always)] + pub fn csdinv1(&mut self) -> CSDINV1_W { + CSDINV1_W { w: self } + } + #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"] + #[inline(always)] + pub fn dcasop(&mut self) -> DCASOP_W { + DCASOP_W { w: self } + } + #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg0(&mut self) -> CSDTRG0_W { + CSDTRG0_W { w: self } + } + #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg1(&mut self) -> CSDTRG1_W { + CSDTRG1_W { w: self } + } + #[doc = "Bit 8 - Cascade 2 Enable"] + #[inline(always)] + pub fn csden2(&mut self) -> CSDEN2_W { + CSDEN2_W { w: self } + } + #[doc = "Bit 9 - Cascade 2 Invert"] + #[inline(always)] + pub fn csdinv2(&mut self) -> CSDINV2_W { + CSDINV2_W { w: self } + } + #[doc = "Bit 10 - Cascade 2 Trigger mode"] + #[inline(always)] + pub fn csdtrg2(&mut self) -> CSDTRG2_W { + CSDTRG2_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csd_ctrl](index.html) module"] +pub struct CSD_CTRL_SPEC; +impl crate::RegisterSpec for CSD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csd_ctrl::R](R) reader structure"] +impl crate::Readable for CSD_CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csd_ctrl::W](W) writer structure"] +impl crate::Writable for CSD_CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CSD_CTRL to value 0"] +impl crate::Resettable for CSD_CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/ctrl.rs b/src/tim0/ctrl.rs new file mode 100644 index 0000000..1d7f569 --- /dev/null +++ b/src/tim0/ctrl.rs @@ -0,0 +1,519 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ACTIVE` reader - Counter Active"] +pub struct ACTIVE_R(crate::FieldReader); +impl ACTIVE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ACTIVE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACTIVE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTO_DISABLE` reader - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] +pub struct AUTO_DISABLE_R(crate::FieldReader); +impl AUTO_DISABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTO_DISABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTO_DISABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTO_DISABLE` writer - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] +pub struct AUTO_DISABLE_W<'a> { + w: &'a mut W, +} +impl<'a> AUTO_DISABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `AUTO_DEACTIVATE` reader - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] +pub struct AUTO_DEACTIVATE_R(crate::FieldReader); +impl AUTO_DEACTIVATE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTO_DEACTIVATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTO_DEACTIVATE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTO_DEACTIVATE` writer - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] +pub struct AUTO_DEACTIVATE_W<'a> { + w: &'a mut W, +} +impl<'a> AUTO_DEACTIVATE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `IRQ_ENB` reader - Interrupt Enable"] +pub struct IRQ_ENB_R(crate::FieldReader); +impl IRQ_ENB_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_ENB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_ENB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_ENB` writer - Interrupt Enable"] +pub struct IRQ_ENB_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_ENB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Counter Status Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STATUS_SEL_A { + #[doc = "0: Single cycle pulse when the counter reaches 0"] + DONE = 0, + #[doc = "1: Returns the counter ACTIVE bit"] + ACTIVE = 1, + #[doc = "2: Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + TOGGLE = 2, + #[doc = "3: Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + PWMA = 3, + #[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + PWMB = 4, + #[doc = "5: Returns the counter ENABLED bit"] + ENABLED = 5, + #[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + PWMA_ACTIVE = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STATUS_SEL_A) -> Self { + variant as _ + } +} +#[doc = "Field `STATUS_SEL` reader - Counter Status Selection"] +pub struct STATUS_SEL_R(crate::FieldReader); +impl STATUS_SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + STATUS_SEL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(STATUS_SEL_A::DONE), + 1 => Some(STATUS_SEL_A::ACTIVE), + 2 => Some(STATUS_SEL_A::TOGGLE), + 3 => Some(STATUS_SEL_A::PWMA), + 4 => Some(STATUS_SEL_A::PWMB), + 5 => Some(STATUS_SEL_A::ENABLED), + 6 => Some(STATUS_SEL_A::PWMA_ACTIVE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DONE`"] + #[inline(always)] + pub fn is_done(&self) -> bool { + **self == STATUS_SEL_A::DONE + } + #[doc = "Checks if the value of the field is `ACTIVE`"] + #[inline(always)] + pub fn is_active(&self) -> bool { + **self == STATUS_SEL_A::ACTIVE + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + **self == STATUS_SEL_A::TOGGLE + } + #[doc = "Checks if the value of the field is `PWMA`"] + #[inline(always)] + pub fn is_pwma(&self) -> bool { + **self == STATUS_SEL_A::PWMA + } + #[doc = "Checks if the value of the field is `PWMB`"] + #[inline(always)] + pub fn is_pwmb(&self) -> bool { + **self == STATUS_SEL_A::PWMB + } + #[doc = "Checks if the value of the field is `ENABLED`"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + **self == STATUS_SEL_A::ENABLED + } + #[doc = "Checks if the value of the field is `PWMA_ACTIVE`"] + #[inline(always)] + pub fn is_pwma_active(&self) -> bool { + **self == STATUS_SEL_A::PWMA_ACTIVE + } +} +impl core::ops::Deref for STATUS_SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS_SEL` writer - Counter Status Selection"] +pub struct STATUS_SEL_W<'a> { + w: &'a mut W, +} +impl<'a> STATUS_SEL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STATUS_SEL_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Single cycle pulse when the counter reaches 0"] + #[inline(always)] + pub fn done(self) -> &'a mut W { + self.variant(STATUS_SEL_A::DONE) + } + #[doc = "Returns the counter ACTIVE bit"] + #[inline(always)] + pub fn active(self) -> &'a mut W { + self.variant(STATUS_SEL_A::ACTIVE) + } + #[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(STATUS_SEL_A::TOGGLE) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + #[inline(always)] + pub fn pwma(self) -> &'a mut W { + self.variant(STATUS_SEL_A::PWMA) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + #[inline(always)] + pub fn pwmb(self) -> &'a mut W { + self.variant(STATUS_SEL_A::PWMB) + } + #[doc = "Returns the counter ENABLED bit"] + #[inline(always)] + pub fn enabled(self) -> &'a mut W { + self.variant(STATUS_SEL_A::ENABLED) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + #[inline(always)] + pub fn pwma_active(self) -> &'a mut W { + self.variant(STATUS_SEL_A::PWMA_ACTIVE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u32 & 0x07) << 5); + self.w + } +} +#[doc = "Field `STATUS_INV` reader - Invert the Output Status"] +pub struct STATUS_INV_R(crate::FieldReader); +impl STATUS_INV_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STATUS_INV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STATUS_INV_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STATUS_INV` writer - Invert the Output Status"] +pub struct STATUS_INV_W<'a> { + w: &'a mut W, +} +impl<'a> STATUS_INV_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `REQ_STOP` reader - Stop Request"] +pub struct REQ_STOP_R(crate::FieldReader); +impl REQ_STOP_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + REQ_STOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REQ_STOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REQ_STOP` writer - Stop Request"] +pub struct REQ_STOP_W<'a> { + w: &'a mut W, +} +impl<'a> REQ_STOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Counter Active"] + #[inline(always)] + pub fn active(&self) -> ACTIVE_R { + ACTIVE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_disable(&self) -> AUTO_DISABLE_R { + AUTO_DISABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_deactivate(&self) -> AUTO_DEACTIVATE_R { + AUTO_DEACTIVATE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Interrupt Enable"] + #[inline(always)] + pub fn irq_enb(&self) -> IRQ_ENB_R { + IRQ_ENB_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:7 - Counter Status Selection"] + #[inline(always)] + pub fn status_sel(&self) -> STATUS_SEL_R { + STATUS_SEL_R::new(((self.bits >> 5) & 0x07) as u8) + } + #[doc = "Bit 8 - Invert the Output Status"] + #[inline(always)] + pub fn status_inv(&self) -> STATUS_INV_R { + STATUS_INV_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Stop Request"] + #[inline(always)] + pub fn req_stop(&self) -> REQ_STOP_R { + REQ_STOP_R::new(((self.bits >> 9) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_disable(&mut self) -> AUTO_DISABLE_W { + AUTO_DISABLE_W { w: self } + } + #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_deactivate(&mut self) -> AUTO_DEACTIVATE_W { + AUTO_DEACTIVATE_W { w: self } + } + #[doc = "Bit 4 - Interrupt Enable"] + #[inline(always)] + pub fn irq_enb(&mut self) -> IRQ_ENB_W { + IRQ_ENB_W { w: self } + } + #[doc = "Bits 5:7 - Counter Status Selection"] + #[inline(always)] + pub fn status_sel(&mut self) -> STATUS_SEL_W { + STATUS_SEL_W { w: self } + } + #[doc = "Bit 8 - Invert the Output Status"] + #[inline(always)] + pub fn status_inv(&mut self) -> STATUS_INV_W { + STATUS_INV_W { w: self } + } + #[doc = "Bit 9 - Stop Request"] + #[inline(always)] + pub fn req_stop(&mut self) -> REQ_STOP_W { + REQ_STOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/enable.rs b/src/tim0/enable.rs new file mode 100644 index 0000000..90b8636 --- /dev/null +++ b/src/tim0/enable.rs @@ -0,0 +1,113 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Counter Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Counter Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/perid.rs b/src/tim0/perid.rs new file mode 100644 index 0000000..d856042 --- /dev/null +++ b/src/tim0/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0211_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0211_07e9 + } +} diff --git a/src/tim0/pwm_value.rs b/src/tim0/pwm_value.rs new file mode 100644 index 0000000..53907ff --- /dev/null +++ b/src/tim0/pwm_value.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PWM_VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PWM_VALUE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The Pulse Width Modulation Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwm_value](index.html) module"] +pub struct PWM_VALUE_SPEC; +impl crate::RegisterSpec for PWM_VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pwm_value::R](R) reader structure"] +impl crate::Readable for PWM_VALUE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pwm_value::W](W) writer structure"] +impl crate::Writable for PWM_VALUE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PWM_VALUE to value 0"] +impl crate::Resettable for PWM_VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/pwma_value.rs b/src/tim0/pwma_value.rs new file mode 100644 index 0000000..90752f9 --- /dev/null +++ b/src/tim0/pwma_value.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PWMA_VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PWMA_VALUE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The Pulse Width Modulation ValueA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwma_value](index.html) module"] +pub struct PWMA_VALUE_SPEC; +impl crate::RegisterSpec for PWMA_VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pwma_value::R](R) reader structure"] +impl crate::Readable for PWMA_VALUE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pwma_value::W](W) writer structure"] +impl crate::Writable for PWMA_VALUE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PWMA_VALUE to value 0"] +impl crate::Resettable for PWMA_VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/pwmb_value.rs b/src/tim0/pwmb_value.rs new file mode 100644 index 0000000..ac2f4ed --- /dev/null +++ b/src/tim0/pwmb_value.rs @@ -0,0 +1,64 @@ +#[doc = "Register `PWMB_VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PWMB_VALUE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The Pulse Width Modulation ValueB\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwmb_value](index.html) module"] +pub struct PWMB_VALUE_SPEC; +impl crate::RegisterSpec for PWMB_VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pwmb_value::R](R) reader structure"] +impl crate::Readable for PWMB_VALUE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pwmb_value::W](W) writer structure"] +impl crate::Writable for PWMB_VALUE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PWMB_VALUE to value 0"] +impl crate::Resettable for PWMB_VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/tim0/rst_value.rs b/src/tim0/rst_value.rs new file mode 100644 index 0000000..c5823b7 --- /dev/null +++ b/src/tim0/rst_value.rs @@ -0,0 +1,64 @@ +#[doc = "Register `RST_VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RST_VALUE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "The value that counter start from after reaching 0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_value](index.html) module"] +pub struct RST_VALUE_SPEC; +impl crate::RegisterSpec for RST_VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rst_value::R](R) reader structure"] +impl crate::Readable for RST_VALUE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rst_value::W](W) writer structure"] +impl crate::Writable for RST_VALUE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RST_VALUE to value 0"] +impl crate::Resettable for RST_VALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng.rs b/src/trng.rs new file mode 100644 index 0000000..7dde357 --- /dev/null +++ b/src/trng.rs @@ -0,0 +1,134 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x0100], + #[doc = "0x100 - Interrupt Mask Register"] + pub imr: crate::Reg, + #[doc = "0x104 - Interrupt Status Register"] + pub isr: crate::Reg, + #[doc = "0x108 - Interrupt Clear Register"] + pub icr: crate::Reg, + #[doc = "0x10c - Configuration Register"] + pub config: crate::Reg, + #[doc = "0x110 - Valid Register"] + pub valid: crate::Reg, + #[doc = "0x114 - Entropy Holding Register Data Register"] + pub ehr_data0: crate::Reg, + #[doc = "0x118 - Entropy Holding Register Data Register"] + pub ehr_data1: crate::Reg, + #[doc = "0x11c - Entropy Holding Register Data Register"] + pub ehr_data2: crate::Reg, + #[doc = "0x120 - Entropy Holding Register Data Register"] + pub ehr_data3: crate::Reg, + #[doc = "0x124 - Entropy Holding Register Data Register"] + pub ehr_data4: crate::Reg, + #[doc = "0x128 - Entropy Holding Register Data Register"] + pub ehr_data5: crate::Reg, + #[doc = "0x12c - Random Source Enable Register"] + pub rnd_source_enable: crate::Reg, + #[doc = "0x130 - Section TBD"] + pub sample_cnt1: crate::Reg, + #[doc = "0x134 - Auto-correlator Statistic Register"] + pub autocorr_statistic: crate::Reg, + #[doc = "0x138 - Section TBD"] + pub debug_control: crate::Reg, + _reserved15: [u8; 0x04], + #[doc = "0x140 - Reset Register"] + pub sw_reset: crate::Reg, + _reserved16: [u8; 0x74], + #[doc = "0x1b8 - Busy Register"] + pub busy: crate::Reg, + #[doc = "0x1bc - Reset Bits Counter Register"] + pub rst_bits_counter: crate::Reg, + _reserved18: [u8; 0x20], + #[doc = "0x1e0 - BIST Counter Register"] + pub bist_cntr0: crate::Reg, + #[doc = "0x1e4 - BIST Counter Register"] + pub bist_cntr1: crate::Reg, + #[doc = "0x1e8 - BIST Counter Register"] + pub bist_cntr2: crate::Reg, +} +#[doc = "IMR register accessor: an alias for `Reg`"] +pub type IMR = crate::Reg; +#[doc = "Interrupt Mask Register"] +pub mod imr; +#[doc = "ISR register accessor: an alias for `Reg`"] +pub type ISR = crate::Reg; +#[doc = "Interrupt Status Register"] +pub mod isr; +#[doc = "ICR register accessor: an alias for `Reg`"] +pub type ICR = crate::Reg; +#[doc = "Interrupt Clear Register"] +pub mod icr; +#[doc = "CONFIG register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration Register"] +pub mod config; +#[doc = "VALID register accessor: an alias for `Reg`"] +pub type VALID = crate::Reg; +#[doc = "Valid Register"] +pub mod valid; +#[doc = "EHR_DATA0 register accessor: an alias for `Reg`"] +pub type EHR_DATA0 = crate::Reg; +#[doc = "Entropy Holding Register Data Register"] +pub mod ehr_data0; +#[doc = "EHR_DATA1 register accessor: an alias for `Reg`"] +pub type EHR_DATA1 = crate::Reg; +#[doc = "Entropy Holding Register Data Register"] +pub mod ehr_data1; +#[doc = "EHR_DATA2 register accessor: an alias for `Reg`"] +pub type EHR_DATA2 = crate::Reg; +#[doc = "Entropy Holding Register Data Register"] +pub mod ehr_data2; +#[doc = "EHR_DATA3 register accessor: an alias for `Reg`"] +pub type EHR_DATA3 = crate::Reg; +#[doc = "Entropy Holding Register Data Register"] +pub mod ehr_data3; +#[doc = "EHR_DATA4 register accessor: an alias for `Reg`"] +pub type EHR_DATA4 = crate::Reg; +#[doc = "Entropy Holding Register Data Register"] +pub mod ehr_data4; +#[doc = "EHR_DATA5 register accessor: an alias for `Reg`"] +pub type EHR_DATA5 = crate::Reg; +#[doc = "Entropy Holding Register Data Register"] +pub mod ehr_data5; +#[doc = "RND_SOURCE_ENABLE register accessor: an alias for `Reg`"] +pub type RND_SOURCE_ENABLE = crate::Reg; +#[doc = "Random Source Enable Register"] +pub mod rnd_source_enable; +#[doc = "SAMPLE_CNT1 register accessor: an alias for `Reg`"] +pub type SAMPLE_CNT1 = crate::Reg; +#[doc = "Section TBD"] +pub mod sample_cnt1; +#[doc = "AUTOCORR_STATISTIC register accessor: an alias for `Reg`"] +pub type AUTOCORR_STATISTIC = crate::Reg; +#[doc = "Auto-correlator Statistic Register"] +pub mod autocorr_statistic; +#[doc = "DEBUG_CONTROL register accessor: an alias for `Reg`"] +pub type DEBUG_CONTROL = crate::Reg; +#[doc = "Section TBD"] +pub mod debug_control; +#[doc = "SW_RESET register accessor: an alias for `Reg`"] +pub type SW_RESET = crate::Reg; +#[doc = "Reset Register"] +pub mod sw_reset; +#[doc = "BUSY register accessor: an alias for `Reg`"] +pub type BUSY = crate::Reg; +#[doc = "Busy Register"] +pub mod busy; +#[doc = "RST_BITS_COUNTER register accessor: an alias for `Reg`"] +pub type RST_BITS_COUNTER = crate::Reg; +#[doc = "Reset Bits Counter Register"] +pub mod rst_bits_counter; +#[doc = "BIST_CNTR0 register accessor: an alias for `Reg`"] +pub type BIST_CNTR0 = crate::Reg; +#[doc = "BIST Counter Register"] +pub mod bist_cntr0; +#[doc = "BIST_CNTR1 register accessor: an alias for `Reg`"] +pub type BIST_CNTR1 = crate::Reg; +#[doc = "BIST Counter Register"] +pub mod bist_cntr1; +#[doc = "BIST_CNTR2 register accessor: an alias for `Reg`"] +pub type BIST_CNTR2 = crate::Reg; +#[doc = "BIST Counter Register"] +pub mod bist_cntr2; diff --git a/src/trng/autocorr_statistic.rs b/src/trng/autocorr_statistic.rs new file mode 100644 index 0000000..de2d010 --- /dev/null +++ b/src/trng/autocorr_statistic.rs @@ -0,0 +1,140 @@ +#[doc = "Register `AUTOCORR_STATISTIC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AUTOCORR_STATISTIC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOCORR_FAILS` reader - Count each time an autocorrelation test fails"] +pub struct AUTOCORR_FAILS_R(crate::FieldReader); +impl AUTOCORR_FAILS_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + AUTOCORR_FAILS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOCORR_FAILS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOCORR_FAILS` writer - Count each time an autocorrelation test fails"] +pub struct AUTOCORR_FAILS_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOCORR_FAILS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 14)) | ((value as u32 & 0xff) << 14); + self.w + } +} +#[doc = "Field `AUTOCORR_TRYS` reader - Count each time an autocorrelation test starts"] +pub struct AUTOCORR_TRYS_R(crate::FieldReader); +impl AUTOCORR_TRYS_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + AUTOCORR_TRYS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOCORR_TRYS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOCORR_TRYS` writer - Count each time an autocorrelation test starts"] +pub struct AUTOCORR_TRYS_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOCORR_TRYS_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3fff) | (value as u32 & 0x3fff); + self.w + } +} +impl R { + #[doc = "Bits 14:21 - Count each time an autocorrelation test fails"] + #[inline(always)] + pub fn autocorr_fails(&self) -> AUTOCORR_FAILS_R { + AUTOCORR_FAILS_R::new(((self.bits >> 14) & 0xff) as u8) + } + #[doc = "Bits 0:13 - Count each time an autocorrelation test starts"] + #[inline(always)] + pub fn autocorr_trys(&self) -> AUTOCORR_TRYS_R { + AUTOCORR_TRYS_R::new((self.bits & 0x3fff) as u16) + } +} +impl W { + #[doc = "Bits 14:21 - Count each time an autocorrelation test fails"] + #[inline(always)] + pub fn autocorr_fails(&mut self) -> AUTOCORR_FAILS_W { + AUTOCORR_FAILS_W { w: self } + } + #[doc = "Bits 0:13 - Count each time an autocorrelation test starts"] + #[inline(always)] + pub fn autocorr_trys(&mut self) -> AUTOCORR_TRYS_W { + AUTOCORR_TRYS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Auto-correlator Statistic Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [autocorr_statistic](index.html) module"] +pub struct AUTOCORR_STATISTIC_SPEC; +impl crate::RegisterSpec for AUTOCORR_STATISTIC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [autocorr_statistic::R](R) reader structure"] +impl crate::Readable for AUTOCORR_STATISTIC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [autocorr_statistic::W](W) writer structure"] +impl crate::Writable for AUTOCORR_STATISTIC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AUTOCORR_STATISTIC to value 0"] +impl crate::Resettable for AUTOCORR_STATISTIC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/bist_cntr0.rs b/src/trng/bist_cntr0.rs new file mode 100644 index 0000000..30c0714 --- /dev/null +++ b/src/trng/bist_cntr0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `BIST_CNTR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROSC_CNTR_VAL` reader - Returns the results of the TRNG BIST counter"] +pub struct ROSC_CNTR_VAL_R(crate::FieldReader); +impl ROSC_CNTR_VAL_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ROSC_CNTR_VAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROSC_CNTR_VAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:21 - Returns the results of the TRNG BIST counter"] + #[inline(always)] + pub fn rosc_cntr_val(&self) -> ROSC_CNTR_VAL_R { + ROSC_CNTR_VAL_R::new((self.bits & 0x003f_ffff) as u32) + } +} +#[doc = "BIST Counter Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bist_cntr0](index.html) module"] +pub struct BIST_CNTR0_SPEC; +impl crate::RegisterSpec for BIST_CNTR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bist_cntr0::R](R) reader structure"] +impl crate::Readable for BIST_CNTR0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BIST_CNTR0 to value 0"] +impl crate::Resettable for BIST_CNTR0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/bist_cntr1.rs b/src/trng/bist_cntr1.rs new file mode 100644 index 0000000..a7bf711 --- /dev/null +++ b/src/trng/bist_cntr1.rs @@ -0,0 +1,53 @@ +#[doc = "Register `BIST_CNTR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROSC_CNTR_VAL` reader - Returns the results of the TRNG BIST counter"] +pub struct ROSC_CNTR_VAL_R(crate::FieldReader); +impl ROSC_CNTR_VAL_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ROSC_CNTR_VAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROSC_CNTR_VAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:21 - Returns the results of the TRNG BIST counter"] + #[inline(always)] + pub fn rosc_cntr_val(&self) -> ROSC_CNTR_VAL_R { + ROSC_CNTR_VAL_R::new((self.bits & 0x003f_ffff) as u32) + } +} +#[doc = "BIST Counter Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bist_cntr1](index.html) module"] +pub struct BIST_CNTR1_SPEC; +impl crate::RegisterSpec for BIST_CNTR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bist_cntr1::R](R) reader structure"] +impl crate::Readable for BIST_CNTR1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BIST_CNTR1 to value 0"] +impl crate::Resettable for BIST_CNTR1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/bist_cntr2.rs b/src/trng/bist_cntr2.rs new file mode 100644 index 0000000..b0ff0e1 --- /dev/null +++ b/src/trng/bist_cntr2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `BIST_CNTR2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ROSC_CNTR_VAL` reader - Returns the results of the TRNG BIST counter"] +pub struct ROSC_CNTR_VAL_R(crate::FieldReader); +impl ROSC_CNTR_VAL_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ROSC_CNTR_VAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROSC_CNTR_VAL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:21 - Returns the results of the TRNG BIST counter"] + #[inline(always)] + pub fn rosc_cntr_val(&self) -> ROSC_CNTR_VAL_R { + ROSC_CNTR_VAL_R::new((self.bits & 0x003f_ffff) as u32) + } +} +#[doc = "BIST Counter Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bist_cntr2](index.html) module"] +pub struct BIST_CNTR2_SPEC; +impl crate::RegisterSpec for BIST_CNTR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bist_cntr2::R](R) reader structure"] +impl crate::Readable for BIST_CNTR2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BIST_CNTR2 to value 0"] +impl crate::Resettable for BIST_CNTR2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/busy.rs b/src/trng/busy.rs new file mode 100644 index 0000000..dbfe6ca --- /dev/null +++ b/src/trng/busy.rs @@ -0,0 +1,53 @@ +#[doc = "Register `BUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSY` reader - Reflects the status of the rng_busy signal"] +pub struct BUSY_R(crate::FieldReader); +impl BUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Reflects the status of the rng_busy signal"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busy](index.html) module"] +pub struct BUSY_SPEC; +impl crate::RegisterSpec for BUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busy::R](R) reader structure"] +impl crate::Readable for BUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSY to value 0"] +impl crate::Resettable for BUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/config.rs b/src/trng/config.rs new file mode 100644 index 0000000..bd0fd94 --- /dev/null +++ b/src/trng/config.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RND_SRC_SEL` reader - Selects the number of inverters (out of four possible selections) in the ring oscillator"] +pub struct RND_SRC_SEL_R(crate::FieldReader); +impl RND_SRC_SEL_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RND_SRC_SEL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RND_SRC_SEL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RND_SRC_SEL` writer - Selects the number of inverters (out of four possible selections) in the ring oscillator"] +pub struct RND_SRC_SEL_W<'a> { + w: &'a mut W, +} +impl<'a> RND_SRC_SEL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Selects the number of inverters (out of four possible selections) in the ring oscillator"] + #[inline(always)] + pub fn rnd_src_sel(&self) -> RND_SRC_SEL_R { + RND_SRC_SEL_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects the number of inverters (out of four possible selections) in the ring oscillator"] + #[inline(always)] + pub fn rnd_src_sel(&mut self) -> RND_SRC_SEL_W { + RND_SRC_SEL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for CONFIG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/debug_control.rs b/src/trng/debug_control.rs new file mode 100644 index 0000000..324f6f9 --- /dev/null +++ b/src/trng/debug_control.rs @@ -0,0 +1,207 @@ +#[doc = "Register `DEBUG_CONTROL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DEBUG_CONTROL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTO_CORRELATE_BYPASS` reader - The autocorrelation test in the TRNG module is bypassed"] +pub struct AUTO_CORRELATE_BYPASS_R(crate::FieldReader); +impl AUTO_CORRELATE_BYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTO_CORRELATE_BYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTO_CORRELATE_BYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTO_CORRELATE_BYPASS` writer - The autocorrelation test in the TRNG module is bypassed"] +pub struct AUTO_CORRELATE_BYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> AUTO_CORRELATE_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CRNGT_BYPASS` reader - The CRNGT test in the TRNG is bypassed"] +pub struct CRNGT_BYPASS_R(crate::FieldReader); +impl CRNGT_BYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRNGT_BYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRNGT_BYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRNGT_BYPASS` writer - The CRNGT test in the TRNG is bypassed"] +pub struct CRNGT_BYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> CRNGT_BYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `VNC_PYPASS` reader - The Von Neumann balancer is bypassed"] +pub struct VNC_PYPASS_R(crate::FieldReader); +impl VNC_PYPASS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VNC_PYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VNC_PYPASS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VNC_PYPASS` writer - The Von Neumann balancer is bypassed"] +pub struct VNC_PYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> VNC_PYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 3 - The autocorrelation test in the TRNG module is bypassed"] + #[inline(always)] + pub fn auto_correlate_bypass(&self) -> AUTO_CORRELATE_BYPASS_R { + AUTO_CORRELATE_BYPASS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - The CRNGT test in the TRNG is bypassed"] + #[inline(always)] + pub fn crngt_bypass(&self) -> CRNGT_BYPASS_R { + CRNGT_BYPASS_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - The Von Neumann balancer is bypassed"] + #[inline(always)] + pub fn vnc_pypass(&self) -> VNC_PYPASS_R { + VNC_PYPASS_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - The autocorrelation test in the TRNG module is bypassed"] + #[inline(always)] + pub fn auto_correlate_bypass(&mut self) -> AUTO_CORRELATE_BYPASS_W { + AUTO_CORRELATE_BYPASS_W { w: self } + } + #[doc = "Bit 2 - The CRNGT test in the TRNG is bypassed"] + #[inline(always)] + pub fn crngt_bypass(&mut self) -> CRNGT_BYPASS_W { + CRNGT_BYPASS_W { w: self } + } + #[doc = "Bit 1 - The Von Neumann balancer is bypassed"] + #[inline(always)] + pub fn vnc_pypass(&mut self) -> VNC_PYPASS_W { + VNC_PYPASS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Section TBD\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [debug_control](index.html) module"] +pub struct DEBUG_CONTROL_SPEC; +impl crate::RegisterSpec for DEBUG_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [debug_control::R](R) reader structure"] +impl crate::Readable for DEBUG_CONTROL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [debug_control::W](W) writer structure"] +impl crate::Writable for DEBUG_CONTROL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DEBUG_CONTROL to value 0"] +impl crate::Resettable for DEBUG_CONTROL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/ehr_data0.rs b/src/trng/ehr_data0.rs new file mode 100644 index 0000000..c450ab8 --- /dev/null +++ b/src/trng/ehr_data0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `EHR_DATA0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EHR_DATA` reader - 32 Bits of Entropy Holding Register"] +pub struct EHR_DATA_R(crate::FieldReader); +impl EHR_DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EHR_DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - 32 Bits of Entropy Holding Register"] + #[inline(always)] + pub fn ehr_data(&self) -> EHR_DATA_R { + EHR_DATA_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "Entropy Holding Register Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ehr_data0](index.html) module"] +pub struct EHR_DATA0_SPEC; +impl crate::RegisterSpec for EHR_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ehr_data0::R](R) reader structure"] +impl crate::Readable for EHR_DATA0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EHR_DATA0 to value 0"] +impl crate::Resettable for EHR_DATA0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/ehr_data1.rs b/src/trng/ehr_data1.rs new file mode 100644 index 0000000..ead896d --- /dev/null +++ b/src/trng/ehr_data1.rs @@ -0,0 +1,53 @@ +#[doc = "Register `EHR_DATA1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EHR_DATA` reader - 32 Bits of Entropy Holding Register"] +pub struct EHR_DATA_R(crate::FieldReader); +impl EHR_DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EHR_DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - 32 Bits of Entropy Holding Register"] + #[inline(always)] + pub fn ehr_data(&self) -> EHR_DATA_R { + EHR_DATA_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "Entropy Holding Register Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ehr_data1](index.html) module"] +pub struct EHR_DATA1_SPEC; +impl crate::RegisterSpec for EHR_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ehr_data1::R](R) reader structure"] +impl crate::Readable for EHR_DATA1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EHR_DATA1 to value 0"] +impl crate::Resettable for EHR_DATA1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/ehr_data2.rs b/src/trng/ehr_data2.rs new file mode 100644 index 0000000..deb4651 --- /dev/null +++ b/src/trng/ehr_data2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `EHR_DATA2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EHR_DATA` reader - 32 Bits of Entropy Holding Register"] +pub struct EHR_DATA_R(crate::FieldReader); +impl EHR_DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EHR_DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - 32 Bits of Entropy Holding Register"] + #[inline(always)] + pub fn ehr_data(&self) -> EHR_DATA_R { + EHR_DATA_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "Entropy Holding Register Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ehr_data2](index.html) module"] +pub struct EHR_DATA2_SPEC; +impl crate::RegisterSpec for EHR_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ehr_data2::R](R) reader structure"] +impl crate::Readable for EHR_DATA2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EHR_DATA2 to value 0"] +impl crate::Resettable for EHR_DATA2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/ehr_data3.rs b/src/trng/ehr_data3.rs new file mode 100644 index 0000000..1c9406d --- /dev/null +++ b/src/trng/ehr_data3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `EHR_DATA3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EHR_DATA` reader - 32 Bits of Entropy Holding Register"] +pub struct EHR_DATA_R(crate::FieldReader); +impl EHR_DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EHR_DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - 32 Bits of Entropy Holding Register"] + #[inline(always)] + pub fn ehr_data(&self) -> EHR_DATA_R { + EHR_DATA_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "Entropy Holding Register Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ehr_data3](index.html) module"] +pub struct EHR_DATA3_SPEC; +impl crate::RegisterSpec for EHR_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ehr_data3::R](R) reader structure"] +impl crate::Readable for EHR_DATA3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EHR_DATA3 to value 0"] +impl crate::Resettable for EHR_DATA3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/ehr_data4.rs b/src/trng/ehr_data4.rs new file mode 100644 index 0000000..5086ef3 --- /dev/null +++ b/src/trng/ehr_data4.rs @@ -0,0 +1,53 @@ +#[doc = "Register `EHR_DATA4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EHR_DATA` reader - 32 Bits of Entropy Holding Register"] +pub struct EHR_DATA_R(crate::FieldReader); +impl EHR_DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EHR_DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - 32 Bits of Entropy Holding Register"] + #[inline(always)] + pub fn ehr_data(&self) -> EHR_DATA_R { + EHR_DATA_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "Entropy Holding Register Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ehr_data4](index.html) module"] +pub struct EHR_DATA4_SPEC; +impl crate::RegisterSpec for EHR_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ehr_data4::R](R) reader structure"] +impl crate::Readable for EHR_DATA4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EHR_DATA4 to value 0"] +impl crate::Resettable for EHR_DATA4_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/ehr_data5.rs b/src/trng/ehr_data5.rs new file mode 100644 index 0000000..bbe7e2e --- /dev/null +++ b/src/trng/ehr_data5.rs @@ -0,0 +1,53 @@ +#[doc = "Register `EHR_DATA5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EHR_DATA` reader - 32 Bits of Entropy Holding Register"] +pub struct EHR_DATA_R(crate::FieldReader); +impl EHR_DATA_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + EHR_DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - 32 Bits of Entropy Holding Register"] + #[inline(always)] + pub fn ehr_data(&self) -> EHR_DATA_R { + EHR_DATA_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "Entropy Holding Register Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ehr_data5](index.html) module"] +pub struct EHR_DATA5_SPEC; +impl crate::RegisterSpec for EHR_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ehr_data5::R](R) reader structure"] +impl crate::Readable for EHR_DATA5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EHR_DATA5 to value 0"] +impl crate::Resettable for EHR_DATA5_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/icr.rs b/src/trng/icr.rs new file mode 100644 index 0000000..1344396 --- /dev/null +++ b/src/trng/icr.rs @@ -0,0 +1,258 @@ +#[doc = "Register `ICR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ICR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VN_ERR` reader - Clears a Von Neumann error"] +pub struct VN_ERR_R(crate::FieldReader); +impl VN_ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VN_ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VN_ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VN_ERR` writer - Clears a Von Neumann error"] +pub struct VN_ERR_W<'a> { + w: &'a mut W, +} +impl<'a> VN_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CRNGT_ERR` reader - Clear a Continuous Random Number Generation Testing (CRNGT) error"] +pub struct CRNGT_ERR_R(crate::FieldReader); +impl CRNGT_ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRNGT_ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRNGT_ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRNGT_ERR` writer - Clear a Continuous Random Number Generation Testing (CRNGT) error"] +pub struct CRNGT_ERR_W<'a> { + w: &'a mut W, +} +impl<'a> CRNGT_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `AUTOCORR_ERR` reader - Software cannot clear this bit. Only a TRNG reset can clear this bit"] +pub struct AUTOCORR_ERR_R(crate::FieldReader); +impl AUTOCORR_ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOCORR_ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOCORR_ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOCORR_ERR` writer - Software cannot clear this bit. Only a TRNG reset can clear this bit"] +pub struct AUTOCORR_ERR_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOCORR_ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EHR_VALID` reader - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] +registers have been read"] +pub struct EHR_VALID_R(crate::FieldReader); +impl EHR_VALID_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EHR_VALID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_VALID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EHR_VALID` writer - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] +registers have been read"] +pub struct EHR_VALID_W<'a> { + w: &'a mut W, +} +impl<'a> EHR_VALID_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Clears a Von Neumann error"] + #[inline(always)] + pub fn vn_err(&self) -> VN_ERR_R { + VN_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Clear a Continuous Random Number Generation Testing (CRNGT) error"] + #[inline(always)] + pub fn crngt_err(&self) -> CRNGT_ERR_R { + CRNGT_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Software cannot clear this bit. Only a TRNG reset can clear this bit"] + #[inline(always)] + pub fn autocorr_err(&self) -> AUTOCORR_ERR_R { + AUTOCORR_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] +registers have been read"] + #[inline(always)] + pub fn ehr_valid(&self) -> EHR_VALID_R { + EHR_VALID_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Clears a Von Neumann error"] + #[inline(always)] + pub fn vn_err(&mut self) -> VN_ERR_W { + VN_ERR_W { w: self } + } + #[doc = "Bit 2 - Clear a Continuous Random Number Generation Testing (CRNGT) error"] + #[inline(always)] + pub fn crngt_err(&mut self) -> CRNGT_ERR_W { + CRNGT_ERR_W { w: self } + } + #[doc = "Bit 1 - Software cannot clear this bit. Only a TRNG reset can clear this bit"] + #[inline(always)] + pub fn autocorr_err(&mut self) -> AUTOCORR_ERR_W { + AUTOCORR_ERR_W { w: self } + } + #[doc = "Bit 0 - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] +registers have been read"] + #[inline(always)] + pub fn ehr_valid(&mut self) -> EHR_VALID_W { + EHR_VALID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"] +pub struct ICR_SPEC; +impl crate::RegisterSpec for ICR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [icr::R](R) reader structure"] +impl crate::Readable for ICR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"] +impl crate::Writable for ICR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ICR to value 0"] +impl crate::Resettable for ICR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/imr.rs b/src/trng/imr.rs new file mode 100644 index 0000000..cb4bb2c --- /dev/null +++ b/src/trng/imr.rs @@ -0,0 +1,254 @@ +#[doc = "Register `IMR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IMR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VN_ERR_INT_MASK` reader - Mask the Von Neumann error"] +pub struct VN_ERR_INT_MASK_R(crate::FieldReader); +impl VN_ERR_INT_MASK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VN_ERR_INT_MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VN_ERR_INT_MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `VN_ERR_INT_MASK` writer - Mask the Von Neumann error"] +pub struct VN_ERR_INT_MASK_W<'a> { + w: &'a mut W, +} +impl<'a> VN_ERR_INT_MASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `CRNGT_ERR_INT_MASK` reader - Mask the CRNGT error"] +pub struct CRNGT_ERR_INT_MASK_R(crate::FieldReader); +impl CRNGT_ERR_INT_MASK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRNGT_ERR_INT_MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRNGT_ERR_INT_MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRNGT_ERR_INT_MASK` writer - Mask the CRNGT error"] +pub struct CRNGT_ERR_INT_MASK_W<'a> { + w: &'a mut W, +} +impl<'a> CRNGT_ERR_INT_MASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `AUTOCORR_ERR_INT_MASK` reader - Mask the Autocorrelation error"] +pub struct AUTOCORR_ERR_INT_MASK_R(crate::FieldReader); +impl AUTOCORR_ERR_INT_MASK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOCORR_ERR_INT_MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOCORR_ERR_INT_MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOCORR_ERR_INT_MASK` writer - Mask the Autocorrelation error"] +pub struct AUTOCORR_ERR_INT_MASK_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOCORR_ERR_INT_MASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `EHR_VALID_INT_MASK` reader - Mask when the TRNG has collected 192 bits"] +pub struct EHR_VALID_INT_MASK_R(crate::FieldReader); +impl EHR_VALID_INT_MASK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EHR_VALID_INT_MASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_VALID_INT_MASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EHR_VALID_INT_MASK` writer - Mask when the TRNG has collected 192 bits"] +pub struct EHR_VALID_INT_MASK_W<'a> { + w: &'a mut W, +} +impl<'a> EHR_VALID_INT_MASK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 3 - Mask the Von Neumann error"] + #[inline(always)] + pub fn vn_err_int_mask(&self) -> VN_ERR_INT_MASK_R { + VN_ERR_INT_MASK_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Mask the CRNGT error"] + #[inline(always)] + pub fn crngt_err_int_mask(&self) -> CRNGT_ERR_INT_MASK_R { + CRNGT_ERR_INT_MASK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Mask the Autocorrelation error"] + #[inline(always)] + pub fn autocorr_err_int_mask(&self) -> AUTOCORR_ERR_INT_MASK_R { + AUTOCORR_ERR_INT_MASK_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Mask when the TRNG has collected 192 bits"] + #[inline(always)] + pub fn ehr_valid_int_mask(&self) -> EHR_VALID_INT_MASK_R { + EHR_VALID_INT_MASK_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 3 - Mask the Von Neumann error"] + #[inline(always)] + pub fn vn_err_int_mask(&mut self) -> VN_ERR_INT_MASK_W { + VN_ERR_INT_MASK_W { w: self } + } + #[doc = "Bit 2 - Mask the CRNGT error"] + #[inline(always)] + pub fn crngt_err_int_mask(&mut self) -> CRNGT_ERR_INT_MASK_W { + CRNGT_ERR_INT_MASK_W { w: self } + } + #[doc = "Bit 1 - Mask the Autocorrelation error"] + #[inline(always)] + pub fn autocorr_err_int_mask(&mut self) -> AUTOCORR_ERR_INT_MASK_W { + AUTOCORR_ERR_INT_MASK_W { w: self } + } + #[doc = "Bit 0 - Mask when the TRNG has collected 192 bits"] + #[inline(always)] + pub fn ehr_valid_int_mask(&mut self) -> EHR_VALID_INT_MASK_W { + EHR_VALID_INT_MASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +pub struct IMR_SPEC; +impl crate::RegisterSpec for IMR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [imr::R](R) reader structure"] +impl crate::Readable for IMR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [imr::W](W) writer structure"] +impl crate::Writable for IMR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IMR to value 0x0f"] +impl crate::Resettable for IMR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0f + } +} diff --git a/src/trng/isr.rs b/src/trng/isr.rs new file mode 100644 index 0000000..950fb74 --- /dev/null +++ b/src/trng/isr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `ISR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VN_ERR` reader - Indicates a Von Neumann error"] +pub struct VN_ERR_R(crate::FieldReader); +impl VN_ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + VN_ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for VN_ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRNGT_ERR` reader - Indicates a Continuous Random Number Generation Testing (CRNGT) error"] +pub struct CRNGT_ERR_R(crate::FieldReader); +impl CRNGT_ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + CRNGT_ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRNGT_ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOCORR_ERR` reader - Indicates that the Autocorrelation test failed four times in a row"] +pub struct AUTOCORR_ERR_R(crate::FieldReader); +impl AUTOCORR_ERR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOCORR_ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOCORR_ERR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EHR_VALID` reader - 192 bits have been collected in the TRNG"] +pub struct EHR_VALID_R(crate::FieldReader); +impl EHR_VALID_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EHR_VALID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_VALID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 3 - Indicates a Von Neumann error"] + #[inline(always)] + pub fn vn_err(&self) -> VN_ERR_R { + VN_ERR_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 2 - Indicates a Continuous Random Number Generation Testing (CRNGT) error"] + #[inline(always)] + pub fn crngt_err(&self) -> CRNGT_ERR_R { + CRNGT_ERR_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 1 - Indicates that the Autocorrelation test failed four times in a row"] + #[inline(always)] + pub fn autocorr_err(&self) -> AUTOCORR_ERR_R { + AUTOCORR_ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - 192 bits have been collected in the TRNG"] + #[inline(always)] + pub fn ehr_valid(&self) -> EHR_VALID_R { + EHR_VALID_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] +pub struct ISR_SPEC; +impl crate::RegisterSpec for ISR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [isr::R](R) reader structure"] +impl crate::Readable for ISR_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ISR to value 0"] +impl crate::Resettable for ISR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/rnd_source_enable.rs b/src/trng/rnd_source_enable.rs new file mode 100644 index 0000000..cd3415c --- /dev/null +++ b/src/trng/rnd_source_enable.rs @@ -0,0 +1,113 @@ +#[doc = "Register `RND_SOURCE_ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RND_SOURCE_ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RND_SRC_EN` reader - The entropy source, ring oscillator, is enabled"] +pub struct RND_SRC_EN_R(crate::FieldReader); +impl RND_SRC_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RND_SRC_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RND_SRC_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RND_SRC_EN` writer - The entropy source, ring oscillator, is enabled"] +pub struct RND_SRC_EN_W<'a> { + w: &'a mut W, +} +impl<'a> RND_SRC_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - The entropy source, ring oscillator, is enabled"] + #[inline(always)] + pub fn rnd_src_en(&self) -> RND_SRC_EN_R { + RND_SRC_EN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - The entropy source, ring oscillator, is enabled"] + #[inline(always)] + pub fn rnd_src_en(&mut self) -> RND_SRC_EN_W { + RND_SRC_EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Random Source Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rnd_source_enable](index.html) module"] +pub struct RND_SOURCE_ENABLE_SPEC; +impl crate::RegisterSpec for RND_SOURCE_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rnd_source_enable::R](R) reader structure"] +impl crate::Readable for RND_SOURCE_ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rnd_source_enable::W](W) writer structure"] +impl crate::Writable for RND_SOURCE_ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RND_SOURCE_ENABLE to value 0"] +impl crate::Resettable for RND_SOURCE_ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/rst_bits_counter.rs b/src/trng/rst_bits_counter.rs new file mode 100644 index 0000000..36ccc4d --- /dev/null +++ b/src/trng/rst_bits_counter.rs @@ -0,0 +1,113 @@ +#[doc = "Register `RST_BITS_COUNTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RST_BITS_COUNTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RST_BITS_COUNTER` reader - Writing any value to this bit resets the bits counter and TRNG valid registers"] +pub struct RST_BITS_COUNTER_R(crate::FieldReader); +impl RST_BITS_COUNTER_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RST_BITS_COUNTER_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RST_BITS_COUNTER_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RST_BITS_COUNTER` writer - Writing any value to this bit resets the bits counter and TRNG valid registers"] +pub struct RST_BITS_COUNTER_W<'a> { + w: &'a mut W, +} +impl<'a> RST_BITS_COUNTER_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Writing any value to this bit resets the bits counter and TRNG valid registers"] + #[inline(always)] + pub fn rst_bits_counter(&self) -> RST_BITS_COUNTER_R { + RST_BITS_COUNTER_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Writing any value to this bit resets the bits counter and TRNG valid registers"] + #[inline(always)] + pub fn rst_bits_counter(&mut self) -> RST_BITS_COUNTER_W { + RST_BITS_COUNTER_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reset Bits Counter Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rst_bits_counter](index.html) module"] +pub struct RST_BITS_COUNTER_SPEC; +impl crate::RegisterSpec for RST_BITS_COUNTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rst_bits_counter::R](R) reader structure"] +impl crate::Readable for RST_BITS_COUNTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rst_bits_counter::W](W) writer structure"] +impl crate::Writable for RST_BITS_COUNTER_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RST_BITS_COUNTER to value 0"] +impl crate::Resettable for RST_BITS_COUNTER_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/sample_cnt1.rs b/src/trng/sample_cnt1.rs new file mode 100644 index 0000000..d557b43 --- /dev/null +++ b/src/trng/sample_cnt1.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SAMPLE_CNT1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPLE_CNT1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLE_CNTR1` reader - Sets the number of clk cycles between two consecutive ring oscillator samples"] +pub struct SAMPLE_CNTR1_R(crate::FieldReader); +impl SAMPLE_CNTR1_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SAMPLE_CNTR1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SAMPLE_CNTR1_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SAMPLE_CNTR1` writer - Sets the number of clk cycles between two consecutive ring oscillator samples"] +pub struct SAMPLE_CNTR1_W<'a> { + w: &'a mut W, +} +impl<'a> SAMPLE_CNTR1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Sets the number of clk cycles between two consecutive ring oscillator samples"] + #[inline(always)] + pub fn sample_cntr1(&self) -> SAMPLE_CNTR1_R { + SAMPLE_CNTR1_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Sets the number of clk cycles between two consecutive ring oscillator samples"] + #[inline(always)] + pub fn sample_cntr1(&mut self) -> SAMPLE_CNTR1_W { + SAMPLE_CNTR1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Section TBD\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sample_cnt1](index.html) module"] +pub struct SAMPLE_CNT1_SPEC; +impl crate::RegisterSpec for SAMPLE_CNT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sample_cnt1::R](R) reader structure"] +impl crate::Readable for SAMPLE_CNT1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sample_cnt1::W](W) writer structure"] +impl crate::Writable for SAMPLE_CNT1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SAMPLE_CNT1 to value 0xffff"] +impl crate::Resettable for SAMPLE_CNT1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff + } +} diff --git a/src/trng/sw_reset.rs b/src/trng/sw_reset.rs new file mode 100644 index 0000000..bdb742c --- /dev/null +++ b/src/trng/sw_reset.rs @@ -0,0 +1,113 @@ +#[doc = "Register `SW_RESET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SW_RESET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SW_RESET` reader - Writing 1 to this register causes an internal TRNG reset"] +pub struct SW_RESET_R(crate::FieldReader); +impl SW_RESET_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + SW_RESET_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SW_RESET_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SW_RESET` writer - Writing 1 to this register causes an internal TRNG reset"] +pub struct SW_RESET_W<'a> { + w: &'a mut W, +} +impl<'a> SW_RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Writing 1 to this register causes an internal TRNG reset"] + #[inline(always)] + pub fn sw_reset(&self) -> SW_RESET_R { + SW_RESET_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Writing 1 to this register causes an internal TRNG reset"] + #[inline(always)] + pub fn sw_reset(&mut self) -> SW_RESET_W { + SW_RESET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sw_reset](index.html) module"] +pub struct SW_RESET_SPEC; +impl crate::RegisterSpec for SW_RESET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sw_reset::R](R) reader structure"] +impl crate::Readable for SW_RESET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sw_reset::W](W) writer structure"] +impl crate::Writable for SW_RESET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SW_RESET to value 0"] +impl crate::Resettable for SW_RESET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/trng/valid.rs b/src/trng/valid.rs new file mode 100644 index 0000000..3dec03a --- /dev/null +++ b/src/trng/valid.rs @@ -0,0 +1,53 @@ +#[doc = "Register `VALID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EHR_VALID` reader - Indicates that the collection of bits in the TRNG is complete"] +pub struct EHR_VALID_R(crate::FieldReader); +impl EHR_VALID_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + EHR_VALID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EHR_VALID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Indicates that the collection of bits in the TRNG is complete"] + #[inline(always)] + pub fn ehr_valid(&self) -> EHR_VALID_R { + EHR_VALID_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Valid Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [valid](index.html) module"] +pub struct VALID_SPEC; +impl crate::RegisterSpec for VALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [valid::R](R) reader structure"] +impl crate::Readable for VALID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALID to value 0"] +impl crate::Resettable for VALID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0.rs b/src/uart0.rs new file mode 100644 index 0000000..4f529a1 --- /dev/null +++ b/src/uart0.rs @@ -0,0 +1,119 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Data In/Out Register"] + pub data: crate::Reg, + #[doc = "0x04 - Enable Register"] + pub enable: crate::Reg, + #[doc = "0x08 - Control Register"] + pub ctrl: crate::Reg, + #[doc = "0x0c - Clock Scale Register"] + pub clkscale: crate::Reg, + #[doc = "0x10 - Status Register"] + pub rxstatus: crate::Reg, + #[doc = "0x14 - Status Register"] + pub txstatus: crate::Reg, + #[doc = "0x18 - Clear FIFO Register"] + pub fifo_clr: crate::Reg, + #[doc = "0x1c - Break Transmit Register"] + pub txbreak: crate::Reg, + #[doc = "0x20 - Address9 Register"] + pub addr9: crate::Reg, + #[doc = "0x24 - Address9 Mask Register"] + pub addr9mask: crate::Reg, + #[doc = "0x28 - IRQ Enable Register"] + pub irq_enb: crate::Reg, + #[doc = "0x2c - IRQ Raw Status Register"] + pub irq_raw: crate::Reg, + #[doc = "0x30 - IRQ Enabled Status Register"] + pub irq_end: crate::Reg, + #[doc = "0x34 - IRQ Clear Status Register"] + pub irq_clr: crate::Reg, + #[doc = "0x38 - Rx FIFO IRQ Trigger Level"] + pub rxfifoirqtrg: crate::Reg, + #[doc = "0x3c - Tx FIFO IRQ Trigger Level"] + pub txfifoirqtrg: crate::Reg, + #[doc = "0x40 - Rx FIFO RTS Trigger Level"] + pub rxfifortstrg: crate::Reg, + #[doc = "0x44 - Internal STATE of UART Controller"] + pub state: crate::Reg, + _reserved18: [u8; 0x0fb4], + #[doc = "0xffc - Peripheral ID Register"] + pub perid: crate::Reg, +} +#[doc = "DATA register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data In/Out Register"] +pub mod data; +#[doc = "ENABLE register accessor: an alias for `Reg`"] +pub type ENABLE = crate::Reg; +#[doc = "Enable Register"] +pub mod enable; +#[doc = "CTRL register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "CLKSCALE register accessor: an alias for `Reg`"] +pub type CLKSCALE = crate::Reg; +#[doc = "Clock Scale Register"] +pub mod clkscale; +#[doc = "RXSTATUS register accessor: an alias for `Reg`"] +pub type RXSTATUS = crate::Reg; +#[doc = "Status Register"] +pub mod rxstatus; +#[doc = "TXSTATUS register accessor: an alias for `Reg`"] +pub type TXSTATUS = crate::Reg; +#[doc = "Status Register"] +pub mod txstatus; +#[doc = "FIFO_CLR register accessor: an alias for `Reg`"] +pub type FIFO_CLR = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "TXBREAK register accessor: an alias for `Reg`"] +pub type TXBREAK = crate::Reg; +#[doc = "Break Transmit Register"] +pub mod txbreak; +#[doc = "ADDR9 register accessor: an alias for `Reg`"] +pub type ADDR9 = crate::Reg; +#[doc = "Address9 Register"] +pub mod addr9; +#[doc = "ADDR9MASK register accessor: an alias for `Reg`"] +pub type ADDR9MASK = crate::Reg; +#[doc = "Address9 Mask Register"] +pub mod addr9mask; +#[doc = "IRQ_ENB register accessor: an alias for `Reg`"] +pub type IRQ_ENB = crate::Reg; +#[doc = "IRQ Enable Register"] +pub mod irq_enb; +#[doc = "IRQ_RAW register accessor: an alias for `Reg`"] +pub type IRQ_RAW = crate::Reg; +#[doc = "IRQ Raw Status Register"] +pub mod irq_raw; +#[doc = "IRQ_END register accessor: an alias for `Reg`"] +pub type IRQ_END = crate::Reg; +#[doc = "IRQ Enabled Status Register"] +pub mod irq_end; +#[doc = "IRQ_CLR register accessor: an alias for `Reg`"] +pub type IRQ_CLR = crate::Reg; +#[doc = "IRQ Clear Status Register"] +pub mod irq_clr; +#[doc = "RXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type RXFIFOIRQTRG = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG register accessor: an alias for `Reg`"] +pub type TXFIFOIRQTRG = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "RXFIFORTSTRG register accessor: an alias for `Reg`"] +pub type RXFIFORTSTRG = crate::Reg; +#[doc = "Rx FIFO RTS Trigger Level"] +pub mod rxfifortstrg; +#[doc = "STATE register accessor: an alias for `Reg`"] +pub type STATE = crate::Reg; +#[doc = "Internal STATE of UART Controller"] +pub mod state; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/uart0/addr9.rs b/src/uart0/addr9.rs new file mode 100644 index 0000000..24f7910 --- /dev/null +++ b/src/uart0/addr9.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ADDR9` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR9` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address9 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr9](index.html) module"] +pub struct ADDR9_SPEC; +impl crate::RegisterSpec for ADDR9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr9::R](R) reader structure"] +impl crate::Readable for ADDR9_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr9::W](W) writer structure"] +impl crate::Writable for ADDR9_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR9 to value 0"] +impl crate::Resettable for ADDR9_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/addr9mask.rs b/src/uart0/addr9mask.rs new file mode 100644 index 0000000..b62ef8e --- /dev/null +++ b/src/uart0/addr9mask.rs @@ -0,0 +1,64 @@ +#[doc = "Register `ADDR9MASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR9MASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address9 Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr9mask](index.html) module"] +pub struct ADDR9MASK_SPEC; +impl crate::RegisterSpec for ADDR9MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr9mask::R](R) reader structure"] +impl crate::Readable for ADDR9MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr9mask::W](W) writer structure"] +impl crate::Writable for ADDR9MASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR9MASK to value 0"] +impl crate::Resettable for ADDR9MASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/clkscale.rs b/src/uart0/clkscale.rs new file mode 100644 index 0000000..40fa684 --- /dev/null +++ b/src/uart0/clkscale.rs @@ -0,0 +1,167 @@ +#[doc = "Register `CLKSCALE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLKSCALE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FRAC` reader - Fractional Divide (64ths)"] +pub struct FRAC_R(crate::FieldReader); +impl FRAC_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + FRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRAC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRAC` writer - Fractional Divide (64ths)"] +pub struct FRAC_W<'a> { + w: &'a mut W, +} +impl<'a> FRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `INT` reader - Integer Divide"] +pub struct INT_R(crate::FieldReader); +impl INT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + INT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INT` writer - Integer Divide"] +pub struct INT_W<'a> { + w: &'a mut W, +} +impl<'a> INT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0003_ffff << 6)) | ((value as u32 & 0x0003_ffff) << 6); + self.w + } +} +#[doc = "Field `RESET` writer - Reset Baud Counter"] +pub struct RESET_W<'a> { + w: &'a mut W, +} +impl<'a> RESET_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Fractional Divide (64ths)"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Integer Divide"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 6) & 0x0003_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:5 - Fractional Divide (64ths)"] + #[inline(always)] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W { w: self } + } + #[doc = "Bits 6:23 - Integer Divide"] + #[inline(always)] + pub fn int(&mut self) -> INT_W { + INT_W { w: self } + } + #[doc = "Bit 31 - Reset Baud Counter"] + #[inline(always)] + pub fn reset(&mut self) -> RESET_W { + RESET_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Scale Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkscale](index.html) module"] +pub struct CLKSCALE_SPEC; +impl crate::RegisterSpec for CLKSCALE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clkscale::R](R) reader structure"] +impl crate::Readable for CLKSCALE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clkscale::W](W) writer structure"] +impl crate::Writable for CLKSCALE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CLKSCALE to value 0"] +impl crate::Resettable for CLKSCALE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/ctrl.rs b/src/uart0/ctrl.rs new file mode 100644 index 0000000..f5663f9 --- /dev/null +++ b/src/uart0/ctrl.rs @@ -0,0 +1,573 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAREN` reader - Parity Enable"] +pub struct PAREN_R(crate::FieldReader); +impl PAREN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAREN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAREN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAREN` writer - Parity Enable"] +pub struct PAREN_W<'a> { + w: &'a mut W, +} +impl<'a> PAREN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PAREVEN` reader - Parity Even/Odd(1/0)"] +pub struct PAREVEN_R(crate::FieldReader); +impl PAREVEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PAREVEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAREVEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAREVEN` writer - Parity Even/Odd(1/0)"] +pub struct PAREVEN_W<'a> { + w: &'a mut W, +} +impl<'a> PAREVEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `PARSTK` reader - Parity Sticky"] +pub struct PARSTK_R(crate::FieldReader); +impl PARSTK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + PARSTK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PARSTK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PARSTK` writer - Parity Sticky"] +pub struct PARSTK_W<'a> { + w: &'a mut W, +} +impl<'a> PARSTK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `STOPBITS` reader - Stop Bits 1/2(0/1)"] +pub struct STOPBITS_R(crate::FieldReader); +impl STOPBITS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + STOPBITS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for STOPBITS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STOPBITS` writer - Stop Bits 1/2(0/1)"] +pub struct STOPBITS_W<'a> { + w: &'a mut W, +} +impl<'a> STOPBITS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `WORDSIZE` reader - Word Size in Bits 5/6/7/8(00/01/10/11)"] +pub struct WORDSIZE_R(crate::FieldReader); +impl WORDSIZE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + WORDSIZE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WORDSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WORDSIZE` writer - Word Size in Bits 5/6/7/8(00/01/10/11)"] +pub struct WORDSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> WORDSIZE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOOPBACK` reader - Loopback Enable"] +pub struct LOOPBACK_R(crate::FieldReader); +impl LOOPBACK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOOPBACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOOPBACK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOOPBACK` writer - Loopback Enable"] +pub struct LOOPBACK_W<'a> { + w: &'a mut W, +} +impl<'a> LOOPBACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `LOOPBACKBLK` reader - Loopback Block"] +pub struct LOOPBACKBLK_R(crate::FieldReader); +impl LOOPBACKBLK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + LOOPBACKBLK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOOPBACKBLK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOOPBACKBLK` writer - Loopback Block"] +pub struct LOOPBACKBLK_W<'a> { + w: &'a mut W, +} +impl<'a> LOOPBACKBLK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `AUTOCTS` reader - Enable Auto CTS mode"] +pub struct AUTOCTS_R(crate::FieldReader); +impl AUTOCTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTOCTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTOCTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTOCTS` writer - Enable Auto CTS mode"] +pub struct AUTOCTS_W<'a> { + w: &'a mut W, +} +impl<'a> AUTOCTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DEFRTS` reader - Default RTSn value"] +pub struct DEFRTS_R(crate::FieldReader); +impl DEFRTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + DEFRTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DEFRTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DEFRTS` writer - Default RTSn value"] +pub struct DEFRTS_W<'a> { + w: &'a mut W, +} +impl<'a> DEFRTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `AUTORTS` reader - Enable Auto RTS mode"] +pub struct AUTORTS_R(crate::FieldReader); +impl AUTORTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + AUTORTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AUTORTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AUTORTS` writer - Enable Auto RTS mode"] +pub struct AUTORTS_W<'a> { + w: &'a mut W, +} +impl<'a> AUTORTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `BAUD8` reader - Enable BAUD8 mode"] +pub struct BAUD8_R(crate::FieldReader); +impl BAUD8_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + BAUD8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD8_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD8` writer - Enable BAUD8 mode"] +pub struct BAUD8_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Parity Enable"] + #[inline(always)] + pub fn paren(&self) -> PAREN_R { + PAREN_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Parity Even/Odd(1/0)"] + #[inline(always)] + pub fn pareven(&self) -> PAREVEN_R { + PAREVEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Parity Sticky"] + #[inline(always)] + pub fn parstk(&self) -> PARSTK_R { + PARSTK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Stop Bits 1/2(0/1)"] + #[inline(always)] + pub fn stopbits(&self) -> STOPBITS_R { + STOPBITS_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"] + #[inline(always)] + pub fn wordsize(&self) -> WORDSIZE_R { + WORDSIZE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - Loopback Enable"] + #[inline(always)] + pub fn loopback(&self) -> LOOPBACK_R { + LOOPBACK_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Loopback Block"] + #[inline(always)] + pub fn loopbackblk(&self) -> LOOPBACKBLK_R { + LOOPBACKBLK_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Enable Auto CTS mode"] + #[inline(always)] + pub fn autocts(&self) -> AUTOCTS_R { + AUTOCTS_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Default RTSn value"] + #[inline(always)] + pub fn defrts(&self) -> DEFRTS_R { + DEFRTS_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Enable Auto RTS mode"] + #[inline(always)] + pub fn autorts(&self) -> AUTORTS_R { + AUTORTS_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Enable BAUD8 mode"] + #[inline(always)] + pub fn baud8(&self) -> BAUD8_R { + BAUD8_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Enable"] + #[inline(always)] + pub fn paren(&mut self) -> PAREN_W { + PAREN_W { w: self } + } + #[doc = "Bit 1 - Parity Even/Odd(1/0)"] + #[inline(always)] + pub fn pareven(&mut self) -> PAREVEN_W { + PAREVEN_W { w: self } + } + #[doc = "Bit 2 - Parity Sticky"] + #[inline(always)] + pub fn parstk(&mut self) -> PARSTK_W { + PARSTK_W { w: self } + } + #[doc = "Bit 3 - Stop Bits 1/2(0/1)"] + #[inline(always)] + pub fn stopbits(&mut self) -> STOPBITS_W { + STOPBITS_W { w: self } + } + #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"] + #[inline(always)] + pub fn wordsize(&mut self) -> WORDSIZE_W { + WORDSIZE_W { w: self } + } + #[doc = "Bit 6 - Loopback Enable"] + #[inline(always)] + pub fn loopback(&mut self) -> LOOPBACK_W { + LOOPBACK_W { w: self } + } + #[doc = "Bit 7 - Loopback Block"] + #[inline(always)] + pub fn loopbackblk(&mut self) -> LOOPBACKBLK_W { + LOOPBACKBLK_W { w: self } + } + #[doc = "Bit 8 - Enable Auto CTS mode"] + #[inline(always)] + pub fn autocts(&mut self) -> AUTOCTS_W { + AUTOCTS_W { w: self } + } + #[doc = "Bit 9 - Default RTSn value"] + #[inline(always)] + pub fn defrts(&mut self) -> DEFRTS_W { + DEFRTS_W { w: self } + } + #[doc = "Bit 10 - Enable Auto RTS mode"] + #[inline(always)] + pub fn autorts(&mut self) -> AUTORTS_W { + AUTORTS_W { w: self } + } + #[doc = "Bit 11 - Enable BAUD8 mode"] + #[inline(always)] + pub fn baud8(&mut self) -> BAUD8_W { + BAUD8_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/data.rs b/src/uart0/data.rs new file mode 100644 index 0000000..61264f6 --- /dev/null +++ b/src/uart0/data.rs @@ -0,0 +1,64 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data In/Out Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/enable.rs b/src/uart0/enable.rs new file mode 100644 index 0000000..5584706 --- /dev/null +++ b/src/uart0/enable.rs @@ -0,0 +1,160 @@ +#[doc = "Register `ENABLE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ENABLE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXENABLE` reader - Rx Enable"] +pub struct RXENABLE_R(crate::FieldReader); +impl RXENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXENABLE` writer - Rx Enable"] +pub struct RXENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> RXENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TXENABLE` reader - Tx Enable"] +pub struct TXENABLE_R(crate::FieldReader); +impl TXENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXENABLE` writer - Tx Enable"] +pub struct TXENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> TXENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - Rx Enable"] + #[inline(always)] + pub fn rxenable(&self) -> RXENABLE_R { + RXENABLE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Tx Enable"] + #[inline(always)] + pub fn txenable(&self) -> TXENABLE_R { + TXENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx Enable"] + #[inline(always)] + pub fn rxenable(&mut self) -> RXENABLE_W { + RXENABLE_W { w: self } + } + #[doc = "Bit 1 - Tx Enable"] + #[inline(always)] + pub fn txenable(&mut self) -> TXENABLE_W { + TXENABLE_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [enable::R](R) reader structure"] +impl crate::Readable for ENABLE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/fifo_clr.rs b/src/uart0/fifo_clr.rs new file mode 100644 index 0000000..3d95fdd --- /dev/null +++ b/src/uart0/fifo_clr.rs @@ -0,0 +1,99 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub struct RXFIFO_W<'a> { + w: &'a mut W, +} +impl<'a> RXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub struct TXFIFO_W<'a> { + w: &'a mut W, +} +impl<'a> TXFIFO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RXFIFO_W { + RXFIFO_W { w: self } + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TXFIFO_W { + TXFIFO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear FIFO Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_clr](index.html) module"] +pub struct FIFO_CLR_SPEC; +impl crate::RegisterSpec for FIFO_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [fifo_clr::W](W) writer structure"] +impl crate::Writable for FIFO_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FIFO_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/irq_clr.rs b/src/uart0/irq_clr.rs new file mode 100644 index 0000000..451b609 --- /dev/null +++ b/src/uart0/irq_clr.rs @@ -0,0 +1,234 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IRQ_RX` writer - RX Interrupt"] +pub struct IRQ_RX_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_RX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IRQ_RX_STATUS` writer - RX Status Interrupt"] +pub struct IRQ_RX_STATUS_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_RX_STATUS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `IRQ_RX_TO` writer - RX Timeout Interrupt"] +pub struct IRQ_RX_TO_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_RX_TO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `IRQ_TX` writer - TX Interrupt"] +pub struct IRQ_TX_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_TX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `IRQ_TX_STATUS` writer - TX Status Interrupt"] +pub struct IRQ_TX_STATUS_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_TX_STATUS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `IRQ_TX_EMPTY` writer - TX Empty Interrupt"] +pub struct IRQ_TX_EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_TX_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `IRQ_TX_CTS` writer - TX CTS Change Interrupt"] +pub struct IRQ_TX_CTS_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_TX_CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl W { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&mut self) -> IRQ_RX_W { + IRQ_RX_W { w: self } + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&mut self) -> IRQ_RX_STATUS_W { + IRQ_RX_STATUS_W { w: self } + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&mut self) -> IRQ_RX_TO_W { + IRQ_RX_TO_W { w: self } + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&mut self) -> IRQ_TX_W { + IRQ_TX_W { w: self } + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&mut self) -> IRQ_TX_STATUS_W { + IRQ_TX_STATUS_W { w: self } + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&mut self) -> IRQ_TX_EMPTY_W { + IRQ_TX_EMPTY_W { w: self } + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&mut self) -> IRQ_TX_CTS_W { + IRQ_TX_CTS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "IRQ Clear Status Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"] +pub struct IRQ_CLR_SPEC; +impl crate::RegisterSpec for IRQ_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"] +impl crate::Writable for IRQ_CLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IRQ_CLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/irq_enb.rs b/src/uart0/irq_enb.rs new file mode 100644 index 0000000..93f50e1 --- /dev/null +++ b/src/uart0/irq_enb.rs @@ -0,0 +1,395 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `IRQ_ENB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IRQ_RX` reader - RX Interrupt"] +pub struct IRQ_RX_R(crate::FieldReader); +impl IRQ_RX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_RX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_RX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_RX` writer - RX Interrupt"] +pub struct IRQ_RX_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_RX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `IRQ_RX_STATUS` reader - RX Status Interrupt"] +pub struct IRQ_RX_STATUS_R(crate::FieldReader); +impl IRQ_RX_STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_RX_STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_RX_STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_RX_STATUS` writer - RX Status Interrupt"] +pub struct IRQ_RX_STATUS_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_RX_STATUS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `IRQ_RX_TO` reader - RX Timeout Interrupt"] +pub struct IRQ_RX_TO_R(crate::FieldReader); +impl IRQ_RX_TO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_RX_TO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_RX_TO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_RX_TO` writer - RX Timeout Interrupt"] +pub struct IRQ_RX_TO_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_RX_TO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `IRQ_TX` reader - TX Interrupt"] +pub struct IRQ_TX_R(crate::FieldReader); +impl IRQ_TX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX` writer - TX Interrupt"] +pub struct IRQ_TX_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_TX_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `IRQ_TX_STATUS` reader - TX Status Interrupt"] +pub struct IRQ_TX_STATUS_R(crate::FieldReader); +impl IRQ_TX_STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX_STATUS` writer - TX Status Interrupt"] +pub struct IRQ_TX_STATUS_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_TX_STATUS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `IRQ_TX_EMPTY` reader - TX Empty Interrupt"] +pub struct IRQ_TX_EMPTY_R(crate::FieldReader); +impl IRQ_TX_EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX_EMPTY` writer - TX Empty Interrupt"] +pub struct IRQ_TX_EMPTY_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_TX_EMPTY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `IRQ_TX_CTS` reader - TX CTS Change Interrupt"] +pub struct IRQ_TX_CTS_R(crate::FieldReader); +impl IRQ_TX_CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX_CTS` writer - TX CTS Change Interrupt"] +pub struct IRQ_TX_CTS_W<'a> { + w: &'a mut W, +} +impl<'a> IRQ_TX_CTS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&self) -> IRQ_RX_R { + IRQ_RX_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&self) -> IRQ_RX_STATUS_R { + IRQ_RX_STATUS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&self) -> IRQ_RX_TO_R { + IRQ_RX_TO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&self) -> IRQ_TX_R { + IRQ_TX_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&self) -> IRQ_TX_STATUS_R { + IRQ_TX_STATUS_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&self) -> IRQ_TX_EMPTY_R { + IRQ_TX_EMPTY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&self) -> IRQ_TX_CTS_R { + IRQ_TX_CTS_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&mut self) -> IRQ_RX_W { + IRQ_RX_W { w: self } + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&mut self) -> IRQ_RX_STATUS_W { + IRQ_RX_STATUS_W { w: self } + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&mut self) -> IRQ_RX_TO_W { + IRQ_RX_TO_W { w: self } + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&mut self) -> IRQ_TX_W { + IRQ_TX_W { w: self } + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&mut self) -> IRQ_TX_STATUS_W { + IRQ_TX_STATUS_W { w: self } + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&mut self) -> IRQ_TX_EMPTY_W { + IRQ_TX_EMPTY_W { w: self } + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&mut self) -> IRQ_TX_CTS_W { + IRQ_TX_CTS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "IRQ Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"] +pub struct IRQ_ENB_SPEC; +impl crate::RegisterSpec for IRQ_ENB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_enb::R](R) reader structure"] +impl crate::Readable for IRQ_ENB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"] +impl crate::Writable for IRQ_ENB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IRQ_ENB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/irq_end.rs b/src/uart0/irq_end.rs new file mode 100644 index 0000000..b2eb6c8 --- /dev/null +++ b/src/uart0/irq_end.rs @@ -0,0 +1,173 @@ +#[doc = "Register `IRQ_END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IRQ_RX` reader - RX Interrupt"] +pub struct IRQ_RX_R(crate::FieldReader); +impl IRQ_RX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_RX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_RX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_RX_STATUS` reader - RX Status Interrupt"] +pub struct IRQ_RX_STATUS_R(crate::FieldReader); +impl IRQ_RX_STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_RX_STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_RX_STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_RX_TO` reader - RX Timeout Interrupt"] +pub struct IRQ_RX_TO_R(crate::FieldReader); +impl IRQ_RX_TO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_RX_TO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_RX_TO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX` reader - TX Interrupt"] +pub struct IRQ_TX_R(crate::FieldReader); +impl IRQ_TX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX_STATUS` reader - TX Status Interrupt"] +pub struct IRQ_TX_STATUS_R(crate::FieldReader); +impl IRQ_TX_STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX_EMPTY` reader - TX Empty Interrupt"] +pub struct IRQ_TX_EMPTY_R(crate::FieldReader); +impl IRQ_TX_EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX_CTS` reader - TX CTS Change Interrupt"] +pub struct IRQ_TX_CTS_R(crate::FieldReader); +impl IRQ_TX_CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&self) -> IRQ_RX_R { + IRQ_RX_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&self) -> IRQ_RX_STATUS_R { + IRQ_RX_STATUS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&self) -> IRQ_RX_TO_R { + IRQ_RX_TO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&self) -> IRQ_TX_R { + IRQ_TX_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&self) -> IRQ_TX_STATUS_R { + IRQ_TX_STATUS_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&self) -> IRQ_TX_EMPTY_R { + IRQ_TX_EMPTY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&self) -> IRQ_TX_CTS_R { + IRQ_TX_CTS_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "IRQ Enabled Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"] +pub struct IRQ_END_SPEC; +impl crate::RegisterSpec for IRQ_END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_end::R](R) reader structure"] +impl crate::Readable for IRQ_END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IRQ_END_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/irq_raw.rs b/src/uart0/irq_raw.rs new file mode 100644 index 0000000..ba40050 --- /dev/null +++ b/src/uart0/irq_raw.rs @@ -0,0 +1,173 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `IRQ_RX` reader - RX Interrupt"] +pub struct IRQ_RX_R(crate::FieldReader); +impl IRQ_RX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_RX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_RX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_RX_STATUS` reader - RX Status Interrupt"] +pub struct IRQ_RX_STATUS_R(crate::FieldReader); +impl IRQ_RX_STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_RX_STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_RX_STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_RX_TO` reader - RX Timeout Interrupt"] +pub struct IRQ_RX_TO_R(crate::FieldReader); +impl IRQ_RX_TO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_RX_TO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_RX_TO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX` reader - TX Interrupt"] +pub struct IRQ_TX_R(crate::FieldReader); +impl IRQ_TX_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX_STATUS` reader - TX Status Interrupt"] +pub struct IRQ_TX_STATUS_R(crate::FieldReader); +impl IRQ_TX_STATUS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_STATUS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_STATUS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX_EMPTY` reader - TX Empty Interrupt"] +pub struct IRQ_TX_EMPTY_R(crate::FieldReader); +impl IRQ_TX_EMPTY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_EMPTY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_EMPTY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IRQ_TX_CTS` reader - TX CTS Change Interrupt"] +pub struct IRQ_TX_CTS_R(crate::FieldReader); +impl IRQ_TX_CTS_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + IRQ_TX_CTS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IRQ_TX_CTS_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&self) -> IRQ_RX_R { + IRQ_RX_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&self) -> IRQ_RX_STATUS_R { + IRQ_RX_STATUS_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&self) -> IRQ_RX_TO_R { + IRQ_RX_TO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&self) -> IRQ_TX_R { + IRQ_TX_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&self) -> IRQ_TX_STATUS_R { + IRQ_TX_STATUS_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&self) -> IRQ_TX_EMPTY_R { + IRQ_TX_EMPTY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&self) -> IRQ_TX_CTS_R { + IRQ_TX_CTS_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +#[doc = "IRQ Raw Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"] +pub struct IRQ_RAW_SPEC; +impl crate::RegisterSpec for IRQ_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [irq_raw::R](R) reader structure"] +impl crate::Readable for IRQ_RAW_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IRQ_RAW to value 0"] +impl crate::Resettable for IRQ_RAW_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/perid.rs b/src/uart0/perid.rs new file mode 100644 index 0000000..ad4532e --- /dev/null +++ b/src/uart0/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0212_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0212_07e9 + } +} diff --git a/src/uart0/rxfifoirqtrg.rs b/src/uart0/rxfifoirqtrg.rs new file mode 100644 index 0000000..fb4d239 --- /dev/null +++ b/src/uart0/rxfifoirqtrg.rs @@ -0,0 +1,64 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifoirqtrg](index.html) module"] +pub struct RXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for RXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxfifoirqtrg::R](R) reader structure"] +impl crate::Readable for RXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxfifoirqtrg::W](W) writer structure"] +impl crate::Writable for RXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/rxfifortstrg.rs b/src/uart0/rxfifortstrg.rs new file mode 100644 index 0000000..860e0fd --- /dev/null +++ b/src/uart0/rxfifortstrg.rs @@ -0,0 +1,64 @@ +#[doc = "Register `RXFIFORTSTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXFIFORTSTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Rx FIFO RTS Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifortstrg](index.html) module"] +pub struct RXFIFORTSTRG_SPEC; +impl crate::RegisterSpec for RXFIFORTSTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxfifortstrg::R](R) reader structure"] +impl crate::Readable for RXFIFORTSTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxfifortstrg::W](W) writer structure"] +impl crate::Writable for RXFIFORTSTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RXFIFORTSTRG to value 0"] +impl crate::Resettable for RXFIFORTSTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/rxstatus.rs b/src/uart0/rxstatus.rs new file mode 100644 index 0000000..779d361 --- /dev/null +++ b/src/uart0/rxstatus.rs @@ -0,0 +1,253 @@ +#[doc = "Register `RXSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RDAVL` reader - Read Data Available"] +pub struct RDAVL_R(crate::FieldReader); +impl RDAVL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RDAVL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RDAVL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RDNFULL` reader - Read Fifo NOT Full"] +pub struct RDNFULL_R(crate::FieldReader); +impl RDNFULL_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RDNFULL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RDNFULL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBUSY` reader - RX Busy Receiving"] +pub struct RXBUSY_R(crate::FieldReader); +impl RXBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXTO` reader - RX Receive Timeout"] +pub struct RXTO_R(crate::FieldReader); +impl RXTO_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXTO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXOVR` reader - Read Fifo Overflow"] +pub struct RXOVR_R(crate::FieldReader); +impl RXOVR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXOVR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXOVR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXFRM` reader - RX Framing Error"] +pub struct RXFRM_R(crate::FieldReader); +impl RXFRM_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXFRM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXFRM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXPAR` reader - RX Parity Error"] +pub struct RXPAR_R(crate::FieldReader); +impl RXPAR_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXPAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXPAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBRK` reader - RX Break Error"] +pub struct RXBRK_R(crate::FieldReader); +impl RXBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXBUSYBRK` reader - RX Busy Receiving Break"] +pub struct RXBUSYBRK_R(crate::FieldReader); +impl RXBUSYBRK_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXBUSYBRK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXBUSYBRK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXADDR9` reader - Address Match for 9 bit mode"] +pub struct RXADDR9_R(crate::FieldReader); +impl RXADDR9_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXADDR9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXADDR9_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXRTSN` reader - RX RTSn Output Value"] +pub struct RXRTSN_R(crate::FieldReader); +impl RXRTSN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RXRTSN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXRTSN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Read Data Available"] + #[inline(always)] + pub fn rdavl(&self) -> RDAVL_R { + RDAVL_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Read Fifo NOT Full"] + #[inline(always)] + pub fn rdnfull(&self) -> RDNFULL_R { + RDNFULL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - RX Busy Receiving"] + #[inline(always)] + pub fn rxbusy(&self) -> RXBUSY_R { + RXBUSY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RX Receive Timeout"] + #[inline(always)] + pub fn rxto(&self) -> RXTO_R { + RXTO_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Read Fifo Overflow"] + #[inline(always)] + pub fn rxovr(&self) -> RXOVR_R { + RXOVR_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - RX Framing Error"] + #[inline(always)] + pub fn rxfrm(&self) -> RXFRM_R { + RXFRM_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - RX Parity Error"] + #[inline(always)] + pub fn rxpar(&self) -> RXPAR_R { + RXPAR_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - RX Break Error"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - RX Busy Receiving Break"] + #[inline(always)] + pub fn rxbusybrk(&self) -> RXBUSYBRK_R { + RXBUSYBRK_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Address Match for 9 bit mode"] + #[inline(always)] + pub fn rxaddr9(&self) -> RXADDR9_R { + RXADDR9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 15 - RX RTSn Output Value"] + #[inline(always)] + pub fn rxrtsn(&self) -> RXRTSN_R { + RXRTSN_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxstatus](index.html) module"] +pub struct RXSTATUS_SPEC; +impl crate::RegisterSpec for RXSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rxstatus::R](R) reader structure"] +impl crate::Readable for RXSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXSTATUS to value 0"] +impl crate::Resettable for RXSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/state.rs b/src/uart0/state.rs new file mode 100644 index 0000000..fd3845e --- /dev/null +++ b/src/uart0/state.rs @@ -0,0 +1,31 @@ +#[doc = "Register `STATE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Internal STATE of UART Controller\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [state](index.html) module"] +pub struct STATE_SPEC; +impl crate::RegisterSpec for STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [state::R](R) reader structure"] +impl crate::Readable for STATE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for STATE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/txbreak.rs b/src/uart0/txbreak.rs new file mode 100644 index 0000000..0b28c0e --- /dev/null +++ b/src/uart0/txbreak.rs @@ -0,0 +1,45 @@ +#[doc = "Register `TXBREAK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Break Transmit Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbreak](index.html) module"] +pub struct TXBREAK_SPEC; +impl crate::RegisterSpec for TXBREAK_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [txbreak::W](W) writer structure"] +impl crate::Writable for TXBREAK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXBREAK to value 0"] +impl crate::Resettable for TXBREAK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/txfifoirqtrg.rs b/src/uart0/txfifoirqtrg.rs new file mode 100644 index 0000000..a88c823 --- /dev/null +++ b/src/uart0/txfifoirqtrg.rs @@ -0,0 +1,64 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfifoirqtrg](index.html) module"] +pub struct TXFIFOIRQTRG_SPEC; +impl crate::RegisterSpec for TXFIFOIRQTRG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txfifoirqtrg::R](R) reader structure"] +impl crate::Readable for TXFIFOIRQTRG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [txfifoirqtrg::W](W) writer structure"] +impl crate::Writable for TXFIFOIRQTRG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TXFIFOIRQTRG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/uart0/txstatus.rs b/src/uart0/txstatus.rs new file mode 100644 index 0000000..e96e737 --- /dev/null +++ b/src/uart0/txstatus.rs @@ -0,0 +1,133 @@ +#[doc = "Register `TXSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `WRRDY` reader - Write Fifo NOT Full"] +pub struct WRRDY_R(crate::FieldReader); +impl WRRDY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRRDY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBUSY` reader - Write Fifo Full"] +pub struct WRBUSY_R(crate::FieldReader); +impl WRBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXBUSY` reader - TX Busy Transmitting"] +pub struct TXBUSY_R(crate::FieldReader); +impl TXBUSY_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXBUSY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRLOST` reader - Write Data Lost (Fifo Overflow)"] +pub struct WRLOST_R(crate::FieldReader); +impl WRLOST_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WRLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRLOST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXCTSN` reader - TX CTSn Input Value"] +pub struct TXCTSN_R(crate::FieldReader); +impl TXCTSN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TXCTSN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXCTSN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Write Fifo NOT Full"] + #[inline(always)] + pub fn wrrdy(&self) -> WRRDY_R { + WRRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Write Fifo Full"] + #[inline(always)] + pub fn wrbusy(&self) -> WRBUSY_R { + WRBUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TX Busy Transmitting"] + #[inline(always)] + pub fn txbusy(&self) -> TXBUSY_R { + TXBUSY_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Write Data Lost (Fifo Overflow)"] + #[inline(always)] + pub fn wrlost(&self) -> WRLOST_R { + WRLOST_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 15 - TX CTSn Input Value"] + #[inline(always)] + pub fn txctsn(&self) -> TXCTSN_R { + TXCTSN_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txstatus](index.html) module"] +pub struct TXSTATUS_SPEC; +impl crate::RegisterSpec for TXSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [txstatus::R](R) reader structure"] +impl crate::Readable for TXSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TXSTATUS to value 0"] +impl crate::Resettable for TXSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility.rs b/src/utility.rs new file mode 100644 index 0000000..4ca41c4 --- /dev/null +++ b/src/utility.rs @@ -0,0 +1,96 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Data Register"] + pub synd_data: crate::Reg, + #[doc = "0x04 - Syndrome Data Register"] + pub synd_synd: crate::Reg, + #[doc = "0x08 - EDAC Encode"] + pub synd_enc_32_44: crate::Reg, + #[doc = "0x0c - EDAC Decode Data"] + pub synd_check_32_44_data: crate::Reg, + #[doc = "0x10 - EDAC Decode Syndrome"] + pub synd_check_32_44_synd: crate::Reg, + #[doc = "0x14 - ROM EDAC Trap Address"] + pub rom_trap_address: crate::Reg, + #[doc = "0x18 - ROM EDAC Trap Syndrome"] + pub rom_trap_synd: crate::Reg, + #[doc = "0x1c - RAM0 EDAC Trap Address"] + pub ram_trap_addr0: crate::Reg, + #[doc = "0x20 - RAM0 EDAC Trap Syndrome"] + pub ram_trap_synd0: crate::Reg, + #[doc = "0x24 - RAM1 EDAC Trap Address"] + pub ram_trap_addr1: crate::Reg, + #[doc = "0x28 - RAM1 EDAC Trap Syndrome"] + pub ram_trap_synd1: crate::Reg, + _reserved11: [u8; 0xf4], + #[doc = "0x120 - EDAC Encode"] + pub synd_enc_32_52: crate::Reg, + #[doc = "0x124 - EDAC Decode Data"] + pub synd_check_32_52_data: crate::Reg, + #[doc = "0x128 - EDAC Decode Syndrome"] + pub synd_check_32_52_synd: crate::Reg, + _reserved14: [u8; 0x0ed0], + #[doc = "0xffc - Peripheral ID Register"] + pub perid: crate::Reg, +} +#[doc = "SYND_DATA register accessor: an alias for `Reg`"] +pub type SYND_DATA = crate::Reg; +#[doc = "Data Register"] +pub mod synd_data; +#[doc = "SYND_SYND register accessor: an alias for `Reg`"] +pub type SYND_SYND = crate::Reg; +#[doc = "Syndrome Data Register"] +pub mod synd_synd; +#[doc = "SYND_ENC_32_44 register accessor: an alias for `Reg`"] +pub type SYND_ENC_32_44 = crate::Reg; +#[doc = "EDAC Encode"] +pub mod synd_enc_32_44; +#[doc = "SYND_CHECK_32_44_DATA register accessor: an alias for `Reg`"] +pub type SYND_CHECK_32_44_DATA = crate::Reg; +#[doc = "EDAC Decode Data"] +pub mod synd_check_32_44_data; +#[doc = "SYND_CHECK_32_44_SYND register accessor: an alias for `Reg`"] +pub type SYND_CHECK_32_44_SYND = crate::Reg; +#[doc = "EDAC Decode Syndrome"] +pub mod synd_check_32_44_synd; +#[doc = "ROM_TRAP_ADDRESS register accessor: an alias for `Reg`"] +pub type ROM_TRAP_ADDRESS = crate::Reg; +#[doc = "ROM EDAC Trap Address"] +pub mod rom_trap_address; +#[doc = "ROM_TRAP_SYND register accessor: an alias for `Reg`"] +pub type ROM_TRAP_SYND = crate::Reg; +#[doc = "ROM EDAC Trap Syndrome"] +pub mod rom_trap_synd; +#[doc = "RAM_TRAP_ADDR0 register accessor: an alias for `Reg`"] +pub type RAM_TRAP_ADDR0 = crate::Reg; +#[doc = "RAM0 EDAC Trap Address"] +pub mod ram_trap_addr0; +#[doc = "RAM_TRAP_SYND0 register accessor: an alias for `Reg`"] +pub type RAM_TRAP_SYND0 = crate::Reg; +#[doc = "RAM0 EDAC Trap Syndrome"] +pub mod ram_trap_synd0; +#[doc = "RAM_TRAP_ADDR1 register accessor: an alias for `Reg`"] +pub type RAM_TRAP_ADDR1 = crate::Reg; +#[doc = "RAM1 EDAC Trap Address"] +pub mod ram_trap_addr1; +#[doc = "RAM_TRAP_SYND1 register accessor: an alias for `Reg`"] +pub type RAM_TRAP_SYND1 = crate::Reg; +#[doc = "RAM1 EDAC Trap Syndrome"] +pub mod ram_trap_synd1; +#[doc = "SYND_ENC_32_52 register accessor: an alias for `Reg`"] +pub type SYND_ENC_32_52 = crate::Reg; +#[doc = "EDAC Encode"] +pub mod synd_enc_32_52; +#[doc = "SYND_CHECK_32_52_DATA register accessor: an alias for `Reg`"] +pub type SYND_CHECK_32_52_DATA = crate::Reg; +#[doc = "EDAC Decode Data"] +pub mod synd_check_32_52_data; +#[doc = "SYND_CHECK_32_52_SYND register accessor: an alias for `Reg`"] +pub type SYND_CHECK_32_52_SYND = crate::Reg; +#[doc = "EDAC Decode Syndrome"] +pub mod synd_check_32_52_synd; +#[doc = "PERID register accessor: an alias for `Reg`"] +pub type PERID = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/src/utility/perid.rs b/src/utility/perid.rs new file mode 100644 index 0000000..33a4e4b --- /dev/null +++ b/src/utility/perid.rs @@ -0,0 +1,31 @@ +#[doc = "Register `PERID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"] +pub struct PERID_SPEC; +impl crate::RegisterSpec for PERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perid::R](R) reader structure"] +impl crate::Readable for PERID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PERID to value 0x0284_07e9"] +impl crate::Resettable for PERID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0284_07e9 + } +} diff --git a/src/utility/ram_trap_addr0.rs b/src/utility/ram_trap_addr0.rs new file mode 100644 index 0000000..c5c3e45 --- /dev/null +++ b/src/utility/ram_trap_addr0.rs @@ -0,0 +1,150 @@ +#[doc = "Register `RAM_TRAP_ADDR0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM_TRAP_ADDR0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable Trap mode"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable Trap mode"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +#[doc = "Field `ADDR` reader - Address bits for trap match"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address bits for trap match"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 2)) | ((value as u32 & 0x1fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM0 EDAC Trap Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram_trap_addr0](index.html) module"] +pub struct RAM_TRAP_ADDR0_SPEC; +impl crate::RegisterSpec for RAM_TRAP_ADDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram_trap_addr0::R](R) reader structure"] +impl crate::Readable for RAM_TRAP_ADDR0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram_trap_addr0::W](W) writer structure"] +impl crate::Writable for RAM_TRAP_ADDR0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM_TRAP_ADDR0 to value 0"] +impl crate::Resettable for RAM_TRAP_ADDR0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/ram_trap_addr1.rs b/src/utility/ram_trap_addr1.rs new file mode 100644 index 0000000..32dcbd0 --- /dev/null +++ b/src/utility/ram_trap_addr1.rs @@ -0,0 +1,150 @@ +#[doc = "Register `RAM_TRAP_ADDR1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM_TRAP_ADDR1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable Trap mode"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable Trap mode"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +#[doc = "Field `ADDR` reader - Address bits for trap match"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address bits for trap match"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 2)) | ((value as u32 & 0x1fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM1 EDAC Trap Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram_trap_addr1](index.html) module"] +pub struct RAM_TRAP_ADDR1_SPEC; +impl crate::RegisterSpec for RAM_TRAP_ADDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram_trap_addr1::R](R) reader structure"] +impl crate::Readable for RAM_TRAP_ADDR1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram_trap_addr1::W](W) writer structure"] +impl crate::Writable for RAM_TRAP_ADDR1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM_TRAP_ADDR1 to value 0"] +impl crate::Resettable for RAM_TRAP_ADDR1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/ram_trap_synd0.rs b/src/utility/ram_trap_synd0.rs new file mode 100644 index 0000000..b4d9dfc --- /dev/null +++ b/src/utility/ram_trap_synd0.rs @@ -0,0 +1,140 @@ +#[doc = "Register `RAM_TRAP_SYND0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM_TRAP_SYND0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RAM_SYND_31_16` reader - 6-bit syndrome value for bits 31-16"] +pub struct RAM_SYND_31_16_R(crate::FieldReader); +impl RAM_SYND_31_16_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAM_SYND_31_16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM_SYND_31_16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM_SYND_31_16` writer - 6-bit syndrome value for bits 31-16"] +pub struct RAM_SYND_31_16_W<'a> { + w: &'a mut W, +} +impl<'a> RAM_SYND_31_16_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Field `RAM_SYND_7_0` reader - 6-bit syndrome value for bits 15-0"] +pub struct RAM_SYND_7_0_R(crate::FieldReader); +impl RAM_SYND_7_0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAM_SYND_7_0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM_SYND_7_0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM_SYND_7_0` writer - 6-bit syndrome value for bits 15-0"] +pub struct RAM_SYND_7_0_W<'a> { + w: &'a mut W, +} +impl<'a> RAM_SYND_7_0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&self) -> RAM_SYND_31_16_R { + RAM_SYND_31_16_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&self) -> RAM_SYND_7_0_R { + RAM_SYND_7_0_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&mut self) -> RAM_SYND_31_16_W { + RAM_SYND_31_16_W { w: self } + } + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&mut self) -> RAM_SYND_7_0_W { + RAM_SYND_7_0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM0 EDAC Trap Syndrome\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram_trap_synd0](index.html) module"] +pub struct RAM_TRAP_SYND0_SPEC; +impl crate::RegisterSpec for RAM_TRAP_SYND0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram_trap_synd0::R](R) reader structure"] +impl crate::Readable for RAM_TRAP_SYND0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram_trap_synd0::W](W) writer structure"] +impl crate::Writable for RAM_TRAP_SYND0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM_TRAP_SYND0 to value 0"] +impl crate::Resettable for RAM_TRAP_SYND0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/ram_trap_synd1.rs b/src/utility/ram_trap_synd1.rs new file mode 100644 index 0000000..a4935a6 --- /dev/null +++ b/src/utility/ram_trap_synd1.rs @@ -0,0 +1,140 @@ +#[doc = "Register `RAM_TRAP_SYND1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RAM_TRAP_SYND1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RAM_SYND_31_16` reader - 6-bit syndrome value for bits 31-16"] +pub struct RAM_SYND_31_16_R(crate::FieldReader); +impl RAM_SYND_31_16_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAM_SYND_31_16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM_SYND_31_16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM_SYND_31_16` writer - 6-bit syndrome value for bits 31-16"] +pub struct RAM_SYND_31_16_W<'a> { + w: &'a mut W, +} +impl<'a> RAM_SYND_31_16_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Field `RAM_SYND_7_0` reader - 6-bit syndrome value for bits 15-0"] +pub struct RAM_SYND_7_0_R(crate::FieldReader); +impl RAM_SYND_7_0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + RAM_SYND_7_0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RAM_SYND_7_0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RAM_SYND_7_0` writer - 6-bit syndrome value for bits 15-0"] +pub struct RAM_SYND_7_0_W<'a> { + w: &'a mut W, +} +impl<'a> RAM_SYND_7_0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&self) -> RAM_SYND_31_16_R { + RAM_SYND_31_16_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&self) -> RAM_SYND_7_0_R { + RAM_SYND_7_0_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&mut self) -> RAM_SYND_31_16_W { + RAM_SYND_31_16_W { w: self } + } + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&mut self) -> RAM_SYND_7_0_W { + RAM_SYND_7_0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RAM1 EDAC Trap Syndrome\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram_trap_synd1](index.html) module"] +pub struct RAM_TRAP_SYND1_SPEC; +impl crate::RegisterSpec for RAM_TRAP_SYND1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ram_trap_synd1::R](R) reader structure"] +impl crate::Readable for RAM_TRAP_SYND1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ram_trap_synd1::W](W) writer structure"] +impl crate::Writable for RAM_TRAP_SYND1_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets RAM_TRAP_SYND1 to value 0"] +impl crate::Resettable for RAM_TRAP_SYND1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/rom_trap_address.rs b/src/utility/rom_trap_address.rs new file mode 100644 index 0000000..f421ddc --- /dev/null +++ b/src/utility/rom_trap_address.rs @@ -0,0 +1,150 @@ +#[doc = "Register `ROM_TRAP_ADDRESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ROM_TRAP_ADDRESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable Trap mode"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable Trap mode"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +#[doc = "Field `ADDR` reader - Address bits for trap match"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address bits for trap match"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x1fff_ffff << 2)) | ((value as u32 & 0x1fff_ffff) << 2); + self.w + } +} +impl R { + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 31) & 0x01) != 0) + } + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 2) & 0x1fff_ffff) as u32) + } +} +impl W { + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "ROM EDAC Trap Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_trap_address](index.html) module"] +pub struct ROM_TRAP_ADDRESS_SPEC; +impl crate::RegisterSpec for ROM_TRAP_ADDRESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rom_trap_address::R](R) reader structure"] +impl crate::Readable for ROM_TRAP_ADDRESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rom_trap_address::W](W) writer structure"] +impl crate::Writable for ROM_TRAP_ADDRESS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ROM_TRAP_ADDRESS to value 0"] +impl crate::Resettable for ROM_TRAP_ADDRESS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/rom_trap_synd.rs b/src/utility/rom_trap_synd.rs new file mode 100644 index 0000000..5942cfa --- /dev/null +++ b/src/utility/rom_trap_synd.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ROM_TRAP_SYND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ROM_TRAP_SYND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `R0M_SYND_31_16` reader - 6-bit syndrome value for bits 31-16"] +pub struct R0M_SYND_31_16_R(crate::FieldReader); +impl R0M_SYND_31_16_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + R0M_SYND_31_16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for R0M_SYND_31_16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `R0M_SYND_31_16` writer - 6-bit syndrome value for bits 31-16"] +pub struct R0M_SYND_31_16_W<'a> { + w: &'a mut W, +} +impl<'a> R0M_SYND_31_16_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Field `ROM_SYND_7_0` reader - 6-bit syndrome value for bits 15-0"] +pub struct ROM_SYND_7_0_R(crate::FieldReader); +impl ROM_SYND_7_0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + ROM_SYND_7_0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ROM_SYND_7_0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ROM_SYND_7_0` writer - 6-bit syndrome value for bits 15-0"] +pub struct ROM_SYND_7_0_W<'a> { + w: &'a mut W, +} +impl<'a> ROM_SYND_7_0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn r0m_synd_31_16(&self) -> R0M_SYND_31_16_R { + R0M_SYND_31_16_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn rom_synd_7_0(&self) -> ROM_SYND_7_0_R { + ROM_SYND_7_0_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn r0m_synd_31_16(&mut self) -> R0M_SYND_31_16_W { + R0M_SYND_31_16_W { w: self } + } + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn rom_synd_7_0(&mut self) -> ROM_SYND_7_0_W { + ROM_SYND_7_0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "ROM EDAC Trap Syndrome\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rom_trap_synd](index.html) module"] +pub struct ROM_TRAP_SYND_SPEC; +impl crate::RegisterSpec for ROM_TRAP_SYND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [rom_trap_synd::R](R) reader structure"] +impl crate::Readable for ROM_TRAP_SYND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rom_trap_synd::W](W) writer structure"] +impl crate::Writable for ROM_TRAP_SYND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ROM_TRAP_SYND to value 0"] +impl crate::Resettable for ROM_TRAP_SYND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/synd_check_32_44_data.rs b/src/utility/synd_check_32_44_data.rs new file mode 100644 index 0000000..78ef7ef --- /dev/null +++ b/src/utility/synd_check_32_44_data.rs @@ -0,0 +1,31 @@ +#[doc = "Register `SYND_CHECK_32_44_DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "EDAC Decode Data\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synd_check_32_44_data](index.html) module"] +pub struct SYND_CHECK_32_44_DATA_SPEC; +impl crate::RegisterSpec for SYND_CHECK_32_44_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [synd_check_32_44_data::R](R) reader structure"] +impl crate::Readable for SYND_CHECK_32_44_DATA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYND_CHECK_32_44_DATA to value 0"] +impl crate::Resettable for SYND_CHECK_32_44_DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/synd_check_32_44_synd.rs b/src/utility/synd_check_32_44_synd.rs new file mode 100644 index 0000000..db8d32a --- /dev/null +++ b/src/utility/synd_check_32_44_synd.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYND_CHECK_32_44_SYND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `MBE` reader - Multiple bit error detect status"] +pub struct MBE_R(crate::FieldReader); +impl MBE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBE` reader - Single bit error detect status"] +pub struct SBE_R(crate::FieldReader); +impl SBE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYND_CHECK_32_44_SYND` reader - Correct syndrome value"] +pub struct SYND_CHECK_32_44_SYND_R(crate::FieldReader); +impl SYND_CHECK_32_44_SYND_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + SYND_CHECK_32_44_SYND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYND_CHECK_32_44_SYND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 14:15 - Multiple bit error detect status"] + #[inline(always)] + pub fn mbe(&self) -> MBE_R { + MBE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bits 12:13 - Single bit error detect status"] + #[inline(always)] + pub fn sbe(&self) -> SBE_R { + SBE_R::new(((self.bits >> 12) & 0x03) as u8) + } + #[doc = "Bits 0:11 - Correct syndrome value"] + #[inline(always)] + pub fn synd_check_32_44_synd(&self) -> SYND_CHECK_32_44_SYND_R { + SYND_CHECK_32_44_SYND_R::new((self.bits & 0x0fff) as u16) + } +} +#[doc = "EDAC Decode Syndrome\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synd_check_32_44_synd](index.html) module"] +pub struct SYND_CHECK_32_44_SYND_SPEC; +impl crate::RegisterSpec for SYND_CHECK_32_44_SYND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [synd_check_32_44_synd::R](R) reader structure"] +impl crate::Readable for SYND_CHECK_32_44_SYND_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYND_CHECK_32_44_SYND to value 0"] +impl crate::Resettable for SYND_CHECK_32_44_SYND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/synd_check_32_52_data.rs b/src/utility/synd_check_32_52_data.rs new file mode 100644 index 0000000..6801468 --- /dev/null +++ b/src/utility/synd_check_32_52_data.rs @@ -0,0 +1,31 @@ +#[doc = "Register `SYND_CHECK_32_52_DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "EDAC Decode Data\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synd_check_32_52_data](index.html) module"] +pub struct SYND_CHECK_32_52_DATA_SPEC; +impl crate::RegisterSpec for SYND_CHECK_32_52_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [synd_check_32_52_data::R](R) reader structure"] +impl crate::Readable for SYND_CHECK_32_52_DATA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYND_CHECK_32_52_DATA to value 0"] +impl crate::Resettable for SYND_CHECK_32_52_DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/synd_check_32_52_synd.rs b/src/utility/synd_check_32_52_synd.rs new file mode 100644 index 0000000..50623f3 --- /dev/null +++ b/src/utility/synd_check_32_52_synd.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYND_CHECK_32_52_SYND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `MBE` reader - Multiple bit error detect status"] +pub struct MBE_R(crate::FieldReader); +impl MBE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + MBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SBE` reader - Single bit error detect status"] +pub struct SBE_R(crate::FieldReader); +impl SBE_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SBE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SBE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYND_CHECK_32_52_SYND` reader - Corrected syndrome value"] +pub struct SYND_CHECK_32_52_SYND_R(crate::FieldReader); +impl SYND_CHECK_32_52_SYND_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SYND_CHECK_32_52_SYND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYND_CHECK_32_52_SYND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 28:31 - Multiple bit error detect status"] + #[inline(always)] + pub fn mbe(&self) -> MBE_R { + MBE_R::new(((self.bits >> 28) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Single bit error detect status"] + #[inline(always)] + pub fn sbe(&self) -> SBE_R { + SBE_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 0:19 - Corrected syndrome value"] + #[inline(always)] + pub fn synd_check_32_52_synd(&self) -> SYND_CHECK_32_52_SYND_R { + SYND_CHECK_32_52_SYND_R::new((self.bits & 0x000f_ffff) as u32) + } +} +#[doc = "EDAC Decode Syndrome\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synd_check_32_52_synd](index.html) module"] +pub struct SYND_CHECK_32_52_SYND_SPEC; +impl crate::RegisterSpec for SYND_CHECK_32_52_SYND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [synd_check_32_52_synd::R](R) reader structure"] +impl crate::Readable for SYND_CHECK_32_52_SYND_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYND_CHECK_32_52_SYND to value 0"] +impl crate::Resettable for SYND_CHECK_32_52_SYND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/synd_data.rs b/src/utility/synd_data.rs new file mode 100644 index 0000000..8d7c93f --- /dev/null +++ b/src/utility/synd_data.rs @@ -0,0 +1,64 @@ +#[doc = "Register `SYND_DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SYND_DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synd_data](index.html) module"] +pub struct SYND_DATA_SPEC; +impl crate::RegisterSpec for SYND_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [synd_data::R](R) reader structure"] +impl crate::Readable for SYND_DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [synd_data::W](W) writer structure"] +impl crate::Writable for SYND_DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SYND_DATA to value 0"] +impl crate::Resettable for SYND_DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/synd_enc_32_44.rs b/src/utility/synd_enc_32_44.rs new file mode 100644 index 0000000..b09459d --- /dev/null +++ b/src/utility/synd_enc_32_44.rs @@ -0,0 +1,140 @@ +#[doc = "Register `SYND_ENC_32_44` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SYND_ENC_32_44` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYND_ENC_31_16` reader - Computed syndrome value for bits 31-16"] +pub struct SYND_ENC_31_16_R(crate::FieldReader); +impl SYND_ENC_31_16_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SYND_ENC_31_16_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYND_ENC_31_16_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYND_ENC_31_16` writer - Computed syndrome value for bits 31-16"] +pub struct SYND_ENC_31_16_W<'a> { + w: &'a mut W, +} +impl<'a> SYND_ENC_31_16_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 6)) | ((value as u32 & 0x3f) << 6); + self.w + } +} +#[doc = "Field `SYND_ENC_7_0` reader - Computed syndrome value for bits 15-0"] +pub struct SYND_ENC_7_0_R(crate::FieldReader); +impl SYND_ENC_7_0_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + SYND_ENC_7_0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYND_ENC_7_0_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYND_ENC_7_0` writer - Computed syndrome value for bits 15-0"] +pub struct SYND_ENC_7_0_W<'a> { + w: &'a mut W, +} +impl<'a> SYND_ENC_7_0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +impl R { + #[doc = "Bits 6:11 - Computed syndrome value for bits 31-16"] + #[inline(always)] + pub fn synd_enc_31_16(&self) -> SYND_ENC_31_16_R { + SYND_ENC_31_16_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 0:5 - Computed syndrome value for bits 15-0"] + #[inline(always)] + pub fn synd_enc_7_0(&self) -> SYND_ENC_7_0_R { + SYND_ENC_7_0_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 6:11 - Computed syndrome value for bits 31-16"] + #[inline(always)] + pub fn synd_enc_31_16(&mut self) -> SYND_ENC_31_16_W { + SYND_ENC_31_16_W { w: self } + } + #[doc = "Bits 0:5 - Computed syndrome value for bits 15-0"] + #[inline(always)] + pub fn synd_enc_7_0(&mut self) -> SYND_ENC_7_0_W { + SYND_ENC_7_0_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EDAC Encode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synd_enc_32_44](index.html) module"] +pub struct SYND_ENC_32_44_SPEC; +impl crate::RegisterSpec for SYND_ENC_32_44_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [synd_enc_32_44::R](R) reader structure"] +impl crate::Readable for SYND_ENC_32_44_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [synd_enc_32_44::W](W) writer structure"] +impl crate::Writable for SYND_ENC_32_44_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SYND_ENC_32_44 to value 0"] +impl crate::Resettable for SYND_ENC_32_44_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/synd_enc_32_52.rs b/src/utility/synd_enc_32_52.rs new file mode 100644 index 0000000..4efbd77 --- /dev/null +++ b/src/utility/synd_enc_32_52.rs @@ -0,0 +1,53 @@ +#[doc = "Register `SYND_ENC_32_52` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SYND_ENC_32_52` reader - Computed syndrome value for bits 15-0"] +pub struct SYND_ENC_32_52_R(crate::FieldReader); +impl SYND_ENC_32_52_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + SYND_ENC_32_52_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYND_ENC_32_52_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:19 - Computed syndrome value for bits 15-0"] + #[inline(always)] + pub fn synd_enc_32_52(&self) -> SYND_ENC_32_52_R { + SYND_ENC_32_52_R::new((self.bits & 0x000f_ffff) as u32) + } +} +#[doc = "EDAC Encode\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synd_enc_32_52](index.html) module"] +pub struct SYND_ENC_32_52_SPEC; +impl crate::RegisterSpec for SYND_ENC_32_52_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [synd_enc_32_52::R](R) reader structure"] +impl crate::Readable for SYND_ENC_32_52_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYND_ENC_32_52 to value 0"] +impl crate::Resettable for SYND_ENC_32_52_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/utility/synd_synd.rs b/src/utility/synd_synd.rs new file mode 100644 index 0000000..d4a240f --- /dev/null +++ b/src/utility/synd_synd.rs @@ -0,0 +1,103 @@ +#[doc = "Register `SYND_SYND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SYND_SYND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SYND_SYND` reader - Provides bits 11:0 for syndrome, 2x6-bit"] +pub struct SYND_SYND_R(crate::FieldReader); +impl SYND_SYND_R { + #[inline(always)] + pub(crate) fn new(bits: u16) -> Self { + SYND_SYND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYND_SYND_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYND_SYND` writer - Provides bits 11:0 for syndrome, 2x6-bit"] +pub struct SYND_SYND_W<'a> { + w: &'a mut W, +} +impl<'a> SYND_SYND_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Provides bits 11:0 for syndrome, 2x6-bit"] + #[inline(always)] + pub fn synd_synd(&self) -> SYND_SYND_R { + SYND_SYND_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Provides bits 11:0 for syndrome, 2x6-bit"] + #[inline(always)] + pub fn synd_synd(&mut self) -> SYND_SYND_W { + SYND_SYND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Syndrome Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [synd_synd](index.html) module"] +pub struct SYND_SYND_SPEC; +impl crate::RegisterSpec for SYND_SYND_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [synd_synd::R](R) reader structure"] +impl crate::Readable for SYND_SYND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [synd_synd::W](W) writer structure"] +impl crate::Writable for SYND_SYND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SYND_SYND to value 0"] +impl crate::Resettable for SYND_SYND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/watch_dog.rs b/src/watch_dog.rs new file mode 100644 index 0000000..67eddd5 --- /dev/null +++ b/src/watch_dog.rs @@ -0,0 +1,109 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Counter Start Value"] + pub wdogload: crate::Reg, + #[doc = "0x04 - Down Counter Value"] + pub wdogvalue: crate::Reg, + #[doc = "0x08 - Enable for block reset and interrupt"] + pub wdogcontrol: crate::Reg, + #[doc = "0x0c - A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register"] + pub wdogintclr: crate::Reg, + #[doc = "0x10 - Raw interrupt status"] + pub wdogris: crate::Reg, + #[doc = "0x14 - Interrupt status"] + pub wdogmis: crate::Reg, + _reserved6: [u8; 0xa8], + #[doc = "0xc0 - Lock"] + pub wdoglock: crate::Reg, + _reserved7: [u8; 0x0e3c], + #[doc = "0xf00 - Integration test control"] + pub wdogitcr: crate::Reg, + #[doc = "0xf04 - Integration test output set"] + pub wdogitop: crate::Reg, + _reserved9: [u8; 0xd8], + #[doc = "0xfe0 - Peripheral ID"] + pub wdogperiphid0: crate::Reg, + #[doc = "0xfe4 - Peripheral ID"] + pub wdogperiphid1: crate::Reg, + #[doc = "0xfe8 - Peripheral ID"] + pub wdogperiphid2: crate::Reg, + #[doc = "0xfec - Peripheral ID"] + pub wdogperiphid3: crate::Reg, + #[doc = "0xff0 - PrimeCell ID"] + pub wdogpcellid0: crate::Reg, + #[doc = "0xff4 - PrimeCell ID"] + pub wdogpcellid1: crate::Reg, + #[doc = "0xff8 - PrimeCell ID"] + pub wdogpcellid2: crate::Reg, + #[doc = "0xffc - PrimeCell ID"] + pub wdogpcellid3: crate::Reg, +} +#[doc = "WDOGLOAD register accessor: an alias for `Reg`"] +pub type WDOGLOAD = crate::Reg; +#[doc = "Counter Start Value"] +pub mod wdogload; +#[doc = "WDOGVALUE register accessor: an alias for `Reg`"] +pub type WDOGVALUE = crate::Reg; +#[doc = "Down Counter Value"] +pub mod wdogvalue; +#[doc = "WDOGCONTROL register accessor: an alias for `Reg`"] +pub type WDOGCONTROL = crate::Reg; +#[doc = "Enable for block reset and interrupt"] +pub mod wdogcontrol; +#[doc = "WDOGINTCLR register accessor: an alias for `Reg`"] +pub type WDOGINTCLR = crate::Reg; +#[doc = "A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register"] +pub mod wdogintclr; +#[doc = "WDOGRIS register accessor: an alias for `Reg`"] +pub type WDOGRIS = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod wdogris; +#[doc = "WDOGMIS register accessor: an alias for `Reg`"] +pub type WDOGMIS = crate::Reg; +#[doc = "Interrupt status"] +pub mod wdogmis; +#[doc = "WDOGLOCK register accessor: an alias for `Reg`"] +pub type WDOGLOCK = crate::Reg; +#[doc = "Lock"] +pub mod wdoglock; +#[doc = "WDOGITCR register accessor: an alias for `Reg`"] +pub type WDOGITCR = crate::Reg; +#[doc = "Integration test control"] +pub mod wdogitcr; +#[doc = "WDOGITOP register accessor: an alias for `Reg`"] +pub type WDOGITOP = crate::Reg; +#[doc = "Integration test output set"] +pub mod wdogitop; +#[doc = "WDOGPERIPHID0 register accessor: an alias for `Reg`"] +pub type WDOGPERIPHID0 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid0; +#[doc = "WDOGPERIPHID1 register accessor: an alias for `Reg`"] +pub type WDOGPERIPHID1 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid1; +#[doc = "WDOGPERIPHID2 register accessor: an alias for `Reg`"] +pub type WDOGPERIPHID2 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid2; +#[doc = "WDOGPERIPHID3 register accessor: an alias for `Reg`"] +pub type WDOGPERIPHID3 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid3; +#[doc = "WDOGPCELLID0 register accessor: an alias for `Reg`"] +pub type WDOGPCELLID0 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid0; +#[doc = "WDOGPCELLID1 register accessor: an alias for `Reg`"] +pub type WDOGPCELLID1 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid1; +#[doc = "WDOGPCELLID2 register accessor: an alias for `Reg`"] +pub type WDOGPCELLID2 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid2; +#[doc = "WDOGPCELLID3 register accessor: an alias for `Reg`"] +pub type WDOGPCELLID3 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid3; diff --git a/src/watch_dog/wdogcontrol.rs b/src/watch_dog/wdogcontrol.rs new file mode 100644 index 0000000..b2a4b71 --- /dev/null +++ b/src/watch_dog/wdogcontrol.rs @@ -0,0 +1,160 @@ +#[doc = "Register `WDOGCONTROL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WDOGCONTROL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESEN` reader - Enable watchdog reset output"] +pub struct RESEN_R(crate::FieldReader); +impl RESEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + RESEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RESEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RESEN` writer - Enable watchdog reset output"] +pub struct RESEN_W<'a> { + w: &'a mut W, +} +impl<'a> RESEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `INTEN` reader - Enable watchdog interrupt"] +pub struct INTEN_R(crate::FieldReader); +impl INTEN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INTEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INTEN` writer - Enable watchdog interrupt"] +pub struct INTEN_W<'a> { + w: &'a mut W, +} +impl<'a> INTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable watchdog reset output"] + #[inline(always)] + pub fn resen(&self) -> RESEN_R { + RESEN_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Enable watchdog interrupt"] + #[inline(always)] + pub fn inten(&self) -> INTEN_R { + INTEN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable watchdog reset output"] + #[inline(always)] + pub fn resen(&mut self) -> RESEN_W { + RESEN_W { w: self } + } + #[doc = "Bit 0 - Enable watchdog interrupt"] + #[inline(always)] + pub fn inten(&mut self) -> INTEN_W { + INTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Enable for block reset and interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogcontrol](index.html) module"] +pub struct WDOGCONTROL_SPEC; +impl crate::RegisterSpec for WDOGCONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogcontrol::R](R) reader structure"] +impl crate::Readable for WDOGCONTROL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wdogcontrol::W](W) writer structure"] +impl crate::Writable for WDOGCONTROL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WDOGCONTROL to value 0"] +impl crate::Resettable for WDOGCONTROL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/watch_dog/wdogintclr.rs b/src/watch_dog/wdogintclr.rs new file mode 100644 index 0000000..95a7481 --- /dev/null +++ b/src/watch_dog/wdogintclr.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WDOGINTCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WDOGINTCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLEAR` reader - Write any value to clear interrupt"] +pub struct CLEAR_R(crate::FieldReader); +impl CLEAR_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CLEAR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLEAR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLEAR` writer - Write any value to clear interrupt"] +pub struct CLEAR_W<'a> { + w: &'a mut W, +} +impl<'a> CLEAR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write any value to clear interrupt"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write any value to clear interrupt"] + #[inline(always)] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogintclr](index.html) module"] +pub struct WDOGINTCLR_SPEC; +impl crate::RegisterSpec for WDOGINTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogintclr::R](R) reader structure"] +impl crate::Readable for WDOGINTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wdogintclr::W](W) writer structure"] +impl crate::Writable for WDOGINTCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WDOGINTCLR to value 0"] +impl crate::Resettable for WDOGINTCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/watch_dog/wdogitcr.rs b/src/watch_dog/wdogitcr.rs new file mode 100644 index 0000000..79c758e --- /dev/null +++ b/src/watch_dog/wdogitcr.rs @@ -0,0 +1,113 @@ +#[doc = "Register `WDOGITCR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WDOGITCR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TEST_MODE_EN` reader - Enable test mode of WDOGINT and WDOGRES"] +pub struct TEST_MODE_EN_R(crate::FieldReader); +impl TEST_MODE_EN_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + TEST_MODE_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TEST_MODE_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TEST_MODE_EN` writer - Enable test mode of WDOGINT and WDOGRES"] +pub struct TEST_MODE_EN_W<'a> { + w: &'a mut W, +} +impl<'a> TEST_MODE_EN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Enable test mode of WDOGINT and WDOGRES"] + #[inline(always)] + pub fn test_mode_en(&self) -> TEST_MODE_EN_R { + TEST_MODE_EN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable test mode of WDOGINT and WDOGRES"] + #[inline(always)] + pub fn test_mode_en(&mut self) -> TEST_MODE_EN_W { + TEST_MODE_EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Integration test control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogitcr](index.html) module"] +pub struct WDOGITCR_SPEC; +impl crate::RegisterSpec for WDOGITCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogitcr::R](R) reader structure"] +impl crate::Readable for WDOGITCR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wdogitcr::W](W) writer structure"] +impl crate::Writable for WDOGITCR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WDOGITCR to value 0"] +impl crate::Resettable for WDOGITCR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/watch_dog/wdogitop.rs b/src/watch_dog/wdogitop.rs new file mode 100644 index 0000000..9395a46 --- /dev/null +++ b/src/watch_dog/wdogitop.rs @@ -0,0 +1,160 @@ +#[doc = "Register `WDOGITOP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WDOGITOP` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WDOGINT` reader - Set output value"] +pub struct WDOGINT_R(crate::FieldReader); +impl WDOGINT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDOGINT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDOGINT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDOGINT` writer - Set output value"] +pub struct WDOGINT_W<'a> { + w: &'a mut W, +} +impl<'a> WDOGINT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `WDOGRES` reader - Set output value"] +pub struct WDOGRES_R(crate::FieldReader); +impl WDOGRES_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + WDOGRES_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDOGRES_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDOGRES` writer - Set output value"] +pub struct WDOGRES_W<'a> { + w: &'a mut W, +} +impl<'a> WDOGRES_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 1 - Set output value"] + #[inline(always)] + pub fn wdogint(&self) -> WDOGINT_R { + WDOGINT_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 0 - Set output value"] + #[inline(always)] + pub fn wdogres(&self) -> WDOGRES_R { + WDOGRES_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Set output value"] + #[inline(always)] + pub fn wdogint(&mut self) -> WDOGINT_W { + WDOGINT_W { w: self } + } + #[doc = "Bit 0 - Set output value"] + #[inline(always)] + pub fn wdogres(&mut self) -> WDOGRES_W { + WDOGRES_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Integration test output set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogitop](index.html) module"] +pub struct WDOGITOP_SPEC; +impl crate::RegisterSpec for WDOGITOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogitop::R](R) reader structure"] +impl crate::Readable for WDOGITOP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wdogitop::W](W) writer structure"] +impl crate::Writable for WDOGITOP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WDOGITOP to value 0"] +impl crate::Resettable for WDOGITOP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/watch_dog/wdogload.rs b/src/watch_dog/wdogload.rs new file mode 100644 index 0000000..310d163 --- /dev/null +++ b/src/watch_dog/wdogload.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WDOGLOAD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WDOGLOAD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CNT` reader - Count to load"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CNT` writer - Count to load"] +pub struct CNT_W<'a> { + w: &'a mut W, +} +impl<'a> CNT_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Count to load"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Count to load"] + #[inline(always)] + pub fn cnt(&mut self) -> CNT_W { + CNT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Counter Start Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogload](index.html) module"] +pub struct WDOGLOAD_SPEC; +impl crate::RegisterSpec for WDOGLOAD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogload::R](R) reader structure"] +impl crate::Readable for WDOGLOAD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wdogload::W](W) writer structure"] +impl crate::Writable for WDOGLOAD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WDOGLOAD to value 0xffff_ffff"] +impl crate::Resettable for WDOGLOAD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +} diff --git a/src/watch_dog/wdoglock.rs b/src/watch_dog/wdoglock.rs new file mode 100644 index 0000000..92e7f23 --- /dev/null +++ b/src/watch_dog/wdoglock.rs @@ -0,0 +1,103 @@ +#[doc = "Register `WDOGLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WDOGLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REG_WR_EN` reader - Register write enable status"] +pub struct REG_WR_EN_R(crate::FieldReader); +impl REG_WR_EN_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + REG_WR_EN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for REG_WR_EN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REG_WR_EN` writer - Register write enable status"] +pub struct REG_WR_EN_W<'a> { + w: &'a mut W, +} +impl<'a> REG_WR_EN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Register write enable status"] + #[inline(always)] + pub fn reg_wr_en(&self) -> REG_WR_EN_R { + REG_WR_EN_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Register write enable status"] + #[inline(always)] + pub fn reg_wr_en(&mut self) -> REG_WR_EN_W { + REG_WR_EN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdoglock](index.html) module"] +pub struct WDOGLOCK_SPEC; +impl crate::RegisterSpec for WDOGLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdoglock::R](R) reader structure"] +impl crate::Readable for WDOGLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wdoglock::W](W) writer structure"] +impl crate::Writable for WDOGLOCK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WDOGLOCK to value 0"] +impl crate::Resettable for WDOGLOCK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/watch_dog/wdogmis.rs b/src/watch_dog/wdogmis.rs new file mode 100644 index 0000000..26b8de6 --- /dev/null +++ b/src/watch_dog/wdogmis.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGMIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INTERRUPT` reader - Masked Interrupt Status"] +pub struct INTERRUPT_R(crate::FieldReader); +impl INTERRUPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INTERRUPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INTERRUPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Masked Interrupt Status"] + #[inline(always)] + pub fn interrupt(&self) -> INTERRUPT_R { + INTERRUPT_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogmis](index.html) module"] +pub struct WDOGMIS_SPEC; +impl crate::RegisterSpec for WDOGMIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogmis::R](R) reader structure"] +impl crate::Readable for WDOGMIS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGMIS to value 0"] +impl crate::Resettable for WDOGMIS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/watch_dog/wdogpcellid0.rs b/src/watch_dog/wdogpcellid0.rs new file mode 100644 index 0000000..12dbe3b --- /dev/null +++ b/src/watch_dog/wdogpcellid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGPCELLID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub struct PCELLID_R(crate::FieldReader); +impl PCELLID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PCELLID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PCELLID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PCELLID_R { + PCELLID_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogpcellid0](index.html) module"] +pub struct WDOGPCELLID0_SPEC; +impl crate::RegisterSpec for WDOGPCELLID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogpcellid0::R](R) reader structure"] +impl crate::Readable for WDOGPCELLID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGPCELLID0 to value 0x0d"] +impl crate::Resettable for WDOGPCELLID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0d + } +} diff --git a/src/watch_dog/wdogpcellid1.rs b/src/watch_dog/wdogpcellid1.rs new file mode 100644 index 0000000..7c63719 --- /dev/null +++ b/src/watch_dog/wdogpcellid1.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGPCELLID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub struct PCELLID_R(crate::FieldReader); +impl PCELLID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PCELLID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PCELLID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PCELLID_R { + PCELLID_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogpcellid1](index.html) module"] +pub struct WDOGPCELLID1_SPEC; +impl crate::RegisterSpec for WDOGPCELLID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogpcellid1::R](R) reader structure"] +impl crate::Readable for WDOGPCELLID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGPCELLID1 to value 0xf0"] +impl crate::Resettable for WDOGPCELLID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xf0 + } +} diff --git a/src/watch_dog/wdogpcellid2.rs b/src/watch_dog/wdogpcellid2.rs new file mode 100644 index 0000000..f23d441 --- /dev/null +++ b/src/watch_dog/wdogpcellid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGPCELLID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub struct PCELLID_R(crate::FieldReader); +impl PCELLID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PCELLID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PCELLID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PCELLID_R { + PCELLID_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogpcellid2](index.html) module"] +pub struct WDOGPCELLID2_SPEC; +impl crate::RegisterSpec for WDOGPCELLID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogpcellid2::R](R) reader structure"] +impl crate::Readable for WDOGPCELLID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGPCELLID2 to value 0x05"] +impl crate::Resettable for WDOGPCELLID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x05 + } +} diff --git a/src/watch_dog/wdogpcellid3.rs b/src/watch_dog/wdogpcellid3.rs new file mode 100644 index 0000000..69ffda4 --- /dev/null +++ b/src/watch_dog/wdogpcellid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGPCELLID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub struct PCELLID_R(crate::FieldReader); +impl PCELLID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PCELLID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PCELLID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PCELLID_R { + PCELLID_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogpcellid3](index.html) module"] +pub struct WDOGPCELLID3_SPEC; +impl crate::RegisterSpec for WDOGPCELLID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogpcellid3::R](R) reader structure"] +impl crate::Readable for WDOGPCELLID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGPCELLID3 to value 0xb1"] +impl crate::Resettable for WDOGPCELLID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb1 + } +} diff --git a/src/watch_dog/wdogperiphid0.rs b/src/watch_dog/wdogperiphid0.rs new file mode 100644 index 0000000..a422d64 --- /dev/null +++ b/src/watch_dog/wdogperiphid0.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGPERIPHID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub struct PERIPHID_R(crate::FieldReader); +impl PERIPHID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERIPHID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERIPHID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PERIPHID_R { + PERIPHID_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogperiphid0](index.html) module"] +pub struct WDOGPERIPHID0_SPEC; +impl crate::RegisterSpec for WDOGPERIPHID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogperiphid0::R](R) reader structure"] +impl crate::Readable for WDOGPERIPHID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGPERIPHID0 to value 0x24"] +impl crate::Resettable for WDOGPERIPHID0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x24 + } +} diff --git a/src/watch_dog/wdogperiphid1.rs b/src/watch_dog/wdogperiphid1.rs new file mode 100644 index 0000000..8d6a39d --- /dev/null +++ b/src/watch_dog/wdogperiphid1.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGPERIPHID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub struct PERIPHID_R(crate::FieldReader); +impl PERIPHID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERIPHID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERIPHID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PERIPHID_R { + PERIPHID_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogperiphid1](index.html) module"] +pub struct WDOGPERIPHID1_SPEC; +impl crate::RegisterSpec for WDOGPERIPHID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogperiphid1::R](R) reader structure"] +impl crate::Readable for WDOGPERIPHID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGPERIPHID1 to value 0xb8"] +impl crate::Resettable for WDOGPERIPHID1_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xb8 + } +} diff --git a/src/watch_dog/wdogperiphid2.rs b/src/watch_dog/wdogperiphid2.rs new file mode 100644 index 0000000..7ae35fc --- /dev/null +++ b/src/watch_dog/wdogperiphid2.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGPERIPHID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub struct PERIPHID_R(crate::FieldReader); +impl PERIPHID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERIPHID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERIPHID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PERIPHID_R { + PERIPHID_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogperiphid2](index.html) module"] +pub struct WDOGPERIPHID2_SPEC; +impl crate::RegisterSpec for WDOGPERIPHID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogperiphid2::R](R) reader structure"] +impl crate::Readable for WDOGPERIPHID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGPERIPHID2 to value 0x1b"] +impl crate::Resettable for WDOGPERIPHID2_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x1b + } +} diff --git a/src/watch_dog/wdogperiphid3.rs b/src/watch_dog/wdogperiphid3.rs new file mode 100644 index 0000000..dd0040d --- /dev/null +++ b/src/watch_dog/wdogperiphid3.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGPERIPHID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub struct PERIPHID_R(crate::FieldReader); +impl PERIPHID_R { + #[inline(always)] + pub(crate) fn new(bits: u8) -> Self { + PERIPHID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PERIPHID_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PERIPHID_R { + PERIPHID_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogperiphid3](index.html) module"] +pub struct WDOGPERIPHID3_SPEC; +impl crate::RegisterSpec for WDOGPERIPHID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogperiphid3::R](R) reader structure"] +impl crate::Readable for WDOGPERIPHID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGPERIPHID3 to value 0"] +impl crate::Resettable for WDOGPERIPHID3_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/watch_dog/wdogris.rs b/src/watch_dog/wdogris.rs new file mode 100644 index 0000000..fb519d0 --- /dev/null +++ b/src/watch_dog/wdogris.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGRIS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `INTERRUPT` reader - Interrupt Status"] +pub struct INTERRUPT_R(crate::FieldReader); +impl INTERRUPT_R { + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + INTERRUPT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for INTERRUPT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Interrupt Status"] + #[inline(always)] + pub fn interrupt(&self) -> INTERRUPT_R { + INTERRUPT_R::new((self.bits & 0x01) != 0) + } +} +#[doc = "Raw interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogris](index.html) module"] +pub struct WDOGRIS_SPEC; +impl crate::RegisterSpec for WDOGRIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogris::R](R) reader structure"] +impl crate::Readable for WDOGRIS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGRIS to value 0"] +impl crate::Resettable for WDOGRIS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/watch_dog/wdogvalue.rs b/src/watch_dog/wdogvalue.rs new file mode 100644 index 0000000..18c388b --- /dev/null +++ b/src/watch_dog/wdogvalue.rs @@ -0,0 +1,53 @@ +#[doc = "Register `WDOGVALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CNT` reader - Actual Count"] +pub struct CNT_R(crate::FieldReader); +impl CNT_R { + #[inline(always)] + pub(crate) fn new(bits: u32) -> Self { + CNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CNT_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bits 0:31 - Actual Count"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new((self.bits & 0xffff_ffff) as u32) + } +} +#[doc = "Down Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdogvalue](index.html) module"] +pub struct WDOGVALUE_SPEC; +impl crate::RegisterSpec for WDOGVALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wdogvalue::R](R) reader structure"] +impl crate::Readable for WDOGVALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets WDOGVALUE to value 0xffff_ffff"] +impl crate::Resettable for WDOGVALUE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0xffff_ffff + } +}