224 lines
12 KiB
Rust
224 lines
12 KiB
Rust
#[doc = r"Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - DMA Status"]
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pub status: crate::Reg<status::STATUS_SPEC>,
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#[doc = "0x04 - DMA Configuration"]
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pub cfg: crate::Reg<cfg::CFG_SPEC>,
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#[doc = "0x08 - Base Pointer for DMA Control Registers"]
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pub ctrl_base_ptr: crate::Reg<ctrl_base_ptr::CTRL_BASE_PTR_SPEC>,
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#[doc = "0x0c - DMA Channel alternate control data base pointer"]
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pub alt_ctrl_base_ptr: crate::Reg<alt_ctrl_base_ptr::ALT_CTRL_BASE_PTR_SPEC>,
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#[doc = "0x10 - DMA channel wait on request status"]
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pub waitonreq_status: crate::Reg<waitonreq_status::WAITONREQ_STATUS_SPEC>,
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#[doc = "0x14 - DMA channel software request"]
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pub chnl_sw_request: crate::Reg<chnl_sw_request::CHNL_SW_REQUEST_SPEC>,
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#[doc = "0x18 - DMA channel useburst set"]
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pub chnl_useburst_set: crate::Reg<chnl_useburst_set::CHNL_USEBURST_SET_SPEC>,
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#[doc = "0x1c - DMA channel useburst clear"]
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pub chnl_useburst_clr: crate::Reg<chnl_useburst_clr::CHNL_USEBURST_CLR_SPEC>,
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#[doc = "0x20 - DMA channel request mask set"]
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pub chnl_req_mask_set: crate::Reg<chnl_req_mask_set::CHNL_REQ_MASK_SET_SPEC>,
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#[doc = "0x24 - DMA channel request mask clear"]
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pub chnl_req_mask_clr: crate::Reg<chnl_req_mask_clr::CHNL_REQ_MASK_CLR_SPEC>,
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#[doc = "0x28 - DMA channel enable set"]
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pub chnl_enable_set: crate::Reg<chnl_enable_set::CHNL_ENABLE_SET_SPEC>,
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#[doc = "0x2c - DMA channel enable clear"]
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pub chnl_enable_clr: crate::Reg<chnl_enable_clr::CHNL_ENABLE_CLR_SPEC>,
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#[doc = "0x30 - DMA channel primary alternate set"]
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pub chnl_pri_alt_set: crate::Reg<chnl_pri_alt_set::CHNL_PRI_ALT_SET_SPEC>,
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#[doc = "0x34 - DMA channel primary alternate clear"]
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pub chnl_pri_alt_clr: crate::Reg<chnl_pri_alt_clr::CHNL_PRI_ALT_CLR_SPEC>,
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#[doc = "0x38 - DMA channel priority set"]
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pub chnl_priority_set: crate::Reg<chnl_priority_set::CHNL_PRIORITY_SET_SPEC>,
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#[doc = "0x3c - DMA channel priority clear"]
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pub chnl_priority_clr: crate::Reg<chnl_priority_clr::CHNL_PRIORITY_CLR_SPEC>,
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_reserved16: [u8; 0x0c],
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#[doc = "0x4c - DMA bus error clear"]
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pub err_clr: crate::Reg<err_clr::ERR_CLR_SPEC>,
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_reserved17: [u8; 0x0db0],
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#[doc = "0xe00 - DMA integration configuration"]
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pub integration_cfg: crate::Reg<integration_cfg::INTEGRATION_CFG_SPEC>,
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_reserved18: [u8; 0x04],
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#[doc = "0xe08 - DMA stall status"]
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pub stall_status: crate::Reg<stall_status::STALL_STATUS_SPEC>,
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_reserved19: [u8; 0x04],
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#[doc = "0xe10 - DMA Configuration"]
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pub dma_req_status: crate::Reg<dma_req_status::DMA_REQ_STATUS_SPEC>,
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_reserved20: [u8; 0x04],
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#[doc = "0xe18 - DMA single request status"]
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pub dma_sreq_status: crate::Reg<dma_sreq_status::DMA_SREQ_STATUS_SPEC>,
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_reserved21: [u8; 0x04],
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#[doc = "0xe20 - DMA done set"]
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pub dma_done_set: crate::Reg<dma_done_set::DMA_DONE_SET_SPEC>,
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#[doc = "0xe24 - DMA done clear"]
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pub dma_done_clr: crate::Reg<dma_done_clr::DMA_DONE_CLR_SPEC>,
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#[doc = "0xe28 - DMA active set"]
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pub dma_active_set: crate::Reg<dma_active_set::DMA_ACTIVE_SET_SPEC>,
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#[doc = "0xe2c - DMA active clear"]
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pub dma_active_clr: crate::Reg<dma_active_clr::DMA_ACTIVE_CLR_SPEC>,
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_reserved25: [u8; 0x18],
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#[doc = "0xe48 - DMA bus error set"]
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pub err_set: crate::Reg<err_set::ERR_SET_SPEC>,
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_reserved26: [u8; 0x0184],
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#[doc = "0xfd0 - DMA Peripheral ID 4"]
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pub periph_id_4: crate::Reg<periph_id_4::PERIPH_ID_4_SPEC>,
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_reserved27: [u8; 0x0c],
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#[doc = "0xfe0 - DMA Peripheral ID 0"]
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pub periph_id_0: crate::Reg<periph_id_0::PERIPH_ID_0_SPEC>,
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#[doc = "0xfe4 - DMA Peripheral ID 1"]
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pub periph_id_1: crate::Reg<periph_id_1::PERIPH_ID_1_SPEC>,
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#[doc = "0xfe8 - DMA Peripheral ID 2"]
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pub periph_id_2: crate::Reg<periph_id_2::PERIPH_ID_2_SPEC>,
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#[doc = "0xfec - DMA Peripheral ID 3"]
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pub periph_id_3: crate::Reg<periph_id_3::PERIPH_ID_3_SPEC>,
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#[doc = "0xff0 - DMA PrimeCell ID 0"]
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pub primecell_id_0: crate::Reg<primecell_id_0::PRIMECELL_ID_0_SPEC>,
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#[doc = "0xff4 - DMA PrimeCell ID 1"]
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pub primecell_id_1: crate::Reg<primecell_id_1::PRIMECELL_ID_1_SPEC>,
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#[doc = "0xff8 - DMA PrimeCell ID 2"]
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pub primecell_id_2: crate::Reg<primecell_id_2::PRIMECELL_ID_2_SPEC>,
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#[doc = "0xffc - DMA PrimeCell ID 3"]
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pub primecell_id_3: crate::Reg<primecell_id_3::PRIMECELL_ID_3_SPEC>,
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}
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#[doc = "STATUS register accessor: an alias for `Reg<STATUS_SPEC>`"]
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pub type STATUS = crate::Reg<status::STATUS_SPEC>;
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#[doc = "DMA Status"]
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pub mod status;
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#[doc = "CFG register accessor: an alias for `Reg<CFG_SPEC>`"]
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pub type CFG = crate::Reg<cfg::CFG_SPEC>;
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#[doc = "DMA Configuration"]
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pub mod cfg;
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#[doc = "CTRL_BASE_PTR register accessor: an alias for `Reg<CTRL_BASE_PTR_SPEC>`"]
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pub type CTRL_BASE_PTR = crate::Reg<ctrl_base_ptr::CTRL_BASE_PTR_SPEC>;
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#[doc = "Base Pointer for DMA Control Registers"]
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pub mod ctrl_base_ptr;
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#[doc = "ALT_CTRL_BASE_PTR register accessor: an alias for `Reg<ALT_CTRL_BASE_PTR_SPEC>`"]
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pub type ALT_CTRL_BASE_PTR = crate::Reg<alt_ctrl_base_ptr::ALT_CTRL_BASE_PTR_SPEC>;
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#[doc = "DMA Channel alternate control data base pointer"]
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pub mod alt_ctrl_base_ptr;
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#[doc = "WAITONREQ_STATUS register accessor: an alias for `Reg<WAITONREQ_STATUS_SPEC>`"]
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pub type WAITONREQ_STATUS = crate::Reg<waitonreq_status::WAITONREQ_STATUS_SPEC>;
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#[doc = "DMA channel wait on request status"]
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pub mod waitonreq_status;
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#[doc = "CHNL_SW_REQUEST register accessor: an alias for `Reg<CHNL_SW_REQUEST_SPEC>`"]
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pub type CHNL_SW_REQUEST = crate::Reg<chnl_sw_request::CHNL_SW_REQUEST_SPEC>;
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#[doc = "DMA channel software request"]
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pub mod chnl_sw_request;
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#[doc = "CHNL_USEBURST_SET register accessor: an alias for `Reg<CHNL_USEBURST_SET_SPEC>`"]
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pub type CHNL_USEBURST_SET = crate::Reg<chnl_useburst_set::CHNL_USEBURST_SET_SPEC>;
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#[doc = "DMA channel useburst set"]
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pub mod chnl_useburst_set;
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#[doc = "CHNL_USEBURST_CLR register accessor: an alias for `Reg<CHNL_USEBURST_CLR_SPEC>`"]
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pub type CHNL_USEBURST_CLR = crate::Reg<chnl_useburst_clr::CHNL_USEBURST_CLR_SPEC>;
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#[doc = "DMA channel useburst clear"]
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pub mod chnl_useburst_clr;
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#[doc = "CHNL_REQ_MASK_SET register accessor: an alias for `Reg<CHNL_REQ_MASK_SET_SPEC>`"]
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pub type CHNL_REQ_MASK_SET = crate::Reg<chnl_req_mask_set::CHNL_REQ_MASK_SET_SPEC>;
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#[doc = "DMA channel request mask set"]
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pub mod chnl_req_mask_set;
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#[doc = "CHNL_REQ_MASK_CLR register accessor: an alias for `Reg<CHNL_REQ_MASK_CLR_SPEC>`"]
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pub type CHNL_REQ_MASK_CLR = crate::Reg<chnl_req_mask_clr::CHNL_REQ_MASK_CLR_SPEC>;
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#[doc = "DMA channel request mask clear"]
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pub mod chnl_req_mask_clr;
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#[doc = "CHNL_ENABLE_SET register accessor: an alias for `Reg<CHNL_ENABLE_SET_SPEC>`"]
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pub type CHNL_ENABLE_SET = crate::Reg<chnl_enable_set::CHNL_ENABLE_SET_SPEC>;
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#[doc = "DMA channel enable set"]
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pub mod chnl_enable_set;
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#[doc = "CHNL_ENABLE_CLR register accessor: an alias for `Reg<CHNL_ENABLE_CLR_SPEC>`"]
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pub type CHNL_ENABLE_CLR = crate::Reg<chnl_enable_clr::CHNL_ENABLE_CLR_SPEC>;
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#[doc = "DMA channel enable clear"]
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pub mod chnl_enable_clr;
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#[doc = "CHNL_PRI_ALT_SET register accessor: an alias for `Reg<CHNL_PRI_ALT_SET_SPEC>`"]
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pub type CHNL_PRI_ALT_SET = crate::Reg<chnl_pri_alt_set::CHNL_PRI_ALT_SET_SPEC>;
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#[doc = "DMA channel primary alternate set"]
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pub mod chnl_pri_alt_set;
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#[doc = "CHNL_PRI_ALT_CLR register accessor: an alias for `Reg<CHNL_PRI_ALT_CLR_SPEC>`"]
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pub type CHNL_PRI_ALT_CLR = crate::Reg<chnl_pri_alt_clr::CHNL_PRI_ALT_CLR_SPEC>;
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#[doc = "DMA channel primary alternate clear"]
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pub mod chnl_pri_alt_clr;
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#[doc = "CHNL_PRIORITY_SET register accessor: an alias for `Reg<CHNL_PRIORITY_SET_SPEC>`"]
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pub type CHNL_PRIORITY_SET = crate::Reg<chnl_priority_set::CHNL_PRIORITY_SET_SPEC>;
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#[doc = "DMA channel priority set"]
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pub mod chnl_priority_set;
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#[doc = "CHNL_PRIORITY_CLR register accessor: an alias for `Reg<CHNL_PRIORITY_CLR_SPEC>`"]
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pub type CHNL_PRIORITY_CLR = crate::Reg<chnl_priority_clr::CHNL_PRIORITY_CLR_SPEC>;
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#[doc = "DMA channel priority clear"]
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pub mod chnl_priority_clr;
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#[doc = "ERR_CLR register accessor: an alias for `Reg<ERR_CLR_SPEC>`"]
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pub type ERR_CLR = crate::Reg<err_clr::ERR_CLR_SPEC>;
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#[doc = "DMA bus error clear"]
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pub mod err_clr;
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#[doc = "INTEGRATION_CFG register accessor: an alias for `Reg<INTEGRATION_CFG_SPEC>`"]
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pub type INTEGRATION_CFG = crate::Reg<integration_cfg::INTEGRATION_CFG_SPEC>;
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#[doc = "DMA integration configuration"]
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pub mod integration_cfg;
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#[doc = "STALL_STATUS register accessor: an alias for `Reg<STALL_STATUS_SPEC>`"]
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pub type STALL_STATUS = crate::Reg<stall_status::STALL_STATUS_SPEC>;
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#[doc = "DMA stall status"]
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pub mod stall_status;
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#[doc = "DMA_REQ_STATUS register accessor: an alias for `Reg<DMA_REQ_STATUS_SPEC>`"]
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pub type DMA_REQ_STATUS = crate::Reg<dma_req_status::DMA_REQ_STATUS_SPEC>;
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#[doc = "DMA Configuration"]
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pub mod dma_req_status;
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#[doc = "DMA_SREQ_STATUS register accessor: an alias for `Reg<DMA_SREQ_STATUS_SPEC>`"]
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pub type DMA_SREQ_STATUS = crate::Reg<dma_sreq_status::DMA_SREQ_STATUS_SPEC>;
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#[doc = "DMA single request status"]
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pub mod dma_sreq_status;
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#[doc = "DMA_DONE_SET register accessor: an alias for `Reg<DMA_DONE_SET_SPEC>`"]
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pub type DMA_DONE_SET = crate::Reg<dma_done_set::DMA_DONE_SET_SPEC>;
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#[doc = "DMA done set"]
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pub mod dma_done_set;
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#[doc = "DMA_DONE_CLR register accessor: an alias for `Reg<DMA_DONE_CLR_SPEC>`"]
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pub type DMA_DONE_CLR = crate::Reg<dma_done_clr::DMA_DONE_CLR_SPEC>;
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#[doc = "DMA done clear"]
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pub mod dma_done_clr;
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#[doc = "DMA_ACTIVE_SET register accessor: an alias for `Reg<DMA_ACTIVE_SET_SPEC>`"]
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pub type DMA_ACTIVE_SET = crate::Reg<dma_active_set::DMA_ACTIVE_SET_SPEC>;
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#[doc = "DMA active set"]
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pub mod dma_active_set;
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#[doc = "DMA_ACTIVE_CLR register accessor: an alias for `Reg<DMA_ACTIVE_CLR_SPEC>`"]
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pub type DMA_ACTIVE_CLR = crate::Reg<dma_active_clr::DMA_ACTIVE_CLR_SPEC>;
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#[doc = "DMA active clear"]
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pub mod dma_active_clr;
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#[doc = "ERR_SET register accessor: an alias for `Reg<ERR_SET_SPEC>`"]
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pub type ERR_SET = crate::Reg<err_set::ERR_SET_SPEC>;
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#[doc = "DMA bus error set"]
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pub mod err_set;
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#[doc = "PERIPH_ID_4 register accessor: an alias for `Reg<PERIPH_ID_4_SPEC>`"]
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pub type PERIPH_ID_4 = crate::Reg<periph_id_4::PERIPH_ID_4_SPEC>;
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#[doc = "DMA Peripheral ID 4"]
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pub mod periph_id_4;
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#[doc = "PERIPH_ID_0 register accessor: an alias for `Reg<PERIPH_ID_0_SPEC>`"]
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pub type PERIPH_ID_0 = crate::Reg<periph_id_0::PERIPH_ID_0_SPEC>;
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#[doc = "DMA Peripheral ID 0"]
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pub mod periph_id_0;
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#[doc = "PERIPH_ID_1 register accessor: an alias for `Reg<PERIPH_ID_1_SPEC>`"]
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pub type PERIPH_ID_1 = crate::Reg<periph_id_1::PERIPH_ID_1_SPEC>;
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#[doc = "DMA Peripheral ID 1"]
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pub mod periph_id_1;
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#[doc = "PERIPH_ID_2 register accessor: an alias for `Reg<PERIPH_ID_2_SPEC>`"]
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pub type PERIPH_ID_2 = crate::Reg<periph_id_2::PERIPH_ID_2_SPEC>;
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#[doc = "DMA Peripheral ID 2"]
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pub mod periph_id_2;
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#[doc = "PERIPH_ID_3 register accessor: an alias for `Reg<PERIPH_ID_3_SPEC>`"]
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pub type PERIPH_ID_3 = crate::Reg<periph_id_3::PERIPH_ID_3_SPEC>;
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#[doc = "DMA Peripheral ID 3"]
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pub mod periph_id_3;
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#[doc = "PRIMECELL_ID_0 register accessor: an alias for `Reg<PRIMECELL_ID_0_SPEC>`"]
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pub type PRIMECELL_ID_0 = crate::Reg<primecell_id_0::PRIMECELL_ID_0_SPEC>;
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#[doc = "DMA PrimeCell ID 0"]
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pub mod primecell_id_0;
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#[doc = "PRIMECELL_ID_1 register accessor: an alias for `Reg<PRIMECELL_ID_1_SPEC>`"]
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pub type PRIMECELL_ID_1 = crate::Reg<primecell_id_1::PRIMECELL_ID_1_SPEC>;
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#[doc = "DMA PrimeCell ID 1"]
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pub mod primecell_id_1;
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#[doc = "PRIMECELL_ID_2 register accessor: an alias for `Reg<PRIMECELL_ID_2_SPEC>`"]
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pub type PRIMECELL_ID_2 = crate::Reg<primecell_id_2::PRIMECELL_ID_2_SPEC>;
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#[doc = "DMA PrimeCell ID 2"]
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pub mod primecell_id_2;
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#[doc = "PRIMECELL_ID_3 register accessor: an alias for `Reg<PRIMECELL_ID_3_SPEC>`"]
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pub type PRIMECELL_ID_3 = crate::Reg<primecell_id_3::PRIMECELL_ID_3_SPEC>;
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#[doc = "DMA PrimeCell ID 3"]
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pub mod primecell_id_3;
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