396 lines
12 KiB
Rust
396 lines
12 KiB
Rust
#[doc = "Register `IRQ_ENB` reader"]
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pub struct R(crate::R<IRQ_ENB_SPEC>);
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impl core::ops::Deref for R {
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type Target = crate::R<IRQ_ENB_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl From<crate::R<IRQ_ENB_SPEC>> for R {
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#[inline(always)]
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fn from(reader: crate::R<IRQ_ENB_SPEC>) -> Self {
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R(reader)
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}
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}
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#[doc = "Register `IRQ_ENB` writer"]
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pub struct W(crate::W<IRQ_ENB_SPEC>);
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impl core::ops::Deref for W {
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type Target = crate::W<IRQ_ENB_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl core::ops::DerefMut for W {
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#[inline(always)]
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fn deref_mut(&mut self) -> &mut Self::Target {
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&mut self.0
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}
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}
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impl From<crate::W<IRQ_ENB_SPEC>> for W {
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#[inline(always)]
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fn from(writer: crate::W<IRQ_ENB_SPEC>) -> Self {
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W(writer)
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}
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}
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#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
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pub struct FIFO_DEPTH_TRIG_R(crate::FieldReader<bool, bool>);
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impl FIFO_DEPTH_TRIG_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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FIFO_DEPTH_TRIG_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for FIFO_DEPTH_TRIG_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
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pub struct FIFO_DEPTH_TRIG_W<'a> {
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w: &'a mut W,
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}
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impl<'a> FIFO_DEPTH_TRIG_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
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self.w
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}
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}
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#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"]
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pub struct TRIG_ERROR_R(crate::FieldReader<bool, bool>);
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impl TRIG_ERROR_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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TRIG_ERROR_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for TRIG_ERROR_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"]
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pub struct TRIG_ERROR_W<'a> {
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w: &'a mut W,
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}
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impl<'a> TRIG_ERROR_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
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self.w
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}
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}
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#[doc = "Field `ADC_DONE` reader - Enables the interrupt for an ADC data acquisition completion"]
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pub struct ADC_DONE_R(crate::FieldReader<bool, bool>);
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impl ADC_DONE_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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ADC_DONE_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for ADC_DONE_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `ADC_DONE` writer - Enables the interrupt for an ADC data acquisition completion"]
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pub struct ADC_DONE_W<'a> {
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w: &'a mut W,
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}
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impl<'a> ADC_DONE_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
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self.w
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}
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}
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#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"]
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pub struct FIFO_UFLOW_R(crate::FieldReader<bool, bool>);
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impl FIFO_UFLOW_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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FIFO_UFLOW_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for FIFO_UFLOW_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"]
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pub struct FIFO_UFLOW_W<'a> {
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w: &'a mut W,
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}
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impl<'a> FIFO_UFLOW_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
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self.w
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}
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}
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#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"]
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pub struct FIFO_OFLOW_R(crate::FieldReader<bool, bool>);
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impl FIFO_OFLOW_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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FIFO_OFLOW_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for FIFO_OFLOW_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"]
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pub struct FIFO_OFLOW_W<'a> {
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w: &'a mut W,
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}
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impl<'a> FIFO_OFLOW_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
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self.w
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}
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}
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#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"]
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pub struct FIFO_FULL_R(crate::FieldReader<bool, bool>);
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impl FIFO_FULL_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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FIFO_FULL_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for FIFO_FULL_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"]
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pub struct FIFO_FULL_W<'a> {
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w: &'a mut W,
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}
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impl<'a> FIFO_FULL_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
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self.w
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}
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}
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#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"]
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pub struct FIFO_EMPTY_R(crate::FieldReader<bool, bool>);
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impl FIFO_EMPTY_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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FIFO_EMPTY_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for FIFO_EMPTY_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"]
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pub struct FIFO_EMPTY_W<'a> {
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w: &'a mut W,
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}
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impl<'a> FIFO_EMPTY_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
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self.w
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}
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}
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impl R {
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#[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
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#[inline(always)]
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pub fn fifo_depth_trig(&self) -> FIFO_DEPTH_TRIG_R {
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FIFO_DEPTH_TRIG_R::new(((self.bits >> 6) & 0x01) != 0)
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}
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#[doc = "Bit 5 - Enables the interrupt for a trigger error"]
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#[inline(always)]
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pub fn trig_error(&self) -> TRIG_ERROR_R {
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TRIG_ERROR_R::new(((self.bits >> 5) & 0x01) != 0)
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}
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#[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
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#[inline(always)]
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pub fn adc_done(&self) -> ADC_DONE_R {
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ADC_DONE_R::new(((self.bits >> 4) & 0x01) != 0)
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}
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#[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
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#[inline(always)]
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pub fn fifo_uflow(&self) -> FIFO_UFLOW_R {
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FIFO_UFLOW_R::new(((self.bits >> 3) & 0x01) != 0)
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}
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#[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
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#[inline(always)]
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pub fn fifo_oflow(&self) -> FIFO_OFLOW_R {
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FIFO_OFLOW_R::new(((self.bits >> 2) & 0x01) != 0)
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}
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#[doc = "Bit 1 - Enables the interrupt for FIFO full"]
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#[inline(always)]
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pub fn fifo_full(&self) -> FIFO_FULL_R {
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FIFO_FULL_R::new(((self.bits >> 1) & 0x01) != 0)
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}
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#[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
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#[inline(always)]
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pub fn fifo_empty(&self) -> FIFO_EMPTY_R {
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FIFO_EMPTY_R::new((self.bits & 0x01) != 0)
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}
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}
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impl W {
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#[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
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#[inline(always)]
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pub fn fifo_depth_trig(&mut self) -> FIFO_DEPTH_TRIG_W {
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FIFO_DEPTH_TRIG_W { w: self }
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}
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#[doc = "Bit 5 - Enables the interrupt for a trigger error"]
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#[inline(always)]
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pub fn trig_error(&mut self) -> TRIG_ERROR_W {
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TRIG_ERROR_W { w: self }
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}
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#[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
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#[inline(always)]
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pub fn adc_done(&mut self) -> ADC_DONE_W {
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ADC_DONE_W { w: self }
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}
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#[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
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#[inline(always)]
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pub fn fifo_uflow(&mut self) -> FIFO_UFLOW_W {
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FIFO_UFLOW_W { w: self }
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}
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#[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
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#[inline(always)]
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pub fn fifo_oflow(&mut self) -> FIFO_OFLOW_W {
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FIFO_OFLOW_W { w: self }
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}
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#[doc = "Bit 1 - Enables the interrupt for FIFO full"]
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#[inline(always)]
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pub fn fifo_full(&mut self) -> FIFO_FULL_W {
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FIFO_FULL_W { w: self }
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}
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#[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
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#[inline(always)]
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pub fn fifo_empty(&mut self) -> FIFO_EMPTY_W {
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FIFO_EMPTY_W { w: self }
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}
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#[doc = "Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.0.bits(bits);
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self
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}
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}
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#[doc = "Interrupt Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"]
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pub struct IRQ_ENB_SPEC;
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impl crate::RegisterSpec for IRQ_ENB_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [irq_enb::R](R) reader structure"]
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impl crate::Readable for IRQ_ENB_SPEC {
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type Reader = R;
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}
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#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"]
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impl crate::Writable for IRQ_ENB_SPEC {
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type Writer = W;
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}
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#[doc = "`reset()` method sets IRQ_ENB to value 0"]
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impl crate::Resettable for IRQ_ENB_SPEC {
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#[inline(always)]
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fn reset_value() -> Self::Ux {
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0
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}
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}
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