151 lines
4.4 KiB
Rust
151 lines
4.4 KiB
Rust
#[doc = "Register `CICEN` reader"]
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pub struct R(crate::R<CICEN_SPEC>);
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impl core::ops::Deref for R {
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type Target = crate::R<CICEN_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl From<crate::R<CICEN_SPEC>> for R {
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#[inline(always)]
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fn from(reader: crate::R<CICEN_SPEC>) -> Self {
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R(reader)
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}
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}
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#[doc = "Register `CICEN` writer"]
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pub struct W(crate::W<CICEN_SPEC>);
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impl core::ops::Deref for W {
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type Target = crate::W<CICEN_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl core::ops::DerefMut for W {
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#[inline(always)]
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fn deref_mut(&mut self) -> &mut Self::Target {
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&mut self.0
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}
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}
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impl From<crate::W<CICEN_SPEC>> for W {
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#[inline(always)]
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fn from(writer: crate::W<CICEN_SPEC>) -> Self {
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W(writer)
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}
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}
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#[doc = "Field `EICEN` reader - Error Interrupt Code Enable"]
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pub struct EICEN_R(crate::FieldReader<bool, bool>);
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impl EICEN_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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EICEN_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for EICEN_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `EICEN` writer - Error Interrupt Code Enable"]
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pub struct EICEN_W<'a> {
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w: &'a mut W,
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}
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impl<'a> EICEN_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
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self.w
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}
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}
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#[doc = "Field `ICEN` reader - Buffer Interrupt Code Enable\\[14:0\\]"]
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pub struct ICEN_R(crate::FieldReader<u16, u16>);
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impl ICEN_R {
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#[inline(always)]
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pub(crate) fn new(bits: u16) -> Self {
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ICEN_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for ICEN_R {
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type Target = crate::FieldReader<u16, u16>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `ICEN` writer - Buffer Interrupt Code Enable\\[14:0\\]"]
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pub struct ICEN_W<'a> {
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w: &'a mut W,
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}
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impl<'a> ICEN_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u16) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x7fff) | (value as u32 & 0x7fff);
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self.w
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}
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}
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impl R {
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#[doc = "Bit 15 - Error Interrupt Code Enable"]
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#[inline(always)]
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pub fn eicen(&self) -> EICEN_R {
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EICEN_R::new(((self.bits >> 15) & 0x01) != 0)
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}
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#[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"]
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#[inline(always)]
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pub fn icen(&self) -> ICEN_R {
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ICEN_R::new((self.bits & 0x7fff) as u16)
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}
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}
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impl W {
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#[doc = "Bit 15 - Error Interrupt Code Enable"]
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#[inline(always)]
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pub fn eicen(&mut self) -> EICEN_W {
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EICEN_W { w: self }
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}
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#[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"]
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#[inline(always)]
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pub fn icen(&mut self) -> ICEN_W {
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ICEN_W { w: self }
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}
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#[doc = "Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.0.bits(bits);
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self
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}
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}
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#[doc = "CAN Interrupt Code Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cicen](index.html) module"]
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pub struct CICEN_SPEC;
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impl crate::RegisterSpec for CICEN_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [cicen::R](R) reader structure"]
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impl crate::Readable for CICEN_SPEC {
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type Reader = R;
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}
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#[doc = "`write(|w| ..)` method takes [cicen::W](W) writer structure"]
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impl crate::Writable for CICEN_SPEC {
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type Writer = W;
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}
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#[doc = "`reset()` method sets CICEN to value 0"]
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impl crate::Resettable for CICEN_SPEC {
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#[inline(always)]
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fn reset_value() -> Self::Ux {
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0
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}
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}
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