#![doc = "Peripheral access API for VA416XX microcontrollers (generated using svd2rust v0.37.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 4;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[allow(unused_imports)]
use generic::*;
#[doc = r"Common register and bit access and modify traits"]
pub mod generic;
#[cfg(feature = "rt")]
extern "C" {
    fn U0();
    fn U1();
    fn U2();
    fn U3();
    fn U4();
    fn U5();
    fn U6();
    fn U7();
    fn U8();
    fn U9();
    fn U10();
    fn U11();
    fn U12();
    fn U13();
    fn U14();
    fn U15();
    fn SPI0_TX();
    fn SPI0_RX();
    fn SPI1_TX();
    fn SPI1_RX();
    fn SPI2_TX();
    fn SPI2_RX();
    fn SPI3_TX();
    fn SPI3_RX();
    fn UART0_TX();
    fn UART0_RX();
    fn UART1_TX();
    fn UART1_RX();
    fn UART2_TX();
    fn UART2_RX();
    fn I2C0_MS();
    fn I2C0_SL();
    fn I2C1_MS();
    fn I2C1_SL();
    fn I2C2_MS();
    fn I2C2_SL();
    fn Ethernet();
    fn U37();
    fn SpW();
    fn U39();
    fn DAC0();
    fn DAC1();
    fn TRNG();
    fn DMA_ERROR();
    fn ADC();
    fn LoCLK();
    fn LVD();
    fn WATCHDOG();
    fn TIM0();
    fn TIM1();
    fn TIM2();
    fn TIM3();
    fn TIM4();
    fn TIM5();
    fn TIM6();
    fn TIM7();
    fn TIM8();
    fn TIM9();
    fn TIM10();
    fn TIM11();
    fn TIM12();
    fn TIM13();
    fn TIM14();
    fn TIM15();
    fn TIM16();
    fn TIM17();
    fn TIM18();
    fn TIM19();
    fn TIM20();
    fn TIM21();
    fn TIM22();
    fn TIM23();
    fn CAN0();
    fn U73();
    fn CAN1();
    fn U75();
    fn EDAC_MBE();
    fn EDAC_SBE();
    fn PORTA0();
    fn PORTA1();
    fn PORTA2();
    fn PORTA3();
    fn PORTA4();
    fn PORTA5();
    fn PORTA6();
    fn PORTA7();
    fn PORTA8();
    fn PORTA9();
    fn PORTA10();
    fn PORTA11();
    fn PORTA12();
    fn PORTA13();
    fn PORTA14();
    fn PORTA15();
    fn PORTB0();
    fn PORTB1();
    fn PORTB2();
    fn PORTB3();
    fn PORTB4();
    fn PORTB5();
    fn PORTB6();
    fn PORTB7();
    fn PORTB8();
    fn PORTB9();
    fn PORTB10();
    fn PORTB11();
    fn PORTB12();
    fn PORTB13();
    fn PORTB14();
    fn PORTB15();
    fn PORTC0();
    fn PORTC1();
    fn PORTC2();
    fn PORTC3();
    fn PORTC4();
    fn PORTC5();
    fn PORTC6();
    fn PORTC7();
    fn PORTC8();
    fn PORTC9();
    fn PORTC10();
    fn PORTC11();
    fn PORTC12();
    fn PORTC13();
    fn PORTC14();
    fn PORTC15();
    fn PORTD0();
    fn PORTD1();
    fn PORTD2();
    fn PORTD3();
    fn PORTD4();
    fn PORTD5();
    fn PORTD6();
    fn PORTD7();
    fn PORTD8();
    fn PORTD9();
    fn PORTD10();
    fn PORTD11();
    fn PORTD12();
    fn PORTD13();
    fn PORTD14();
    fn PORTD15();
    fn PORTE0();
    fn PORTE1();
    fn PORTE2();
    fn PORTE3();
    fn PORTE4();
    fn PORTE5();
    fn PORTE6();
    fn PORTE7();
    fn PORTE8();
    fn PORTE9();
    fn PORTE10();
    fn PORTE11();
    fn PORTE12();
    fn PORTE13();
    fn PORTE14();
    fn PORTE15();
    fn PORTF0();
    fn PORTF1();
    fn PORTF2();
    fn PORTF3();
    fn PORTF4();
    fn PORTF5();
    fn PORTF6();
    fn PORTF7();
    fn PORTF8();
    fn PORTF9();
    fn PORTF10();
    fn PORTF11();
    fn PORTF12();
    fn PORTF13();
    fn PORTF14();
    fn PORTF15();
    fn DMA_ACTIVE0();
    fn DMA_ACTIVE1();
    fn DMA_ACTIVE2();
    fn DMA_ACTIVE3();
    fn DMA_DONE0();
    fn DMA_DONE1();
    fn DMA_DONE2();
    fn DMA_DONE3();
    fn I2C0_MS_RX();
    fn I2C0_MS_TX();
    fn I2C0_SL_RX();
    fn I2C0_SL_TX();
    fn I2C1_MS_RX();
    fn I2C1_MS_TX();
    fn I2C1_SL_RX();
    fn I2C1_SL_TX();
    fn I2C2_MS_RX();
    fn I2C2_MS_TX();
    fn I2C2_SL_RX();
    fn I2C2_SL_TX();
    fn FPU();
    fn TXEV();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    _handler: unsafe extern "C" fn(),
    _reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 196] = [
    Vector { _handler: U0 },
    Vector { _handler: U1 },
    Vector { _handler: U2 },
    Vector { _handler: U3 },
    Vector { _handler: U4 },
    Vector { _handler: U5 },
    Vector { _handler: U6 },
    Vector { _handler: U7 },
    Vector { _handler: U8 },
    Vector { _handler: U9 },
    Vector { _handler: U10 },
    Vector { _handler: U11 },
    Vector { _handler: U12 },
    Vector { _handler: U13 },
    Vector { _handler: U14 },
    Vector { _handler: U15 },
    Vector { _handler: SPI0_TX },
    Vector { _handler: SPI0_RX },
    Vector { _handler: SPI1_TX },
    Vector { _handler: SPI1_RX },
    Vector { _handler: SPI2_TX },
    Vector { _handler: SPI2_RX },
    Vector { _handler: SPI3_TX },
    Vector { _handler: SPI3_RX },
    Vector { _handler: UART0_TX },
    Vector { _handler: UART0_RX },
    Vector { _handler: UART1_TX },
    Vector { _handler: UART1_RX },
    Vector { _handler: UART2_TX },
    Vector { _handler: UART2_RX },
    Vector { _handler: I2C0_MS },
    Vector { _handler: I2C0_SL },
    Vector { _handler: I2C1_MS },
    Vector { _handler: I2C1_SL },
    Vector { _handler: I2C2_MS },
    Vector { _handler: I2C2_SL },
    Vector { _handler: Ethernet },
    Vector { _handler: U37 },
    Vector { _handler: SpW },
    Vector { _handler: U39 },
    Vector { _handler: DAC0 },
    Vector { _handler: DAC1 },
    Vector { _handler: TRNG },
    Vector {
        _handler: DMA_ERROR,
    },
    Vector { _handler: ADC },
    Vector { _handler: LoCLK },
    Vector { _handler: LVD },
    Vector { _handler: WATCHDOG },
    Vector { _handler: TIM0 },
    Vector { _handler: TIM1 },
    Vector { _handler: TIM2 },
    Vector { _handler: TIM3 },
    Vector { _handler: TIM4 },
    Vector { _handler: TIM5 },
    Vector { _handler: TIM6 },
    Vector { _handler: TIM7 },
    Vector { _handler: TIM8 },
    Vector { _handler: TIM9 },
    Vector { _handler: TIM10 },
    Vector { _handler: TIM11 },
    Vector { _handler: TIM12 },
    Vector { _handler: TIM13 },
    Vector { _handler: TIM14 },
    Vector { _handler: TIM15 },
    Vector { _handler: TIM16 },
    Vector { _handler: TIM17 },
    Vector { _handler: TIM18 },
    Vector { _handler: TIM19 },
    Vector { _handler: TIM20 },
    Vector { _handler: TIM21 },
    Vector { _handler: TIM22 },
    Vector { _handler: TIM23 },
    Vector { _handler: CAN0 },
    Vector { _handler: U73 },
    Vector { _handler: CAN1 },
    Vector { _handler: U75 },
    Vector { _handler: EDAC_MBE },
    Vector { _handler: EDAC_SBE },
    Vector { _handler: PORTA0 },
    Vector { _handler: PORTA1 },
    Vector { _handler: PORTA2 },
    Vector { _handler: PORTA3 },
    Vector { _handler: PORTA4 },
    Vector { _handler: PORTA5 },
    Vector { _handler: PORTA6 },
    Vector { _handler: PORTA7 },
    Vector { _handler: PORTA8 },
    Vector { _handler: PORTA9 },
    Vector { _handler: PORTA10 },
    Vector { _handler: PORTA11 },
    Vector { _handler: PORTA12 },
    Vector { _handler: PORTA13 },
    Vector { _handler: PORTA14 },
    Vector { _handler: PORTA15 },
    Vector { _handler: PORTB0 },
    Vector { _handler: PORTB1 },
    Vector { _handler: PORTB2 },
    Vector { _handler: PORTB3 },
    Vector { _handler: PORTB4 },
    Vector { _handler: PORTB5 },
    Vector { _handler: PORTB6 },
    Vector { _handler: PORTB7 },
    Vector { _handler: PORTB8 },
    Vector { _handler: PORTB9 },
    Vector { _handler: PORTB10 },
    Vector { _handler: PORTB11 },
    Vector { _handler: PORTB12 },
    Vector { _handler: PORTB13 },
    Vector { _handler: PORTB14 },
    Vector { _handler: PORTB15 },
    Vector { _handler: PORTC0 },
    Vector { _handler: PORTC1 },
    Vector { _handler: PORTC2 },
    Vector { _handler: PORTC3 },
    Vector { _handler: PORTC4 },
    Vector { _handler: PORTC5 },
    Vector { _handler: PORTC6 },
    Vector { _handler: PORTC7 },
    Vector { _handler: PORTC8 },
    Vector { _handler: PORTC9 },
    Vector { _handler: PORTC10 },
    Vector { _handler: PORTC11 },
    Vector { _handler: PORTC12 },
    Vector { _handler: PORTC13 },
    Vector { _handler: PORTC14 },
    Vector { _handler: PORTC15 },
    Vector { _handler: PORTD0 },
    Vector { _handler: PORTD1 },
    Vector { _handler: PORTD2 },
    Vector { _handler: PORTD3 },
    Vector { _handler: PORTD4 },
    Vector { _handler: PORTD5 },
    Vector { _handler: PORTD6 },
    Vector { _handler: PORTD7 },
    Vector { _handler: PORTD8 },
    Vector { _handler: PORTD9 },
    Vector { _handler: PORTD10 },
    Vector { _handler: PORTD11 },
    Vector { _handler: PORTD12 },
    Vector { _handler: PORTD13 },
    Vector { _handler: PORTD14 },
    Vector { _handler: PORTD15 },
    Vector { _handler: PORTE0 },
    Vector { _handler: PORTE1 },
    Vector { _handler: PORTE2 },
    Vector { _handler: PORTE3 },
    Vector { _handler: PORTE4 },
    Vector { _handler: PORTE5 },
    Vector { _handler: PORTE6 },
    Vector { _handler: PORTE7 },
    Vector { _handler: PORTE8 },
    Vector { _handler: PORTE9 },
    Vector { _handler: PORTE10 },
    Vector { _handler: PORTE11 },
    Vector { _handler: PORTE12 },
    Vector { _handler: PORTE13 },
    Vector { _handler: PORTE14 },
    Vector { _handler: PORTE15 },
    Vector { _handler: PORTF0 },
    Vector { _handler: PORTF1 },
    Vector { _handler: PORTF2 },
    Vector { _handler: PORTF3 },
    Vector { _handler: PORTF4 },
    Vector { _handler: PORTF5 },
    Vector { _handler: PORTF6 },
    Vector { _handler: PORTF7 },
    Vector { _handler: PORTF8 },
    Vector { _handler: PORTF9 },
    Vector { _handler: PORTF10 },
    Vector { _handler: PORTF11 },
    Vector { _handler: PORTF12 },
    Vector { _handler: PORTF13 },
    Vector { _handler: PORTF14 },
    Vector { _handler: PORTF15 },
    Vector {
        _handler: DMA_ACTIVE0,
    },
    Vector {
        _handler: DMA_ACTIVE1,
    },
    Vector {
        _handler: DMA_ACTIVE2,
    },
    Vector {
        _handler: DMA_ACTIVE3,
    },
    Vector {
        _handler: DMA_DONE0,
    },
    Vector {
        _handler: DMA_DONE1,
    },
    Vector {
        _handler: DMA_DONE2,
    },
    Vector {
        _handler: DMA_DONE3,
    },
    Vector {
        _handler: I2C0_MS_RX,
    },
    Vector {
        _handler: I2C0_MS_TX,
    },
    Vector {
        _handler: I2C0_SL_RX,
    },
    Vector {
        _handler: I2C0_SL_TX,
    },
    Vector {
        _handler: I2C1_MS_RX,
    },
    Vector {
        _handler: I2C1_MS_TX,
    },
    Vector {
        _handler: I2C1_SL_RX,
    },
    Vector {
        _handler: I2C1_SL_TX,
    },
    Vector {
        _handler: I2C2_MS_RX,
    },
    Vector {
        _handler: I2C2_MS_TX,
    },
    Vector {
        _handler: I2C2_SL_RX,
    },
    Vector {
        _handler: I2C2_SL_TX,
    },
    Vector { _handler: FPU },
    Vector { _handler: TXEV },
];
#[doc = r"Enumeration of all the interrupts."]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
    #[doc = "0 - U0"]
    U0 = 0,
    #[doc = "1 - U1"]
    U1 = 1,
    #[doc = "2 - U2"]
    U2 = 2,
    #[doc = "3 - U3"]
    U3 = 3,
    #[doc = "4 - U4"]
    U4 = 4,
    #[doc = "5 - U5"]
    U5 = 5,
    #[doc = "6 - U6"]
    U6 = 6,
    #[doc = "7 - U7"]
    U7 = 7,
    #[doc = "8 - U8"]
    U8 = 8,
    #[doc = "9 - U9"]
    U9 = 9,
    #[doc = "10 - U10"]
    U10 = 10,
    #[doc = "11 - U11"]
    U11 = 11,
    #[doc = "12 - U12"]
    U12 = 12,
    #[doc = "13 - U13"]
    U13 = 13,
    #[doc = "14 - U14"]
    U14 = 14,
    #[doc = "15 - U15"]
    U15 = 15,
    #[doc = "16 - SPI0_TX"]
    SPI0_TX = 16,
    #[doc = "17 - SPI0_RX"]
    SPI0_RX = 17,
    #[doc = "18 - SPI1_TX"]
    SPI1_TX = 18,
    #[doc = "19 - SPI1_RX"]
    SPI1_RX = 19,
    #[doc = "20 - SPI2_TX"]
    SPI2_TX = 20,
    #[doc = "21 - SPI2_RX"]
    SPI2_RX = 21,
    #[doc = "22 - SPI3_TX"]
    SPI3_TX = 22,
    #[doc = "23 - SPI3_RX"]
    SPI3_RX = 23,
    #[doc = "24 - UART0_TX"]
    UART0_TX = 24,
    #[doc = "25 - UART0_RX"]
    UART0_RX = 25,
    #[doc = "26 - UART1_TX"]
    UART1_TX = 26,
    #[doc = "27 - UART1_RX"]
    UART1_RX = 27,
    #[doc = "28 - UART2_TX"]
    UART2_TX = 28,
    #[doc = "29 - UART2_RX"]
    UART2_RX = 29,
    #[doc = "30 - I2C0_MS"]
    I2C0_MS = 30,
    #[doc = "31 - I2C0_SL"]
    I2C0_SL = 31,
    #[doc = "32 - I2C1_MS"]
    I2C1_MS = 32,
    #[doc = "33 - I2C1_SL"]
    I2C1_SL = 33,
    #[doc = "34 - I2C2_MS"]
    I2C2_MS = 34,
    #[doc = "35 - I2C2_SL"]
    I2C2_SL = 35,
    #[doc = "36 - Ethernet"]
    Ethernet = 36,
    #[doc = "37 - U37"]
    U37 = 37,
    #[doc = "38 - SpW"]
    SpW = 38,
    #[doc = "39 - U39"]
    U39 = 39,
    #[doc = "40 - DAC0"]
    DAC0 = 40,
    #[doc = "41 - DAC1"]
    DAC1 = 41,
    #[doc = "42 - TRNG"]
    TRNG = 42,
    #[doc = "43 - DMA_ERROR"]
    DMA_ERROR = 43,
    #[doc = "44 - ADC"]
    ADC = 44,
    #[doc = "45 - LoCLK"]
    LoCLK = 45,
    #[doc = "46 - LVD"]
    LVD = 46,
    #[doc = "47 - WATCHDOG"]
    WATCHDOG = 47,
    #[doc = "48 - TIM0"]
    TIM0 = 48,
    #[doc = "49 - TIM1"]
    TIM1 = 49,
    #[doc = "50 - TIM2"]
    TIM2 = 50,
    #[doc = "51 - TIM3"]
    TIM3 = 51,
    #[doc = "52 - TIM4"]
    TIM4 = 52,
    #[doc = "53 - TIM5"]
    TIM5 = 53,
    #[doc = "54 - TIM6"]
    TIM6 = 54,
    #[doc = "55 - TIM7"]
    TIM7 = 55,
    #[doc = "56 - TIM8"]
    TIM8 = 56,
    #[doc = "57 - TIM9"]
    TIM9 = 57,
    #[doc = "58 - TIM10"]
    TIM10 = 58,
    #[doc = "59 - TIM11"]
    TIM11 = 59,
    #[doc = "60 - TIM12"]
    TIM12 = 60,
    #[doc = "61 - TIM13"]
    TIM13 = 61,
    #[doc = "62 - TIM14"]
    TIM14 = 62,
    #[doc = "63 - TIM15"]
    TIM15 = 63,
    #[doc = "64 - TIM16"]
    TIM16 = 64,
    #[doc = "65 - TIM17"]
    TIM17 = 65,
    #[doc = "66 - TIM18"]
    TIM18 = 66,
    #[doc = "67 - TIM19"]
    TIM19 = 67,
    #[doc = "68 - TIM20"]
    TIM20 = 68,
    #[doc = "69 - TIM21"]
    TIM21 = 69,
    #[doc = "70 - TIM22"]
    TIM22 = 70,
    #[doc = "71 - TIM23"]
    TIM23 = 71,
    #[doc = "72 - CAN0"]
    CAN0 = 72,
    #[doc = "73 - U73"]
    U73 = 73,
    #[doc = "74 - CAN1"]
    CAN1 = 74,
    #[doc = "75 - U75"]
    U75 = 75,
    #[doc = "76 - EDAC_MBE"]
    EDAC_MBE = 76,
    #[doc = "77 - EDAC_SBE"]
    EDAC_SBE = 77,
    #[doc = "78 - PORTA0"]
    PORTA0 = 78,
    #[doc = "79 - PORTA1"]
    PORTA1 = 79,
    #[doc = "80 - PORTA2"]
    PORTA2 = 80,
    #[doc = "81 - PORTA3"]
    PORTA3 = 81,
    #[doc = "82 - PORTA4"]
    PORTA4 = 82,
    #[doc = "83 - PORTA5"]
    PORTA5 = 83,
    #[doc = "84 - PORTA6"]
    PORTA6 = 84,
    #[doc = "85 - PORTA7"]
    PORTA7 = 85,
    #[doc = "86 - PORTA8"]
    PORTA8 = 86,
    #[doc = "87 - PORTA9"]
    PORTA9 = 87,
    #[doc = "88 - PORTA10"]
    PORTA10 = 88,
    #[doc = "89 - PORTA11"]
    PORTA11 = 89,
    #[doc = "90 - PORTA12"]
    PORTA12 = 90,
    #[doc = "91 - PORTA13"]
    PORTA13 = 91,
    #[doc = "92 - PORTA14"]
    PORTA14 = 92,
    #[doc = "93 - PORTA15"]
    PORTA15 = 93,
    #[doc = "94 - PORTB0"]
    PORTB0 = 94,
    #[doc = "95 - PORTB1"]
    PORTB1 = 95,
    #[doc = "96 - PORTB2"]
    PORTB2 = 96,
    #[doc = "97 - PORTB3"]
    PORTB3 = 97,
    #[doc = "98 - PORTB4"]
    PORTB4 = 98,
    #[doc = "99 - PORTB5"]
    PORTB5 = 99,
    #[doc = "100 - PORTB6"]
    PORTB6 = 100,
    #[doc = "101 - PORTB7"]
    PORTB7 = 101,
    #[doc = "102 - PORTB8"]
    PORTB8 = 102,
    #[doc = "103 - PORTB9"]
    PORTB9 = 103,
    #[doc = "104 - PORTB10"]
    PORTB10 = 104,
    #[doc = "105 - PORTB11"]
    PORTB11 = 105,
    #[doc = "106 - PORTB12"]
    PORTB12 = 106,
    #[doc = "107 - PORTB13"]
    PORTB13 = 107,
    #[doc = "108 - PORTB14"]
    PORTB14 = 108,
    #[doc = "109 - PORTB15"]
    PORTB15 = 109,
    #[doc = "110 - PORTC0"]
    PORTC0 = 110,
    #[doc = "111 - PORTC1"]
    PORTC1 = 111,
    #[doc = "112 - PORTC2"]
    PORTC2 = 112,
    #[doc = "113 - PORTC3"]
    PORTC3 = 113,
    #[doc = "114 - PORTC4"]
    PORTC4 = 114,
    #[doc = "115 - PORTC5"]
    PORTC5 = 115,
    #[doc = "116 - PORTC6"]
    PORTC6 = 116,
    #[doc = "117 - PORTC7"]
    PORTC7 = 117,
    #[doc = "118 - PORTC8"]
    PORTC8 = 118,
    #[doc = "119 - PORTC9"]
    PORTC9 = 119,
    #[doc = "120 - PORTC10"]
    PORTC10 = 120,
    #[doc = "121 - PORTC11"]
    PORTC11 = 121,
    #[doc = "122 - PORTC12"]
    PORTC12 = 122,
    #[doc = "123 - PORTC13"]
    PORTC13 = 123,
    #[doc = "124 - PORTC14"]
    PORTC14 = 124,
    #[doc = "125 - PORTC15"]
    PORTC15 = 125,
    #[doc = "126 - PORTD0"]
    PORTD0 = 126,
    #[doc = "127 - PORTD1"]
    PORTD1 = 127,
    #[doc = "128 - PORTD2"]
    PORTD2 = 128,
    #[doc = "129 - PORTD3"]
    PORTD3 = 129,
    #[doc = "130 - PORTD4"]
    PORTD4 = 130,
    #[doc = "131 - PORTD5"]
    PORTD5 = 131,
    #[doc = "132 - PORTD6"]
    PORTD6 = 132,
    #[doc = "133 - PORTD7"]
    PORTD7 = 133,
    #[doc = "134 - PORTD8"]
    PORTD8 = 134,
    #[doc = "135 - PORTD9"]
    PORTD9 = 135,
    #[doc = "136 - PORTD10"]
    PORTD10 = 136,
    #[doc = "137 - PORTD11"]
    PORTD11 = 137,
    #[doc = "138 - PORTD12"]
    PORTD12 = 138,
    #[doc = "139 - PORTD13"]
    PORTD13 = 139,
    #[doc = "140 - PORTD14"]
    PORTD14 = 140,
    #[doc = "141 - PORTD15"]
    PORTD15 = 141,
    #[doc = "142 - PORTE0"]
    PORTE0 = 142,
    #[doc = "143 - PORTE1"]
    PORTE1 = 143,
    #[doc = "144 - PORTE2"]
    PORTE2 = 144,
    #[doc = "145 - PORTE3"]
    PORTE3 = 145,
    #[doc = "146 - PORTE4"]
    PORTE4 = 146,
    #[doc = "147 - PORTE5"]
    PORTE5 = 147,
    #[doc = "148 - PORTE6"]
    PORTE6 = 148,
    #[doc = "149 - PORTE7"]
    PORTE7 = 149,
    #[doc = "150 - PORTE8"]
    PORTE8 = 150,
    #[doc = "151 - PORTE9"]
    PORTE9 = 151,
    #[doc = "152 - PORTE10"]
    PORTE10 = 152,
    #[doc = "153 - PORTE11"]
    PORTE11 = 153,
    #[doc = "154 - PORTE12"]
    PORTE12 = 154,
    #[doc = "155 - PORTE13"]
    PORTE13 = 155,
    #[doc = "156 - PORTE14"]
    PORTE14 = 156,
    #[doc = "157 - PORTE15"]
    PORTE15 = 157,
    #[doc = "158 - PORTF0"]
    PORTF0 = 158,
    #[doc = "159 - PORTF1"]
    PORTF1 = 159,
    #[doc = "160 - PORTF2"]
    PORTF2 = 160,
    #[doc = "161 - PORTF3"]
    PORTF3 = 161,
    #[doc = "162 - PORTF4"]
    PORTF4 = 162,
    #[doc = "163 - PORTF5"]
    PORTF5 = 163,
    #[doc = "164 - PORTF6"]
    PORTF6 = 164,
    #[doc = "165 - PORTF7"]
    PORTF7 = 165,
    #[doc = "166 - PORTF8"]
    PORTF8 = 166,
    #[doc = "167 - PORTF9"]
    PORTF9 = 167,
    #[doc = "168 - PORTF10"]
    PORTF10 = 168,
    #[doc = "169 - PORTF11"]
    PORTF11 = 169,
    #[doc = "170 - PORTF12"]
    PORTF12 = 170,
    #[doc = "171 - PORTF13"]
    PORTF13 = 171,
    #[doc = "172 - PORTF14"]
    PORTF14 = 172,
    #[doc = "173 - PORTF15"]
    PORTF15 = 173,
    #[doc = "174 - DMA_ACTIVE0"]
    DMA_ACTIVE0 = 174,
    #[doc = "175 - DMA_ACTIVE1"]
    DMA_ACTIVE1 = 175,
    #[doc = "176 - DMA_ACTIVE2"]
    DMA_ACTIVE2 = 176,
    #[doc = "177 - DMA_ACTIVE3"]
    DMA_ACTIVE3 = 177,
    #[doc = "178 - DMA_DONE0"]
    DMA_DONE0 = 178,
    #[doc = "179 - DMA_DONE1"]
    DMA_DONE1 = 179,
    #[doc = "180 - DMA_DONE2"]
    DMA_DONE2 = 180,
    #[doc = "181 - DMA_DONE3"]
    DMA_DONE3 = 181,
    #[doc = "182 - I2C0_MS_RX"]
    I2C0_MS_RX = 182,
    #[doc = "183 - I2C0_MS_TX"]
    I2C0_MS_TX = 183,
    #[doc = "184 - I2C0_SL_RX"]
    I2C0_SL_RX = 184,
    #[doc = "185 - I2C0_SL_TX"]
    I2C0_SL_TX = 185,
    #[doc = "186 - I2C1_MS_RX"]
    I2C1_MS_RX = 186,
    #[doc = "187 - I2C1_MS_TX"]
    I2C1_MS_TX = 187,
    #[doc = "188 - I2C1_SL_RX"]
    I2C1_SL_RX = 188,
    #[doc = "189 - I2C1_SL_TX"]
    I2C1_SL_TX = 189,
    #[doc = "190 - I2C2_MS_RX"]
    I2C2_MS_RX = 190,
    #[doc = "191 - I2C2_MS_TX"]
    I2C2_MS_TX = 191,
    #[doc = "192 - I2C2_SL_RX"]
    I2C2_SL_RX = 192,
    #[doc = "193 - I2C2_SL_TX"]
    I2C2_SL_TX = 193,
    #[doc = "194 - FPU"]
    FPU = 194,
    #[doc = "195 - TXEV"]
    TXEV = 195,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
    #[inline(always)]
    fn number(self) -> u16 {
        self as u16
    }
}
#[doc = "Clock Generation Peripheral"]
pub type Clkgen = crate::Periph<clkgen::RegisterBlock, 0x4000_6000>;
impl core::fmt::Debug for Clkgen {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Clkgen").finish()
    }
}
#[doc = "Clock Generation Peripheral"]
pub mod clkgen;
#[doc = "System Configuration Peripheral"]
pub type Sysconfig = crate::Periph<sysconfig::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for Sysconfig {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Sysconfig").finish()
    }
}
#[doc = "System Configuration Peripheral"]
pub mod sysconfig;
#[doc = "DMA Controller Block"]
pub type Dma = crate::Periph<dma::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for Dma {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Dma").finish()
    }
}
#[doc = "DMA Controller Block"]
pub mod dma;
#[doc = "IO Pin Configuration Peripheral"]
pub type Ioconfig = crate::Periph<ioconfig::RegisterBlock, 0x4001_1000>;
impl core::fmt::Debug for Ioconfig {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Ioconfig").finish()
    }
}
#[doc = "IO Pin Configuration Peripheral"]
pub mod ioconfig;
#[doc = "Utility Peripheral"]
pub type Utility = crate::Periph<utility::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for Utility {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Utility").finish()
    }
}
#[doc = "Utility Peripheral"]
pub mod utility;
#[doc = "GPIO Peripheral"]
pub type Porta = crate::Periph<porta::RegisterBlock, 0x4001_2000>;
impl core::fmt::Debug for Porta {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Porta").finish()
    }
}
#[doc = "GPIO Peripheral"]
pub mod porta;
#[doc = "GPIO Peripheral"]
pub type Portb = crate::Periph<porta::RegisterBlock, 0x4001_2400>;
impl core::fmt::Debug for Portb {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Portb").finish()
    }
}
#[doc = "GPIO Peripheral"]
pub use self::porta as portb;
#[doc = "GPIO Peripheral"]
pub type Portc = crate::Periph<porta::RegisterBlock, 0x4001_2800>;
impl core::fmt::Debug for Portc {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Portc").finish()
    }
}
#[doc = "GPIO Peripheral"]
pub use self::porta as portc;
#[doc = "GPIO Peripheral"]
pub type Portd = crate::Periph<porta::RegisterBlock, 0x4001_2c00>;
impl core::fmt::Debug for Portd {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Portd").finish()
    }
}
#[doc = "GPIO Peripheral"]
pub use self::porta as portd;
#[doc = "GPIO Peripheral"]
pub type Porte = crate::Periph<porta::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for Porte {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Porte").finish()
    }
}
#[doc = "GPIO Peripheral"]
pub use self::porta as porte;
#[doc = "GPIO Peripheral"]
pub type Portf = crate::Periph<porta::RegisterBlock, 0x4001_3400>;
impl core::fmt::Debug for Portf {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Portf").finish()
    }
}
#[doc = "GPIO Peripheral"]
pub use self::porta as portf;
#[doc = "GPIO Peripheral"]
pub type Portg = crate::Periph<porta::RegisterBlock, 0x4001_3800>;
impl core::fmt::Debug for Portg {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Portg").finish()
    }
}
#[doc = "GPIO Peripheral"]
pub use self::porta as portg;
#[doc = "Timer/Counter Peripheral"]
pub type Tim0 = crate::Periph<tim0::RegisterBlock, 0x4001_8000>;
impl core::fmt::Debug for Tim0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim0").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub mod tim0;
#[doc = "Timer/Counter Peripheral"]
pub type Tim1 = crate::Periph<tim0::RegisterBlock, 0x4001_8400>;
impl core::fmt::Debug for Tim1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim1").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim1;
#[doc = "Timer/Counter Peripheral"]
pub type Tim2 = crate::Periph<tim0::RegisterBlock, 0x4001_8800>;
impl core::fmt::Debug for Tim2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim2").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim2;
#[doc = "Timer/Counter Peripheral"]
pub type Tim3 = crate::Periph<tim0::RegisterBlock, 0x4001_8c00>;
impl core::fmt::Debug for Tim3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim3").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim3;
#[doc = "Timer/Counter Peripheral"]
pub type Tim4 = crate::Periph<tim0::RegisterBlock, 0x4001_9000>;
impl core::fmt::Debug for Tim4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim4").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim4;
#[doc = "Timer/Counter Peripheral"]
pub type Tim5 = crate::Periph<tim0::RegisterBlock, 0x4001_9400>;
impl core::fmt::Debug for Tim5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim5").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim5;
#[doc = "Timer/Counter Peripheral"]
pub type Tim6 = crate::Periph<tim0::RegisterBlock, 0x4001_9800>;
impl core::fmt::Debug for Tim6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim6").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim6;
#[doc = "Timer/Counter Peripheral"]
pub type Tim7 = crate::Periph<tim0::RegisterBlock, 0x4001_9c00>;
impl core::fmt::Debug for Tim7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim7").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim7;
#[doc = "Timer/Counter Peripheral"]
pub type Tim8 = crate::Periph<tim0::RegisterBlock, 0x4001_a000>;
impl core::fmt::Debug for Tim8 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim8").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim8;
#[doc = "Timer/Counter Peripheral"]
pub type Tim9 = crate::Periph<tim0::RegisterBlock, 0x4001_a400>;
impl core::fmt::Debug for Tim9 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim9").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim9;
#[doc = "Timer/Counter Peripheral"]
pub type Tim10 = crate::Periph<tim0::RegisterBlock, 0x4001_a800>;
impl core::fmt::Debug for Tim10 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim10").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim10;
#[doc = "Timer/Counter Peripheral"]
pub type Tim11 = crate::Periph<tim0::RegisterBlock, 0x4001_ac00>;
impl core::fmt::Debug for Tim11 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim11").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim11;
#[doc = "Timer/Counter Peripheral"]
pub type Tim12 = crate::Periph<tim0::RegisterBlock, 0x4001_b000>;
impl core::fmt::Debug for Tim12 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim12").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim12;
#[doc = "Timer/Counter Peripheral"]
pub type Tim13 = crate::Periph<tim0::RegisterBlock, 0x4001_b400>;
impl core::fmt::Debug for Tim13 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim13").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim13;
#[doc = "Timer/Counter Peripheral"]
pub type Tim14 = crate::Periph<tim0::RegisterBlock, 0x4001_b800>;
impl core::fmt::Debug for Tim14 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim14").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim14;
#[doc = "Timer/Counter Peripheral"]
pub type Tim15 = crate::Periph<tim0::RegisterBlock, 0x4001_bc00>;
impl core::fmt::Debug for Tim15 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim15").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim15;
#[doc = "Timer/Counter Peripheral"]
pub type Tim16 = crate::Periph<tim0::RegisterBlock, 0x4002_8000>;
impl core::fmt::Debug for Tim16 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim16").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim16;
#[doc = "Timer/Counter Peripheral"]
pub type Tim17 = crate::Periph<tim0::RegisterBlock, 0x4002_8400>;
impl core::fmt::Debug for Tim17 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim17").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim17;
#[doc = "Timer/Counter Peripheral"]
pub type Tim18 = crate::Periph<tim0::RegisterBlock, 0x4002_8800>;
impl core::fmt::Debug for Tim18 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim18").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim18;
#[doc = "Timer/Counter Peripheral"]
pub type Tim19 = crate::Periph<tim0::RegisterBlock, 0x4002_8c00>;
impl core::fmt::Debug for Tim19 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim19").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim19;
#[doc = "Timer/Counter Peripheral"]
pub type Tim20 = crate::Periph<tim0::RegisterBlock, 0x4002_9000>;
impl core::fmt::Debug for Tim20 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim20").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim20;
#[doc = "Timer/Counter Peripheral"]
pub type Tim21 = crate::Periph<tim0::RegisterBlock, 0x4002_9400>;
impl core::fmt::Debug for Tim21 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim21").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim21;
#[doc = "Timer/Counter Peripheral"]
pub type Tim22 = crate::Periph<tim0::RegisterBlock, 0x4002_9800>;
impl core::fmt::Debug for Tim22 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim22").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim22;
#[doc = "Timer/Counter Peripheral"]
pub type Tim23 = crate::Periph<tim0::RegisterBlock, 0x4002_9c00>;
impl core::fmt::Debug for Tim23 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Tim23").finish()
    }
}
#[doc = "Timer/Counter Peripheral"]
pub use self::tim0 as tim23;
#[doc = "UART Peripheral"]
pub type Uart0 = crate::Periph<uart0::RegisterBlock, 0x4002_4000>;
impl core::fmt::Debug for Uart0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Uart0").finish()
    }
}
#[doc = "UART Peripheral"]
pub mod uart0;
#[doc = "UART Peripheral"]
pub type Uart1 = crate::Periph<uart0::RegisterBlock, 0x4002_5000>;
impl core::fmt::Debug for Uart1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Uart1").finish()
    }
}
#[doc = "UART Peripheral"]
pub use self::uart0 as uart1;
#[doc = "UART Peripheral"]
pub type Uart2 = crate::Periph<uart0::RegisterBlock, 0x4001_7000>;
impl core::fmt::Debug for Uart2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Uart2").finish()
    }
}
#[doc = "UART Peripheral"]
pub use self::uart0 as uart2;
#[doc = "SPI Peripheral"]
pub type Spi0 = crate::Periph<spi0::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for Spi0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Spi0").finish()
    }
}
#[doc = "SPI Peripheral"]
pub mod spi0;
#[doc = "SPI Peripheral"]
pub type Spi1 = crate::Periph<spi0::RegisterBlock, 0x4001_5400>;
impl core::fmt::Debug for Spi1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Spi1").finish()
    }
}
#[doc = "SPI Peripheral"]
pub use self::spi0 as spi1;
#[doc = "SPI Peripheral"]
pub type Spi2 = crate::Periph<spi0::RegisterBlock, 0x4001_5800>;
impl core::fmt::Debug for Spi2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Spi2").finish()
    }
}
#[doc = "SPI Peripheral"]
pub use self::spi0 as spi2;
#[doc = "SPI Peripheral"]
pub type Spi3 = crate::Periph<spi0::RegisterBlock, 0x4001_5c00>;
impl core::fmt::Debug for Spi3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Spi3").finish()
    }
}
#[doc = "SPI Peripheral"]
pub use self::spi0 as spi3;
#[doc = "I2C Peripheral"]
pub type I2c0 = crate::Periph<i2c0::RegisterBlock, 0x4001_6000>;
impl core::fmt::Debug for I2c0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2c0").finish()
    }
}
#[doc = "I2C Peripheral"]
pub mod i2c0;
#[doc = "I2C Peripheral"]
pub type I2c1 = crate::Periph<i2c0::RegisterBlock, 0x4001_6400>;
impl core::fmt::Debug for I2c1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2c1").finish()
    }
}
#[doc = "I2C Peripheral"]
pub use self::i2c0 as i2c1;
#[doc = "I2C Peripheral"]
pub type I2c2 = crate::Periph<i2c0::RegisterBlock, 0x4001_6800>;
impl core::fmt::Debug for I2c2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2c2").finish()
    }
}
#[doc = "I2C Peripheral"]
pub use self::i2c0 as i2c2;
#[doc = "CAN Peripheral"]
pub type Can0 = crate::Periph<can0::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for Can0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Can0").finish()
    }
}
#[doc = "CAN Peripheral"]
pub mod can0;
#[doc = "CAN Peripheral"]
pub type Can1 = crate::Periph<can0::RegisterBlock, 0x4001_4400>;
impl core::fmt::Debug for Can1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Can1").finish()
    }
}
#[doc = "CAN Peripheral"]
pub use self::can0 as can1;
#[doc = "Analog to Digital Converter Peripheral"]
pub type Adc = crate::Periph<adc::RegisterBlock, 0x4002_2000>;
impl core::fmt::Debug for Adc {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Adc").finish()
    }
}
#[doc = "Analog to Digital Converter Peripheral"]
pub mod adc;
#[doc = "Digital to Analog Converter Peripheral"]
pub type Dac0 = crate::Periph<dac0::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for Dac0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Dac0").finish()
    }
}
#[doc = "Digital to Analog Converter Peripheral"]
pub mod dac0;
#[doc = "Digital to Analog Converter Peripheral"]
pub type Dac1 = crate::Periph<dac0::RegisterBlock, 0x4002_3800>;
impl core::fmt::Debug for Dac1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Dac1").finish()
    }
}
#[doc = "Digital to Analog Converter Peripheral"]
pub use self::dac0 as dac1;
#[doc = "SpaceWire Peripheral"]
pub type Spw = crate::Periph<spw::RegisterBlock, 0x4000_3000>;
impl core::fmt::Debug for Spw {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Spw").finish()
    }
}
#[doc = "SpaceWire Peripheral"]
pub mod spw;
#[doc = "Interrupt Router Peripheral"]
pub type IrqRouter = crate::Periph<irq_router::RegisterBlock, 0x4000_2000>;
impl core::fmt::Debug for IrqRouter {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IrqRouter").finish()
    }
}
#[doc = "Interrupt Router Peripheral"]
pub mod irq_router;
#[doc = "Watchdog Block Peripheral"]
pub type WatchDog = crate::Periph<watch_dog::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for WatchDog {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WatchDog").finish()
    }
}
#[doc = "Watchdog Block Peripheral"]
pub mod watch_dog;
#[doc = "True Random Number Generator"]
pub type Trng = crate::Periph<trng::RegisterBlock, 0x4002_7000>;
impl core::fmt::Debug for Trng {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Trng").finish()
    }
}
#[doc = "True Random Number Generator"]
pub mod trng;
#[doc = "Ethernet Block"]
pub type Eth = crate::Periph<eth::RegisterBlock, 0x4000_4000>;
impl core::fmt::Debug for Eth {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("Eth").finish()
    }
}
#[doc = "Ethernet Block"]
pub mod eth;
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
    #[doc = "CLKGEN"]
    pub clkgen: Clkgen,
    #[doc = "SYSCONFIG"]
    pub sysconfig: Sysconfig,
    #[doc = "DMA"]
    pub dma: Dma,
    #[doc = "IOCONFIG"]
    pub ioconfig: Ioconfig,
    #[doc = "UTILITY"]
    pub utility: Utility,
    #[doc = "PORTA"]
    pub porta: Porta,
    #[doc = "PORTB"]
    pub portb: Portb,
    #[doc = "PORTC"]
    pub portc: Portc,
    #[doc = "PORTD"]
    pub portd: Portd,
    #[doc = "PORTE"]
    pub porte: Porte,
    #[doc = "PORTF"]
    pub portf: Portf,
    #[doc = "PORTG"]
    pub portg: Portg,
    #[doc = "TIM0"]
    pub tim0: Tim0,
    #[doc = "TIM1"]
    pub tim1: Tim1,
    #[doc = "TIM2"]
    pub tim2: Tim2,
    #[doc = "TIM3"]
    pub tim3: Tim3,
    #[doc = "TIM4"]
    pub tim4: Tim4,
    #[doc = "TIM5"]
    pub tim5: Tim5,
    #[doc = "TIM6"]
    pub tim6: Tim6,
    #[doc = "TIM7"]
    pub tim7: Tim7,
    #[doc = "TIM8"]
    pub tim8: Tim8,
    #[doc = "TIM9"]
    pub tim9: Tim9,
    #[doc = "TIM10"]
    pub tim10: Tim10,
    #[doc = "TIM11"]
    pub tim11: Tim11,
    #[doc = "TIM12"]
    pub tim12: Tim12,
    #[doc = "TIM13"]
    pub tim13: Tim13,
    #[doc = "TIM14"]
    pub tim14: Tim14,
    #[doc = "TIM15"]
    pub tim15: Tim15,
    #[doc = "TIM16"]
    pub tim16: Tim16,
    #[doc = "TIM17"]
    pub tim17: Tim17,
    #[doc = "TIM18"]
    pub tim18: Tim18,
    #[doc = "TIM19"]
    pub tim19: Tim19,
    #[doc = "TIM20"]
    pub tim20: Tim20,
    #[doc = "TIM21"]
    pub tim21: Tim21,
    #[doc = "TIM22"]
    pub tim22: Tim22,
    #[doc = "TIM23"]
    pub tim23: Tim23,
    #[doc = "UART0"]
    pub uart0: Uart0,
    #[doc = "UART1"]
    pub uart1: Uart1,
    #[doc = "UART2"]
    pub uart2: Uart2,
    #[doc = "SPI0"]
    pub spi0: Spi0,
    #[doc = "SPI1"]
    pub spi1: Spi1,
    #[doc = "SPI2"]
    pub spi2: Spi2,
    #[doc = "SPI3"]
    pub spi3: Spi3,
    #[doc = "I2C0"]
    pub i2c0: I2c0,
    #[doc = "I2C1"]
    pub i2c1: I2c1,
    #[doc = "I2C2"]
    pub i2c2: I2c2,
    #[doc = "CAN0"]
    pub can0: Can0,
    #[doc = "CAN1"]
    pub can1: Can1,
    #[doc = "ADC"]
    pub adc: Adc,
    #[doc = "DAC0"]
    pub dac0: Dac0,
    #[doc = "DAC1"]
    pub dac1: Dac1,
    #[doc = "SPW"]
    pub spw: Spw,
    #[doc = "IRQ_ROUTER"]
    pub irq_router: IrqRouter,
    #[doc = "WATCH_DOG"]
    pub watch_dog: WatchDog,
    #[doc = "TRNG"]
    pub trng: Trng,
    #[doc = "ETH"]
    pub eth: Eth,
}
impl Peripherals {
    #[doc = r" Returns all the peripherals *once*."]
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    #[doc = r" Unchecked version of `Peripherals::take`."]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Each of the returned peripherals must be used at most once."]
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            clkgen: Clkgen::steal(),
            sysconfig: Sysconfig::steal(),
            dma: Dma::steal(),
            ioconfig: Ioconfig::steal(),
            utility: Utility::steal(),
            porta: Porta::steal(),
            portb: Portb::steal(),
            portc: Portc::steal(),
            portd: Portd::steal(),
            porte: Porte::steal(),
            portf: Portf::steal(),
            portg: Portg::steal(),
            tim0: Tim0::steal(),
            tim1: Tim1::steal(),
            tim2: Tim2::steal(),
            tim3: Tim3::steal(),
            tim4: Tim4::steal(),
            tim5: Tim5::steal(),
            tim6: Tim6::steal(),
            tim7: Tim7::steal(),
            tim8: Tim8::steal(),
            tim9: Tim9::steal(),
            tim10: Tim10::steal(),
            tim11: Tim11::steal(),
            tim12: Tim12::steal(),
            tim13: Tim13::steal(),
            tim14: Tim14::steal(),
            tim15: Tim15::steal(),
            tim16: Tim16::steal(),
            tim17: Tim17::steal(),
            tim18: Tim18::steal(),
            tim19: Tim19::steal(),
            tim20: Tim20::steal(),
            tim21: Tim21::steal(),
            tim22: Tim22::steal(),
            tim23: Tim23::steal(),
            uart0: Uart0::steal(),
            uart1: Uart1::steal(),
            uart2: Uart2::steal(),
            spi0: Spi0::steal(),
            spi1: Spi1::steal(),
            spi2: Spi2::steal(),
            spi3: Spi3::steal(),
            i2c0: I2c0::steal(),
            i2c1: I2c1::steal(),
            i2c2: I2c2::steal(),
            can0: Can0::steal(),
            can1: Can1::steal(),
            adc: Adc::steal(),
            dac0: Dac0::steal(),
            dac1: Dac1::steal(),
            spw: Spw::steal(),
            irq_router: IrqRouter::steal(),
            watch_dog: WatchDog::steal(),
            trng: Trng::steal(),
            eth: Eth::steal(),
        }
    }
}
