diff --git a/vorago-shared-hal/src/spi/asynch.rs b/vorago-shared-hal/src/spi/asynch.rs
index 967b008..bf9c38b 100644
--- a/vorago-shared-hal/src/spi/asynch.rs
+++ b/vorago-shared-hal/src/spi/asynch.rs
@@ -486,7 +486,23 @@ impl<'spi> Drop for SpiFuture<'spi> {
 pub struct SpiAsync(pub super::Spi<u8>);
 
 impl SpiAsync {
-    pub fn new(spi: super::Spi<u8>) -> Self {
+    pub fn new(
+        spi: super::Spi<u8>,
+        #[cfg(feature = "vor1x")] opt_irq_cfg: Option<crate::InterruptConfig>,
+    ) -> Self {
+        #[cfg(feature = "vor1x")]
+        if let Some(irq_cfg) = opt_irq_cfg {
+            if irq_cfg.route {
+                crate::enable_peripheral_clock(crate::PeripheralSelect::Irqsel);
+                unsafe { va108xx::Irqsel::steal() }
+                    .spi(spi.id as usize)
+                    .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
+            }
+            if irq_cfg.enable_in_nvic {
+                // Safety: User has specifically configured this.
+                unsafe { crate::enable_nvic_interrupt(irq_cfg.id) };
+            }
+        }
         Self(spi)
     }