From 3055515dfdb07c852fc5620de8a5e31e7d708e06 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Thu, 23 Apr 2026 16:46:29 +0200 Subject: [PATCH] now it works --- va108xx/va108xx-hal/src/sysconfig.rs | 3 +- vorago-shared-hal/Cargo.toml | 2 +- vorago-shared-hal/src/spi/asynch.rs | 42 +++++++++++++++++----------- vorago-shared-hal/src/spi/mod.rs | 4 --- vorago-shared-hal/src/spi/regs.rs | 4 +-- 5 files changed, 31 insertions(+), 24 deletions(-) diff --git a/va108xx/va108xx-hal/src/sysconfig.rs b/va108xx/va108xx-hal/src/sysconfig.rs index bf70601..06e0aef 100644 --- a/va108xx/va108xx-hal/src/sysconfig.rs +++ b/va108xx/va108xx-hal/src/sysconfig.rs @@ -39,5 +39,6 @@ pub fn disable_ram_scrubbing() { } pub use vorago_shared_hal::sysconfig::{ - assert_peripheral_reset, disable_peripheral_clock, enable_peripheral_clock, + assert_peripheral_reset, deassert_peripheral_reset, disable_peripheral_clock, + enable_peripheral_clock, reset_peripheral_for_cycles, }; diff --git a/vorago-shared-hal/Cargo.toml b/vorago-shared-hal/Cargo.toml index 71b9662..4c8280e 100644 --- a/vorago-shared-hal/Cargo.toml +++ b/vorago-shared-hal/Cargo.toml @@ -26,7 +26,7 @@ raw-slicee = "0.1" thiserror = { version = "2", default-features = false } paste = "1" fugit = "0.3" -defmt = { version = "1", optional = true } +defmt = { version = "1" } va108xx = { version = "0.6", path = "../va108xx/va108xx", default-features = false, optional = true } va416xx = { version = "0.5", path = "../va416xx/va416xx", default-features = false, optional = true } embassy-sync = "0.7" diff --git a/vorago-shared-hal/src/spi/asynch.rs b/vorago-shared-hal/src/spi/asynch.rs index bf9c38b..829fd84 100644 --- a/vorago-shared-hal/src/spi/asynch.rs +++ b/vorago-shared-hal/src/spi/asynch.rs @@ -26,14 +26,14 @@ static DONE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2]; pub fn on_interrupt(peripheral: super::Bank) { let mut spi = unsafe { peripheral.steal_regs() }; let idx = peripheral as usize; - let interrupt_enabled = spi.read_interrupt_enable(); + let interrupt_enabled = spi.read_interrupt_control(); + let isr = spi.read_interrupt_status(); // IRQ is not related. if interrupt_enabled.raw_value() == 0 { return; } // Prevent spurious interrupts from messing with out logic here. - spi.write_interrupt_enable(InterruptControl::DISABLE_ALL); - let isr = spi.read_interrupt_status(); + spi.write_interrupt_control(InterruptControl::DISABLE_ALL); spi.write_interrupt_clear(InterruptClear::ALL); let mut context = critical_section::with(|cs| { let context_ref = TRANSFER_CONTEXTS[idx].borrow(cs); @@ -71,7 +71,7 @@ fn on_interrupt_read( }); // The FIFO still needs to be pumped. - while context.tx_progress < read_slice.len() && !spi.read_status().tx_not_full() { + while context.tx_progress < read_slice.len() && spi.read_status().tx_not_full() { spi.write_data(Data::new_with_raw_value(0)); context.tx_progress += 1; } @@ -96,7 +96,7 @@ fn on_interrupt_write( }); // Data still needs to be sent - while context.tx_progress < transfer_len && !spi.read_status().tx_not_full() { + while context.tx_progress < transfer_len && spi.read_status().tx_not_full() { spi.write_data(Data::new_with_raw_value( write_slice[context.tx_progress] as u32, )); @@ -119,7 +119,7 @@ fn on_interrupt_transfer( let transfer_len = core::cmp::max(read_len, write_len); // Send data first to avoid overwriting data that still needs to be sent. - while context.tx_progress < transfer_len && !spi.read_status().tx_not_full() { + while context.tx_progress < transfer_len && spi.read_status().tx_not_full() { if context.tx_progress < write_len { spi.write_data(Data::new_with_raw_value( write_slice[context.tx_progress] as u32, @@ -154,7 +154,7 @@ fn on_interrupt_transfer_in_place( let transfer_slice = unsafe { context.rx_slice.get_mut().unwrap() }; let transfer_len = transfer_slice.len(); // Send data first to avoid overwriting data that still needs to be sent. - while context.tx_progress < transfer_len && !spi.read_status().tx_not_full() { + while context.tx_progress < transfer_len && spi.read_status().tx_not_full() { spi.write_data(Data::new_with_raw_value( transfer_slice[context.tx_progress] as u32, )); @@ -236,10 +236,11 @@ fn unfinished_transfer( let new_trig_level = core::cmp::min(super::FIFO_DEPTH, transfer_len - rx_progress); spi.write_rx_fifo_trigger(TriggerLevel::new(u5::new(new_trig_level as u8))); // Re-enable interrupts with the new RX FIFO trigger level. - spi.write_interrupt_enable(InterruptControl::ENABLE_ALL); + spi.write_interrupt_control(InterruptControl::ENABLE_ALL); } #[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum TransferType { Read, Write, @@ -283,7 +284,7 @@ impl<'spi> SpiFuture<'spi> { let idx = bank as usize; DONE[idx].store(false, core::sync::atomic::Ordering::Relaxed); spi.regs - .write_interrupt_enable(InterruptControl::DISABLE_ALL); + .write_interrupt_control(InterruptControl::DISABLE_ALL); spi.regs.write_fifo_clear(FifoClear::ALL); spi.regs.modify_ctrl1(|v| v.with_mtxpause(true)); let write_idx = core::cmp::min(super::FIFO_DEPTH, words.len()); @@ -306,7 +307,7 @@ impl<'spi> SpiFuture<'spi> { context.rx_progress = 0; spi.regs.write_interrupt_clear(InterruptClear::ALL); spi.regs - .write_interrupt_enable(InterruptControl::ENABLE_ALL); + .write_interrupt_control(InterruptControl::ENABLE_ALL); spi.regs.modify_ctrl1(|v| v.with_mtxpause(false)); }); Self { @@ -333,7 +334,7 @@ impl<'spi> SpiFuture<'spi> { context.rx_progress = 0; spi.regs.write_interrupt_clear(InterruptClear::ALL); spi.regs - .write_interrupt_enable(InterruptControl::ENABLE_ALL); + .write_interrupt_control(InterruptControl::ENABLE_ALL); spi.regs.modify_ctrl1(|v| v.with_mtxpause(false)); }); Self { @@ -365,7 +366,7 @@ impl<'spi> SpiFuture<'spi> { context.rx_progress = 0; spi.regs.write_interrupt_clear(InterruptClear::ALL); spi.regs - .write_interrupt_enable(InterruptControl::ENABLE_ALL); + .write_interrupt_control(InterruptControl::ENABLE_ALL); spi.regs.modify_ctrl1(|v| v.with_mtxpause(false)); }); Self { @@ -396,7 +397,7 @@ impl<'spi> SpiFuture<'spi> { context.rx_progress = 0; spi.regs.write_interrupt_clear(InterruptClear::ALL); spi.regs - .write_interrupt_enable(InterruptControl::ENABLE_ALL); + .write_interrupt_control(InterruptControl::ENABLE_ALL); spi.regs.modify_ctrl1(|v| v.with_mtxpause(false)); }); Self { @@ -414,7 +415,7 @@ impl<'spi> SpiFuture<'spi> { let idx = bank as usize; DONE[idx].store(false, core::sync::atomic::Ordering::Relaxed); spi.regs - .write_interrupt_enable(InterruptControl::DISABLE_ALL); + .write_interrupt_control(InterruptControl::DISABLE_ALL); spi.regs.write_fifo_clear(FifoClear::ALL); spi.regs.modify_ctrl1(|v| v.with_mtxpause(true)); @@ -439,6 +440,10 @@ impl<'spi> SpiFuture<'spi> { if write_len > super::FIFO_DEPTH { spi.regs .write_tx_fifo_trigger(TriggerLevel::new(u5::new(2))); + } else { + spi.regs + .write_tx_fifo_trigger(TriggerLevel::new(u5::new(0))); + } } } @@ -473,7 +478,7 @@ impl<'spi> Drop for SpiFuture<'spi> { self.spi.regs.write_interrupt_clear(InterruptClear::ALL); self.spi .regs - .write_interrupt_enable(InterruptControl::DISABLE_ALL); + .write_interrupt_control(InterruptControl::DISABLE_ALL); self.spi.regs.write_fifo_clear(FifoClear::ALL); } } @@ -487,11 +492,14 @@ pub struct SpiAsync(pub super::Spi); impl SpiAsync { pub fn new( - spi: super::Spi, + mut spi: super::Spi, #[cfg(feature = "vor1x")] opt_irq_cfg: Option, ) -> Self { #[cfg(feature = "vor1x")] if let Some(irq_cfg) = opt_irq_cfg { + spi.regs + .write_interrupt_control(InterruptControl::DISABLE_ALL); + spi.regs.write_interrupt_clear(InterruptClear::ALL); if irq_cfg.route { crate::enable_peripheral_clock(crate::PeripheralSelect::Irqsel); unsafe { va108xx::Irqsel::steal() } @@ -503,6 +511,8 @@ impl SpiAsync { unsafe { crate::enable_nvic_interrupt(irq_cfg.id) }; } } + // Disable blockmode for asynchronous mode. + spi.regs.modify_ctrl1(|v| v.with_bm_stall(false).with_blockmode(false)); Self(spi) } diff --git a/vorago-shared-hal/src/spi/mod.rs b/vorago-shared-hal/src/spi/mod.rs index e97b5e9..58ef440 100644 --- a/vorago-shared-hal/src/spi/mod.rs +++ b/vorago-shared-hal/src/spi/mod.rs @@ -523,7 +523,6 @@ pub fn clk_div_for_target_clock(sys_clk: Hertz, spi_clk: Hertz) -> Option { pub struct Spi { id: Bank, regs: regs::MmioSpi<'static>, - cfg: SpiConfig, /// Fill word for read-only SPI transactions. fill_word: Word, blockmode: bool, @@ -656,7 +655,6 @@ where Spi { id: spi_sel, regs: regs::Spi::new_mmio(spi_sel), - cfg: spi_cfg, fill_word: Default::default(), bmstall: spi_cfg.bmstall, blockmode: spi_cfg.blockmode, @@ -1034,7 +1032,6 @@ impl From> for Spi { Spi { id: old_spi.id, regs: old_spi.regs, - cfg: old_spi.cfg, blockmode: old_spi.blockmode, fill_word: Default::default(), bmstall: old_spi.bmstall, @@ -1052,7 +1049,6 @@ impl From> for Spi { Spi { id: old_spi.id, regs: old_spi.regs, - cfg: old_spi.cfg, blockmode: old_spi.blockmode, fill_word: Default::default(), bmstall: old_spi.bmstall, diff --git a/vorago-shared-hal/src/spi/regs.rs b/vorago-shared-hal/src/spi/regs.rs index 1245b90..451ac3a 100644 --- a/vorago-shared-hal/src/spi/regs.rs +++ b/vorago-shared-hal/src/spi/regs.rs @@ -186,7 +186,7 @@ impl InterruptControl { #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] pub struct InterruptStatus { - /// TX FIFO count <= TX FIFO trigger level. + /// TX FIFO count < TX FIFO trigger level. #[bit(3, r)] tx: bool, /// RX FIFO count >= RX FIFO trigger level. @@ -238,7 +238,7 @@ pub struct Spi { #[mmio(PureRead)] status: Status, clkprescale: ClockPrescaler, - interrupt_enable: InterruptControl, + interrupt_control: InterruptControl, /// Raw interrupt status. #[mmio(PureRead)] interrupt_status_raw: InterruptStatus,