From e1b3abcba93c0526bdac9bf631aa18b91dd60937 Mon Sep 17 00:00:00 2001
From: Robin Mueller <robin.mueller.m@pm.me>
Date: Mon, 18 May 2026 20:25:28 +0200
Subject: [PATCH] invert Pull enum

---
 vorago-shared-hal/CHANGELOG.md         | 1 +
 vorago-shared-hal/src/ioconfig/regs.rs | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/vorago-shared-hal/CHANGELOG.md b/vorago-shared-hal/CHANGELOG.md
index c799b28..d03dfd6 100644
--- a/vorago-shared-hal/CHANGELOG.md
+++ b/vorago-shared-hal/CHANGELOG.md
@@ -26,6 +26,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Fixed
 
+- `Pull::Up` and `Pull::High` were inverted.
 - Removed HW CS pin provider implementation for PA23, PA22 and PA21, which are multi HW CS pins.
 - Added missing `AnyPin` trait impl for Multi HW CS pins.
 - Expose inner `Input` pin for `InputPinAsync`.
diff --git a/vorago-shared-hal/src/ioconfig/regs.rs b/vorago-shared-hal/src/ioconfig/regs.rs
index 6798c31..fc8883e 100644
--- a/vorago-shared-hal/src/ioconfig/regs.rs
+++ b/vorago-shared-hal/src/ioconfig/regs.rs
@@ -39,8 +39,8 @@ pub enum FilterClockSelect {
 #[bitbybit::bitenum(u1, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Pull {
-    Up = 0,
-    Down = 1,
+    Down = 0,
+    Up = 1,
 }
 
 #[derive(Debug, Eq, PartialEq)]