From c1b25115089dd29f4c7ef9f912da9d9468385d07 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Mon, 18 May 2026 20:25:28 +0200 Subject: [PATCH] invert Pull enum --- vorago-shared-hal/CHANGELOG.md | 3 ++- vorago-shared-hal/src/ioconfig/regs.rs | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/vorago-shared-hal/CHANGELOG.md b/vorago-shared-hal/CHANGELOG.md index c799b28..fb57263 100644 --- a/vorago-shared-hal/CHANGELOG.md +++ b/vorago-shared-hal/CHANGELOG.md @@ -26,6 +26,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Fixed +- `Pull::Up` and `Pull::High` were inverted. - Removed HW CS pin provider implementation for PA23, PA22 and PA21, which are multi HW CS pins. - Added missing `AnyPin` trait impl for Multi HW CS pins. - Expose inner `Input` pin for `InputPinAsync`. @@ -55,4 +56,4 @@ Init commit. [unreleased]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.2.0...HEAD [v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.1.0...v0.2.0 -[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/src/tag/v0.1.0 +[v0.1.0]: https://egit.irs.u ni-stuttgart.de/rust/vorago-shared-hal/src/tag/v0.1.0 diff --git a/vorago-shared-hal/src/ioconfig/regs.rs b/vorago-shared-hal/src/ioconfig/regs.rs index 6798c31..fc8883e 100644 --- a/vorago-shared-hal/src/ioconfig/regs.rs +++ b/vorago-shared-hal/src/ioconfig/regs.rs @@ -39,8 +39,8 @@ pub enum FilterClockSelect { #[bitbybit::bitenum(u1, exhaustive = true)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub enum Pull { - Up = 0, - Down = 1, + Down = 0, + Up = 1, } #[derive(Debug, Eq, PartialEq)]