commit d413f01d912c533e993cde5a0cf673b1dee6209c Author: Robin Mueller Date: Tue Oct 28 21:36:14 2025 +0100 Vorago Repo Unification diff --git a/.github/workflows/shared-hal.yml b/.github/workflows/shared-hal.yml new file mode 100644 index 0000000..ecafdeb --- /dev/null +++ b/.github/workflows/shared-hal.yml @@ -0,0 +1,47 @@ +name: shared-hal-ci +on: [push, pull_request] +defaults: + run: + working-directory: ./vorago-shared-hal + +jobs: + check: + name: Check build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv7em-none-eabihf, thumbv6m-none-eabi" + - run: cargo check --target thumbv7em-none-eabihf --features "vor4x, defmt" + - run: cargo check --target thumbv6m-none-eabi --features "vor1x, defmt" + + fmt: + name: Check formatting + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + - run: cargo fmt --all -- --check + + docs: + name: Check Documentation Build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@nightly + with: + targets: "thumbv7em-none-eabihf, thumbv6m-none-eabi" + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --target thumbv7em-none-eabihf --features "vor4x, defmt" + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --target thumbv6m-none-eabi --features "vor1x, defmt" + + clippy: + name: Clippy + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv7em-none-eabihf, thumbv6m-none-eabi" + - run: cargo clippy --target thumbv7em-none-eabihf --features vor4x -- -D warnings + - run: cargo clippy --target thumbv6m-none-eabi --features vor1x -- -D warnings diff --git a/.github/workflows/va108xx.yml b/.github/workflows/va108xx.yml new file mode 100644 index 0000000..4063602 --- /dev/null +++ b/.github/workflows/va108xx.yml @@ -0,0 +1,61 @@ +name: va108xx-ci +on: [push, pull_request] +defaults: + run: + working-directory: ./va108xx + +jobs: + check: + name: Check build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv6m-none-eabi" + - run: cargo check --target thumbv6m-none-eabi + - run: cargo check --target thumbv6m-none-eabi --examples + - run: cargo check -p va108xx --target thumbv6m-none-eabi --all-features + - run: cargo check -p va108xx-hal --target thumbv6m-none-eabi --features "defmt" + + test: + name: Run Tests + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + - name: Install nextest + uses: taiki-e/install-action@nextest + - run: cargo nextest run --all-features -p va108xx-hal --no-tests=pass + # I think we can skip those on an embedded crate.. + # - run: cargo test --doc -p va108xx-hal + + fmt: + name: Check formatting + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + components: rustfmt + - run: cargo fmt --all -- --check + + docs: + name: Check Documentation Build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@nightly + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx --all-features + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx-hal --all-features + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p vorago-reb1 + + clippy: + name: Clippy + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv6m-none-eabi" + - run: cargo clippy --target thumbv6m-none-eabi -- -D warnings diff --git a/.github/workflows/va416xx.yml b/.github/workflows/va416xx.yml new file mode 100644 index 0000000..b7e2e18 --- /dev/null +++ b/.github/workflows/va416xx.yml @@ -0,0 +1,59 @@ +name: va416xx-ci +on: [push, pull_request] +defaults: + run: + working-directory: ./va416xx + +jobs: + check: + name: Check build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv7em-none-eabihf" + - run: cargo check --target thumbv7em-none-eabihf + - run: cargo check --target thumbv7em-none-eabihf --examples + - run: cargo check -p va416xx --target thumbv7em-none-eabihf --all-features + - run: cargo check -p va416xx-hal --target thumbv7em-none-eabihf --features "defmt va41630" + + test: + name: Run Tests + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + - name: Install nextest + uses: taiki-e/install-action@nextest + - run: cargo nextest run --features va41630 -p va416xx-hal + # I think we can skip those on an embedded crate.. + # - run: cargo test --doc -p va108xx-hal + + fmt: + name: Check formatting + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + - run: cargo fmt --all -- --check + + docs: + name: Check Documentation Build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@nightly + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p vorago-peb1 + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va416xx-hal --features va41630 + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va416xx + + clippy: + name: Clippy + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv7em-none-eabihf" + - run: cargo clippy --target thumbv7em-none-eabihf -- -D warnings diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b0711ad --- /dev/null +++ b/.gitignore @@ -0,0 +1,7 @@ +# Generated by Cargo +# will have compiled files and executables +target/ + +# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries +# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html +Cargo.lock diff --git a/va108xx/.cargo/.gitignore b/va108xx/.cargo/.gitignore new file mode 100644 index 0000000..5b6c096 --- /dev/null +++ b/va108xx/.cargo/.gitignore @@ -0,0 +1 @@ +config.toml diff --git a/va108xx/.cargo/config.toml.template b/va108xx/.cargo/config.toml.template new file mode 100644 index 0000000..6b78b69 --- /dev/null +++ b/va108xx/.cargo/config.toml.template @@ -0,0 +1,46 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# uncomment ONE of these three option to make `cargo run` start a GDB session +# which option to pick depends on your system +# runner = "arm-none-eabi-gdb -q -x openocd.gdb" +# runner = "gdb-multiarch -q -x openocd.gdb" +# runner = "gdb -q -x openocd.gdb" +# runner = "gdb-multiarch -q -x jlink.gdb" + +runner = "probe-rs run --chip VA108xx_RAM --protocol jtag" +# runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format", "{L} {s}"] + +rustflags = [ + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", + + # LLD (shipped with the Rust toolchain) is used as the default linker + "-C", "link-arg=-Tlink.x", + + # knurling-rs tooling. If you want to use flip-link, ensure it is installed first. + "-C", "linker=flip-link", + # Unfortunately, defmt is clunky to use without probe-rs.. + "-C", "link-arg=-Tdefmt.x", + + # Can be useful for debugging. + # "-Clink-args=-Map=app.map" +] + +[build] +# Pick ONE of these compilation targets +target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) +# target = "thumbv8m.base-none-eabi" # Cortex-M23 +# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU) +# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU) + +[alias] +re = "run --example" +rb = "run --bin" +rrb = "run --release --bin" +ut = "test --target x86_64-unknown-linux-gnu" + +[env] +DEFMT_LOG = "info" diff --git a/va108xx/.gitignore b/va108xx/.gitignore new file mode 100644 index 0000000..da0771f --- /dev/null +++ b/va108xx/.gitignore @@ -0,0 +1,12 @@ +/app.map + +# These are backup files generated by rustfmt +**/*.rs.bk + +/.vscode + +# JetBrains IDEs +/.idea +*.iml + +/Embed.toml diff --git a/va108xx/.gitmodules b/va108xx/.gitmodules new file mode 100644 index 0000000..e69de29 diff --git a/va108xx/Cargo.toml b/va108xx/Cargo.toml new file mode 100644 index 0000000..966472f --- /dev/null +++ b/va108xx/Cargo.toml @@ -0,0 +1,46 @@ +[workspace] +resolver = "2" +members = [ + "vorago-reb1", + "va108xx", + "va108xx-hal", + "va108xx-embassy", + "examples/simple", + "examples/rtic", + "examples/embassy", + "board-tests", + "bootloader", + "flashloader", +] +exclude = [ + "flashloader/slot-a-blinky", + "flashloader/slot-b-blinky", +] + +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +# 1 instead of 0, the flashloader is too larger otherwise.. +# opt-level = 1 # <- +overflow-checks = true # <- + +# cargo build/run --release +[profile.release] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = 3 # <- +overflow-checks = false # <- + +[profile.small] +inherits = "release" +codegen-units = 1 +debug-assertions = false # <- +lto = true +opt-level = 'z' # <- +overflow-checks = false # <- +strip = true # Automatically strip symbols from the binary. diff --git a/va108xx/Embed.toml.template b/va108xx/Embed.toml.template new file mode 100644 index 0000000..3fc1518 --- /dev/null +++ b/va108xx/Embed.toml.template @@ -0,0 +1,12 @@ +[default.probe] +protocol = "Jtag" + +[default.general] +chip = "VA108xx_RAM" + +[default.rtt] +enabled = true + +[default.gdb] +# Whether or not a GDB server should be opened after flashing. +enabled = false diff --git a/va108xx/LICENSE-APACHE b/va108xx/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va108xx/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va108xx/NOTICE b/va108xx/NOTICE new file mode 100644 index 0000000..77d1111 --- /dev/null +++ b/va108xx/NOTICE @@ -0,0 +1,3 @@ +Rust workspace to develop code for the Vorago VA108xx family of MCUs + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va108xx/README.md b/va108xx/README.md new file mode 100644 index 0000000..8ec81a2 --- /dev/null +++ b/va108xx/README.md @@ -0,0 +1,189 @@ +[![build](https://github.com/us-irs/va108xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va108xx-rs/actions/workflows/ci.yml) + +Vorago VA108xx Rust Support +========= + +This crate collection provides support to write Rust applications for the VA108XX family +of devices. + +## List of crates + +This workspace contains the following released crates: + +- The [`va108xx`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx) PAC + crate containing basic low-level register definition. +- The [`va108xx-hal`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-hal) + HAL crate containing higher-level abstractions on top of the PAC register crate. +- The [`va108xx-embassy`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-embassy) + crate containing support for running the embassy-rs RTOS. +- The [`vorago-reb1`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1) + BSP crate containing support for the REB1 development board. + +It also contains the following helper crates: + +- The [`bootloader`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/bootloader) + crate contains a sample bootloader strongly based on the one provided by Vorago. +- The [`flashloader`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader) + crate contains a sample flashloader which is able to update the redundant images in the NVM which + is compatible to the provided bootloader as well. +- The [`board-tests`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/board-tests) + contains an application which can be used to test the libraries on the board. +- The [`examples`](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples) + folder contains various example applications crates using the HAL and the PAC. + This folder also contains dedicated example applications using the + [`RTIC`](https://rtic.rs/2/book/en/) and [`embassy`](https://github.com/embassy-rs/embassy) + native Rust RTOSes. + +The majority of the HAL implementation and the Embassy-rs support are contained in the external +[`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) crate. + +## Using the `.cargo/config.toml` file + +Use the following command to have a starting `config.toml` file + +```sh +cp .cargo/config.toml.template .cargo/config.toml +``` + +You then can adapt the `config.toml` to your needs. For example, you can configure runners +to conveniently flash with `cargo run`. + +## Using the sample VS Code files + +Use the following command to have a starting configuration for VS Code: + +```sh +cp -rT vscode .vscode +``` + +You can then adapt the files in `.vscode` to your needs. + +## Building projects + +Building an application requires the `thumbv6m-none-eabi` cross-compiler toolchain. +If you have not installed it yet, you can do so with + +```sh +rustup target add thumbv6m-none-eabi +``` + +After that, you can use `cargo build` to build the development version of the crate. +For example, you can use + +```sh +cargo build --example blinky +``` + +to build a simple blinky app. + +## Flashing, running and debugging the software + +You can use CLI or VS Code for flashing, running and debugging. + +### Using CLI with probe-rs + +Install [probe-rs](https://probe.rs/docs/getting-started/installation/) first. + +You can use `probe-rs` to run the software and display RTT log output. However, debugging does not +work yet. + +After installation, you can run the following command + +```sh +probe-rs run --chip VA108xx_RAM --protocol jtag target/thumbv6m-none-eabi/debug/examples/blinky +``` + +to flash and run the blinky program on the RAM. There is also a `VA108xx` chip target +available for persistent flashing. + +Runner configuration is available in the `.cargo/def-config.toml` file to use `probe-rs` for +convenience. `probe-rs` is also able to process and display `defmt` strings directly. + +### Using VS Code + +Assuming a working debug connection to your VA108xx board, you can debug using VS Code with +the [`Cortex-Debug` plugin](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug). +Please make sure that [`objdump-multiarch` and `nm-multiarch`](https://forums.raspberrypi.com/viewtopic.php?t=333146) +are installed as well. + +Some sample configuration files for VS code were provided and can be used by running +`cp -rT vscode .vscode` like specified above. After that, you can use `Run and Debug` +to automatically rebuild and flash your application. + +If you would like to use a custom GDB application, you can specify the gdb binary in the following +configuration variables in your `settings.json`: + +- `"cortex-debug.gdbPath"` +- `"cortex-debug.gdbPath.linux"` +- `"cortex-debug.gdbPath.windows"` +- `"cortex-debug.gdbPath.osx"` + +The provided VS Code configurations also provide an integrated RTT logger, which you can access +via the terminal at `RTT Ch:0 console`. In order for the RTT block address detection to +work properly, `objdump-multiarch` and `nm-multiarch` need to be installed. + +### Using CLI with GDB and Segger J-Link Tools + +Install the following two tools first: + +1. [SEGGER J-Link tools](https://www.segger.com/downloads/jlink/) installed +2. [gdb-multiarch](https://packages.debian.org/sid/gdb-multiarch) or similar + cross-architecture debugger installed. All commands here assume `gdb-multiarch`. + +You can build the blinky example application with the following command + +```sh +cargo build --example blinky +``` + +Start the GDB server first. The server needs to be started with a certain configuration and with +a JLink script to disable ROM protection. +For example, on Debian based system the following command can be used to do this (this command +is also run when running the `jlink-gdb.sh` script) + +```sh +JLinkGDBServer -select USB -device Cortex-M0 -endian little -if JTAG-speed auto \ + -LocalhostOnly -jtagconf -1,-1 +``` + +After this, you can flash and debug the application with the following command + +```sh +gdb-mutliarch -q -x jlink/jlink.gdb target/thumbv6m-none-eabihf/debug/examples/blinky -tui +``` + +Please note that you can automate all steps except starting the GDB server by using a cargo +runner configuration, for example with the following lines in your `.cargo/config.toml` file: + +```toml +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +runner = "gdb-multiarch -q -x jlink/jlink.gdb" +``` + +After that, you can simply use `cargo run --example blinky` to flash the blinky +example. + +### Using the RTT Viewer + +The Segger RTT viewer can be used to display log messages received from the target. The base +address for the RTT block placement is 0x10000000. It is recommended to use a search range of +0x1000 around that base address when using the RTT viewer. + +The RTT viewer will not be able to process `defmt` printouts. However, you can view the defmt +logs by [installing defmt-print](https://crates.io/crates/defmt-print) first and then running + +```sh +defmt-print -e tcp +``` + +The path of the ELF file which is being debugged needs to be specified for this to work. + +## Learning (Embedded) Rust + +If you are unfamiliar with Rust on Embedded Systems or Rust in general, the following resources +are recommended: + +- [Rust Book](https://doc.rust-lang.org/book/) +- [Embedded Rust Book](https://docs.rust-embedded.org/book/) +- [Embedded Rust Discovery](https://docs.rust-embedded.org/discovery/microbit/) +- [Awesome Embedded Rust](https://github.com/rust-embedded/awesome-embedded-rust) diff --git a/va108xx/automation/Dockerfile b/va108xx/automation/Dockerfile new file mode 100644 index 0000000..b789384 --- /dev/null +++ b/va108xx/automation/Dockerfile @@ -0,0 +1,13 @@ +# Run the following commands from root directory to build and run locally +# docker build -f automation/Dockerfile -t . +# docker run -it +FROM rust:latest +RUN apt-get update +RUN apt-get --yes upgrade +# tzdata is a dependency, won't install otherwise +ARG DEBIAN_FRONTEND=noninteractive + +RUN rustup install nightly && \ + rustup target add thumbv6m-none-eabi && \ + rustup +nightly target add thumbv6m-none-eabi && \ + rustup component add rustfmt clippy diff --git a/va108xx/automation/Jenkinsfile b/va108xx/automation/Jenkinsfile new file mode 100644 index 0000000..7b401a0 --- /dev/null +++ b/va108xx/automation/Jenkinsfile @@ -0,0 +1,45 @@ +pipeline { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + + stages { + stage('Rust Toolchain Info') { + steps { + sh 'rustc --version' + } + } + stage('Clippy') { + steps { + sh 'cargo clippy --target thumbv6m-none-eabi' + } + } + stage('Rustfmt') { + steps { + sh 'cargo fmt' + } + } + stage('Docs') { + steps { + sh """ + RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx + RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx-hal + RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p vorago-reb1 + """ + } + } + stage('Check') { + steps { + sh 'cargo check --target thumbv6m-none-eabi' + } + } + stage('Check Examples') { + steps { + sh 'cargo check --target thumbv6m-none-eabi --examples' + } + } + } +} diff --git a/va108xx/board-tests/Cargo.toml b/va108xx/board-tests/Cargo.toml new file mode 100644 index 0000000..bcfc493 --- /dev/null +++ b/va108xx/board-tests/Cargo.toml @@ -0,0 +1,18 @@ +[package] +name = "board-tests" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +cortex-m-rt = "0.7" +defmt = "1" +defmt-rtt = "1" +panic-probe = { version = "1", features = ["print-defmt"] } +embedded-hal = "1" + +[dependencies.va108xx-hal] +version = "0.12" +features = ["rt"] +path = "../va108xx-hal" + diff --git a/va108xx/board-tests/src/main.rs b/va108xx/board-tests/src/main.rs new file mode 100644 index 0000000..df708f6 --- /dev/null +++ b/va108xx/board-tests/src/main.rs @@ -0,0 +1,184 @@ +//! Test image +//! +//! It would be nice to use a test framework like defmt-test, but I have issues +//! with probe run and it would be better to make the RTT work first +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +// Logging provider +use defmt_rtt as _; +// Panic provider +use panic_probe as _; +use va108xx_hal::{ + gpio::{regs::Gpio, Input, Output, PinState, Pull}, + pac, + pins::{PinsA, PinsB, Port}, + prelude::*, + time::Hertz, + timer::CountdownTimer, +}; + +#[allow(dead_code)] +#[derive(Debug, defmt::Format)] +enum TestCase { + // Tie PORTA[0] to PORTA[1] for these tests! + TestBasic, + TestPullup, + TestPulldown, + TestMask, + // Tie PORTB[22] to PORTB[23] for this test + PortB, + Perid, + // Tie PA0 to an oscilloscope and configure pulse detection + Pulse, + // Tie PA0, PA1 and PA3 to an oscilloscope + DelayGpio, + // PA0 can be checked with an oscillsope to verify timing correctness. + DelayMs, +} + +#[entry] +fn main() -> ! { + defmt::println!("-- VA108xx Test Application --"); + let dp = pac::Peripherals::take().unwrap(); + let cp = cortex_m::Peripherals::take().unwrap(); + let pinsa = PinsA::new(dp.porta); + let pinsb = PinsB::new(dp.portb); + let mut led1 = Output::new(pinsa.pa10, PinState::Low); + let test_case = TestCase::DelayMs; + + match test_case { + TestCase::TestBasic + | TestCase::TestPulldown + | TestCase::TestPullup + | TestCase::TestMask => { + defmt::info!( + "Test case {:?}. Make sure to tie PORTA[0] to PORTA[1]", + test_case + ); + } + _ => { + defmt::info!("Test case {:?}", test_case); + } + } + match test_case { + TestCase::TestBasic => { + // Tie PORTA[0] to PORTA[1] for these tests! + let mut out = Output::new(pinsa.pa0, PinState::Low); + let input = Input::new_floating(pinsa.pa1); + out.set_high(); + assert!(input.is_high()); + out.set_low(); + assert!(input.is_low()); + } + TestCase::TestPullup => { + // Tie PORTA[0] to PORTA[1] for these tests! + let input = Input::new_with_pull(pinsa.pa1, Pull::Up); + assert!(input.is_high()); + let mut out = Output::new(pinsa.pa0, PinState::Low); + out.set_low(); + assert!(input.is_low()); + out.set_high(); + assert!(input.is_high()); + } + TestCase::TestPulldown => { + // Tie PORTA[0] to PORTA[1] for these tests! + let input = Input::new_with_pull(pinsa.pa1, Pull::Down); + assert!(input.is_low()); + let mut out = Output::new(pinsa.pa0, PinState::Low); + out.set_low(); + assert!(input.is_low()); + out.set_high(); + assert!(input.is_high()); + } + TestCase::TestMask => { + // Tie PORTA[0] to PORTA[1] for these tests! + // Need to test this low-level.. + /* + let mut input = Input::new_with_pull(pinsa.pa1, Pull::Down); + input.clear_datamask(); + assert!(!input.datamask()); + let mut out = pinsa.pa0.into_push_pull_output(); + out.clear_datamask(); + assert!(input.is_low_masked().is_err()); + assert!(out.set_high_masked().is_err()); + */ + } + TestCase::PortB => { + // Tie PORTB[22] to PORTB[23] for these tests! + let mut out = Output::new(pinsb.pb22, PinState::Low); + let input = Input::new_floating(pinsb.pb23); + out.set_high(); + assert!(input.is_high()); + out.set_low(); + assert!(input.is_low()); + } + TestCase::Perid => { + let mmio_porta = Gpio::new_mmio(Port::A); + assert_eq!(mmio_porta.read_perid(), 0x004007e1); + let mmio_porta = Gpio::new_mmio(Port::B); + assert_eq!(mmio_porta.read_perid(), 0x004007e1); + } + TestCase::Pulse => { + let mut output_pulsed = Output::new(pinsa.pa0, PinState::Low); + output_pulsed.configure_pulse_mode(true, PinState::Low); + defmt::info!("Pulsing high 10 times.."); + output_pulsed.set_low(); + for _ in 0..10 { + output_pulsed.set_high(); + cortex_m::asm::delay(25_000_000); + } + output_pulsed.configure_pulse_mode(true, PinState::High); + defmt::info!("Pulsing low 10 times.."); + for _ in 0..10 { + output_pulsed.set_low(); + cortex_m::asm::delay(25_000_000); + } + } + TestCase::DelayGpio => { + let mut out_0 = Output::new(pinsa.pa0, PinState::Low); + out_0.configure_delay(true, false); + let mut out_1 = Output::new(pinsa.pa1, PinState::Low); + out_1.configure_delay(false, true); + let mut out_2 = Output::new(pinsa.pa3, PinState::Low); + out_2.configure_delay(true, true); + for _ in 0..20 { + out_0.toggle(); + out_1.toggle(); + out_2.toggle(); + cortex_m::asm::delay(25_000_000); + } + } + TestCase::DelayMs => { + let mut delay_timer = CountdownTimer::new(dp.tim1, 50.MHz()); + let mut pa0 = Output::new(pinsa.pa0, PinState::Low); + for _ in 0..5 { + led1.toggle(); + delay_timer.delay_ms(500); + led1.toggle(); + delay_timer.delay_ms(500); + } + let ahb_freq: Hertz = 50.MHz(); + let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.raw()); + // Release image should be used to verify timings for pin PA0 + for _ in 0..5 { + pa0.toggle(); + syst_delay.delay_us(50); + pa0.toggle(); + syst_delay.delay_us(50); + pa0.toggle(); + delay_timer.delay_us(50); + pa0.toggle(); + delay_timer.delay_us(50); + } + } + } + + defmt::info!("Test success"); + loop { + led1.toggle(); + cortex_m::asm::delay(25_000_000); + } +} diff --git a/va108xx/bootloader/Cargo.toml b/va108xx/bootloader/Cargo.toml new file mode 100644 index 0000000..212e8a0 --- /dev/null +++ b/va108xx/bootloader/Cargo.toml @@ -0,0 +1,28 @@ +[package] +name = "bootloader" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +cortex-m-rt = "0.7" +embedded-hal = "1" +defmt-rtt = "1" +defmt = "1" +panic-probe = { version = "1", features = ["defmt"] } +crc = "3" +num_enum = { version = "0.7", default-features = false } +static_assertions = "1" + +[dependencies.va108xx-hal] +version = "0.12" +path = "../va108xx-hal" +features = ["defmt"] + +[dependencies.vorago-reb1] +version = "0.9" +path = "../vorago-reb1" + +[features] +default = [] +rtt-panic = [] diff --git a/va108xx/bootloader/README.md b/va108xx/bootloader/README.md new file mode 100644 index 0000000..32a1cd9 --- /dev/null +++ b/va108xx/bootloader/README.md @@ -0,0 +1,51 @@ +VA108xx Bootloader Application +======= + +This is the Rust version of the bootloader supplied by Vorago. + +## Memory Map + +The bootloader uses the following memory map: + +| Address | Notes | Size | +| ------ | ---- | ---- | +| 0x0 | Bootloader start | code up to 0x2FFE bytes | +| 0x2FFE | Bootloader CRC | half-word | +| 0x3000 | App image A start | code up to 0xE7F4 (~59K) bytes | +| 0x117F4 | App image A CRC check length | word | +| 0x117F8 | App image A CRC check value | word | +| 0x117FC | App image B start | code up to 0xE7F4 (~59K) bytes | +| 0x1FFF0 | App image B CRC check length | word | +| 0x1FFF4 | App image B CRC check value | word | +| 0x1FFF8 | Reserved section, contains boot select parameter | 8 bytes | +| 0x20000 | End of NVM | end | + +## Additional Information + +This bootloader was specifically written for the REB1 board, so it assumes a M95M01 ST EEPROM +is used to load the application code. The bootloader will also delay for a configurable amount +of time before booting. This allows to catch the RTT printout, but should probably be disabled +for production firmware. + +This bootloader does not provide tools to flash the NVM memory by itself. Instead, you can use +the [flashloader](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader) +application to perform this task using a CCSDS interface via a UART. + +The bootloader performs the following steps: + +1. The application will calculate the checksum of itself if the bootloader CRC is blank (all zeroes + or all ones). If the CRC is not blank and the checksum check fails, it will immediately boot + application image A. Otherwise, it proceeds to the next step. +2. Read the boot slot from a reserved section at the end of the EEPROM. If no valid value is read, + select boot slot A. +3. Check the checksum of the boot slot. If that checksum is valid, it will boot that slot. If not, + it will proceed to the next step. +4. Check the checksum of the other slot . If that checksum is valid, it will boot that slot. If + not, it will boot App A as the fallback image. + +In your actual production application, a command to update the preferred boot slot could be exposed +to allow performing software updates in a safe way. + +Please note that you *MUST* compile the application at slot A and slot B with an appropriate +`memory.x` file where the base address of the `FLASH` was adapted according to the base address +shown in the memory map above. The memory files to do this were provided in the `scripts` folder. diff --git a/va108xx/bootloader/src/lib.rs b/va108xx/bootloader/src/lib.rs new file mode 100644 index 0000000..24e41a6 --- /dev/null +++ b/va108xx/bootloader/src/lib.rs @@ -0,0 +1,10 @@ +#![no_std] + +use core::convert::Infallible; + +/// Simple trait which makes swapping the NVM easier. NVMs only need to implement this interface. +pub trait NvmInterface { + fn write(&mut self, address: usize, data: &[u8]) -> Result<(), Infallible>; + fn read(&mut self, address: usize, buf: &mut [u8]) -> Result<(), Infallible>; + fn verify(&mut self, address: usize, data: &[u8]) -> Result; +} diff --git a/va108xx/bootloader/src/main.rs b/va108xx/bootloader/src/main.rs new file mode 100644 index 0000000..a17bfae --- /dev/null +++ b/va108xx/bootloader/src/main.rs @@ -0,0 +1,339 @@ +//! Vorago bootloader which can boot from two images. +#![no_main] +#![no_std] +use bootloader::NvmInterface; +use cortex_m_rt::entry; +use crc::{Crc, CRC_16_IBM_3740}; +use embedded_hal::delay::DelayNs; +use num_enum::TryFromPrimitive; +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; +use va108xx_hal::{pac, spi::SpiClockConfig, time::Hertz, timer::CountdownTimer}; +use vorago_reb1::m95m01::M95M01; + +// Useful for debugging and see what the bootloader is doing. Enabled currently, because +// the binary stays small enough. +const DEFMT_PRINTOUT: bool = true; +const DEBUG_PRINTOUTS: bool = true; +// Small delay, allows RTT printout to catch up. +const BOOT_DELAY_MS: u32 = 2000; + +// Dangerous option! An image with this option set to true will flash itself from RAM directly +// into the NVM. This can be used as a recovery option from a direct RAM flash to fix the NVM +// boot process. Please note that this will flash an image which will also always perform the +// self-flash itself. It is recommended that you use a tool like probe-rs, Keil IDE, or a flash +// loader to boot a bootloader without this feature. +const FLASH_SELF: bool = false; + +// Register definitions for Cortex-M0 SCB register. +pub const SCB_AIRCR_VECTKEY_POS: u32 = 16; +pub const SCB_AIRCR_VECTKEY_MSK: u32 = 0xFFFF << SCB_AIRCR_VECTKEY_POS; + +pub const SCB_AIRCR_SYSRESETREQ_POS: u32 = 2; +pub const SCB_AIRCR_SYSRESETREQ_MSK: u32 = 1 << SCB_AIRCR_SYSRESETREQ_POS; + +const CLOCK_FREQ: Hertz = Hertz::from_raw(50_000_000); + +// Important bootloader addresses and offsets, vector table information. + +const NVM_SIZE: u32 = 0x20000; +const BOOTLOADER_START_ADDR: u32 = 0x0; +const BOOTLOADER_CRC_ADDR: u32 = BOOTLOADER_END_ADDR - 2; +// This is also the maximum size of the bootloader. +const BOOTLOADER_END_ADDR: u32 = 0x3000; +const APP_A_START_ADDR: u32 = BOOTLOADER_END_ADDR; +// 0x117F8 +const APP_A_SIZE_ADDR: u32 = APP_A_END_ADDR - 8; +// Four bytes reserved, even when only 2 byte CRC is used. Leaves flexibility to switch to CRC32. +// 0x117FC +const APP_A_CRC_ADDR: u32 = APP_A_END_ADDR - 4; +// 0x11800 +pub const APP_A_END_ADDR: u32 = APP_A_START_ADDR + APP_IMG_SZ; +// The actual size of the image which is relevant for CRC calculation. +const APP_B_START_ADDR: u32 = APP_A_END_ADDR; +// The actual size of the image which is relevant for CRC calculation. +// 0x1FFF8 +const APP_B_SIZE_ADDR: u32 = APP_B_END_ADDR - 8; +// Four bytes reserved, even when only 2 byte CRC is used. Leaves flexibility to switch to CRC32. +// 0x1FFFC +const APP_B_CRC_ADDR: u32 = APP_B_END_ADDR - 4; +// 0x20000. 8 bytes at end of EEPROM reserved for preferred image parameter. This reserved +// size should be a multiple of 8 due to alignment requirements. +pub const APP_B_END_ADDR: u32 = NVM_SIZE - 8; +pub const APP_IMG_SZ: u32 = (APP_B_END_ADDR - APP_A_START_ADDR) / 2; + +static_assertions::const_assert!((APP_B_END_ADDR - BOOTLOADER_END_ADDR) % 2 == 0); + +pub const VECTOR_TABLE_OFFSET: u32 = 0x0; +pub const VECTOR_TABLE_LEN: u32 = 0xC0; +pub const RESET_VECTOR_OFFSET: u32 = 0x4; +pub const PREFERRED_SLOT_OFFSET: u32 = 0x20000 - 1; + +const CRC_ALGO: Crc = Crc::::new(&CRC_16_IBM_3740); + +#[derive(Debug, Copy, Clone, PartialEq, Eq, TryFromPrimitive, defmt::Format)] +#[repr(u8)] +enum AppSel { + A = 0, + B = 1, +} + +pub struct NvmWrapper(pub M95M01); + +// Newtype pattern. We could now more easily swap the used NVM type. +impl NvmInterface for NvmWrapper { + fn write(&mut self, address: usize, data: &[u8]) -> Result<(), core::convert::Infallible> { + self.0.write(address, data) + } + + fn read(&mut self, address: usize, buf: &mut [u8]) -> Result<(), core::convert::Infallible> { + self.0.read(address, buf) + } + + fn verify(&mut self, address: usize, data: &[u8]) -> Result { + self.0.verify(address, data) + } +} + +#[entry] +fn main() -> ! { + if DEFMT_PRINTOUT { + defmt::println!("-- VA108xx bootloader --"); + } + let dp = pac::Peripherals::take().unwrap(); + let cp = cortex_m::Peripherals::take().unwrap(); + let mut timer = CountdownTimer::new(dp.tim0, CLOCK_FREQ); + + let clk_config = SpiClockConfig::new(2, 4); + let mut nvm = M95M01::new(dp.spic, clk_config); + + if FLASH_SELF { + let mut first_four_bytes: [u8; 4] = [0; 4]; + read_four_bytes_at_addr_zero(&mut first_four_bytes); + let bootloader_data = { + unsafe { + &*core::ptr::slice_from_raw_parts( + (BOOTLOADER_START_ADDR + 4) as *const u8, + (BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 6) as usize, + ) + } + }; + let mut digest = CRC_ALGO.digest(); + digest.update(&first_four_bytes); + digest.update(bootloader_data); + let bootloader_crc = digest.finalize(); + + nvm.write(0x0, &first_four_bytes) + .expect("writing to NVM failed"); + nvm.write(0x4, bootloader_data) + .expect("writing to NVM failed"); + if let Err(e) = nvm.verify(0x0, &first_four_bytes) { + if DEFMT_PRINTOUT { + defmt::error!("verification of self-flash to NVM failed: {:?}", e); + } + } + if let Err(e) = nvm.verify(0x4, bootloader_data) { + if DEFMT_PRINTOUT { + defmt::error!("verification of self-flash to NVM failed: {:?}", e); + } + } + + nvm.write(BOOTLOADER_CRC_ADDR as usize, &bootloader_crc.to_be_bytes()) + .expect("writing CRC failed"); + if let Err(e) = nvm.verify(BOOTLOADER_CRC_ADDR as usize, &bootloader_crc.to_be_bytes()) { + if DEFMT_PRINTOUT { + defmt::error!( + "error: CRC verification for bootloader self-flash failed: {:?}", + e + ); + } + } + } + + let mut nvm = NvmWrapper(nvm); + + // Check bootloader's CRC (and write it if blank) + check_own_crc(&dp.sysconfig, &cp, &mut nvm, &mut timer); + + let mut preferred_app_raw = [0; 1]; + nvm.read(PREFERRED_SLOT_OFFSET as usize, &mut preferred_app_raw) + .expect("reading preferred slot failed"); + let preferred_app = AppSel::try_from(preferred_app_raw[0]).unwrap_or(AppSel::A); + let other_app = if preferred_app == AppSel::A { + AppSel::B + } else { + AppSel::A + }; + + if check_app_crc(preferred_app) { + boot_app(&dp.sysconfig, &cp, preferred_app, &mut timer) + } else if check_app_crc(other_app) { + boot_app(&dp.sysconfig, &cp, other_app, &mut timer) + } else { + if DEBUG_PRINTOUTS && DEFMT_PRINTOUT { + defmt::error!("both images corrupt! booting image A"); + } + // TODO: Shift a CCSDS packet out to inform host/OBC about image corruption. + // Both images seem to be corrupt. Boot default image A. + boot_app(&dp.sysconfig, &cp, AppSel::A, &mut timer) + } +} + +fn check_own_crc( + sysconfig: &pac::Sysconfig, + cp: &cortex_m::Peripherals, + nvm: &mut NvmWrapper, + timer: &mut CountdownTimer, +) { + let crc_exp = unsafe { (BOOTLOADER_CRC_ADDR as *const u16).read_unaligned().to_be() }; + // I'd prefer to use [core::slice::from_raw_parts], but that is problematic + // because the address of the bootloader is 0x0, so the NULL check fails and the functions + // panics. + let mut first_four_bytes: [u8; 4] = [0; 4]; + read_four_bytes_at_addr_zero(&mut first_four_bytes); + let mut digest = CRC_ALGO.digest(); + digest.update(&first_four_bytes); + digest.update(unsafe { + &*core::ptr::slice_from_raw_parts( + (BOOTLOADER_START_ADDR + 4) as *const u8, + (BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 6) as usize, + ) + }); + let crc_calc = digest.finalize(); + if crc_exp == 0x0000 || crc_exp == 0xffff { + if DEBUG_PRINTOUTS && DEFMT_PRINTOUT { + defmt::info!("BL CRC blank - prog new CRC"); + } + // Blank CRC, write it to NVM. + nvm.write(BOOTLOADER_CRC_ADDR as usize, &crc_calc.to_be_bytes()) + .expect("writing CRC failed"); + // The Vorago bootloader resets here. I am not sure why this is done but I think it is + // necessary because somehow the boot will not work if we just continue as usual. + // cortex_m::peripheral::SCB::sys_reset(); + } else if crc_exp != crc_calc { + // Bootloader is corrupted. Try to run App A. + if DEBUG_PRINTOUTS && DEFMT_PRINTOUT { + defmt::warn!( + "bootloader CRC corrupt, read {} and expected {}. booting image A immediately", + crc_calc, + crc_exp + ); + } + // TODO: Shift out minimal CCSDS frame to notify about bootloader corruption. + boot_app(sysconfig, cp, AppSel::A, timer); + } +} + +// Reading from address 0x0 is problematic in Rust. +// See https://users.rust-lang.org/t/reading-from-physical-address-0x0/117408/5. +// This solution falls back to assembler to deal with this. +fn read_four_bytes_at_addr_zero(buf: &mut [u8; 4]) { + unsafe { + core::arch::asm!( + "ldr r0, [{0}]", // Load 4 bytes from src into r0 register + "str r0, [{1}]", // Store r0 register into first_four_bytes + in(reg) BOOTLOADER_START_ADDR as *const u8, // Input: src pointer (0x0) + in(reg) buf as *mut [u8; 4], // Input: destination pointer + ); + } +} +fn check_app_crc(app_sel: AppSel) -> bool { + if DEBUG_PRINTOUTS && DEFMT_PRINTOUT { + defmt::info!("Checking image {:?}", app_sel); + } + if app_sel == AppSel::A { + check_app_given_addr(APP_A_CRC_ADDR, APP_A_START_ADDR, APP_A_SIZE_ADDR) + } else { + check_app_given_addr(APP_B_CRC_ADDR, APP_B_START_ADDR, APP_B_SIZE_ADDR) + } +} + +fn check_app_given_addr(crc_addr: u32, start_addr: u32, image_size_addr: u32) -> bool { + let crc_exp = unsafe { (crc_addr as *const u16).read_unaligned().to_be() }; + let image_size = unsafe { (image_size_addr as *const u32).read_unaligned().to_be() }; + // Sanity check. + if image_size > APP_A_END_ADDR - APP_A_START_ADDR - 8 { + if DEFMT_PRINTOUT { + defmt::error!("detected invalid app size {}", image_size); + } + return false; + } + let crc_calc = CRC_ALGO.checksum(unsafe { + core::slice::from_raw_parts(start_addr as *const u8, image_size as usize) + }); + if crc_calc == crc_exp { + return true; + } + false +} + +// The boot works by copying the interrupt vector table (IVT) of the respective app to the +// base address in code RAM (0x0) and then performing a soft reset. +fn boot_app( + syscfg: &pac::Sysconfig, + cp: &cortex_m::Peripherals, + app_sel: AppSel, + timer: &mut CountdownTimer, +) -> ! { + if DEBUG_PRINTOUTS && DEFMT_PRINTOUT { + defmt::info!("booting app {:?}", app_sel); + } + timer.delay_ms(BOOT_DELAY_MS); + + // Clear all interrupts set. + unsafe { + cp.NVIC.icer[0].write(0xFFFFFFFF); + cp.NVIC.icpr[0].write(0xFFFFFFFF); + } + // Disable ROM protection. + syscfg.rom_prot().write(|w| w.wren().set_bit()); + let base_addr = if app_sel == AppSel::A { + APP_A_START_ADDR + } else { + APP_B_START_ADDR + }; + unsafe { + // First 4 bytes done with inline assembly, writing to the physical address 0x0 can not + // be done without it. See https://users.rust-lang.org/t/reading-from-physical-address-0x0/117408/2. + let first_four_bytes = core::ptr::read(base_addr as *const u32); + core::arch::asm!( + "str {0}, [{1}]", + in(reg) first_four_bytes, // Input: App vector table. + in(reg) BOOTLOADER_START_ADDR as *mut u32, // Input: destination pointer + ); + core::slice::from_raw_parts_mut( + (BOOTLOADER_START_ADDR + 4) as *mut u8, + (VECTOR_TABLE_LEN - 4) as usize, + ) + .copy_from_slice(core::slice::from_raw_parts( + (base_addr + 4) as *const u8, + (VECTOR_TABLE_LEN - 4) as usize, + )); + } + // Disable re-loading from FRAM/code ROM on soft reset + syscfg + .rst_cntl_rom() + .modify(|_, w| w.sysrstreq().clear_bit()); + + soft_reset(cp); +} + +// Soft reset based on https://github.com/ARM-software/CMSIS_6/blob/5782d6f8057906d360f4b95ec08a2354afe5c9b9/CMSIS/Core/Include/core_cm0.h#L874. +fn soft_reset(cp: &cortex_m::Peripherals) -> ! { + // Ensure all outstanding memory accesses included buffered write are completed before reset. + cortex_m::asm::dsb(); + unsafe { + cp.SCB + .aircr + .write((0x5FA << SCB_AIRCR_VECTKEY_POS) | SCB_AIRCR_SYSRESETREQ_MSK); + } + // Ensure completion of memory access. + cortex_m::asm::dsb(); + + // Loop until the reset occurs. + loop { + cortex_m::asm::nop(); + } +} diff --git a/va108xx/docs/ADT75.pdf b/va108xx/docs/ADT75.pdf new file mode 100644 index 0000000..19d4e8c Binary files /dev/null and b/va108xx/docs/ADT75.pdf differ diff --git a/va108xx/docs/ADXL343-1503782.pdf b/va108xx/docs/ADXL343-1503782.pdf new file mode 100644 index 0000000..d73ac60 Binary files /dev/null and b/va108xx/docs/ADXL343-1503782.pdf differ diff --git a/va108xx/docs/MAX11618-MAX11625.pdf b/va108xx/docs/MAX11618-MAX11625.pdf new file mode 100644 index 0000000..be13e57 Binary files /dev/null and b/va108xx/docs/MAX11618-MAX11625.pdf differ diff --git a/va108xx/docs/REB1-Development-Board/REB1_APPS_RevB_schematic_13Apr2016.pdf b/va108xx/docs/REB1-Development-Board/REB1_APPS_RevB_schematic_13Apr2016.pdf new file mode 100644 index 0000000..aaeee0d Binary files /dev/null and b/va108xx/docs/REB1-Development-Board/REB1_APPS_RevB_schematic_13Apr2016.pdf differ diff --git a/va108xx/docs/REB1-Development-Board/REB1_QSG.pdf b/va108xx/docs/REB1-Development-Board/REB1_QSG.pdf new file mode 100644 index 0000000..681e950 Binary files /dev/null and b/va108xx/docs/REB1-Development-Board/REB1_QSG.pdf differ diff --git a/va108xx/docs/REB1-Development-Board/REB1_TopView.png b/va108xx/docs/REB1-Development-Board/REB1_TopView.png new file mode 100644 index 0000000..d0e4b0b Binary files /dev/null and b/va108xx/docs/REB1-Development-Board/REB1_TopView.png differ diff --git a/va108xx/docs/REB1-Development-Board/REB1_Users_Manual_v3.0.pdf b/va108xx/docs/REB1-Development-Board/REB1_Users_Manual_v3.0.pdf new file mode 100644 index 0000000..07567cd Binary files /dev/null and b/va108xx/docs/REB1-Development-Board/REB1_Users_Manual_v3.0.pdf differ diff --git a/va108xx/docs/VA108X0_PG.pdf b/va108xx/docs/VA108X0_PG.pdf new file mode 100644 index 0000000..b6c6e64 Binary files /dev/null and b/va108xx/docs/VA108X0_PG.pdf differ diff --git a/va108xx/examples/README.md b/va108xx/examples/README.md new file mode 100644 index 0000000..9df12f4 --- /dev/null +++ b/va108xx/examples/README.md @@ -0,0 +1,33 @@ +VA108xx Example Applications +======== + +This folder contains various examples +Consult the main README first for setup of the repository. + +## Simple examples + +```rs +cargo run --example blinky +``` + +You can have a look at the `simple/examples` folder to see all available simple examples + +## RTIC example + +```rs +cargo run --bin rtic-example +``` + +## Embassy example + +Blinky with time driver IRQs in library + +```rs +cargo run --bin embassy-example +``` + +Blinky with custom time driver IRQs + +```rs +cargo run --bin embassy-example --no-default-features --features custom-irqs +``` diff --git a/va108xx/examples/embassy/Cargo.toml b/va108xx/examples/embassy/Cargo.toml new file mode 100644 index 0000000..cdf169a --- /dev/null +++ b/va108xx/examples/embassy/Cargo.toml @@ -0,0 +1,39 @@ +[package] +name = "embassy-example" +version = "0.1.0" +edition = "2021" + +[dependencies] +cfg-if = "1" +cortex-m-rt = "0.7" +embedded-hal-async = "1" +embedded-io = "0.6" +embedded-io-async = "0.6" +heapless = "0.9" +static_cell = "2" + +defmt = "1" +defmt-rtt = "1" +panic-probe = { version = "1", features = ["print-defmt"] } + +critical-section = "1" + +embassy-sync = "0.7" +embassy-time = "0.5" +embassy-executor = { version = "0.9", features = [ + "arch-cortex-m", + "executor-thread", + "executor-interrupt" +]} + +va108xx-hal = { version = "0.12", path = "../../va108xx-hal", features = ["defmt"] } +va108xx-embassy = { version = "0.3", path = "../../va108xx-embassy" } + +[features] +default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"] +custom-irqs = [] +ticks-hz-1_000 = ["embassy-time/tick-hz-1_000"] +ticks-hz-32_768 = ["embassy-time/tick-hz-32_768"] + +[package.metadata.cargo-machete] +ignored = ["cortex-m-rt"] diff --git a/va108xx/examples/embassy/src/bin/async-gpio.rs b/va108xx/examples/embassy/src/bin/async-gpio.rs new file mode 100644 index 0000000..bf0a32b --- /dev/null +++ b/va108xx/examples/embassy/src/bin/async-gpio.rs @@ -0,0 +1,247 @@ +//! This example demonstrates the usage of async GPIO operations on VA108xx. +//! +//! You need to tie the PA0 to the PA1 pin for this example to work. You can optionally tie the PB22 to PB23 pins well +//! and then set the `CHECK_PB22_TO_PB23` to true to also test async operations on Port B. +#![no_std] +#![no_main] +// This imports the logger and the panic handler. +use embassy_example as _; + +use embassy_executor::Spawner; +use embassy_sync::channel::{Receiver, Sender}; +use embassy_sync::{blocking_mutex::raw::ThreadModeRawMutex, channel::Channel}; +use embassy_time::{Duration, Instant, Timer}; +use embedded_hal_async::digital::Wait; +use va108xx_hal::gpio::asynch::{on_interrupt_for_async_gpio_for_port, InputPinAsync}; +use va108xx_hal::gpio::{Input, Output, PinState, Port}; +use va108xx_hal::pins::{PinsA, PinsB}; +use va108xx_hal::{ + pac::{self, interrupt}, + prelude::*, +}; + +const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000); + +const CHECK_PA0_TO_PA1: bool = true; +const CHECK_PB22_TO_PB23: bool = false; + +// Can also be set to OC10 and works as well. +const PB22_TO_PB23_IRQ: pac::Interrupt = pac::Interrupt::OC11; + +#[derive(Clone, Copy)] +pub struct GpioCmd { + cmd_type: GpioCmdType, + after_delay: u32, +} + +impl GpioCmd { + pub fn new(cmd_type: GpioCmdType, after_delay: u32) -> Self { + Self { + cmd_type, + after_delay, + } + } +} + +#[derive(Clone, Copy)] +pub enum GpioCmdType { + SetHigh, + SetLow, + RisingEdge, + FallingEdge, +} + +// Declare a bounded channel of 3 u32s. +static CHANNEL_PA0_PA1: Channel = Channel::new(); +static CHANNEL_PB22_TO_PB23: Channel = Channel::new(); + +#[embassy_executor::main] +async fn main(spawner: Spawner) { + defmt::println!("-- VA108xx Async GPIO Demo --"); + + let dp = pac::Peripherals::take().unwrap(); + + // Safety: Only called once here. + va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ); + + let porta = PinsA::new(dp.porta); + let portb = PinsB::new(dp.portb); + let mut led0 = Output::new(porta.pa10, PinState::Low); + let out_pa0 = Output::new(porta.pa0, PinState::Low); + let in_pa1 = Input::new_floating(porta.pa1); + let out_pb22 = Output::new(portb.pb22, PinState::Low); + let in_pb23 = Input::new_floating(portb.pb23); + + let in_pa1_async = InputPinAsync::new(in_pa1, pac::Interrupt::OC10); + let in_pb23_async = InputPinAsync::new(in_pb23, PB22_TO_PB23_IRQ); + + spawner + .spawn(output_task( + "PA0 to PA1", + out_pa0, + CHANNEL_PA0_PA1.receiver(), + )) + .unwrap(); + spawner + .spawn(output_task( + "PB22 to PB23", + out_pb22, + CHANNEL_PB22_TO_PB23.receiver(), + )) + .unwrap(); + + if CHECK_PA0_TO_PA1 { + check_pin_to_pin_async_ops("PA0 to PA1", CHANNEL_PA0_PA1.sender(), in_pa1_async).await; + defmt::info!("Example PA0 to PA1 done"); + } + if CHECK_PB22_TO_PB23 { + check_pin_to_pin_async_ops("PB22 to PB23", CHANNEL_PB22_TO_PB23.sender(), in_pb23_async) + .await; + defmt::info!("Example PB22 to PB23 done"); + } + + defmt::info!("Example done, toggling LED0"); + loop { + led0.toggle(); + Timer::after(Duration::from_millis(500)).await; + } +} + +async fn check_pin_to_pin_async_ops( + ctx: &'static str, + sender: Sender<'static, ThreadModeRawMutex, GpioCmd, 3>, + mut async_input: impl Wait, +) { + defmt::info!( + "{}: sending SetHigh command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender.send(GpioCmd::new(GpioCmdType::SetHigh, 20)).await; + async_input.wait_for_high().await.unwrap(); + defmt::info!( + "{}: Input pin is high now ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending SetLow command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender.send(GpioCmd::new(GpioCmdType::SetLow, 20)).await; + async_input.wait_for_low().await.unwrap(); + defmt::info!( + "{}: Input pin is low now ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending RisingEdge command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender.send(GpioCmd::new(GpioCmdType::RisingEdge, 20)).await; + async_input.wait_for_rising_edge().await.unwrap(); + defmt::info!( + "{}: input pin had rising edge ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending Falling command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender + .send(GpioCmd::new(GpioCmdType::FallingEdge, 20)) + .await; + async_input.wait_for_falling_edge().await.unwrap(); + defmt::info!( + "{}: input pin had a falling edge ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending Falling command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender + .send(GpioCmd::new(GpioCmdType::FallingEdge, 20)) + .await; + async_input.wait_for_any_edge().await.unwrap(); + defmt::info!( + "{}: input pin had a falling (any) edge ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending Falling command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender.send(GpioCmd::new(GpioCmdType::RisingEdge, 20)).await; + async_input.wait_for_any_edge().await.unwrap(); + defmt::info!( + "{}: input pin had a rising (any) edge ({} ms)", + ctx, + Instant::now().as_millis() + ); +} + +#[embassy_executor::task(pool_size = 2)] +async fn output_task( + ctx: &'static str, + mut out: Output, + receiver: Receiver<'static, ThreadModeRawMutex, GpioCmd, 3>, +) { + loop { + let next_cmd = receiver.receive().await; + Timer::after(Duration::from_millis(next_cmd.after_delay.into())).await; + match next_cmd.cmd_type { + GpioCmdType::SetHigh => { + defmt::info!("{}: Set output high", ctx); + out.set_high(); + } + GpioCmdType::SetLow => { + defmt::info!("{}: Set output low", ctx); + out.set_low(); + } + GpioCmdType::RisingEdge => { + defmt::info!("{}: Rising edge", ctx); + if !out.is_set_low() { + out.set_low(); + } + out.set_high(); + } + GpioCmdType::FallingEdge => { + defmt::info!("{}: Falling edge", ctx); + if !out.is_set_high() { + out.set_high(); + } + out.set_low(); + } + } + } +} + +// PB22 to PB23 can be handled by both OC10 and OC11 depending on configuration. +#[interrupt] +#[allow(non_snake_case)] +fn OC10() { + on_interrupt_for_async_gpio_for_port(Port::A); + on_interrupt_for_async_gpio_for_port(Port::B); +} + +// This interrupt only handles PORT B interrupts. +#[interrupt] +#[allow(non_snake_case)] +fn OC11() { + on_interrupt_for_async_gpio_for_port(Port::B); +} diff --git a/va108xx/examples/embassy/src/bin/async-uart-rx.rs b/va108xx/examples/embassy/src/bin/async-uart-rx.rs new file mode 100644 index 0000000..5839a20 --- /dev/null +++ b/va108xx/examples/embassy/src/bin/async-uart-rx.rs @@ -0,0 +1,163 @@ +//! Asynchronous UART reception example application. +//! +//! This application receives data on two UARTs permanently using a ring buffer. +//! The ring buffer are read them asynchronously. UART A is received on ports PA8 and PA9. +//! UART B is received on ports PA2 and PA3. +//! +//! Instructions: +//! +//! 1. Tie a USB to UART converter with RX to PA9 and TX to PA8 for UART A. +//! Tie a USB to UART converter with RX to PA3 and TX to PA2 for UART B. +//! 2. Connect to the serial interface by using an application like Putty or picocom. You can +//! type something in the terminal and check if the data is echoed back. You can also check the +//! RTT logs to see received data. +#![no_std] +#![no_main] +// This imports the logger and the panic handler. +use embassy_example as _; + +use core::cell::RefCell; +use critical_section::Mutex; +use embassy_executor::Spawner; +use embassy_time::Instant; +use embedded_io::Write; +use embedded_io_async::Read; +use heapless::spsc::{Consumer, Producer, Queue}; +use va108xx_hal::{ + gpio::{Output, PinState}, + pac::{self, interrupt}, + pins::PinsA, + prelude::*, + uart::{ + self, on_interrupt_rx_overwriting, + rx_asynch::{on_interrupt_rx, RxAsync}, + Bank, RxAsyncOverwriting, Tx, + }, + InterruptConfig, +}; + +const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000); + +static QUEUE_UART_A: static_cell::ConstStaticCell> = + static_cell::ConstStaticCell::new(Queue::new()); +static PRODUCER_UART_A: Mutex>>> = Mutex::new(RefCell::new(None)); + +static QUEUE_UART_B: static_cell::ConstStaticCell> = + static_cell::ConstStaticCell::new(Queue::new()); +static PRODUCER_UART_B: Mutex>>> = Mutex::new(RefCell::new(None)); +static CONSUMER_UART_B: Mutex>>> = Mutex::new(RefCell::new(None)); + +// main is itself an async function. +#[embassy_executor::main] +async fn main(spawner: Spawner) { + defmt::println!("-- VA108xx Async UART RX Demo --"); + + let dp = pac::Peripherals::take().unwrap(); + + // Safety: Only called once here. + va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ); + + let porta = PinsA::new(dp.porta); + let mut led0 = Output::new(porta.pa10, PinState::Low); + let mut led1 = Output::new(porta.pa7, PinState::Low); + let mut led2 = Output::new(porta.pa6, PinState::Low); + + let tx_uart_a = porta.pa9; + let rx_uart_a = porta.pa8; + + let uarta = uart::Uart::new_with_interrupt( + dp.uarta, + tx_uart_a, + rx_uart_a, + 50.MHz(), + 115200.Hz().into(), + InterruptConfig::new(pac::Interrupt::OC2, true, true), + ) + .unwrap(); + + let tx_uart_b = porta.pa3; + let rx_uart_b = porta.pa2; + + let uartb = uart::Uart::new_with_interrupt( + dp.uartb, + tx_uart_b, + rx_uart_b, + 50.MHz(), + 115200.Hz().into(), + InterruptConfig::new(pac::Interrupt::OC3, true, true), + ) + .unwrap(); + let (mut tx_uart_a, rx_uart_a) = uarta.split(); + let (tx_uart_b, rx_uart_b) = uartb.split(); + let (prod_uart_a, cons_uart_a) = QUEUE_UART_A.take().split(); + // Pass the producer to the interrupt handler. + let (prod_uart_b, cons_uart_b) = QUEUE_UART_B.take().split(); + critical_section::with(|cs| { + *PRODUCER_UART_A.borrow(cs).borrow_mut() = Some(prod_uart_a); + *PRODUCER_UART_B.borrow(cs).borrow_mut() = Some(prod_uart_b); + *CONSUMER_UART_B.borrow(cs).borrow_mut() = Some(cons_uart_b); + }); + let mut async_rx_uart_a = RxAsync::new(rx_uart_a, cons_uart_a); + let async_rx_uart_b = RxAsyncOverwriting::new(rx_uart_b, &CONSUMER_UART_B); + spawner + .spawn(uart_b_task(async_rx_uart_b, tx_uart_b)) + .unwrap(); + let mut buf = [0u8; 256]; + loop { + defmt::info!("Current time UART A: {}", Instant::now().as_secs()); + led0.toggle(); + led1.toggle(); + led2.toggle(); + let read_bytes = async_rx_uart_a.read(&mut buf).await.unwrap(); + let read_str = core::str::from_utf8(&buf[..read_bytes]).unwrap(); + defmt::info!( + "Read {} bytes asynchronously on UART A: {:?}", + read_bytes, + read_str + ); + tx_uart_a.write_all(read_str.as_bytes()).unwrap(); + } +} + +#[embassy_executor::task] +async fn uart_b_task(mut async_rx: RxAsyncOverwriting, mut tx: Tx) { + let mut buf = [0u8; 256]; + loop { + defmt::info!("Current time UART B: {}", Instant::now().as_secs()); + // Infallible asynchronous operation. + let read_bytes = async_rx.read(&mut buf).await.unwrap(); + let read_str = core::str::from_utf8(&buf[..read_bytes]).unwrap(); + defmt::info!( + "Read {} bytes asynchronously on UART B: {:?}", + read_bytes, + read_str + ); + tx.write_all(read_str.as_bytes()).unwrap(); + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn OC2() { + let mut prod = + critical_section::with(|cs| PRODUCER_UART_A.borrow(cs).borrow_mut().take().unwrap()); + let errors = on_interrupt_rx(Bank::Uart0, &mut prod); + critical_section::with(|cs| *PRODUCER_UART_A.borrow(cs).borrow_mut() = Some(prod)); + // In a production app, we could use a channel to send the errors to the main task. + if let Err(errors) = errors { + defmt::info!("UART A errors: {:?}", errors); + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn OC3() { + let mut prod = + critical_section::with(|cs| PRODUCER_UART_B.borrow(cs).borrow_mut().take().unwrap()); + let errors = on_interrupt_rx_overwriting(Bank::Uart1, &mut prod, &CONSUMER_UART_B); + critical_section::with(|cs| *PRODUCER_UART_B.borrow(cs).borrow_mut() = Some(prod)); + // In a production app, we could use a channel to send the errors to the main task. + if let Err(errors) = errors { + defmt::info!("UART B errors: {:?}", errors); + } +} diff --git a/va108xx/examples/embassy/src/bin/async-uart-tx.rs b/va108xx/examples/embassy/src/bin/async-uart-tx.rs new file mode 100644 index 0000000..4fd4f69 --- /dev/null +++ b/va108xx/examples/embassy/src/bin/async-uart-tx.rs @@ -0,0 +1,90 @@ +//! Asynchronous UART transmission example application. +//! +//! This application receives sends 4 strings with different sizes permanently using UART A. +//! Ports PA8 and PA9 are used for this. +//! +//! Instructions: +//! +//! 1. Tie a USB to UART converter with RX to PA9 and TX to PA8 for UART A. +//! 2. Connect to the serial interface by using an application like Putty or picocom. You can +//! can verify the correctness of the sent strings. +#![no_std] +#![no_main] +// This imports the logger and the panic handler. +use embassy_example as _; + +use embassy_executor::Spawner; +use embassy_time::{Duration, Instant, Ticker}; +use embedded_io_async::Write; +use va108xx_hal::{ + gpio::{Output, PinState}, + pac::{self, interrupt}, + pins::PinsA, + prelude::*, + uart::{self, on_interrupt_tx, Bank, TxAsync}, + InterruptConfig, +}; + +const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000); + +const STR_LIST: &[&str] = &[ + "Hello World\r\n", + "Smoll\r\n", + "A string which is larger than the FIFO size\r\n", + "A really large string which is significantly larger than the FIFO size\r\n", +]; + +// main is itself an async function. +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + defmt::println!("-- VA108xx Async UART TX Demo --"); + + let dp = pac::Peripherals::take().unwrap(); + + // Safety: Only called once here. + va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ); + + let porta = PinsA::new(dp.porta); + + let mut led0 = Output::new(porta.pa10, PinState::Low); + let mut led1 = Output::new(porta.pa7, PinState::Low); + let mut led2 = Output::new(porta.pa6, PinState::Low); + + let tx = porta.pa9; + let rx = porta.pa8; + + let uarta = uart::Uart::new_with_interrupt( + dp.uarta, + tx, + rx, + 50.MHz(), + 115200.Hz().into(), + InterruptConfig::new(pac::Interrupt::OC2, true, true), + ) + .unwrap(); + let (tx, _rx) = uarta.split(); + let mut async_tx = TxAsync::new(tx); + let mut ticker = Ticker::every(Duration::from_secs(1)); + let mut idx = 0; + loop { + defmt::info!("Current time: {}", Instant::now().as_secs()); + led0.toggle(); + led1.toggle(); + led2.toggle(); + let _written = async_tx + .write(STR_LIST[idx].as_bytes()) + .await + .expect("writing failed"); + idx += 1; + if idx == STR_LIST.len() { + idx = 0; + } + ticker.next().await; + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn OC2() { + on_interrupt_tx(Bank::Uart0); +} diff --git a/va108xx/examples/embassy/src/lib.rs b/va108xx/examples/embassy/src/lib.rs new file mode 100644 index 0000000..c1d93ab --- /dev/null +++ b/va108xx/examples/embassy/src/lib.rs @@ -0,0 +1,3 @@ +#![no_std] +use defmt_rtt as _; +use panic_probe as _; diff --git a/va108xx/examples/embassy/src/main.rs b/va108xx/examples/embassy/src/main.rs new file mode 100644 index 0000000..a0fa571 --- /dev/null +++ b/va108xx/examples/embassy/src/main.rs @@ -0,0 +1,62 @@ +#![no_std] +#![no_main] +use embassy_example as _; +use embassy_executor::Spawner; +use embassy_time::{Duration, Instant, Ticker}; + +cfg_if::cfg_if! { + if #[cfg(feature = "custom-irqs")] { + use va108xx_embassy::embassy_time_driver_irqs; + use va108xx_hal::pac::interrupt; + embassy_time_driver_irqs!(timekeeper_irq = OC23, alarm_irq = OC24); + } +} + +use va108xx_hal::{ + gpio::{Output, PinState}, + pac, + pins::PinsA, + prelude::*, +}; + +const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000); + +// main is itself an async function. +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + defmt::println!("-- VA108xx Embassy Demo --"); + + let dp = pac::Peripherals::take().unwrap(); + + // Safety: Only called once here. + cfg_if::cfg_if! { + if #[cfg(not(feature = "custom-irqs"))] { + va108xx_embassy::init( + dp.tim23, + dp.tim22, + SYSCLK_FREQ, + ); + } else { + va108xx_embassy::init_with_custom_irqs( + dp.tim23, + dp.tim22, + SYSCLK_FREQ, + pac::Interrupt::OC23, + pac::Interrupt::OC24, + ); + } + } + + let porta = PinsA::new(dp.porta); + let mut led0 = Output::new(porta.pa10, PinState::Low); + let mut led1 = Output::new(porta.pa7, PinState::Low); + let mut led2 = Output::new(porta.pa6, PinState::Low); + let mut ticker = Ticker::every(Duration::from_secs(1)); + loop { + ticker.next().await; + defmt::info!("Current time: {}", Instant::now().as_secs()); + led0.toggle(); + led1.toggle(); + led2.toggle(); + } +} diff --git a/va108xx/examples/rtic/Cargo.toml b/va108xx/examples/rtic/Cargo.toml new file mode 100644 index 0000000..8215894 --- /dev/null +++ b/va108xx/examples/rtic/Cargo.toml @@ -0,0 +1,17 @@ +[package] +name = "rtic-example" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +embedded-io = "0.6" +defmt-rtt = "1" +defmt = "1" +panic-probe = { version = "1", features = ["defmt"] } +rtic = { version = "2", features = ["thumbv6-backend"] } +rtic-monotonics = { version = "2", features = ["cortex-m-systick"] } +ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] } + +va108xx-hal = { version = "0.12", path = "../../va108xx-hal" } +vorago-reb1 = { version = "0.9", path = "../../vorago-reb1" } diff --git a/va108xx/examples/rtic/src/bin/blinky-button-rtic.rs b/va108xx/examples/rtic/src/bin/blinky-button-rtic.rs new file mode 100644 index 0000000..b12a692 --- /dev/null +++ b/va108xx/examples/rtic/src/bin/blinky-button-rtic.rs @@ -0,0 +1,98 @@ +//! Blinky button application for the REB1 board using RTIC +#![no_main] +#![no_std] + +#[rtic::app(device = pac)] +mod app { + use rtic_example::SYSCLK_FREQ; + // Import panic provider. + use panic_probe as _; + // Import global logger. + use defmt_rtt as _; + use va108xx_hal::{ + clock::{set_clk_div_register, FilterClockSelect}, + gpio::{FilterType, InterruptEdge}, + pac, + pins::PinsA, + timer::InterruptConfig, + }; + use vorago_reb1::button::Button; + use vorago_reb1::leds::Leds; + + rtic_monotonics::systick_monotonic!(Mono, 1_000); + + #[derive(Debug, PartialEq, defmt::Format)] + pub enum PressMode { + Toggle, + Keep, + } + + // You can change the press mode here + const DEFAULT_MODE: PressMode = PressMode::Toggle; + + #[local] + struct Local { + leds: Leds, + button: Button, + mode: PressMode, + } + + #[shared] + struct Shared {} + + #[init] + fn init(cx: init::Context) -> (Shared, Local) { + defmt::println!("-- Vorago Button IRQ Example --"); + Mono::start(cx.core.SYST, SYSCLK_FREQ.raw()); + + let mode = DEFAULT_MODE; + defmt::info!("Using {:?} mode", mode); + + let mut dp = cx.device; + let pinsa = PinsA::new(dp.porta); + let edge_irq = match mode { + PressMode::Toggle => InterruptEdge::HighToLow, + PressMode::Keep => InterruptEdge::BothEdges, + }; + + // Configure an edge interrupt on the button and route it to interrupt vector 15 + let mut button = Button::new(pinsa.pa11); + + if mode == PressMode::Toggle { + // This filter debounces the switch for edge based interrupts + button.configure_filter_type(FilterType::FilterFourCycles, FilterClockSelect::Clk1); + set_clk_div_register(&mut dp.sysconfig, FilterClockSelect::Clk1, 50_000); + } + button.configure_and_enable_edge_interrupt( + edge_irq, + InterruptConfig::new(pac::interrupt::OC15, true, true), + ); + let mut leds = Leds::new(pinsa.pa10, pinsa.pa7, pinsa.pa6); + for led in leds.iter_mut() { + led.off(); + } + (Shared {}, Local { leds, button, mode }) + } + + // `shared` cannot be accessed from this context + #[idle] + fn idle(_cx: idle::Context) -> ! { + loop { + cortex_m::asm::nop(); + } + } + + #[task(binds = OC15, local=[button, leds, mode])] + fn button_task(cx: button_task::Context) { + let leds = cx.local.leds; + let button = cx.local.button; + let mode = cx.local.mode; + if *mode == PressMode::Toggle { + leds[0].toggle(); + } else if button.released() { + leds[0].off(); + } else { + leds[0].on(); + } + } +} diff --git a/va108xx/examples/rtic/src/bin/rtic-empty.rs b/va108xx/examples/rtic/src/bin/rtic-empty.rs new file mode 100644 index 0000000..294e382 --- /dev/null +++ b/va108xx/examples/rtic/src/bin/rtic-empty.rs @@ -0,0 +1,31 @@ +//! Empty RTIC project template +#![no_main] +#![no_std] + +#[rtic::app(device = pac)] +mod app { + // Import panic provider. + use panic_probe as _; + // Import global logger. + use defmt_rtt as _; + use va108xx_hal::pac; + + #[local] + struct Local {} + + #[shared] + struct Shared {} + + #[init] + fn init(_ctx: init::Context) -> (Shared, Local) { + defmt::println!("-- Vorago RTIC template --"); + (Shared {}, Local {}) + } + + // `shared` cannot be accessed from this context + #[idle] + fn idle(_cx: idle::Context) -> ! { + #[allow(clippy::empty_loop)] + loop {} + } +} diff --git a/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs b/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs new file mode 100644 index 0000000..a2839ca --- /dev/null +++ b/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs @@ -0,0 +1,133 @@ +//! More complex UART application on UART PA8 (TX) and PA9 (RX). +//! +//! Uses the IRQ capabilities of the VA10820 peripheral and the RTIC framework to poll the UART in +//! a non-blocking way. All received data will be sent back to the sender. +#![no_main] +#![no_std] + +use ringbuf::StaticRb; + +// Larger buffer for TC to be able to hold the possibly large memory write packets. +const RX_RING_BUF_SIZE: usize = 1024; + +#[rtic::app(device = pac, dispatchers = [OC4])] +mod app { + use super::*; + use embedded_io::Write; + use ringbuf::traits::{Consumer, Observer, Producer}; + use rtic_example::SYSCLK_FREQ; + // Import panic provider. + use panic_probe as _; + // Import global logger. + use defmt_rtt as _; + use rtic_monotonics::Monotonic; + use va108xx_hal::{ + pac, + pins::PinsA, + prelude::*, + uart::{self, RxWithInterrupt, Tx}, + InterruptConfig, + }; + + #[local] + struct Local { + rx: RxWithInterrupt, + tx: Tx, + } + + #[shared] + struct Shared { + rb: StaticRb, + } + + rtic_monotonics::systick_monotonic!(Mono, 1_000); + + #[init] + fn init(cx: init::Context) -> (Shared, Local) { + defmt::println!("-- VA108xx UART Echo with IRQ example application--"); + + Mono::start(cx.core.SYST, SYSCLK_FREQ.raw()); + + let dp = cx.device; + let gpioa = PinsA::new(dp.porta); + let tx = gpioa.pa9; + let rx = gpioa.pa8; + + let irq_uart = uart::Uart::new_with_interrupt( + dp.uarta, + tx, + rx, + SYSCLK_FREQ, + 115200.Hz().into(), + InterruptConfig::new(pac::Interrupt::OC3, true, true), + ) + .unwrap(); + let (tx, rx) = irq_uart.split(); + let mut rx = rx.into_rx_with_irq(); + + rx.start(); + + echo_handler::spawn().unwrap(); + ( + Shared { + rb: StaticRb::default(), + }, + Local { rx, tx }, + ) + } + + // `shared` cannot be accessed from this context + #[idle] + fn idle(_cx: idle::Context) -> ! { + loop { + cortex_m::asm::nop(); + } + } + + #[task( + binds = OC3, + shared = [rb], + local = [ + rx, + ], + )] + fn reception_task(mut cx: reception_task::Context) { + let mut buf: [u8; 16] = [0; 16]; + let mut ringbuf_full = false; + let result = cx.local.rx.on_interrupt(&mut buf); + if result.bytes_read > 0 && result.errors.is_none() { + cx.shared.rb.lock(|rb| { + if rb.vacant_len() < result.bytes_read { + ringbuf_full = true; + } else { + rb.push_slice(&buf[0..result.bytes_read]); + } + }); + } + if ringbuf_full { + // Could also drop oldest data, but that would require the consumer to be shared. + defmt::println!("buffer full, data was dropped"); + } + } + + #[task(shared = [rb], local = [ + buf: [u8; RX_RING_BUF_SIZE] = [0; RX_RING_BUF_SIZE], + + tx + ], priority=1)] + async fn echo_handler(mut cx: echo_handler::Context) { + loop { + cx.shared.rb.lock(|rb| { + let bytes_to_read = rb.occupied_len(); + if bytes_to_read > 0 { + let actual_read_bytes = rb.pop_slice(&mut cx.local.buf[0..bytes_to_read]); + cx.local + .tx + .write_all(&cx.local.buf[0..actual_read_bytes]) + .expect("Failed to write to TX"); + } + }); + Mono::delay(50.millis()).await; + } + } +} diff --git a/va108xx/examples/rtic/src/lib.rs b/va108xx/examples/rtic/src/lib.rs new file mode 100644 index 0000000..5eea1ac --- /dev/null +++ b/va108xx/examples/rtic/src/lib.rs @@ -0,0 +1,4 @@ +#![no_std] +use va108xx_hal::time::Hertz; + +pub const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000); diff --git a/va108xx/examples/rtic/src/main.rs b/va108xx/examples/rtic/src/main.rs new file mode 100644 index 0000000..833a751 --- /dev/null +++ b/va108xx/examples/rtic/src/main.rs @@ -0,0 +1,68 @@ +//! RTIC minimal blinky +#![no_main] +#![no_std] + +#[rtic::app(device = pac, dispatchers = [OC31, OC30, OC29])] +mod app { + use cortex_m::asm; + use rtic_example::SYSCLK_FREQ; + use rtic_monotonics::systick::prelude::*; + use rtic_monotonics::Monotonic; + // Import panic provider. + use panic_probe as _; + // Import global logger. + use defmt_rtt as _; + use va108xx_hal::{ + gpio::{Output, PinState}, + pac, + pins::PinsA, + }; + + #[local] + struct Local { + led0: Output, + led1: Output, + led2: Output, + } + + #[shared] + struct Shared {} + + rtic_monotonics::systick_monotonic!(Mono, 1_000); + + #[init] + fn init(cx: init::Context) -> (Shared, Local) { + defmt::println!("-- Vorago VA108xx RTIC template --"); + + Mono::start(cx.core.SYST, SYSCLK_FREQ.raw()); + + let porta = PinsA::new(cx.device.porta); + let led0 = Output::new(porta.pa10, PinState::Low); + let led1 = Output::new(porta.pa7, PinState::Low); + let led2 = Output::new(porta.pa6, PinState::Low); + blinky::spawn().ok(); + (Shared {}, Local { led0, led1, led2 }) + } + + // `shared` cannot be accessed from this context + #[idle] + fn idle(_cx: idle::Context) -> ! { + loop { + asm::nop(); + } + } + + #[task( + priority = 3, + local=[led0, led1, led2], + )] + async fn blinky(cx: blinky::Context) { + loop { + defmt::println!("toggling LEDs"); + cx.local.led0.toggle(); + cx.local.led1.toggle(); + cx.local.led2.toggle(); + Mono::delay(1000.millis()).await; + } + } +} diff --git a/va108xx/examples/simple/Cargo.toml b/va108xx/examples/simple/Cargo.toml new file mode 100644 index 0000000..2264c24 --- /dev/null +++ b/va108xx/examples/simple/Cargo.toml @@ -0,0 +1,21 @@ +[package] +name = "simple-examples" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = {version = "0.7", features = ["critical-section-single-core"]} +cortex-m-rt = "0.7" +panic-halt = "1" +defmt-rtt = "1" +defmt = "1" +panic-probe = { version = "1", features = ["defmt"] } +embedded-hal = "1" +embedded-hal-nb = "1" +embedded-io = "0.6" +portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] } + +[dependencies.va108xx-hal] +version = "0.12" +path = "../../va108xx-hal" +features = ["defmt"] diff --git a/va108xx/examples/simple/examples/blinky-pac.rs b/va108xx/examples/simple/examples/blinky-pac.rs new file mode 100644 index 0000000..bd5f5ca --- /dev/null +++ b/va108xx/examples/simple/examples/blinky-pac.rs @@ -0,0 +1,47 @@ +//! Blinky examples using only the PAC +//! +//! Additional note on LEDs: +//! Pulling the GPIOs low makes the LEDs blink. See REB1 +//! schematic for more details. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use panic_halt as _; +use va108xx_hal::pac; + +// REB LED pin definitions. All on port A +const LED_D2: u32 = 1 << 10; +const LED_D3: u32 = 1 << 7; +const LED_D4: u32 = 1 << 6; + +#[entry] +fn main() -> ! { + let dp = pac::Peripherals::take().unwrap(); + // Enable all peripheral clocks + dp.sysconfig + .peripheral_clk_enable() + .modify(|_, w| unsafe { w.bits(0xffffffff) }); + dp.porta + .dir() + .modify(|_, w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + dp.porta + .datamask() + .modify(|_, w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + for _ in 0..10 { + dp.porta + .clrout() + .write(|w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + cortex_m::asm::delay(5_000_000); + dp.porta + .setout() + .write(|w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + cortex_m::asm::delay(5_000_000); + } + loop { + dp.porta + .togout() + .write(|w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + cortex_m::asm::delay(25_000_000); + } +} diff --git a/va108xx/examples/simple/examples/blinky.rs b/va108xx/examples/simple/examples/blinky.rs new file mode 100644 index 0000000..d7f57d3 --- /dev/null +++ b/va108xx/examples/simple/examples/blinky.rs @@ -0,0 +1,46 @@ +//! Simple blinky example +//! +//! Additional note on LEDs when using the REB1 development board: +//! Be not afraid: Pulling the GPIOs low makes the LEDs blink. See REB1 +//! schematic for more details. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use panic_halt as _; +use va108xx_hal::{ + gpio::{Output, PinState}, + pac::{self}, + pins::PinsA, + prelude::*, + timer::CountdownTimer, +}; + +#[entry] +fn main() -> ! { + let dp = pac::Peripherals::take().unwrap(); + let mut delay = CountdownTimer::new(dp.tim1, 50.MHz()); + let porta = PinsA::new(dp.porta); + let mut led1 = Output::new(porta.pa10, PinState::Low); + let mut led2 = Output::new(porta.pa7, PinState::Low); + let mut led3 = Output::new(porta.pa6, PinState::Low); + for _ in 0..10 { + led1.set_low(); + led2.set_low(); + led3.set_low(); + delay.delay_ms(200); + led1.set_high(); + led2.set_high(); + led3.set_high(); + delay.delay_ms(200); + } + loop { + led1.toggle(); + delay.delay_ms(200); + led2.toggle(); + delay.delay_ms(200); + led3.toggle(); + delay.delay_ms(200); + } +} diff --git a/va108xx/examples/simple/examples/cascade.rs b/va108xx/examples/simple/examples/cascade.rs new file mode 100644 index 0000000..a204fda --- /dev/null +++ b/va108xx/examples/simple/examples/cascade.rs @@ -0,0 +1,109 @@ +//! Simple Cascade example +//! +//! A timer will be periodically started which starts another timer via the cascade feature. +//! This timer will then start another timer with the cascade feature as well. +#![no_main] +#![no_std] +#![allow(non_snake_case)] + +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; +use va108xx_hal::{ + pac::{self, interrupt}, + prelude::*, + timer::{CascadeControl, CascadeSelect, CascadeSource, CountdownTimer, InterruptConfig}, +}; + +#[entry] +fn main() -> ! { + defmt::println!("-- VA108xx Cascade example application--"); + + let dp = pac::Peripherals::take().unwrap(); + let mut delay = CountdownTimer::new(dp.tim0, 50.MHz()); + + // Will be started periodically to trigger a cascade + let mut cascade_triggerer = CountdownTimer::new(dp.tim3, 50.MHz()); + cascade_triggerer.auto_disable(true); + cascade_triggerer.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC1, true, false)); + cascade_triggerer.enable(); + + // First target for cascade + let mut cascade_target_1 = CountdownTimer::new(dp.tim4, 50.MHz()); + cascade_target_1.auto_deactivate(true); + cascade_target_1 + .cascade_source(CascadeSelect::Csd0, CascadeSource::Tim(3)) + .unwrap(); + let mut csd_cfg = CascadeControl { + enable_src_0: true, + trigger_mode_0: true, + ..Default::default() + }; + cascade_target_1.cascade_control(csd_cfg); + // Normally it should already be sufficient to activate IRQ in the CTRL + // register but a full interrupt is use here to display print output when + // the timer expires + cascade_target_1.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC2, true, false)); + // The counter will only activate when the cascade signal is coming in so + // it is okay to call start here to set the reset value + cascade_target_1.start(1.Hz()); + + // Activated by first cascade target + let mut cascade_target_2 = CountdownTimer::new(dp.tim5, 50.MHz()); + cascade_target_2.auto_deactivate(true); + // Set TIM4 as cascade source + cascade_target_2 + .cascade_source(CascadeSelect::Csd1, CascadeSource::Tim(4)) + .unwrap(); + + csd_cfg = CascadeControl::default(); + csd_cfg.enable_src_1 = true; + // Use trigger mode here + csd_cfg.trigger_mode_1 = true; + cascade_target_2.cascade_control(csd_cfg); + // Normally it should already be sufficient to activate IRQ in the CTRL + // register but a full interrupt is use here to display print output when + // the timer expires + cascade_target_2.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC3, true, false)); + // The counter will only activate when the cascade signal is coming in so + // it is okay to call start here to set the reset value + cascade_target_2.start(1.Hz()); + + // Unpend all IRQs + unsafe { + cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0); + cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC1); + cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC2); + cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC3); + } + + loop { + defmt::info!("-- Triggering cascade in 0.5 seconds --"); + cascade_triggerer.start(2.Hz()); + delay.delay_ms(5000); + } +} + +#[interrupt] +fn OC1() { + static mut IDX: u32 = 0; + defmt::info!("{}: Cascade trigger timed out", &IDX); + *IDX += 1; +} + +#[interrupt] +fn OC2() { + static mut IDX: u32 = 0; + defmt::info!("{}: First cascade target timed out", &IDX); + *IDX += 1; +} + +#[interrupt] +fn OC3() { + static mut IDX: u32 = 0; + defmt::info!("{}: Second cascade target timed out", &IDX); + *IDX += 1; +} diff --git a/va108xx/examples/simple/examples/pwm.rs b/va108xx/examples/simple/examples/pwm.rs new file mode 100644 index 0000000..9590bfe --- /dev/null +++ b/va108xx/examples/simple/examples/pwm.rs @@ -0,0 +1,68 @@ +//! Simple PWM example +//! +//! Outputs a PWM waveform on pin PA3. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::{delay::DelayNs, pwm::SetDutyCycle}; +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; +use va108xx_hal::{ + pac, + pins::PinsA, + prelude::*, + pwm::{self, get_duty_from_percent, PwmA, PwmB, PwmPin}, + timer::CountdownTimer, +}; + +#[entry] +fn main() -> ! { + defmt::println!("-- VA108xx PWM example application--"); + let dp = pac::Peripherals::take().unwrap(); + let pinsa = PinsA::new(dp.porta); + let mut pwm = pwm::PwmPin::new(pinsa.pa3, dp.tim3, 50.MHz(), 10.Hz()).unwrap(); + let mut delay = CountdownTimer::new(dp.tim0, 50.MHz()); + let mut current_duty_cycle = 0.0; + pwm.set_duty_cycle(get_duty_from_percent(current_duty_cycle)) + .unwrap(); + pwm.enable(); + + // Delete type information, increased code readibility for the rest of the code + loop { + let mut counter = 0; + // Increase duty cycle continuously + while current_duty_cycle < 1.0 { + delay.delay_ms(400); + current_duty_cycle += 0.02; + counter += 1; + if counter % 10 == 0 { + defmt::info!("current duty cycle: {}", current_duty_cycle); + } + + pwm.set_duty_cycle(get_duty_from_percent(current_duty_cycle)) + .unwrap(); + } + + // Switch to PWMB and decrease the window with a high signal from 100 % to 0 % + // continously + current_duty_cycle = 0.0; + let mut upper_limit = 1.0; + let mut lower_limit = 0.0; + let mut pwmb: PwmPin = PwmPin::from(pwm); + pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit)); + pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit)); + while lower_limit < 0.5 { + delay.delay_ms(400); + lower_limit += 0.01; + upper_limit -= 0.01; + pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit)); + pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit)); + defmt::info!("Lower limit: {}", pwmb.pwmb_lower_limit()); + defmt::info!("Upper limit: {}", pwmb.pwmb_upper_limit()); + } + pwm = PwmPin::::from(pwmb); + } +} diff --git a/va108xx/examples/simple/examples/spi.rs b/va108xx/examples/simple/examples/spi.rs new file mode 100644 index 0000000..e8c24dc --- /dev/null +++ b/va108xx/examples/simple/examples/spi.rs @@ -0,0 +1,137 @@ +//! SPI example application +#![no_main] +#![no_std] +use cortex_m_rt::entry; +use embedded_hal::{ + delay::DelayNs, + spi::{Mode, SpiBus, MODE_0}, +}; +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; +use va108xx_hal::{ + pac, + pins::{PinsA, PinsB}, + prelude::*, + spi::{self, configure_pin_as_hw_cs_pin, Spi, SpiClockConfig, TransferConfig}, + timer::CountdownTimer, +}; + +#[derive(PartialEq, Debug)] +pub enum ExampleSelect { + // Enter loopback mode. It is not necessary to tie MOSI/MISO together for this + Loopback, + MosiMisoTiedTogetherManually, +} + +#[derive(PartialEq, Debug)] +pub enum SpiBusSelect { + SpiAPortA, + SpiAPortB, + SpiBPortB, +} + +const EXAMPLE_SEL: ExampleSelect = ExampleSelect::Loopback; +const SPI_BUS_SEL: SpiBusSelect = SpiBusSelect::SpiBPortB; +const SPI_SPEED_KHZ: u32 = 1000; +const SPI_MODE: Mode = MODE_0; +const BLOCKMODE: bool = true; +const FILL_WORD: u8 = 0x0f; + +#[entry] +fn main() -> ! { + defmt::println!("-- VA108xx SPI example application--"); + let dp = pac::Peripherals::take().unwrap(); + let mut delay = CountdownTimer::new(dp.tim0, 50.MHz()); + + let spi_clk_cfg = SpiClockConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz()) + .expect("creating SPI clock config failed"); + let pinsa = PinsA::new(dp.porta); + let pinsb = PinsB::new(dp.portb); + + let mut spi_cfg = spi::SpiConfig::default(); + if EXAMPLE_SEL == ExampleSelect::Loopback { + spi_cfg = spi_cfg.loopback(true) + } + + // Set up the SPI peripheral + let mut spi = match SPI_BUS_SEL { + SpiBusSelect::SpiAPortA => { + let (sck, mosi, miso) = (pinsa.pa31, pinsa.pa30, pinsa.pa29); + let mut spia = Spi::new(dp.spia, (sck, miso, mosi), spi_cfg).unwrap(); + spia.set_fill_word(FILL_WORD); + spia + } + SpiBusSelect::SpiAPortB => { + let (sck, mosi, miso) = (pinsb.pb9, pinsb.pb8, pinsb.pb7); + let mut spia = Spi::new(dp.spia, (sck, miso, mosi), spi_cfg).unwrap(); + spia.set_fill_word(FILL_WORD); + spia + } + SpiBusSelect::SpiBPortB => { + let (sck, mosi, miso) = (pinsb.pb5, pinsb.pb4, pinsb.pb3); + let mut spib = Spi::new(dp.spib, (sck, miso, mosi), spi_cfg).unwrap(); + spib.set_fill_word(FILL_WORD); + spib + } + }; + // Configure transfer specific properties here + match SPI_BUS_SEL { + SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => { + let transfer_cfg = TransferConfig { + clk_cfg: Some(spi_clk_cfg), + mode: Some(SPI_MODE), + sod: true, + blockmode: BLOCKMODE, + bmstall: true, + hw_cs: None, + }; + spi.cfg_transfer(&transfer_cfg); + } + SpiBusSelect::SpiBPortB => { + let hw_cs_pin = configure_pin_as_hw_cs_pin(pinsb.pb2); + let transfer_cfg = TransferConfig { + clk_cfg: Some(spi_clk_cfg), + mode: Some(SPI_MODE), + sod: false, + blockmode: BLOCKMODE, + bmstall: true, + hw_cs: Some(hw_cs_pin), + }; + spi.cfg_transfer(&transfer_cfg); + } + } + + // Application logic + loop { + let mut reply_buf: [u8; 8] = [0; 8]; + // Can't really verify correct reply here. + spi.write(&[0x42]).expect("write failed"); + // Because of the loopback mode, we should get back the fill word here. + spi.read(&mut reply_buf[0..1]).unwrap(); + assert_eq!(reply_buf[0], FILL_WORD); + delay.delay_ms(500_u32); + + let tx_buf: [u8; 3] = [0x01, 0x02, 0x03]; + spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap(); + assert_eq!(tx_buf, reply_buf[0..3]); + defmt::info!( + "Received reply: {}, {}, {}", + reply_buf[0], + reply_buf[1], + reply_buf[2] + ); + delay.delay_ms(500_u32); + + let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01]; + spi.transfer_in_place(&mut tx_rx_buf).unwrap(); + defmt::info!( + "Received reply: {}, {}, {}", + tx_rx_buf[0], + tx_rx_buf[1], + tx_rx_buf[2] + ); + assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]); + } +} diff --git a/va108xx/examples/simple/examples/timer-ticks.rs b/va108xx/examples/simple/examples/timer-ticks.rs new file mode 100644 index 0000000..291f7d4 --- /dev/null +++ b/va108xx/examples/simple/examples/timer-ticks.rs @@ -0,0 +1,106 @@ +//! MS and Second counter implemented using the TIM0 and TIM1 peripheral +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; +use portable_atomic::AtomicU32; +use va108xx_hal::{ + pac::{self, interrupt}, + prelude::*, + time::Hertz, + timer::{CountdownTimer, InterruptConfig}, +}; + +#[allow(dead_code)] +enum LibType { + Pac, + Hal, +} + +static MS_COUNTER: AtomicU32 = AtomicU32::new(0); +static SEC_COUNTER: AtomicU32 = AtomicU32::new(0); + +#[entry] +fn main() -> ! { + let dp = pac::Peripherals::take().unwrap(); + let mut delay = CountdownTimer::new(dp.tim2, 50.MHz()); + let mut last_ms = 0; + defmt::info!("-- Vorago system ticks using timers --"); + let lib_type = LibType::Hal; + match lib_type { + LibType::Pac => { + unsafe { + dp.sysconfig + .peripheral_clk_enable() + .modify(|_, w| w.irqsel().set_bit()); + dp.sysconfig + .tim_clk_enable() + .modify(|r, w| w.bits(r.bits() | (1 << 0) | (1 << 1))); + dp.irqsel.tim(0).write(|w| w.bits(0x00)); + dp.irqsel.tim(1).write(|w| w.bits(0x01)); + } + + let sys_clk: Hertz = 50.MHz(); + let cnt_ms = sys_clk.raw() / 1000 - 1; + let cnt_sec = sys_clk.raw() - 1; + unsafe { + dp.tim0.cnt_value().write(|w| w.bits(cnt_ms)); + dp.tim0.rst_value().write(|w| w.bits(cnt_ms)); + dp.tim0.ctrl().write(|w| { + w.enable().set_bit(); + w.irq_enb().set_bit() + }); + dp.tim1.cnt_value().write(|w| w.bits(cnt_sec)); + dp.tim1.rst_value().write(|w| w.bits(cnt_sec)); + dp.tim1.ctrl().write(|w| { + w.enable().set_bit(); + w.irq_enb().set_bit() + }); + unmask_irqs(); + } + } + LibType::Hal => { + let mut ms_timer = CountdownTimer::new(dp.tim0, 50.MHz()); + ms_timer.enable_interrupt(InterruptConfig::new(interrupt::OC0, true, true)); + ms_timer.start(1.kHz()); + let mut second_timer = CountdownTimer::new(dp.tim1, 50.MHz()); + second_timer.enable_interrupt(InterruptConfig::new(interrupt::OC1, true, true)); + second_timer.start(1.Hz()); + } + } + loop { + let current_ms = MS_COUNTER.load(portable_atomic::Ordering::Relaxed); + if current_ms - last_ms >= 1000 { + // To prevent drift. + last_ms += 1000; + defmt::info!("MS counter: {}", current_ms); + let second = SEC_COUNTER.load(portable_atomic::Ordering::Relaxed); + defmt::info!("Second counter: {}", second); + } + delay.delay_ms(50); + } +} + +fn unmask_irqs() { + unsafe { + cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0); + cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC1); + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn OC0() { + MS_COUNTER.fetch_add(1, portable_atomic::Ordering::Relaxed); +} + +#[interrupt] +#[allow(non_snake_case)] +fn OC1() { + SEC_COUNTER.fetch_add(1, portable_atomic::Ordering::Relaxed); +} diff --git a/va108xx/examples/simple/examples/uart.rs b/va108xx/examples/simple/examples/uart.rs new file mode 100644 index 0000000..50c6986 --- /dev/null +++ b/va108xx/examples/simple/examples/uart.rs @@ -0,0 +1,46 @@ +//! UART example application. Sends a test string over a UART and then enters +//! echo mode. +//! +//! Instructions: +//! +//! 1. Tie a USB to UART converter with RX to PA9 and TX to PA8. +//! 2. Connect to the serial interface by using an application like Putty or picocom. +//! You should set a "Hello World" print when the application starts. After that, everything +//! typed on the console should be printed back by the echo application. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal_nb::{nb, serial::Read}; +use embedded_io::Write as _; +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; +use va108xx_hal::{pac, pins::PinsA, prelude::*, uart}; + +#[entry] +fn main() -> ! { + defmt::println!("-- VA108xx UART example application--"); + + let dp = pac::Peripherals::take().unwrap(); + + let gpioa = PinsA::new(dp.porta); + let tx = gpioa.pa9; + let rx = gpioa.pa8; + let uart = + uart::Uart::new_without_interrupt(dp.uarta, tx, rx, 50.MHz(), 115200.Hz().into()).unwrap(); + + let (mut tx, mut rx) = uart.split(); + writeln!(tx, "Hello World\r").unwrap(); + loop { + // Echo what is received on the serial link. + match rx.read() { + Ok(recv) => { + nb::block!(embedded_hal_nb::serial::Write::write(&mut tx, recv)) + .expect("TX send error"); + } + Err(nb::Error::WouldBlock) => (), + } + } +} diff --git a/va108xx/examples/simple/src/main.rs b/va108xx/examples/simple/src/main.rs new file mode 100644 index 0000000..9256a3b --- /dev/null +++ b/va108xx/examples/simple/src/main.rs @@ -0,0 +1,20 @@ +//! Dummy app which does not do anything. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use va108xx_hal as _; + +#[entry] +fn main() -> ! { + loop { + cortex_m::asm::nop(); + } +} + +#[panic_handler] +fn panic(_info: &core::panic::PanicInfo) -> ! { + loop { + cortex_m::asm::nop(); + } +} diff --git a/va108xx/flashloader/.gitignore b/va108xx/flashloader/.gitignore new file mode 100644 index 0000000..f9606a3 --- /dev/null +++ b/va108xx/flashloader/.gitignore @@ -0,0 +1 @@ +/venv diff --git a/va108xx/flashloader/Cargo.toml b/va108xx/flashloader/Cargo.toml new file mode 100644 index 0000000..c184a81 --- /dev/null +++ b/va108xx/flashloader/Cargo.toml @@ -0,0 +1,35 @@ +[package] +name = "flashloader" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"]} +cortex-m-rt = "0.7" +embedded-io = "0.6" +defmt = "1" +defmt-rtt = { version = "1" } +panic-probe = { version = "1", features = ["print-defmt"] } +num_enum = { version = "0.7", default-features = false } +cobs = { version = "0.4", default-features = false } +satrs = { version = "0.3.0-alpha.1", default-features = false } +ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] } +spacepackets = { version = "0.15", default-features = false, features = ["defmt"] } +# Even though we do not use this directly, we need to activate this feature explicitely +# so that RTIC compiles because thumv6 does not have CAS operations natively. +portable-atomic = {version = "1", features = ["unsafe-assume-single-core"]} + +rtic = { version = "2", features = ["thumbv6-backend"] } +rtic-monotonics = { version = "2", features = ["cortex-m-systick"] } + +[dependencies.va108xx-hal] +version = "0.12" +path = "../va108xx-hal" +features = ["defmt"] + +[dependencies.vorago-reb1] +version = "0.9" +path = "../vorago-reb1" + +[package.metadata.cargo-machete] +ignored = ["portable-atomic", "cortex-m-rt"] diff --git a/va108xx/flashloader/README.md b/va108xx/flashloader/README.md new file mode 100644 index 0000000..242b9f9 --- /dev/null +++ b/va108xx/flashloader/README.md @@ -0,0 +1,75 @@ +VA108xx Flashloader Application +======== + +This flashloader shows a minimal example for a self-updatable Rust software which exposes +a simple PUS (CCSDS) interface to update the software. It also provides a Python application +called the `image-loader.py` which can be used to upload compiled images to the flashloader +application to write them to the NVM. + +Please note that the both the application and the image loader are tailored towards usage +with the [bootloader provided by this repository](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/bootloader). + +The software can quickly be adapted to interface with a real primary on-board software instead of +the Python script provided here to upload images because it uses a low-level CCSDS based packet +interface. + +## Using the Python image loader + +The Python image loader communicates with the Rust flashload application using a dedicated serial +port with a baudrate of 115200. + +It is recommended to run the script in a dedicated virtual environment. For example, on UNIX +systems you can use `python3 -m venv venv` and then `source venv/bin/activate` to create +and activate a virtual environment. + +After that, you can use + +```sh +pip install -r requirements.txt +``` + +to install all required dependencies. + +After that, it is recommended to use `./image-load.py -h` to get an overview of some options. +The flash loader uses the UART0 with the Pins PA8 (RX) and PA9 (TX) interface of the VA108xx to perform CCSDS based +communication. The Python image loader application will search for a file named `loader.toml` and +use the `serial_port` key to determine the serial port to use for serial communication. + +### Examples + +You can use + +```sh +./image-loader.py -p +``` + +to send a ping an verify the connection. + +You can use + +```sh +cd flashloader/slot-a-blinky +cargo build --release +cd ../.. +./image-loader.py -t a ./slot-a-blinky/target/thumbv6m-none-eabi/release/slot-a-blinky +``` + +to build the slot A sample application and upload it to a running flash loader application +to write it to slot A. + +You can use + +```sh +./image-loader.py -s a +``` + +to select the Slot A as a boot slot. The boot slot is stored in a reserved section in EEPROM +and will be read and used by the bootloader to determine which slot to boot. + +You can use + +```sh +./image-loader.py -c -t a +``` + +to corrupt the image A and test that it switches to image B after a failed CRC check instead. diff --git a/va108xx/flashloader/image-loader.py b/va108xx/flashloader/image-loader.py new file mode 100755 index 0000000..0c22c4e --- /dev/null +++ b/va108xx/flashloader/image-loader.py @@ -0,0 +1,476 @@ +#!/usr/bin/env python3 +from typing import List, Tuple +from spacepackets.ecss.defs import PusService +from spacepackets.ecss.tm import PusTm +import toml +import struct +import logging +import argparse +import time +import enum +from com_interface import ComInterface +from com_interface.serial_base import SerialCfg +from com_interface.serial_cobs import SerialCobsComIF +from crcmod.predefined import PredefinedCrc +from spacepackets.ecss.tc import PusTc +from spacepackets.ecss.pus_verificator import PusVerificator, StatusField +from spacepackets.ecss.pus_1_verification import Service1Tm, UnpackParams +from spacepackets.seqcount import SeqCountProvider +from pathlib import Path +import dataclasses +from elftools.elf.elffile import ELFFile + + +BAUD_RATE = 115200 + +BOOTLOADER_START_ADDR = 0x0 +BOOTLOADER_END_ADDR = 0x3000 +BOOTLOADER_CRC_ADDR = BOOTLOADER_END_ADDR - 2 +BOOTLOADER_MAX_SIZE = BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 2 + +APP_A_START_ADDR = 0x3000 +APP_B_END_ADDR = 0x20000 - 8 +IMG_SLOT_SIZE = (APP_B_END_ADDR - APP_A_START_ADDR) // 2 + +APP_A_END_ADDR = APP_A_START_ADDR + IMG_SLOT_SIZE +# The actual size of the image which is relevant for CRC calculation. +APP_A_SIZE_ADDR = APP_A_END_ADDR - 8 +APP_A_CRC_ADDR = APP_A_END_ADDR - 4 +APP_A_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8 + +APP_B_START_ADDR = APP_A_END_ADDR +# The actual size of the image which is relevant for CRC calculation. +APP_B_SIZE_ADDR = APP_B_END_ADDR - 8 +APP_B_CRC_ADDR = APP_B_END_ADDR - 4 +APP_B_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8 + + +CHUNK_SIZE = 400 + +MEMORY_SERVICE = 6 +ACTION_SERVICE = 8 + +RAW_MEMORY_WRITE_SUBSERVICE = 2 +BOOT_NVM_MEMORY_ID = 1 +PING_PAYLOAD_SIZE = 0 + + +class ActionId(enum.IntEnum): + CORRUPT_APP_A = 128 + CORRUPT_APP_B = 129 + SET_BOOT_SLOT = 130 + + +_LOGGER = logging.getLogger(__name__) +SEQ_PROVIDER = SeqCountProvider(bit_width=14) + + +@dataclasses.dataclass +class LoadableSegment: + name: str + offset: int + size: int + data: bytes + + +class Target(enum.Enum): + BOOTLOADER = 0 + APP_A = 1 + APP_B = 2 + + +class AppSel(enum.IntEnum): + APP_A = 0 + APP_B = 1 + + +class ImageLoader: + def __init__(self, com_if: ComInterface, verificator: PusVerificator) -> None: + self.com_if = com_if + self.verificator = verificator + + def handle_boot_sel_cmd(self, target: AppSel): + _LOGGER.info("Sending ping command") + action_tc = PusTc( + apid=0x00, + service=PusService.S8_FUNC_CMD, + subservice=ActionId.SET_BOOT_SLOT, + seq_count=SEQ_PROVIDER.get_and_increment(), + app_data=bytes([target]), + ) + self.verificator.add_tc(action_tc) + self.com_if.send(bytes(action_tc.pack())) + self.await_for_command_copletion("boot image selection command") + + def handle_ping_cmd(self): + _LOGGER.info("Sending ping command") + ping_tc = PusTc( + apid=0x00, + service=PusService.S17_TEST, + subservice=1, + seq_count=SEQ_PROVIDER.get_and_increment(), + app_data=bytes(PING_PAYLOAD_SIZE), + ) + self.verificator.add_tc(ping_tc) + self.com_if.send(bytes(ping_tc.pack())) + self.await_for_command_copletion("ping command") + + def await_for_command_copletion(self, context: str): + done = False + now = time.time() + while time.time() - now < 2.0: + if not self.com_if.data_available(): + time.sleep(0.2) + continue + for reply in self.com_if.receive(): + result = self.verificator.add_tm( + Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0)) + ) + if result is not None and result.completed: + _LOGGER.info(f"received {context} reply") + done = True + if done: + break + if not done: + _LOGGER.warning(f"no {context} reply received") + + def handle_corruption_cmd(self, target: Target): + if target == Target.BOOTLOADER: + _LOGGER.error("can not corrupt bootloader") + if target == Target.APP_A: + self.send_tc( + PusTc( + apid=0, + service=ACTION_SERVICE, + subservice=ActionId.CORRUPT_APP_A, + ), + ) + if target == Target.APP_B: + self.send_tc( + PusTc( + apid=0, + service=ACTION_SERVICE, + subservice=ActionId.CORRUPT_APP_B, + ), + ) + + def handle_flash_cmd(self, target: Target, file_path: Path) -> int: + loadable_segments = [] + _LOGGER.info("Parsing ELF file for loadable sections") + total_size = 0 + loadable_segments, total_size = create_loadable_segments(target, file_path) + check_segments(target, total_size) + print_segments_info(target, loadable_segments, total_size, file_path) + result = self._perform_flashing_algorithm(loadable_segments) + if result != 0: + return result + self._crc_and_app_size_postprocessing(target, total_size, loadable_segments) + return 0 + + def _perform_flashing_algorithm( + self, + loadable_segments: List[LoadableSegment], + ) -> int: + # Perform the flashing algorithm. + for segment in loadable_segments: + segment_end = segment.offset + segment.size + current_addr = segment.offset + pos_in_segment = 0 + while pos_in_segment < segment.size: + next_chunk_size = min(segment_end - current_addr, CHUNK_SIZE) + data = segment.data[pos_in_segment : pos_in_segment + next_chunk_size] + next_packet = pack_memory_write_command(current_addr, data) + _LOGGER.info( + f"Sending memory write command for address {current_addr:#08x} and data with " + f"length {len(data)}" + ) + self.verificator.add_tc(next_packet) + self.com_if.send(bytes(next_packet.pack())) + current_addr += next_chunk_size + pos_in_segment += next_chunk_size + start_time = time.time() + while True: + if time.time() - start_time > 1.0: + _LOGGER.error("Timeout while waiting for reply") + return -1 + data_available = self.com_if.data_available(0.1) + done = False + if not data_available: + continue + replies = self.com_if.receive() + for reply in replies: + tm = PusTm.unpack(reply, 0) + if tm.service != 1: + continue + service_1_tm = Service1Tm.from_tm(tm, UnpackParams(0)) + check_result = self.verificator.add_tm(service_1_tm) + # We could send after we have received the step reply, but that can + # somehow lead to overrun errors. I think it's okay to do it like + # this as long as the flash loader only uses polling.. + if ( + check_result is not None + and check_result.status.completed == StatusField.SUCCESS + ): + done = True + + # This is an optimized variant, but I think the small delay is not an issue. + """ + if ( + check_result is not None + and check_result.status.step == StatusField.SUCCESS + and len(check_result.status.step_list) == 1 + ): + done = True + """ + self.verificator.remove_completed_entries() + if done: + break + return 0 + + def _crc_and_app_size_postprocessing( + self, + target: Target, + total_size: int, + loadable_segments: List[LoadableSegment], + ): + if target == Target.BOOTLOADER: + _LOGGER.info("Blanking the bootloader checksum") + # Blank the checksum. For the bootloader, the bootloader will calculate the + # checksum itself on the initial run. + checksum_write_packet = pack_memory_write_command( + BOOTLOADER_CRC_ADDR, bytes([0x00, 0x00]) + ) + self.send_tc(checksum_write_packet) + else: + crc_addr = None + size_addr = None + if target == Target.APP_A: + crc_addr = APP_A_CRC_ADDR + size_addr = APP_A_SIZE_ADDR + elif target == Target.APP_B: + crc_addr = APP_B_CRC_ADDR + size_addr = APP_B_SIZE_ADDR + assert crc_addr is not None + assert size_addr is not None + _LOGGER.info(f"Writing app size {total_size} at address {size_addr:#08x}") + size_write_packet = pack_memory_write_command( + size_addr, struct.pack("!I", total_size) + ) + self.com_if.send(bytes(size_write_packet.pack())) + time.sleep(0.2) + crc_calc = PredefinedCrc("crc-ccitt-false") + for segment in loadable_segments: + crc_calc.update(segment.data) + checksum = crc_calc.digest() + _LOGGER.info( + f"Writing checksum 0x[{checksum.hex(sep=',')}] at address {crc_addr:#08x}" + ) + self.send_tc(pack_memory_write_command(crc_addr, checksum)) + + def send_tc(self, tc: PusTc): + self.com_if.send(bytes(tc.pack())) + + +def main() -> int: + print("Python VA108XX Image Loader Application") + logging.basicConfig( + format="[%(asctime)s] [%(levelname)s] %(message)s", level=logging.DEBUG + ) + parser = argparse.ArgumentParser( + prog="image-loader", description="Python VA416XX Image Loader Application" + ) + parser.add_argument("-p", "--ping", action="store_true", help="Send ping command") + parser.add_argument( + "-s", "--sel", choices=["a", "b"], help="Set boot slot (Slot A or B)" + ) + parser.add_argument("-c", "--corrupt", action="store_true", help="Corrupt a target") + parser.add_argument( + "-t", + "--target", + choices=["bl", "a", "b"], + help="Target (Bootloader or slot A or B)", + ) + parser.add_argument( + "path", nargs="?", default=None, help="Path to the App to flash" + ) + args = parser.parse_args() + serial_port = None + if Path("loader.toml").exists(): + with open("loader.toml", "r") as toml_file: + parsed_toml = toml.loads(toml_file.read()) + if "serial_port" in parsed_toml: + serial_port = parsed_toml["serial_port"] + if serial_port is None: + serial_port = input("Please specify the serial port manually: ") + serial_cfg = SerialCfg( + com_if_id="ser_cobs", + serial_port=serial_port, + baud_rate=BAUD_RATE, + polling_frequency=0.1, + ) + verificator = PusVerificator() + com_if = SerialCobsComIF(serial_cfg) + com_if.open() + target = None + if args.target == "bl": + target = Target.BOOTLOADER + elif args.target == "a": + target = Target.APP_A + elif args.target == "b": + target = Target.APP_B + + boot_sel = None + if args.sel: + if args.sel == "a": + boot_sel = AppSel.APP_A + elif args.sel == "b": + boot_sel = AppSel.APP_B + + image_loader = ImageLoader(com_if, verificator) + file_path = None + result = -1 + if args.ping: + image_loader.handle_ping_cmd() + com_if.close() + return 0 + if args.sel and boot_sel is not None: + image_loader.handle_boot_sel_cmd(boot_sel) + if target: + if not args.corrupt: + if not args.path: + _LOGGER.error("App Path needs to be specified for the flash process") + file_path = Path(args.path) + if not file_path.exists(): + _LOGGER.error("File does not exist") + if args.corrupt: + if not target: + _LOGGER.error("target for corruption command required") + com_if.close() + return -1 + image_loader.handle_corruption_cmd(target) + else: + if file_path is not None: + assert target is not None + result = image_loader.handle_flash_cmd(target, file_path) + + com_if.close() + return result + + +def create_loadable_segments( + target: Target, file_path: Path +) -> Tuple[List[LoadableSegment], int]: + loadable_segments = [] + total_size = 0 + with open(file_path, "rb") as app_file: + elf_file = ELFFile(app_file) + + for idx, segment in enumerate(elf_file.iter_segments("PT_LOAD")): + if segment.header.p_filesz == 0: + continue + # Basic validity checks of the base addresses. + if idx == 0: + if ( + target == Target.BOOTLOADER + and segment.header.p_paddr != BOOTLOADER_START_ADDR + ): + raise ValueError( + f"detected possibly invalid start address {segment.header.p_paddr:#08x} for " + f"bootloader, expected {BOOTLOADER_START_ADDR}" + ) + if ( + target == Target.APP_A + and segment.header.p_paddr != APP_A_START_ADDR + ): + raise ValueError( + f"detected possibly invalid start address {segment.header.p_paddr:#08x} for " + f"App A, expected {APP_A_START_ADDR}" + ) + if ( + target == Target.APP_B + and segment.header.p_paddr != APP_B_START_ADDR + ): + raise ValueError( + f"detected possibly invalid start address {segment.header.p_paddr:#08x} for " + f"App B, expected {APP_B_START_ADDR}" + ) + name = None + for section in elf_file.iter_sections(): + if ( + section.header.sh_offset == segment.header.p_offset + and section.header.sh_size > 0 + ): + name = section.name + if name is None: + _LOGGER.warning("no fitting section found for segment") + continue + # print(f"Segment Addr: {segment.header.p_paddr}") + # print(f"Segment Offset: {segment.header.p_offset}") + # print(f"Segment Filesize: {segment.header.p_filesz}") + loadable_segments.append( + LoadableSegment( + name=name, + offset=segment.header.p_paddr, + size=segment.header.p_filesz, + data=segment.data(), + ) + ) + total_size += segment.header.p_filesz + return loadable_segments, total_size + + +def check_segments( + target: Target, + total_size: int, +): + # Set context string and perform basic sanity checks. + if target == Target.BOOTLOADER and total_size > BOOTLOADER_MAX_SIZE: + raise ValueError( + f"provided bootloader app larger than allowed {total_size} bytes" + ) + elif target == Target.APP_A and total_size > APP_A_MAX_SIZE: + raise ValueError(f"provided App A larger than allowed {total_size} bytes") + elif target == Target.APP_B and total_size > APP_B_MAX_SIZE: + raise ValueError(f"provided App B larger than allowed {total_size} bytes") + + +def print_segments_info( + target: Target, + loadable_segments: List[LoadableSegment], + total_size: int, + file_path: Path, +): + # Set context string and perform basic sanity checks. + if target == Target.BOOTLOADER: + context_str = "Bootloader" + elif target == Target.APP_A: + context_str = "App Slot A" + elif target == Target.APP_B: + context_str = "App Slot B" + _LOGGER.info(f"Flashing {context_str} with image {file_path} (size {total_size})") + for idx, segment in enumerate(loadable_segments): + _LOGGER.info( + f"Loadable section {idx} {segment.name} with offset {segment.offset:#08x} and " + f"size {segment.size}" + ) + + +def pack_memory_write_command(addr: int, data: bytes) -> PusTc: + app_data = bytearray() + app_data.append(BOOT_NVM_MEMORY_ID) + # N parameter is always 1 here. + app_data.append(1) + app_data.extend(struct.pack("!I", addr)) + app_data.extend(struct.pack("!I", len(data))) + app_data.extend(data) + return PusTc( + apid=0, + service=MEMORY_SERVICE, + subservice=RAW_MEMORY_WRITE_SUBSERVICE, + seq_count=SEQ_PROVIDER.get_and_increment(), + app_data=bytes(app_data), + ) + + +if __name__ == "__main__": + main() diff --git a/va108xx/flashloader/loader.toml b/va108xx/flashloader/loader.toml new file mode 100644 index 0000000..008f3de --- /dev/null +++ b/va108xx/flashloader/loader.toml @@ -0,0 +1 @@ +serial_port = "/dev/ttyUSB1" diff --git a/va108xx/flashloader/requirements.txt b/va108xx/flashloader/requirements.txt new file mode 100644 index 0000000..dbcb091 --- /dev/null +++ b/va108xx/flashloader/requirements.txt @@ -0,0 +1,5 @@ +spacepackets == 0.28 +com-interface == 0.1 +toml == 0.10 +pyelftools == 0.31 +crcmod == 1.7 diff --git a/va108xx/flashloader/slot-a-blinky/.gitignore b/va108xx/flashloader/slot-a-blinky/.gitignore new file mode 100644 index 0000000..7f153fc --- /dev/null +++ b/va108xx/flashloader/slot-a-blinky/.gitignore @@ -0,0 +1,2 @@ +/target +/app.map diff --git a/va108xx/flashloader/slot-a-blinky/Cargo.toml b/va108xx/flashloader/slot-a-blinky/Cargo.toml new file mode 100644 index 0000000..fd39c54 --- /dev/null +++ b/va108xx/flashloader/slot-a-blinky/Cargo.toml @@ -0,0 +1,41 @@ +[package] +name = "slot-a-blinky" +version = "0.1.0" +edition = "2021" + +[workspace] + +[dependencies] +cortex-m-rt = "0.7" +panic-rtt-target = { version = "0.1.3" } +rtt-target = { version = "0.5" } +embedded-hal = "1" +va108xx-hal = { version = "0.11" } + +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +# This is problematic for stepping.. +# opt-level = 'z' # <- +overflow-checks = true # <- + +# cargo build/run --release +[profile.release] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = 3 # <- +overflow-checks = false # <- + +[profile.small] +inherits = "release" +codegen-units = 1 +debug-assertions = false # <- +lto = true +opt-level = 'z' # <- +overflow-checks = false # <- +# strip = true # Automatically strip symbols from the binary. diff --git a/va108xx/flashloader/slot-a-blinky/memory.x b/va108xx/flashloader/slot-a-blinky/memory.x new file mode 100644 index 0000000..a9daa25 --- /dev/null +++ b/va108xx/flashloader/slot-a-blinky/memory.x @@ -0,0 +1,11 @@ +/* Special linker script for application slot A with an offset at address 0x3000 */ +MEMORY +{ + FLASH : ORIGIN = 0x00003000, LENGTH = 0xE7FC + RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/va108xx/flashloader/slot-a-blinky/src/main.rs b/va108xx/flashloader/slot-a-blinky/src/main.rs new file mode 100644 index 0000000..332567a --- /dev/null +++ b/va108xx/flashloader/slot-a-blinky/src/main.rs @@ -0,0 +1,25 @@ +//! Simple blinky example using the HAL +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer}; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("VA108xx HAL blinky example for App Slot A"); + + let mut dp = pac::Peripherals::take().unwrap(); + let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0); + let porta = PinsA::new(&mut dp.sysconfig, dp.porta); + let mut led1 = porta.pa10.into_readable_push_pull_output(); + + loop { + led1.toggle(); + timer.delay_ms(500); + } +} diff --git a/va108xx/flashloader/slot-b-blinky/.gitignore b/va108xx/flashloader/slot-b-blinky/.gitignore new file mode 100644 index 0000000..7f153fc --- /dev/null +++ b/va108xx/flashloader/slot-b-blinky/.gitignore @@ -0,0 +1,2 @@ +/target +/app.map diff --git a/va108xx/flashloader/slot-b-blinky/Cargo.toml b/va108xx/flashloader/slot-b-blinky/Cargo.toml new file mode 100644 index 0000000..05cea56 --- /dev/null +++ b/va108xx/flashloader/slot-b-blinky/Cargo.toml @@ -0,0 +1,41 @@ +[package] +name = "slot-b-blinky" +version = "0.1.0" +edition = "2021" + +[workspace] + +[dependencies] +cortex-m-rt = "0.7" +panic-rtt-target = { version = "0.1.3" } +rtt-target = { version = "0.5" } +embedded-hal = "1" +va108xx-hal = { version = "0.11" } + +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +# This is problematic for stepping.. +# opt-level = 'z' # <- +overflow-checks = true # <- + +# cargo build/run --release +[profile.release] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = 3 # <- +overflow-checks = false # <- + +[profile.small] +inherits = "release" +codegen-units = 1 +debug-assertions = false # <- +lto = true +opt-level = 'z' # <- +overflow-checks = false # <- +# strip = true # Automatically strip symbols from the binary. diff --git a/va108xx/flashloader/slot-b-blinky/memory.x b/va108xx/flashloader/slot-b-blinky/memory.x new file mode 100644 index 0000000..f5ac660 --- /dev/null +++ b/va108xx/flashloader/slot-b-blinky/memory.x @@ -0,0 +1,11 @@ +/* Special linker script for application slot B */ +MEMORY +{ + FLASH : ORIGIN = 0x000117FC, LENGTH = 0xE7FC + RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/va108xx/flashloader/slot-b-blinky/src/main.rs b/va108xx/flashloader/slot-b-blinky/src/main.rs new file mode 100644 index 0000000..5a42407 --- /dev/null +++ b/va108xx/flashloader/slot-b-blinky/src/main.rs @@ -0,0 +1,25 @@ +//! Simple blinky example using the HAL +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer}; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("VA108xx HAL blinky example for App Slot B"); + + let mut dp = pac::Peripherals::take().unwrap(); + let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0); + let porta = PinsA::new(&mut dp.sysconfig, dp.porta); + let mut led2 = porta.pa7.into_readable_push_pull_output(); + + loop { + led2.toggle(); + timer.delay_ms(1000); + } +} diff --git a/va108xx/flashloader/src/main.rs b/va108xx/flashloader/src/main.rs new file mode 100644 index 0000000..f93c657 --- /dev/null +++ b/va108xx/flashloader/src/main.rs @@ -0,0 +1,465 @@ +//! Vorago flashloader which can be used to flash image A and image B via a simple +//! low-level CCSDS memory interface via a UART interface. +#![no_main] +#![no_std] + +use defmt_rtt as _; // global logger +use num_enum::TryFromPrimitive; +use panic_probe as _; +use ringbuf::{ + traits::{Consumer, Observer, Producer}, + StaticRb, +}; +use va108xx_hal::prelude::*; + +const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000); + +const MAX_TC_SIZE: usize = 524; +const MAX_TC_FRAME_SIZE: usize = cobs::max_encoding_length(MAX_TC_SIZE); + +const MAX_TM_SIZE: usize = 128; +const MAX_TM_FRAME_SIZE: usize = cobs::max_encoding_length(MAX_TM_SIZE); + +const UART_BAUDRATE: u32 = 115200; +const BOOT_NVM_MEMORY_ID: u8 = 1; +const RX_DEBUGGING: bool = false; + +pub enum ActionId { + CorruptImageA = 128, + CorruptImageB = 129, + SetBootSlot = 130, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq, TryFromPrimitive, defmt::Format)] +#[repr(u8)] +enum AppSel { + A = 0, + B = 1, +} + +// Larger buffer for TC to be able to hold the possibly large memory write packets. +const BUF_RB_SIZE_TC: usize = 1024; +const SIZES_RB_SIZE_TC: usize = 16; + +const BUF_RB_SIZE_TM: usize = 256; +const SIZES_RB_SIZE_TM: usize = 16; + +pub struct RingBufWrapper { + pub buf: StaticRb, + pub sizes: StaticRb, +} + +pub const APP_A_START_ADDR: u32 = 0x3000; +pub const APP_A_END_ADDR: u32 = 0x117FC; +pub const APP_B_START_ADDR: u32 = APP_A_END_ADDR; +pub const APP_B_END_ADDR: u32 = 0x20000; + +pub const PREFERRED_SLOT_OFFSET: u32 = 0x20000 - 1; + +#[rtic::app(device = pac, dispatchers = [OC20, OC21, OC22])] +mod app { + use super::*; + use cortex_m::asm; + use embedded_io::Write; + use rtic::Mutex; + use rtic_monotonics::systick::prelude::*; + use satrs::pus::verification::{FailParams, VerificationReportCreator}; + use spacepackets::ecss::PusServiceId; + use spacepackets::ecss::{ + tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket, + }; + use va108xx_hal::pins::PinsA; + use va108xx_hal::spi::SpiClockConfig; + use va108xx_hal::uart::InterruptContextTimeoutOrMaxSize; + use va108xx_hal::{pac, uart, InterruptConfig}; + use vorago_reb1::m95m01::M95M01; + + #[derive(Default, Debug, Copy, Clone, PartialEq, Eq)] + pub enum CobsReaderStates { + #[default] + WaitingForStart, + WatingForEnd, + FrameOverflow, + } + + #[local] + struct Local { + uart_rx: uart::RxWithInterrupt, + uart_tx: uart::Tx, + rx_context: InterruptContextTimeoutOrMaxSize, + verif_reporter: VerificationReportCreator, + nvm: M95M01, + } + + #[shared] + struct Shared { + // Having this shared allows multiple tasks to generate telemetry. + tm_rb: RingBufWrapper, + tc_rb: RingBufWrapper, + } + + rtic_monotonics::systick_monotonic!(Mono, 1000); + + #[init] + fn init(cx: init::Context) -> (Shared, Local) { + defmt::println!("-- Vorago flashloader --"); + + Mono::start(cx.core.SYST, SYSCLK_FREQ.raw()); + + let dp = cx.device; + let spi_clock_config = SpiClockConfig::new(2, 4); + let nvm = M95M01::new(dp.spic, spi_clock_config); + + let gpioa = PinsA::new(dp.porta); + let tx = gpioa.pa9; + let rx = gpioa.pa8; + + let irq_uart = uart::Uart::new_with_interrupt( + dp.uarta, + tx, + rx, + SYSCLK_FREQ, + UART_BAUDRATE.Hz().into(), + InterruptConfig::new(pac::Interrupt::OC0, true, true), + ) + .unwrap(); + let (tx, rx) = irq_uart.split(); + // Unwrap is okay, we explicitely set the interrupt ID. + let mut rx = rx.into_rx_with_irq(); + + let verif_reporter = VerificationReportCreator::new(0).unwrap(); + + let mut rx_context = InterruptContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE); + rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context) + .expect("initiating UART RX failed"); + pus_tc_handler::spawn().unwrap(); + pus_tm_tx_handler::spawn().unwrap(); + ( + Shared { + tc_rb: RingBufWrapper { + buf: StaticRb::default(), + sizes: StaticRb::default(), + }, + tm_rb: RingBufWrapper { + buf: StaticRb::default(), + sizes: StaticRb::default(), + }, + }, + Local { + uart_rx: rx, + uart_tx: tx, + rx_context, + verif_reporter, + nvm, + }, + ) + } + + // `shared` cannot be accessed from this context + #[idle] + fn idle(_cx: idle::Context) -> ! { + loop { + asm::nop(); + } + } + + // This is the interrupt handler to read all bytes received on the UART0. + #[task( + binds = OC0, + local = [ + cnt: u32 = 0, + rx_buf: [u8; MAX_TC_FRAME_SIZE] = [0; MAX_TC_FRAME_SIZE], + rx_context, + uart_rx, + ], + shared = [tc_rb] + )] + fn uart_rx_irq(mut cx: uart_rx_irq::Context) { + match cx + .local + .uart_rx + .on_interrupt_max_size_or_timeout_based(cx.local.rx_context, cx.local.rx_buf) + { + Ok(result) => { + if RX_DEBUGGING { + defmt::debug!("RX Info: {:?}", cx.local.rx_context); + defmt::debug!("RX Result: {:?}", result); + } + if result.complete() { + // Check frame validity (must have COBS format) and decode the frame. + // Currently, we expect a full frame or a frame received through a timeout + // to be one COBS frame. We could parse for multiple COBS packets in one + // frame, but the additional complexity is not necessary here.. + if cx.local.rx_buf[0] == 0 && cx.local.rx_buf[result.bytes_read - 1] == 0 { + let decoded_size = + cobs::decode_in_place(&mut cx.local.rx_buf[1..result.bytes_read]); + if decoded_size.is_err() { + defmt::warn!("COBS decoding failed"); + } else { + let decoded_size = decoded_size.unwrap(); + let mut tc_rb_full = false; + cx.shared.tc_rb.lock(|rb| { + if rb.sizes.vacant_len() >= 1 && rb.buf.vacant_len() >= decoded_size + { + rb.sizes.try_push(decoded_size).unwrap(); + rb.buf.push_slice(&cx.local.rx_buf[1..1 + decoded_size]); + } else { + tc_rb_full = true; + } + }); + if tc_rb_full { + defmt::warn!("COBS TC queue full"); + } + } + } else { + defmt::warn!( + "COBS frame with invalid format, start and end bytes are not 0" + ); + } + + // Initiate next transfer. + cx.local + .uart_rx + .read_fixed_len_or_timeout_based_using_irq(cx.local.rx_context) + .expect("read operation failed"); + } + if result.has_errors() { + defmt::warn!("UART error: {:?}", result.errors.unwrap()); + } + } + Err(e) => { + defmt::warn!("UART error: {:?}", e); + } + } + } + + #[task( + priority = 2, + local=[ + tc_buf: [u8; MAX_TC_SIZE] = [0; MAX_TC_SIZE], + readback_buf: [u8; MAX_TC_SIZE] = [0; MAX_TC_SIZE], + src_data_buf: [u8; 16] = [0; 16], + verif_buf: [u8; 32] = [0; 32], + nvm, + verif_reporter + ], + shared=[tm_rb, tc_rb] + )] + async fn pus_tc_handler(mut cx: pus_tc_handler::Context) { + loop { + // Try to read a TC from the ring buffer. + let packet_len = cx.shared.tc_rb.lock(|rb| rb.sizes.try_pop()); + if packet_len.is_none() { + // Small delay, TCs might arrive very quickly. + Mono::delay(20.millis()).await; + continue; + } + let packet_len = packet_len.unwrap(); + defmt::info!("received packet with length {}", packet_len); + let popped_packet_len = cx + .shared + .tc_rb + .lock(|rb| rb.buf.pop_slice(&mut cx.local.tc_buf[0..packet_len])); + assert_eq!(popped_packet_len, packet_len); + // Read a telecommand, now handle it. + handle_valid_pus_tc(&mut cx); + } + } + + fn handle_valid_pus_tc(cx: &mut pus_tc_handler::Context) { + let pus_tc = PusTcReader::new(cx.local.tc_buf); + if pus_tc.is_err() { + defmt::warn!("PUS TC error: {}", pus_tc.unwrap_err()); + return; + } + let pus_tc = pus_tc.unwrap(); + let mut write_and_send = |tm: &PusTmCreator| { + let written_size = tm.write_to_bytes(cx.local.verif_buf).unwrap(); + cx.shared.tm_rb.lock(|prod| { + prod.sizes.try_push(tm.len_written()).unwrap(); + prod.buf.push_slice(&cx.local.verif_buf[0..written_size]); + }); + }; + let request_id = VerificationReportCreator::read_request_id_from_tc(&pus_tc); + let tm = cx + .local + .verif_reporter + .acceptance_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("acceptance success failed"); + write_and_send(&tm); + + let tm = cx + .local + .verif_reporter + .start_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("acceptance success failed"); + write_and_send(&tm); + + if pus_tc.service() == PusServiceId::Action as u8 { + let mut corrupt_image = |base_addr: u32| { + let mut buf = [0u8; 4]; + cx.local + .nvm + .read(base_addr as usize + 32, &mut buf) + .expect("reading from NVM failed"); + buf[0] += 1; + cx.local + .nvm + .write(base_addr as usize + 32, &buf) + .expect("writing to NVM failed"); + let tm = cx + .local + .verif_reporter + .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("completion success failed"); + write_and_send(&tm); + }; + if pus_tc.subservice() == ActionId::CorruptImageA as u8 { + defmt::info!("corrupting App Image A"); + corrupt_image(APP_A_START_ADDR); + } + if pus_tc.subservice() == ActionId::CorruptImageB as u8 { + defmt::info!("corrupting App Image B"); + corrupt_image(APP_B_START_ADDR); + } + if pus_tc.subservice() == ActionId::SetBootSlot as u8 { + if pus_tc.app_data().is_empty() { + defmt::warn!("App data for preferred image command too short"); + } + let app_sel_result = AppSel::try_from(pus_tc.app_data()[0]); + if app_sel_result.is_err() { + defmt::warn!("Invalid app selection value: {}", pus_tc.app_data()[0]); + } + defmt::info!( + "received boot selection command with app select: {:?}", + app_sel_result.unwrap() + ); + cx.local + .nvm + .write(PREFERRED_SLOT_OFFSET as usize, &[pus_tc.app_data()[0]]) + .expect("writing to NVM failed"); + let tm = cx + .local + .verif_reporter + .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("completion success failed"); + write_and_send(&tm); + } + } + if pus_tc.service() == PusServiceId::Test as u8 && pus_tc.subservice() == 1 { + defmt::info!("received ping TC"); + let tm = cx + .local + .verif_reporter + .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("completion success failed"); + write_and_send(&tm); + } else if pus_tc.service() == PusServiceId::MemoryManagement as u8 { + let tm = cx + .local + .verif_reporter + .step_success( + cx.local.src_data_buf, + &request_id, + 0, + 0, + &[], + EcssEnumU8::new(0), + ) + .expect("step success failed"); + write_and_send(&tm); + // Raw memory write TC + if pus_tc.subservice() == 2 { + let app_data = pus_tc.app_data(); + if app_data.len() < 10 { + defmt::warn!( + "app data for raw memory write is too short: {}", + app_data.len() + ); + } + let memory_id = app_data[0]; + if memory_id != BOOT_NVM_MEMORY_ID { + defmt::warn!("memory ID {} not supported", memory_id); + // TODO: Error reporting + return; + } + let offset = u32::from_be_bytes(app_data[2..6].try_into().unwrap()); + let data_len = u32::from_be_bytes(app_data[6..10].try_into().unwrap()); + if 10 + data_len as usize > app_data.len() { + defmt::warn!( + "invalid data length {} for raw mem write detected", + data_len + ); + // TODO: Error reporting + return; + } + let data = &app_data[10..10 + data_len as usize]; + defmt::info!("writing {} bytes at offset {} to NVM", data_len, offset); + cx.local + .nvm + .write(offset as usize, data) + .expect("writing to NVM failed"); + let tm = if !cx + .local + .nvm + .verify(offset as usize, data) + .expect("NVM verification failed") + { + defmt::warn!("verification of data written to NVM failed"); + cx.local + .verif_reporter + .completion_failure( + cx.local.src_data_buf, + &request_id, + 0, + 0, + FailParams::new(&[], &EcssEnumU8::new(0), &[]), + ) + .expect("completion success failed") + } else { + cx.local + .verif_reporter + .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("completion success failed") + }; + write_and_send(&tm); + defmt::info!("NVM operation done"); + } + } + } + + #[task( + priority = 1, + local=[ + read_buf: [u8;MAX_TM_SIZE] = [0; MAX_TM_SIZE], + encoded_buf: [u8;MAX_TM_FRAME_SIZE] = [0; MAX_TM_FRAME_SIZE], + uart_tx, + ], + shared=[tm_rb] + )] + async fn pus_tm_tx_handler(mut cx: pus_tm_tx_handler::Context) { + loop { + let mut occupied_len = cx.shared.tm_rb.lock(|rb| rb.sizes.occupied_len()); + while occupied_len > 0 { + let next_size = cx.shared.tm_rb.lock(|rb| { + let next_size = rb.sizes.try_pop().unwrap(); + rb.buf.pop_slice(&mut cx.local.read_buf[0..next_size]); + next_size + }); + cx.local.encoded_buf[0] = 0; + let send_size = cobs::encode( + &cx.local.read_buf[0..next_size], + &mut cx.local.encoded_buf[1..], + ); + cx.local.encoded_buf[send_size + 1] = 0; + cx.local + .uart_tx + .write_all(&cx.local.encoded_buf[0..send_size + 2]) + .unwrap(); + occupied_len -= 1; + Mono::delay(2.millis()).await; + } + Mono::delay(50.millis()).await; + } + } +} diff --git a/va108xx/jlink-gdb.sh b/va108xx/jlink-gdb.sh new file mode 100755 index 0000000..6233f1f --- /dev/null +++ b/va108xx/jlink-gdb.sh @@ -0,0 +1,3 @@ +#!/bin/bash +JLinkGDBServer -select USB -device VA10820 -endian little -if JTAG -speed auto \ + -LocalhostOnly -jtagconf -1,-1 diff --git a/va108xx/jlink.gdb b/va108xx/jlink.gdb new file mode 100644 index 0000000..20ff2d5 --- /dev/null +++ b/va108xx/jlink.gdb @@ -0,0 +1,10 @@ +target remote localhost:2331 + +monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va108xx/memory.x b/va108xx/memory.x new file mode 100644 index 0000000..1ca0e97 --- /dev/null +++ b/va108xx/memory.x @@ -0,0 +1,10 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 0x20000 /* 128K */ + RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/va108xx/scripts/VA108xx_Series.yaml b/va108xx/scripts/VA108xx_Series.yaml new file mode 100644 index 0000000..42b7393 --- /dev/null +++ b/va108xx/scripts/VA108xx_Series.yaml @@ -0,0 +1,173 @@ +name: VA108xx Series +generated_from_pack: true +pack_file_release: 1.4.0 +variants: +- name: VA108xx + cores: + - name: main + type: armv6m + core_access_options: !Arm + ap: 0 + psel: 0x0 + jtag_tap: 1 + memory_map: + - !Ram + name: DRAM + range: + start: 0x10000000 + end: 0x10008000 + cores: + - main + - !Nvm + name: NVM + range: + start: 0x0 + end: 0x20000 + cores: + - main + access: + write: false + boot: true + flash_algorithms: + - va108xx_fm25v20a_fram_128kb_prog + - va108xx_m95m01_128kb_prog + - va108xx_mr25h10_1mb_prog + - va108xx_ttflash_prog +- name: VA108xx_RAM + cores: + - name: main + type: armv6m + core_access_options: !Arm + ap: 0 + psel: 0x0 + jtag_tap: 1 + memory_map: + - !Ram + name: DRAM + range: + start: 0x10000000 + end: 0x10008000 + cores: + - main + - !Ram + name: IRAM + range: + start: 0x0 + end: 0x20000 + cores: + - main + access: + write: false + boot: true +flash_algorithms: +- name: va108xx_fm25v20a_fram_128kb_prog + description: VA108_FM25V20A_FRAM_128KB + instructions: QLpwR8C6cEdkSMFoyQf80MFoyQb81AMhwWJwR3BHALVgSV9IyGNdSgIgEGFeSBBgXkhQYAMg0GL/9+b/XEiQYNBowAf80AEgkGDAB5Bg//fb/wAgAL0Atf/31v9PSFRJgWDBaMkH/NABIYFg/SGBYMkHgWD/98j/ACAAvXC1ACJLTUZLAiYURp1g//e9/xACnmABAgkOmWAABAAOmGCcYAAg2WiJB/zVnGBAHP8o+NPYaIAH/NUBIMAHmGD/96T/ASBAAlIcgkLe0wAgcL0AIHBHPLUFRgAgC0YAkP/3lP8uTDNIoGD/94//AiCgYCgCAA6gYCgEAA6gYOiyoGAL4OBogAf81RB4oGCgaAGQAJhSHEAcWx4AkAEr8dHgaIAH/NUQeAEhyQdAGKBg//ds/wAgPL0AIHBH8LUORgVG//dj/xZIAyGBYCkCCQ6BYCkECQ6BYOmygWAAIxlGgWDEaGQH/NWEaFscBCv32wAjDOCBYMRoZAf81YRoF3jksqdCAdDoGPC9UhxbHLNC8NMBIckHgWD/9zj/qBnwvQAgBUD///8AQAAAQAcEAACCAgAABgAAgAAAAAA= + pc_init: 0x1f + pc_uninit: 0x57 + pc_program_page: 0xd3 + pc_erase_sector: 0xcf + pc_erase_all: 0x7d + data_section_offset: 0x1b4 + flash_properties: + address_range: + start: 0x0 + end: 0x20000 + page_size: 0x100 + erased_byte_value: 0x0 + program_page_timeout: 3000 + erase_sector_timeout: 3000 + sectors: + - size: 0x2000 + address: 0x0 +- name: va108xx_m95m01_128kb_prog + description: VA108XX_M95M01_128KB + default: true + instructions: QLpwR8C6cEd6SMFoyQf80MFoyQb81AMhwWJwR3i1//fz/wUk5QcAJnJIc0sDIoRghWDBaMkH/NDBaEkH/NWBaACRwWhJB/zVgWgAkckHwmIH0ACWAL8AmUkcAJGZQvnb5ed4vQC1ZklkSMhjYUoCIBBhZEgQYGRIUGADINBi//fD/2JIkGD/97//ASCQYMAHkGD/97n/ACAAvQC1//e+///3sv9TSllIkGD/963/ASCQYFZI9zCQYP/3pv8AIAC98LUAJFFPS00mRq9g//ec/yACAiGpYAECCQ6pYAAEAA6oYK5gACDpaIkH/NWuYEAc/yj40+hogAf81QEgwAeoYP/3gv//94r/ASBAAmQchELb0wAg8L0AIHBHfLUGRgAgFEYNRgCQ//d5///3bf8xSjZIkGD/92j/AiCQYDACAA6QYDAEAA6QYPCykGAL4NBogAf81SB4kGCQaAGQAJhkHEAcbR4AkAEt8dHQaIAH/NUgeAEhyQdAGJBg//dF///3Tf8AIHy9ACBwR/C1FEYORgVG//dD///3N/8WSQMgiGAoAgAOiGAoBAAOiGDosohgACMaRopgyGhAB/zViGhbHAQr99sAIAzgimDLaFsH/NWLaCd427KfQgHQKBjwvUAcZBywQvDTASDAB4hg//cM/6gZ8L0AIAVAUMMAAP///wBAAABABwQAAIICAAAGAACAAAAAAA== + pc_init: 0x65 + pc_uninit: 0x9b + pc_program_page: 0x11b + pc_erase_sector: 0x117 + pc_erase_all: 0xc1 + data_section_offset: 0x210 + flash_properties: + address_range: + start: 0x0 + end: 0x20000 + page_size: 0x100 + erased_byte_value: 0x0 + program_page_timeout: 3000 + erase_sector_timeout: 3000 + sectors: + - size: 0x2000 + address: 0x0 +- name: va108xx_mr25h10_1mb_prog + description: VA108_MR25H10_1Mb + instructions: QLpwR8C6cEdjSMFoyQf80MFoyQb81AMhwWJwR3BHALVfSV5IyGNcSgIgEGFdSBBgXUhQYAMg0GL/9+b/W0iQYP/34v8BIJBgwAeQYP/33P8AIAC9ALX/99f/T0pTSJBg//fS/wEgkGBQSPcwkGD/98v/ACAAvXC1ACJMTUZLAiYURp1g//fA/xACnmABAgkOmWAABAAOmGCcYAAg2WiJB/zVnGBAHP8o+NPYaIAH/NUBIMAHmGD/96f/ASBAAlIcgkLe0wAgcL0AIHBHPLUFRgAgC0YAkP/3l/8vTDNIoGD/95L/AiCgYCgCAA6gYCgEAA6gYOiyoGAL4OBogAf81RB4oGCgaAGQAJhSHEAcWx4AkAEr8dHgaIAH/NUQeAEhyQdAGKBg//dv/wAgPL0AIHBH8LUORgVG//dm/xZIAyGBYCkCCQ6BYCkECQ6BYOmygWAAIxlGgWDEaGQH/NWEaFscBCv32wAjDOCBYMRoZAf81YRoF3jksqdCAdDoGPC9UhxbHLNC8NMBIckHgWD/9zv/qBnwvQAAACAFQP///wBAAABABwQAAIICAAAGAACAAAAAAA== + pc_init: 0x1f + pc_uninit: 0x55 + pc_program_page: 0xcd + pc_erase_sector: 0xc9 + pc_erase_all: 0x77 + data_section_offset: 0x1b0 + flash_properties: + address_range: + start: 0x0 + end: 0x20000 + page_size: 0x100 + erased_byte_value: 0x0 + program_page_timeout: 10000 + erase_sector_timeout: 10000 + sectors: + - size: 0x2000 + address: 0x0 +- name: va108xx_ttflash_prog + description: VA108_TT_Flash_8MBx + instructions: QLpwR8C6cEd9SMFoyQf80MFoyQb81AMhwWJwR3i1//fz/wUk5QcAJnVIdksDIoRghWDBaMkH/NDBaEkH/NWBaACRwWhJB/zVgWgAkckHwmIH0ACWAL8AmUkcAJGZQvnb5ed4vQC1aUlnSMhjZEoCIBBhZ0gQYGdIUGADINBi//fD/2VIkGD/97//ASCQYAAgkGABIMAHkGD/97b/ACAAvQC1//e7///3r/9VSlpIkGD/96r/ASCQYP0gkGDAB5Bg//ei/wAgAL0Atf/3p///95v/S0hQSYFgT0laMYFg//eT///3m/8AIAC9ELUERv/3lf//94n/QkpHSJBg//eE/yAgkGAgAgAOkGAgBAAOkGABIeCyyQdAGJBg//d////3c/8AIBC9fLUGRgAgFEYNRgCQ//dz///3Z/8xSjZIkGD/92L/AiCQYDACAA6QYDAEAA6QYPCykGAL4NBogAf81SB4kGCQaAGQAJhkHEAcbR4AkAEt8dHQaIAH/NUgeAEhyQdAGJBg//c////3R/8AIHy9ACBwR/C1FEYORgVG//c9///3Mf8WSQMgiGAoAgAOiGAoBAAOiGDosohgACMaRopgyGhAB/zViGhbHAQr99sAIAzgimDLaFsH/NWLaCd427KfQgHQKBjwvUAcZBywQvDTASDAB4hg//cG/6gZ8L0AIAVAUMMAAP///wBAAABABwQAAIICAAAGAACAAAAAAA== + pc_init: 0x65 + pc_uninit: 0xa1 + pc_program_page: 0x127 + pc_erase_sector: 0xeb + pc_erase_all: 0xc9 + data_section_offset: 0x21c + flash_properties: + address_range: + start: 0x0 + end: 0x20000 + page_size: 0x100 + erased_byte_value: 0xff + program_page_timeout: 10000 + erase_sector_timeout: 50000 + sectors: + - size: 0x1000 + address: 0x0 + - size: 0x1000 + address: 0x1000 + - size: 0x1000 + address: 0x2000 + - size: 0x1000 + address: 0x3000 + - size: 0x1000 + address: 0x4000 + - size: 0x1000 + address: 0x5000 + - size: 0x1000 + address: 0x6000 + - size: 0x1000 + address: 0x7000 + - size: 0x1000 + address: 0x8000 + - size: 0x1000 + address: 0x9000 + - size: 0x1000 + address: 0xa000 + - size: 0x1000 + address: 0xb000 + - size: 0x1000 + address: 0xc000 + - size: 0x1000 + address: 0xd000 + - size: 0x1000 + address: 0xe000 + - size: 0x1000 + address: 0xf000 diff --git a/va108xx/scripts/defmt-telnet.sh b/va108xx/scripts/defmt-telnet.sh new file mode 100755 index 0000000..e86688a --- /dev/null +++ b/va108xx/scripts/defmt-telnet.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +# Check if binary path was provided +if [ "$#" -ne 1 ]; then + echo "Usage: $0 " + exit 1 +fi + +BINARY="$1" + +# Check if file exists +if [ ! -f "$BINARY" ]; then + echo "Error: File '$BINARY' not found." + exit 1 +fi + +# Run the command +telnet localhost 19021 | defmt-print -e "$BINARY" diff --git a/va108xx/scripts/memory_app_a.x b/va108xx/scripts/memory_app_a.x new file mode 100644 index 0000000..7bd7260 --- /dev/null +++ b/va108xx/scripts/memory_app_a.x @@ -0,0 +1,10 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00003000, LENGTH = 0xE7F8 /* (128k - 12k) / 2 - 8 */ + RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/va108xx/scripts/memory_app_b.x b/va108xx/scripts/memory_app_b.x new file mode 100644 index 0000000..ae016ad --- /dev/null +++ b/va108xx/scripts/memory_app_b.x @@ -0,0 +1,10 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00011800, LENGTH = 0xE7F8 /* (128k - 12k) / 2 - 8 */ + RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/va108xx/va108xx-embassy/CHANGELOG.md b/va108xx/va108xx-embassy/CHANGELOG.md new file mode 100644 index 0000000..ec06a3e --- /dev/null +++ b/va108xx/va108xx-embassy/CHANGELOG.md @@ -0,0 +1,36 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +## [unreleased] + +## [v0.3.0] 2025-09-03 + +Bumped allowed va108xx-hal to v0.12 + +## [v0.2.1] 2025-03-07 + +- Bumped allowed va108xx-hal to v0.11 + +## [v0.2.0] 2025-02-17 + +- Bumped va108xx-hal to v0.10.0 +- Remove `embassy` module, expose public functions in library root directly + + +## [v0.1.2] and [v0.1.1] 2025-02-13 + +Docs patch + +## [v0.1.0] 2025-02-13 + +Initial release + +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.3.0...HEAD +[v0.3.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.1...va10xx-embassy-v0.3.0 +[v0.2.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.0...va10xx-embassy-v0.2.1 +[v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.1.2...va10xx-embassy-v0.2.0 diff --git a/va108xx/va108xx-embassy/Cargo.toml b/va108xx/va108xx-embassy/Cargo.toml new file mode 100644 index 0000000..1ee3fa7 --- /dev/null +++ b/va108xx/va108xx-embassy/Cargo.toml @@ -0,0 +1,27 @@ +[package] +name = "va108xx-embassy" +version = "0.3.0" +edition = "2021" +authors = ["Robin Mueller "] +description = "Embassy-rs support for the Vorago VA108xx family of microcontrollers" +homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs" +repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs" +license = "Apache-2.0" +keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"] +categories = ["aerospace", "embedded", "no-std", "hardware-support"] + +[dependencies] +vorago-shared-hal = { version = "0.2", features = ["vor1x"] } +va108xx-hal = { version = "0.12" } + +[features] +default = ["irq-oc30-oc31"] +irqs-in-lib = [] +# This determines the reserved interrupt functions for the embassy time drivers. Only one +# is allowed to be selected! +irq-oc28-oc29 = ["irqs-in-lib"] +irq-oc29-oc30 = ["irqs-in-lib"] +irq-oc30-oc31 = ["irqs-in-lib"] + +[package.metadata.docs.rs] +rustdoc-args = ["--generate-link-to-definition"] diff --git a/va108xx/va108xx-embassy/README.md b/va108xx/va108xx-embassy/README.md new file mode 100644 index 0000000..62a00e8 --- /dev/null +++ b/va108xx/va108xx-embassy/README.md @@ -0,0 +1,10 @@ +[![Crates.io](https://img.shields.io/crates/v/va108xx-embassy)](https://crates.io/crates/va108xx-embassy) +[![docs.rs](https://img.shields.io/docsrs/va108xx-embassy)](https://docs.rs/va108xx-embassy) + +# Embassy-rs support for the Vorago VA108xx MCU family + +This repository contains the [embassy-rs](https://github.com/embassy-rs/embassy) support for the +VA108xx family. Currently, it contains the time driver to allow using embassy-rs. It uses the TIM +peripherals provided by the VA108xx family for this purpose. + +The documentation contains more information on how to use this crate. diff --git a/va108xx/va108xx-embassy/docs.sh b/va108xx/va108xx-embassy/docs.sh new file mode 100755 index 0000000..c8ddd4e --- /dev/null +++ b/va108xx/va108xx-embassy/docs.sh @@ -0,0 +1,3 @@ +#!/bin/bash +export RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" +cargo +nightly doc --open diff --git a/va108xx/va108xx-embassy/src/lib.rs b/va108xx/va108xx-embassy/src/lib.rs new file mode 100644 index 0000000..66785a1 --- /dev/null +++ b/va108xx/va108xx-embassy/src/lib.rs @@ -0,0 +1,109 @@ +//! # Embassy-rs support for the Vorago VA108xx MCU family +//! +//! This repository contains the [embassy-rs](https://github.com/embassy-rs/embassy) support for +//! the VA108xx family. Currently, it contains the time driver to allow using embassy-rs. It uses +//! the TIM peripherals provided by the VA108xx family for this purpose. +//! +//! ## Usage +//! +//! This library exposes the [init] or the [init_with_custom_irqs] functions which set up the time +//! driver. This function must be called once at the start of the application. +//! +//! This implementation requires two TIM peripherals provided by the VA108xx device. +//! The user can freely specify the two used TIM peripheral by passing the concrete TIM instances +//! into the [init_with_custom_irqs] and [init] method. +//! +//! The application also requires two interrupt handlers to handle the timekeeper and alarm +//! interrupts. By default, this library will define the interrupt handler inside the library +//! itself by using the `irq-oc30-oc31` feature flag. This library exposes three combinations: +//! +//! - `irq-oc30-oc31`: Uses [pac::Interrupt::OC30] and [pac::Interrupt::OC31] +//! - `irq-oc29-oc30`: Uses [pac::Interrupt::OC29] and [pac::Interrupt::OC30] +//! - `irq-oc28-oc29`: Uses [pac::Interrupt::OC28] and [pac::Interrupt::OC20] +//! +//! You can disable the default features and then specify one of the features above to use the +//! documented combination of IRQs. It is also possible to specify custom IRQs by importing and +//! using the [embassy_time_driver_irqs] macro to declare the IRQ handlers in the +//! application code. If this is done, [init_with_custom_irqs] must be used +//! method to pass the IRQ numbers to the library. +//! +//! ## Examples +//! +//! [embassy example projects](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy) +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] + +#[cfg(feature = "irqs-in-lib")] +use va108xx_hal::pac::{self, interrupt}; +use va108xx_hal::time::Hertz; +use va108xx_hal::timer::TimInstance; +use vorago_shared_hal::embassy::time_driver; + +/// Macro to define the IRQ handlers for the time driver. +/// +/// By default, the code generated by this macro will be defined inside the library depending on +/// the feature flags specified. However, the macro is exported to allow users to specify the +/// interrupt handlers themselves. +/// +/// Please note that you have to explicitely import the [macro@va108xx_hal::pac::interrupt] +/// macro in the application code in case this macro is used there. +#[macro_export] +macro_rules! embassy_time_driver_irqs { + ( + timekeeper_irq = $timekeeper_irq:ident, + alarm_irq = $alarm_irq:ident + ) => { + const TIMEKEEPER_IRQ: pac::Interrupt = pac::Interrupt::$timekeeper_irq; + + #[interrupt] + #[allow(non_snake_case)] + fn $timekeeper_irq() { + // Safety: We call it once here. + unsafe { $crate::time_driver().on_interrupt_timekeeping() } + } + + const ALARM_IRQ: pac::Interrupt = pac::Interrupt::$alarm_irq; + + #[interrupt] + #[allow(non_snake_case)] + fn $alarm_irq() { + // Safety: We call it once here. + unsafe { $crate::time_driver().on_interrupt_alarm() } + } + }; +} + +// Provide three combinations of IRQs for the time driver by default. + +#[cfg(feature = "irq-oc30-oc31")] +embassy_time_driver_irqs!(timekeeper_irq = OC31, alarm_irq = OC30); +#[cfg(feature = "irq-oc29-oc30")] +embassy_time_driver_irqs!(timekeeper_irq = OC30, alarm_irq = OC29); +#[cfg(feature = "irq-oc28-oc29")] +embassy_time_driver_irqs!(timekeeper_irq = OC29, alarm_irq = OC28); + +/// Initialization method for embassy. +/// +/// This should be used if the interrupt handler is provided by the library, which is the +/// default case. +#[cfg(feature = "irqs-in-lib")] +pub fn init( + timekeeper_tim: TimekeeperTim, + alarm_tim: AlarmTim, + sysclk: Hertz, +) { + time_driver().__init(sysclk, timekeeper_tim, alarm_tim, TIMEKEEPER_IRQ, ALARM_IRQ) +} + +/// Initialization method for embassy when using custom IRQ handlers. +/// +/// Requires an explicit [pac::Interrupt] argument for the timekeeper and alarm IRQs. +pub fn init_with_custom_irqs( + timekeeper_tim: TimekeeperTim, + alarm_tim: AlarmTim, + sysclk: Hertz, + timekeeper_irq: pac::Interrupt, + alarm_irq: pac::Interrupt, +) { + time_driver().__init(sysclk, timekeeper_tim, alarm_tim, timekeeper_irq, alarm_irq) +} diff --git a/va108xx/va108xx-hal/.cargo/config.toml b/va108xx/va108xx-hal/.cargo/config.toml new file mode 100644 index 0000000..dd54ddd --- /dev/null +++ b/va108xx/va108xx-hal/.cargo/config.toml @@ -0,0 +1,36 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# uncomment ONE of these three option to make `cargo run` start a GDB session +# which option to pick depends on your system +# runner = "arm-none-eabi-gdb -q -x jlink.gdb" +# runner = "gdb-multiarch -q -x jlink.gdb" +# runner = "gdb -q -x openocd.gdb" + +rustflags = [ + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", + + # LLD (shipped with the Rust toolchain) is used as the default linker + "-C", "link-arg=-Tlink.x", + + # if you run into problems with LLD switch to the GNU linker by commenting out + # this line + # "-C", "linker=arm-none-eabi-ld", + + # if you need to link to pre-compiled C libraries provided by a C toolchain + # use GCC as the linker by commenting out both lines above and then + # uncommenting the three lines below + # "-C", "linker=arm-none-eabi-gcc", + # "-C", "link-arg=-Wl,-Tlink.x", + # "-C", "link-arg=-nostartfiles", +] + +[build] +# Pick ONE of these compilation targets +target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) +# target = "thumbv8m.base-none-eabi" # Cortex-M23 +# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU) +# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU) \ No newline at end of file diff --git a/va108xx/va108xx-hal/.github/bors.toml b/va108xx/va108xx-hal/.github/bors.toml new file mode 100644 index 0000000..1779788 --- /dev/null +++ b/va108xx/va108xx-hal/.github/bors.toml @@ -0,0 +1,2 @@ +status = ["ci"] +delete_merged_branches = true diff --git a/va108xx/va108xx-hal/.github/workflows/changelog.yml b/va108xx/va108xx-hal/.github/workflows/changelog.yml new file mode 100644 index 0000000..dbba297 --- /dev/null +++ b/va108xx/va108xx-hal/.github/workflows/changelog.yml @@ -0,0 +1,20 @@ +on: + pull_request_target: + +name: Changelog check + +jobs: + changelog: + name: Changelog check + runs-on: ubuntu-latest + steps: + - name: Checkout sources + uses: actions/checkout@v2 + + - name: Changelog updated + uses: Zomzog/changelog-checker@v1.2.0 + with: + fileName: CHANGELOG.md + noChangelogLabel: no changelog + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} diff --git a/va108xx/va108xx-hal/.github/workflows/ci.yml b/va108xx/va108xx-hal/.github/workflows/ci.yml new file mode 100644 index 0000000..8caa486 --- /dev/null +++ b/va108xx/va108xx-hal/.github/workflows/ci.yml @@ -0,0 +1,65 @@ +on: [push] + +name: ci + +jobs: + check: + name: Check + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + target: thumbv6m-none-eabi + override: true + - uses: actions-rs/cargo@v1 + with: + command: check + - uses: actions-rs/cargo@v1 + with: + command: check + args: --examples + + fmt: + name: Rustfmt + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + override: true + - run: rustup component add rustfmt + - uses: actions-rs/cargo@v1 + with: + command: fmt + args: --all -- --check + + clippy: + name: Clippy + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + target: thumbv6m-none-eabi + override: true + - run: rustup component add clippy + - uses: actions-rs/cargo@v1 + with: + command: clippy + args: -- -D warnings + + ci: + if: ${{ success() }} + # all new jobs must be added to this list + needs: [check, fmt, clippy] + runs-on: ubuntu-latest + steps: + - name: CI succeeded + run: exit 0 \ No newline at end of file diff --git a/va108xx/va108xx-hal/.gitignore b/va108xx/va108xx-hal/.gitignore new file mode 100644 index 0000000..fd634d0 --- /dev/null +++ b/va108xx/va108xx-hal/.gitignore @@ -0,0 +1,9 @@ +# Generated by Cargo +# will have compiled files and executables +/target/ + +# https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html +Cargo.lock + +# These are backup files generated by rustfmt +**/*.rs.bk diff --git a/va108xx/va108xx-hal/CHANGELOG.md b/va108xx/va108xx-hal/CHANGELOG.md new file mode 100644 index 0000000..9df8357 --- /dev/null +++ b/va108xx/va108xx-hal/CHANGELOG.md @@ -0,0 +1,287 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +## [unreleased] + +## [v0.12.0] 2025-09-03 + +## Changed + +- Move most library components to new [`vorago-shared-hal`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal) + which is mostly re-exported in this crate. +- Overhaul and simplification of several HAL APIs. The system configuration and IRQ router + peripheral instance generally does not need to be passed to HAL API anymore. +- All HAL drivers are now type erased. The constructors will still expect and consume the PAC + singleton component for resource management purposes, but are not cached anymore. +- Refactoring of GPIO library to be more inline with embassy GPIO API. + +## Added + +- I2C clock timeout feature support. + +## [v0.11.1] 2025-03-10 + +## Fixed + +- Fix `embedded_io` UART implementation to implement the documented contract properly. + The implementation will now block until at least one byte is available or can be written, unless + the send or receive buffer is empty. + +## [v0.11.0] 2025-03-07 + +## Changed + +- Bugfix for I2C `TimingCfg::reg` +- Simplified UART error handling. All APIs are now infallible because writing to a FIFO or + reading from a FIFO never fails. Users can either poll errors using `Rx::poll_errors` or + `Uart::poll_rx_errors` / `UartBase::poll_rx_errors`, or detect errors using the provided + interrupt handlers. + +## [v0.10.0] 2025-02-17 + +## Added + +- A lot of missing `defmt::Format` implementations. + +## Changed + +- Larger refactoring of GPIO library. The edge and level interrupt configurator functions do not + enable interrupts anymore. Instead, there are explicit `enbable_interrupt` and + `disable_interrupt` methods +- Renamed GPIO `DynGroup` to `Port` +- Rename generic GPIO interrupt handler into `on_interrupt_for_asynch_gpio` + into `on_interrupt_for_async_gpio_for_port` which expects a Port argument + +## Fixed + +- Bug in async GPIO interrupt handler where all enabled interrupts, even the ones which might + be unrelated to the pin, were disabled. + +## [v0.9.0] 2025-02-13 + +## Fixed + +- Important bugfix for UART driver which causes UART B drivers not to work. + +## Removed + +- Deleted some HAL re-exports in the PWM module + +## Changed + +- GPIO API: Interrupt, pulse and filter and `set_datamask` and `clear_datamask` APIs are now + methods which mutable modify the pin instead of consuming and returning it. +- Simplified PWM module implementation. +- All error types now implement `core::error::Error` by using the `thiserror::Error` derive. +- `InvalidPinTypeError` now wraps the pin mode. +- I2C `TimingCfg` constructor now returns explicit error instead of generic Error. + Removed the timing configuration error type from the generic I2C error enumeration. +- `PinsA` and `PinsB` constructor do not expect an optional `pac::Ioconfig` argument anymore. +- `IrqCfg` renamed to `InterruptConfig`, kept alias for old name. +- All library provided interrupt handlers now start with common prefix `on_interrupt_*` +- `RxWithIrq` renamed to `RxWithInterrupt` +- `Rx::into_rx_with_irq` does not expect any arguments any more. +- `filter_type` renamed to `configure_filter_type`. +- `level_irq` renamed to `configure_level_interrupt`. +- `edge_irq` renamed to `configure_edge_interrupt`. +- `PinsA` and `PinsB` constructor do not expect an optional IOCONFIG argument anymore. +- UART interrupt management is now handled by the main constructor instead of later stages to + statically ensure one interrupt vector for the UART peripheral. `Uart::new` expects an + optional `InterruptConfig` argument. +- `enable_interrupt` and `disable_interrupt` renamed to `enable_nvic_interrupt` and + `disable_nvic_interrupt` to distinguish them from peripheral interrupts more clearly. +- `port_mux` renamed to `port_function_select` +- Renamed `IrqUartErrors` to `UartErrors`. + +## Added + +- Add `downgrade` method for `Pin` and `upgrade` method for `DynPin` as explicit conversion + methods. +- Asynchronous GPIO support. +- Asynchronous UART TX support. +- Asynchronous UART RX support. +- Add new `get_tim_raw` unsafe method to retrieve TIM peripheral blocks. +- `Uart::with_with_interrupt` and `Uart::new_without_interrupt` + +## [v0.8.0] 2024-09-30 + +## Changed + +- Improves `CascardSource` handling and general API when chosing cascade sources. +- Replaced `utility::unmask_irq` by `enable_interrupt` and `disable_interrupt` API. +- Improve and fix SPI abstractions. Add new low level interface. The primary SPI constructor now + only expects a configuration structure and the transfer configuration needs to be applied in a + separate step. +- Removed complete `timer` module re-export in `pwm` module +- `CountDownTimer` renamed to `CountdownTimer` + +## Fixes + +- Fixes for SPI peripheral: Flush implementation was incorrect and should now flush properly. + +## [v0.7.0] 2024-07-04 + +- Replace `uarta` and `uartb` `Uart` constructors by `new` constructor +- Replace SPI `spia`, `spib` and `spic` constructors by `new` constructor +- Replace I2C `i2ca`, `i2cb` constructors by `new` constructor. Update constructor + to fail on invalid fast I2C speed system clock values +- Renamed `gpio::pins` to `gpio::pin` and `gpio::dynpins` to `gpio::dynpin` +- Simplify UART clock divider calculations and remove `libm` dependency consequently + +## [v0.6.0] 2024-06-16 + +- Updated `embedded-hal` to v1 +- Added optional `defmt` v0.3 feature and support. + +## v0.5.2 2024-06-16 + +## Fixed + +- Replaced usage to `ptr::write_volatile` in UART module which is denied on more recent Rust + compilers. + +## v0.5.1 + +### Changes + +- Updated dependencies: + - `cortex-m-rtic` (dev-depencency) to 1.1.2 + - `once_cell` to 1.12.0 + - Other dependencies: Only revision has changed + +## v0.5.0 + +### Added + +- Reactored IRQ handling, so that `unmask` operations can be moved to HAL +- Added UART IRQ handler. Right now, can only perform reception, TX still needs to be done in + a blocking manner +- Added RTIC template and RTIC UART IRQ application + +### Fixed + +- Bugfix in UART code where RX and TX could not be enabled or disabled independently + +## v0.4.3 + +- Various smaller fixes for READMEs, update of links in documentation +- Simplified CI for github, do not use `cross` +- New `blinky-pac` example +- Use HAL delay in `blinky` example + +## v0.4.2 + +### Added + +- `port_mux` function to set pin function select manually + +### Changed + +- Clear TX and RX FIFO in SPI transfer function + +## v0.4.1 + +### Fixed + +- Initial blockmode setting was not set in SPI constructor + +## v0.4.0 + +### Changed + +- Replaced `Hertz` by `impl Into` completely and removed + `+ Copy` where not necessary + +## v0.3.1 + +- Updated all links to point to new repository + +## v0.3.0 + +### Added + +- TIM Cascade example + +### Changed + +- `CountDownTimer` new function now expects an `impl Into` instead of `Hertz` +- Primary repository now hosted on IRS external git: https://egit.irs.uni-stuttgart.de/rust/va108xx-hal +- Relicensed as Apache-2.0 + +## v0.2.3 + +### Added + +- Basic API for EDAC functionality +- PWM implementation and example +- API to perform peripheral resets + +### Changed + +- Improved Timer API. It is now possible to simply use `new` on `CountDownTimer` + +## v0.2.2 + +### Added + +- DelayUs and DelayMs trait implementations for timer +- SPI implementation for blocking API, supports blockmode as well +- Basic I2C implementation for blocking API + +### Changed + +- API which expects values in Hertz now uses `impl Into` as input parameter + +## v0.2.1 + +### Added + +- Adds the IRQ interface to configure interrupts on output and input pins +- Utility function to set up millisecond timer with `TIM0` +- Function to set clock divisor registers in `clock` module + +### Changed + +- Minor optimizations and tweaks for GPIO module +- Moved the `FilterClkSel` struct to the `clock` module, re-exporting in `gpio` +- Clearing output state at initialization of Output pins + +## v0.2.0 + +### Changed + +- New GPIO implementation which uses type-level programming. Implementation heavily based on the + ATSAMD GPIO HAL: https://docs.rs/atsamd-hal/0.13.0/atsamd_hal/gpio/v2/index.html +- Changes to API, therefore minor version bump + +### Added + +- UART implementation +- UART example +- Some bugfixes for GPIO implementation +- Rust edition updated to 2021 + +## v0.1.0 + +### Added + +- First version of the HAL which adds the GPIO implementation and timer implementation. +- Also adds some examples and helper files to set up new binary crates +- RTT example application +- Added basic test binary in form of an example +- README with basic instructions how to set up own binary crate + +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.12.0...HEAD +[v0.12.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.1...va108xx-hal-v0.12.0 +[v0.11.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...va108xx-hal-v0.11.1 +[v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0 +[v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0 +[v0.9.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.8.0...va108xx-hal-v0.9.0 +[v0.8.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.7.0...va108xx-hal-v0.8.0 +[v0.7.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.6.0...va108xx-hal-v0.7.0 +[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/tag/va108xx-hal-v0.6.0 diff --git a/va108xx/va108xx-hal/Cargo.toml b/va108xx/va108xx-hal/Cargo.toml new file mode 100644 index 0000000..c04bbe2 --- /dev/null +++ b/va108xx/va108xx-hal/Cargo.toml @@ -0,0 +1,36 @@ +[package] +name = "va108xx-hal" +version = "0.12.0" +authors = ["Robin Mueller "] +edition = "2021" +description = "HAL for the Vorago VA108xx family of microcontrollers" +homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs" +repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs" +license = "Apache-2.0" +keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"] +categories = ["aerospace", "embedded", "no-std", "hardware-support"] + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"]} +vorago-shared-hal = { version = "0.2", features = ["vor1x"] } +fugit = "0.3" +thiserror = { version = "2", default-features = false } +va108xx = { version = "0.6", default-features = false, features = ["critical-section", "defmt"] } +defmt = { version = "1", optional = true } + +[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies] +portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] } +[target.'cfg(not(all(target_arch = "arm", target_os = "none")))'.dependencies] +portable-atomic = "1" + +[features] +default = ["rt"] +rt = ["va108xx/rt"] +defmt = ["dep:defmt", "vorago-shared-hal/defmt"] + +[package.metadata.docs.rs] +all-features = true +rustdoc-args = ["--generate-link-to-definition"] + +[package.metadata.cargo-machete] +ignored = ["cortex-m"] diff --git a/va108xx/va108xx-hal/LICENSE-APACHE b/va108xx/va108xx-hal/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va108xx/va108xx-hal/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + +4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va108xx/va108xx-hal/NOTICE b/va108xx/va108xx-hal/NOTICE new file mode 100644 index 0000000..4b4fe08 --- /dev/null +++ b/va108xx/va108xx-hal/NOTICE @@ -0,0 +1,3 @@ +Rust Hardware Abstraction Layer (HAL) crate for the Vorago VA108xx family of MCUs + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va108xx/va108xx-hal/README.md b/va108xx/va108xx-hal/README.md new file mode 100644 index 0000000..e22507f --- /dev/null +++ b/va108xx/va108xx-hal/README.md @@ -0,0 +1,69 @@ +[![Crates.io](https://img.shields.io/crates/v/va108xx-hal)](https://crates.io/crates/va108xx-hal) +[![docs.rs](https://img.shields.io/docsrs/va108xx-hal)](https://docs.rs/va108xx-hal) + +# HAL for the Vorago VA108xx MCU family + +This repository contains the **H**ardware **A**bstraction **L**ayer (HAL), which is an additional +hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx). + +It is the result of reading the datasheet for the device and encoding a type-safe layer over the +raw PAC. This crate also implements traits specified by the +[embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with +various drivers in the embedded rust ecosystem. + +In contrats to other HAL implementations, there is only one chip variant available here so there +is no need to pass the chip variant as a feature. + +## Building + +Building an application requires the `thumbv6m-none-eabi` cross-compiler toolchain. +If you have not installed it yet, you can do so with + +```sh +rustup target add thumbv6m-none-eabi +``` + +After that, you can use `cargo build` to build the development version of the crate. + +## Setting up your own binary crate + +If you have a custom board, you might be interested in setting up a new binary crate for your +project. These steps aim to provide a complete list to get a binary crate working to flash +your custom board. + +The hello world of embedded development is usually to blinky a LED. This example +is contained within the +[examples folder](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs). + +1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building) +2. Create a new binary crate with `cargo init` +3. To ensure that `cargo build` cross-compiles, it is recommended to create a `.cargo/config.toml` + file. A sample `.cargo/config.toml` file is provided in this repository as well +4. Copy the `memory.x` file into your project. This file contains information required by the linker. +5. Copy the `blinky.rs` file to the `src/main.rs` file in your binary crate +6. You need to add some dependencies to your `Cargo.toml` file + + ```toml + [dependencies] + cortex-m = "" + cortex-m-rt = "" + panic-halt = "" + embedded-hal = "" + + [dependencies.va108xx-hal] + version = "" + features = ["rt"] + ``` + +6. Build the application with `cargo build` + +7. Flashing the board might work differently for different boards and there is usually + more than one way. You can find example instructions in primary README. + +## Embedded Rust + +If you have not done this yet, it is recommended to read some of the excellent resources available +to learn Rust: + +- [Rust Embedded Book](https://docs.rust-embedded.org/book/) +- [Rust Discovery Book](https://docs.rust-embedded.org/discovery/) diff --git a/va108xx/va108xx-hal/automation/Dockerfile b/va108xx/va108xx-hal/automation/Dockerfile new file mode 100644 index 0000000..b789384 --- /dev/null +++ b/va108xx/va108xx-hal/automation/Dockerfile @@ -0,0 +1,13 @@ +# Run the following commands from root directory to build and run locally +# docker build -f automation/Dockerfile -t . +# docker run -it +FROM rust:latest +RUN apt-get update +RUN apt-get --yes upgrade +# tzdata is a dependency, won't install otherwise +ARG DEBIAN_FRONTEND=noninteractive + +RUN rustup install nightly && \ + rustup target add thumbv6m-none-eabi && \ + rustup +nightly target add thumbv6m-none-eabi && \ + rustup component add rustfmt clippy diff --git a/va108xx/va108xx-hal/automation/Jenkinsfile b/va108xx/va108xx-hal/automation/Jenkinsfile new file mode 100644 index 0000000..9a27623 --- /dev/null +++ b/va108xx/va108xx-hal/automation/Jenkinsfile @@ -0,0 +1,37 @@ +pipeline { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + + + stages { + stage('Clippy') { + steps { + sh 'cargo clippy' + } + } + stage('Rustfmt') { + steps { + sh 'cargo fmt' + } + } + stage('Docs') { + steps { + sh 'cargo +nightly doc' + } + } + stage('Check') { + steps { + sh 'cargo check --target thumbv6m-none-eabi' + } + } + stage('Check Examples') { + steps { + sh 'cargo check --target thumbv6m-none-eabi --examples' + } + } + } +} \ No newline at end of file diff --git a/va108xx/va108xx-hal/docs.sh b/va108xx/va108xx-hal/docs.sh new file mode 100755 index 0000000..37563d2 --- /dev/null +++ b/va108xx/va108xx-hal/docs.sh @@ -0,0 +1,3 @@ +#!/bin/sh +export RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" +cargo +nightly doc --all-features --open diff --git a/va108xx/va108xx-hal/jlink.gdb b/va108xx/va108xx-hal/jlink.gdb new file mode 100644 index 0000000..20ff2d5 --- /dev/null +++ b/va108xx/va108xx-hal/jlink.gdb @@ -0,0 +1,10 @@ +target remote localhost:2331 + +monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va108xx/va108xx-hal/memory.x b/va108xx/va108xx-hal/memory.x new file mode 100644 index 0000000..1ca0e97 --- /dev/null +++ b/va108xx/va108xx-hal/memory.x @@ -0,0 +1,10 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 0x20000 /* 128K */ + RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/va108xx/va108xx-hal/src/clock.rs b/va108xx/va108xx-hal/src/clock.rs new file mode 100644 index 0000000..643f95f --- /dev/null +++ b/va108xx/va108xx-hal/src/clock.rs @@ -0,0 +1,32 @@ +//! # API for clock related functionality +//! +//! This also includes functionality to enable the peripheral clocks +pub use vorago_shared_hal::gpio::FilterClockSelect; +pub use vorago_shared_hal::sysconfig::{disable_peripheral_clock, enable_peripheral_clock}; + +pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClockSelect, div: u32) { + match clk_sel { + FilterClockSelect::SysClk => (), + FilterClockSelect::Clk1 => { + syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) }); + } + FilterClockSelect::Clk2 => { + syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) }); + } + FilterClockSelect::Clk3 => { + syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) }); + } + FilterClockSelect::Clk4 => { + syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) }); + } + FilterClockSelect::Clk5 => { + syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) }); + } + FilterClockSelect::Clk6 => { + syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) }); + } + FilterClockSelect::Clk7 => { + syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) }); + } + } +} diff --git a/va108xx/va108xx-hal/src/gpio/mod.rs b/va108xx/va108xx-hal/src/gpio/mod.rs new file mode 100644 index 0000000..428cd93 --- /dev/null +++ b/va108xx/va108xx-hal/src/gpio/mod.rs @@ -0,0 +1,20 @@ +//! GPIO support module. +//! +//! Contains abstractions to use the pins provided by the [crate::pins] module as GPIO or +//! IO peripheral pins. +//! +//! The core data structures provided for this are the +//! +//! - [Output] for push-pull output pins. +//! - [Input] for input pins. +//! - [Flex] for pins with flexible configuration requirements. +//! - [IoPeriphPin] for IO peripheral pins. +//! +//! The [crate::pins] module exposes singletons to access the [Pin]s required by this module +//! in a type-safe way. +//! +//! ## Examples +//! +//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs) +//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs) +pub use vorago_shared_hal::gpio::*; diff --git a/va108xx/va108xx-hal/src/i2c.rs b/va108xx/va108xx-hal/src/i2c.rs new file mode 100644 index 0000000..f620edd --- /dev/null +++ b/va108xx/va108xx-hal/src/i2c.rs @@ -0,0 +1,6 @@ +//! API for the I2C peripheral +//! +//! ## Examples +//! +//! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs) +pub use vorago_shared_hal::i2c::*; diff --git a/va108xx/va108xx-hal/src/lib.rs b/va108xx/va108xx-hal/src/lib.rs new file mode 100644 index 0000000..5da9b3e --- /dev/null +++ b/va108xx/va108xx-hal/src/lib.rs @@ -0,0 +1,60 @@ +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] + +use gpio::Port; +pub use va108xx; +pub use va108xx as pac; + +pub mod clock; +pub mod gpio; +pub mod i2c; +pub mod pins; +pub mod prelude; +pub mod pwm; +pub mod spi; +pub mod sysconfig; +pub mod time; +pub mod timer; +pub mod uart; + +pub use vorago_shared_hal::{ + disable_nvic_interrupt, enable_nvic_interrupt, FunctionSelect, InterruptConfig, + PeripheralSelect, +}; + +/// This is the NONE destination reigster value for the IRQSEL peripheral. +pub const IRQ_DST_NONE: u32 = 0xffffffff; + +#[derive(Debug, PartialEq, Eq, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("invalid pin with number {0}")] +pub struct InvalidPinError(u8); + +/// Can be used to manually manipulate the function select of port pins. +/// +/// The function selection table can be found on p.36 of the programmers guide. Please note +/// that most of the structures and APIs in this library will automatically correctly configure +/// the pin or statically expect the correct pin type. +pub fn port_function_select( + ioconfig: &mut pac::Ioconfig, + port: Port, + pin: u8, + funsel: FunctionSelect, +) -> Result<(), InvalidPinError> { + if (port == Port::A && pin >= 32) || (port == Port::B && pin >= 24) { + return Err(InvalidPinError(pin)); + } + + let reg_block = match port { + Port::A => ioconfig.porta(pin as usize), + Port::B => ioconfig.portb(pin as usize), + }; + + reg_block.modify(|_, w| unsafe { w.funsel().bits(funsel as u8) }); + Ok(()) +} + +#[allow(dead_code)] +pub(crate) mod sealed { + pub trait Sealed {} +} diff --git a/va108xx/va108xx-hal/src/pins.rs b/va108xx/va108xx-hal/src/pins.rs new file mode 100644 index 0000000..1c46616 --- /dev/null +++ b/va108xx/va108xx-hal/src/pins.rs @@ -0,0 +1,6 @@ +//! Pin resource management singletons. +//! +//! This module contains the pin singletons. It allows creating those singletons +//! to access the [Pin] structures of individual ports in a safe way with checked ownership +//! rules. +pub use vorago_shared_hal::pins::*; diff --git a/va108xx/va108xx-hal/src/prelude.rs b/va108xx/va108xx-hal/src/prelude.rs new file mode 100644 index 0000000..516618f --- /dev/null +++ b/va108xx/va108xx-hal/src/prelude.rs @@ -0,0 +1,5 @@ +//! Prelude +pub use fugit::ExtU32 as _; +pub use fugit::RateExtU32 as _; + +pub use crate::time::*; diff --git a/va108xx/va108xx-hal/src/pwm.rs b/va108xx/va108xx-hal/src/pwm.rs new file mode 100644 index 0000000..f8662c0 --- /dev/null +++ b/va108xx/va108xx-hal/src/pwm.rs @@ -0,0 +1,8 @@ +//! API for Pulse-Width Modulation (PWM) +//! +//! The Vorago VA108xx devices use the TIM peripherals to perform PWM related tasks +//! +//! ## Examples +//! +//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/pwm.rs) +pub use vorago_shared_hal::pwm::*; diff --git a/va108xx/va108xx-hal/src/spi/mod.rs b/va108xx/va108xx-hal/src/spi/mod.rs new file mode 100644 index 0000000..a3e9cd2 --- /dev/null +++ b/va108xx/va108xx-hal/src/spi/mod.rs @@ -0,0 +1,12 @@ +//! API for the SPI peripheral. +//! +//! The main abstraction provided by this module is the [Spi] an structure. +//! It provides the [SpiBus trait](https://docs.rs/embedded-hal/latest/embedded_hal/spi/trait.SpiBus.html), +//! but also offer a low level interface via the [SpiLowLevel] trait. +//! +//! ## Examples +//! +//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/spi.rs) +//! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11519-adc.rs) +//! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/src/m95m01.rs) +pub use vorago_shared_hal::spi::*; diff --git a/va108xx/va108xx-hal/src/sysconfig.rs b/va108xx/va108xx-hal/src/sysconfig.rs new file mode 100644 index 0000000..bf70601 --- /dev/null +++ b/va108xx/va108xx-hal/src/sysconfig.rs @@ -0,0 +1,43 @@ +#[derive(PartialEq, Eq, Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InvalidCounterResetVal(pub(crate) ()); + +/// Enable scrubbing for the ROM +/// +/// Returns [InvalidCounterResetVal] if the scrub rate is 0 +/// (equivalent to disabling) or larger than 24 bits +pub fn enable_rom_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVal> { + let syscfg = unsafe { va108xx::Sysconfig::steal() }; + if scrub_rate == 0 || scrub_rate > u32::pow(2, 24) { + return Err(InvalidCounterResetVal(())); + } + syscfg.rom_scrub().write(|w| unsafe { w.bits(scrub_rate) }); + Ok(()) +} + +pub fn disable_rom_scrubbing() { + let syscfg = unsafe { va108xx::Sysconfig::steal() }; + syscfg.rom_scrub().write(|w| unsafe { w.bits(0) }); +} + +/// Enable scrubbing for the RAM +/// +/// Returns [InvalidCounterResetVal] if the scrub rate is 0 +/// (equivalent to disabling) or larger than 24 bits +pub fn enable_ram_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVal> { + let syscfg = unsafe { va108xx::Sysconfig::steal() }; + if scrub_rate == 0 || scrub_rate > u32::pow(2, 24) { + return Err(InvalidCounterResetVal(())); + } + syscfg.ram_scrub().write(|w| unsafe { w.bits(scrub_rate) }); + Ok(()) +} + +pub fn disable_ram_scrubbing() { + let syscfg = unsafe { va108xx::Sysconfig::steal() }; + syscfg.ram_scrub().write(|w| unsafe { w.bits(0) }); +} + +pub use vorago_shared_hal::sysconfig::{ + assert_peripheral_reset, disable_peripheral_clock, enable_peripheral_clock, +}; diff --git a/va108xx/va108xx-hal/src/time.rs b/va108xx/va108xx-hal/src/time.rs new file mode 100644 index 0000000..148f3ee --- /dev/null +++ b/va108xx/va108xx-hal/src/time.rs @@ -0,0 +1,2 @@ +//! Time units +pub use vorago_shared_hal::time::*; diff --git a/va108xx/va108xx-hal/src/timer.rs b/va108xx/va108xx-hal/src/timer.rs new file mode 100644 index 0000000..e39d18d --- /dev/null +++ b/va108xx/va108xx-hal/src/timer.rs @@ -0,0 +1,7 @@ +//! API for the TIM peripherals +//! +//! ## Examples +//! +//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs) +//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs) +pub use vorago_shared_hal::timer::*; diff --git a/va108xx/va108xx-hal/src/uart/mod.rs b/va108xx/va108xx-hal/src/uart/mod.rs new file mode 100644 index 0000000..33e4fb0 --- /dev/null +++ b/va108xx/va108xx-hal/src/uart/mod.rs @@ -0,0 +1,17 @@ +//! # API for the UART peripheral +//! +//! The core of this API are the [Uart], [Rx] and [Tx] structures. +//! The RX structure also has a dedicated [RxWithInterrupt] variant which allows reading the receiver +//! using interrupts. +//! +//! The [rx_asynch] and [tx_asynch] modules provide an asynchronous non-blocking API for the UART +//! peripheral. +//! +//! ## Examples +//! +//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/uart.rs) +//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs) +//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader) +//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs) +//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs) +pub use vorago_shared_hal::uart::*; diff --git a/va108xx/va108xx-hal/tests/DueSerialTest/.gitignore b/va108xx/va108xx-hal/tests/DueSerialTest/.gitignore new file mode 100644 index 0000000..89cc49c --- /dev/null +++ b/va108xx/va108xx-hal/tests/DueSerialTest/.gitignore @@ -0,0 +1,5 @@ +.pio +.vscode/.browse.c_cpp.db* +.vscode/c_cpp_properties.json +.vscode/launch.json +.vscode/ipch diff --git a/va108xx/va108xx-hal/tests/DueSerialTest/.vscode/extensions.json b/va108xx/va108xx-hal/tests/DueSerialTest/.vscode/extensions.json new file mode 100644 index 0000000..e80666b --- /dev/null +++ b/va108xx/va108xx-hal/tests/DueSerialTest/.vscode/extensions.json @@ -0,0 +1,7 @@ +{ + // See http://go.microsoft.com/fwlink/?LinkId=827846 + // for the documentation about the extensions.json format + "recommendations": [ + "platformio.platformio-ide" + ] +} diff --git a/va108xx/va108xx-hal/tests/DueSerialTest/README.md b/va108xx/va108xx-hal/tests/DueSerialTest/README.md new file mode 100644 index 0000000..c53cfa1 --- /dev/null +++ b/va108xx/va108xx-hal/tests/DueSerialTest/README.md @@ -0,0 +1,2 @@ +This is a Platform IO test script for the Arduino Due which can be used to sent different kind +of strings via the serial interface (RX1 and TX1) to the Vorago board. diff --git a/va108xx/va108xx-hal/tests/DueSerialTest/include/README b/va108xx/va108xx-hal/tests/DueSerialTest/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/va108xx/va108xx-hal/tests/DueSerialTest/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/va108xx/va108xx-hal/tests/DueSerialTest/lib/README b/va108xx/va108xx-hal/tests/DueSerialTest/lib/README new file mode 100644 index 0000000..6debab1 --- /dev/null +++ b/va108xx/va108xx-hal/tests/DueSerialTest/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/va108xx/va108xx-hal/tests/DueSerialTest/platformio.ini b/va108xx/va108xx-hal/tests/DueSerialTest/platformio.ini new file mode 100644 index 0000000..a448357 --- /dev/null +++ b/va108xx/va108xx-hal/tests/DueSerialTest/platformio.ini @@ -0,0 +1,15 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[env:due] +platform = atmelsam +board = due +framework = arduino +monitor_speed = 115200 diff --git a/va108xx/va108xx-hal/tests/DueSerialTest/src/main.cpp b/va108xx/va108xx-hal/tests/DueSerialTest/src/main.cpp new file mode 100644 index 0000000..2fbed5f --- /dev/null +++ b/va108xx/va108xx-hal/tests/DueSerialTest/src/main.cpp @@ -0,0 +1,78 @@ +#include + +enum SendModes { + ECHO, + ONLY_WRITE, + ONLY_READ, + WRITE_READ +}; + +enum StringModes { + FIXED, + VARIABLE +}; + +// Configure the test application here +SendModes SEND_MODE = SendModes::WRITE_READ; +StringModes STRING_MODE = StringModes::VARIABLE; +uint8_t STRING_IDX = 0; + +String STRINGS[4] = { + "$Hi\n", + "$Hello\n", + "$Hello World\n", + "$Hello and Merry Christmas to all of you!\n" +}; + +void setup() { + // put your setup code here, to run once: + Serial.begin(115200); + Serial.println("Starting Arduino Serial Test script.."); + Serial1.begin(115200); + if(STRING_MODE == StringModes::VARIABLE) { + STRING_IDX = 0; + } + pinMode(LED_BUILTIN, OUTPUT); +} + +void loop() { + static byte ICOMING_BYTE = 0; + static uint32_t GLOBAL_IDX = 0; + digitalWrite(LED_BUILTIN, !digitalRead(LED_BUILTIN)); + // put your main code here, to run repeatedly: + // send data only when you receive data: + if (SEND_MODE == SendModes::ONLY_WRITE or SEND_MODE == SendModes::WRITE_READ) { + Serial.println("Sending string.."); + Serial1.write(STRINGS[STRING_IDX].c_str()); + if(STRING_MODE == StringModes::VARIABLE) { + STRING_IDX += 1; + if(STRING_IDX > 3) { + STRING_IDX = 0; + } + } + } + if( + SEND_MODE == SendModes::WRITE_READ or + SEND_MODE == SendModes::ONLY_READ or + SEND_MODE == SendModes::ECHO + ) { + if (Serial1.available() > 0) { + // read the incoming byte: + String readString = Serial1.readStringUntil('\n'); + + Serial.print(GLOBAL_IDX); + Serial.print(" - "); + GLOBAL_IDX++; + // say what you got: + Serial.print("I received: "); + Serial.println(readString); + if(SEND_MODE == SendModes::ECHO) { + delay(200); + Serial.println("Sending back echo message"); + String sendBack = readString + '\n'; + Serial1.write(sendBack.c_str()); + } + } + } + delay(3000); +} diff --git a/va108xx/va108xx-hal/tests/DueSerialTest/test/README b/va108xx/va108xx-hal/tests/DueSerialTest/test/README new file mode 100644 index 0000000..b94d089 --- /dev/null +++ b/va108xx/va108xx-hal/tests/DueSerialTest/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PlatformIO Unit Testing and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PlatformIO Unit Testing: +- https://docs.platformio.org/page/plus/unit-testing.html diff --git a/va108xx/va108xx/.github/bors.toml b/va108xx/va108xx/.github/bors.toml new file mode 100644 index 0000000..1779788 --- /dev/null +++ b/va108xx/va108xx/.github/bors.toml @@ -0,0 +1,2 @@ +status = ["ci"] +delete_merged_branches = true diff --git a/va108xx/va108xx/.github/workflows/changelog.yml b/va108xx/va108xx/.github/workflows/changelog.yml new file mode 100644 index 0000000..dbba297 --- /dev/null +++ b/va108xx/va108xx/.github/workflows/changelog.yml @@ -0,0 +1,20 @@ +on: + pull_request_target: + +name: Changelog check + +jobs: + changelog: + name: Changelog check + runs-on: ubuntu-latest + steps: + - name: Checkout sources + uses: actions/checkout@v2 + + - name: Changelog updated + uses: Zomzog/changelog-checker@v1.2.0 + with: + fileName: CHANGELOG.md + noChangelogLabel: no changelog + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} diff --git a/va108xx/va108xx/.github/workflows/ci.yml b/va108xx/va108xx/.github/workflows/ci.yml new file mode 100644 index 0000000..393eecb --- /dev/null +++ b/va108xx/va108xx/.github/workflows/ci.yml @@ -0,0 +1,61 @@ +on: [push] + +name: build + +jobs: + check: + name: Check + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + target: thumbv6m-none-eabi + override: true + - uses: actions-rs/cargo@v1 + with: + command: check + + fmt: + name: Rustfmt + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + override: true + - run: rustup component add rustfmt + - uses: actions-rs/cargo@v1 + with: + command: fmt + args: --all -- --check + + clippy: + name: Clippy + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + target: thumbv6m-none-eabi + override: true + - run: rustup component add clippy + - uses: actions-rs/cargo@v1 + with: + command: clippy + args: -- -D warnings + + ci: + if: ${{ success() }} + # all new jobs must be added to this list + needs: [check, fmt, clippy] + runs-on: ubuntu-latest + steps: + - name: CI succeeded + run: exit 0 \ No newline at end of file diff --git a/va108xx/va108xx/.gitignore b/va108xx/va108xx/.gitignore new file mode 100644 index 0000000..f2e972d --- /dev/null +++ b/va108xx/va108xx/.gitignore @@ -0,0 +1,6 @@ +# Generated by Cargo +# will have compiled files and executables +/target/ + +# These are backup files generated by rustfmt +**/*.rs.bk diff --git a/va108xx/va108xx/CHANGELOG.md b/va108xx/va108xx/CHANGELOG.md new file mode 100644 index 0000000..582efb8 --- /dev/null +++ b/va108xx/va108xx/CHANGELOG.md @@ -0,0 +1,94 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +## [unreleased] + +## [v0.6.0] 2025-09-03 + +- Re-generated PAC with `svd2rust` v0.37.0 + +## [v0.5.1] 2025-07-22 + +defmt version v1 + +## [v0.5.0] 2025-02-17 + +- Re-generated PAC with `svd2rust` v0.35.0 and added optional `defmt` and `Debug` implementations + +## [v0.4.0] 2025-02-12 + +- Re-generated PAC with `svd2rust` v0.35.0 + +## [v0.3.0] 2024-06-16 + +- Re-generated PAC with `svd2rust` v0.33.3 + +## [v0.2.4] + +- Added missing bitfield `CSDTRG2` in `CSD_CTRL` register of `TIM0` peripheral + +## [v0.2.3] + +- Added peripheral reset fields for `PERIPHERAL_RESET` register + +## [v0.2.2] + +- README tweks + +## [v0.2.1] + +- Some README and Manifest weaks + +## [v0.2.0] + +- Authorative repository was transferred to https://egit.irs.uni-stuttgart.de/rust/va108xx-rs but + there still will be a GitHub mirror. Project relicensed as Apache-2.0 only + +## [v0.1.3] + +### Added + +- Added two missing bit fields for I2CA STATUS register: I2CIDLE and IDLE + +### Fixed + +- Made I2CA STATUS register read-only + +## [v0.1.2] + +### Fixed + +- Generated with patched version of `svd2rust`: See + https://github.com/rust-embedded/svd2rust/pull/549 for more details. + Some bitmasks were missing from register reader definitions. + +## [v0.1.1] + +- Relicensed under dual Apache-2.0 / MIT license + +### Changed + +- SVD file handling improved and new fields added for the peripheral + clock enable register + +### Added + +- Helper script to automate all steps for PAC generation +- Added badges for README + +## [v0.1.0] + +### Added + +- First version of the PAC which builds. Uses a patched version + of `svd2rust`: https://github.com/rust-embedded/svd2rust + +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.6.0...HEAD +[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.5.1...va108xx-v0.6.0 +[v0.5.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.5.0...va108xx-v0.5.1 +[v0.5.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.4.0...va108xx-v0.5.0 diff --git a/va108xx/va108xx/Cargo.toml b/va108xx/va108xx/Cargo.toml new file mode 100644 index 0000000..8f0af1d --- /dev/null +++ b/va108xx/va108xx/Cargo.toml @@ -0,0 +1,30 @@ +[package] +name = "va108xx" +version = "0.6.0" +authors = ["Robin Mueller "] +edition = "2021" +description = "PAC for the Vorago VA108xx family of microcontrollers" +homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs" +repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs" +license = "Apache-2.0" +keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"] +categories = ["embedded", "no-std", "hardware-support"] + +[dependencies] +cortex-m = "0.7" +vcell = "0.1.3" +defmt = { version = "1", optional = true } +critical-section = { version = "1", optional = true } + +[dependencies.cortex-m-rt] +optional = true +version = ">=0.6.15,<0.8" + +[features] +rt = ["cortex-m-rt/device"] +# Adds Debug implementation +debug = [] + +[package.metadata.docs.rs] +all-features = true +rustdoc-args = ["--generate-link-to-definition"] diff --git a/va108xx/va108xx/LICENSE-APACHE b/va108xx/va108xx/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va108xx/va108xx/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + +4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va108xx/va108xx/NOTICE b/va108xx/va108xx/NOTICE new file mode 100644 index 0000000..35769f0 --- /dev/null +++ b/va108xx/va108xx/NOTICE @@ -0,0 +1,3 @@ +Peripheral access crate for the Vorago VA108xx family microcontrollers + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va108xx/va108xx/README.md b/va108xx/va108xx/README.md new file mode 100644 index 0000000..a5ec109 --- /dev/null +++ b/va108xx/va108xx/README.md @@ -0,0 +1,67 @@ +[![Crates.io](https://img.shields.io/crates/v/va108xx)](https://crates.io/crates/va108xx) +[![docs.rs](https://img.shields.io/docsrs/va108xx)](https://docs.rs/va108xx) + +# PAC for the Vorago VA108xx microcontroller family + +This repository contains the Peripheral Access Crate (PAC) for +Voragos VA108xx series of Cortex-M0 based microcontrollers. + +The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust). + +If you are interested in higher-level abstractions, it is recommended you visit +the `va108xx-hal` HAL crate and the `vorago-reb1` BSP crate which build on top of this PAC. + +## Usage + +To use this crate, add this to your `Cargo.toml` + +```toml +[dependencies.va108xx] +version = "" +features = ["rt"] +``` + +The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`. + +For full details on the autgenerated API, please see the +[svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api). + +## Optional Features + +- [`defmt`](https://defmt.ferrous-systems.com/): Add support for `defmt` by adding the + [`defmt::Format`](https://defmt.ferrous-systems.com/format) derive on many types. +- `debug`: Add `Debug` derives for various structures + +## Regenerating the PAC + +If you want to re-generate the PAC, for example if the register file `va416xx.svd` changes +or the `svd2rust` version is updated, you can do some using the following these steps: + +1. Make sure all necessary tools are installed: [`svd2rust`](https://docs.rs/svd2rust/latest/svd2rust/), + [`svdtools`](https://github.com/rust-embedded/svdtools) and [`form`](https://crates.io/crates/form). + You can install all tools with `cargo`: + + ```sh + cargo install --locked svd2rust svdtools form + ``` + +2. Patch the vendor-provided SVD file `svd/va41xx.svd`. This can be done using `svdtools` in + conjunction with the `svd/va108xx-patch.yml` file. + + ```sh + svdtools patch svd/va108xx-patch.yml + ``` + +3. Use `svd2rust` to generate the Rust library + + ```sh + svd2rust -i svd/va108xx.svd.patched + ``` + +4. Use the `form` tool to split the generated `lib.rs` into individual modules. + + ```sh + form -i lib.rs -o src/ + ``` + +The `gen-helper.sh` automates steps 2-4. diff --git a/va108xx/va108xx/automation/Dockerfile b/va108xx/va108xx/automation/Dockerfile new file mode 100644 index 0000000..5fb8a3d --- /dev/null +++ b/va108xx/va108xx/automation/Dockerfile @@ -0,0 +1,11 @@ +# Run the following commands from root directory to build and run locally +# docker build -f automation/Dockerfile -t . +# docker run -it +FROM rust:latest +RUN apt-get update +RUN apt-get --yes upgrade +# tzdata is a dependency, won't install otherwise +ARG DEBIAN_FRONTEND=noninteractive + +RUN rustup target add thumbv6m-none-eabi && \ + rustup component add rustfmt clippy diff --git a/va108xx/va108xx/automation/Jenkinsfile b/va108xx/va108xx/automation/Jenkinsfile new file mode 100644 index 0000000..cad5b57 --- /dev/null +++ b/va108xx/va108xx/automation/Jenkinsfile @@ -0,0 +1,39 @@ +pipeline { + agent any + + stages { + stage('Clippy') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo clippy' + } + } + stage('Rustfmt') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo fmt' + } + } + stage('Check') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo check --target thumbv6m-none-eabi' + } + } + } +} \ No newline at end of file diff --git a/va108xx/va108xx/build.rs b/va108xx/va108xx/build.rs new file mode 100644 index 0000000..d0781ac --- /dev/null +++ b/va108xx/va108xx/build.rs @@ -0,0 +1,17 @@ +#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/va108xx/va108xx/device.x b/va108xx/va108xx/device.x new file mode 100644 index 0000000..a191a90 --- /dev/null +++ b/va108xx/va108xx/device.x @@ -0,0 +1,33 @@ +PROVIDE(OC0 = DefaultHandler); +PROVIDE(OC1 = DefaultHandler); +PROVIDE(OC2 = DefaultHandler); +PROVIDE(OC3 = DefaultHandler); +PROVIDE(OC4 = DefaultHandler); +PROVIDE(OC5 = DefaultHandler); +PROVIDE(OC6 = DefaultHandler); +PROVIDE(OC7 = DefaultHandler); +PROVIDE(OC8 = DefaultHandler); +PROVIDE(OC9 = DefaultHandler); +PROVIDE(OC10 = DefaultHandler); +PROVIDE(OC11 = DefaultHandler); +PROVIDE(OC12 = DefaultHandler); +PROVIDE(OC13 = DefaultHandler); +PROVIDE(OC14 = DefaultHandler); +PROVIDE(OC15 = DefaultHandler); +PROVIDE(OC16 = DefaultHandler); +PROVIDE(OC17 = DefaultHandler); +PROVIDE(OC18 = DefaultHandler); +PROVIDE(OC19 = DefaultHandler); +PROVIDE(OC20 = DefaultHandler); +PROVIDE(OC21 = DefaultHandler); +PROVIDE(OC22 = DefaultHandler); +PROVIDE(OC23 = DefaultHandler); +PROVIDE(OC24 = DefaultHandler); +PROVIDE(OC25 = DefaultHandler); +PROVIDE(OC26 = DefaultHandler); +PROVIDE(OC27 = DefaultHandler); +PROVIDE(OC28 = DefaultHandler); +PROVIDE(OC29 = DefaultHandler); +PROVIDE(OC30 = DefaultHandler); +PROVIDE(OC31 = DefaultHandler); + diff --git a/va108xx/va108xx/docs.sh b/va108xx/va108xx/docs.sh new file mode 100755 index 0000000..37563d2 --- /dev/null +++ b/va108xx/va108xx/docs.sh @@ -0,0 +1,3 @@ +#!/bin/sh +export RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" +cargo +nightly doc --all-features --open diff --git a/va108xx/va108xx/gen-helper.sh b/va108xx/va108xx/gen-helper.sh new file mode 100755 index 0000000..64cb72e --- /dev/null +++ b/va108xx/va108xx/gen-helper.sh @@ -0,0 +1,43 @@ +#!/bin/bash + +# Use installed tool by default +svd2rust_bin="svd2rust" +# Automates the steps specified in https://docs.rs/svd2rust/0.19.0/svd2rust/ +if [ -f svd2rust ]; then + # If the local directory contains svd2rust, use that version instead + svd2rust_bin="./svd2rust" +elif [ -f ../svd2rust ]; then + # Keeps the repository clean + svd2rust_bin="../svd2rust" +fi +if [ -x "$(${svd2rust_bin} --version)" ]; then + echo "No svd2rust found locally or installed." \ + "Install it with cargo install svd2rust" + exit +fi + +if ! command -v form &> /dev/null +then + echo "form tool was not found" + exit 1 +fi + +if ! command -v svdtools &> /dev/null +then + echo "svdtools was not found" + exit 1 +fi + +svdtools patch svd/va108xx-patch.yml +# See https://github.com/rust-embedded/svd2rust/issues/830 for required re-export. +${svd2rust_bin} --reexport-interrupt --impl-defmt defmt --impl-debug-feature debug -i svd/va108xx.svd.patched + +result=$? +if [ $result -ne 0 ]; then + echo "svd2rust failed with code $result" + exit +fi + +rm -rf src +form -i lib.rs -o src/ && rm lib.rs +cargo fmt diff --git a/va108xx/va108xx/src/generic.rs b/va108xx/va108xx/src/generic.rs new file mode 100644 index 0000000..1bb995a --- /dev/null +++ b/va108xx/va108xx/src/generic.rs @@ -0,0 +1,768 @@ +use core::marker; +#[doc = " Generic peripheral accessor"] +pub struct Periph { + _marker: marker::PhantomData, +} +unsafe impl Send for Periph {} +impl Periph { + #[doc = "Pointer to the register block"] + pub const PTR: *const RB = A as *const _; + #[doc = "Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const RB { + Self::PTR + } + #[doc = " Steal an instance of this peripheral"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = " that may race with any existing instances, for example by only"] + #[doc = " accessing read-only or write-only registers, or by consuming the"] + #[doc = " original peripheral and using critical sections to coordinate"] + #[doc = " access between multiple new instances."] + #[doc = ""] + #[doc = " Additionally, other software such as HALs may rely on only one"] + #[doc = " peripheral instance existing to ensure memory safety; ensure"] + #[doc = " no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: marker::PhantomData, + } + } +} +impl core::ops::Deref for Periph { + type Target = RB; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " `0`"] + const ZERO: Self; + #[doc = " `1`"] + const ONE: Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + const ZERO: Self = 0; + const ONE: Self = 1; + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + impl FieldSpec for $U { + type Ux = $U; + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + core::fmt::Debug + PartialEq + From; +} +#[doc = " Marker for fields with fixed values"] +pub trait IsEnum: FieldSpec {} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec {} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Is it safe to write any bits to register"] + type Safety; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux = Self::Ux::ZERO; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc(hidden)] +pub mod raw; +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub type R = raw::R; +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub const fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub type W = raw::W; +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +impl W +where + REG: Writable, +{ + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub fn set(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = raw::FieldReader; +#[doc = " Bit-wise field reader"] +pub type BitReader = raw::BitReader; +impl FieldReader { + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub const fn bits(&self) -> FI::Ux { + self.bits + } +} +impl core::fmt::Debug for FieldReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +impl PartialEq for FieldReader +where + FI: FieldSpec + Copy, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&FI::Ux::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub const fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub const fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub const fn bit_is_set(&self) -> bool { + self.bit() + } +} +impl core::fmt::Debug for BitReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +#[doc = " Marker for register/field writers which can take any value of specified width"] +pub struct Safe; +#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] +pub struct Unsafe; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct Range; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeFrom; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeTo; +#[doc = " Write field Proxy"] +pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> = + raw::FieldWriter<'a, REG, WI, FI, Safety>; +impl FieldWriter<'_, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } +} +impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64> + FieldWriter<'a, REG, WI, FI, Range> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN && value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: IsEnum, + REG::Ux: From, +{ + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; + impl<'a, REG, FI> $writer<'a, REG, FI> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + Self::WIDTH + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, REG, FI> BitWriter<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> R { + R { + bits: self.register.get(), + _reg: marker::PhantomData, + } + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) -> REG::Ux + where + F: FnOnce(&mut W) -> &mut W, + { + let value = f(&mut W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }) + .bits; + self.register.set(value); + value + } + #[doc = " Writes bits to a `Writable` register and produce a value."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write_and(|w| {"] + #[doc = " w.field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write_and(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[doc = ""] + #[doc = " Values can be returned from the closure:"] + #[doc = " ```ignore"] + #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"] + #[doc = " ```"] + #[inline(always)] + pub fn from_write(&self, f: F) -> T + where + F: FnOnce(&mut W) -> T, + { + let mut writer = W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }; + let result = f(&mut writer); + self.register.set(writer.bits); + result + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) -> REG::Ux + where + F: FnOnce(&mut W) -> &mut W, + { + let value = f(&mut W { + bits: REG::Ux::ZERO, + _reg: marker::PhantomData, + }) + .bits; + self.register.set(value); + value + } + #[doc = " Writes 0 to a `Writable` register and produces a value."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn from_write_with_zero(&self, f: F) -> T + where + F: FnOnce(&mut W) -> T, + { + let mut writer = W { + bits: REG::Ux::ZERO, + _reg: marker::PhantomData, + }; + let result = f(&mut writer); + self.register.set(writer.bits); + result + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) -> REG::Ux + where + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, + { + let bits = self.register.get(); + let value = f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }, + ) + .bits; + self.register.set(value); + value + } + #[doc = " Modifies the contents of the register by reading and then writing it"] + #[doc = " and produces a value."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.modify(|r, w| {"] + #[doc = " let new_bits = r.bits() | 3;"] + #[doc = " unsafe {"] + #[doc = " w.bits(new_bits);"] + #[doc = " }"] + #[doc = ""] + #[doc = " new_bits"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn from_modify(&self, f: F) -> T + where + for<'w> F: FnOnce(&R, &'w mut W) -> T, + { + let bits = self.register.get(); + let mut writer = W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }; + let result = f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut writer, + ); + self.register.set(writer.bits); + result + } +} +impl core::fmt::Debug for crate::generic::Reg +where + R: core::fmt::Debug, +{ + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} diff --git a/va108xx/va108xx/src/generic/raw.rs b/va108xx/va108xx/src/generic/raw.rs new file mode 100644 index 0000000..d60a23a --- /dev/null +++ b/va108xx/va108xx/src/generic/raw.rs @@ -0,0 +1,95 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[must_use = "after creating `FieldWriter` you need to call field value setting method"] +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} +#[must_use = "after creating `BitWriter` you need to call bit setting method"] +pub struct BitWriter<'a, REG, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} diff --git a/va108xx/va108xx/src/i2ca.rs b/va108xx/va108xx/src/i2ca.rs new file mode 100644 index 0000000..63722b1 --- /dev/null +++ b/va108xx/va108xx/src/i2ca.rs @@ -0,0 +1,419 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + clkscale: Clkscale, + words: Words, + address: Address, + data: Data, + cmd: Cmd, + status: Status, + state: State, + txcount: Txcount, + rxcount: Rxcount, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + txfifoirqtrg: Txfifoirqtrg, + fifo_clr: FifoClr, + tmconfig: Tmconfig, + clktolimit: Clktolimit, + _reserved19: [u8; 0xb4], + s0_ctrl: S0Ctrl, + s0_maxwords: S0Maxwords, + s0_address: S0Address, + s0_addressmask: S0Addressmask, + s0_data: S0Data, + s0_lastaddress: S0Lastaddress, + s0_status: S0Status, + s0_state: S0State, + s0_txcount: S0Txcount, + s0_rxcount: S0Rxcount, + s0_irq_enb: S0IrqEnb, + s0_irq_raw: S0IrqRaw, + s0_irq_end: S0IrqEnd, + s0_irq_clr: S0IrqClr, + s0_rxfifoirqtrg: S0Rxfifoirqtrg, + s0_txfifoirqtrg: S0Txfifoirqtrg, + s0_fifo_clr: S0FifoClr, + s0_addressb: S0Addressb, + s0_addressmaskb: S0Addressmaskb, + _reserved38: [u8; 0x0eb0], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - Clock Scale divide value"] + #[inline(always)] + pub const fn clkscale(&self) -> &Clkscale { + &self.clkscale + } + #[doc = "0x08 - Word Count value"] + #[inline(always)] + pub const fn words(&self) -> &Words { + &self.words + } + #[doc = "0x0c - I2C Address value"] + #[inline(always)] + pub const fn address(&self) -> &Address { + &self.address + } + #[doc = "0x10 - Data Input/Output"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x14 - Command Register"] + #[inline(always)] + pub const fn cmd(&self) -> &Cmd { + &self.cmd + } + #[doc = "0x18 - I2C Controller Status Register"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x1c - Internal STATE of I2C Master Controller"] + #[inline(always)] + pub const fn state(&self) -> &State { + &self.state + } + #[doc = "0x20 - TX Count Register"] + #[inline(always)] + pub const fn txcount(&self) -> &Txcount { + &self.txcount + } + #[doc = "0x24 - RX Count Register"] + #[inline(always)] + pub const fn rxcount(&self) -> &Rxcount { + &self.rxcount + } + #[doc = "0x28 - Interrupt Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x2c - Raw Interrupt Status Register"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x30 - Enabled Interrupt Status Register"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x34 - Clear Interrupt Status Register"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x38 - Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x3c - Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x40 - Clear FIFO Register"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x44 - Timing Config Register"] + #[inline(always)] + pub const fn tmconfig(&self) -> &Tmconfig { + &self.tmconfig + } + #[doc = "0x48 - Clock Low Timeout Limit Register"] + #[inline(always)] + pub const fn clktolimit(&self) -> &Clktolimit { + &self.clktolimit + } + #[doc = "0x100 - Slave Control Register"] + #[inline(always)] + pub const fn s0_ctrl(&self) -> &S0Ctrl { + &self.s0_ctrl + } + #[doc = "0x104 - Slave MaxWords Register"] + #[inline(always)] + pub const fn s0_maxwords(&self) -> &S0Maxwords { + &self.s0_maxwords + } + #[doc = "0x108 - Slave I2C Address Value"] + #[inline(always)] + pub const fn s0_address(&self) -> &S0Address { + &self.s0_address + } + #[doc = "0x10c - Slave I2C Address Mask value"] + #[inline(always)] + pub const fn s0_addressmask(&self) -> &S0Addressmask { + &self.s0_addressmask + } + #[doc = "0x110 - Slave Data Input/Output"] + #[inline(always)] + pub const fn s0_data(&self) -> &S0Data { + &self.s0_data + } + #[doc = "0x114 - Slave I2C Last Address value"] + #[inline(always)] + pub const fn s0_lastaddress(&self) -> &S0Lastaddress { + &self.s0_lastaddress + } + #[doc = "0x118 - Slave I2C Controller Status Register"] + #[inline(always)] + pub const fn s0_status(&self) -> &S0Status { + &self.s0_status + } + #[doc = "0x11c - Internal STATE of I2C Slave Controller"] + #[inline(always)] + pub const fn s0_state(&self) -> &S0State { + &self.s0_state + } + #[doc = "0x120 - Slave TX Count Register"] + #[inline(always)] + pub const fn s0_txcount(&self) -> &S0Txcount { + &self.s0_txcount + } + #[doc = "0x124 - Slave RX Count Register"] + #[inline(always)] + pub const fn s0_rxcount(&self) -> &S0Rxcount { + &self.s0_rxcount + } + #[doc = "0x128 - Slave Interrupt Enable Register"] + #[inline(always)] + pub const fn s0_irq_enb(&self) -> &S0IrqEnb { + &self.s0_irq_enb + } + #[doc = "0x12c - Slave Raw Interrupt Status Register"] + #[inline(always)] + pub const fn s0_irq_raw(&self) -> &S0IrqRaw { + &self.s0_irq_raw + } + #[doc = "0x130 - Slave Enabled Interrupt Status Register"] + #[inline(always)] + pub const fn s0_irq_end(&self) -> &S0IrqEnd { + &self.s0_irq_end + } + #[doc = "0x134 - Slave Clear Interrupt Status Register"] + #[inline(always)] + pub const fn s0_irq_clr(&self) -> &S0IrqClr { + &self.s0_irq_clr + } + #[doc = "0x138 - Slave Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn s0_rxfifoirqtrg(&self) -> &S0Rxfifoirqtrg { + &self.s0_rxfifoirqtrg + } + #[doc = "0x13c - Slave Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn s0_txfifoirqtrg(&self) -> &S0Txfifoirqtrg { + &self.s0_txfifoirqtrg + } + #[doc = "0x140 - Slave Clear FIFO Register"] + #[inline(always)] + pub const fn s0_fifo_clr(&self) -> &S0FifoClr { + &self.s0_fifo_clr + } + #[doc = "0x144 - Slave I2C Address B Value"] + #[inline(always)] + pub const fn s0_addressb(&self) -> &S0Addressb { + &self.s0_addressb + } + #[doc = "0x148 - Slave I2C Address B Mask value"] + #[inline(always)] + pub const fn s0_addressmaskb(&self) -> &S0Addressmaskb { + &self.s0_addressmaskb + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] module"] +#[doc(alias = "CLKSCALE")] +pub type Clkscale = crate::Reg; +#[doc = "Clock Scale divide value"] +pub mod clkscale; +#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`] module"] +#[doc(alias = "WORDS")] +pub type Words = crate::Reg; +#[doc = "Word Count value"] +pub mod words; +#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`] module"] +#[doc(alias = "ADDRESS")] +pub type Address = crate::Reg; +#[doc = "I2C Address value"] +pub mod address; +#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data Input/Output"] +pub mod data; +#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"] +#[doc(alias = "CMD")] +pub type Cmd = crate::Reg; +#[doc = "Command Register"] +pub mod cmd; +#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "I2C Controller Status Register"] +pub mod status; +#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +#[doc(alias = "STATE")] +pub type State = crate::Reg; +#[doc = "Internal STATE of I2C Master Controller"] +pub mod state; +#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`] module"] +#[doc(alias = "TXCOUNT")] +pub type Txcount = crate::Reg; +#[doc = "TX Count Register"] +pub mod txcount; +#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`] module"] +#[doc(alias = "RXCOUNT")] +pub type Rxcount = crate::Reg; +#[doc = "RX Count Register"] +pub mod rxcount; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`] module"] +#[doc(alias = "TMCONFIG")] +pub type Tmconfig = crate::Reg; +#[doc = "Timing Config Register"] +pub mod tmconfig; +#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`] module"] +#[doc(alias = "CLKTOLIMIT")] +pub type Clktolimit = crate::Reg; +#[doc = "Clock Low Timeout Limit Register"] +pub mod clktolimit; +#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`] module"] +#[doc(alias = "S0_CTRL")] +pub type S0Ctrl = crate::Reg; +#[doc = "Slave Control Register"] +pub mod s0_ctrl; +#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`] module"] +#[doc(alias = "S0_MAXWORDS")] +pub type S0Maxwords = crate::Reg; +#[doc = "Slave MaxWords Register"] +pub mod s0_maxwords; +#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`] module"] +#[doc(alias = "S0_ADDRESS")] +pub type S0Address = crate::Reg; +#[doc = "Slave I2C Address Value"] +pub mod s0_address; +#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`] module"] +#[doc(alias = "S0_ADDRESSMASK")] +pub type S0Addressmask = crate::Reg; +#[doc = "Slave I2C Address Mask value"] +pub mod s0_addressmask; +#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`] module"] +#[doc(alias = "S0_DATA")] +pub type S0Data = crate::Reg; +#[doc = "Slave Data Input/Output"] +pub mod s0_data; +#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`] module"] +#[doc(alias = "S0_LASTADDRESS")] +pub type S0Lastaddress = crate::Reg; +#[doc = "Slave I2C Last Address value"] +pub mod s0_lastaddress; +#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`] module"] +#[doc(alias = "S0_STATUS")] +pub type S0Status = crate::Reg; +#[doc = "Slave I2C Controller Status Register"] +pub mod s0_status; +#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`] module"] +#[doc(alias = "S0_STATE")] +pub type S0State = crate::Reg; +#[doc = "Internal STATE of I2C Slave Controller"] +pub mod s0_state; +#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`] module"] +#[doc(alias = "S0_TXCOUNT")] +pub type S0Txcount = crate::Reg; +#[doc = "Slave TX Count Register"] +pub mod s0_txcount; +#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`] module"] +#[doc(alias = "S0_RXCOUNT")] +pub type S0Rxcount = crate::Reg; +#[doc = "Slave RX Count Register"] +pub mod s0_rxcount; +#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`] module"] +#[doc(alias = "S0_IRQ_ENB")] +pub type S0IrqEnb = crate::Reg; +#[doc = "Slave Interrupt Enable Register"] +pub mod s0_irq_enb; +pub use s0_irq_enb as s0_irq_raw; +pub use s0_irq_enb as s0_irq_end; +pub use s0_irq_enb as s0_irq_clr; +pub use S0IrqEnb as S0IrqRaw; +pub use S0IrqEnb as S0IrqEnd; +pub use S0IrqEnb as S0IrqClr; +#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`] module"] +#[doc(alias = "S0_RXFIFOIRQTRG")] +pub type S0Rxfifoirqtrg = crate::Reg; +#[doc = "Slave Rx FIFO IRQ Trigger Level"] +pub mod s0_rxfifoirqtrg; +#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`] module"] +#[doc(alias = "S0_TXFIFOIRQTRG")] +pub type S0Txfifoirqtrg = crate::Reg; +#[doc = "Slave Tx FIFO IRQ Trigger Level"] +pub mod s0_txfifoirqtrg; +#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`] module"] +#[doc(alias = "S0_FIFO_CLR")] +pub type S0FifoClr = crate::Reg; +#[doc = "Slave Clear FIFO Register"] +pub mod s0_fifo_clr; +#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`] module"] +#[doc(alias = "S0_ADDRESSB")] +pub type S0Addressb = crate::Reg; +#[doc = "Slave I2C Address B Value"] +pub mod s0_addressb; +#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`] module"] +#[doc(alias = "S0_ADDRESSMASKB")] +pub type S0Addressmaskb = crate::Reg; +#[doc = "Slave I2C Address B Mask value"] +pub mod s0_addressmaskb; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va108xx/va108xx/src/i2ca/address.rs b/va108xx/va108xx/src/i2ca/address.rs new file mode 100644 index 0000000..af668ea --- /dev/null +++ b/va108xx/va108xx/src/i2ca/address.rs @@ -0,0 +1,24 @@ +#[doc = "Register `ADDRESS` reader"] +pub type R = crate::R; +#[doc = "Register `ADDRESS` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AddressSpec; +impl crate::RegisterSpec for AddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`address::R`](R) reader structure"] +impl crate::Readable for AddressSpec {} +#[doc = "`write(|w| ..)` method takes [`address::W`](W) writer structure"] +impl crate::Writable for AddressSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADDRESS to value 0"] +impl crate::Resettable for AddressSpec {} diff --git a/va108xx/va108xx/src/i2ca/clkscale.rs b/va108xx/va108xx/src/i2ca/clkscale.rs new file mode 100644 index 0000000..1562308 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/clkscale.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CLKSCALE` reader"] +pub type R = crate::R; +#[doc = "Register `CLKSCALE` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` reader - Enable FastMode"] +pub type ValueR = crate::FieldReader; +#[doc = "Field `VALUE` writer - Enable FastMode"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `FASTMODE` reader - Enable FastMode"] +pub type FastmodeR = crate::BitReader; +#[doc = "Field `FASTMODE` writer - Enable FastMode"] +pub type FastmodeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - Enable FastMode"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - Enable FastMode"] + #[inline(always)] + pub fn fastmode(&self) -> FastmodeR { + FastmodeR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:30 - Enable FastMode"] + #[inline(always)] + pub fn value(&mut self) -> ValueW<'_, ClkscaleSpec> { + ValueW::new(self, 0) + } + #[doc = "Bit 31 - Enable FastMode"] + #[inline(always)] + pub fn fastmode(&mut self) -> FastmodeW<'_, ClkscaleSpec> { + FastmodeW::new(self, 31) + } +} +#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkscaleSpec; +impl crate::RegisterSpec for ClkscaleSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkscale::R`](R) reader structure"] +impl crate::Readable for ClkscaleSpec {} +#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"] +impl crate::Writable for ClkscaleSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKSCALE to value 0"] +impl crate::Resettable for ClkscaleSpec {} diff --git a/va108xx/va108xx/src/i2ca/clktolimit.rs b/va108xx/va108xx/src/i2ca/clktolimit.rs new file mode 100644 index 0000000..fa91d73 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/clktolimit.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKTOLIMIT` reader"] +pub type R = crate::R; +#[doc = "Register `CLKTOLIMIT` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClktolimitSpec; +impl crate::RegisterSpec for ClktolimitSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clktolimit::R`](R) reader structure"] +impl crate::Readable for ClktolimitSpec {} +#[doc = "`write(|w| ..)` method takes [`clktolimit::W`](W) writer structure"] +impl crate::Writable for ClktolimitSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKTOLIMIT to value 0"] +impl crate::Resettable for ClktolimitSpec {} diff --git a/va108xx/va108xx/src/i2ca/cmd.rs b/va108xx/va108xx/src/i2ca/cmd.rs new file mode 100644 index 0000000..bc295f0 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/cmd.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CMD` reader"] +pub type R = crate::R; +#[doc = "Register `CMD` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CmdSpec; +impl crate::RegisterSpec for CmdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmd::R`](R) reader structure"] +impl crate::Readable for CmdSpec {} +#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"] +impl crate::Writable for CmdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMD to value 0"] +impl crate::Resettable for CmdSpec {} diff --git a/va108xx/va108xx/src/i2ca/ctrl.rs b/va108xx/va108xx/src/i2ca/ctrl.rs new file mode 100644 index 0000000..cdd52e2 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/ctrl.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CLKENABLED` reader - I2C CLK Enabled"] +pub type ClkenabledR = crate::BitReader; +#[doc = "Field `CLKENABLED` writer - I2C CLK Enabled"] +pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - I2C Activated"] +pub type EnabledR = crate::BitReader; +#[doc = "Field `ENABLED` writer - I2C Activated"] +pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - I2C Active"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - I2C Active"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"] +pub type TxfemdR = crate::BitReader; +#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"] +pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"] +pub type RxffmdR = crate::BitReader; +#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"] +pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALGFILTER` reader - Enable Input Analog Glitch Filter"] +pub type AlgfilterR = crate::BitReader; +#[doc = "Field `ALGFILTER` writer - Enable Input Analog Glitch Filter"] +pub type AlgfilterW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DLGFILTER` reader - Enable Input Digital Glitch Filter"] +pub type DlgfilterR = crate::BitReader; +#[doc = "Field `DLGFILTER` writer - Enable Input Digital Glitch Filter"] +pub type DlgfilterW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACK` reader - Enable LoopBack Mode"] +pub type LoopbackR = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Enable LoopBack Mode"] +pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMCONFIGENB` reader - Enable Timing Config Register"] +pub type TmconfigenbR = crate::BitReader; +#[doc = "Field `TMCONFIGENB` writer - Enable Timing Config Register"] +pub type TmconfigenbW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C CLK Enabled"] + #[inline(always)] + pub fn clkenabled(&self) -> ClkenabledR { + ClkenabledR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&self) -> EnabledR { + EnabledR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&self) -> TxfemdR { + TxfemdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&self) -> RxffmdR { + RxffmdR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable Input Analog Glitch Filter"] + #[inline(always)] + pub fn algfilter(&self) -> AlgfilterR { + AlgfilterR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable Input Digital Glitch Filter"] + #[inline(always)] + pub fn dlgfilter(&self) -> DlgfilterR { + DlgfilterR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Enable LoopBack Mode"] + #[inline(always)] + pub fn loopback(&self) -> LoopbackR { + LoopbackR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable Timing Config Register"] + #[inline(always)] + pub fn tmconfigenb(&self) -> TmconfigenbR { + TmconfigenbR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C CLK Enabled"] + #[inline(always)] + pub fn clkenabled(&mut self) -> ClkenabledW<'_, CtrlSpec> { + ClkenabledW::new(self, 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&mut self) -> EnabledW<'_, CtrlSpec> { + EnabledW::new(self, 1) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, CtrlSpec> { + EnableW::new(self, 2) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&mut self) -> TxfemdW<'_, CtrlSpec> { + TxfemdW::new(self, 3) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&mut self) -> RxffmdW<'_, CtrlSpec> { + RxffmdW::new(self, 4) + } + #[doc = "Bit 5 - Enable Input Analog Glitch Filter"] + #[inline(always)] + pub fn algfilter(&mut self) -> AlgfilterW<'_, CtrlSpec> { + AlgfilterW::new(self, 5) + } + #[doc = "Bit 6 - Enable Input Digital Glitch Filter"] + #[inline(always)] + pub fn dlgfilter(&mut self) -> DlgfilterW<'_, CtrlSpec> { + DlgfilterW::new(self, 6) + } + #[doc = "Bit 8 - Enable LoopBack Mode"] + #[inline(always)] + pub fn loopback(&mut self) -> LoopbackW<'_, CtrlSpec> { + LoopbackW::new(self, 8) + } + #[doc = "Bit 9 - Enable Timing Config Register"] + #[inline(always)] + pub fn tmconfigenb(&mut self) -> TmconfigenbW<'_, CtrlSpec> { + TmconfigenbW::new(self, 9) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/va108xx/va108xx/src/i2ca/data.rs b/va108xx/va108xx/src/i2ca/data.rs new file mode 100644 index 0000000..8968f26 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/data.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec {} diff --git a/va108xx/va108xx/src/i2ca/fifo_clr.rs b/va108xx/va108xx/src/i2ca/fifo_clr.rs new file mode 100644 index 0000000..339ac41 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/fifo_clr.rs @@ -0,0 +1,29 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> { + TxfifoW::new(self, 1) + } +} +#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec {} diff --git a/va108xx/va108xx/src/i2ca/irq_enb.rs b/va108xx/va108xx/src/i2ca/irq_enb.rs new file mode 100644 index 0000000..df35253 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/irq_enb.rs @@ -0,0 +1,217 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"] +pub type I2cidleR = crate::BitReader; +#[doc = "Field `I2CIDLE` writer - I2C Bus is Idle"] +pub type I2cidleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub type StalledR = crate::BitReader; +#[doc = "Field `STALLED` writer - Controller is Stalled"] +pub type StalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub type ArblostR = crate::BitReader; +#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"] +pub type ArblostW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub type NackaddrR = crate::BitReader; +#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"] +pub type NackaddrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"] +pub type ClklotoR = crate::BitReader; +#[doc = "Field `CLKLOTO` writer - I2C Clock Low Timeout"] +pub type ClklotoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"] +pub type TxoverflowR = crate::BitReader; +#[doc = "Field `TXOVERFLOW` writer - TX FIFO Overflowed"] +pub type TxoverflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub type RxoverflowR = crate::BitReader; +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub type TxreadyR = crate::BitReader; +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub type RxreadyR = crate::BitReader; +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&self) -> I2cidleR { + I2cidleR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> StalledR { + StalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ArblostR { + ArblostR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NackaddrR { + NackaddrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&self) -> ClklotoR { + ClklotoR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&self) -> TxoverflowR { + TxoverflowR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RxoverflowR { + RxoverflowR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TxreadyR { + TxreadyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RxreadyR { + RxreadyR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&mut self) -> I2cidleW<'_, IrqEnbSpec> { + I2cidleW::new(self, 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IdleW<'_, IrqEnbSpec> { + IdleW::new(self, 1) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WaitingW<'_, IrqEnbSpec> { + WaitingW::new(self, 2) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&mut self) -> StalledW<'_, IrqEnbSpec> { + StalledW::new(self, 3) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ArblostW<'_, IrqEnbSpec> { + ArblostW::new(self, 4) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&mut self) -> NackaddrW<'_, IrqEnbSpec> { + NackaddrW::new(self, 5) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NackdataW<'_, IrqEnbSpec> { + NackdataW::new(self, 6) + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&mut self) -> ClklotoW<'_, IrqEnbSpec> { + ClklotoW::new(self, 7) + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&mut self) -> TxoverflowW<'_, IrqEnbSpec> { + TxoverflowW::new(self, 10) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&mut self) -> RxoverflowW<'_, IrqEnbSpec> { + RxoverflowW::new(self, 11) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&mut self) -> TxreadyW<'_, IrqEnbSpec> { + TxreadyW::new(self, 12) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&mut self) -> RxreadyW<'_, IrqEnbSpec> { + RxreadyW::new(self, 13) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TxemptyW<'_, IrqEnbSpec> { + TxemptyW::new(self, 14) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RxfullW<'_, IrqEnbSpec> { + RxfullW::new(self, 15) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va108xx/va108xx/src/i2ca/perid.rs b/va108xx/va108xx/src/i2ca/perid.rs new file mode 100644 index 0000000..cb9be57 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0014_07e1"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0014_07e1; +} diff --git a/va108xx/va108xx/src/i2ca/rxcount.rs b/va108xx/va108xx/src/i2ca/rxcount.rs new file mode 100644 index 0000000..eb4e7c1 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/rxcount.rs @@ -0,0 +1,17 @@ +#[doc = "Register `RXCOUNT` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxcountSpec; +impl crate::RegisterSpec for RxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxcount::R`](R) reader structure"] +impl crate::Readable for RxcountSpec {} +#[doc = "`reset()` method sets RXCOUNT to value 0"] +impl crate::Resettable for RxcountSpec {} diff --git a/va108xx/va108xx/src/i2ca/rxfifoirqtrg.rs b/va108xx/va108xx/src/i2ca/rxfifoirqtrg.rs new file mode 100644 index 0000000..e38d450 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/rxfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RxfifoirqtrgSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_address.rs b/va108xx/va108xx/src/i2ca/s0_address.rs new file mode 100644 index 0000000..11df17f --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_address.rs @@ -0,0 +1,24 @@ +#[doc = "Register `S0_ADDRESS` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESS` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressSpec; +impl crate::RegisterSpec for S0AddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_address::R`](R) reader structure"] +impl crate::Readable for S0AddressSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_address::W`](W) writer structure"] +impl crate::Writable for S0AddressSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_ADDRESS to value 0"] +impl crate::Resettable for S0AddressSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_addressb.rs b/va108xx/va108xx/src/i2ca/s0_addressb.rs new file mode 100644 index 0000000..977e1e8 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_addressb.rs @@ -0,0 +1,24 @@ +#[doc = "Register `S0_ADDRESSB` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESSB` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressbSpec; +impl crate::RegisterSpec for S0AddressbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_addressb::R`](R) reader structure"] +impl crate::Readable for S0AddressbSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_addressb::W`](W) writer structure"] +impl crate::Writable for S0AddressbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_ADDRESSB to value 0"] +impl crate::Resettable for S0AddressbSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_addressmask.rs b/va108xx/va108xx/src/i2ca/s0_addressmask.rs new file mode 100644 index 0000000..0280a3c --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_addressmask.rs @@ -0,0 +1,24 @@ +#[doc = "Register `S0_ADDRESSMASK` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESSMASK` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressmaskSpec; +impl crate::RegisterSpec for S0AddressmaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_addressmask::R`](R) reader structure"] +impl crate::Readable for S0AddressmaskSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_addressmask::W`](W) writer structure"] +impl crate::Writable for S0AddressmaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"] +impl crate::Resettable for S0AddressmaskSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_addressmaskb.rs b/va108xx/va108xx/src/i2ca/s0_addressmaskb.rs new file mode 100644 index 0000000..879849b --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_addressmaskb.rs @@ -0,0 +1,24 @@ +#[doc = "Register `S0_ADDRESSMASKB` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESSMASKB` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressmaskbSpec; +impl crate::RegisterSpec for S0AddressmaskbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_addressmaskb::R`](R) reader structure"] +impl crate::Readable for S0AddressmaskbSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_addressmaskb::W`](W) writer structure"] +impl crate::Writable for S0AddressmaskbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0"] +impl crate::Resettable for S0AddressmaskbSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_ctrl.rs b/va108xx/va108xx/src/i2ca/s0_ctrl.rs new file mode 100644 index 0000000..0bfde74 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_ctrl.rs @@ -0,0 +1,91 @@ +#[doc = "Register `S0_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `S0_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CLKENABLED` reader - I2C Enabled"] +pub type ClkenabledR = crate::BitReader; +#[doc = "Field `CLKENABLED` writer - I2C Enabled"] +pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - I2C Activated"] +pub type EnabledR = crate::BitReader; +#[doc = "Field `ENABLED` writer - I2C Activated"] +pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - I2C Active"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - I2C Active"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"] +pub type TxfemdR = crate::BitReader; +#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"] +pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"] +pub type RxffmdR = crate::BitReader; +#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"] +pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C Enabled"] + #[inline(always)] + pub fn clkenabled(&self) -> ClkenabledR { + ClkenabledR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&self) -> EnabledR { + EnabledR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&self) -> TxfemdR { + TxfemdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&self) -> RxffmdR { + RxffmdR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C Enabled"] + #[inline(always)] + pub fn clkenabled(&mut self) -> ClkenabledW<'_, S0CtrlSpec> { + ClkenabledW::new(self, 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&mut self) -> EnabledW<'_, S0CtrlSpec> { + EnabledW::new(self, 1) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, S0CtrlSpec> { + EnableW::new(self, 2) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&mut self) -> TxfemdW<'_, S0CtrlSpec> { + TxfemdW::new(self, 3) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&mut self) -> RxffmdW<'_, S0CtrlSpec> { + RxffmdW::new(self, 4) + } +} +#[doc = "Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0CtrlSpec; +impl crate::RegisterSpec for S0CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_ctrl::R`](R) reader structure"] +impl crate::Readable for S0CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_ctrl::W`](W) writer structure"] +impl crate::Writable for S0CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_CTRL to value 0"] +impl crate::Resettable for S0CtrlSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_data.rs b/va108xx/va108xx/src/i2ca/s0_data.rs new file mode 100644 index 0000000..356239d --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_data.rs @@ -0,0 +1,24 @@ +#[doc = "Register `S0_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `S0_DATA` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0DataSpec; +impl crate::RegisterSpec for S0DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_data::R`](R) reader structure"] +impl crate::Readable for S0DataSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_data::W`](W) writer structure"] +impl crate::Writable for S0DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_DATA to value 0"] +impl crate::Resettable for S0DataSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_fifo_clr.rs b/va108xx/va108xx/src/i2ca/s0_fifo_clr.rs new file mode 100644 index 0000000..b36d3e2 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_fifo_clr.rs @@ -0,0 +1,29 @@ +#[doc = "Register `S0_FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RxfifoW<'_, S0FifoClrSpec> { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TxfifoW<'_, S0FifoClrSpec> { + TxfifoW::new(self, 1) + } +} +#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0FifoClrSpec; +impl crate::RegisterSpec for S0FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`s0_fifo_clr::W`](W) writer structure"] +impl crate::Writable for S0FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_FIFO_CLR to value 0"] +impl crate::Resettable for S0FifoClrSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_irq_enb.rs b/va108xx/va108xx/src/i2ca/s0_irq_enb.rs new file mode 100644 index 0000000..47e6f08 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_irq_enb.rs @@ -0,0 +1,245 @@ +#[doc = "Register `S0_IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `S0_IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub type CompletedR = crate::BitReader; +#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"] +pub type CompletedW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub type TxstalledR = crate::BitReader; +#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"] +pub type TxstalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub type RxstalledR = crate::BitReader; +#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"] +pub type RxstalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub type AddressmatchR = crate::BitReader; +#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"] +pub type AddressmatchW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub type RxdatafirstR = crate::BitReader; +#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"] +pub type RxdatafirstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_START` reader - I2C Start Condition"] +pub type I2cStartR = crate::BitReader; +#[doc = "Field `I2C_START` writer - I2C Start Condition"] +pub type I2cStartW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"] +pub type I2cStopR = crate::BitReader; +#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"] +pub type I2cStopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"] +pub type TxunderflowR = crate::BitReader; +#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"] +pub type TxunderflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub type RxoverflowR = crate::BitReader; +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub type TxreadyR = crate::BitReader; +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub type RxreadyR = crate::BitReader; +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> CompletedR { + CompletedR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TxstalledR { + TxstalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RxstalledR { + RxstalledR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> AddressmatchR { + AddressmatchR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RxdatafirstR { + RxdatafirstR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&self) -> I2cStartR { + I2cStartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&self) -> I2cStopR { + I2cStopR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&self) -> TxunderflowR { + TxunderflowR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RxoverflowR { + RxoverflowR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TxreadyR { + TxreadyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RxreadyR { + RxreadyR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&mut self) -> CompletedW<'_, S0IrqEnbSpec> { + CompletedW::new(self, 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IdleW<'_, S0IrqEnbSpec> { + IdleW::new(self, 1) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WaitingW<'_, S0IrqEnbSpec> { + WaitingW::new(self, 2) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&mut self) -> TxstalledW<'_, S0IrqEnbSpec> { + TxstalledW::new(self, 3) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&mut self) -> RxstalledW<'_, S0IrqEnbSpec> { + RxstalledW::new(self, 4) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&mut self) -> AddressmatchW<'_, S0IrqEnbSpec> { + AddressmatchW::new(self, 5) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NackdataW<'_, S0IrqEnbSpec> { + NackdataW::new(self, 6) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&mut self) -> RxdatafirstW<'_, S0IrqEnbSpec> { + RxdatafirstW::new(self, 7) + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&mut self) -> I2cStartW<'_, S0IrqEnbSpec> { + I2cStartW::new(self, 8) + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&mut self) -> I2cStopW<'_, S0IrqEnbSpec> { + I2cStopW::new(self, 9) + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&mut self) -> TxunderflowW<'_, S0IrqEnbSpec> { + TxunderflowW::new(self, 10) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&mut self) -> RxoverflowW<'_, S0IrqEnbSpec> { + RxoverflowW::new(self, 11) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&mut self) -> TxreadyW<'_, S0IrqEnbSpec> { + TxreadyW::new(self, 12) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&mut self) -> RxreadyW<'_, S0IrqEnbSpec> { + RxreadyW::new(self, 13) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TxemptyW<'_, S0IrqEnbSpec> { + TxemptyW::new(self, 14) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RxfullW<'_, S0IrqEnbSpec> { + RxfullW::new(self, 15) + } +} +#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0IrqEnbSpec; +impl crate::RegisterSpec for S0IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_irq_enb::R`](R) reader structure"] +impl crate::Readable for S0IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"] +impl crate::Writable for S0IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_IRQ_ENB to value 0"] +impl crate::Resettable for S0IrqEnbSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_lastaddress.rs b/va108xx/va108xx/src/i2ca/s0_lastaddress.rs new file mode 100644 index 0000000..6e7e186 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_lastaddress.rs @@ -0,0 +1,17 @@ +#[doc = "Register `S0_LASTADDRESS` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0LastaddressSpec; +impl crate::RegisterSpec for S0LastaddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_lastaddress::R`](R) reader structure"] +impl crate::Readable for S0LastaddressSpec {} +#[doc = "`reset()` method sets S0_LASTADDRESS to value 0"] +impl crate::Resettable for S0LastaddressSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_maxwords.rs b/va108xx/va108xx/src/i2ca/s0_maxwords.rs new file mode 100644 index 0000000..edbfdff --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_maxwords.rs @@ -0,0 +1,24 @@ +#[doc = "Register `S0_MAXWORDS` reader"] +pub type R = crate::R; +#[doc = "Register `S0_MAXWORDS` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0MaxwordsSpec; +impl crate::RegisterSpec for S0MaxwordsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_maxwords::R`](R) reader structure"] +impl crate::Readable for S0MaxwordsSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_maxwords::W`](W) writer structure"] +impl crate::Writable for S0MaxwordsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_MAXWORDS to value 0"] +impl crate::Resettable for S0MaxwordsSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_rxcount.rs b/va108xx/va108xx/src/i2ca/s0_rxcount.rs new file mode 100644 index 0000000..0d001d3 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_rxcount.rs @@ -0,0 +1,17 @@ +#[doc = "Register `S0_RXCOUNT` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0RxcountSpec; +impl crate::RegisterSpec for S0RxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_rxcount::R`](R) reader structure"] +impl crate::Readable for S0RxcountSpec {} +#[doc = "`reset()` method sets S0_RXCOUNT to value 0"] +impl crate::Resettable for S0RxcountSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_rxfifoirqtrg.rs b/va108xx/va108xx/src/i2ca/s0_rxfifoirqtrg.rs new file mode 100644 index 0000000..20bb03b --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_rxfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `S0_RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `S0_RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0RxfifoirqtrgSpec; +impl crate::RegisterSpec for S0RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for S0RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for S0RxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"] +impl crate::Resettable for S0RxfifoirqtrgSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_state.rs b/va108xx/va108xx/src/i2ca/s0_state.rs new file mode 100644 index 0000000..19c09e3 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_state.rs @@ -0,0 +1,17 @@ +#[doc = "Register `S0_STATE` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0StateSpec; +impl crate::RegisterSpec for S0StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_state::R`](R) reader structure"] +impl crate::Readable for S0StateSpec {} +#[doc = "`reset()` method sets S0_STATE to value 0"] +impl crate::Resettable for S0StateSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_status.rs b/va108xx/va108xx/src/i2ca/s0_status.rs new file mode 100644 index 0000000..ae6e4bb --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_status.rs @@ -0,0 +1,132 @@ +#[doc = "Register `S0_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub type CompletedR = crate::BitReader; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub type TxstalledR = crate::BitReader; +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub type RxstalledR = crate::BitReader; +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub type AddressmatchR = crate::BitReader; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub type RxdatafirstR = crate::BitReader; +#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"] +pub type RxnemptyR = crate::BitReader; +#[doc = "Field `RXFULL` reader - RX FIFO is Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub type RxtriggerR = crate::BitReader; +#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXNFULL` reader - TX FIFO is Full"] +pub type TxnfullR = crate::BitReader; +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub type TxtriggerR = crate::BitReader; +#[doc = "Field `RAW_BUSY` reader - I2C Raw Busy value"] +pub type RawBusyR = crate::BitReader; +#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"] +pub type RawSdaR = crate::BitReader; +#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"] +pub type RawSclR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> CompletedR { + CompletedR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TxstalledR { + TxstalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RxstalledR { + RxstalledR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> AddressmatchR { + AddressmatchR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RxdatafirstR { + RxdatafirstR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&self) -> RxnemptyR { + RxnemptyR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RxtriggerR { + RxtriggerR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&self) -> TxnfullR { + TxnfullR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TxtriggerR { + TxtriggerR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 29 - I2C Raw Busy value"] + #[inline(always)] + pub fn raw_busy(&self) -> RawBusyR { + RawBusyR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&self) -> RawSdaR { + RawSdaR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&self) -> RawSclR { + RawSclR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0StatusSpec; +impl crate::RegisterSpec for S0StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_status::R`](R) reader structure"] +impl crate::Readable for S0StatusSpec {} +#[doc = "`reset()` method sets S0_STATUS to value 0"] +impl crate::Resettable for S0StatusSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_txcount.rs b/va108xx/va108xx/src/i2ca/s0_txcount.rs new file mode 100644 index 0000000..6e4c723 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_txcount.rs @@ -0,0 +1,17 @@ +#[doc = "Register `S0_TXCOUNT` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0TxcountSpec; +impl crate::RegisterSpec for S0TxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_txcount::R`](R) reader structure"] +impl crate::Readable for S0TxcountSpec {} +#[doc = "`reset()` method sets S0_TXCOUNT to value 0"] +impl crate::Resettable for S0TxcountSpec {} diff --git a/va108xx/va108xx/src/i2ca/s0_txfifoirqtrg.rs b/va108xx/va108xx/src/i2ca/s0_txfifoirqtrg.rs new file mode 100644 index 0000000..97bbec2 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/s0_txfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `S0_TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `S0_TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0TxfifoirqtrgSpec; +impl crate::RegisterSpec for S0TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for S0TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for S0TxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0"] +impl crate::Resettable for S0TxfifoirqtrgSpec {} diff --git a/va108xx/va108xx/src/i2ca/state.rs b/va108xx/va108xx/src/i2ca/state.rs new file mode 100644 index 0000000..e37bca4 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/state.rs @@ -0,0 +1,17 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StateSpec; +impl crate::RegisterSpec for StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for StateSpec {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for StateSpec {} diff --git a/va108xx/va108xx/src/i2ca/status.rs b/va108xx/va108xx/src/i2ca/status.rs new file mode 100644 index 0000000..bc47fcc --- /dev/null +++ b/va108xx/va108xx/src/i2ca/status.rs @@ -0,0 +1,118 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `I2C_IDLE` reader - I2C bus is Idle"] +pub type I2cIdleR = crate::BitReader; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub type StalledR = crate::BitReader; +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub type ArblostR = crate::BitReader; +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub type NackaddrR = crate::BitReader; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"] +pub type RxnemptyR = crate::BitReader; +#[doc = "Field `RXFULL` reader - RX FIFO is Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub type RxtriggerR = crate::BitReader; +#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXNFULL` reader - TX FIFO is Full"] +pub type TxnfullR = crate::BitReader; +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub type TxtriggerR = crate::BitReader; +#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"] +pub type RawSdaR = crate::BitReader; +#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"] +pub type RawSclR = crate::BitReader; +impl R { + #[doc = "Bit 0 - I2C bus is Idle"] + #[inline(always)] + pub fn i2c_idle(&self) -> I2cIdleR { + I2cIdleR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> StalledR { + StalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ArblostR { + ArblostR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NackaddrR { + NackaddrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&self) -> RxnemptyR { + RxnemptyR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RxtriggerR { + RxtriggerR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&self) -> TxnfullR { + TxnfullR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TxtriggerR { + TxtriggerR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&self) -> RawSdaR { + RawSdaR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&self) -> RawSclR { + RawSclR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec {} diff --git a/va108xx/va108xx/src/i2ca/tmconfig.rs b/va108xx/va108xx/src/i2ca/tmconfig.rs new file mode 100644 index 0000000..670f854 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/tmconfig.rs @@ -0,0 +1,24 @@ +#[doc = "Register `TMCONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `TMCONFIG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TmconfigSpec; +impl crate::RegisterSpec for TmconfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmconfig::R`](R) reader structure"] +impl crate::Readable for TmconfigSpec {} +#[doc = "`write(|w| ..)` method takes [`tmconfig::W`](W) writer structure"] +impl crate::Writable for TmconfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TMCONFIG to value 0"] +impl crate::Resettable for TmconfigSpec {} diff --git a/va108xx/va108xx/src/i2ca/txcount.rs b/va108xx/va108xx/src/i2ca/txcount.rs new file mode 100644 index 0000000..1a33820 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/txcount.rs @@ -0,0 +1,17 @@ +#[doc = "Register `TXCOUNT` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxcountSpec; +impl crate::RegisterSpec for TxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txcount::R`](R) reader structure"] +impl crate::Readable for TxcountSpec {} +#[doc = "`reset()` method sets TXCOUNT to value 0"] +impl crate::Resettable for TxcountSpec {} diff --git a/va108xx/va108xx/src/i2ca/txfifoirqtrg.rs b/va108xx/va108xx/src/i2ca/txfifoirqtrg.rs new file mode 100644 index 0000000..ea0e7d3 --- /dev/null +++ b/va108xx/va108xx/src/i2ca/txfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TxfifoirqtrgSpec {} diff --git a/va108xx/va108xx/src/i2ca/words.rs b/va108xx/va108xx/src/i2ca/words.rs new file mode 100644 index 0000000..ac3f45c --- /dev/null +++ b/va108xx/va108xx/src/i2ca/words.rs @@ -0,0 +1,24 @@ +#[doc = "Register `WORDS` reader"] +pub type R = crate::R; +#[doc = "Register `WORDS` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WordsSpec; +impl crate::RegisterSpec for WordsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`words::R`](R) reader structure"] +impl crate::Readable for WordsSpec {} +#[doc = "`write(|w| ..)` method takes [`words::W`](W) writer structure"] +impl crate::Writable for WordsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORDS to value 0"] +impl crate::Resettable for WordsSpec {} diff --git a/va108xx/va108xx/src/ioconfig.rs b/va108xx/va108xx/src/ioconfig.rs new file mode 100644 index 0000000..a46cf9f --- /dev/null +++ b/va108xx/va108xx/src/ioconfig.rs @@ -0,0 +1,49 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + porta: [Porta; 32], + portb: [Portb; 32], + _reserved2: [u8; 0x0efc], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00..0x80 - PORTA Pin Configuration Register"] + #[inline(always)] + pub const fn porta(&self, n: usize) -> &Porta { + &self.porta[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x80 - PORTA Pin Configuration Register"] + #[inline(always)] + pub fn porta_iter(&self) -> impl Iterator { + self.porta.iter() + } + #[doc = "0x80..0x100 - PORTB Pin Configuration Register"] + #[inline(always)] + pub const fn portb(&self, n: usize) -> &Portb { + &self.portb[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x80..0x100 - PORTB Pin Configuration Register"] + #[inline(always)] + pub fn portb_iter(&self) -> impl Iterator { + self.portb.iter() + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`] module"] +#[doc(alias = "PORTA")] +pub type Porta = crate::Reg; +#[doc = "PORTA Pin Configuration Register"] +pub mod porta; +pub use porta as portb; +pub use Porta as Portb; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va108xx/va108xx/src/ioconfig/perid.rs b/va108xx/va108xx/src/ioconfig/perid.rs new file mode 100644 index 0000000..170c08a --- /dev/null +++ b/va108xx/va108xx/src/ioconfig/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0082_07e1"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0082_07e1; +} diff --git a/va108xx/va108xx/src/ioconfig/porta.rs b/va108xx/va108xx/src/ioconfig/porta.rs new file mode 100644 index 0000000..26249e8 --- /dev/null +++ b/va108xx/va108xx/src/ioconfig/porta.rs @@ -0,0 +1,284 @@ +#[doc = "Register `PORTA[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `PORTA[%s]` writer"] +pub type W = crate::W; +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Flttype { + #[doc = "0: Synchronize to system clock"] + Sync = 0, + #[doc = "1: Direct input, no synchronization"] + Direct = 1, + #[doc = "2: Require 2 samples to have the same value"] + Filter1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + Filter2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + Filter3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + Filter4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Flttype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Flttype { + type Ux = u8; +} +impl crate::IsEnum for Flttype {} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub type FlttypeR = crate::FieldReader; +impl FlttypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Flttype::Sync), + 1 => Some(Flttype::Direct), + 2 => Some(Flttype::Filter1), + 3 => Some(Flttype::Filter2), + 4 => Some(Flttype::Filter3), + 5 => Some(Flttype::Filter4), + _ => None, + } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + *self == Flttype::Sync + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + *self == Flttype::Direct + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + *self == Flttype::Filter1 + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + *self == Flttype::Filter2 + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + *self == Flttype::Filter3 + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + *self == Flttype::Filter4 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub type FlttypeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Flttype>; +impl<'a, REG> FlttypeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut crate::W { + self.variant(Flttype::Sync) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut crate::W { + self.variant(Flttype::Direct) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut crate::W { + self.variant(Flttype::Filter1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut crate::W { + self.variant(Flttype::Filter2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut crate::W { + self.variant(Flttype::Filter3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut crate::W { + self.variant(Flttype::Filter4) + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub type FltclkR = crate::FieldReader; +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub type FltclkW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub type InvinpR = crate::BitReader; +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub type InvinpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub type IewoR = crate::BitReader; +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub type IewoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub type OpendrnR = crate::BitReader; +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub type OpendrnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub type InvoutR = crate::BitReader; +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub type InvoutW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub type PlevelR = crate::BitReader; +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub type PlevelW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub type PenR = crate::BitReader; +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub type PenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub type PwoaR = crate::BitReader; +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub type PwoaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub type FunselR = crate::FieldReader; +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub type FunselW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub type IodisR = crate::BitReader; +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub type IodisW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FlttypeR { + FlttypeR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FltclkR { + FltclkR::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> InvinpR { + InvinpR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IewoR { + IewoR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OpendrnR { + OpendrnR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> InvoutR { + InvoutR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PlevelR { + PlevelR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PenR { + PenR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PwoaR { + PwoaR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FunselR { + FunselR::new(((self.bits >> 13) & 7) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IodisR { + IodisR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&mut self) -> FlttypeW<'_, PortaSpec> { + FlttypeW::new(self, 0) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&mut self) -> FltclkW<'_, PortaSpec> { + FltclkW::new(self, 3) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&mut self) -> InvinpW<'_, PortaSpec> { + InvinpW::new(self, 6) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&mut self) -> IewoW<'_, PortaSpec> { + IewoW::new(self, 7) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&mut self) -> OpendrnW<'_, PortaSpec> { + OpendrnW::new(self, 8) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&mut self) -> InvoutW<'_, PortaSpec> { + InvoutW::new(self, 9) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&mut self) -> PlevelW<'_, PortaSpec> { + PlevelW::new(self, 10) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&mut self) -> PenW<'_, PortaSpec> { + PenW::new(self, 11) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&mut self) -> PwoaW<'_, PortaSpec> { + PwoaW::new(self, 12) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&mut self) -> FunselW<'_, PortaSpec> { + FunselW::new(self, 13) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&mut self) -> IodisW<'_, PortaSpec> { + IodisW::new(self, 16) + } +} +#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PortaSpec; +impl crate::RegisterSpec for PortaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`porta::R`](R) reader structure"] +impl crate::Readable for PortaSpec {} +#[doc = "`write(|w| ..)` method takes [`porta::W`](W) writer structure"] +impl crate::Writable for PortaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PORTA[%s] to value 0"] +impl crate::Resettable for PortaSpec {} diff --git a/va108xx/va108xx/src/irqsel.rs b/va108xx/va108xx/src/irqsel.rs new file mode 100644 index 0000000..ba9309f --- /dev/null +++ b/va108xx/va108xx/src/irqsel.rs @@ -0,0 +1,218 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + porta: [Porta; 32], + portb: [Portb; 32], + tim: [Tim; 32], + uart: [Uart; 4], + spi: [Spi; 4], + i2c_ms: [I2cMs; 4], + i2c_sl: [I2cSl; 4], + int_ram_sbe: IntRamSbe, + int_ram_mbe: IntRamMbe, + int_rom_sbe: IntRomSbe, + int_rom_mbe: IntRomMbe, + txev: Txev, + _reserved12: [u8; 0x062c], + irqs: [Irqs; 32], + _reserved13: [u8; 0x68], + edbgrq: Edbgrq, + mereset: Mereset, + watchdog: Watchdog, + rxev: Rxev, + nmi: Nmi, + _reserved18: [u8; 0x0700], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"] + #[inline(always)] + pub const fn porta(&self, n: usize) -> &Porta { + &self.porta[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"] + #[inline(always)] + pub fn porta_iter(&self) -> impl Iterator { + self.porta.iter() + } + #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"] + #[inline(always)] + pub const fn portb(&self, n: usize) -> &Portb { + &self.portb[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"] + #[inline(always)] + pub fn portb_iter(&self) -> impl Iterator { + self.portb.iter() + } + #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"] + #[inline(always)] + pub const fn tim(&self, n: usize) -> &Tim { + &self.tim[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"] + #[inline(always)] + pub fn tim_iter(&self) -> impl Iterator { + self.tim.iter() + } + #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"] + #[inline(always)] + pub const fn uart(&self, n: usize) -> &Uart { + &self.uart[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"] + #[inline(always)] + pub fn uart_iter(&self) -> impl Iterator { + self.uart.iter() + } + #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"] + #[inline(always)] + pub const fn spi(&self, n: usize) -> &Spi { + &self.spi[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"] + #[inline(always)] + pub fn spi_iter(&self) -> impl Iterator { + self.spi.iter() + } + #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"] + #[inline(always)] + pub const fn i2c_ms(&self, n: usize) -> &I2cMs { + &self.i2c_ms[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"] + #[inline(always)] + pub fn i2c_ms_iter(&self) -> impl Iterator { + self.i2c_ms.iter() + } + #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"] + #[inline(always)] + pub const fn i2c_sl(&self, n: usize) -> &I2cSl { + &self.i2c_sl[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"] + #[inline(always)] + pub fn i2c_sl_iter(&self) -> impl Iterator { + self.i2c_sl.iter() + } + #[doc = "0x1c0 - Internal Memory RAM SBE Interrupt Redirect Selection"] + #[inline(always)] + pub const fn int_ram_sbe(&self) -> &IntRamSbe { + &self.int_ram_sbe + } + #[doc = "0x1c4 - Internal Memory RAM MBE Interrupt Redirect Selection"] + #[inline(always)] + pub const fn int_ram_mbe(&self) -> &IntRamMbe { + &self.int_ram_mbe + } + #[doc = "0x1c8 - Internal Memory ROM SBE Interrupt Redirect Selection"] + #[inline(always)] + pub const fn int_rom_sbe(&self) -> &IntRomSbe { + &self.int_rom_sbe + } + #[doc = "0x1cc - Internal Memory ROM MBE Interrupt Redirect Selection"] + #[inline(always)] + pub const fn int_rom_mbe(&self) -> &IntRomMbe { + &self.int_rom_mbe + } + #[doc = "0x1d0 - Processor TXEV Interrupt Redirect Selection"] + #[inline(always)] + pub const fn txev(&self) -> &Txev { + &self.txev + } + #[doc = "0x800..0x880 - Interrupt Status Register"] + #[inline(always)] + pub const fn irqs(&self, n: usize) -> &Irqs { + &self.irqs[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x800..0x880 - Interrupt Status Register"] + #[inline(always)] + pub fn irqs_iter(&self) -> impl Iterator { + self.irqs.iter() + } + #[doc = "0x8e8 - EDBGRQ Status Register"] + #[inline(always)] + pub const fn edbgrq(&self) -> &Edbgrq { + &self.edbgrq + } + #[doc = "0x8ec - MERESET Status Register"] + #[inline(always)] + pub const fn mereset(&self) -> &Mereset { + &self.mereset + } + #[doc = "0x8f0 - WATCHDOG Status Register"] + #[inline(always)] + pub const fn watchdog(&self) -> &Watchdog { + &self.watchdog + } + #[doc = "0x8f4 - RXEV Status Register"] + #[inline(always)] + pub const fn rxev(&self) -> &Rxev { + &self.rxev + } + #[doc = "0x8f8 - NMI Status Register"] + #[inline(always)] + pub const fn nmi(&self) -> &Nmi { + &self.nmi + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`] module"] +#[doc(alias = "INT_RAM_SBE")] +pub type IntRamSbe = crate::Reg; +#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection"] +pub mod int_ram_sbe; +pub use int_ram_sbe as porta; +pub use int_ram_sbe as portb; +pub use int_ram_sbe as tim; +pub use int_ram_sbe as uart; +pub use int_ram_sbe as spi; +pub use int_ram_sbe as i2c_ms; +pub use int_ram_sbe as i2c_sl; +pub use int_ram_sbe as int_ram_mbe; +pub use int_ram_sbe as int_rom_sbe; +pub use int_ram_sbe as int_rom_mbe; +pub use int_ram_sbe as txev; +pub use IntRamSbe as Porta; +pub use IntRamSbe as Portb; +pub use IntRamSbe as Tim; +pub use IntRamSbe as Uart; +pub use IntRamSbe as Spi; +pub use IntRamSbe as I2cMs; +pub use IntRamSbe as I2cSl; +pub use IntRamSbe as IntRamMbe; +pub use IntRamSbe as IntRomSbe; +pub use IntRamSbe as IntRomMbe; +pub use IntRamSbe as Txev; +#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`] module"] +#[doc(alias = "NMI")] +pub type Nmi = crate::Reg; +#[doc = "NMI Status Register"] +pub mod nmi; +pub use nmi as rxev; +pub use nmi as watchdog; +pub use nmi as mereset; +pub use nmi as edbgrq; +pub use nmi as irqs; +pub use Nmi as Rxev; +pub use Nmi as Watchdog; +pub use Nmi as Mereset; +pub use Nmi as Edbgrq; +pub use Nmi as Irqs; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va108xx/va108xx/src/irqsel/int_ram_sbe.rs b/va108xx/va108xx/src/irqsel/int_ram_sbe.rs new file mode 100644 index 0000000..49f01e1 --- /dev/null +++ b/va108xx/va108xx/src/irqsel/int_ram_sbe.rs @@ -0,0 +1,26 @@ +#[doc = "Register `INT_RAM_SBE` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAM_SBE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntRamSbeSpec; +impl crate::RegisterSpec for IntRamSbeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ram_sbe::R`](R) reader structure"] +impl crate::Readable for IntRamSbeSpec {} +#[doc = "`write(|w| ..)` method takes [`int_ram_sbe::W`](W) writer structure"] +impl crate::Writable for IntRamSbeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets INT_RAM_SBE to value 0xffff_ffff"] +impl crate::Resettable for IntRamSbeSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va108xx/va108xx/src/irqsel/nmi.rs b/va108xx/va108xx/src/irqsel/nmi.rs new file mode 100644 index 0000000..008ce1d --- /dev/null +++ b/va108xx/va108xx/src/irqsel/nmi.rs @@ -0,0 +1,20 @@ +#[doc = "Register `NMI` reader"] +pub type R = crate::R; +#[doc = "Field `ACTIVE` reader - Active"] +pub type ActiveR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Active"] + #[inline(always)] + pub fn active(&self) -> ActiveR { + ActiveR::new((self.bits & 1) != 0) + } +} +#[doc = "NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NmiSpec; +impl crate::RegisterSpec for NmiSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`nmi::R`](R) reader structure"] +impl crate::Readable for NmiSpec {} +#[doc = "`reset()` method sets NMI to value 0"] +impl crate::Resettable for NmiSpec {} diff --git a/va108xx/va108xx/src/irqsel/perid.rs b/va108xx/va108xx/src/irqsel/perid.rs new file mode 100644 index 0000000..0593594 --- /dev/null +++ b/va108xx/va108xx/src/irqsel/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0080_07e1"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0080_07e1; +} diff --git a/va108xx/va108xx/src/lib.rs b/va108xx/va108xx/src/lib.rs new file mode 100644 index 0000000..f1584d8 --- /dev/null +++ b/va108xx/va108xx/src/lib.rs @@ -0,0 +1,644 @@ +#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.37.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn OC0(); + fn OC1(); + fn OC2(); + fn OC3(); + fn OC4(); + fn OC5(); + fn OC6(); + fn OC7(); + fn OC8(); + fn OC9(); + fn OC10(); + fn OC11(); + fn OC12(); + fn OC13(); + fn OC14(); + fn OC15(); + fn OC16(); + fn OC17(); + fn OC18(); + fn OC19(); + fn OC20(); + fn OC21(); + fn OC22(); + fn OC23(); + fn OC24(); + fn OC25(); + fn OC26(); + fn OC27(); + fn OC28(); + fn OC29(); + fn OC30(); + fn OC31(); +} +#[doc(hidden)] +#[repr(C)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 32] = [ + Vector { _handler: OC0 }, + Vector { _handler: OC1 }, + Vector { _handler: OC2 }, + Vector { _handler: OC3 }, + Vector { _handler: OC4 }, + Vector { _handler: OC5 }, + Vector { _handler: OC6 }, + Vector { _handler: OC7 }, + Vector { _handler: OC8 }, + Vector { _handler: OC9 }, + Vector { _handler: OC10 }, + Vector { _handler: OC11 }, + Vector { _handler: OC12 }, + Vector { _handler: OC13 }, + Vector { _handler: OC14 }, + Vector { _handler: OC15 }, + Vector { _handler: OC16 }, + Vector { _handler: OC17 }, + Vector { _handler: OC18 }, + Vector { _handler: OC19 }, + Vector { _handler: OC20 }, + Vector { _handler: OC21 }, + Vector { _handler: OC22 }, + Vector { _handler: OC23 }, + Vector { _handler: OC24 }, + Vector { _handler: OC25 }, + Vector { _handler: OC26 }, + Vector { _handler: OC27 }, + Vector { _handler: OC28 }, + Vector { _handler: OC29 }, + Vector { _handler: OC30 }, + Vector { _handler: OC31 }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - OC0"] + OC0 = 0, + #[doc = "1 - OC1"] + OC1 = 1, + #[doc = "2 - OC2"] + OC2 = 2, + #[doc = "3 - OC3"] + OC3 = 3, + #[doc = "4 - OC4"] + OC4 = 4, + #[doc = "5 - OC5"] + OC5 = 5, + #[doc = "6 - OC6"] + OC6 = 6, + #[doc = "7 - OC7"] + OC7 = 7, + #[doc = "8 - OC8"] + OC8 = 8, + #[doc = "9 - OC9"] + OC9 = 9, + #[doc = "10 - OC10"] + OC10 = 10, + #[doc = "11 - OC11"] + OC11 = 11, + #[doc = "12 - OC12"] + OC12 = 12, + #[doc = "13 - OC13"] + OC13 = 13, + #[doc = "14 - OC14"] + OC14 = 14, + #[doc = "15 - OC15"] + OC15 = 15, + #[doc = "16 - OC16"] + OC16 = 16, + #[doc = "17 - OC17"] + OC17 = 17, + #[doc = "18 - OC18"] + OC18 = 18, + #[doc = "19 - OC19"] + OC19 = 19, + #[doc = "20 - OC20"] + OC20 = 20, + #[doc = "21 - OC21"] + OC21 = 21, + #[doc = "22 - OC22"] + OC22 = 22, + #[doc = "23 - OC23"] + OC23 = 23, + #[doc = "24 - OC24"] + OC24 = 24, + #[doc = "25 - OC25"] + OC25 = 25, + #[doc = "26 - OC26"] + OC26 = 26, + #[doc = "27 - OC27"] + OC27 = 27, + #[doc = "28 - OC28"] + OC28 = 28, + #[doc = "29 - OC29"] + OC29 = 29, + #[doc = "30 - OC30"] + OC30 = 30, + #[doc = "31 - OC31"] + OC31 = 31, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "System Configuration Peripheral"] +pub type Sysconfig = crate::Periph; +impl core::fmt::Debug for Sysconfig { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sysconfig").finish() + } +} +#[doc = "System Configuration Peripheral"] +pub mod sysconfig; +#[doc = "Interrupt Selector Peripheral"] +pub type Irqsel = crate::Periph; +impl core::fmt::Debug for Irqsel { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Irqsel").finish() + } +} +#[doc = "Interrupt Selector Peripheral"] +pub mod irqsel; +#[doc = "IO Pin Configuration Peripheral"] +pub type Ioconfig = crate::Periph; +impl core::fmt::Debug for Ioconfig { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ioconfig").finish() + } +} +#[doc = "IO Pin Configuration Peripheral"] +pub mod ioconfig; +#[doc = "Utility Peripheral"] +pub type Utility = crate::Periph; +impl core::fmt::Debug for Utility { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Utility").finish() + } +} +#[doc = "Utility Peripheral"] +pub mod utility; +#[doc = "GPIO Peripheral"] +pub type Porta = crate::Periph; +impl core::fmt::Debug for Porta { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Porta").finish() + } +} +#[doc = "GPIO Peripheral"] +pub mod porta; +#[doc = "GPIO Peripheral"] +pub type Portb = crate::Periph; +impl core::fmt::Debug for Portb { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portb").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portb; +#[doc = "Timer/Counter Peripheral"] +pub type Tim0 = crate::Periph; +impl core::fmt::Debug for Tim0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim0").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub mod tim0; +#[doc = "Timer/Counter Peripheral"] +pub type Tim1 = crate::Periph; +impl core::fmt::Debug for Tim1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim1").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim1; +#[doc = "Timer/Counter Peripheral"] +pub type Tim2 = crate::Periph; +impl core::fmt::Debug for Tim2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim2").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim2; +#[doc = "Timer/Counter Peripheral"] +pub type Tim3 = crate::Periph; +impl core::fmt::Debug for Tim3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim3").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim3; +#[doc = "Timer/Counter Peripheral"] +pub type Tim4 = crate::Periph; +impl core::fmt::Debug for Tim4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim4").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim4; +#[doc = "Timer/Counter Peripheral"] +pub type Tim5 = crate::Periph; +impl core::fmt::Debug for Tim5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim5").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim5; +#[doc = "Timer/Counter Peripheral"] +pub type Tim6 = crate::Periph; +impl core::fmt::Debug for Tim6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim6").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim6; +#[doc = "Timer/Counter Peripheral"] +pub type Tim7 = crate::Periph; +impl core::fmt::Debug for Tim7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim7").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim7; +#[doc = "Timer/Counter Peripheral"] +pub type Tim8 = crate::Periph; +impl core::fmt::Debug for Tim8 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim8").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim8; +#[doc = "Timer/Counter Peripheral"] +pub type Tim9 = crate::Periph; +impl core::fmt::Debug for Tim9 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim9").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim9; +#[doc = "Timer/Counter Peripheral"] +pub type Tim10 = crate::Periph; +impl core::fmt::Debug for Tim10 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim10").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim10; +#[doc = "Timer/Counter Peripheral"] +pub type Tim11 = crate::Periph; +impl core::fmt::Debug for Tim11 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim11").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim11; +#[doc = "Timer/Counter Peripheral"] +pub type Tim12 = crate::Periph; +impl core::fmt::Debug for Tim12 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim12").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim12; +#[doc = "Timer/Counter Peripheral"] +pub type Tim13 = crate::Periph; +impl core::fmt::Debug for Tim13 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim13").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim13; +#[doc = "Timer/Counter Peripheral"] +pub type Tim14 = crate::Periph; +impl core::fmt::Debug for Tim14 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim14").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim14; +#[doc = "Timer/Counter Peripheral"] +pub type Tim15 = crate::Periph; +impl core::fmt::Debug for Tim15 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim15").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim15; +#[doc = "Timer/Counter Peripheral"] +pub type Tim16 = crate::Periph; +impl core::fmt::Debug for Tim16 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim16").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim16; +#[doc = "Timer/Counter Peripheral"] +pub type Tim17 = crate::Periph; +impl core::fmt::Debug for Tim17 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim17").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim17; +#[doc = "Timer/Counter Peripheral"] +pub type Tim18 = crate::Periph; +impl core::fmt::Debug for Tim18 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim18").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim18; +#[doc = "Timer/Counter Peripheral"] +pub type Tim19 = crate::Periph; +impl core::fmt::Debug for Tim19 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim19").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim19; +#[doc = "Timer/Counter Peripheral"] +pub type Tim20 = crate::Periph; +impl core::fmt::Debug for Tim20 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim20").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim20; +#[doc = "Timer/Counter Peripheral"] +pub type Tim21 = crate::Periph; +impl core::fmt::Debug for Tim21 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim21").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim21; +#[doc = "Timer/Counter Peripheral"] +pub type Tim22 = crate::Periph; +impl core::fmt::Debug for Tim22 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim22").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim22; +#[doc = "Timer/Counter Peripheral"] +pub type Tim23 = crate::Periph; +impl core::fmt::Debug for Tim23 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim23").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim23; +#[doc = "UART Peripheral"] +pub type Uarta = crate::Periph; +impl core::fmt::Debug for Uarta { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Uarta").finish() + } +} +#[doc = "UART Peripheral"] +pub mod uarta; +#[doc = "UART Peripheral"] +pub type Uartb = crate::Periph; +impl core::fmt::Debug for Uartb { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Uartb").finish() + } +} +#[doc = "UART Peripheral"] +pub use self::uarta as uartb; +#[doc = "SPI Peripheral"] +pub type Spia = crate::Periph; +impl core::fmt::Debug for Spia { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spia").finish() + } +} +#[doc = "SPI Peripheral"] +pub mod spia; +#[doc = "SPI Peripheral"] +pub type Spib = crate::Periph; +impl core::fmt::Debug for Spib { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spib").finish() + } +} +#[doc = "SPI Peripheral"] +pub use self::spia as spib; +#[doc = "SPI Peripheral"] +pub type Spic = crate::Periph; +impl core::fmt::Debug for Spic { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spic").finish() + } +} +#[doc = "SPI Peripheral"] +pub use self::spia as spic; +#[doc = "I2C Peripheral"] +pub type I2ca = crate::Periph; +impl core::fmt::Debug for I2ca { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2ca").finish() + } +} +#[doc = "I2C Peripheral"] +pub mod i2ca; +#[doc = "I2C Peripheral"] +pub type I2cb = crate::Periph; +impl core::fmt::Debug for I2cb { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2cb").finish() + } +} +#[doc = "I2C Peripheral"] +pub use self::i2ca as i2cb; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "SYSCONFIG"] + pub sysconfig: Sysconfig, + #[doc = "IRQSEL"] + pub irqsel: Irqsel, + #[doc = "IOCONFIG"] + pub ioconfig: Ioconfig, + #[doc = "UTILITY"] + pub utility: Utility, + #[doc = "PORTA"] + pub porta: Porta, + #[doc = "PORTB"] + pub portb: Portb, + #[doc = "TIM0"] + pub tim0: Tim0, + #[doc = "TIM1"] + pub tim1: Tim1, + #[doc = "TIM2"] + pub tim2: Tim2, + #[doc = "TIM3"] + pub tim3: Tim3, + #[doc = "TIM4"] + pub tim4: Tim4, + #[doc = "TIM5"] + pub tim5: Tim5, + #[doc = "TIM6"] + pub tim6: Tim6, + #[doc = "TIM7"] + pub tim7: Tim7, + #[doc = "TIM8"] + pub tim8: Tim8, + #[doc = "TIM9"] + pub tim9: Tim9, + #[doc = "TIM10"] + pub tim10: Tim10, + #[doc = "TIM11"] + pub tim11: Tim11, + #[doc = "TIM12"] + pub tim12: Tim12, + #[doc = "TIM13"] + pub tim13: Tim13, + #[doc = "TIM14"] + pub tim14: Tim14, + #[doc = "TIM15"] + pub tim15: Tim15, + #[doc = "TIM16"] + pub tim16: Tim16, + #[doc = "TIM17"] + pub tim17: Tim17, + #[doc = "TIM18"] + pub tim18: Tim18, + #[doc = "TIM19"] + pub tim19: Tim19, + #[doc = "TIM20"] + pub tim20: Tim20, + #[doc = "TIM21"] + pub tim21: Tim21, + #[doc = "TIM22"] + pub tim22: Tim22, + #[doc = "TIM23"] + pub tim23: Tim23, + #[doc = "UARTA"] + pub uarta: Uarta, + #[doc = "UARTB"] + pub uartb: Uartb, + #[doc = "SPIA"] + pub spia: Spia, + #[doc = "SPIB"] + pub spib: Spib, + #[doc = "SPIC"] + pub spic: Spic, + #[doc = "I2CA"] + pub i2ca: I2ca, + #[doc = "I2CB"] + pub i2cb: I2cb, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + sysconfig: Sysconfig::steal(), + irqsel: Irqsel::steal(), + ioconfig: Ioconfig::steal(), + utility: Utility::steal(), + porta: Porta::steal(), + portb: Portb::steal(), + tim0: Tim0::steal(), + tim1: Tim1::steal(), + tim2: Tim2::steal(), + tim3: Tim3::steal(), + tim4: Tim4::steal(), + tim5: Tim5::steal(), + tim6: Tim6::steal(), + tim7: Tim7::steal(), + tim8: Tim8::steal(), + tim9: Tim9::steal(), + tim10: Tim10::steal(), + tim11: Tim11::steal(), + tim12: Tim12::steal(), + tim13: Tim13::steal(), + tim14: Tim14::steal(), + tim15: Tim15::steal(), + tim16: Tim16::steal(), + tim17: Tim17::steal(), + tim18: Tim18::steal(), + tim19: Tim19::steal(), + tim20: Tim20::steal(), + tim21: Tim21::steal(), + tim22: Tim22::steal(), + tim23: Tim23::steal(), + uarta: Uarta::steal(), + uartb: Uartb::steal(), + spia: Spia::steal(), + spib: Spib::steal(), + spic: Spic::steal(), + i2ca: I2ca::steal(), + i2cb: I2cb::steal(), + } + } +} diff --git a/va108xx/va108xx/src/porta.rs b/va108xx/va108xx/src/porta.rs new file mode 100644 index 0000000..e7e8f40 --- /dev/null +++ b/va108xx/va108xx/src/porta.rs @@ -0,0 +1,424 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved_0_datain: [u8; 0x04], + _reserved_1_datainraw: [u8; 0x04], + _reserved_2_dataout: [u8; 0x04], + _reserved_3_dataoutraw: [u8; 0x04], + _reserved_4_setout: [u8; 0x04], + _reserved_5_clrout: [u8; 0x04], + _reserved_6_togout: [u8; 0x04], + _reserved_7_datamask: [u8; 0x04], + _reserved_8_dir: [u8; 0x04], + _reserved_9_pulse: [u8; 0x04], + _reserved_10_pulsebase: [u8; 0x04], + _reserved_11_delay: [u8; 0x04], + _reserved_12_delay: [u8; 0x04], + irq_sen: IrqSen, + irq_edge: IrqEdge, + irq_evt: IrqEvt, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + edge_status: EdgeStatus, + _reserved20: [u8; 0x0fac], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Data In Register by Byte"] + #[inline(always)] + pub const fn datainbyte(&self, n: usize) -> &Datainbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x00 - Data In Register by Byte"] + #[inline(always)] + pub fn datainbyte_iter(&self) -> impl Iterator { + (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(n).cast() }) + } + #[doc = "0x00 - Data In Register"] + #[inline(always)] + pub const fn datain(&self) -> &Datain { + unsafe { &*core::ptr::from_ref(self).cast::().cast() } + } + #[doc = "0x04 - Data In Raw Register by Byte"] + #[inline(always)] + pub const fn datainrawbyte(&self, n: usize) -> &Datainrawbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(4).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x04 - Data In Raw Register by Byte"] + #[inline(always)] + pub fn datainrawbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(4).add(n).cast() }) + } + #[doc = "0x04 - Data In Raw Register"] + #[inline(always)] + pub const fn datainraw(&self) -> &Datainraw { + unsafe { &*core::ptr::from_ref(self).cast::().add(4).cast() } + } + #[doc = "0x08 - Data Out Register by Byte"] + #[inline(always)] + pub const fn dataoutbyte(&self, n: usize) -> &Dataoutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(8).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x08 - Data Out Register by Byte"] + #[inline(always)] + pub fn dataoutbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(8).add(n).cast() }) + } + #[doc = "0x08 - Data Out Register"] + #[inline(always)] + pub const fn dataout(&self) -> &Dataout { + unsafe { &*core::ptr::from_ref(self).cast::().add(8).cast() } + } + #[doc = "0x0c - Data Out Register by Byte"] + #[inline(always)] + pub const fn dataoutrawbyte(&self, n: usize) -> &Dataoutrawbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(12).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x0c - Data Out Register by Byte"] + #[inline(always)] + pub fn dataoutrawbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(12).add(n).cast() }) + } + #[doc = "0x0c - Data Out Register"] + #[inline(always)] + pub const fn dataoutraw(&self) -> &Dataoutraw { + unsafe { &*core::ptr::from_ref(self).cast::().add(12).cast() } + } + #[doc = "0x10 - Set Out Register by Byte"] + #[inline(always)] + pub const fn setoutbyte(&self, n: usize) -> &Setoutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(16).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x10 - Set Out Register by Byte"] + #[inline(always)] + pub fn setoutbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(16).add(n).cast() }) + } + #[doc = "0x10 - Set Out Register"] + #[inline(always)] + pub const fn setout(&self) -> &Setout { + unsafe { &*core::ptr::from_ref(self).cast::().add(16).cast() } + } + #[doc = "0x14 - Clear Out Register by Byte"] + #[inline(always)] + pub const fn clroutbyte(&self, n: usize) -> &Clroutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(20).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x14 - Clear Out Register by Byte"] + #[inline(always)] + pub fn clroutbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(20).add(n).cast() }) + } + #[doc = "0x14 - Clear Out Register"] + #[inline(always)] + pub const fn clrout(&self) -> &Clrout { + unsafe { &*core::ptr::from_ref(self).cast::().add(20).cast() } + } + #[doc = "0x18 - Toggle Out Register by Byte"] + #[inline(always)] + pub const fn togoutbyte(&self, n: usize) -> &Togoutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(24).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x18 - Toggle Out Register by Byte"] + #[inline(always)] + pub fn togoutbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(24).add(n).cast() }) + } + #[doc = "0x18 - Toggle Out Register"] + #[inline(always)] + pub const fn togout(&self) -> &Togout { + unsafe { &*core::ptr::from_ref(self).cast::().add(24).cast() } + } + #[doc = "0x1c - Data Out Register by Byte"] + #[inline(always)] + pub const fn datamaskbyte(&self, n: usize) -> &Datamaskbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(28).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1c - Data Out Register by Byte"] + #[inline(always)] + pub fn datamaskbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(28).add(n).cast() }) + } + #[doc = "0x1c - Data mask Register"] + #[inline(always)] + pub const fn datamask(&self) -> &Datamask { + unsafe { &*core::ptr::from_ref(self).cast::().add(28).cast() } + } + #[doc = "0x20 - Direction Register by Byte"] + #[inline(always)] + pub const fn dirbyte(&self, n: usize) -> &Dirbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(32).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x20 - Direction Register by Byte"] + #[inline(always)] + pub fn dirbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(32).add(n).cast() }) + } + #[doc = "0x20 - Direction Register (1:Output, 0:Input)"] + #[inline(always)] + pub const fn dir(&self) -> &Dir { + unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } + } + #[doc = "0x24 - Pulse Mode Register by Byte"] + #[inline(always)] + pub const fn pulsebyte(&self, n: usize) -> &Pulsebyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(36).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x24 - Pulse Mode Register by Byte"] + #[inline(always)] + pub fn pulsebyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(36).add(n).cast() }) + } + #[doc = "0x24 - Pulse Mode Register"] + #[inline(always)] + pub const fn pulse(&self) -> &Pulse { + unsafe { &*core::ptr::from_ref(self).cast::().add(36).cast() } + } + #[doc = "0x28 - Pulse Base Mode Register by Byte"] + #[inline(always)] + pub const fn pulsebasebyte(&self, n: usize) -> &Pulsebasebyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(40).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x28 - Pulse Base Mode Register by Byte"] + #[inline(always)] + pub fn pulsebasebyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(40).add(n).cast() }) + } + #[doc = "0x28 - Pulse Base Value Register"] + #[inline(always)] + pub const fn pulsebase(&self) -> &Pulsebase { + unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } + } + #[doc = "0x2c - Delay1 Register by Byte"] + #[inline(always)] + pub const fn delay1byte(&self, n: usize) -> &Delay1byte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(44).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c - Delay1 Register by Byte"] + #[inline(always)] + pub fn delay1byte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(44).add(n).cast() }) + } + #[doc = "0x2c - Delay1 Register"] + #[inline(always)] + pub const fn delay1(&self) -> &Delay1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } + } + #[doc = "0x30 - Delay2 Register by Byte"] + #[inline(always)] + pub const fn delay2byte(&self, n: usize) -> &Delay2byte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(48).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x30 - Delay2 Register by Byte"] + #[inline(always)] + pub fn delay2byte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(48).add(n).cast() }) + } + #[doc = "0x30 - Delay2 Register"] + #[inline(always)] + pub const fn delay2(&self) -> &Delay2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } + } + #[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] + #[inline(always)] + pub const fn irq_sen(&self) -> &IrqSen { + &self.irq_sen + } + #[doc = "0x38 - Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] + #[inline(always)] + pub const fn irq_edge(&self) -> &IrqEdge { + &self.irq_edge + } + #[doc = "0x3c - Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] + #[inline(always)] + pub const fn irq_evt(&self) -> &IrqEvt { + &self.irq_evt + } + #[doc = "0x40 - Interrupt Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x44 - Raw Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x48 - Masked Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x4c - Edge Status Register"] + #[inline(always)] + pub const fn edge_status(&self) -> &EdgeStatus { + &self.edge_status + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`] module"] +#[doc(alias = "DATAIN")] +pub type Datain = crate::Reg; +#[doc = "Data In Register"] +pub mod datain; +#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`] module"] +#[doc(alias = "DATAINBYTE")] +pub type Datainbyte = crate::Reg; +#[doc = "Data In Register by Byte"] +pub mod datainbyte; +pub use datain as datainraw; +pub use datainbyte as datainrawbyte; +pub use Datain as Datainraw; +pub use Datainbyte as Datainrawbyte; +#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`] module"] +#[doc(alias = "DATAOUT")] +pub type Dataout = crate::Reg; +#[doc = "Data Out Register"] +pub mod dataout; +#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`] module"] +#[doc(alias = "DATAOUTBYTE")] +pub type Dataoutbyte = crate::Reg; +#[doc = "Data Out Register by Byte"] +pub mod dataoutbyte; +pub use dataout as dataoutraw; +pub use dataout as setout; +pub use dataout as clrout; +pub use dataout as togout; +pub use dataoutbyte as dataoutrawbyte; +pub use dataoutbyte as setoutbyte; +pub use dataoutbyte as clroutbyte; +pub use dataoutbyte as togoutbyte; +pub use Dataout as Dataoutraw; +pub use Dataout as Setout; +pub use Dataout as Clrout; +pub use Dataout as Togout; +pub use Dataoutbyte as Dataoutrawbyte; +pub use Dataoutbyte as Setoutbyte; +pub use Dataoutbyte as Clroutbyte; +pub use Dataoutbyte as Togoutbyte; +#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`] module"] +#[doc(alias = "DATAMASK")] +pub type Datamask = crate::Reg; +#[doc = "Data mask Register"] +pub mod datamask; +#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`] module"] +#[doc(alias = "DATAMASKBYTE")] +pub type Datamaskbyte = crate::Reg; +#[doc = "Data Out Register by Byte"] +pub mod datamaskbyte; +pub use datamask as dir; +pub use datamask as pulse; +pub use datamask as pulsebase; +pub use datamask as delay1; +pub use datamask as delay2; +pub use datamaskbyte as dirbyte; +pub use datamaskbyte as pulsebyte; +pub use datamaskbyte as pulsebasebyte; +pub use datamaskbyte as delay1byte; +pub use datamaskbyte as delay2byte; +pub use Datamask as Dir; +pub use Datamask as Pulse; +pub use Datamask as Pulsebase; +pub use Datamask as Delay1; +pub use Datamask as Delay2; +pub use Datamaskbyte as Dirbyte; +pub use Datamaskbyte as Pulsebyte; +pub use Datamaskbyte as Pulsebasebyte; +pub use Datamaskbyte as Delay1byte; +pub use Datamaskbyte as Delay2byte; +#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`] module"] +#[doc(alias = "IRQ_SEN")] +pub type IrqSen = crate::Reg; +#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] +pub mod irq_sen; +#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`] module"] +#[doc(alias = "IRQ_EDGE")] +pub type IrqEdge = crate::Reg; +#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] +pub mod irq_edge; +#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`] module"] +#[doc(alias = "IRQ_EVT")] +pub type IrqEvt = crate::Reg; +#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] +pub mod irq_evt; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] module"] +#[doc(alias = "IRQ_RAW")] +pub type IrqRaw = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] module"] +#[doc(alias = "IRQ_END")] +pub type IrqEnd = crate::Reg; +#[doc = "Masked Interrupt Status"] +pub mod irq_end; +#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`] module"] +#[doc(alias = "EDGE_STATUS")] +pub type EdgeStatus = crate::Reg; +#[doc = "Edge Status Register"] +pub mod edge_status; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va108xx/va108xx/src/porta/datain.rs b/va108xx/va108xx/src/porta/datain.rs new file mode 100644 index 0000000..713b210 --- /dev/null +++ b/va108xx/va108xx/src/porta/datain.rs @@ -0,0 +1,17 @@ +#[doc = "Register `DATAIN` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatainSpec; +impl crate::RegisterSpec for DatainSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`datain::R`](R) reader structure"] +impl crate::Readable for DatainSpec {} +#[doc = "`reset()` method sets DATAIN to value 0"] +impl crate::Resettable for DatainSpec {} diff --git a/va108xx/va108xx/src/porta/datainbyte.rs b/va108xx/va108xx/src/porta/datainbyte.rs new file mode 100644 index 0000000..2b15efa --- /dev/null +++ b/va108xx/va108xx/src/porta/datainbyte.rs @@ -0,0 +1,17 @@ +#[doc = "Register `DATAINBYTE[%s]` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatainbyteSpec; +impl crate::RegisterSpec for DatainbyteSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`datainbyte::R`](R) reader structure"] +impl crate::Readable for DatainbyteSpec {} +#[doc = "`reset()` method sets DATAINBYTE[%s] to value 0"] +impl crate::Resettable for DatainbyteSpec {} diff --git a/va108xx/va108xx/src/porta/datamask.rs b/va108xx/va108xx/src/porta/datamask.rs new file mode 100644 index 0000000..e9f72a7 --- /dev/null +++ b/va108xx/va108xx/src/porta/datamask.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATAMASK` reader"] +pub type R = crate::R; +#[doc = "Register `DATAMASK` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatamaskSpec; +impl crate::RegisterSpec for DatamaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`datamask::R`](R) reader structure"] +impl crate::Readable for DatamaskSpec {} +#[doc = "`write(|w| ..)` method takes [`datamask::W`](W) writer structure"] +impl crate::Writable for DatamaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATAMASK to value 0"] +impl crate::Resettable for DatamaskSpec {} diff --git a/va108xx/va108xx/src/porta/datamaskbyte.rs b/va108xx/va108xx/src/porta/datamaskbyte.rs new file mode 100644 index 0000000..e7a812a --- /dev/null +++ b/va108xx/va108xx/src/porta/datamaskbyte.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATAMASKBYTE[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `DATAMASKBYTE[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatamaskbyteSpec; +impl crate::RegisterSpec for DatamaskbyteSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`datamaskbyte::R`](R) reader structure"] +impl crate::Readable for DatamaskbyteSpec {} +#[doc = "`write(|w| ..)` method takes [`datamaskbyte::W`](W) writer structure"] +impl crate::Writable for DatamaskbyteSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATAMASKBYTE[%s] to value 0"] +impl crate::Resettable for DatamaskbyteSpec {} diff --git a/va108xx/va108xx/src/porta/dataout.rs b/va108xx/va108xx/src/porta/dataout.rs new file mode 100644 index 0000000..59207cb --- /dev/null +++ b/va108xx/va108xx/src/porta/dataout.rs @@ -0,0 +1,20 @@ +#[doc = "Register `DATAOUT` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W {} +#[doc = "Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataoutSpec; +impl crate::RegisterSpec for DataoutSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`dataout::W`](W) writer structure"] +impl crate::Writable for DataoutSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATAOUT to value 0"] +impl crate::Resettable for DataoutSpec {} diff --git a/va108xx/va108xx/src/porta/dataoutbyte.rs b/va108xx/va108xx/src/porta/dataoutbyte.rs new file mode 100644 index 0000000..3261f34 --- /dev/null +++ b/va108xx/va108xx/src/porta/dataoutbyte.rs @@ -0,0 +1,20 @@ +#[doc = "Register `DATAOUTBYTE[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W {} +#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataoutbyteSpec; +impl crate::RegisterSpec for DataoutbyteSpec { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [`dataoutbyte::W`](W) writer structure"] +impl crate::Writable for DataoutbyteSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATAOUTBYTE[%s] to value 0"] +impl crate::Resettable for DataoutbyteSpec {} diff --git a/va108xx/va108xx/src/porta/edge_status.rs b/va108xx/va108xx/src/porta/edge_status.rs new file mode 100644 index 0000000..da93837 --- /dev/null +++ b/va108xx/va108xx/src/porta/edge_status.rs @@ -0,0 +1,24 @@ +#[doc = "Register `EDGE_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `EDGE_STATUS` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EdgeStatusSpec; +impl crate::RegisterSpec for EdgeStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`edge_status::R`](R) reader structure"] +impl crate::Readable for EdgeStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`edge_status::W`](W) writer structure"] +impl crate::Writable for EdgeStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EDGE_STATUS to value 0"] +impl crate::Resettable for EdgeStatusSpec {} diff --git a/va108xx/va108xx/src/porta/irq_edge.rs b/va108xx/va108xx/src/porta/irq_edge.rs new file mode 100644 index 0000000..130ee47 --- /dev/null +++ b/va108xx/va108xx/src/porta/irq_edge.rs @@ -0,0 +1,24 @@ +#[doc = "Register `IRQ_EDGE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_EDGE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEdgeSpec; +impl crate::RegisterSpec for IrqEdgeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_edge::R`](R) reader structure"] +impl crate::Readable for IrqEdgeSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_edge::W`](W) writer structure"] +impl crate::Writable for IrqEdgeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_EDGE to value 0"] +impl crate::Resettable for IrqEdgeSpec {} diff --git a/va108xx/va108xx/src/porta/irq_enb.rs b/va108xx/va108xx/src/porta/irq_enb.rs new file mode 100644 index 0000000..64d6f21 --- /dev/null +++ b/va108xx/va108xx/src/porta/irq_enb.rs @@ -0,0 +1,24 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va108xx/va108xx/src/porta/irq_end.rs b/va108xx/va108xx/src/porta/irq_end.rs new file mode 100644 index 0000000..f051d70 --- /dev/null +++ b/va108xx/va108xx/src/porta/irq_end.rs @@ -0,0 +1,17 @@ +#[doc = "Register `IRQ_END` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEndSpec; +impl crate::RegisterSpec for IrqEndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"] +impl crate::Readable for IrqEndSpec {} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IrqEndSpec {} diff --git a/va108xx/va108xx/src/porta/irq_evt.rs b/va108xx/va108xx/src/porta/irq_evt.rs new file mode 100644 index 0000000..075b780 --- /dev/null +++ b/va108xx/va108xx/src/porta/irq_evt.rs @@ -0,0 +1,24 @@ +#[doc = "Register `IRQ_EVT` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_EVT` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEvtSpec; +impl crate::RegisterSpec for IrqEvtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_evt::R`](R) reader structure"] +impl crate::Readable for IrqEvtSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_evt::W`](W) writer structure"] +impl crate::Writable for IrqEvtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_EVT to value 0"] +impl crate::Resettable for IrqEvtSpec {} diff --git a/va108xx/va108xx/src/porta/irq_raw.rs b/va108xx/va108xx/src/porta/irq_raw.rs new file mode 100644 index 0000000..5278bfb --- /dev/null +++ b/va108xx/va108xx/src/porta/irq_raw.rs @@ -0,0 +1,17 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqRawSpec; +impl crate::RegisterSpec for IrqRawSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"] +impl crate::Readable for IrqRawSpec {} +#[doc = "`reset()` method sets IRQ_RAW to value 0"] +impl crate::Resettable for IrqRawSpec {} diff --git a/va108xx/va108xx/src/porta/irq_sen.rs b/va108xx/va108xx/src/porta/irq_sen.rs new file mode 100644 index 0000000..0f75eb6 --- /dev/null +++ b/va108xx/va108xx/src/porta/irq_sen.rs @@ -0,0 +1,24 @@ +#[doc = "Register `IRQ_SEN` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_SEN` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqSenSpec; +impl crate::RegisterSpec for IrqSenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_sen::R`](R) reader structure"] +impl crate::Readable for IrqSenSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_sen::W`](W) writer structure"] +impl crate::Writable for IrqSenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_SEN to value 0"] +impl crate::Resettable for IrqSenSpec {} diff --git a/va108xx/va108xx/src/porta/perid.rs b/va108xx/va108xx/src/porta/perid.rs new file mode 100644 index 0000000..fbacdc8 --- /dev/null +++ b/va108xx/va108xx/src/porta/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0010_07e1"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0010_07e1; +} diff --git a/va108xx/va108xx/src/spia.rs b/va108xx/va108xx/src/spia.rs new file mode 100644 index 0000000..52836ac --- /dev/null +++ b/va108xx/va108xx/src/spia.rs @@ -0,0 +1,152 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl0: Ctrl0, + ctrl1: Ctrl1, + data: Data, + status: Status, + clkprescale: Clkprescale, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + txfifoirqtrg: Txfifoirqtrg, + fifo_clr: FifoClr, + state: State, + _reserved13: [u8; 0x0fc8], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register 0"] + #[inline(always)] + pub const fn ctrl0(&self) -> &Ctrl0 { + &self.ctrl0 + } + #[doc = "0x04 - Control Register 1"] + #[inline(always)] + pub const fn ctrl1(&self) -> &Ctrl1 { + &self.ctrl1 + } + #[doc = "0x08 - Data Input/Output"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x0c - Status Register"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x10 - Clock Pre Scale divide value"] + #[inline(always)] + pub const fn clkprescale(&self) -> &Clkprescale { + &self.clkprescale + } + #[doc = "0x14 - Interrupt Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x18 - Raw Interrupt Status Register"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x1c - Enabled Interrupt Status Register"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x20 - Clear Interrupt Status Register"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x24 - Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x28 - Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x2c - Clear FIFO Register"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x30 - Internal STATE of SPI Controller"] + #[inline(always)] + pub const fn state(&self) -> &State { + &self.state + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] module"] +#[doc(alias = "CTRL0")] +pub type Ctrl0 = crate::Reg; +#[doc = "Control Register 0"] +pub mod ctrl0; +#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"] +#[doc(alias = "CTRL1")] +pub type Ctrl1 = crate::Reg; +#[doc = "Control Register 1"] +pub mod ctrl1; +#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data Input/Output"] +pub mod data; +#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`] module"] +#[doc(alias = "CLKPRESCALE")] +pub type Clkprescale = crate::Reg; +#[doc = "Clock Pre Scale divide value"] +pub mod clkprescale; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +#[doc(alias = "STATE")] +pub type State = crate::Reg; +#[doc = "Internal STATE of SPI Controller"] +pub mod state; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va108xx/va108xx/src/spia/clkprescale.rs b/va108xx/va108xx/src/spia/clkprescale.rs new file mode 100644 index 0000000..f202eb8 --- /dev/null +++ b/va108xx/va108xx/src/spia/clkprescale.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKPRESCALE` reader"] +pub type R = crate::R; +#[doc = "Register `CLKPRESCALE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkprescaleSpec; +impl crate::RegisterSpec for ClkprescaleSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkprescale::R`](R) reader structure"] +impl crate::Readable for ClkprescaleSpec {} +#[doc = "`write(|w| ..)` method takes [`clkprescale::W`](W) writer structure"] +impl crate::Writable for ClkprescaleSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKPRESCALE to value 0"] +impl crate::Resettable for ClkprescaleSpec {} diff --git a/va108xx/va108xx/src/spia/ctrl0.rs b/va108xx/va108xx/src/spia/ctrl0.rs new file mode 100644 index 0000000..29abe30 --- /dev/null +++ b/va108xx/va108xx/src/spia/ctrl0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `SIZE` reader - Data Size(0x3=>4, 0xf=>16)"] +pub type SizeR = crate::FieldReader; +#[doc = "Field `SIZE` writer - Data Size(0x3=>4, 0xf=>16)"] +pub type SizeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SPO` reader - SPI Clock Polarity"] +pub type SpoR = crate::BitReader; +#[doc = "Field `SPO` writer - SPI Clock Polarity"] +pub type SpoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPH` reader - SPI Clock Phase"] +pub type SphR = crate::BitReader; +#[doc = "Field `SPH` writer - SPI Clock Phase"] +pub type SphW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCRDV` reader - Serial Clock Rate divide+1 value"] +pub type ScrdvR = crate::FieldReader; +#[doc = "Field `SCRDV` writer - Serial Clock Rate divide+1 value"] +pub type ScrdvW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] + #[inline(always)] + pub fn size(&self) -> SizeR { + SizeR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - SPI Clock Polarity"] + #[inline(always)] + pub fn spo(&self) -> SpoR { + SpoR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - SPI Clock Phase"] + #[inline(always)] + pub fn sph(&self) -> SphR { + SphR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] + #[inline(always)] + pub fn scrdv(&self) -> ScrdvR { + ScrdvR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] + #[inline(always)] + pub fn size(&mut self) -> SizeW<'_, Ctrl0Spec> { + SizeW::new(self, 0) + } + #[doc = "Bit 6 - SPI Clock Polarity"] + #[inline(always)] + pub fn spo(&mut self) -> SpoW<'_, Ctrl0Spec> { + SpoW::new(self, 6) + } + #[doc = "Bit 7 - SPI Clock Phase"] + #[inline(always)] + pub fn sph(&mut self) -> SphW<'_, Ctrl0Spec> { + SphW::new(self, 7) + } + #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] + #[inline(always)] + pub fn scrdv(&mut self) -> ScrdvW<'_, Ctrl0Spec> { + ScrdvW::new(self, 8) + } +} +#[doc = "Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl0Spec; +impl crate::RegisterSpec for Ctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"] +impl crate::Readable for Ctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"] +impl crate::Writable for Ctrl0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL0 to value 0"] +impl crate::Resettable for Ctrl0Spec {} diff --git a/va108xx/va108xx/src/spia/ctrl1.rs b/va108xx/va108xx/src/spia/ctrl1.rs new file mode 100644 index 0000000..2c756fa --- /dev/null +++ b/va108xx/va108xx/src/spia/ctrl1.rs @@ -0,0 +1,161 @@ +#[doc = "Register `CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `LBM` reader - Loop Back"] +pub type LbmR = crate::BitReader; +#[doc = "Field `LBM` writer - Loop Back"] +pub type LbmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MS` reader - Master/Slave (0:Master, 1:Slave)"] +pub type MsR = crate::BitReader; +#[doc = "Field `MS` writer - Master/Slave (0:Master, 1:Slave)"] +pub type MsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOD` reader - Slave output Disable"] +pub type SodR = crate::BitReader; +#[doc = "Field `SOD` writer - Slave output Disable"] +pub type SodW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SS` reader - Slave Select"] +pub type SsR = crate::FieldReader; +#[doc = "Field `SS` writer - Slave Select"] +pub type SsW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `BLOCKMODE` reader - Block Mode Enable"] +pub type BlockmodeR = crate::BitReader; +#[doc = "Field `BLOCKMODE` writer - Block Mode Enable"] +pub type BlockmodeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BMSTART` reader - Block Mode Start Status Enable"] +pub type BmstartR = crate::BitReader; +#[doc = "Field `BMSTART` writer - Block Mode Start Status Enable"] +pub type BmstartW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BMSTALL` reader - Block Mode Stall Enable"] +pub type BmstallR = crate::BitReader; +#[doc = "Field `BMSTALL` writer - Block Mode Stall Enable"] +pub type BmstallW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MDLYCAP` reader - Master Delayed Capture Enable"] +pub type MdlycapR = crate::BitReader; +#[doc = "Field `MDLYCAP` writer - Master Delayed Capture Enable"] +pub type MdlycapW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MTXPAUSE` reader - Master Tx Pause Enable"] +pub type MtxpauseR = crate::BitReader; +#[doc = "Field `MTXPAUSE` writer - Master Tx Pause Enable"] +pub type MtxpauseW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Loop Back"] + #[inline(always)] + pub fn lbm(&self) -> LbmR { + LbmR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] + #[inline(always)] + pub fn ms(&self) -> MsR { + MsR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave output Disable"] + #[inline(always)] + pub fn sod(&self) -> SodR { + SodR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Slave Select"] + #[inline(always)] + pub fn ss(&self) -> SsR { + SsR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Block Mode Enable"] + #[inline(always)] + pub fn blockmode(&self) -> BlockmodeR { + BlockmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Block Mode Start Status Enable"] + #[inline(always)] + pub fn bmstart(&self) -> BmstartR { + BmstartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Block Mode Stall Enable"] + #[inline(always)] + pub fn bmstall(&self) -> BmstallR { + BmstallR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Master Delayed Capture Enable"] + #[inline(always)] + pub fn mdlycap(&self) -> MdlycapR { + MdlycapR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Master Tx Pause Enable"] + #[inline(always)] + pub fn mtxpause(&self) -> MtxpauseR { + MtxpauseR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop Back"] + #[inline(always)] + pub fn lbm(&mut self) -> LbmW<'_, Ctrl1Spec> { + LbmW::new(self, 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, Ctrl1Spec> { + EnableW::new(self, 1) + } + #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] + #[inline(always)] + pub fn ms(&mut self) -> MsW<'_, Ctrl1Spec> { + MsW::new(self, 2) + } + #[doc = "Bit 3 - Slave output Disable"] + #[inline(always)] + pub fn sod(&mut self) -> SodW<'_, Ctrl1Spec> { + SodW::new(self, 3) + } + #[doc = "Bits 4:6 - Slave Select"] + #[inline(always)] + pub fn ss(&mut self) -> SsW<'_, Ctrl1Spec> { + SsW::new(self, 4) + } + #[doc = "Bit 7 - Block Mode Enable"] + #[inline(always)] + pub fn blockmode(&mut self) -> BlockmodeW<'_, Ctrl1Spec> { + BlockmodeW::new(self, 7) + } + #[doc = "Bit 8 - Block Mode Start Status Enable"] + #[inline(always)] + pub fn bmstart(&mut self) -> BmstartW<'_, Ctrl1Spec> { + BmstartW::new(self, 8) + } + #[doc = "Bit 9 - Block Mode Stall Enable"] + #[inline(always)] + pub fn bmstall(&mut self) -> BmstallW<'_, Ctrl1Spec> { + BmstallW::new(self, 9) + } + #[doc = "Bit 10 - Master Delayed Capture Enable"] + #[inline(always)] + pub fn mdlycap(&mut self) -> MdlycapW<'_, Ctrl1Spec> { + MdlycapW::new(self, 10) + } + #[doc = "Bit 11 - Master Tx Pause Enable"] + #[inline(always)] + pub fn mtxpause(&mut self) -> MtxpauseW<'_, Ctrl1Spec> { + MtxpauseW::new(self, 11) + } +} +#[doc = "Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1Spec; +impl crate::RegisterSpec for Ctrl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"] +impl crate::Readable for Ctrl1Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] +impl crate::Writable for Ctrl1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for Ctrl1Spec {} diff --git a/va108xx/va108xx/src/spia/data.rs b/va108xx/va108xx/src/spia/data.rs new file mode 100644 index 0000000..8968f26 --- /dev/null +++ b/va108xx/va108xx/src/spia/data.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec {} diff --git a/va108xx/va108xx/src/spia/fifo_clr.rs b/va108xx/va108xx/src/spia/fifo_clr.rs new file mode 100644 index 0000000..339ac41 --- /dev/null +++ b/va108xx/va108xx/src/spia/fifo_clr.rs @@ -0,0 +1,29 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> { + TxfifoW::new(self, 1) + } +} +#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec {} diff --git a/va108xx/va108xx/src/spia/irq_enb.rs b/va108xx/va108xx/src/spia/irq_enb.rs new file mode 100644 index 0000000..325da2d --- /dev/null +++ b/va108xx/va108xx/src/spia/irq_enb.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `RORIM` reader - RX Overrun"] +pub type RorimR = crate::BitReader; +#[doc = "Field `RORIM` writer - RX Overrun"] +pub type RorimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTIM` reader - RX Timeout"] +pub type RtimR = crate::BitReader; +#[doc = "Field `RTIM` writer - RX Timeout"] +pub type RtimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXIM` reader - RX Fifo is at least half full"] +pub type RximR = crate::BitReader; +#[doc = "Field `RXIM` writer - RX Fifo is at least half full"] +pub type RximW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"] +pub type TximR = crate::BitReader; +#[doc = "Field `TXIM` writer - TX Fifo is at least half empty"] +pub type TximW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&self) -> RorimR { + RorimR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&self) -> RtimR { + RtimR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&self) -> RximR { + RximR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&self) -> TximR { + TximR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&mut self) -> RorimW<'_, IrqEnbSpec> { + RorimW::new(self, 0) + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&mut self) -> RtimW<'_, IrqEnbSpec> { + RtimW::new(self, 1) + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&mut self) -> RximW<'_, IrqEnbSpec> { + RximW::new(self, 2) + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&mut self) -> TximW<'_, IrqEnbSpec> { + TximW::new(self, 3) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va108xx/va108xx/src/spia/perid.rs b/va108xx/va108xx/src/spia/perid.rs new file mode 100644 index 0000000..68e90c4 --- /dev/null +++ b/va108xx/va108xx/src/spia/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0012_07e1"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0012_07e1; +} diff --git a/va108xx/va108xx/src/spia/rxfifoirqtrg.rs b/va108xx/va108xx/src/spia/rxfifoirqtrg.rs new file mode 100644 index 0000000..e38d450 --- /dev/null +++ b/va108xx/va108xx/src/spia/rxfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RxfifoirqtrgSpec {} diff --git a/va108xx/va108xx/src/spia/state.rs b/va108xx/va108xx/src/spia/state.rs new file mode 100644 index 0000000..3a494cd --- /dev/null +++ b/va108xx/va108xx/src/spia/state.rs @@ -0,0 +1,17 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StateSpec; +impl crate::RegisterSpec for StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for StateSpec {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for StateSpec {} diff --git a/va108xx/va108xx/src/spia/status.rs b/va108xx/va108xx/src/spia/status.rs new file mode 100644 index 0000000..0000307 --- /dev/null +++ b/va108xx/va108xx/src/spia/status.rs @@ -0,0 +1,69 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TFE` reader - Transmit FIFO empty"] +pub type TfeR = crate::BitReader; +#[doc = "Field `TNF` reader - Transmit FIFO not full"] +pub type TnfR = crate::BitReader; +#[doc = "Field `RNE` reader - Receive FIFO not empty"] +pub type RneR = crate::BitReader; +#[doc = "Field `RFF` reader - Receive FIFO Full"] +pub type RffR = crate::BitReader; +#[doc = "Field `BUSY` reader - Busy"] +pub type BusyR = crate::BitReader; +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte in BLOCKMODE"] +pub type RxdatafirstR = crate::BitReader; +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub type RxtriggerR = crate::BitReader; +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub type TxtriggerR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty"] + #[inline(always)] + pub fn tfe(&self) -> TfeR { + TfeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full"] + #[inline(always)] + pub fn tnf(&self) -> TnfR { + TnfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty"] + #[inline(always)] + pub fn rne(&self) -> RneR { + RneR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO Full"] + #[inline(always)] + pub fn rff(&self) -> RffR { + RffR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BusyR { + BusyR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pending Data is first Byte in BLOCKMODE"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RxdatafirstR { + RxdatafirstR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RxtriggerR { + RxtriggerR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TxtriggerR { + TxtriggerR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec {} diff --git a/va108xx/va108xx/src/spia/txfifoirqtrg.rs b/va108xx/va108xx/src/spia/txfifoirqtrg.rs new file mode 100644 index 0000000..ea0e7d3 --- /dev/null +++ b/va108xx/va108xx/src/spia/txfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TxfifoirqtrgSpec {} diff --git a/va108xx/va108xx/src/sysconfig.rs b/va108xx/va108xx/src/sysconfig.rs new file mode 100644 index 0000000..5802fa3 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig.rs @@ -0,0 +1,358 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + rst_stat: RstStat, + rst_cntl_rom: RstCntlRom, + rst_cntl_ram: RstCntlRam, + rom_prot: RomProt, + rom_scrub: RomScrub, + ram_scrub: RamScrub, + rom_trap_addr: RomTrapAddr, + rom_trap_synd: RomTrapSynd, + ram_trap_addr: RamTrapAddr, + ram_trap_synd: RamTrapSynd, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + ram_sbe: RamSbe, + ram_mbe: RamMbe, + rom_sbe: RomSbe, + rom_mbe: RomMbe, + ioconfig_clkdiv0: IoconfigClkdiv0, + ioconfig_clkdiv: [IoconfigClkdiv; 7], + rom_retries: RomRetries, + refresh_config: RefreshConfig, + tim_reset: TimReset, + tim_clk_enable: TimClkEnable, + peripheral_reset: PeripheralReset, + peripheral_clk_enable: PeripheralClkEnable, + lockup_reset: LockupReset, + _reserved27: [u8; 0x0f6c], + ef_config: EfConfig, + ef_id: EfId, + procid: Procid, + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - System Reset Status"] + #[inline(always)] + pub const fn rst_stat(&self) -> &RstStat { + &self.rst_stat + } + #[doc = "0x04 - ROM Reset Control"] + #[inline(always)] + pub const fn rst_cntl_rom(&self) -> &RstCntlRom { + &self.rst_cntl_rom + } + #[doc = "0x08 - RAM Reset Control"] + #[inline(always)] + pub const fn rst_cntl_ram(&self) -> &RstCntlRam { + &self.rst_cntl_ram + } + #[doc = "0x0c - ROM Protection Configuration"] + #[inline(always)] + pub const fn rom_prot(&self) -> &RomProt { + &self.rom_prot + } + #[doc = "0x10 - ROM Scrub Period Configuration"] + #[inline(always)] + pub const fn rom_scrub(&self) -> &RomScrub { + &self.rom_scrub + } + #[doc = "0x14 - RAM Scrub Period Configuration"] + #[inline(always)] + pub const fn ram_scrub(&self) -> &RamScrub { + &self.ram_scrub + } + #[doc = "0x18 - ROM Trap Address"] + #[inline(always)] + pub const fn rom_trap_addr(&self) -> &RomTrapAddr { + &self.rom_trap_addr + } + #[doc = "0x1c - ROM Trap Syndrome"] + #[inline(always)] + pub const fn rom_trap_synd(&self) -> &RomTrapSynd { + &self.rom_trap_synd + } + #[doc = "0x20 - RAM Trap Address"] + #[inline(always)] + pub const fn ram_trap_addr(&self) -> &RamTrapAddr { + &self.ram_trap_addr + } + #[doc = "0x24 - RAM Trap Syndrome"] + #[inline(always)] + pub const fn ram_trap_synd(&self) -> &RamTrapSynd { + &self.ram_trap_synd + } + #[doc = "0x28 - Enable EDAC Error Interrupt Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x2c - Raw EDAC Error Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x30 - Enabled EDAC Error Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x34 - Clear EDAC Error Interrupt Status"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x38 - Count of RAM EDAC Single Bit Errors"] + #[inline(always)] + pub const fn ram_sbe(&self) -> &RamSbe { + &self.ram_sbe + } + #[doc = "0x3c - Count of RAM EDAC Multi Bit Errors"] + #[inline(always)] + pub const fn ram_mbe(&self) -> &RamMbe { + &self.ram_mbe + } + #[doc = "0x40 - Count of ROM EDAC Single Bit Errors"] + #[inline(always)] + pub const fn rom_sbe(&self) -> &RomSbe { + &self.rom_sbe + } + #[doc = "0x44 - Count of ROM EDAC Multi Bit Errors"] + #[inline(always)] + pub const fn rom_mbe(&self) -> &RomMbe { + &self.rom_mbe + } + #[doc = "0x48 - IO Configuration Clock Divider Register"] + #[inline(always)] + pub const fn ioconfig_clkdiv0(&self) -> &IoconfigClkdiv0 { + &self.ioconfig_clkdiv0 + } + #[doc = "0x4c..0x68 - IO Configuration Clock Divider Register"] + #[doc = ""] + #[doc = "
`n` is the index of register in the array. `n == 0` corresponds to `IOCONFIG_CLKDIV1` register.
"] + #[inline(always)] + pub const fn ioconfig_clkdiv(&self, n: usize) -> &IoconfigClkdiv { + &self.ioconfig_clkdiv[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x4c..0x68 - IO Configuration Clock Divider Register"] + #[inline(always)] + pub fn ioconfig_clkdiv_iter(&self) -> impl Iterator { + self.ioconfig_clkdiv.iter() + } + #[doc = "0x4c - IO Configuration Clock Divider Register"] + #[inline(always)] + pub const fn ioconfig_clkdiv1(&self) -> &IoconfigClkdiv { + self.ioconfig_clkdiv(0) + } + #[doc = "0x50 - IO Configuration Clock Divider Register"] + #[inline(always)] + pub const fn ioconfig_clkdiv2(&self) -> &IoconfigClkdiv { + self.ioconfig_clkdiv(1) + } + #[doc = "0x54 - IO Configuration Clock Divider Register"] + #[inline(always)] + pub const fn ioconfig_clkdiv3(&self) -> &IoconfigClkdiv { + self.ioconfig_clkdiv(2) + } + #[doc = "0x58 - IO Configuration Clock Divider Register"] + #[inline(always)] + pub const fn ioconfig_clkdiv4(&self) -> &IoconfigClkdiv { + self.ioconfig_clkdiv(3) + } + #[doc = "0x5c - IO Configuration Clock Divider Register"] + #[inline(always)] + pub const fn ioconfig_clkdiv5(&self) -> &IoconfigClkdiv { + self.ioconfig_clkdiv(4) + } + #[doc = "0x60 - IO Configuration Clock Divider Register"] + #[inline(always)] + pub const fn ioconfig_clkdiv6(&self) -> &IoconfigClkdiv { + self.ioconfig_clkdiv(5) + } + #[doc = "0x64 - IO Configuration Clock Divider Register"] + #[inline(always)] + pub const fn ioconfig_clkdiv7(&self) -> &IoconfigClkdiv { + self.ioconfig_clkdiv(6) + } + #[doc = "0x68 - ROM BOOT Retry count"] + #[inline(always)] + pub const fn rom_retries(&self) -> &RomRetries { + &self.rom_retries + } + #[doc = "0x6c - Register Refresh Control"] + #[inline(always)] + pub const fn refresh_config(&self) -> &RefreshConfig { + &self.refresh_config + } + #[doc = "0x70 - TIM Reset Control"] + #[inline(always)] + pub const fn tim_reset(&self) -> &TimReset { + &self.tim_reset + } + #[doc = "0x74 - TIM Enable Control"] + #[inline(always)] + pub const fn tim_clk_enable(&self) -> &TimClkEnable { + &self.tim_clk_enable + } + #[doc = "0x78 - Peripheral Reset Control"] + #[inline(always)] + pub const fn peripheral_reset(&self) -> &PeripheralReset { + &self.peripheral_reset + } + #[doc = "0x7c - Peripheral Enable Control"] + #[inline(always)] + pub const fn peripheral_clk_enable(&self) -> &PeripheralClkEnable { + &self.peripheral_clk_enable + } + #[doc = "0x80 - Lockup Reset Configuration"] + #[inline(always)] + pub const fn lockup_reset(&self) -> &LockupReset { + &self.lockup_reset + } + #[doc = "0xff0 - EFuse Config Register"] + #[inline(always)] + pub const fn ef_config(&self) -> &EfConfig { + &self.ef_config + } + #[doc = "0xff4 - EFuse ID Register"] + #[inline(always)] + pub const fn ef_id(&self) -> &EfId { + &self.ef_id + } + #[doc = "0xff8 - Processor ID Register"] + #[inline(always)] + pub const fn procid(&self) -> &Procid { + &self.procid + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`] module"] +#[doc(alias = "RST_STAT")] +pub type RstStat = crate::Reg; +#[doc = "System Reset Status"] +pub mod rst_stat; +pub use rst_stat as rst_cntl_rom; +pub use rst_stat as rst_cntl_ram; +pub use RstStat as RstCntlRom; +pub use RstStat as RstCntlRam; +#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`] module"] +#[doc(alias = "ROM_PROT")] +pub type RomProt = crate::Reg; +#[doc = "ROM Protection Configuration"] +pub mod rom_prot; +#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`] module"] +#[doc(alias = "ROM_SCRUB")] +pub type RomScrub = crate::Reg; +#[doc = "ROM Scrub Period Configuration"] +pub mod rom_scrub; +pub use rom_scrub as ram_scrub; +pub use RomScrub as RamScrub; +#[doc = "ROM_TRAP_ADDR (rw) register accessor: ROM Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_addr`] module"] +#[doc(alias = "ROM_TRAP_ADDR")] +pub type RomTrapAddr = crate::Reg; +#[doc = "ROM Trap Address"] +pub mod rom_trap_addr; +#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`] module"] +#[doc(alias = "ROM_TRAP_SYND")] +pub type RomTrapSynd = crate::Reg; +#[doc = "ROM Trap Syndrome"] +pub mod rom_trap_synd; +pub use rom_trap_addr as ram_trap_addr; +pub use rom_trap_synd as ram_trap_synd; +pub use RomTrapAddr as RamTrapAddr; +pub use RomTrapSynd as RamTrapSynd; +#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Enable EDAC Error Interrupt Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RAM_SBE (rw) register accessor: Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sbe`] module"] +#[doc(alias = "RAM_SBE")] +pub type RamSbe = crate::Reg; +#[doc = "Count of RAM EDAC Single Bit Errors"] +pub mod ram_sbe; +pub use ram_sbe as ram_mbe; +pub use ram_sbe as rom_sbe; +pub use ram_sbe as rom_mbe; +pub use RamSbe as RamMbe; +pub use RamSbe as RomSbe; +pub use RamSbe as RomMbe; +#[doc = "IOCONFIG_CLKDIV0 (r) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv0`] module"] +#[doc(alias = "IOCONFIG_CLKDIV0")] +pub type IoconfigClkdiv0 = crate::Reg; +#[doc = "IO Configuration Clock Divider Register"] +pub mod ioconfig_clkdiv0; +#[doc = "IOCONFIG_CLKDIV (rw) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv`] module"] +#[doc(alias = "IOCONFIG_CLKDIV")] +pub type IoconfigClkdiv = crate::Reg; +#[doc = "IO Configuration Clock Divider Register"] +pub mod ioconfig_clkdiv; +#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`] module"] +#[doc(alias = "ROM_RETRIES")] +pub type RomRetries = crate::Reg; +#[doc = "ROM BOOT Retry count"] +pub mod rom_retries; +#[doc = "REFRESH_CONFIG (rw) register accessor: Register Refresh Control\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config`] module"] +#[doc(alias = "REFRESH_CONFIG")] +pub type RefreshConfig = crate::Reg; +#[doc = "Register Refresh Control"] +pub mod refresh_config; +#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`] module"] +#[doc(alias = "TIM_RESET")] +pub type TimReset = crate::Reg; +#[doc = "TIM Reset Control"] +pub mod tim_reset; +#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`] module"] +#[doc(alias = "TIM_CLK_ENABLE")] +pub type TimClkEnable = crate::Reg; +#[doc = "TIM Enable Control"] +pub mod tim_clk_enable; +#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`] module"] +#[doc(alias = "PERIPHERAL_RESET")] +pub type PeripheralReset = crate::Reg; +#[doc = "Peripheral Reset Control"] +pub mod peripheral_reset; +#[doc = "PERIPHERAL_CLK_ENABLE (rw) register accessor: Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_clk_enable`] module"] +#[doc(alias = "PERIPHERAL_CLK_ENABLE")] +pub type PeripheralClkEnable = crate::Reg; +#[doc = "Peripheral Enable Control"] +pub mod peripheral_clk_enable; +#[doc = "LOCKUP_RESET (rw) register accessor: Lockup Reset Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lockup_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockup_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lockup_reset`] module"] +#[doc(alias = "LOCKUP_RESET")] +pub type LockupReset = crate::Reg; +#[doc = "Lockup Reset Configuration"] +pub mod lockup_reset; +#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`] module"] +#[doc(alias = "EF_CONFIG")] +pub type EfConfig = crate::Reg; +#[doc = "EFuse Config Register"] +pub mod ef_config; +#[doc = "EF_ID (r) register accessor: EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id`] module"] +#[doc(alias = "EF_ID")] +pub type EfId = crate::Reg; +#[doc = "EFuse ID Register"] +pub mod ef_id; +#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`] module"] +#[doc(alias = "PROCID")] +pub type Procid = crate::Reg; +#[doc = "Processor ID Register"] +pub mod procid; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va108xx/va108xx/src/sysconfig/ef_config.rs b/va108xx/va108xx/src/sysconfig/ef_config.rs new file mode 100644 index 0000000..dee1625 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/ef_config.rs @@ -0,0 +1,17 @@ +#[doc = "Register `EF_CONFIG` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EfConfigSpec; +impl crate::RegisterSpec for EfConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ef_config::R`](R) reader structure"] +impl crate::Readable for EfConfigSpec {} +#[doc = "`reset()` method sets EF_CONFIG to value 0"] +impl crate::Resettable for EfConfigSpec {} diff --git a/va108xx/va108xx/src/sysconfig/ef_id.rs b/va108xx/va108xx/src/sysconfig/ef_id.rs new file mode 100644 index 0000000..146ff26 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/ef_id.rs @@ -0,0 +1,17 @@ +#[doc = "Register `EF_ID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EfIdSpec; +impl crate::RegisterSpec for EfIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ef_id::R`](R) reader structure"] +impl crate::Readable for EfIdSpec {} +#[doc = "`reset()` method sets EF_ID to value 0"] +impl crate::Resettable for EfIdSpec {} diff --git a/va108xx/va108xx/src/sysconfig/ioconfig_clkdiv.rs b/va108xx/va108xx/src/sysconfig/ioconfig_clkdiv.rs new file mode 100644 index 0000000..a115337 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/ioconfig_clkdiv.rs @@ -0,0 +1,24 @@ +#[doc = "Register `IOCONFIG_CLKDIV%s` reader"] +pub type R = crate::R; +#[doc = "Register `IOCONFIG_CLKDIV%s` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IoconfigClkdivSpec; +impl crate::RegisterSpec for IoconfigClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioconfig_clkdiv::R`](R) reader structure"] +impl crate::Readable for IoconfigClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`ioconfig_clkdiv::W`](W) writer structure"] +impl crate::Writable for IoconfigClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IOCONFIG_CLKDIV%s to value 0"] +impl crate::Resettable for IoconfigClkdivSpec {} diff --git a/va108xx/va108xx/src/sysconfig/ioconfig_clkdiv0.rs b/va108xx/va108xx/src/sysconfig/ioconfig_clkdiv0.rs new file mode 100644 index 0000000..c2ddc0c --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/ioconfig_clkdiv0.rs @@ -0,0 +1,17 @@ +#[doc = "Register `IOCONFIG_CLKDIV0` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IoconfigClkdiv0Spec; +impl crate::RegisterSpec for IoconfigClkdiv0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ioconfig_clkdiv0::R`](R) reader structure"] +impl crate::Readable for IoconfigClkdiv0Spec {} +#[doc = "`reset()` method sets IOCONFIG_CLKDIV0 to value 0"] +impl crate::Resettable for IoconfigClkdiv0Spec {} diff --git a/va108xx/va108xx/src/sysconfig/irq_enb.rs b/va108xx/va108xx/src/sysconfig/irq_enb.rs new file mode 100644 index 0000000..61838df --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/irq_enb.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `RAMSBE` reader - RAM Single Bit Interrupt"] +pub type RamsbeR = crate::BitReader; +#[doc = "Field `RAMSBE` writer - RAM Single Bit Interrupt"] +pub type RamsbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAMMBE` reader - RAM Multi Bit Interrupt"] +pub type RammbeR = crate::BitReader; +#[doc = "Field `RAMMBE` writer - RAM Multi Bit Interrupt"] +pub type RammbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"] +pub type RomsbeR = crate::BitReader; +#[doc = "Field `ROMSBE` writer - ROM Single Bit Interrupt"] +pub type RomsbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"] +pub type RommbeR = crate::BitReader; +#[doc = "Field `ROMMBE` writer - ROM Multi Bit Interrupt"] +pub type RommbeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - RAM Single Bit Interrupt"] + #[inline(always)] + pub fn ramsbe(&self) -> RamsbeR { + RamsbeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RAM Multi Bit Interrupt"] + #[inline(always)] + pub fn rammbe(&self) -> RammbeR { + RammbeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&self) -> RomsbeR { + RomsbeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&self) -> RommbeR { + RommbeR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RAM Single Bit Interrupt"] + #[inline(always)] + pub fn ramsbe(&mut self) -> RamsbeW<'_, IrqEnbSpec> { + RamsbeW::new(self, 0) + } + #[doc = "Bit 1 - RAM Multi Bit Interrupt"] + #[inline(always)] + pub fn rammbe(&mut self) -> RammbeW<'_, IrqEnbSpec> { + RammbeW::new(self, 1) + } + #[doc = "Bit 2 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&mut self) -> RomsbeW<'_, IrqEnbSpec> { + RomsbeW::new(self, 2) + } + #[doc = "Bit 3 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&mut self) -> RommbeW<'_, IrqEnbSpec> { + RommbeW::new(self, 3) + } +} +#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va108xx/va108xx/src/sysconfig/lockup_reset.rs b/va108xx/va108xx/src/sysconfig/lockup_reset.rs new file mode 100644 index 0000000..e5b5523 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/lockup_reset.rs @@ -0,0 +1,37 @@ +#[doc = "Register `LOCKUP_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `LOCKUP_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `LREN` reader - Lockup Reset Enable Bit"] +pub type LrenR = crate::BitReader; +#[doc = "Field `LREN` writer - Lockup Reset Enable Bit"] +pub type LrenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Lockup Reset Enable Bit"] + #[inline(always)] + pub fn lren(&self) -> LrenR { + LrenR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Lockup Reset Enable Bit"] + #[inline(always)] + pub fn lren(&mut self) -> LrenW<'_, LockupResetSpec> { + LrenW::new(self, 0) + } +} +#[doc = "Lockup Reset Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lockup_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockup_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LockupResetSpec; +impl crate::RegisterSpec for LockupResetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lockup_reset::R`](R) reader structure"] +impl crate::Readable for LockupResetSpec {} +#[doc = "`write(|w| ..)` method takes [`lockup_reset::W`](W) writer structure"] +impl crate::Writable for LockupResetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets LOCKUP_RESET to value 0x01"] +impl crate::Resettable for LockupResetSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/va108xx/va108xx/src/sysconfig/perid.rs b/va108xx/va108xx/src/sysconfig/perid.rs new file mode 100644 index 0000000..0593594 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0080_07e1"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0080_07e1; +} diff --git a/va108xx/va108xx/src/sysconfig/peripheral_clk_enable.rs b/va108xx/va108xx/src/sysconfig/peripheral_clk_enable.rs new file mode 100644 index 0000000..f1d78dc --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/peripheral_clk_enable.rs @@ -0,0 +1,203 @@ +#[doc = "Register `PERIPHERAL_CLK_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPHERAL_CLK_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `PORTA` reader - Enable PORTA clock"] +pub type PortaR = crate::BitReader; +#[doc = "Field `PORTA` writer - Enable PORTA clock"] +pub type PortaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTB` reader - Enable PORTB clock"] +pub type PortbR = crate::BitReader; +#[doc = "Field `PORTB` writer - Enable PORTB clock"] +pub type PortbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_0` reader - Enable SPI\\[0\\] clock"] +pub type Spi0R = crate::BitReader; +#[doc = "Field `SPI_0` writer - Enable SPI\\[0\\] clock"] +pub type Spi0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_1` reader - Enable SPI\\[1\\] clock"] +pub type Spi1R = crate::BitReader; +#[doc = "Field `SPI_1` writer - Enable SPI\\[1\\] clock"] +pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_2` reader - Enable SPI\\[2\\] clock"] +pub type Spi2R = crate::BitReader; +#[doc = "Field `SPI_2` writer - Enable SPI\\[2\\] clock"] +pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART_0` reader - Enable UART\\[0\\] clock"] +pub type Uart0R = crate::BitReader; +#[doc = "Field `UART_0` writer - Enable UART\\[0\\] clock"] +pub type Uart0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART_1` reader - Enable UART\\[1\\] clock"] +pub type Uart1R = crate::BitReader; +#[doc = "Field `UART_1` writer - Enable UART\\[1\\] clock"] +pub type Uart1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_0` reader - Enable I2C\\[0\\] clock"] +pub type I2c0R = crate::BitReader; +#[doc = "Field `I2C_0` writer - Enable I2C\\[0\\] clock"] +pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_1` reader - Enable I2C\\[1\\] clock"] +pub type I2c1R = crate::BitReader; +#[doc = "Field `I2C_1` writer - Enable I2C\\[1\\] clock"] +pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQSEL` reader - Enable IRQ selector clock"] +pub type IrqselR = crate::BitReader; +#[doc = "Field `IRQSEL` writer - Enable IRQ selector clock"] +pub type IrqselW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IOCONFIG` reader - Enable IO Configuration block clock"] +pub type IoconfigR = crate::BitReader; +#[doc = "Field `IOCONFIG` writer - Enable IO Configuration block clock"] +pub type IoconfigW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UTILITY` reader - Enable utility clock"] +pub type UtilityR = crate::BitReader; +#[doc = "Field `UTILITY` writer - Enable utility clock"] +pub type UtilityW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO` reader - Enable GPIO clock"] +pub type GpioR = crate::BitReader; +#[doc = "Field `GPIO` writer - Enable GPIO clock"] +pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable PORTA clock"] + #[inline(always)] + pub fn porta(&self) -> PortaR { + PortaR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable PORTB clock"] + #[inline(always)] + pub fn portb(&self) -> PortbR { + PortbR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Enable SPI\\[0\\] clock"] + #[inline(always)] + pub fn spi_0(&self) -> Spi0R { + Spi0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable SPI\\[1\\] clock"] + #[inline(always)] + pub fn spi_1(&self) -> Spi1R { + Spi1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable SPI\\[2\\] clock"] + #[inline(always)] + pub fn spi_2(&self) -> Spi2R { + Spi2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Enable UART\\[0\\] clock"] + #[inline(always)] + pub fn uart_0(&self) -> Uart0R { + Uart0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable UART\\[1\\] clock"] + #[inline(always)] + pub fn uart_1(&self) -> Uart1R { + Uart1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 16 - Enable I2C\\[0\\] clock"] + #[inline(always)] + pub fn i2c_0(&self) -> I2c0R { + I2c0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable I2C\\[1\\] clock"] + #[inline(always)] + pub fn i2c_1(&self) -> I2c1R { + I2c1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 21 - Enable IRQ selector clock"] + #[inline(always)] + pub fn irqsel(&self) -> IrqselR { + IrqselR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Enable IO Configuration block clock"] + #[inline(always)] + pub fn ioconfig(&self) -> IoconfigR { + IoconfigR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Enable utility clock"] + #[inline(always)] + pub fn utility(&self) -> UtilityR { + UtilityR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Enable GPIO clock"] + #[inline(always)] + pub fn gpio(&self) -> GpioR { + GpioR::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable PORTA clock"] + #[inline(always)] + pub fn porta(&mut self) -> PortaW<'_, PeripheralClkEnableSpec> { + PortaW::new(self, 0) + } + #[doc = "Bit 1 - Enable PORTB clock"] + #[inline(always)] + pub fn portb(&mut self) -> PortbW<'_, PeripheralClkEnableSpec> { + PortbW::new(self, 1) + } + #[doc = "Bit 4 - Enable SPI\\[0\\] clock"] + #[inline(always)] + pub fn spi_0(&mut self) -> Spi0W<'_, PeripheralClkEnableSpec> { + Spi0W::new(self, 4) + } + #[doc = "Bit 5 - Enable SPI\\[1\\] clock"] + #[inline(always)] + pub fn spi_1(&mut self) -> Spi1W<'_, PeripheralClkEnableSpec> { + Spi1W::new(self, 5) + } + #[doc = "Bit 6 - Enable SPI\\[2\\] clock"] + #[inline(always)] + pub fn spi_2(&mut self) -> Spi2W<'_, PeripheralClkEnableSpec> { + Spi2W::new(self, 6) + } + #[doc = "Bit 8 - Enable UART\\[0\\] clock"] + #[inline(always)] + pub fn uart_0(&mut self) -> Uart0W<'_, PeripheralClkEnableSpec> { + Uart0W::new(self, 8) + } + #[doc = "Bit 9 - Enable UART\\[1\\] clock"] + #[inline(always)] + pub fn uart_1(&mut self) -> Uart1W<'_, PeripheralClkEnableSpec> { + Uart1W::new(self, 9) + } + #[doc = "Bit 16 - Enable I2C\\[0\\] clock"] + #[inline(always)] + pub fn i2c_0(&mut self) -> I2c0W<'_, PeripheralClkEnableSpec> { + I2c0W::new(self, 16) + } + #[doc = "Bit 17 - Enable I2C\\[1\\] clock"] + #[inline(always)] + pub fn i2c_1(&mut self) -> I2c1W<'_, PeripheralClkEnableSpec> { + I2c1W::new(self, 17) + } + #[doc = "Bit 21 - Enable IRQ selector clock"] + #[inline(always)] + pub fn irqsel(&mut self) -> IrqselW<'_, PeripheralClkEnableSpec> { + IrqselW::new(self, 21) + } + #[doc = "Bit 22 - Enable IO Configuration block clock"] + #[inline(always)] + pub fn ioconfig(&mut self) -> IoconfigW<'_, PeripheralClkEnableSpec> { + IoconfigW::new(self, 22) + } + #[doc = "Bit 23 - Enable utility clock"] + #[inline(always)] + pub fn utility(&mut self) -> UtilityW<'_, PeripheralClkEnableSpec> { + UtilityW::new(self, 23) + } + #[doc = "Bit 24 - Enable GPIO clock"] + #[inline(always)] + pub fn gpio(&mut self) -> GpioW<'_, PeripheralClkEnableSpec> { + GpioW::new(self, 24) + } +} +#[doc = "Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeripheralClkEnableSpec; +impl crate::RegisterSpec for PeripheralClkEnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`peripheral_clk_enable::R`](R) reader structure"] +impl crate::Readable for PeripheralClkEnableSpec {} +#[doc = "`write(|w| ..)` method takes [`peripheral_clk_enable::W`](W) writer structure"] +impl crate::Writable for PeripheralClkEnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PERIPHERAL_CLK_ENABLE to value 0"] +impl crate::Resettable for PeripheralClkEnableSpec {} diff --git a/va108xx/va108xx/src/sysconfig/peripheral_reset.rs b/va108xx/va108xx/src/sysconfig/peripheral_reset.rs new file mode 100644 index 0000000..92a21d1 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/peripheral_reset.rs @@ -0,0 +1,205 @@ +#[doc = "Register `PERIPHERAL_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPHERAL_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `PORTA` reader - Reset PORTA"] +pub type PortaR = crate::BitReader; +#[doc = "Field `PORTA` writer - Reset PORTA"] +pub type PortaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTB` reader - Reset PORTB"] +pub type PortbR = crate::BitReader; +#[doc = "Field `PORTB` writer - Reset PORTB"] +pub type PortbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_0` reader - Reset SPI\\[0\\]"] +pub type Spi0R = crate::BitReader; +#[doc = "Field `SPI_0` writer - Reset SPI\\[0\\]"] +pub type Spi0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_1` reader - Reset SPI\\[1\\]"] +pub type Spi1R = crate::BitReader; +#[doc = "Field `SPI_1` writer - Reset SPI\\[1\\]"] +pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_2` reader - Reset SPI\\[2\\]"] +pub type Spi2R = crate::BitReader; +#[doc = "Field `SPI_2` writer - Reset SPI\\[2\\]"] +pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART_0` reader - Reset UART\\[0\\]"] +pub type Uart0R = crate::BitReader; +#[doc = "Field `UART_0` writer - Reset UART\\[0\\]"] +pub type Uart0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART_1` reader - Reset UART\\[1\\]"] +pub type Uart1R = crate::BitReader; +#[doc = "Field `UART_1` writer - Reset UART\\[1\\]"] +pub type Uart1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_0` reader - Reset I2C\\[0\\]"] +pub type I2c0R = crate::BitReader; +#[doc = "Field `I2C_0` writer - Reset I2C\\[0\\]"] +pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_1` reader - Reset I2C\\[1\\]"] +pub type I2c1R = crate::BitReader; +#[doc = "Field `I2C_1` writer - Reset I2C\\[1\\]"] +pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQSEL` reader - Reset IRQ selector"] +pub type IrqselR = crate::BitReader; +#[doc = "Field `IRQSEL` writer - Reset IRQ selector"] +pub type IrqselW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IOCONFIG` reader - Reset IO Configuration block"] +pub type IoconfigR = crate::BitReader; +#[doc = "Field `IOCONFIG` writer - Reset IO Configuration block"] +pub type IoconfigW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UTILITY` reader - Reset Utility Block"] +pub type UtilityR = crate::BitReader; +#[doc = "Field `UTILITY` writer - Reset Utility Block"] +pub type UtilityW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO` reader - Reset GPIO"] +pub type GpioR = crate::BitReader; +#[doc = "Field `GPIO` writer - Reset GPIO"] +pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reset PORTA"] + #[inline(always)] + pub fn porta(&self) -> PortaR { + PortaR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reset PORTB"] + #[inline(always)] + pub fn portb(&self) -> PortbR { + PortbR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Reset SPI\\[0\\]"] + #[inline(always)] + pub fn spi_0(&self) -> Spi0R { + Spi0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reset SPI\\[1\\]"] + #[inline(always)] + pub fn spi_1(&self) -> Spi1R { + Spi1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reset SPI\\[2\\]"] + #[inline(always)] + pub fn spi_2(&self) -> Spi2R { + Spi2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Reset UART\\[0\\]"] + #[inline(always)] + pub fn uart_0(&self) -> Uart0R { + Uart0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reset UART\\[1\\]"] + #[inline(always)] + pub fn uart_1(&self) -> Uart1R { + Uart1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 16 - Reset I2C\\[0\\]"] + #[inline(always)] + pub fn i2c_0(&self) -> I2c0R { + I2c0R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reset I2C\\[1\\]"] + #[inline(always)] + pub fn i2c_1(&self) -> I2c1R { + I2c1R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 21 - Reset IRQ selector"] + #[inline(always)] + pub fn irqsel(&self) -> IrqselR { + IrqselR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reset IO Configuration block"] + #[inline(always)] + pub fn ioconfig(&self) -> IoconfigR { + IoconfigR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reset Utility Block"] + #[inline(always)] + pub fn utility(&self) -> UtilityR { + UtilityR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reset GPIO"] + #[inline(always)] + pub fn gpio(&self) -> GpioR { + GpioR::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Reset PORTA"] + #[inline(always)] + pub fn porta(&mut self) -> PortaW<'_, PeripheralResetSpec> { + PortaW::new(self, 0) + } + #[doc = "Bit 1 - Reset PORTB"] + #[inline(always)] + pub fn portb(&mut self) -> PortbW<'_, PeripheralResetSpec> { + PortbW::new(self, 1) + } + #[doc = "Bit 4 - Reset SPI\\[0\\]"] + #[inline(always)] + pub fn spi_0(&mut self) -> Spi0W<'_, PeripheralResetSpec> { + Spi0W::new(self, 4) + } + #[doc = "Bit 5 - Reset SPI\\[1\\]"] + #[inline(always)] + pub fn spi_1(&mut self) -> Spi1W<'_, PeripheralResetSpec> { + Spi1W::new(self, 5) + } + #[doc = "Bit 6 - Reset SPI\\[2\\]"] + #[inline(always)] + pub fn spi_2(&mut self) -> Spi2W<'_, PeripheralResetSpec> { + Spi2W::new(self, 6) + } + #[doc = "Bit 8 - Reset UART\\[0\\]"] + #[inline(always)] + pub fn uart_0(&mut self) -> Uart0W<'_, PeripheralResetSpec> { + Uart0W::new(self, 8) + } + #[doc = "Bit 9 - Reset UART\\[1\\]"] + #[inline(always)] + pub fn uart_1(&mut self) -> Uart1W<'_, PeripheralResetSpec> { + Uart1W::new(self, 9) + } + #[doc = "Bit 16 - Reset I2C\\[0\\]"] + #[inline(always)] + pub fn i2c_0(&mut self) -> I2c0W<'_, PeripheralResetSpec> { + I2c0W::new(self, 16) + } + #[doc = "Bit 17 - Reset I2C\\[1\\]"] + #[inline(always)] + pub fn i2c_1(&mut self) -> I2c1W<'_, PeripheralResetSpec> { + I2c1W::new(self, 17) + } + #[doc = "Bit 21 - Reset IRQ selector"] + #[inline(always)] + pub fn irqsel(&mut self) -> IrqselW<'_, PeripheralResetSpec> { + IrqselW::new(self, 21) + } + #[doc = "Bit 22 - Reset IO Configuration block"] + #[inline(always)] + pub fn ioconfig(&mut self) -> IoconfigW<'_, PeripheralResetSpec> { + IoconfigW::new(self, 22) + } + #[doc = "Bit 23 - Reset Utility Block"] + #[inline(always)] + pub fn utility(&mut self) -> UtilityW<'_, PeripheralResetSpec> { + UtilityW::new(self, 23) + } + #[doc = "Bit 24 - Reset GPIO"] + #[inline(always)] + pub fn gpio(&mut self) -> GpioW<'_, PeripheralResetSpec> { + GpioW::new(self, 24) + } +} +#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeripheralResetSpec; +impl crate::RegisterSpec for PeripheralResetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`peripheral_reset::R`](R) reader structure"] +impl crate::Readable for PeripheralResetSpec {} +#[doc = "`write(|w| ..)` method takes [`peripheral_reset::W`](W) writer structure"] +impl crate::Writable for PeripheralResetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PERIPHERAL_RESET to value 0xffff_ffff"] +impl crate::Resettable for PeripheralResetSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va108xx/va108xx/src/sysconfig/procid.rs b/va108xx/va108xx/src/sysconfig/procid.rs new file mode 100644 index 0000000..98b8907 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/procid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PROCID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ProcidSpec; +impl crate::RegisterSpec for ProcidSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`procid::R`](R) reader structure"] +impl crate::Readable for ProcidSpec {} +#[doc = "`reset()` method sets PROCID to value 0x0400_17e3"] +impl crate::Resettable for ProcidSpec { + const RESET_VALUE: u32 = 0x0400_17e3; +} diff --git a/va108xx/va108xx/src/sysconfig/ram_sbe.rs b/va108xx/va108xx/src/sysconfig/ram_sbe.rs new file mode 100644 index 0000000..f70d068 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/ram_sbe.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RAM_SBE` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_SBE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamSbeSpec; +impl crate::RegisterSpec for RamSbeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_sbe::R`](R) reader structure"] +impl crate::Readable for RamSbeSpec {} +#[doc = "`write(|w| ..)` method takes [`ram_sbe::W`](W) writer structure"] +impl crate::Writable for RamSbeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RAM_SBE to value 0"] +impl crate::Resettable for RamSbeSpec {} diff --git a/va108xx/va108xx/src/sysconfig/refresh_config.rs b/va108xx/va108xx/src/sysconfig/refresh_config.rs new file mode 100644 index 0000000..0d29da8 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/refresh_config.rs @@ -0,0 +1,24 @@ +#[doc = "Register `REFRESH_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `REFRESH_CONFIG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Register Refresh Control\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RefreshConfigSpec; +impl crate::RegisterSpec for RefreshConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`refresh_config::R`](R) reader structure"] +impl crate::Readable for RefreshConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`refresh_config::W`](W) writer structure"] +impl crate::Writable for RefreshConfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets REFRESH_CONFIG to value 0"] +impl crate::Resettable for RefreshConfigSpec {} diff --git a/va108xx/va108xx/src/sysconfig/rom_prot.rs b/va108xx/va108xx/src/sysconfig/rom_prot.rs new file mode 100644 index 0000000..6ae1532 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/rom_prot.rs @@ -0,0 +1,37 @@ +#[doc = "Register `ROM_PROT` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_PROT` writer"] +pub type W = crate::W; +#[doc = "Field `WREN` reader - ROM Write Enable Bit"] +pub type WrenR = crate::BitReader; +#[doc = "Field `WREN` writer - ROM Write Enable Bit"] +pub type WrenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - ROM Write Enable Bit"] + #[inline(always)] + pub fn wren(&self) -> WrenR { + WrenR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ROM Write Enable Bit"] + #[inline(always)] + pub fn wren(&mut self) -> WrenW<'_, RomProtSpec> { + WrenW::new(self, 0) + } +} +#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomProtSpec; +impl crate::RegisterSpec for RomProtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_prot::R`](R) reader structure"] +impl crate::Readable for RomProtSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_prot::W`](W) writer structure"] +impl crate::Writable for RomProtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ROM_PROT to value 0x01"] +impl crate::Resettable for RomProtSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/va108xx/va108xx/src/sysconfig/rom_retries.rs b/va108xx/va108xx/src/sysconfig/rom_retries.rs new file mode 100644 index 0000000..6c58fd1 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/rom_retries.rs @@ -0,0 +1,17 @@ +#[doc = "Register `ROM_RETRIES` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomRetriesSpec; +impl crate::RegisterSpec for RomRetriesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_retries::R`](R) reader structure"] +impl crate::Readable for RomRetriesSpec {} +#[doc = "`reset()` method sets ROM_RETRIES to value 0"] +impl crate::Resettable for RomRetriesSpec {} diff --git a/va108xx/va108xx/src/sysconfig/rom_scrub.rs b/va108xx/va108xx/src/sysconfig/rom_scrub.rs new file mode 100644 index 0000000..19de208 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/rom_scrub.rs @@ -0,0 +1,43 @@ +#[doc = "Register `ROM_SCRUB` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_SCRUB` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` reader - Counter divide value"] +pub type ValueR = crate::FieldReader; +#[doc = "Field `VALUE` writer - Counter divide value"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `RESET` writer - Reset Counter"] +pub type ResetW<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&mut self) -> ValueW<'_, RomScrubSpec> { + ValueW::new(self, 0) + } + #[doc = "Bit 31 - Reset Counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW<'_, RomScrubSpec> { + ResetW::new(self, 31) + } +} +#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomScrubSpec; +impl crate::RegisterSpec for RomScrubSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_scrub::R`](R) reader structure"] +impl crate::Readable for RomScrubSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_scrub::W`](W) writer structure"] +impl crate::Writable for RomScrubSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000; +} +#[doc = "`reset()` method sets ROM_SCRUB to value 0"] +impl crate::Resettable for RomScrubSpec {} diff --git a/va108xx/va108xx/src/sysconfig/rom_trap_addr.rs b/va108xx/va108xx/src/sysconfig/rom_trap_addr.rs new file mode 100644 index 0000000..e5a5309 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/rom_trap_addr.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ROM_TRAP_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_TRAP_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - Trap Address Match Bits"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Trap Address Match Bits"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `ENABLE` reader - Trap Enable Bit"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Trap Enable Bit"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 2:15 - Trap Address Match Bits"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new(((self.bits >> 2) & 0x3fff) as u16) + } + #[doc = "Bit 31 - Trap Enable Bit"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:15 - Trap Address Match Bits"] + #[inline(always)] + pub fn addr(&mut self) -> AddrW<'_, RomTrapAddrSpec> { + AddrW::new(self, 2) + } + #[doc = "Bit 31 - Trap Enable Bit"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, RomTrapAddrSpec> { + EnableW::new(self, 31) + } +} +#[doc = "ROM Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomTrapAddrSpec; +impl crate::RegisterSpec for RomTrapAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_trap_addr::R`](R) reader structure"] +impl crate::Readable for RomTrapAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_trap_addr::W`](W) writer structure"] +impl crate::Writable for RomTrapAddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ROM_TRAP_ADDR to value 0"] +impl crate::Resettable for RomTrapAddrSpec {} diff --git a/va108xx/va108xx/src/sysconfig/rom_trap_synd.rs b/va108xx/va108xx/src/sysconfig/rom_trap_synd.rs new file mode 100644 index 0000000..679b8fa --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/rom_trap_synd.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ROM_TRAP_SYND` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_TRAP_SYND` writer"] +pub type W = crate::W; +#[doc = "Field `SYND` reader - Trap Syndrom Bits"] +pub type SyndR = crate::FieldReader; +#[doc = "Field `SYND` writer - Trap Syndrom Bits"] +pub type SyndW<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - Trap Syndrom Bits"] + #[inline(always)] + pub fn synd(&self) -> SyndR { + SyndR::new(self.bits & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 0:19 - Trap Syndrom Bits"] + #[inline(always)] + pub fn synd(&mut self) -> SyndW<'_, RomTrapSyndSpec> { + SyndW::new(self, 0) + } +} +#[doc = "ROM Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomTrapSyndSpec; +impl crate::RegisterSpec for RomTrapSyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_trap_synd::R`](R) reader structure"] +impl crate::Readable for RomTrapSyndSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_trap_synd::W`](W) writer structure"] +impl crate::Writable for RomTrapSyndSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ROM_TRAP_SYND to value 0"] +impl crate::Resettable for RomTrapSyndSpec {} diff --git a/va108xx/va108xx/src/sysconfig/rst_stat.rs b/va108xx/va108xx/src/sysconfig/rst_stat.rs new file mode 100644 index 0000000..4f60669 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/rst_stat.rs @@ -0,0 +1,107 @@ +#[doc = "Register `RST_STAT` reader"] +pub type R = crate::R; +#[doc = "Register `RST_STAT` writer"] +pub type W = crate::W; +#[doc = "Field `POR` reader - Power On Reset Status"] +pub type PorR = crate::BitReader; +#[doc = "Field `POR` writer - Power On Reset Status"] +pub type PorW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTRST` reader - External Reset Status"] +pub type ExtrstR = crate::BitReader; +#[doc = "Field `EXTRST` writer - External Reset Status"] +pub type ExtrstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"] +pub type SysrstreqR = crate::BitReader; +#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"] +pub type SysrstreqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"] +pub type LookupR = crate::BitReader; +#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"] +pub type LookupW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"] +pub type WatchdogR = crate::BitReader; +#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"] +pub type WatchdogW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEMERR` reader - Memory Error Reset Status"] +pub type MemerrR = crate::BitReader; +#[doc = "Field `MEMERR` writer - Memory Error Reset Status"] +pub type MemerrW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&self) -> PorR { + PorR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&self) -> ExtrstR { + ExtrstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&self) -> SysrstreqR { + SysrstreqR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&self) -> LookupR { + LookupR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&self) -> WatchdogR { + WatchdogR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Memory Error Reset Status"] + #[inline(always)] + pub fn memerr(&self) -> MemerrR { + MemerrR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&mut self) -> PorW<'_, RstStatSpec> { + PorW::new(self, 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&mut self) -> ExtrstW<'_, RstStatSpec> { + ExtrstW::new(self, 1) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&mut self) -> SysrstreqW<'_, RstStatSpec> { + SysrstreqW::new(self, 2) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&mut self) -> LookupW<'_, RstStatSpec> { + LookupW::new(self, 3) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&mut self) -> WatchdogW<'_, RstStatSpec> { + WatchdogW::new(self, 4) + } + #[doc = "Bit 5 - Memory Error Reset Status"] + #[inline(always)] + pub fn memerr(&mut self) -> MemerrW<'_, RstStatSpec> { + MemerrW::new(self, 5) + } +} +#[doc = "System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RstStatSpec; +impl crate::RegisterSpec for RstStatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_stat::R`](R) reader structure"] +impl crate::Readable for RstStatSpec {} +#[doc = "`write(|w| ..)` method takes [`rst_stat::W`](W) writer structure"] +impl crate::Writable for RstStatSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RST_STAT to value 0x01"] +impl crate::Resettable for RstStatSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/va108xx/va108xx/src/sysconfig/tim_clk_enable.rs b/va108xx/va108xx/src/sysconfig/tim_clk_enable.rs new file mode 100644 index 0000000..924f734 --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/tim_clk_enable.rs @@ -0,0 +1,24 @@ +#[doc = "Register `TIM_CLK_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `TIM_CLK_ENABLE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimClkEnableSpec; +impl crate::RegisterSpec for TimClkEnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tim_clk_enable::R`](R) reader structure"] +impl crate::Readable for TimClkEnableSpec {} +#[doc = "`write(|w| ..)` method takes [`tim_clk_enable::W`](W) writer structure"] +impl crate::Writable for TimClkEnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIM_CLK_ENABLE to value 0"] +impl crate::Resettable for TimClkEnableSpec {} diff --git a/va108xx/va108xx/src/sysconfig/tim_reset.rs b/va108xx/va108xx/src/sysconfig/tim_reset.rs new file mode 100644 index 0000000..f23b9ef --- /dev/null +++ b/va108xx/va108xx/src/sysconfig/tim_reset.rs @@ -0,0 +1,26 @@ +#[doc = "Register `TIM_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `TIM_RESET` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimResetSpec; +impl crate::RegisterSpec for TimResetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tim_reset::R`](R) reader structure"] +impl crate::Readable for TimResetSpec {} +#[doc = "`write(|w| ..)` method takes [`tim_reset::W`](W) writer structure"] +impl crate::Writable for TimResetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIM_RESET to value 0xffff_ffff"] +impl crate::Resettable for TimResetSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va108xx/va108xx/src/tim0.rs b/va108xx/va108xx/src/tim0.rs new file mode 100644 index 0000000..b4a76af --- /dev/null +++ b/va108xx/va108xx/src/tim0.rs @@ -0,0 +1,132 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + rst_value: RstValue, + cnt_value: CntValue, + enable: Enable, + csd_ctrl: CsdCtrl, + cascade0: Cascade0, + cascade1: Cascade1, + cascade2: Cascade2, + _reserved_8_pwm_value: [u8; 0x04], + pwmb_value: PwmbValue, + _reserved10: [u8; 0x0fd4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - The value that counter start from after reaching 0."] + #[inline(always)] + pub const fn rst_value(&self) -> &RstValue { + &self.rst_value + } + #[doc = "0x08 - The current value of the counter"] + #[inline(always)] + pub const fn cnt_value(&self) -> &CntValue { + &self.cnt_value + } + #[doc = "0x0c - Alternate access to the Counter ENABLE bit in the CTRL Register"] + #[inline(always)] + pub const fn enable(&self) -> &Enable { + &self.enable + } + #[doc = "0x10 - The Cascade Control Register. Controls the counter external enable signals"] + #[inline(always)] + pub const fn csd_ctrl(&self) -> &CsdCtrl { + &self.csd_ctrl + } + #[doc = "0x14 - Cascade Enable Selection"] + #[inline(always)] + pub const fn cascade0(&self) -> &Cascade0 { + &self.cascade0 + } + #[doc = "0x18 - Cascade Enable Selection"] + #[inline(always)] + pub const fn cascade1(&self) -> &Cascade1 { + &self.cascade1 + } + #[doc = "0x1c - Cascade Enable Selection"] + #[inline(always)] + pub const fn cascade2(&self) -> &Cascade2 { + &self.cascade2 + } + #[doc = "0x20 - The Pulse Width Modulation ValueA"] + #[inline(always)] + pub const fn pwma_value(&self) -> &PwmaValue { + unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } + } + #[doc = "0x20 - The Pulse Width Modulation Value"] + #[inline(always)] + pub const fn pwm_value(&self) -> &PwmValue { + unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } + } + #[doc = "0x24 - The Pulse Width Modulation ValueB"] + #[inline(always)] + pub const fn pwmb_value(&self) -> &PwmbValue { + &self.pwmb_value + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "RST_VALUE (rw) register accessor: The value that counter start from after reaching 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_value`] module"] +#[doc(alias = "RST_VALUE")] +pub type RstValue = crate::Reg; +#[doc = "The value that counter start from after reaching 0."] +pub mod rst_value; +#[doc = "CNT_VALUE (rw) register accessor: The current value of the counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt_value`] module"] +#[doc(alias = "CNT_VALUE")] +pub type CntValue = crate::Reg; +#[doc = "The current value of the counter"] +pub mod cnt_value; +#[doc = "ENABLE (rw) register accessor: Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] +#[doc(alias = "ENABLE")] +pub type Enable = crate::Reg; +#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register"] +pub mod enable; +#[doc = "CSD_CTRL (rw) register accessor: The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::Reg::read) this register and get [`csd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csd_ctrl`] module"] +#[doc(alias = "CSD_CTRL")] +pub type CsdCtrl = crate::Reg; +#[doc = "The Cascade Control Register. Controls the counter external enable signals"] +pub mod csd_ctrl; +#[doc = "CASCADE0 (rw) register accessor: Cascade Enable Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`cascade0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cascade0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cascade0`] module"] +#[doc(alias = "CASCADE0")] +pub type Cascade0 = crate::Reg; +#[doc = "Cascade Enable Selection"] +pub mod cascade0; +pub use cascade0 as cascade1; +pub use cascade0 as cascade2; +pub use Cascade0 as Cascade1; +pub use Cascade0 as Cascade2; +#[doc = "PWM_VALUE (rw) register accessor: The Pulse Width Modulation Value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_value`] module"] +#[doc(alias = "PWM_VALUE")] +pub type PwmValue = crate::Reg; +#[doc = "The Pulse Width Modulation Value"] +pub mod pwm_value; +#[doc = "PWMA_VALUE (rw) register accessor: The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::Reg::read) this register and get [`pwma_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwma_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwma_value`] module"] +#[doc(alias = "PWMA_VALUE")] +pub type PwmaValue = crate::Reg; +#[doc = "The Pulse Width Modulation ValueA"] +pub mod pwma_value; +#[doc = "PWMB_VALUE (rw) register accessor: The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmb_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmb_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmb_value`] module"] +#[doc(alias = "PWMB_VALUE")] +pub type PwmbValue = crate::Reg; +#[doc = "The Pulse Width Modulation ValueB"] +pub mod pwmb_value; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va108xx/va108xx/src/tim0/cascade0.rs b/va108xx/va108xx/src/tim0/cascade0.rs new file mode 100644 index 0000000..216d7bd --- /dev/null +++ b/va108xx/va108xx/src/tim0/cascade0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CASCADE0` reader"] +pub type R = crate::R; +#[doc = "Register `CASCADE0` writer"] +pub type W = crate::W; +#[doc = "Field `CASSEL` reader - Cascade Selection"] +pub type CasselR = crate::FieldReader; +#[doc = "Field `CASSEL` writer - Cascade Selection"] +pub type CasselW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&self) -> CasselR { + CasselR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&mut self) -> CasselW<'_, Cascade0Spec> { + CasselW::new(self, 0) + } +} +#[doc = "Cascade Enable Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`cascade0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cascade0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cascade0Spec; +impl crate::RegisterSpec for Cascade0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cascade0::R`](R) reader structure"] +impl crate::Readable for Cascade0Spec {} +#[doc = "`write(|w| ..)` method takes [`cascade0::W`](W) writer structure"] +impl crate::Writable for Cascade0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CASCADE0 to value 0"] +impl crate::Resettable for Cascade0Spec {} diff --git a/va108xx/va108xx/src/tim0/cnt_value.rs b/va108xx/va108xx/src/tim0/cnt_value.rs new file mode 100644 index 0000000..39350ff --- /dev/null +++ b/va108xx/va108xx/src/tim0/cnt_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CNT_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `CNT_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The current value of the counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CntValueSpec; +impl crate::RegisterSpec for CntValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnt_value::R`](R) reader structure"] +impl crate::Readable for CntValueSpec {} +#[doc = "`write(|w| ..)` method takes [`cnt_value::W`](W) writer structure"] +impl crate::Writable for CntValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNT_VALUE to value 0"] +impl crate::Resettable for CntValueSpec {} diff --git a/va108xx/va108xx/src/tim0/csd_ctrl.rs b/va108xx/va108xx/src/tim0/csd_ctrl.rs new file mode 100644 index 0000000..17240fc --- /dev/null +++ b/va108xx/va108xx/src/tim0/csd_ctrl.rs @@ -0,0 +1,175 @@ +#[doc = "Register `CSD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CSD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CSDEN0` reader - Cascade 0 Enable"] +pub type Csden0R = crate::BitReader; +#[doc = "Field `CSDEN0` writer - Cascade 0 Enable"] +pub type Csden0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDINV0` reader - Cascade 0 Invert"] +pub type Csdinv0R = crate::BitReader; +#[doc = "Field `CSDINV0` writer - Cascade 0 Invert"] +pub type Csdinv0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDEN1` reader - Cascade 1 Enable"] +pub type Csden1R = crate::BitReader; +#[doc = "Field `CSDEN1` writer - Cascade 1 Enable"] +pub type Csden1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDINV1` reader - Cascade 1 Invert"] +pub type Csdinv1R = crate::BitReader; +#[doc = "Field `CSDINV1` writer - Cascade 1 Invert"] +pub type Csdinv1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCASOP` reader - Dual Cascade Operation (0:AND, 1:OR)"] +pub type DcasopR = crate::BitReader; +#[doc = "Field `DCASOP` writer - Dual Cascade Operation (0:AND, 1:OR)"] +pub type DcasopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDTRG0` reader - Cascade 0 Enabled as Trigger"] +pub type Csdtrg0R = crate::BitReader; +#[doc = "Field `CSDTRG0` writer - Cascade 0 Enabled as Trigger"] +pub type Csdtrg0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDTRG1` reader - Cascade 1 Enabled as Trigger"] +pub type Csdtrg1R = crate::BitReader; +#[doc = "Field `CSDTRG1` writer - Cascade 1 Enabled as Trigger"] +pub type Csdtrg1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDEN2` reader - Cascade 2 Enable"] +pub type Csden2R = crate::BitReader; +#[doc = "Field `CSDEN2` writer - Cascade 2 Enable"] +pub type Csden2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDINV2` reader - Cascade 2 Invert"] +pub type Csdinv2R = crate::BitReader; +#[doc = "Field `CSDINV2` writer - Cascade 2 Invert"] +pub type Csdinv2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDTRG2` reader - Cascade 2 Enabled as Trigger"] +pub type Csdtrg2R = crate::BitReader; +#[doc = "Field `CSDTRG2` writer - Cascade 2 Enabled as Trigger"] +pub type Csdtrg2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDXXX2` reader - Cascade 2 test mode"] +pub type Csdxxx2R = crate::BitReader; +#[doc = "Field `CSDXXX2` writer - Cascade 2 test mode"] +pub type Csdxxx2W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Cascade 0 Enable"] + #[inline(always)] + pub fn csden0(&self) -> Csden0R { + Csden0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Cascade 0 Invert"] + #[inline(always)] + pub fn csdinv0(&self) -> Csdinv0R { + Csdinv0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Cascade 1 Enable"] + #[inline(always)] + pub fn csden1(&self) -> Csden1R { + Csden1R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Cascade 1 Invert"] + #[inline(always)] + pub fn csdinv1(&self) -> Csdinv1R { + Csdinv1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"] + #[inline(always)] + pub fn dcasop(&self) -> DcasopR { + DcasopR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg0(&self) -> Csdtrg0R { + Csdtrg0R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg1(&self) -> Csdtrg1R { + Csdtrg1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Cascade 2 Enable"] + #[inline(always)] + pub fn csden2(&self) -> Csden2R { + Csden2R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Cascade 2 Invert"] + #[inline(always)] + pub fn csdinv2(&self) -> Csdinv2R { + Csdinv2R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg2(&self) -> Csdtrg2R { + Csdtrg2R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Cascade 2 test mode"] + #[inline(always)] + pub fn csdxxx2(&self) -> Csdxxx2R { + Csdxxx2R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cascade 0 Enable"] + #[inline(always)] + pub fn csden0(&mut self) -> Csden0W<'_, CsdCtrlSpec> { + Csden0W::new(self, 0) + } + #[doc = "Bit 1 - Cascade 0 Invert"] + #[inline(always)] + pub fn csdinv0(&mut self) -> Csdinv0W<'_, CsdCtrlSpec> { + Csdinv0W::new(self, 1) + } + #[doc = "Bit 2 - Cascade 1 Enable"] + #[inline(always)] + pub fn csden1(&mut self) -> Csden1W<'_, CsdCtrlSpec> { + Csden1W::new(self, 2) + } + #[doc = "Bit 3 - Cascade 1 Invert"] + #[inline(always)] + pub fn csdinv1(&mut self) -> Csdinv1W<'_, CsdCtrlSpec> { + Csdinv1W::new(self, 3) + } + #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"] + #[inline(always)] + pub fn dcasop(&mut self) -> DcasopW<'_, CsdCtrlSpec> { + DcasopW::new(self, 4) + } + #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg0(&mut self) -> Csdtrg0W<'_, CsdCtrlSpec> { + Csdtrg0W::new(self, 6) + } + #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg1(&mut self) -> Csdtrg1W<'_, CsdCtrlSpec> { + Csdtrg1W::new(self, 7) + } + #[doc = "Bit 8 - Cascade 2 Enable"] + #[inline(always)] + pub fn csden2(&mut self) -> Csden2W<'_, CsdCtrlSpec> { + Csden2W::new(self, 8) + } + #[doc = "Bit 9 - Cascade 2 Invert"] + #[inline(always)] + pub fn csdinv2(&mut self) -> Csdinv2W<'_, CsdCtrlSpec> { + Csdinv2W::new(self, 9) + } + #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg2(&mut self) -> Csdtrg2W<'_, CsdCtrlSpec> { + Csdtrg2W::new(self, 10) + } + #[doc = "Bit 11 - Cascade 2 test mode"] + #[inline(always)] + pub fn csdxxx2(&mut self) -> Csdxxx2W<'_, CsdCtrlSpec> { + Csdxxx2W::new(self, 11) + } +} +#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::Reg::read) this register and get [`csd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CsdCtrlSpec; +impl crate::RegisterSpec for CsdCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`csd_ctrl::R`](R) reader structure"] +impl crate::Readable for CsdCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`csd_ctrl::W`](W) writer structure"] +impl crate::Writable for CsdCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CSD_CTRL to value 0"] +impl crate::Resettable for CsdCtrlSpec {} diff --git a/va108xx/va108xx/src/tim0/ctrl.rs b/va108xx/va108xx/src/tim0/ctrl.rs new file mode 100644 index 0000000..bab9535 --- /dev/null +++ b/va108xx/va108xx/src/tim0/ctrl.rs @@ -0,0 +1,248 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Counter Enable"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Counter Enable"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE` reader - Counter Active"] +pub type ActiveR = crate::BitReader; +#[doc = "Field `AUTO_DISABLE` reader - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] +pub type AutoDisableR = crate::BitReader; +#[doc = "Field `AUTO_DISABLE` writer - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] +pub type AutoDisableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTO_DEACTIVATE` reader - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] +pub type AutoDeactivateR = crate::BitReader; +#[doc = "Field `AUTO_DEACTIVATE` writer - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] +pub type AutoDeactivateW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_ENB` reader - Interrupt Enable"] +pub type IrqEnbR = crate::BitReader; +#[doc = "Field `IRQ_ENB` writer - Interrupt Enable"] +pub type IrqEnbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Counter Status Selection\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum StatusSel { + #[doc = "0: Single cycle pulse when the counter reaches 0"] + Done = 0, + #[doc = "1: Returns the counter ACTIVE bit"] + Active = 1, + #[doc = "2: Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + Toggle = 2, + #[doc = "3: Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + Pwma = 3, + #[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + Pwmb = 4, + #[doc = "5: Returns the counter ENABLED bit"] + Enabled = 5, + #[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + PwmaActive = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: StatusSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for StatusSel { + type Ux = u8; +} +impl crate::IsEnum for StatusSel {} +#[doc = "Field `STATUS_SEL` reader - Counter Status Selection"] +pub type StatusSelR = crate::FieldReader; +impl StatusSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(StatusSel::Done), + 1 => Some(StatusSel::Active), + 2 => Some(StatusSel::Toggle), + 3 => Some(StatusSel::Pwma), + 4 => Some(StatusSel::Pwmb), + 5 => Some(StatusSel::Enabled), + 6 => Some(StatusSel::PwmaActive), + _ => None, + } + } + #[doc = "Single cycle pulse when the counter reaches 0"] + #[inline(always)] + pub fn is_done(&self) -> bool { + *self == StatusSel::Done + } + #[doc = "Returns the counter ACTIVE bit"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == StatusSel::Active + } + #[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + *self == StatusSel::Toggle + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + #[inline(always)] + pub fn is_pwma(&self) -> bool { + *self == StatusSel::Pwma + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + #[inline(always)] + pub fn is_pwmb(&self) -> bool { + *self == StatusSel::Pwmb + } + #[doc = "Returns the counter ENABLED bit"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == StatusSel::Enabled + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + #[inline(always)] + pub fn is_pwma_active(&self) -> bool { + *self == StatusSel::PwmaActive + } +} +#[doc = "Field `STATUS_SEL` writer - Counter Status Selection"] +pub type StatusSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, StatusSel>; +impl<'a, REG> StatusSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single cycle pulse when the counter reaches 0"] + #[inline(always)] + pub fn done(self) -> &'a mut crate::W { + self.variant(StatusSel::Done) + } + #[doc = "Returns the counter ACTIVE bit"] + #[inline(always)] + pub fn active(self) -> &'a mut crate::W { + self.variant(StatusSel::Active) + } + #[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + #[inline(always)] + pub fn toggle(self) -> &'a mut crate::W { + self.variant(StatusSel::Toggle) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + #[inline(always)] + pub fn pwma(self) -> &'a mut crate::W { + self.variant(StatusSel::Pwma) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + #[inline(always)] + pub fn pwmb(self) -> &'a mut crate::W { + self.variant(StatusSel::Pwmb) + } + #[doc = "Returns the counter ENABLED bit"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(StatusSel::Enabled) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + #[inline(always)] + pub fn pwma_active(self) -> &'a mut crate::W { + self.variant(StatusSel::PwmaActive) + } +} +#[doc = "Field `STATUS_INV` reader - Invert the Output Status"] +pub type StatusInvR = crate::BitReader; +#[doc = "Field `STATUS_INV` writer - Invert the Output Status"] +pub type StatusInvW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REQ_STOP` reader - Stop Request"] +pub type ReqStopR = crate::BitReader; +#[doc = "Field `REQ_STOP` writer - Stop Request"] +pub type ReqStopW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Counter Active"] + #[inline(always)] + pub fn active(&self) -> ActiveR { + ActiveR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_disable(&self) -> AutoDisableR { + AutoDisableR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_deactivate(&self) -> AutoDeactivateR { + AutoDeactivateR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt Enable"] + #[inline(always)] + pub fn irq_enb(&self) -> IrqEnbR { + IrqEnbR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - Counter Status Selection"] + #[inline(always)] + pub fn status_sel(&self) -> StatusSelR { + StatusSelR::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 8 - Invert the Output Status"] + #[inline(always)] + pub fn status_inv(&self) -> StatusInvR { + StatusInvR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Stop Request"] + #[inline(always)] + pub fn req_stop(&self) -> ReqStopR { + ReqStopR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, CtrlSpec> { + EnableW::new(self, 0) + } + #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_disable(&mut self) -> AutoDisableW<'_, CtrlSpec> { + AutoDisableW::new(self, 2) + } + #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_deactivate(&mut self) -> AutoDeactivateW<'_, CtrlSpec> { + AutoDeactivateW::new(self, 3) + } + #[doc = "Bit 4 - Interrupt Enable"] + #[inline(always)] + pub fn irq_enb(&mut self) -> IrqEnbW<'_, CtrlSpec> { + IrqEnbW::new(self, 4) + } + #[doc = "Bits 5:7 - Counter Status Selection"] + #[inline(always)] + pub fn status_sel(&mut self) -> StatusSelW<'_, CtrlSpec> { + StatusSelW::new(self, 5) + } + #[doc = "Bit 8 - Invert the Output Status"] + #[inline(always)] + pub fn status_inv(&mut self) -> StatusInvW<'_, CtrlSpec> { + StatusInvW::new(self, 8) + } + #[doc = "Bit 9 - Stop Request"] + #[inline(always)] + pub fn req_stop(&mut self) -> ReqStopW<'_, CtrlSpec> { + ReqStopW::new(self, 9) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/va108xx/va108xx/src/tim0/enable.rs b/va108xx/va108xx/src/tim0/enable.rs new file mode 100644 index 0000000..f142b05 --- /dev/null +++ b/va108xx/va108xx/src/tim0/enable.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Counter Enable"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Counter Enable"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, EnableSpec> { + EnableW::new(self, 0) + } +} +#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EnableSpec; +impl crate::RegisterSpec for EnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`enable::R`](R) reader structure"] +impl crate::Readable for EnableSpec {} +#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"] +impl crate::Writable for EnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for EnableSpec {} diff --git a/va108xx/va108xx/src/tim0/perid.rs b/va108xx/va108xx/src/tim0/perid.rs new file mode 100644 index 0000000..24b82c0 --- /dev/null +++ b/va108xx/va108xx/src/tim0/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0011_07e1"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0011_07e1; +} diff --git a/va108xx/va108xx/src/tim0/pwm_value.rs b/va108xx/va108xx/src/tim0/pwm_value.rs new file mode 100644 index 0000000..6ac3389 --- /dev/null +++ b/va108xx/va108xx/src/tim0/pwm_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `PWM_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `PWM_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The Pulse Width Modulation Value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmValueSpec; +impl crate::RegisterSpec for PwmValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm_value::R`](R) reader structure"] +impl crate::Readable for PwmValueSpec {} +#[doc = "`write(|w| ..)` method takes [`pwm_value::W`](W) writer structure"] +impl crate::Writable for PwmValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWM_VALUE to value 0"] +impl crate::Resettable for PwmValueSpec {} diff --git a/va108xx/va108xx/src/tim0/pwma_value.rs b/va108xx/va108xx/src/tim0/pwma_value.rs new file mode 100644 index 0000000..ada6a2f --- /dev/null +++ b/va108xx/va108xx/src/tim0/pwma_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `PWMA_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `PWMA_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::Reg::read) this register and get [`pwma_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwma_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmaValueSpec; +impl crate::RegisterSpec for PwmaValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwma_value::R`](R) reader structure"] +impl crate::Readable for PwmaValueSpec {} +#[doc = "`write(|w| ..)` method takes [`pwma_value::W`](W) writer structure"] +impl crate::Writable for PwmaValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWMA_VALUE to value 0"] +impl crate::Resettable for PwmaValueSpec {} diff --git a/va108xx/va108xx/src/tim0/pwmb_value.rs b/va108xx/va108xx/src/tim0/pwmb_value.rs new file mode 100644 index 0000000..6f09486 --- /dev/null +++ b/va108xx/va108xx/src/tim0/pwmb_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `PWMB_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `PWMB_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmb_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmb_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmbValueSpec; +impl crate::RegisterSpec for PwmbValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwmb_value::R`](R) reader structure"] +impl crate::Readable for PwmbValueSpec {} +#[doc = "`write(|w| ..)` method takes [`pwmb_value::W`](W) writer structure"] +impl crate::Writable for PwmbValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWMB_VALUE to value 0"] +impl crate::Resettable for PwmbValueSpec {} diff --git a/va108xx/va108xx/src/tim0/rst_value.rs b/va108xx/va108xx/src/tim0/rst_value.rs new file mode 100644 index 0000000..69d5109 --- /dev/null +++ b/va108xx/va108xx/src/tim0/rst_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RST_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `RST_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The value that counter start from after reaching 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RstValueSpec; +impl crate::RegisterSpec for RstValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_value::R`](R) reader structure"] +impl crate::Readable for RstValueSpec {} +#[doc = "`write(|w| ..)` method takes [`rst_value::W`](W) writer structure"] +impl crate::Writable for RstValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RST_VALUE to value 0"] +impl crate::Resettable for RstValueSpec {} diff --git a/va108xx/va108xx/src/uarta.rs b/va108xx/va108xx/src/uarta.rs new file mode 100644 index 0000000..43216ab --- /dev/null +++ b/va108xx/va108xx/src/uarta.rs @@ -0,0 +1,207 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + data: Data, + enable: Enable, + ctrl: Ctrl, + clkscale: Clkscale, + rxstatus: Rxstatus, + txstatus: Txstatus, + fifo_clr: FifoClr, + txbreak: Txbreak, + addr9: Addr9, + addr9mask: Addr9mask, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + txfifoirqtrg: Txfifoirqtrg, + rxfifortstrg: Rxfifortstrg, + state: State, + _reserved18: [u8; 0x0fb4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Data In/Out Register"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x04 - Enable Register"] + #[inline(always)] + pub const fn enable(&self) -> &Enable { + &self.enable + } + #[doc = "0x08 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x0c - Clock Scale Register"] + #[inline(always)] + pub const fn clkscale(&self) -> &Clkscale { + &self.clkscale + } + #[doc = "0x10 - Status Register"] + #[inline(always)] + pub const fn rxstatus(&self) -> &Rxstatus { + &self.rxstatus + } + #[doc = "0x14 - Status Register"] + #[inline(always)] + pub const fn txstatus(&self) -> &Txstatus { + &self.txstatus + } + #[doc = "0x18 - Clear FIFO Register"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x1c - Break Transmit Register"] + #[inline(always)] + pub const fn txbreak(&self) -> &Txbreak { + &self.txbreak + } + #[doc = "0x20 - Address9 Register"] + #[inline(always)] + pub const fn addr9(&self) -> &Addr9 { + &self.addr9 + } + #[doc = "0x24 - Address9 Mask Register"] + #[inline(always)] + pub const fn addr9mask(&self) -> &Addr9mask { + &self.addr9mask + } + #[doc = "0x28 - IRQ Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x2c - IRQ Raw Status Register"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x30 - IRQ Enabled Status Register"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x34 - IRQ Clear Status Register"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x38 - Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x3c - Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x40 - Rx FIFO RTS Trigger Level"] + #[inline(always)] + pub const fn rxfifortstrg(&self) -> &Rxfifortstrg { + &self.rxfifortstrg + } + #[doc = "0x44 - Internal STATE of UART Controller"] + #[inline(always)] + pub const fn state(&self) -> &State { + &self.state + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "DATA (rw) register accessor: Data In/Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data In/Out Register"] +pub mod data; +#[doc = "ENABLE (rw) register accessor: Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] +#[doc(alias = "ENABLE")] +pub type Enable = crate::Reg; +#[doc = "Enable Register"] +pub mod enable; +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "CLKSCALE (rw) register accessor: Clock Scale Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] module"] +#[doc(alias = "CLKSCALE")] +pub type Clkscale = crate::Reg; +#[doc = "Clock Scale Register"] +pub mod clkscale; +#[doc = "RXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxstatus`] module"] +#[doc(alias = "RXSTATUS")] +pub type Rxstatus = crate::Reg; +#[doc = "Status Register"] +pub mod rxstatus; +#[doc = "TXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txstatus`] module"] +#[doc(alias = "TXSTATUS")] +pub type Txstatus = crate::Reg; +#[doc = "Status Register"] +pub mod txstatus; +#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "TXBREAK (w) register accessor: Break Transmit Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbreak::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbreak`] module"] +#[doc(alias = "TXBREAK")] +pub type Txbreak = crate::Reg; +#[doc = "Break Transmit Register"] +pub mod txbreak; +#[doc = "ADDR9 (rw) register accessor: Address9 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9`] module"] +#[doc(alias = "ADDR9")] +pub type Addr9 = crate::Reg; +#[doc = "Address9 Register"] +pub mod addr9; +#[doc = "ADDR9MASK (rw) register accessor: Address9 Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9mask`] module"] +#[doc(alias = "ADDR9MASK")] +pub type Addr9mask = crate::Reg; +#[doc = "Address9 Mask Register"] +pub mod addr9mask; +#[doc = "IRQ_ENB (rw) register accessor: IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "IRQ Enable Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "RXFIFORTSTRG (rw) register accessor: Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifortstrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifortstrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifortstrg`] module"] +#[doc(alias = "RXFIFORTSTRG")] +pub type Rxfifortstrg = crate::Reg; +#[doc = "Rx FIFO RTS Trigger Level"] +pub mod rxfifortstrg; +#[doc = "STATE (r) register accessor: Internal STATE of UART Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +#[doc(alias = "STATE")] +pub type State = crate::Reg; +#[doc = "Internal STATE of UART Controller"] +pub mod state; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va108xx/va108xx/src/uarta/addr9.rs b/va108xx/va108xx/src/uarta/addr9.rs new file mode 100644 index 0000000..56b06b3 --- /dev/null +++ b/va108xx/va108xx/src/uarta/addr9.rs @@ -0,0 +1,24 @@ +#[doc = "Register `ADDR9` reader"] +pub type R = crate::R; +#[doc = "Register `ADDR9` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Address9 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Addr9Spec; +impl crate::RegisterSpec for Addr9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`addr9::R`](R) reader structure"] +impl crate::Readable for Addr9Spec {} +#[doc = "`write(|w| ..)` method takes [`addr9::W`](W) writer structure"] +impl crate::Writable for Addr9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADDR9 to value 0"] +impl crate::Resettable for Addr9Spec {} diff --git a/va108xx/va108xx/src/uarta/addr9mask.rs b/va108xx/va108xx/src/uarta/addr9mask.rs new file mode 100644 index 0000000..4b47c5c --- /dev/null +++ b/va108xx/va108xx/src/uarta/addr9mask.rs @@ -0,0 +1,24 @@ +#[doc = "Register `ADDR9MASK` reader"] +pub type R = crate::R; +#[doc = "Register `ADDR9MASK` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Address9 Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Addr9maskSpec; +impl crate::RegisterSpec for Addr9maskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`addr9mask::R`](R) reader structure"] +impl crate::Readable for Addr9maskSpec {} +#[doc = "`write(|w| ..)` method takes [`addr9mask::W`](W) writer structure"] +impl crate::Writable for Addr9maskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADDR9MASK to value 0"] +impl crate::Resettable for Addr9maskSpec {} diff --git a/va108xx/va108xx/src/uarta/clkscale.rs b/va108xx/va108xx/src/uarta/clkscale.rs new file mode 100644 index 0000000..2b5b7af --- /dev/null +++ b/va108xx/va108xx/src/uarta/clkscale.rs @@ -0,0 +1,56 @@ +#[doc = "Register `CLKSCALE` reader"] +pub type R = crate::R; +#[doc = "Register `CLKSCALE` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional Divide (64ths)"] +pub type FracR = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional Divide (64ths)"] +pub type FracW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `INT` reader - Integer Divide"] +pub type IntR = crate::FieldReader; +#[doc = "Field `INT` writer - Integer Divide"] +pub type IntW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `RESET` writer - Reset Baud Counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - Fractional Divide (64ths)"] + #[inline(always)] + pub fn frac(&self) -> FracR { + FracR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Integer Divide"] + #[inline(always)] + pub fn int(&self) -> IntR { + IntR::new((self.bits >> 6) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bits 0:5 - Fractional Divide (64ths)"] + #[inline(always)] + pub fn frac(&mut self) -> FracW<'_, ClkscaleSpec> { + FracW::new(self, 0) + } + #[doc = "Bits 6:23 - Integer Divide"] + #[inline(always)] + pub fn int(&mut self) -> IntW<'_, ClkscaleSpec> { + IntW::new(self, 6) + } + #[doc = "Bit 31 - Reset Baud Counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW<'_, ClkscaleSpec> { + ResetW::new(self, 31) + } +} +#[doc = "Clock Scale Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkscaleSpec; +impl crate::RegisterSpec for ClkscaleSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkscale::R`](R) reader structure"] +impl crate::Readable for ClkscaleSpec {} +#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"] +impl crate::Writable for ClkscaleSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKSCALE to value 0"] +impl crate::Resettable for ClkscaleSpec {} diff --git a/va108xx/va108xx/src/uarta/ctrl.rs b/va108xx/va108xx/src/uarta/ctrl.rs new file mode 100644 index 0000000..117e6a5 --- /dev/null +++ b/va108xx/va108xx/src/uarta/ctrl.rs @@ -0,0 +1,175 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PAREN` reader - Parity Enable"] +pub type ParenR = crate::BitReader; +#[doc = "Field `PAREN` writer - Parity Enable"] +pub type ParenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAREVEN` reader - Parity Even/Odd(1/0)"] +pub type ParevenR = crate::BitReader; +#[doc = "Field `PAREVEN` writer - Parity Even/Odd(1/0)"] +pub type ParevenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARSTK` reader - Parity Sticky"] +pub type ParstkR = crate::BitReader; +#[doc = "Field `PARSTK` writer - Parity Sticky"] +pub type ParstkW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STOPBITS` reader - Stop Bits 1/2(0/1)"] +pub type StopbitsR = crate::BitReader; +#[doc = "Field `STOPBITS` writer - Stop Bits 1/2(0/1)"] +pub type StopbitsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WORDSIZE` reader - Word Size in Bits 5/6/7/8(00/01/10/11)"] +pub type WordsizeR = crate::FieldReader; +#[doc = "Field `WORDSIZE` writer - Word Size in Bits 5/6/7/8(00/01/10/11)"] +pub type WordsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LOOPBACK` reader - Loopback Enable"] +pub type LoopbackR = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Loopback Enable"] +pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACKBLK` reader - Loopback Block"] +pub type LoopbackblkR = crate::BitReader; +#[doc = "Field `LOOPBACKBLK` writer - Loopback Block"] +pub type LoopbackblkW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOCTS` reader - Enable Auto CTS mode"] +pub type AutoctsR = crate::BitReader; +#[doc = "Field `AUTOCTS` writer - Enable Auto CTS mode"] +pub type AutoctsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEFRTS` reader - Default RTSn value"] +pub type DefrtsR = crate::BitReader; +#[doc = "Field `DEFRTS` writer - Default RTSn value"] +pub type DefrtsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTORTS` reader - Enable Auto RTS mode"] +pub type AutortsR = crate::BitReader; +#[doc = "Field `AUTORTS` writer - Enable Auto RTS mode"] +pub type AutortsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BAUD8` reader - Enable BAUD8 mode"] +pub type Baud8R = crate::BitReader; +#[doc = "Field `BAUD8` writer - Enable BAUD8 mode"] +pub type Baud8W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Parity Enable"] + #[inline(always)] + pub fn paren(&self) -> ParenR { + ParenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Parity Even/Odd(1/0)"] + #[inline(always)] + pub fn pareven(&self) -> ParevenR { + ParevenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Parity Sticky"] + #[inline(always)] + pub fn parstk(&self) -> ParstkR { + ParstkR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Stop Bits 1/2(0/1)"] + #[inline(always)] + pub fn stopbits(&self) -> StopbitsR { + StopbitsR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"] + #[inline(always)] + pub fn wordsize(&self) -> WordsizeR { + WordsizeR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Loopback Enable"] + #[inline(always)] + pub fn loopback(&self) -> LoopbackR { + LoopbackR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Loopback Block"] + #[inline(always)] + pub fn loopbackblk(&self) -> LoopbackblkR { + LoopbackblkR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable Auto CTS mode"] + #[inline(always)] + pub fn autocts(&self) -> AutoctsR { + AutoctsR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Default RTSn value"] + #[inline(always)] + pub fn defrts(&self) -> DefrtsR { + DefrtsR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable Auto RTS mode"] + #[inline(always)] + pub fn autorts(&self) -> AutortsR { + AutortsR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable BAUD8 mode"] + #[inline(always)] + pub fn baud8(&self) -> Baud8R { + Baud8R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Enable"] + #[inline(always)] + pub fn paren(&mut self) -> ParenW<'_, CtrlSpec> { + ParenW::new(self, 0) + } + #[doc = "Bit 1 - Parity Even/Odd(1/0)"] + #[inline(always)] + pub fn pareven(&mut self) -> ParevenW<'_, CtrlSpec> { + ParevenW::new(self, 1) + } + #[doc = "Bit 2 - Parity Sticky"] + #[inline(always)] + pub fn parstk(&mut self) -> ParstkW<'_, CtrlSpec> { + ParstkW::new(self, 2) + } + #[doc = "Bit 3 - Stop Bits 1/2(0/1)"] + #[inline(always)] + pub fn stopbits(&mut self) -> StopbitsW<'_, CtrlSpec> { + StopbitsW::new(self, 3) + } + #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"] + #[inline(always)] + pub fn wordsize(&mut self) -> WordsizeW<'_, CtrlSpec> { + WordsizeW::new(self, 4) + } + #[doc = "Bit 6 - Loopback Enable"] + #[inline(always)] + pub fn loopback(&mut self) -> LoopbackW<'_, CtrlSpec> { + LoopbackW::new(self, 6) + } + #[doc = "Bit 7 - Loopback Block"] + #[inline(always)] + pub fn loopbackblk(&mut self) -> LoopbackblkW<'_, CtrlSpec> { + LoopbackblkW::new(self, 7) + } + #[doc = "Bit 8 - Enable Auto CTS mode"] + #[inline(always)] + pub fn autocts(&mut self) -> AutoctsW<'_, CtrlSpec> { + AutoctsW::new(self, 8) + } + #[doc = "Bit 9 - Default RTSn value"] + #[inline(always)] + pub fn defrts(&mut self) -> DefrtsW<'_, CtrlSpec> { + DefrtsW::new(self, 9) + } + #[doc = "Bit 10 - Enable Auto RTS mode"] + #[inline(always)] + pub fn autorts(&mut self) -> AutortsW<'_, CtrlSpec> { + AutortsW::new(self, 10) + } + #[doc = "Bit 11 - Enable BAUD8 mode"] + #[inline(always)] + pub fn baud8(&mut self) -> Baud8W<'_, CtrlSpec> { + Baud8W::new(self, 11) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/va108xx/va108xx/src/uarta/data.rs b/va108xx/va108xx/src/uarta/data.rs new file mode 100644 index 0000000..e14fd45 --- /dev/null +++ b/va108xx/va108xx/src/uarta/data.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data In/Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec {} diff --git a/va108xx/va108xx/src/uarta/enable.rs b/va108xx/va108xx/src/uarta/enable.rs new file mode 100644 index 0000000..ca6957e --- /dev/null +++ b/va108xx/va108xx/src/uarta/enable.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `RXENABLE` reader - Rx Enable"] +pub type RxenableR = crate::BitReader; +#[doc = "Field `RXENABLE` writer - Rx Enable"] +pub type RxenableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXENABLE` reader - Tx Enable"] +pub type TxenableR = crate::BitReader; +#[doc = "Field `TXENABLE` writer - Tx Enable"] +pub type TxenableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Rx Enable"] + #[inline(always)] + pub fn rxenable(&self) -> RxenableR { + RxenableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tx Enable"] + #[inline(always)] + pub fn txenable(&self) -> TxenableR { + TxenableR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx Enable"] + #[inline(always)] + pub fn rxenable(&mut self) -> RxenableW<'_, EnableSpec> { + RxenableW::new(self, 0) + } + #[doc = "Bit 1 - Tx Enable"] + #[inline(always)] + pub fn txenable(&mut self) -> TxenableW<'_, EnableSpec> { + TxenableW::new(self, 1) + } +} +#[doc = "Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EnableSpec; +impl crate::RegisterSpec for EnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`enable::R`](R) reader structure"] +impl crate::Readable for EnableSpec {} +#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"] +impl crate::Writable for EnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for EnableSpec {} diff --git a/va108xx/va108xx/src/uarta/fifo_clr.rs b/va108xx/va108xx/src/uarta/fifo_clr.rs new file mode 100644 index 0000000..7fa5438 --- /dev/null +++ b/va108xx/va108xx/src/uarta/fifo_clr.rs @@ -0,0 +1,43 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXSTS` writer - Clear Rx Status"] +pub type RxstsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSTS` writer - Clear Tx Status"] +pub type TxstsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx Status"] + #[inline(always)] + pub fn rxsts(&mut self) -> RxstsW<'_, FifoClrSpec> { + RxstsW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx Status"] + #[inline(always)] + pub fn txsts(&mut self) -> TxstsW<'_, FifoClrSpec> { + TxstsW::new(self, 1) + } + #[doc = "Bit 2 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> { + RxfifoW::new(self, 2) + } + #[doc = "Bit 3 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> { + TxfifoW::new(self, 3) + } +} +#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec {} diff --git a/va108xx/va108xx/src/uarta/irq_enb.rs b/va108xx/va108xx/src/uarta/irq_enb.rs new file mode 100644 index 0000000..3965a8c --- /dev/null +++ b/va108xx/va108xx/src/uarta/irq_enb.rs @@ -0,0 +1,119 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `IRQ_RX` reader - RX Interrupt"] +pub type IrqRxR = crate::BitReader; +#[doc = "Field `IRQ_RX` writer - RX Interrupt"] +pub type IrqRxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_RX_STATUS` reader - RX Status Interrupt"] +pub type IrqRxStatusR = crate::BitReader; +#[doc = "Field `IRQ_RX_STATUS` writer - RX Status Interrupt"] +pub type IrqRxStatusW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_RX_TO` reader - RX Timeout Interrupt"] +pub type IrqRxToR = crate::BitReader; +#[doc = "Field `IRQ_RX_TO` writer - RX Timeout Interrupt"] +pub type IrqRxToW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX` reader - TX Interrupt"] +pub type IrqTxR = crate::BitReader; +#[doc = "Field `IRQ_TX` writer - TX Interrupt"] +pub type IrqTxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX_STATUS` reader - TX Status Interrupt"] +pub type IrqTxStatusR = crate::BitReader; +#[doc = "Field `IRQ_TX_STATUS` writer - TX Status Interrupt"] +pub type IrqTxStatusW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX_EMPTY` reader - TX Empty Interrupt"] +pub type IrqTxEmptyR = crate::BitReader; +#[doc = "Field `IRQ_TX_EMPTY` writer - TX Empty Interrupt"] +pub type IrqTxEmptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX_CTS` reader - TX CTS Change Interrupt"] +pub type IrqTxCtsR = crate::BitReader; +#[doc = "Field `IRQ_TX_CTS` writer - TX CTS Change Interrupt"] +pub type IrqTxCtsW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&self) -> IrqRxR { + IrqRxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&self) -> IrqRxStatusR { + IrqRxStatusR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&self) -> IrqRxToR { + IrqRxToR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&self) -> IrqTxR { + IrqTxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&self) -> IrqTxStatusR { + IrqTxStatusR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&self) -> IrqTxEmptyR { + IrqTxEmptyR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&self) -> IrqTxCtsR { + IrqTxCtsR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&mut self) -> IrqRxW<'_, IrqEnbSpec> { + IrqRxW::new(self, 0) + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&mut self) -> IrqRxStatusW<'_, IrqEnbSpec> { + IrqRxStatusW::new(self, 1) + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&mut self) -> IrqRxToW<'_, IrqEnbSpec> { + IrqRxToW::new(self, 2) + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&mut self) -> IrqTxW<'_, IrqEnbSpec> { + IrqTxW::new(self, 4) + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&mut self) -> IrqTxStatusW<'_, IrqEnbSpec> { + IrqTxStatusW::new(self, 5) + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&mut self) -> IrqTxEmptyW<'_, IrqEnbSpec> { + IrqTxEmptyW::new(self, 6) + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&mut self) -> IrqTxCtsW<'_, IrqEnbSpec> { + IrqTxCtsW::new(self, 7) + } +} +#[doc = "IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va108xx/va108xx/src/uarta/perid.rs b/va108xx/va108xx/src/uarta/perid.rs new file mode 100644 index 0000000..68e90c4 --- /dev/null +++ b/va108xx/va108xx/src/uarta/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0012_07e1"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0012_07e1; +} diff --git a/va108xx/va108xx/src/uarta/rxfifoirqtrg.rs b/va108xx/va108xx/src/uarta/rxfifoirqtrg.rs new file mode 100644 index 0000000..e38d450 --- /dev/null +++ b/va108xx/va108xx/src/uarta/rxfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RxfifoirqtrgSpec {} diff --git a/va108xx/va108xx/src/uarta/rxfifortstrg.rs b/va108xx/va108xx/src/uarta/rxfifortstrg.rs new file mode 100644 index 0000000..370a154 --- /dev/null +++ b/va108xx/va108xx/src/uarta/rxfifortstrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RXFIFORTSTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFORTSTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifortstrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifortstrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifortstrgSpec; +impl crate::RegisterSpec for RxfifortstrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifortstrg::R`](R) reader structure"] +impl crate::Readable for RxfifortstrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifortstrg::W`](W) writer structure"] +impl crate::Writable for RxfifortstrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFIFORTSTRG to value 0"] +impl crate::Resettable for RxfifortstrgSpec {} diff --git a/va108xx/va108xx/src/uarta/rxstatus.rs b/va108xx/va108xx/src/uarta/rxstatus.rs new file mode 100644 index 0000000..1b0ab58 --- /dev/null +++ b/va108xx/va108xx/src/uarta/rxstatus.rs @@ -0,0 +1,90 @@ +#[doc = "Register `RXSTATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RDAVL` reader - Read Data Available"] +pub type RdavlR = crate::BitReader; +#[doc = "Field `RDNFULL` reader - Read Fifo NOT Full"] +pub type RdnfullR = crate::BitReader; +#[doc = "Field `RXBUSY` reader - RX Busy Receiving"] +pub type RxbusyR = crate::BitReader; +#[doc = "Field `RXTO` reader - RX Receive Timeout"] +pub type RxtoR = crate::BitReader; +#[doc = "Field `RXOVR` reader - Read Fifo Overflow"] +pub type RxovrR = crate::BitReader; +#[doc = "Field `RXFRM` reader - RX Framing Error"] +pub type RxfrmR = crate::BitReader; +#[doc = "Field `RXPAR` reader - RX Parity Error"] +pub type RxparR = crate::BitReader; +#[doc = "Field `RXBRK` reader - RX Break Error"] +pub type RxbrkR = crate::BitReader; +#[doc = "Field `RXBUSYBRK` reader - RX Busy Receiving Break"] +pub type RxbusybrkR = crate::BitReader; +#[doc = "Field `RXADDR9` reader - Address Match for 9 bit mode"] +pub type Rxaddr9R = crate::BitReader; +#[doc = "Field `RXRTSN` reader - RX RTSn Output Value"] +pub type RxrtsnR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read Data Available"] + #[inline(always)] + pub fn rdavl(&self) -> RdavlR { + RdavlR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Read Fifo NOT Full"] + #[inline(always)] + pub fn rdnfull(&self) -> RdnfullR { + RdnfullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Busy Receiving"] + #[inline(always)] + pub fn rxbusy(&self) -> RxbusyR { + RxbusyR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RX Receive Timeout"] + #[inline(always)] + pub fn rxto(&self) -> RxtoR { + RxtoR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Read Fifo Overflow"] + #[inline(always)] + pub fn rxovr(&self) -> RxovrR { + RxovrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RX Framing Error"] + #[inline(always)] + pub fn rxfrm(&self) -> RxfrmR { + RxfrmR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RX Parity Error"] + #[inline(always)] + pub fn rxpar(&self) -> RxparR { + RxparR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - RX Break Error"] + #[inline(always)] + pub fn rxbrk(&self) -> RxbrkR { + RxbrkR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX Busy Receiving Break"] + #[inline(always)] + pub fn rxbusybrk(&self) -> RxbusybrkR { + RxbusybrkR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Address Match for 9 bit mode"] + #[inline(always)] + pub fn rxaddr9(&self) -> Rxaddr9R { + Rxaddr9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 15 - RX RTSn Output Value"] + #[inline(always)] + pub fn rxrtsn(&self) -> RxrtsnR { + RxrtsnR::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxstatusSpec; +impl crate::RegisterSpec for RxstatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxstatus::R`](R) reader structure"] +impl crate::Readable for RxstatusSpec {} +#[doc = "`reset()` method sets RXSTATUS to value 0"] +impl crate::Resettable for RxstatusSpec {} diff --git a/va108xx/va108xx/src/uarta/state.rs b/va108xx/va108xx/src/uarta/state.rs new file mode 100644 index 0000000..f8dd56a --- /dev/null +++ b/va108xx/va108xx/src/uarta/state.rs @@ -0,0 +1,17 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of UART Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StateSpec; +impl crate::RegisterSpec for StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for StateSpec {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for StateSpec {} diff --git a/va108xx/va108xx/src/uarta/txbreak.rs b/va108xx/va108xx/src/uarta/txbreak.rs new file mode 100644 index 0000000..d943200 --- /dev/null +++ b/va108xx/va108xx/src/uarta/txbreak.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXBREAK` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W {} +#[doc = "Break Transmit Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbreak::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxbreakSpec; +impl crate::RegisterSpec for TxbreakSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`txbreak::W`](W) writer structure"] +impl crate::Writable for TxbreakSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TXBREAK to value 0"] +impl crate::Resettable for TxbreakSpec {} diff --git a/va108xx/va108xx/src/uarta/txfifoirqtrg.rs b/va108xx/va108xx/src/uarta/txfifoirqtrg.rs new file mode 100644 index 0000000..ea0e7d3 --- /dev/null +++ b/va108xx/va108xx/src/uarta/txfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TxfifoirqtrgSpec {} diff --git a/va108xx/va108xx/src/uarta/txstatus.rs b/va108xx/va108xx/src/uarta/txstatus.rs new file mode 100644 index 0000000..1ad3856 --- /dev/null +++ b/va108xx/va108xx/src/uarta/txstatus.rs @@ -0,0 +1,48 @@ +#[doc = "Register `TXSTATUS` reader"] +pub type R = crate::R; +#[doc = "Field `WRRDY` reader - Write Fifo NOT Full"] +pub type WrrdyR = crate::BitReader; +#[doc = "Field `WRBUSY` reader - Write Fifo Full"] +pub type WrbusyR = crate::BitReader; +#[doc = "Field `TXBUSY` reader - TX Busy Transmitting"] +pub type TxbusyR = crate::BitReader; +#[doc = "Field `WRLOST` reader - Write Data Lost (Fifo Overflow)"] +pub type WrlostR = crate::BitReader; +#[doc = "Field `TXCTSN` reader - TX CTSn Input Value"] +pub type TxctsnR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Write Fifo NOT Full"] + #[inline(always)] + pub fn wrrdy(&self) -> WrrdyR { + WrrdyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write Fifo Full"] + #[inline(always)] + pub fn wrbusy(&self) -> WrbusyR { + WrbusyR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - TX Busy Transmitting"] + #[inline(always)] + pub fn txbusy(&self) -> TxbusyR { + TxbusyR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write Data Lost (Fifo Overflow)"] + #[inline(always)] + pub fn wrlost(&self) -> WrlostR { + WrlostR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 15 - TX CTSn Input Value"] + #[inline(always)] + pub fn txctsn(&self) -> TxctsnR { + TxctsnR::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxstatusSpec; +impl crate::RegisterSpec for TxstatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txstatus::R`](R) reader structure"] +impl crate::Readable for TxstatusSpec {} +#[doc = "`reset()` method sets TXSTATUS to value 0"] +impl crate::Resettable for TxstatusSpec {} diff --git a/va108xx/va108xx/src/utility.rs b/va108xx/va108xx/src/utility.rs new file mode 100644 index 0000000..3d1d455 --- /dev/null +++ b/va108xx/va108xx/src/utility.rs @@ -0,0 +1,161 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + synd_data0: SyndData0, + synd_data1: SyndData1, + synd_synd: SyndSynd, + synd_enc_32: SyndEnc32, + synd_check_32_data: SyndCheck32Data, + synd_check_32_synd: SyndCheck32Synd, + synd_enc_64: SyndEnc64, + synd_check_64_data0: SyndCheck64Data0, + synd_check_64_data1: SyndCheck64Data1, + synd_check_64_synd: SyndCheck64Synd, + synd_enc_32_52: SyndEnc32_52, + synd_check_32_52_data: SyndCheck32_52Data, + synd_check_32_52_synd: SyndCheck32_52Synd, + _reserved13: [u8; 0x0fc8], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Synd Data 0 Register"] + #[inline(always)] + pub const fn synd_data0(&self) -> &SyndData0 { + &self.synd_data0 + } + #[doc = "0x04 - Synd Data 1 Register"] + #[inline(always)] + pub const fn synd_data1(&self) -> &SyndData1 { + &self.synd_data1 + } + #[doc = "0x08 - Synd Parity Register"] + #[inline(always)] + pub const fn synd_synd(&self) -> &SyndSynd { + &self.synd_synd + } + #[doc = "0x0c - Synd 32 bit Encoded Syndrome"] + #[inline(always)] + pub const fn synd_enc_32(&self) -> &SyndEnc32 { + &self.synd_enc_32 + } + #[doc = "0x10 - Synd 32 bit Corrected Data"] + #[inline(always)] + pub const fn synd_check_32_data(&self) -> &SyndCheck32Data { + &self.synd_check_32_data + } + #[doc = "0x14 - Synd 32 bit Corrected Syndrome and Status"] + #[inline(always)] + pub const fn synd_check_32_synd(&self) -> &SyndCheck32Synd { + &self.synd_check_32_synd + } + #[doc = "0x18 - Synd 64 bit Encoded Syndrome"] + #[inline(always)] + pub const fn synd_enc_64(&self) -> &SyndEnc64 { + &self.synd_enc_64 + } + #[doc = "0x1c - Synd 64 bit Corrected Data 0"] + #[inline(always)] + pub const fn synd_check_64_data0(&self) -> &SyndCheck64Data0 { + &self.synd_check_64_data0 + } + #[doc = "0x20 - Synd 64 bit Corrected Data 1"] + #[inline(always)] + pub const fn synd_check_64_data1(&self) -> &SyndCheck64Data1 { + &self.synd_check_64_data1 + } + #[doc = "0x24 - Synd 64 bit Corrected Parity and Status"] + #[inline(always)] + pub const fn synd_check_64_synd(&self) -> &SyndCheck64Synd { + &self.synd_check_64_synd + } + #[doc = "0x28 - Synd 32/52 bit Encoded Syndrome"] + #[inline(always)] + pub const fn synd_enc_32_52(&self) -> &SyndEnc32_52 { + &self.synd_enc_32_52 + } + #[doc = "0x2c - Synd 32/52 bit Corrected Data"] + #[inline(always)] + pub const fn synd_check_32_52_data(&self) -> &SyndCheck32_52Data { + &self.synd_check_32_52_data + } + #[doc = "0x30 - Synd 32/52 bit Corrected Syndrome and Status"] + #[inline(always)] + pub const fn synd_check_32_52_synd(&self) -> &SyndCheck32_52Synd { + &self.synd_check_32_52_synd + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "SYND_DATA0 (rw) register accessor: Synd Data 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_data0`] module"] +#[doc(alias = "SYND_DATA0")] +pub type SyndData0 = crate::Reg; +#[doc = "Synd Data 0 Register"] +pub mod synd_data0; +#[doc = "SYND_DATA1 (rw) register accessor: Synd Data 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_data1`] module"] +#[doc(alias = "SYND_DATA1")] +pub type SyndData1 = crate::Reg; +#[doc = "Synd Data 1 Register"] +pub mod synd_data1; +#[doc = "SYND_SYND (rw) register accessor: Synd Parity Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_synd`] module"] +#[doc(alias = "SYND_SYND")] +pub type SyndSynd = crate::Reg; +#[doc = "Synd Parity Register"] +pub mod synd_synd; +#[doc = "SYND_ENC_32 (r) register accessor: Synd 32 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32`] module"] +#[doc(alias = "SYND_ENC_32")] +pub type SyndEnc32 = crate::Reg; +#[doc = "Synd 32 bit Encoded Syndrome"] +pub mod synd_enc_32; +#[doc = "SYND_CHECK_32_DATA (r) register accessor: Synd 32 bit Corrected Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_data`] module"] +#[doc(alias = "SYND_CHECK_32_DATA")] +pub type SyndCheck32Data = crate::Reg; +#[doc = "Synd 32 bit Corrected Data"] +pub mod synd_check_32_data; +#[doc = "SYND_CHECK_32_SYND (r) register accessor: Synd 32 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_synd`] module"] +#[doc(alias = "SYND_CHECK_32_SYND")] +pub type SyndCheck32Synd = crate::Reg; +#[doc = "Synd 32 bit Corrected Syndrome and Status"] +pub mod synd_check_32_synd; +#[doc = "SYND_ENC_64 (r) register accessor: Synd 64 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_64::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_64`] module"] +#[doc(alias = "SYND_ENC_64")] +pub type SyndEnc64 = crate::Reg; +#[doc = "Synd 64 bit Encoded Syndrome"] +pub mod synd_enc_64; +#[doc = "SYND_CHECK_64_DATA0 (r) register accessor: Synd 64 bit Corrected Data 0\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_64_data0`] module"] +#[doc(alias = "SYND_CHECK_64_DATA0")] +pub type SyndCheck64Data0 = crate::Reg; +#[doc = "Synd 64 bit Corrected Data 0"] +pub mod synd_check_64_data0; +#[doc = "SYND_CHECK_64_DATA1 (r) register accessor: Synd 64 bit Corrected Data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_64_data1`] module"] +#[doc(alias = "SYND_CHECK_64_DATA1")] +pub type SyndCheck64Data1 = crate::Reg; +#[doc = "Synd 64 bit Corrected Data 1"] +pub mod synd_check_64_data1; +#[doc = "SYND_CHECK_64_SYND (r) register accessor: Synd 64 bit Corrected Parity and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_64_synd`] module"] +#[doc(alias = "SYND_CHECK_64_SYND")] +pub type SyndCheck64Synd = crate::Reg; +#[doc = "Synd 64 bit Corrected Parity and Status"] +pub mod synd_check_64_synd; +#[doc = "SYND_ENC_32_52 (r) register accessor: Synd 32/52 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32_52::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32_52`] module"] +#[doc(alias = "SYND_ENC_32_52")] +pub type SyndEnc32_52 = crate::Reg; +#[doc = "Synd 32/52 bit Encoded Syndrome"] +pub mod synd_enc_32_52; +#[doc = "SYND_CHECK_32_52_DATA (r) register accessor: Synd 32/52 bit Corrected Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_data`] module"] +#[doc(alias = "SYND_CHECK_32_52_DATA")] +pub type SyndCheck32_52Data = crate::Reg; +#[doc = "Synd 32/52 bit Corrected Data"] +pub mod synd_check_32_52_data; +#[doc = "SYND_CHECK_32_52_SYND (r) register accessor: Synd 32/52 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_synd`] module"] +#[doc(alias = "SYND_CHECK_32_52_SYND")] +pub type SyndCheck32_52Synd = crate::Reg; +#[doc = "Synd 32/52 bit Corrected Syndrome and Status"] +pub mod synd_check_32_52_synd; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va108xx/va108xx/src/utility/perid.rs b/va108xx/va108xx/src/utility/perid.rs new file mode 100644 index 0000000..170c08a --- /dev/null +++ b/va108xx/va108xx/src/utility/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0082_07e1"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0082_07e1; +} diff --git a/va108xx/va108xx/src/utility/synd_check_32_52_data.rs b/va108xx/va108xx/src/utility/synd_check_32_52_data.rs new file mode 100644 index 0000000..de7cad8 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_check_32_52_data.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_CHECK_32_52_DATA` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 32/52 bit Corrected Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_52DataSpec; +impl crate::RegisterSpec for SyndCheck32_52DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_52_data::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_52DataSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_52_DATA to value 0"] +impl crate::Resettable for SyndCheck32_52DataSpec {} diff --git a/va108xx/va108xx/src/utility/synd_check_32_52_synd.rs b/va108xx/va108xx/src/utility/synd_check_32_52_synd.rs new file mode 100644 index 0000000..8f290e7 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_check_32_52_synd.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_CHECK_32_52_SYND` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 32/52 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_52SyndSpec; +impl crate::RegisterSpec for SyndCheck32_52SyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_52_synd::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_52SyndSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_52_SYND to value 0"] +impl crate::Resettable for SyndCheck32_52SyndSpec {} diff --git a/va108xx/va108xx/src/utility/synd_check_32_data.rs b/va108xx/va108xx/src/utility/synd_check_32_data.rs new file mode 100644 index 0000000..019e818 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_check_32_data.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_CHECK_32_DATA` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 32 bit Corrected Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32DataSpec; +impl crate::RegisterSpec for SyndCheck32DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_data::R`](R) reader structure"] +impl crate::Readable for SyndCheck32DataSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_DATA to value 0"] +impl crate::Resettable for SyndCheck32DataSpec {} diff --git a/va108xx/va108xx/src/utility/synd_check_32_synd.rs b/va108xx/va108xx/src/utility/synd_check_32_synd.rs new file mode 100644 index 0000000..3b213a5 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_check_32_synd.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_CHECK_32_SYND` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 32 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32SyndSpec; +impl crate::RegisterSpec for SyndCheck32SyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_synd::R`](R) reader structure"] +impl crate::Readable for SyndCheck32SyndSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_SYND to value 0"] +impl crate::Resettable for SyndCheck32SyndSpec {} diff --git a/va108xx/va108xx/src/utility/synd_check_64_data0.rs b/va108xx/va108xx/src/utility/synd_check_64_data0.rs new file mode 100644 index 0000000..dccf105 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_check_64_data0.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_CHECK_64_DATA0` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 64 bit Corrected Data 0\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck64Data0Spec; +impl crate::RegisterSpec for SyndCheck64Data0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_64_data0::R`](R) reader structure"] +impl crate::Readable for SyndCheck64Data0Spec {} +#[doc = "`reset()` method sets SYND_CHECK_64_DATA0 to value 0"] +impl crate::Resettable for SyndCheck64Data0Spec {} diff --git a/va108xx/va108xx/src/utility/synd_check_64_data1.rs b/va108xx/va108xx/src/utility/synd_check_64_data1.rs new file mode 100644 index 0000000..e034302 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_check_64_data1.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_CHECK_64_DATA1` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 64 bit Corrected Data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck64Data1Spec; +impl crate::RegisterSpec for SyndCheck64Data1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_64_data1::R`](R) reader structure"] +impl crate::Readable for SyndCheck64Data1Spec {} +#[doc = "`reset()` method sets SYND_CHECK_64_DATA1 to value 0"] +impl crate::Resettable for SyndCheck64Data1Spec {} diff --git a/va108xx/va108xx/src/utility/synd_check_64_synd.rs b/va108xx/va108xx/src/utility/synd_check_64_synd.rs new file mode 100644 index 0000000..a61d419 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_check_64_synd.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_CHECK_64_SYND` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 64 bit Corrected Parity and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck64SyndSpec; +impl crate::RegisterSpec for SyndCheck64SyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_64_synd::R`](R) reader structure"] +impl crate::Readable for SyndCheck64SyndSpec {} +#[doc = "`reset()` method sets SYND_CHECK_64_SYND to value 0"] +impl crate::Resettable for SyndCheck64SyndSpec {} diff --git a/va108xx/va108xx/src/utility/synd_data0.rs b/va108xx/va108xx/src/utility/synd_data0.rs new file mode 100644 index 0000000..596ea2e --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_data0.rs @@ -0,0 +1,24 @@ +#[doc = "Register `SYND_DATA0` reader"] +pub type R = crate::R; +#[doc = "Register `SYND_DATA0` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Synd Data 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndData0Spec; +impl crate::RegisterSpec for SyndData0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_data0::R`](R) reader structure"] +impl crate::Readable for SyndData0Spec {} +#[doc = "`write(|w| ..)` method takes [`synd_data0::W`](W) writer structure"] +impl crate::Writable for SyndData0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SYND_DATA0 to value 0"] +impl crate::Resettable for SyndData0Spec {} diff --git a/va108xx/va108xx/src/utility/synd_data1.rs b/va108xx/va108xx/src/utility/synd_data1.rs new file mode 100644 index 0000000..6ef87cb --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_data1.rs @@ -0,0 +1,24 @@ +#[doc = "Register `SYND_DATA1` reader"] +pub type R = crate::R; +#[doc = "Register `SYND_DATA1` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Synd Data 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndData1Spec; +impl crate::RegisterSpec for SyndData1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_data1::R`](R) reader structure"] +impl crate::Readable for SyndData1Spec {} +#[doc = "`write(|w| ..)` method takes [`synd_data1::W`](W) writer structure"] +impl crate::Writable for SyndData1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SYND_DATA1 to value 0"] +impl crate::Resettable for SyndData1Spec {} diff --git a/va108xx/va108xx/src/utility/synd_enc_32.rs b/va108xx/va108xx/src/utility/synd_enc_32.rs new file mode 100644 index 0000000..4df3687 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_enc_32.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_ENC_32` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 32 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndEnc32Spec; +impl crate::RegisterSpec for SyndEnc32Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_enc_32::R`](R) reader structure"] +impl crate::Readable for SyndEnc32Spec {} +#[doc = "`reset()` method sets SYND_ENC_32 to value 0"] +impl crate::Resettable for SyndEnc32Spec {} diff --git a/va108xx/va108xx/src/utility/synd_enc_32_52.rs b/va108xx/va108xx/src/utility/synd_enc_32_52.rs new file mode 100644 index 0000000..46e3b05 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_enc_32_52.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_ENC_32_52` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 32/52 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32_52::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndEnc32_52Spec; +impl crate::RegisterSpec for SyndEnc32_52Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_enc_32_52::R`](R) reader structure"] +impl crate::Readable for SyndEnc32_52Spec {} +#[doc = "`reset()` method sets SYND_ENC_32_52 to value 0"] +impl crate::Resettable for SyndEnc32_52Spec {} diff --git a/va108xx/va108xx/src/utility/synd_enc_64.rs b/va108xx/va108xx/src/utility/synd_enc_64.rs new file mode 100644 index 0000000..d5aad72 --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_enc_64.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_ENC_64` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Synd 64 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_64::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndEnc64Spec; +impl crate::RegisterSpec for SyndEnc64Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_enc_64::R`](R) reader structure"] +impl crate::Readable for SyndEnc64Spec {} +#[doc = "`reset()` method sets SYND_ENC_64 to value 0"] +impl crate::Resettable for SyndEnc64Spec {} diff --git a/va108xx/va108xx/src/utility/synd_synd.rs b/va108xx/va108xx/src/utility/synd_synd.rs new file mode 100644 index 0000000..55c702c --- /dev/null +++ b/va108xx/va108xx/src/utility/synd_synd.rs @@ -0,0 +1,24 @@ +#[doc = "Register `SYND_SYND` reader"] +pub type R = crate::R; +#[doc = "Register `SYND_SYND` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Synd Parity Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_synd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_synd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndSyndSpec; +impl crate::RegisterSpec for SyndSyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_synd::R`](R) reader structure"] +impl crate::Readable for SyndSyndSpec {} +#[doc = "`write(|w| ..)` method takes [`synd_synd::W`](W) writer structure"] +impl crate::Writable for SyndSyndSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SYND_SYND to value 0"] +impl crate::Resettable for SyndSyndSpec {} diff --git a/va108xx/va108xx/svd/va108xx-orig.svd b/va108xx/va108xx/svd/va108xx-orig.svd new file mode 100644 index 0000000..3b956de --- /dev/null +++ b/va108xx/va108xx/svd/va108xx-orig.svd @@ -0,0 +1,2743 @@ + + + VORAGO TECHNOLOGIES + SST + va108xx + M0 + 1.1 + ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 50MHz + + VORAGO Technologies \n +\n +----------------------------------------------------------------------------\n + Copyright (c) 2013-2016 VORAGO Technologies\n +\n + BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n + AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n +\n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n + FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n + + + CM0 + r0p0 + little + false + false + 2 + false + + system_VA108xx + VOR_ + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + SYSCONFIG + 1.0 + System Configuration Peripheral + 0x40000000 + + 0 + 0x00001000 + registers + + + + RST_STAT + System Reset Status + 0x000 + read-write + 0x00000001 + + + POR + Power On Reset Status + [0:0] + + + EXTRST + External Reset Status + [1:1] + + + SYSRSTREQ + SYSRESETREQ Reset Status + [2:2] + + + LOOKUP + LOOKUP Reset Status + [3:3] + + + WATCHDOG + WATCHDOG Reset Status + [4:4] + + + MEMERR + Memory Error Reset Status + [5:5] + + + + + RST_CNTL_ROM + ROM Reset Control + 0x004 + 0x0000001F + + + RST_CNTL_RAM + RAM Reset Control + 0x008 + 0x0000001F + + + ROM_PROT + ROM Protection Configuration + 0x00C + 0x00000001 + + + WREN + ROM Write Enable Bit + [0:0] + + + + + ROM_SCRUB + ROM Scrub Period Configuration + 0x010 + read-write + 0x00000000 + + + VALUE + Counter divide value + [23:0] + + + RESET + Reset Counter + [31:31] + write-only + + oneToClear + + + + + + RAM_SCRUB + RAM Scrub Period Configuration + 0x014 + + + ROM_TRAP_ADDR + ROM Trap Address + 0x018 + 0x00000000 + + + ADDR + Trap Address Match Bits + [15:2] + + + ENABLE + Trap Enable Bit + [31:31] + + + + + ROM_TRAP_SYND + ROM Trap Syndrome + 0x01C + 0x00000000 + + + SYND + Trap Syndrom Bits + [19:0] + + + + + RAM_TRAP_ADDR + RAM Trap Address + 0x020 + + + RAM_TRAP_SYND + RAM Trap Syndrome + 0x024 + + + IRQ_ENB + Enable EDAC Error Interrupt Register + 0x028 + read-write + 0x00000000 + + + RAMSBE + RAM Single Bit Interrupt + [0:0] + + + RAMMBE + RAM Multi Bit Interrupt + [1:1] + + + ROMSBE + ROM Single Bit Interrupt + [2:2] + + + ROMMBE + ROM Multi Bit Interrupt + [3:3] + + + + + IRQ_RAW + Raw EDAC Error Interrupt Status + 0x02C + read-only + 0x00000000 + + + IRQ_END + Enabled EDAC Error Interrupt Status + 0x030 + read-only + 0x00000000 + + + IRQ_CLR + Clear EDAC Error Interrupt Status + 0x034 + write-only + 0x00000000 + + oneToClear + + + + RAM_SBE + Count of RAM EDAC Single Bit Errors + 0x038 + 0x00000000 + + + RAM_MBE + Count of RAM EDAC Multi Bit Errors + 0x03C + + + ROM_SBE + Count of ROM EDAC Single Bit Errors + 0x040 + + + ROM_MBE + Count of ROM EDAC Multi Bit Errors + 0x044 + + + IOCONFIG_CLKDIV0 + IO Configuration Clock Divider Register + 0x048 + read-only + 0x00000000 + + + 7 + 4 + 1-7 + IOCONFIG_CLKDIV%s + IO Configuration Clock Divider Register + 0x04C + 0x00000000 + + + ROM_RETRIES + ROM BOOT Retry count + 0x068 + read-only + 0x00000000 + + + REFRESH_CONFIG + Register Refresh Control + 0x06C + 0x00000000 + + + TIM_RESET + TIM Reset Control + 0x070 + 0xFFFFFFFF + + + TIM_CLK_ENABLE + TIM Enable Control + 0x074 + 0x00000000 + + + PERIPHERAL_RESET + Peripheral Reset Control + 0x078 + 0xFFFFFFFF + + + PERIPHERAL_CLK_ENABLE + Peripheral Enable Control + 0x07C + 0x00000000 + + + LOCKUP_RESET + Lockup Reset Configuration + 0x080 + 0x00000001 + + + LREN + Lockup Reset Enable Bit + [0:0] + + + + + EF_CONFIG + EFuse Config Register + 0xff0 + read-only + 0x00000000 + + + EF_ID + EFuse ID Register + 0xff4 + read-only + 0x00000000 + + + PROCID + Processor ID Register + 0xff8 + read-only + 0x040017e3 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x008007e1 + + + + + + + IRQSEL + 1.0 + Interrupt Selector Peripheral + 0x40001000 + + 0 + 0x00001000 + registers + + + OC0 + 0 + + + OC1 + 1 + + + OC2 + 2 + + + OC3 + 3 + + + OC4 + 4 + + + OC5 + 5 + + + OC6 + 6 + + + OC7 + 7 + + + OC8 + 8 + + + OC9 + 9 + + + OC10 + 10 + + + OC11 + 11 + + + OC12 + 12 + + + OC13 + 13 + + + OC14 + 14 + + + OC15 + 15 + + + OC16 + 16 + + + OC17 + 17 + + + OC18 + 18 + + + OC19 + 19 + + + OC20 + 20 + + + OC21 + 21 + + + OC22 + 22 + + + OC23 + 23 + + + OC24 + 24 + + + OC25 + 25 + + + OC26 + 26 + + + OC27 + 27 + + + OC28 + 28 + + + OC29 + 29 + + + OC30 + 30 + + + OC31 + 31 + + + + INT_RAM_SBE + Internal Memory RAM SBE Interrupt Redirect Selection + 0x01C0 + read-write + 0xFFFFFFFF + + + 32 + 4 + PORTA[%s] + PORTA Interrupt Redirect Selection + 0x000 + + + 32 + 4 + PORTB[%s] + PORTB Interrupt Redirect Selection + 0x080 + + + 32 + 4 + TIM[%s] + TIM Interrupt Redirect Selection + 0x100 + + + 4 + 4 + UART[%s] + UART Interrupt Redirect Selection + 0x180 + + + 4 + 4 + SPI[%s] + SPI Interrupt Redirect Selection + 0x190 + + + 4 + 4 + I2C_MS[%s] + Master I2C Interrupt Redirect Selection + 0x01a0 + + + 4 + 4 + I2C_SL[%s] + Slave I2C Interrupt Redirect Selection + 0x01B0 + + + INT_RAM_MBE + Internal Memory RAM MBE Interrupt Redirect Selection + 0x01C4 + + + INT_ROM_SBE + Internal Memory ROM SBE Interrupt Redirect Selection + 0x01C8 + + + INT_ROM_MBE + Internal Memory ROM MBE Interrupt Redirect Selection + 0x01CC + + + TXEV + Processor TXEV Interrupt Redirect Selection + 0x01D0 + + + NMI + NMI Status Register + 0x8f8 + read-only + 0x00000000 + + + ACTIVE + Active + [0:0] + + + + + RXEV + RXEV Status Register + 0x8f4 + + + WATCHDOG + WATCHDOG Status Register + 0x8f0 + + + MERESET + MERESET Status Register + 0x8ec + + + EDBGRQ + EDBGRQ Status Register + 0x8e8 + + + 32 + 4 + IRQS[%s] + Interrupt Status Register + 0x800 + + + PERID + Peripheral ID Register + 0xffc + 32 + read-only + 0x008007e1 + + + + + + + IOCONFIG + 1.0 + IO Pin Configuration Peripheral + 0x40002000 + + 0 + 0x00001000 + registers + + + + 32 + 4 + PORTA[%s] + PORTA Pin Configuration Register + 0x000 + 0x00000000 + + + FLTTYPE + Input Filter Selectoin + [2:0] + + + SYNC + Synchronize to system clock + 0 + + + DIRECT + Direct input, no synchronization + 1 + + + FILTER1 + Require 2 samples to have the same value + 2 + + + FILTER2 + Require 3 samples to have the same value + 3 + + + FILTER3 + Require 4 samples to have the same value + 4 + + + FILTER4 + Require 5 samples to have the same value + 5 + + + + + FLTCLK + Input Filter Clock Selection + [5:3] + + + INVINP + Input Invert Selection + [6:6] + + + IEWO + Input Enable While Output enabled + [7:7] + + + OPENDRN + Output Open Drain Mode + [8:8] + + + INVOUT + Output Invert Selection + [9:9] + + + PLEVEL + Internal Pull up/down level + [10:10] + + + PEN + Enable Internal Pull up/down + [11:11] + + + PWOA + Enable Pull when output active + [12:12] + + + FUNSEL + Pin Function Selection + [15:13] + + + IODIS + IO Pin Disable + [16:16] + + + + + PORTB[%s] + PORTB Pin Configuration Register + 0x0080 + 0x00000800 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x008207e1 + + + + + + + UTILITY + 1.0 + Utility Peripheral + 0x40003000 + + 0 + 0x00001000 + registers + + + + SYND_DATA0 + Synd Data 0 Register + 0x000 + 0x00000000 + + + SYND_DATA1 + Synd Data 1 Register + 0x004 + 0x00000000 + + + SYND_SYND + Synd Parity Register + 0x008 + 0x00000000 + + + SYND_ENC_32 + Synd 32 bit Encoded Syndrome + 0x00c + read-only + 0x00000000 + + + SYND_CHECK_32_DATA + Synd 32 bit Corrected Data + 0x010 + read-only + 0x00000000 + + + SYND_CHECK_32_SYND + Synd 32 bit Corrected Syndrome and Status + 0x014 + read-only + 0x00000000 + + + SYND_ENC_64 + Synd 64 bit Encoded Syndrome + 0x018 + read-only + 0x00000000 + + + SYND_CHECK_64_DATA0 + Synd 64 bit Corrected Data 0 + 0x01c + read-only + 0x00000000 + + + SYND_CHECK_64_DATA1 + Synd 64 bit Corrected Data 1 + 0x020 + read-only + 0x00000000 + + + SYND_CHECK_64_SYND + Synd 64 bit Corrected Parity and Status + 0x024 + read-only + 0x00000000 + + + SYND_ENC_32_52 + Synd 32/52 bit Encoded Syndrome + 0x028 + read-only + 0x00000000 + + + SYND_CHECK_32_52_DATA + Synd 32/52 bit Corrected Data + 0x02c + read-only + 0x00000000 + + + SYND_CHECK_32_52_SYND + Synd 32/52 bit Corrected Syndrome and Status + 0x030 + read-only + 0x00000000 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x008207e1 + + + + + + + PORTA + 1.0 + GPIO Peripheral + GPIO + 0x50000000 + + 0 + 0x00001000 + registers + + + + + DATAIN + Data In Register + 0x000 + read-only + 0x0000000 + + + 4 + 1 + DATAINBYTE[%s] + Data In Register by Byte + DATAIN + 0x000 + 8 + read-only + 0x0000000 + + + DATAINRAW + Data In Raw Register + 0x004 + 0x0000000 + + + DATAINRAWBYTE[%s] + Data In Raw Register by Byte + DATAINRAW + 0x004 + 0x0000000 + + + DATAOUT + Data Out Register + 0x008 + write-only + 0x0000000 + + + 4 + 1 + DATAOUTBYTE[%s] + Data Out Register by Byte + DATAOUT + 0x008 + 8 + write-only + 0x0000000 + + + DATAOUTRAW + Data Out Register + 0x00c + 0x0000000 + + + DATAOUTRAWBYTE[%s] + Data Out Register by Byte + DATAOUTRAW + 0x00c + 0x0000000 + + + SETOUT + Set Out Register + 0x010 + 0x0000000 + + + SETOUTBYTE[%s] + Set Out Register by Byte + SETOUT + 0x010 + 0x0000000 + + + CLROUT + Clear Out Register + 0x014 + 0x0000000 + + + CLROUTBYTE[%s] + Clear Out Register by Byte + CLROUT + 0x014 + 0x0000000 + + + TOGOUT + Toggle Out Register + 0x018 + 0x0000000 + + + TOGOUTBYTE[%s] + Toggle Out Register by Byte + TOGOUT + 0x018 + 0x0000000 + + + DATAMASK + Data mask Register + 0x01c + 0x0000000 + + + 4 + 1 + DATAMASKBYTE[%s] + Data Out Register by Byte + DATAMASK + 0x01c + 8 + 0x0000000 + + + DIR + Direction Register (1:Output, 0:Input) + 0x020 + 0x0000000 + + + DIRBYTE[%s] + Direction Register by Byte + DIR + 0x020 + 0x0000000 + + + PULSE + Pulse Mode Register + 0x024 + 0x0000000 + + + PULSEBYTE[%s] + Pulse Mode Register by Byte + PULSE + 0x024 + 0x0000000 + + + PULSEBASE + Pulse Base Value Register + 0x028 + 0x0000000 + + + PULSEBASEBYTE[%s] + Pulse Base Mode Register by Byte + PULSEBASE + 0x028 + 0x0000000 + + + DELAY1 + Delay1 Register + 0x02c + 0x0000000 + + + DELAY1BYTE[%s] + Delay1 Register by Byte + DELAY1 + 0x02c + 0x0000000 + + + DELAY2 + Delay2 Register + 0x030 + 32 + read-write + 0x0000000 + + + DELAY2BYTE[%s] + Delay2 Register by Byte + DELAY2 + 0x030 + 0x0000000 + + + IRQ_SEN + Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive) + 0x034 + 0x0000000 + + + IRQ_EDGE + Interrupt Both Edge Register (1:Both Edges, 0:Single Edge) + 0x038 + 0x0000000 + + + IRQ_EVT + Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) + 0x03c + 0x0000000 + + + IRQ_ENB + Interrupt Enable Register + 0x040 + 0x0000000 + + + IRQ_RAW + Raw Interrupt Status + 0x044 + read-only + 0x0000000 + + + IRQ_END + Masked Interrupt Status + 0x048 + read-only + 0x0000000 + + + EDGE_STATUS + Edge Status Register + 0x04c + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0xffc + 32 + read-only + 0x001007e1 + + + + + PORTB + 0x50001000 + + + + + TIM0 + 1.0 + Timer/Counter Peripheral + Timer_Counter + 0x40020000 + + 0 + 0x00001000 + registers + + + + + CTRL + Control Register + 0x000 + read-write + + + ENABLE + Counter Enable + [0:0] + + + ACTIVE + Counter Active + [1:1] + read-only + + + AUTO_DISABLE + Auto Disables the counter (set ENABLE to 0) when the count reaches 0 + [2:2] + + + AUTO_DEACTIVATE + Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0 + [3:3] + + + IRQ_ENB + Interrupt Enable + [4:4] + + + STATUS_SEL + Counter Status Selection + [7:5] + + + DONE + Single cycle pulse when the counter reaches 0 + 0 + + + ACTIVE + Returns the counter ACTIVE bit + 1 + + + TOGGLE + Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output. + 2 + + + PWMA + Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE + 3 + + + PWMB + Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE + 4 + + + ENABLED + Returns the counter ENABLED bit + 5 + + + PWMA_ACTIVE + Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0 + 6 + + + + + STATUS_INV + Invert the Output Status + [8:8] + + + REQ_STOP + Stop Request + [9:9] + + + + + RST_VALUE + The value that counter start from after reaching 0. + 0x004 + + + CNT_VALUE + The current value of the counter + 0x008 + + + ENABLE + Alternate access to the Counter ENABLE bit in the CTRL Register + 0x00c + + + ENABLE + Counter Enable + [0:0] + + + + + CSD_CTRL + The Cascade Control Register. Controls the counter external enable signals + 0x010 + + + CSDEN0 + Cascade 0 Enable + [0:0] + + + CSDINV0 + Cascade 0 Invert + [1:1] + + + CSDEN1 + Cascade 1 Enable + [2:2] + + + CSDINV1 + Cascade 1 Invert + [3:3] + + + DCASOP + Dual Cascade Operation (0:AND, 1:OR) + [4:4] + + + CSDTRG0 + Cascade 0 Enabled as Trigger + [6:6] + + + CSDTRG1 + Cascade 1 Enabled as Trigger + [7:7] + + + CSDEN2 + Cascade 2 Enable + [8:8] + + + CSDINV2 + Cascade 2 Invert + [9:9] + + + CSDXXX2 + Cascade 2 test mode + [11:11] + + + + + CASCADE0 + Cascade Enable Selection + 0x014 + + + CASSEL + Cascade Selection + [7:0] + + + + + CASCADE1 + Cascade Enable Selection + 0x018 + + + CASCADE2 + Cascade Enable Selection + 0x01c + + + PWM_VALUE + The Pulse Width Modulation Value + 0x020 + + + PWMA_VALUE + The Pulse Width Modulation ValueA + PWM_VALUE + 0x020 + + + PWMB_VALUE + The Pulse Width Modulation ValueB + 0x024 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001107e1 + + + + + TIM1 + 0x40021000 + + + TIM2 + 0x40022000 + + + TIM3 + 0x40023000 + + + TIM4 + 0x40024000 + + + TIM5 + 0x40025000 + + + TIM6 + 0x40026000 + + + TIM7 + 0x40027000 + + + TIM8 + 0x40028000 + + + TIM9 + 0x40029000 + + + TIM10 + 0x4002a000 + + + TIM11 + 0x4002b000 + + + TIM12 + 0x4002c000 + + + TIM13 + 0x4002d000 + + + TIM14 + 0x4002e000 + + + TIM15 + 0x4002f000 + + + TIM16 + 0x40030000 + + + TIM17 + 0x40031000 + + + TIM18 + 0x40032000 + + + TIM19 + 0x40033000 + + + TIM20 + 0x40034000 + + + TIM21 + 0x40035000 + + + TIM22 + 0x40036000 + + + TIM23 + 0x40037000 + + + + + UARTA + 1.0 + UART Peripheral + UART + 0x40040000 + + 0 + 0x00001000 + registers + + + + + DATA + Data In/Out Register + 0x000 + 0x0000000 + + + ENABLE + Enable Register + 0x004 + 0x0000000 + + + RXENABLE + Rx Enable + [0:0] + + + TXENABLE + Tx Enable + [1:1] + + + + + CTRL + Control Register + 0x008 + 0x0000000 + + + PAREN + Parity Enable + [0:0] + + + PAREVEN + Parity Even/Odd(1/0) + [1:1] + + + PARSTK + Parity Sticky + [2:2] + + + STOPBITS + Stop Bits 1/2(0/1) + [3:3] + + + WORDSIZE + Word Size in Bits 5/6/7/8(00/01/10/11) + [5:4] + + + LOOPBACK + Loopback Enable + [6:6] + + + LOOPBACKBLK + Loopback Block + [7:7] + + + AUTOCTS + Enable Auto CTS mode + [8:8] + + + DEFRTS + Default RTSn value + [9:9] + + + AUTORTS + Enable Auto RTS mode + [10:10] + + + BAUD8 + Enable BAUD8 mode + [11:11] + + + + + CLKSCALE + Clock Scale Register + 0x00c + 0x0000000 + + + FRAC + Fractional Divide (64ths) + [5:0] + + + INT + Integer Divide + [23:6] + + + RESET + Reset Baud Counter + [31:31] + write-only + + + + + RXSTATUS + Status Register + 0x010 + read-only + 0x0000000 + + + RDAVL + Read Data Available + [0:0] + + + RDNFULL + Read Fifo NOT Full + [1:1] + + + RXBUSY + RX Busy Receiving + [2:2] + + + RXTO + RX Receive Timeout + [3:3] + + + RXOVR + Read Fifo Overflow + [4:4] + + + RXFRM + RX Framing Error + [5:5] + + + RXPAR + RX Parity Error + [6:6] + + + RXBRK + RX Break Error + [7:7] + + + RXBUSYBRK + RX Busy Receiving Break + [8:8] + + + RXADDR9 + Address Match for 9 bit mode + [9:9] + + + RXRTSN + RX RTSn Output Value + [15:15] + + + + + TXSTATUS + Status Register + 0x014 + read-only + 0x0000000 + + + WRRDY + Write Fifo NOT Full + [0:0] + + + WRBUSY + Write Fifo Full + [1:1] + + + TXBUSY + TX Busy Transmitting + [2:2] + + + WRLOST + Write Data Lost (Fifo Overflow) + [3:3] + + + TXCTSN + TX CTSn Input Value + [15:15] + + + + + FIFO_CLR + Clear FIFO Register + 0x018 + write-only + 0x0000000 + + + RXSTS + Clear Rx Status + [0:0] + + + TXSTS + Clear Tx Status + [1:1] + + + RXFIFO + Clear Rx FIFO + [2:2] + + + TXFIFO + Clear Tx FIFO + [3:3] + + + + + TXBREAK + Break Transmit Register + 0x01c + write-only + 0x0000000 + + + ADDR9 + Address9 Register + 0x020 + read-write + 0x0000000 + + + ADDR9MASK + Address9 Mask Register + 0x024 + read-write + 0x0000000 + + + IRQ_ENB + IRQ Enable Register + 0x028 + read-write + 0x0000000 + + + IRQ_RX + RX Interrupt + [0:0] + + + IRQ_RX_STATUS + RX Status Interrupt + [1:1] + + + IRQ_RX_TO + RX Timeout Interrupt + [2:2] + + + IRQ_TX + TX Interrupt + [4:4] + + + IRQ_TX_STATUS + TX Status Interrupt + [5:5] + + + IRQ_TX_EMPTY + TX Empty Interrupt + [6:6] + + + IRQ_TX_CTS + TX CTS Change Interrupt + [7:7] + + + + + IRQ_RAW + IRQ Raw Status Register + 0x02c + read-only + 0x0000000 + + + IRQ_END + IRQ Enabled Status Register + 0x030 + read-only + 0x0000000 + + + IRQ_CLR + IRQ Clear Status Register + 0x034 + write-only + 0x0000000 + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x038 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x03c + + + RXFIFORTSTRG + Rx FIFO RTS Trigger Level + 0x040 + + + STATE + Internal STATE of UART Controller + 0x044 + 32 + read-only + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001207e1 + + + + + UARTB + 0x40041000 + + + + + SPIA + 1.0 + SPI Peripheral + SPI + 0x40050000 + + 0 + 0x00001000 + registers + + + + + CTRL0 + Control Register 0 + 0x000 + 0x0000000 + + + SIZE + Data Size(0x3=>4, 0xf=>16) + [3:0] + + + SPO + SPI Clock Polarity + [6:6] + + + SPH + SPI Clock Phase + [7:7] + + + SCRDV + Serial Clock Rate divide+1 value + [15:8] + + + + + CTRL1 + Control Register 1 + 0x004 + 0x0000000 + + + LBM + Loop Back + [0:0] + + + ENABLE + Enable + [1:1] + + + MS + Master/Slave (0:Master, 1:Slave) + [2:2] + + + SOD + Slave output Disable + [3:3] + + + SS + Slave Select + [6:4] + + + BLOCKMODE + Block Mode Enable + [7:7] + + + BMSTART + Block Mode Start Status Enable + [8:8] + + + BMSTALL + Block Mode Stall Enable + [9:9] + + + MDLYCAP + Master Delayed Capture Enable + [10:10] + + + MTXPAUSE + Master Tx Pause Enable + [11:11] + + + + + DATA + Data Input/Output + 0x008 + + + STATUS + Status Register + 0x00C + read-only + 0x0000000 + + + TFE + Transmit FIFO empty + [0:0] + + + TNF + Transmit FIFO not full + [1:1] + + + RNE + Receive FIFO not empty + [2:2] + + + RFF + Receive FIFO Full + [3:3] + + + BUSY + Busy + [4:4] + + + RXDATAFIRST + Pending Data is first Byte in BLOCKMODE + [5:5] + + + RXTRIGGER + RX FIFO Above Trigger Level + [6:6] + + + TXTRIGGER + TX FIFO Below Trigger Level + [7:7] + + + + + CLKPRESCALE + Clock Pre Scale divide value + 0x010 + + + IRQ_ENB + Interrupt Enable Register + 0x014 + read-write + 0x0000000 + + + RORIM + RX Overrun + [0:0] + + + RTIM + RX Timeout + [1:1] + + + RXIM + RX Fifo is at least half full + [2:2] + + + TXIM + TX Fifo is at least half empty + [3:3] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x018 + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x01C + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x020 + write-only + + oneToClear + + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x024 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x028 + + + FIFO_CLR + Clear FIFO Register + 0x02c + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + STATE + Internal STATE of SPI Controller + 0x030 + read-only + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001207e1 + + + + + SPIB + 0x40051000 + + + SPIC + 0x40052000 + + + + + I2CA + 1.0 + I2C Peripheral + I2C + 0x40060000 + + 0 + 0x00001000 + registers + + + + + + CTRL + Control Register + 0x000 + 0x0000000 + + + CLKENABLED + I2C CLK Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + ALGFILTER + Enable Input Analog Glitch Filter + [5:5] + + + DLGFILTER + Enable Input Digital Glitch Filter + [6:6] + + + LOOPBACK + Enable LoopBack Mode + [8:8] + + + TMCONFIGENB + Enable Timing Config Register + [9:9] + + + + + CLKSCALE + Clock Scale divide value + 0x004 + + + VALUE + Enable FastMode + [30:0] + + + FASTMODE + Enable FastMode + [31:31] + + + + + WORDS + Word Count value + 0x008 + + + ADDRESS + I2C Address value + 0x00c + + + DATA + Data Input/Output + 0x010 + + + CMD + Command Register + 0x014 + + + STATUS + I2C Controller Status Register + 0x018 + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + STATE + Internal STATE of I2C Master Controller + 0x01c + read-only + + + TXCOUNT + TX Count Register + 0x020 + read-only + + + RXCOUNT + RX Count Register + 0x024 + read-only + + + IRQ_ENB + Interrupt Enable Register + 0x028 + read-write + 0x0000000 + + + I2CIDLE + I2C Bus is Idle + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + CLKLOTO + I2C Clock Low Timeout + [7:7] + + + TXOVERFLOW + TX FIFO Overflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x02c + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x030 + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x034 + write-only + + oneToClear + + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x038 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x03c + + + FIFO_CLR + Clear FIFO Register + 0x040 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TMCONFIG + Timing Config Register + 0x044 + + + CLKTOLIMIT + Clock Low Timeout Limit Register + 0x048 + + + + S0_CTRL + Slave Control Register + 0x100 + 0x0000000 + + + CLKENABLED + I2C Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + + + S0_MAXWORDS + Slave MaxWords Register + 0x104 + + + S0_ADDRESS + Slave I2C Address Value + 0x108 + + + S0_ADDRESSMASK + Slave I2C Address Mask value + 0x10c + + + S0_DATA + Slave Data Input/Output + 0x110 + + + S0_LASTADDRESS + Slave I2C Last Address value + 0x114 + read-only + + + S0_STATUS + Slave I2C Controller Status Register + 0x118 + read-only + 0x0000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_BUSY + I2C Raw Busy value + [29:29] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + S0_STATE + Internal STATE of I2C Slave Controller + 0x11c + read-only + + + S0_TXCOUNT + Slave TX Count Register + 0x120 + read-only + + + S0_RXCOUNT + Slave RX Count Register + 0x124 + read-only + + + S0_IRQ_ENB + Slave Interrupt Enable Register + 0x128 + read-write + 0x0000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + I2C_START + I2C Start Condition + [8:8] + + + I2C_STOP + I2C Stop Condition + [9:9] + + + TXUNDERFLOW + TX FIFO Underflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + S0_IRQ_RAW + Slave Raw Interrupt Status Register + 0x12c + read-only + + + S0_IRQ_END + Slave Enabled Interrupt Status Register + 0x130 + read-only + + + S0_IRQ_CLR + Slave Clear Interrupt Status Register + 0x134 + write-only + + oneToClear + + + + S0_RXFIFOIRQTRG + Slave Rx FIFO IRQ Trigger Level + 0x138 + + + S0_TXFIFOIRQTRG + Slave Tx FIFO IRQ Trigger Level + 0x13c + + + S0_FIFO_CLR + Slave Clear FIFO Register + 0x140 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + S0_ADDRESSB + Slave I2C Address B Value + 0x144 + + + S0_ADDRESSMASKB + Slave I2C Address B Mask value + 0x148 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001407e1 + + + + + I2CB + 0x40061000 + + + + diff --git a/va108xx/va108xx/svd/va108xx-patch.yml b/va108xx/va108xx/svd/va108xx-patch.yml new file mode 100644 index 0000000..a7a8873 --- /dev/null +++ b/va108xx/va108xx/svd/va108xx-patch.yml @@ -0,0 +1,137 @@ +_svd: va108xx.svd + +SYSCONFIG: + PERIPHERAL_CLK_ENABLE: + _add: + PORTA: + description: Enable PORTA clock + bitOffset: 0 + bitWidth: 1 + PORTB: + description: Enable PORTB clock + bitOffset: 1 + bitWidth: 1 + SPI_0: + description: Enable SPI[0] clock + bitOffset: 4 + bitWidth: 1 + SPI_1: + description: Enable SPI[1] clock + bitOffset: 5 + bitWidth: 1 + SPI_2: + description: Enable SPI[2] clock + bitOffset: 6 + bitWidth: 1 + UART_0: + description: Enable UART[0] clock + bitOffset: 8 + bitWidth: 1 + UART_1: + description: Enable UART[1] clock + bitOffset: 9 + bitWidth: 1 + I2C_0: + description: Enable I2C[0] clock + bitOffset: 16 + bitWidth: 1 + I2C_1: + description: Enable I2C[1] clock + bitOffset: 17 + bitWidth: 1 + IRQSEL: + description: Enable IRQ selector clock + bitOffset: 21 + bitWidth: 1 + IOCONFIG: + description: Enable IO Configuration block clock + bitOffset: 22 + bitWidth: 1 + UTILITY: + description: Enable utility clock + bitOffset: 23 + bitWidth: 1 + GPIO: + description: Enable GPIO clock + bitOffset: 24 + bitWidth: 1 + + PERIPHERAL_RESET: + _add: + PORTA: + description: Reset PORTA + bitOffset: 0 + bitWidth: 1 + PORTB: + description: Reset PORTB + bitOffset: 1 + bitWidth: 1 + SPI_0: + description: Reset SPI[0] + bitOffset: 4 + bitWidth: 1 + SPI_1: + description: Reset SPI[1] + bitOffset: 5 + bitWidth: 1 + SPI_2: + description: Reset SPI[2] + bitOffset: 6 + bitWidth: 1 + UART_0: + description: Reset UART[0] + bitOffset: 8 + bitWidth: 1 + UART_1: + description: Reset UART[1] + bitOffset: 9 + bitWidth: 1 + I2C_0: + description: Reset I2C[0] + bitOffset: 16 + bitWidth: 1 + I2C_1: + description: Reset I2C[1] + bitOffset: 17 + bitWidth: 1 + IRQSEL: + description: Reset IRQ selector + bitOffset: 21 + bitWidth: 1 + IOCONFIG: + description: Reset IO Configuration block + bitOffset: 22 + bitWidth: 1 + UTILITY: + description: Reset Utility Block + bitOffset: 23 + bitWidth: 1 + GPIO: + description: Reset GPIO + bitOffset: 24 + bitWidth: 1 + +# I2CB is derived from I2CA +I2CA: + _modify: + STATUS: + access: read-only + STATUS: + _add: + I2C_IDLE: + description: I2C bus is Idle + bitOffset: 0 + bitWidth: 1 + IDLE: + description: Controller is Idle + bitOffset: 1 + bitWidth: 1 + +# All TIMs are derived from TIM0 +TIM0: + CSD_CTRL: + _add: + CSDTRG2: + description: Cascade 2 Enabled as Trigger + bitOffset: 10 + bitWidth: 1 diff --git a/va108xx/va108xx/svd/va108xx.svd b/va108xx/va108xx/svd/va108xx.svd new file mode 100644 index 0000000..0658a97 --- /dev/null +++ b/va108xx/va108xx/svd/va108xx.svd @@ -0,0 +1,2733 @@ + + + VORAGO TECHNOLOGIES + SST + va108xx + M0 + 1.1 + ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 50MHz + + VORAGO Technologies \n +\n +----------------------------------------------------------------------------\n + Copyright (c) 2013-2016 VORAGO Technologies\n +\n + BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n + AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n +\n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n + FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n + + + CM0 + r0p0 + little + false + false + 2 + false + + system_VA108xx + VOR_ + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + SYSCONFIG + 1.0 + System Configuration Peripheral + 0x40000000 + + 0 + 0x00001000 + registers + + + + RST_STAT + System Reset Status + 0x000 + read-write + 0x00000001 + + + POR + Power On Reset Status + [0:0] + + + EXTRST + External Reset Status + [1:1] + + + SYSRSTREQ + SYSRESETREQ Reset Status + [2:2] + + + LOOKUP + LOOKUP Reset Status + [3:3] + + + WATCHDOG + WATCHDOG Reset Status + [4:4] + + + MEMERR + Memory Error Reset Status + [5:5] + + + + + RST_CNTL_ROM + ROM Reset Control + 0x004 + 0x0000001F + + + RST_CNTL_RAM + RAM Reset Control + 0x008 + 0x0000001F + + + ROM_PROT + ROM Protection Configuration + 0x00C + 0x00000001 + + + WREN + ROM Write Enable Bit + [0:0] + + + + + ROM_SCRUB + ROM Scrub Period Configuration + 0x010 + read-write + 0x00000000 + + + VALUE + Counter divide value + [23:0] + + + RESET + Reset Counter + [31:31] + write-only + oneToClear + + + + + RAM_SCRUB + RAM Scrub Period Configuration + 0x014 + + + ROM_TRAP_ADDR + ROM Trap Address + 0x018 + 0x00000000 + + + ADDR + Trap Address Match Bits + [15:2] + + + ENABLE + Trap Enable Bit + [31:31] + + + + + ROM_TRAP_SYND + ROM Trap Syndrome + 0x01C + 0x00000000 + + + SYND + Trap Syndrom Bits + [19:0] + + + + + RAM_TRAP_ADDR + RAM Trap Address + 0x020 + + + RAM_TRAP_SYND + RAM Trap Syndrome + 0x024 + + + IRQ_ENB + Enable EDAC Error Interrupt Register + 0x028 + read-write + 0x00000000 + + + RAMSBE + RAM Single Bit Interrupt + [0:0] + + + RAMMBE + RAM Multi Bit Interrupt + [1:1] + + + ROMSBE + ROM Single Bit Interrupt + [2:2] + + + ROMMBE + ROM Multi Bit Interrupt + [3:3] + + + + + IRQ_RAW + Raw EDAC Error Interrupt Status + 0x02C + read-only + 0x00000000 + + + IRQ_END + Enabled EDAC Error Interrupt Status + 0x030 + read-only + 0x00000000 + + + IRQ_CLR + Clear EDAC Error Interrupt Status + 0x034 + write-only + 0x00000000 + oneToClear + + + RAM_SBE + Count of RAM EDAC Single Bit Errors + 0x038 + 0x00000000 + + + RAM_MBE + Count of RAM EDAC Multi Bit Errors + 0x03C + + + ROM_SBE + Count of ROM EDAC Single Bit Errors + 0x040 + + + ROM_MBE + Count of ROM EDAC Multi Bit Errors + 0x044 + + + IOCONFIG_CLKDIV0 + IO Configuration Clock Divider Register + 0x048 + read-only + 0x00000000 + + + 7 + 4 + 1-7 + IOCONFIG_CLKDIV%s + IO Configuration Clock Divider Register + 0x04C + 0x00000000 + + + ROM_RETRIES + ROM BOOT Retry count + 0x068 + read-only + 0x00000000 + + + REFRESH_CONFIG + Register Refresh Control + 0x06C + 0x00000000 + + + TIM_RESET + TIM Reset Control + 0x070 + 0xFFFFFFFF + + + TIM_CLK_ENABLE + TIM Enable Control + 0x074 + 0x00000000 + + + PERIPHERAL_RESET + Peripheral Reset Control + 0x078 + 0xFFFFFFFF + + + PERIPHERAL_CLK_ENABLE + Peripheral Enable Control + 0x07C + 0x00000000 + + + LOCKUP_RESET + Lockup Reset Configuration + 0x080 + 0x00000001 + + + LREN + Lockup Reset Enable Bit + [0:0] + + + + + EF_CONFIG + EFuse Config Register + 0xff0 + read-only + 0x00000000 + + + EF_ID + EFuse ID Register + 0xff4 + read-only + 0x00000000 + + + PROCID + Processor ID Register + 0xff8 + read-only + 0x040017e3 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x008007e1 + + + + + + + IRQSEL + 1.0 + Interrupt Selector Peripheral + 0x40001000 + + 0 + 0x00001000 + registers + + + OC0 + 0 + + + OC1 + 1 + + + OC2 + 2 + + + OC3 + 3 + + + OC4 + 4 + + + OC5 + 5 + + + OC6 + 6 + + + OC7 + 7 + + + OC8 + 8 + + + OC9 + 9 + + + OC10 + 10 + + + OC11 + 11 + + + OC12 + 12 + + + OC13 + 13 + + + OC14 + 14 + + + OC15 + 15 + + + OC16 + 16 + + + OC17 + 17 + + + OC18 + 18 + + + OC19 + 19 + + + OC20 + 20 + + + OC21 + 21 + + + OC22 + 22 + + + OC23 + 23 + + + OC24 + 24 + + + OC25 + 25 + + + OC26 + 26 + + + OC27 + 27 + + + OC28 + 28 + + + OC29 + 29 + + + OC30 + 30 + + + OC31 + 31 + + + + INT_RAM_SBE + Internal Memory RAM SBE Interrupt Redirect Selection + 0x01C0 + read-write + 0xFFFFFFFF + + + 32 + 4 + PORTA[%s] + PORTA Interrupt Redirect Selection + 0x000 + + + 32 + 4 + PORTB[%s] + PORTB Interrupt Redirect Selection + 0x080 + + + 32 + 4 + TIM[%s] + TIM Interrupt Redirect Selection + 0x100 + + + 4 + 4 + UART[%s] + UART Interrupt Redirect Selection + 0x180 + + + 4 + 4 + SPI[%s] + SPI Interrupt Redirect Selection + 0x190 + + + 4 + 4 + I2C_MS[%s] + Master I2C Interrupt Redirect Selection + 0x01a0 + + + 4 + 4 + I2C_SL[%s] + Slave I2C Interrupt Redirect Selection + 0x01B0 + + + INT_RAM_MBE + Internal Memory RAM MBE Interrupt Redirect Selection + 0x01C4 + + + INT_ROM_SBE + Internal Memory ROM SBE Interrupt Redirect Selection + 0x01C8 + + + INT_ROM_MBE + Internal Memory ROM MBE Interrupt Redirect Selection + 0x01CC + + + TXEV + Processor TXEV Interrupt Redirect Selection + 0x01D0 + + + NMI + NMI Status Register + 0x8f8 + read-only + 0x00000000 + + + ACTIVE + Active + [0:0] + + + + + RXEV + RXEV Status Register + 0x8f4 + + + WATCHDOG + WATCHDOG Status Register + 0x8f0 + + + MERESET + MERESET Status Register + 0x8ec + + + EDBGRQ + EDBGRQ Status Register + 0x8e8 + + + 32 + 4 + IRQS[%s] + Interrupt Status Register + 0x800 + + + PERID + Peripheral ID Register + 0xffc + 32 + read-only + 0x008007e1 + + + + + + + IOCONFIG + 1.0 + IO Pin Configuration Peripheral + 0x40002000 + + 0 + 0x00001000 + registers + + + + 32 + 4 + PORTA[%s] + PORTA Pin Configuration Register + 0x000 + 0x00000000 + + + FLTTYPE + Input Filter Selectoin + [2:0] + + + SYNC + Synchronize to system clock + 0 + + + DIRECT + Direct input, no synchronization + 1 + + + FILTER1 + Require 2 samples to have the same value + 2 + + + FILTER2 + Require 3 samples to have the same value + 3 + + + FILTER3 + Require 4 samples to have the same value + 4 + + + FILTER4 + Require 5 samples to have the same value + 5 + + + + + FLTCLK + Input Filter Clock Selection + [5:3] + + + INVINP + Input Invert Selection + [6:6] + + + IEWO + Input Enable While Output enabled + [7:7] + + + OPENDRN + Output Open Drain Mode + [8:8] + + + INVOUT + Output Invert Selection + [9:9] + + + PLEVEL + Internal Pull up/down level + [10:10] + + + PEN + Enable Internal Pull up/down + [11:11] + + + PWOA + Enable Pull when output active + [12:12] + + + FUNSEL + Pin Function Selection + [15:13] + + + IODIS + IO Pin Disable + [16:16] + + + + + PORTB[%s] + PORTB Pin Configuration Register + 0x0080 + 0x00000800 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x008207e1 + + + + + + + UTILITY + 1.0 + Utility Peripheral + 0x40003000 + + 0 + 0x00001000 + registers + + + + SYND_DATA0 + Synd Data 0 Register + 0x000 + 0x00000000 + + + SYND_DATA1 + Synd Data 1 Register + 0x004 + 0x00000000 + + + SYND_SYND + Synd Parity Register + 0x008 + 0x00000000 + + + SYND_ENC_32 + Synd 32 bit Encoded Syndrome + 0x00c + read-only + 0x00000000 + + + SYND_CHECK_32_DATA + Synd 32 bit Corrected Data + 0x010 + read-only + 0x00000000 + + + SYND_CHECK_32_SYND + Synd 32 bit Corrected Syndrome and Status + 0x014 + read-only + 0x00000000 + + + SYND_ENC_64 + Synd 64 bit Encoded Syndrome + 0x018 + read-only + 0x00000000 + + + SYND_CHECK_64_DATA0 + Synd 64 bit Corrected Data 0 + 0x01c + read-only + 0x00000000 + + + SYND_CHECK_64_DATA1 + Synd 64 bit Corrected Data 1 + 0x020 + read-only + 0x00000000 + + + SYND_CHECK_64_SYND + Synd 64 bit Corrected Parity and Status + 0x024 + read-only + 0x00000000 + + + SYND_ENC_32_52 + Synd 32/52 bit Encoded Syndrome + 0x028 + read-only + 0x00000000 + + + SYND_CHECK_32_52_DATA + Synd 32/52 bit Corrected Data + 0x02c + read-only + 0x00000000 + + + SYND_CHECK_32_52_SYND + Synd 32/52 bit Corrected Syndrome and Status + 0x030 + read-only + 0x00000000 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x008207e1 + + + + + + + PORTA + 1.0 + GPIO Peripheral + GPIO + 0x50000000 + + 0 + 0x00001000 + registers + + + + + DATAIN + Data In Register + 0x000 + read-only + 0x0000000 + + + 4 + 1 + DATAINBYTE[%s] + Data In Register by Byte + DATAIN + 0x000 + 8 + read-only + 0x0000000 + + + DATAINRAW + Data In Raw Register + 0x004 + 0x0000000 + + + DATAINRAWBYTE[%s] + Data In Raw Register by Byte + DATAINRAW + 0x004 + 0x0000000 + + + DATAOUT + Data Out Register + 0x008 + write-only + 0x0000000 + + + 4 + 1 + DATAOUTBYTE[%s] + Data Out Register by Byte + DATAOUT + 0x008 + 8 + write-only + 0x0000000 + + + DATAOUTRAW + Data Out Register + 0x00c + 0x0000000 + + + DATAOUTRAWBYTE[%s] + Data Out Register by Byte + DATAOUTRAW + 0x00c + 0x0000000 + + + SETOUT + Set Out Register + 0x010 + 0x0000000 + + + SETOUTBYTE[%s] + Set Out Register by Byte + SETOUT + 0x010 + 0x0000000 + + + CLROUT + Clear Out Register + 0x014 + 0x0000000 + + + CLROUTBYTE[%s] + Clear Out Register by Byte + CLROUT + 0x014 + 0x0000000 + + + TOGOUT + Toggle Out Register + 0x018 + 0x0000000 + + + TOGOUTBYTE[%s] + Toggle Out Register by Byte + TOGOUT + 0x018 + 0x0000000 + + + DATAMASK + Data mask Register + 0x01c + 0x0000000 + + + 4 + 1 + DATAMASKBYTE[%s] + Data Out Register by Byte + DATAMASK + 0x01c + 8 + 0x0000000 + + + DIR + Direction Register (1:Output, 0:Input) + 0x020 + 0x0000000 + + + DIRBYTE[%s] + Direction Register by Byte + DIR + 0x020 + 0x0000000 + + + PULSE + Pulse Mode Register + 0x024 + 0x0000000 + + + PULSEBYTE[%s] + Pulse Mode Register by Byte + PULSE + 0x024 + 0x0000000 + + + PULSEBASE + Pulse Base Value Register + 0x028 + 0x0000000 + + + PULSEBASEBYTE[%s] + Pulse Base Mode Register by Byte + PULSEBASE + 0x028 + 0x0000000 + + + DELAY1 + Delay1 Register + 0x02c + 0x0000000 + + + DELAY1BYTE[%s] + Delay1 Register by Byte + DELAY1 + 0x02c + 0x0000000 + + + DELAY2 + Delay2 Register + 0x030 + 32 + read-write + 0x0000000 + + + DELAY2BYTE[%s] + Delay2 Register by Byte + DELAY2 + 0x030 + 0x0000000 + + + IRQ_SEN + Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive) + 0x034 + 0x0000000 + + + IRQ_EDGE + Interrupt Both Edge Register (1:Both Edges, 0:Single Edge) + 0x038 + 0x0000000 + + + IRQ_EVT + Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) + 0x03c + 0x0000000 + + + IRQ_ENB + Interrupt Enable Register + 0x040 + 0x0000000 + + + IRQ_RAW + Raw Interrupt Status + 0x044 + read-only + 0x0000000 + + + IRQ_END + Masked Interrupt Status + 0x048 + read-only + 0x0000000 + + + EDGE_STATUS + Edge Status Register + 0x04c + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0xffc + 32 + read-only + 0x001007e1 + + + + + PORTB + 0x50001000 + + + + + TIM0 + 1.0 + Timer/Counter Peripheral + Timer_Counter + 0x40020000 + + 0 + 0x00001000 + registers + + + + + CTRL + Control Register + 0x000 + read-write + + + ENABLE + Counter Enable + [0:0] + + + ACTIVE + Counter Active + [1:1] + read-only + + + AUTO_DISABLE + Auto Disables the counter (set ENABLE to 0) when the count reaches 0 + [2:2] + + + AUTO_DEACTIVATE + Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0 + [3:3] + + + IRQ_ENB + Interrupt Enable + [4:4] + + + STATUS_SEL + Counter Status Selection + [7:5] + + + DONE + Single cycle pulse when the counter reaches 0 + 0 + + + ACTIVE + Returns the counter ACTIVE bit + 1 + + + TOGGLE + Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output. + 2 + + + PWMA + Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE + 3 + + + PWMB + Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE + 4 + + + ENABLED + Returns the counter ENABLED bit + 5 + + + PWMA_ACTIVE + Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0 + 6 + + + + + STATUS_INV + Invert the Output Status + [8:8] + + + REQ_STOP + Stop Request + [9:9] + + + + + RST_VALUE + The value that counter start from after reaching 0. + 0x004 + + + CNT_VALUE + The current value of the counter + 0x008 + + + ENABLE + Alternate access to the Counter ENABLE bit in the CTRL Register + 0x00c + + + ENABLE + Counter Enable + [0:0] + + + + + CSD_CTRL + The Cascade Control Register. Controls the counter external enable signals + 0x010 + + + CSDEN0 + Cascade 0 Enable + [0:0] + + + CSDINV0 + Cascade 0 Invert + [1:1] + + + CSDEN1 + Cascade 1 Enable + [2:2] + + + CSDINV1 + Cascade 1 Invert + [3:3] + + + DCASOP + Dual Cascade Operation (0:AND, 1:OR) + [4:4] + + + CSDTRG0 + Cascade 0 Enabled as Trigger + [6:6] + + + CSDTRG1 + Cascade 1 Enabled as Trigger + [7:7] + + + CSDEN2 + Cascade 2 Enable + [8:8] + + + CSDINV2 + Cascade 2 Invert + [9:9] + + + CSDXXX2 + Cascade 2 test mode + [11:11] + + + + + CASCADE0 + Cascade Enable Selection + 0x014 + + + CASSEL + Cascade Selection + [7:0] + + + + + CASCADE1 + Cascade Enable Selection + 0x018 + + + CASCADE2 + Cascade Enable Selection + 0x01c + + + PWM_VALUE + The Pulse Width Modulation Value + 0x020 + + + PWMA_VALUE + The Pulse Width Modulation ValueA + PWM_VALUE + 0x020 + + + PWMB_VALUE + The Pulse Width Modulation ValueB + 0x024 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001107e1 + + + + + TIM1 + 0x40021000 + + + TIM2 + 0x40022000 + + + TIM3 + 0x40023000 + + + TIM4 + 0x40024000 + + + TIM5 + 0x40025000 + + + TIM6 + 0x40026000 + + + TIM7 + 0x40027000 + + + TIM8 + 0x40028000 + + + TIM9 + 0x40029000 + + + TIM10 + 0x4002a000 + + + TIM11 + 0x4002b000 + + + TIM12 + 0x4002c000 + + + TIM13 + 0x4002d000 + + + TIM14 + 0x4002e000 + + + TIM15 + 0x4002f000 + + + TIM16 + 0x40030000 + + + TIM17 + 0x40031000 + + + TIM18 + 0x40032000 + + + TIM19 + 0x40033000 + + + TIM20 + 0x40034000 + + + TIM21 + 0x40035000 + + + TIM22 + 0x40036000 + + + TIM23 + 0x40037000 + + + + + UARTA + 1.0 + UART Peripheral + UART + 0x40040000 + + 0 + 0x00001000 + registers + + + + + DATA + Data In/Out Register + 0x000 + 0x0000000 + + + ENABLE + Enable Register + 0x004 + 0x0000000 + + + RXENABLE + Rx Enable + [0:0] + + + TXENABLE + Tx Enable + [1:1] + + + + + CTRL + Control Register + 0x008 + 0x0000000 + + + PAREN + Parity Enable + [0:0] + + + PAREVEN + Parity Even/Odd(1/0) + [1:1] + + + PARSTK + Parity Sticky + [2:2] + + + STOPBITS + Stop Bits 1/2(0/1) + [3:3] + + + WORDSIZE + Word Size in Bits 5/6/7/8(00/01/10/11) + [5:4] + + + LOOPBACK + Loopback Enable + [6:6] + + + LOOPBACKBLK + Loopback Block + [7:7] + + + AUTOCTS + Enable Auto CTS mode + [8:8] + + + DEFRTS + Default RTSn value + [9:9] + + + AUTORTS + Enable Auto RTS mode + [10:10] + + + BAUD8 + Enable BAUD8 mode + [11:11] + + + + + CLKSCALE + Clock Scale Register + 0x00c + 0x0000000 + + + FRAC + Fractional Divide (64ths) + [5:0] + + + INT + Integer Divide + [23:6] + + + RESET + Reset Baud Counter + [31:31] + write-only + + + + + RXSTATUS + Status Register + 0x010 + read-only + 0x0000000 + + + RDAVL + Read Data Available + [0:0] + + + RDNFULL + Read Fifo NOT Full + [1:1] + + + RXBUSY + RX Busy Receiving + [2:2] + + + RXTO + RX Receive Timeout + [3:3] + + + RXOVR + Read Fifo Overflow + [4:4] + + + RXFRM + RX Framing Error + [5:5] + + + RXPAR + RX Parity Error + [6:6] + + + RXBRK + RX Break Error + [7:7] + + + RXBUSYBRK + RX Busy Receiving Break + [8:8] + + + RXADDR9 + Address Match for 9 bit mode + [9:9] + + + RXRTSN + RX RTSn Output Value + [15:15] + + + + + TXSTATUS + Status Register + 0x014 + read-only + 0x0000000 + + + WRRDY + Write Fifo NOT Full + [0:0] + + + WRBUSY + Write Fifo Full + [1:1] + + + TXBUSY + TX Busy Transmitting + [2:2] + + + WRLOST + Write Data Lost (Fifo Overflow) + [3:3] + + + TXCTSN + TX CTSn Input Value + [15:15] + + + + + FIFO_CLR + Clear FIFO Register + 0x018 + write-only + 0x0000000 + + + RXSTS + Clear Rx Status + [0:0] + + + TXSTS + Clear Tx Status + [1:1] + + + RXFIFO + Clear Rx FIFO + [2:2] + + + TXFIFO + Clear Tx FIFO + [3:3] + + + + + TXBREAK + Break Transmit Register + 0x01c + write-only + 0x0000000 + + + ADDR9 + Address9 Register + 0x020 + read-write + 0x0000000 + + + ADDR9MASK + Address9 Mask Register + 0x024 + read-write + 0x0000000 + + + IRQ_ENB + IRQ Enable Register + 0x028 + read-write + 0x0000000 + + + IRQ_RX + RX Interrupt + [0:0] + + + IRQ_RX_STATUS + RX Status Interrupt + [1:1] + + + IRQ_RX_TO + RX Timeout Interrupt + [2:2] + + + IRQ_TX + TX Interrupt + [4:4] + + + IRQ_TX_STATUS + TX Status Interrupt + [5:5] + + + IRQ_TX_EMPTY + TX Empty Interrupt + [6:6] + + + IRQ_TX_CTS + TX CTS Change Interrupt + [7:7] + + + + + IRQ_RAW + IRQ Raw Status Register + 0x02c + read-only + 0x0000000 + + + IRQ_END + IRQ Enabled Status Register + 0x030 + read-only + 0x0000000 + + + IRQ_CLR + IRQ Clear Status Register + 0x034 + write-only + 0x0000000 + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x038 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x03c + + + RXFIFORTSTRG + Rx FIFO RTS Trigger Level + 0x040 + + + STATE + Internal STATE of UART Controller + 0x044 + 32 + read-only + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001207e1 + + + + + UARTB + 0x40041000 + + + + + SPIA + 1.0 + SPI Peripheral + SPI + 0x40050000 + + 0 + 0x00001000 + registers + + + + + CTRL0 + Control Register 0 + 0x000 + 0x0000000 + + + SIZE + Data Size(0x3=>4, 0xf=>16) + [3:0] + + + SPO + SPI Clock Polarity + [6:6] + + + SPH + SPI Clock Phase + [7:7] + + + SCRDV + Serial Clock Rate divide+1 value + [15:8] + + + + + CTRL1 + Control Register 1 + 0x004 + 0x0000000 + + + LBM + Loop Back + [0:0] + + + ENABLE + Enable + [1:1] + + + MS + Master/Slave (0:Master, 1:Slave) + [2:2] + + + SOD + Slave output Disable + [3:3] + + + SS + Slave Select + [6:4] + + + BLOCKMODE + Block Mode Enable + [7:7] + + + BMSTART + Block Mode Start Status Enable + [8:8] + + + BMSTALL + Block Mode Stall Enable + [9:9] + + + MDLYCAP + Master Delayed Capture Enable + [10:10] + + + MTXPAUSE + Master Tx Pause Enable + [11:11] + + + + + DATA + Data Input/Output + 0x008 + + + STATUS + Status Register + 0x00C + read-only + 0x0000000 + + + TFE + Transmit FIFO empty + [0:0] + + + TNF + Transmit FIFO not full + [1:1] + + + RNE + Receive FIFO not empty + [2:2] + + + RFF + Receive FIFO Full + [3:3] + + + BUSY + Busy + [4:4] + + + RXDATAFIRST + Pending Data is first Byte in BLOCKMODE + [5:5] + + + RXTRIGGER + RX FIFO Above Trigger Level + [6:6] + + + TXTRIGGER + TX FIFO Below Trigger Level + [7:7] + + + + + CLKPRESCALE + Clock Pre Scale divide value + 0x010 + + + IRQ_ENB + Interrupt Enable Register + 0x014 + read-write + 0x0000000 + + + RORIM + RX Overrun + [0:0] + + + RTIM + RX Timeout + [1:1] + + + RXIM + RX Fifo is at least half full + [2:2] + + + TXIM + TX Fifo is at least half empty + [3:3] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x018 + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x01C + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x020 + write-only + oneToClear + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x024 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x028 + + + FIFO_CLR + Clear FIFO Register + 0x02c + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + STATE + Internal STATE of SPI Controller + 0x030 + read-only + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001207e1 + + + + + SPIB + 0x40051000 + + + SPIC + 0x40052000 + + + + + I2CA + 1.0 + I2C Peripheral + I2C + 0x40060000 + + 0 + 0x00001000 + registers + + + + + + CTRL + Control Register + 0x000 + 0x0000000 + + + CLKENABLED + I2C CLK Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + ALGFILTER + Enable Input Analog Glitch Filter + [5:5] + + + DLGFILTER + Enable Input Digital Glitch Filter + [6:6] + + + LOOPBACK + Enable LoopBack Mode + [8:8] + + + TMCONFIGENB + Enable Timing Config Register + [9:9] + + + + + CLKSCALE + Clock Scale divide value + 0x004 + + + VALUE + Enable FastMode + [30:0] + + + FASTMODE + Enable FastMode + [31:31] + + + + + WORDS + Word Count value + 0x008 + + + ADDRESS + I2C Address value + 0x00c + + + DATA + Data Input/Output + 0x010 + + + CMD + Command Register + 0x014 + + + STATUS + I2C Controller Status Register + 0x018 + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + STATE + Internal STATE of I2C Master Controller + 0x01c + read-only + + + TXCOUNT + TX Count Register + 0x020 + read-only + + + RXCOUNT + RX Count Register + 0x024 + read-only + + + IRQ_ENB + Interrupt Enable Register + 0x028 + read-write + 0x0000000 + + + I2CIDLE + I2C Bus is Idle + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + CLKLOTO + I2C Clock Low Timeout + [7:7] + + + TXOVERFLOW + TX FIFO Overflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x02c + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x030 + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x034 + write-only + oneToClear + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x038 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x03c + + + FIFO_CLR + Clear FIFO Register + 0x040 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TMCONFIG + Timing Config Register + 0x044 + + + CLKTOLIMIT + Clock Low Timeout Limit Register + 0x048 + + + + S0_CTRL + Slave Control Register + 0x100 + 0x0000000 + + + CLKENABLED + I2C Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + + + S0_MAXWORDS + Slave MaxWords Register + 0x104 + + + S0_ADDRESS + Slave I2C Address Value + 0x108 + + + S0_ADDRESSMASK + Slave I2C Address Mask value + 0x10c + + + S0_DATA + Slave Data Input/Output + 0x110 + + + S0_LASTADDRESS + Slave I2C Last Address value + 0x114 + read-only + + + S0_STATUS + Slave I2C Controller Status Register + 0x118 + read-only + 0x0000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_BUSY + I2C Raw Busy value + [29:29] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + S0_STATE + Internal STATE of I2C Slave Controller + 0x11c + read-only + + + S0_TXCOUNT + Slave TX Count Register + 0x120 + read-only + + + S0_RXCOUNT + Slave RX Count Register + 0x124 + read-only + + + S0_IRQ_ENB + Slave Interrupt Enable Register + 0x128 + read-write + 0x0000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + I2C_START + I2C Start Condition + [8:8] + + + I2C_STOP + I2C Stop Condition + [9:9] + + + TXUNDERFLOW + TX FIFO Underflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + S0_IRQ_RAW + Slave Raw Interrupt Status Register + 0x12c + read-only + + + S0_IRQ_END + Slave Enabled Interrupt Status Register + 0x130 + read-only + + + S0_IRQ_CLR + Slave Clear Interrupt Status Register + 0x134 + write-only + oneToClear + + + S0_RXFIFOIRQTRG + Slave Rx FIFO IRQ Trigger Level + 0x138 + + + S0_TXFIFOIRQTRG + Slave Tx FIFO IRQ Trigger Level + 0x13c + + + S0_FIFO_CLR + Slave Clear FIFO Register + 0x140 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + S0_ADDRESSB + Slave I2C Address B Value + 0x144 + + + S0_ADDRESSMASKB + Slave I2C Address B Mask value + 0x148 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001407e1 + + + + + I2CB + 0x40061000 + + + + diff --git a/va108xx/va108xx/svd/va108xx.svd.patched b/va108xx/va108xx/svd/va108xx.svd.patched new file mode 100644 index 0000000..39c07b4 --- /dev/null +++ b/va108xx/va108xx/svd/va108xx.svd.patched @@ -0,0 +1,2883 @@ + + + VORAGO TECHNOLOGIES + SST + va108xx + M0 + 1.1 + ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 50MHz + VORAGO Technologies \n +\n +----------------------------------------------------------------------------\n + Copyright (c) 2013-2016 VORAGO Technologies\n +\n + BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n + AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n +\n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n + FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n + + CM0 + r0p0 + little + false + false + 2 + false + + system_VA108xx + VOR_ + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + SYSCONFIG + 1.0 + System Configuration Peripheral + 0x40000000 + + 0x0 + 0x1000 + registers + + + + RST_STAT + System Reset Status + 0x0 + read-write + 0x00000001 + + + POR + Power On Reset Status + [0:0] + + + EXTRST + External Reset Status + [1:1] + + + SYSRSTREQ + SYSRESETREQ Reset Status + [2:2] + + + LOOKUP + LOOKUP Reset Status + [3:3] + + + WATCHDOG + WATCHDOG Reset Status + [4:4] + + + MEMERR + Memory Error Reset Status + [5:5] + + + + + RST_CNTL_ROM + ROM Reset Control + 0x4 + 0x0000001F + + + RST_CNTL_RAM + RAM Reset Control + 0x8 + 0x0000001F + + + ROM_PROT + ROM Protection Configuration + 0xC + 0x00000001 + + + WREN + ROM Write Enable Bit + [0:0] + + + + + ROM_SCRUB + ROM Scrub Period Configuration + 0x10 + read-write + 0x00000000 + + + VALUE + Counter divide value + [23:0] + + + RESET + Reset Counter + [31:31] + write-only + oneToClear + + + + + RAM_SCRUB + RAM Scrub Period Configuration + 0x14 + + + ROM_TRAP_ADDR + ROM Trap Address + 0x18 + 0x00000000 + + + ADDR + Trap Address Match Bits + [15:2] + + + ENABLE + Trap Enable Bit + [31:31] + + + + + ROM_TRAP_SYND + ROM Trap Syndrome + 0x1C + 0x00000000 + + + SYND + Trap Syndrom Bits + [19:0] + + + + + RAM_TRAP_ADDR + RAM Trap Address + 0x20 + + + RAM_TRAP_SYND + RAM Trap Syndrome + 0x24 + + + IRQ_ENB + Enable EDAC Error Interrupt Register + 0x28 + read-write + 0x00000000 + + + RAMSBE + RAM Single Bit Interrupt + [0:0] + + + RAMMBE + RAM Multi Bit Interrupt + [1:1] + + + ROMSBE + ROM Single Bit Interrupt + [2:2] + + + ROMMBE + ROM Multi Bit Interrupt + [3:3] + + + + + IRQ_RAW + Raw EDAC Error Interrupt Status + 0x2C + read-only + 0x00000000 + + + IRQ_END + Enabled EDAC Error Interrupt Status + 0x30 + read-only + 0x00000000 + + + IRQ_CLR + Clear EDAC Error Interrupt Status + 0x34 + write-only + 0x00000000 + oneToClear + + + RAM_SBE + Count of RAM EDAC Single Bit Errors + 0x38 + 0x00000000 + + + RAM_MBE + Count of RAM EDAC Multi Bit Errors + 0x3C + + + ROM_SBE + Count of ROM EDAC Single Bit Errors + 0x40 + + + ROM_MBE + Count of ROM EDAC Multi Bit Errors + 0x44 + + + IOCONFIG_CLKDIV0 + IO Configuration Clock Divider Register + 0x48 + read-only + 0x00000000 + + + 7 + 0x4 + 1-7 + IOCONFIG_CLKDIV%s + IO Configuration Clock Divider Register + 0x4C + 0x00000000 + + + ROM_RETRIES + ROM BOOT Retry count + 0x68 + read-only + 0x00000000 + + + REFRESH_CONFIG + Register Refresh Control + 0x6C + 0x00000000 + + + TIM_RESET + TIM Reset Control + 0x70 + 0xFFFFFFFF + + + TIM_CLK_ENABLE + TIM Enable Control + 0x74 + 0x00000000 + + + PERIPHERAL_RESET + Peripheral Reset Control + 0x78 + 0xFFFFFFFF + + + PORTA + Reset PORTA + 0 + 1 + + + PORTB + Reset PORTB + 1 + 1 + + + SPI_0 + Reset SPI[0] + 4 + 1 + + + SPI_1 + Reset SPI[1] + 5 + 1 + + + SPI_2 + Reset SPI[2] + 6 + 1 + + + UART_0 + Reset UART[0] + 8 + 1 + + + UART_1 + Reset UART[1] + 9 + 1 + + + I2C_0 + Reset I2C[0] + 16 + 1 + + + I2C_1 + Reset I2C[1] + 17 + 1 + + + IRQSEL + Reset IRQ selector + 21 + 1 + + + IOCONFIG + Reset IO Configuration block + 22 + 1 + + + UTILITY + Reset Utility Block + 23 + 1 + + + GPIO + Reset GPIO + 24 + 1 + + + + + PERIPHERAL_CLK_ENABLE + Peripheral Enable Control + 0x7C + 0x00000000 + + + PORTA + Enable PORTA clock + 0 + 1 + + + PORTB + Enable PORTB clock + 1 + 1 + + + SPI_0 + Enable SPI[0] clock + 4 + 1 + + + SPI_1 + Enable SPI[1] clock + 5 + 1 + + + SPI_2 + Enable SPI[2] clock + 6 + 1 + + + UART_0 + Enable UART[0] clock + 8 + 1 + + + UART_1 + Enable UART[1] clock + 9 + 1 + + + I2C_0 + Enable I2C[0] clock + 16 + 1 + + + I2C_1 + Enable I2C[1] clock + 17 + 1 + + + IRQSEL + Enable IRQ selector clock + 21 + 1 + + + IOCONFIG + Enable IO Configuration block clock + 22 + 1 + + + UTILITY + Enable utility clock + 23 + 1 + + + GPIO + Enable GPIO clock + 24 + 1 + + + + + LOCKUP_RESET + Lockup Reset Configuration + 0x80 + 0x00000001 + + + LREN + Lockup Reset Enable Bit + [0:0] + + + + + EF_CONFIG + EFuse Config Register + 0xFF0 + read-only + 0x00000000 + + + EF_ID + EFuse ID Register + 0xFF4 + read-only + 0x00000000 + + + PROCID + Processor ID Register + 0xFF8 + read-only + 0x040017E3 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x008007E1 + + + + + IRQSEL + 1.0 + Interrupt Selector Peripheral + 0x40001000 + + 0x0 + 0x1000 + registers + + + OC0 + 0 + + + OC1 + 1 + + + OC2 + 2 + + + OC3 + 3 + + + OC4 + 4 + + + OC5 + 5 + + + OC6 + 6 + + + OC7 + 7 + + + OC8 + 8 + + + OC9 + 9 + + + OC10 + 10 + + + OC11 + 11 + + + OC12 + 12 + + + OC13 + 13 + + + OC14 + 14 + + + OC15 + 15 + + + OC16 + 16 + + + OC17 + 17 + + + OC18 + 18 + + + OC19 + 19 + + + OC20 + 20 + + + OC21 + 21 + + + OC22 + 22 + + + OC23 + 23 + + + OC24 + 24 + + + OC25 + 25 + + + OC26 + 26 + + + OC27 + 27 + + + OC28 + 28 + + + OC29 + 29 + + + OC30 + 30 + + + OC31 + 31 + + + + INT_RAM_SBE + Internal Memory RAM SBE Interrupt Redirect Selection + 0x1C0 + read-write + 0xFFFFFFFF + + + 32 + 0x4 + PORTA[%s] + PORTA Interrupt Redirect Selection + 0x0 + + + 32 + 0x4 + PORTB[%s] + PORTB Interrupt Redirect Selection + 0x80 + + + 32 + 0x4 + TIM[%s] + TIM Interrupt Redirect Selection + 0x100 + + + 4 + 0x4 + UART[%s] + UART Interrupt Redirect Selection + 0x180 + + + 4 + 0x4 + SPI[%s] + SPI Interrupt Redirect Selection + 0x190 + + + 4 + 0x4 + I2C_MS[%s] + Master I2C Interrupt Redirect Selection + 0x1A0 + + + 4 + 0x4 + I2C_SL[%s] + Slave I2C Interrupt Redirect Selection + 0x1B0 + + + INT_RAM_MBE + Internal Memory RAM MBE Interrupt Redirect Selection + 0x1C4 + + + INT_ROM_SBE + Internal Memory ROM SBE Interrupt Redirect Selection + 0x1C8 + + + INT_ROM_MBE + Internal Memory ROM MBE Interrupt Redirect Selection + 0x1CC + + + TXEV + Processor TXEV Interrupt Redirect Selection + 0x1D0 + + + NMI + NMI Status Register + 0x8F8 + read-only + 0x00000000 + + + ACTIVE + Active + [0:0] + + + + + RXEV + RXEV Status Register + 0x8F4 + + + WATCHDOG + WATCHDOG Status Register + 0x8F0 + + + MERESET + MERESET Status Register + 0x8EC + + + EDBGRQ + EDBGRQ Status Register + 0x8E8 + + + 32 + 0x4 + IRQS[%s] + Interrupt Status Register + 0x800 + + + PERID + Peripheral ID Register + 0xFFC + 0x20 + read-only + 0x008007E1 + + + + + IOCONFIG + 1.0 + IO Pin Configuration Peripheral + 0x40002000 + + 0x0 + 0x1000 + registers + + + + 32 + 0x4 + PORTA[%s] + PORTA Pin Configuration Register + 0x0 + 0x00000000 + + + FLTTYPE + Input Filter Selectoin + [2:0] + + + SYNC + Synchronize to system clock + 0 + + + DIRECT + Direct input, no synchronization + 1 + + + FILTER1 + Require 2 samples to have the same value + 2 + + + FILTER2 + Require 3 samples to have the same value + 3 + + + FILTER3 + Require 4 samples to have the same value + 4 + + + FILTER4 + Require 5 samples to have the same value + 5 + + + + + FLTCLK + Input Filter Clock Selection + [5:3] + + + INVINP + Input Invert Selection + [6:6] + + + IEWO + Input Enable While Output enabled + [7:7] + + + OPENDRN + Output Open Drain Mode + [8:8] + + + INVOUT + Output Invert Selection + [9:9] + + + PLEVEL + Internal Pull up/down level + [10:10] + + + PEN + Enable Internal Pull up/down + [11:11] + + + PWOA + Enable Pull when output active + [12:12] + + + FUNSEL + Pin Function Selection + [15:13] + + + IODIS + IO Pin Disable + [16:16] + + + + + PORTB[%s] + PORTB Pin Configuration Register + 0x80 + 0x00000800 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x008207E1 + + + + + UTILITY + 1.0 + Utility Peripheral + 0x40003000 + + 0x0 + 0x1000 + registers + + + + SYND_DATA0 + Synd Data 0 Register + 0x0 + 0x00000000 + + + SYND_DATA1 + Synd Data 1 Register + 0x4 + 0x00000000 + + + SYND_SYND + Synd Parity Register + 0x8 + 0x00000000 + + + SYND_ENC_32 + Synd 32 bit Encoded Syndrome + 0xC + read-only + 0x00000000 + + + SYND_CHECK_32_DATA + Synd 32 bit Corrected Data + 0x10 + read-only + 0x00000000 + + + SYND_CHECK_32_SYND + Synd 32 bit Corrected Syndrome and Status + 0x14 + read-only + 0x00000000 + + + SYND_ENC_64 + Synd 64 bit Encoded Syndrome + 0x18 + read-only + 0x00000000 + + + SYND_CHECK_64_DATA0 + Synd 64 bit Corrected Data 0 + 0x1C + read-only + 0x00000000 + + + SYND_CHECK_64_DATA1 + Synd 64 bit Corrected Data 1 + 0x20 + read-only + 0x00000000 + + + SYND_CHECK_64_SYND + Synd 64 bit Corrected Parity and Status + 0x24 + read-only + 0x00000000 + + + SYND_ENC_32_52 + Synd 32/52 bit Encoded Syndrome + 0x28 + read-only + 0x00000000 + + + SYND_CHECK_32_52_DATA + Synd 32/52 bit Corrected Data + 0x2C + read-only + 0x00000000 + + + SYND_CHECK_32_52_SYND + Synd 32/52 bit Corrected Syndrome and Status + 0x30 + read-only + 0x00000000 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x008207E1 + + + + + PORTA + 1.0 + GPIO Peripheral + GPIO + 0x50000000 + + 0x0 + 0x1000 + registers + + + + DATAIN + Data In Register + 0x0 + read-only + 0x00000000 + + + 4 + 0x1 + DATAINBYTE[%s] + Data In Register by Byte + DATAIN + 0x0 + 0x8 + read-only + 0x00000000 + + + DATAINRAW + Data In Raw Register + 0x4 + 0x00000000 + + + DATAINRAWBYTE[%s] + Data In Raw Register by Byte + DATAINRAW + 0x4 + 0x00000000 + + + DATAOUT + Data Out Register + 0x8 + write-only + 0x00000000 + + + 4 + 0x1 + DATAOUTBYTE[%s] + Data Out Register by Byte + DATAOUT + 0x8 + 0x8 + write-only + 0x00000000 + + + DATAOUTRAW + Data Out Register + 0xC + 0x00000000 + + + DATAOUTRAWBYTE[%s] + Data Out Register by Byte + DATAOUTRAW + 0xC + 0x00000000 + + + SETOUT + Set Out Register + 0x10 + 0x00000000 + + + SETOUTBYTE[%s] + Set Out Register by Byte + SETOUT + 0x10 + 0x00000000 + + + CLROUT + Clear Out Register + 0x14 + 0x00000000 + + + CLROUTBYTE[%s] + Clear Out Register by Byte + CLROUT + 0x14 + 0x00000000 + + + TOGOUT + Toggle Out Register + 0x18 + 0x00000000 + + + TOGOUTBYTE[%s] + Toggle Out Register by Byte + TOGOUT + 0x18 + 0x00000000 + + + DATAMASK + Data mask Register + 0x1C + 0x00000000 + + + 4 + 0x1 + DATAMASKBYTE[%s] + Data Out Register by Byte + DATAMASK + 0x1C + 0x8 + 0x00000000 + + + DIR + Direction Register (1:Output, 0:Input) + 0x20 + 0x00000000 + + + DIRBYTE[%s] + Direction Register by Byte + DIR + 0x20 + 0x00000000 + + + PULSE + Pulse Mode Register + 0x24 + 0x00000000 + + + PULSEBYTE[%s] + Pulse Mode Register by Byte + PULSE + 0x24 + 0x00000000 + + + PULSEBASE + Pulse Base Value Register + 0x28 + 0x00000000 + + + PULSEBASEBYTE[%s] + Pulse Base Mode Register by Byte + PULSEBASE + 0x28 + 0x00000000 + + + DELAY1 + Delay1 Register + 0x2C + 0x00000000 + + + DELAY1BYTE[%s] + Delay1 Register by Byte + DELAY1 + 0x2C + 0x00000000 + + + DELAY2 + Delay2 Register + 0x30 + 0x20 + read-write + 0x00000000 + + + DELAY2BYTE[%s] + Delay2 Register by Byte + DELAY2 + 0x30 + 0x00000000 + + + IRQ_SEN + Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive) + 0x34 + 0x00000000 + + + IRQ_EDGE + Interrupt Both Edge Register (1:Both Edges, 0:Single Edge) + 0x38 + 0x00000000 + + + IRQ_EVT + Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) + 0x3C + 0x00000000 + + + IRQ_ENB + Interrupt Enable Register + 0x40 + 0x00000000 + + + IRQ_RAW + Raw Interrupt Status + 0x44 + read-only + 0x00000000 + + + IRQ_END + Masked Interrupt Status + 0x48 + read-only + 0x00000000 + + + EDGE_STATUS + Edge Status Register + 0x4C + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0xFFC + 0x20 + read-only + 0x001007E1 + + + + + PORTB + 0x50001000 + + + TIM0 + 1.0 + Timer/Counter Peripheral + Timer_Counter + 0x40020000 + + 0x0 + 0x1000 + registers + + + + CTRL + Control Register + 0x0 + read-write + + + ENABLE + Counter Enable + [0:0] + + + ACTIVE + Counter Active + [1:1] + read-only + + + AUTO_DISABLE + Auto Disables the counter (set ENABLE to 0) when the count reaches 0 + [2:2] + + + AUTO_DEACTIVATE + Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0 + [3:3] + + + IRQ_ENB + Interrupt Enable + [4:4] + + + STATUS_SEL + Counter Status Selection + [7:5] + + + DONE + Single cycle pulse when the counter reaches 0 + 0 + + + ACTIVE + Returns the counter ACTIVE bit + 1 + + + TOGGLE + Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output. + 2 + + + PWMA + Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE + 3 + + + PWMB + Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE + 4 + + + ENABLED + Returns the counter ENABLED bit + 5 + + + PWMA_ACTIVE + Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0 + 6 + + + + + STATUS_INV + Invert the Output Status + [8:8] + + + REQ_STOP + Stop Request + [9:9] + + + + + RST_VALUE + The value that counter start from after reaching 0. + 0x4 + + + CNT_VALUE + The current value of the counter + 0x8 + + + ENABLE + Alternate access to the Counter ENABLE bit in the CTRL Register + 0xC + + + ENABLE + Counter Enable + [0:0] + + + + + CSD_CTRL + The Cascade Control Register. Controls the counter external enable signals + 0x10 + + + CSDEN0 + Cascade 0 Enable + [0:0] + + + CSDINV0 + Cascade 0 Invert + [1:1] + + + CSDEN1 + Cascade 1 Enable + [2:2] + + + CSDINV1 + Cascade 1 Invert + [3:3] + + + DCASOP + Dual Cascade Operation (0:AND, 1:OR) + [4:4] + + + CSDTRG0 + Cascade 0 Enabled as Trigger + [6:6] + + + CSDTRG1 + Cascade 1 Enabled as Trigger + [7:7] + + + CSDEN2 + Cascade 2 Enable + [8:8] + + + CSDINV2 + Cascade 2 Invert + [9:9] + + + CSDXXX2 + Cascade 2 test mode + [11:11] + + + CSDTRG2 + Cascade 2 Enabled as Trigger + 10 + 1 + + + + + CASCADE0 + Cascade Enable Selection + 0x14 + + + CASSEL + Cascade Selection + [7:0] + + + + + CASCADE1 + Cascade Enable Selection + 0x18 + + + CASCADE2 + Cascade Enable Selection + 0x1C + + + PWM_VALUE + The Pulse Width Modulation Value + 0x20 + + + PWMA_VALUE + The Pulse Width Modulation ValueA + PWM_VALUE + 0x20 + + + PWMB_VALUE + The Pulse Width Modulation ValueB + 0x24 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x001107E1 + + + + + TIM1 + 0x40021000 + + + TIM2 + 0x40022000 + + + TIM3 + 0x40023000 + + + TIM4 + 0x40024000 + + + TIM5 + 0x40025000 + + + TIM6 + 0x40026000 + + + TIM7 + 0x40027000 + + + TIM8 + 0x40028000 + + + TIM9 + 0x40029000 + + + TIM10 + 0x4002A000 + + + TIM11 + 0x4002B000 + + + TIM12 + 0x4002C000 + + + TIM13 + 0x4002D000 + + + TIM14 + 0x4002E000 + + + TIM15 + 0x4002F000 + + + TIM16 + 0x40030000 + + + TIM17 + 0x40031000 + + + TIM18 + 0x40032000 + + + TIM19 + 0x40033000 + + + TIM20 + 0x40034000 + + + TIM21 + 0x40035000 + + + TIM22 + 0x40036000 + + + TIM23 + 0x40037000 + + + UARTA + 1.0 + UART Peripheral + UART + 0x40040000 + + 0x0 + 0x1000 + registers + + + + DATA + Data In/Out Register + 0x0 + 0x00000000 + + + ENABLE + Enable Register + 0x4 + 0x00000000 + + + RXENABLE + Rx Enable + [0:0] + + + TXENABLE + Tx Enable + [1:1] + + + + + CTRL + Control Register + 0x8 + 0x00000000 + + + PAREN + Parity Enable + [0:0] + + + PAREVEN + Parity Even/Odd(1/0) + [1:1] + + + PARSTK + Parity Sticky + [2:2] + + + STOPBITS + Stop Bits 1/2(0/1) + [3:3] + + + WORDSIZE + Word Size in Bits 5/6/7/8(00/01/10/11) + [5:4] + + + LOOPBACK + Loopback Enable + [6:6] + + + LOOPBACKBLK + Loopback Block + [7:7] + + + AUTOCTS + Enable Auto CTS mode + [8:8] + + + DEFRTS + Default RTSn value + [9:9] + + + AUTORTS + Enable Auto RTS mode + [10:10] + + + BAUD8 + Enable BAUD8 mode + [11:11] + + + + + CLKSCALE + Clock Scale Register + 0xC + 0x00000000 + + + FRAC + Fractional Divide (64ths) + [5:0] + + + INT + Integer Divide + [23:6] + + + RESET + Reset Baud Counter + [31:31] + write-only + + + + + RXSTATUS + Status Register + 0x10 + read-only + 0x00000000 + + + RDAVL + Read Data Available + [0:0] + + + RDNFULL + Read Fifo NOT Full + [1:1] + + + RXBUSY + RX Busy Receiving + [2:2] + + + RXTO + RX Receive Timeout + [3:3] + + + RXOVR + Read Fifo Overflow + [4:4] + + + RXFRM + RX Framing Error + [5:5] + + + RXPAR + RX Parity Error + [6:6] + + + RXBRK + RX Break Error + [7:7] + + + RXBUSYBRK + RX Busy Receiving Break + [8:8] + + + RXADDR9 + Address Match for 9 bit mode + [9:9] + + + RXRTSN + RX RTSn Output Value + [15:15] + + + + + TXSTATUS + Status Register + 0x14 + read-only + 0x00000000 + + + WRRDY + Write Fifo NOT Full + [0:0] + + + WRBUSY + Write Fifo Full + [1:1] + + + TXBUSY + TX Busy Transmitting + [2:2] + + + WRLOST + Write Data Lost (Fifo Overflow) + [3:3] + + + TXCTSN + TX CTSn Input Value + [15:15] + + + + + FIFO_CLR + Clear FIFO Register + 0x18 + write-only + 0x00000000 + + + RXSTS + Clear Rx Status + [0:0] + + + TXSTS + Clear Tx Status + [1:1] + + + RXFIFO + Clear Rx FIFO + [2:2] + + + TXFIFO + Clear Tx FIFO + [3:3] + + + + + TXBREAK + Break Transmit Register + 0x1C + write-only + 0x00000000 + + + ADDR9 + Address9 Register + 0x20 + read-write + 0x00000000 + + + ADDR9MASK + Address9 Mask Register + 0x24 + read-write + 0x00000000 + + + IRQ_ENB + IRQ Enable Register + 0x28 + read-write + 0x00000000 + + + IRQ_RX + RX Interrupt + [0:0] + + + IRQ_RX_STATUS + RX Status Interrupt + [1:1] + + + IRQ_RX_TO + RX Timeout Interrupt + [2:2] + + + IRQ_TX + TX Interrupt + [4:4] + + + IRQ_TX_STATUS + TX Status Interrupt + [5:5] + + + IRQ_TX_EMPTY + TX Empty Interrupt + [6:6] + + + IRQ_TX_CTS + TX CTS Change Interrupt + [7:7] + + + + + IRQ_RAW + IRQ Raw Status Register + 0x2C + read-only + 0x00000000 + + + IRQ_END + IRQ Enabled Status Register + 0x30 + read-only + 0x00000000 + + + IRQ_CLR + IRQ Clear Status Register + 0x34 + write-only + 0x00000000 + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x38 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x3C + + + RXFIFORTSTRG + Rx FIFO RTS Trigger Level + 0x40 + + + STATE + Internal STATE of UART Controller + 0x44 + 0x20 + read-only + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x001207E1 + + + + + UARTB + 0x40041000 + + + SPIA + 1.0 + SPI Peripheral + SPI + 0x40050000 + + 0x0 + 0x1000 + registers + + + + CTRL0 + Control Register 0 + 0x0 + 0x00000000 + + + SIZE + Data Size(0x3=>4, 0xf=>16) + [3:0] + + + SPO + SPI Clock Polarity + [6:6] + + + SPH + SPI Clock Phase + [7:7] + + + SCRDV + Serial Clock Rate divide+1 value + [15:8] + + + + + CTRL1 + Control Register 1 + 0x4 + 0x00000000 + + + LBM + Loop Back + [0:0] + + + ENABLE + Enable + [1:1] + + + MS + Master/Slave (0:Master, 1:Slave) + [2:2] + + + SOD + Slave output Disable + [3:3] + + + SS + Slave Select + [6:4] + + + BLOCKMODE + Block Mode Enable + [7:7] + + + BMSTART + Block Mode Start Status Enable + [8:8] + + + BMSTALL + Block Mode Stall Enable + [9:9] + + + MDLYCAP + Master Delayed Capture Enable + [10:10] + + + MTXPAUSE + Master Tx Pause Enable + [11:11] + + + + + DATA + Data Input/Output + 0x8 + + + STATUS + Status Register + 0xC + read-only + 0x00000000 + + + TFE + Transmit FIFO empty + [0:0] + + + TNF + Transmit FIFO not full + [1:1] + + + RNE + Receive FIFO not empty + [2:2] + + + RFF + Receive FIFO Full + [3:3] + + + BUSY + Busy + [4:4] + + + RXDATAFIRST + Pending Data is first Byte in BLOCKMODE + [5:5] + + + RXTRIGGER + RX FIFO Above Trigger Level + [6:6] + + + TXTRIGGER + TX FIFO Below Trigger Level + [7:7] + + + + + CLKPRESCALE + Clock Pre Scale divide value + 0x10 + + + IRQ_ENB + Interrupt Enable Register + 0x14 + read-write + 0x00000000 + + + RORIM + RX Overrun + [0:0] + + + RTIM + RX Timeout + [1:1] + + + RXIM + RX Fifo is at least half full + [2:2] + + + TXIM + TX Fifo is at least half empty + [3:3] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x18 + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x1C + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x20 + write-only + oneToClear + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x24 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x28 + + + FIFO_CLR + Clear FIFO Register + 0x2C + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + STATE + Internal STATE of SPI Controller + 0x30 + read-only + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x001207E1 + + + + + SPIB + 0x40051000 + + + SPIC + 0x40052000 + + + I2CA + 1.0 + I2C Peripheral + I2C + 0x40060000 + + 0x0 + 0x1000 + registers + + + + CTRL + Control Register + 0x0 + 0x00000000 + + + CLKENABLED + I2C CLK Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + ALGFILTER + Enable Input Analog Glitch Filter + [5:5] + + + DLGFILTER + Enable Input Digital Glitch Filter + [6:6] + + + LOOPBACK + Enable LoopBack Mode + [8:8] + + + TMCONFIGENB + Enable Timing Config Register + [9:9] + + + + + CLKSCALE + Clock Scale divide value + 0x4 + + + VALUE + Enable FastMode + [30:0] + + + FASTMODE + Enable FastMode + [31:31] + + + + + WORDS + Word Count value + 0x8 + + + ADDRESS + I2C Address value + 0xC + + + DATA + Data Input/Output + 0x10 + + + CMD + Command Register + 0x14 + + + STATUS + I2C Controller Status Register + 0x18 + read-only + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + I2C_IDLE + I2C bus is Idle + 0 + 1 + + + IDLE + Controller is Idle + 1 + 1 + + + + + STATE + Internal STATE of I2C Master Controller + 0x1C + read-only + + + TXCOUNT + TX Count Register + 0x20 + read-only + + + RXCOUNT + RX Count Register + 0x24 + read-only + + + IRQ_ENB + Interrupt Enable Register + 0x28 + read-write + 0x00000000 + + + I2CIDLE + I2C Bus is Idle + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + CLKLOTO + I2C Clock Low Timeout + [7:7] + + + TXOVERFLOW + TX FIFO Overflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x2C + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x30 + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x34 + write-only + oneToClear + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x38 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x3C + + + FIFO_CLR + Clear FIFO Register + 0x40 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TMCONFIG + Timing Config Register + 0x44 + + + CLKTOLIMIT + Clock Low Timeout Limit Register + 0x48 + + + S0_CTRL + Slave Control Register + 0x100 + 0x00000000 + + + CLKENABLED + I2C Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + + + S0_MAXWORDS + Slave MaxWords Register + 0x104 + + + S0_ADDRESS + Slave I2C Address Value + 0x108 + + + S0_ADDRESSMASK + Slave I2C Address Mask value + 0x10C + + + S0_DATA + Slave Data Input/Output + 0x110 + + + S0_LASTADDRESS + Slave I2C Last Address value + 0x114 + read-only + + + S0_STATUS + Slave I2C Controller Status Register + 0x118 + read-only + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_BUSY + I2C Raw Busy value + [29:29] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + S0_STATE + Internal STATE of I2C Slave Controller + 0x11C + read-only + + + S0_TXCOUNT + Slave TX Count Register + 0x120 + read-only + + + S0_RXCOUNT + Slave RX Count Register + 0x124 + read-only + + + S0_IRQ_ENB + Slave Interrupt Enable Register + 0x128 + read-write + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + I2C_START + I2C Start Condition + [8:8] + + + I2C_STOP + I2C Stop Condition + [9:9] + + + TXUNDERFLOW + TX FIFO Underflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + S0_IRQ_RAW + Slave Raw Interrupt Status Register + 0x12C + read-only + + + S0_IRQ_END + Slave Enabled Interrupt Status Register + 0x130 + read-only + + + S0_IRQ_CLR + Slave Clear Interrupt Status Register + 0x134 + write-only + oneToClear + + + S0_RXFIFOIRQTRG + Slave Rx FIFO IRQ Trigger Level + 0x138 + + + S0_TXFIFOIRQTRG + Slave Tx FIFO IRQ Trigger Level + 0x13C + + + S0_FIFO_CLR + Slave Clear FIFO Register + 0x140 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + S0_ADDRESSB + Slave I2C Address B Value + 0x144 + + + S0_ADDRESSMASKB + Slave I2C Address B Mask value + 0x148 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x001407E1 + + + + + I2CB + 0x40061000 + + + \ No newline at end of file diff --git a/va108xx/vorago-reb1/.cargo/config.toml b/va108xx/vorago-reb1/.cargo/config.toml new file mode 100644 index 0000000..dd54ddd --- /dev/null +++ b/va108xx/vorago-reb1/.cargo/config.toml @@ -0,0 +1,36 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# uncomment ONE of these three option to make `cargo run` start a GDB session +# which option to pick depends on your system +# runner = "arm-none-eabi-gdb -q -x jlink.gdb" +# runner = "gdb-multiarch -q -x jlink.gdb" +# runner = "gdb -q -x openocd.gdb" + +rustflags = [ + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", + + # LLD (shipped with the Rust toolchain) is used as the default linker + "-C", "link-arg=-Tlink.x", + + # if you run into problems with LLD switch to the GNU linker by commenting out + # this line + # "-C", "linker=arm-none-eabi-ld", + + # if you need to link to pre-compiled C libraries provided by a C toolchain + # use GCC as the linker by commenting out both lines above and then + # uncommenting the three lines below + # "-C", "linker=arm-none-eabi-gcc", + # "-C", "link-arg=-Wl,-Tlink.x", + # "-C", "link-arg=-nostartfiles", +] + +[build] +# Pick ONE of these compilation targets +target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) +# target = "thumbv8m.base-none-eabi" # Cortex-M23 +# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU) +# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU) \ No newline at end of file diff --git a/va108xx/vorago-reb1/.github/bors.toml b/va108xx/vorago-reb1/.github/bors.toml new file mode 100644 index 0000000..1779788 --- /dev/null +++ b/va108xx/vorago-reb1/.github/bors.toml @@ -0,0 +1,2 @@ +status = ["ci"] +delete_merged_branches = true diff --git a/va108xx/vorago-reb1/.github/workflows/ci.yml b/va108xx/vorago-reb1/.github/workflows/ci.yml new file mode 100644 index 0000000..8caa486 --- /dev/null +++ b/va108xx/vorago-reb1/.github/workflows/ci.yml @@ -0,0 +1,65 @@ +on: [push] + +name: ci + +jobs: + check: + name: Check + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + target: thumbv6m-none-eabi + override: true + - uses: actions-rs/cargo@v1 + with: + command: check + - uses: actions-rs/cargo@v1 + with: + command: check + args: --examples + + fmt: + name: Rustfmt + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + override: true + - run: rustup component add rustfmt + - uses: actions-rs/cargo@v1 + with: + command: fmt + args: --all -- --check + + clippy: + name: Clippy + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + target: thumbv6m-none-eabi + override: true + - run: rustup component add clippy + - uses: actions-rs/cargo@v1 + with: + command: clippy + args: -- -D warnings + + ci: + if: ${{ success() }} + # all new jobs must be added to this list + needs: [check, fmt, clippy] + runs-on: ubuntu-latest + steps: + - name: CI succeeded + run: exit 0 \ No newline at end of file diff --git a/va108xx/vorago-reb1/.gitignore b/va108xx/vorago-reb1/.gitignore new file mode 100644 index 0000000..22d3516 --- /dev/null +++ b/va108xx/vorago-reb1/.gitignore @@ -0,0 +1,15 @@ +# Generated by Cargo +# will have compiled files and executables +/target/ + +# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries +# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html +Cargo.lock + +# These are backup files generated by rustfmt +**/*.rs.bk + + +# Added by cargo + +/target diff --git a/va108xx/vorago-reb1/CHANGELOG.md b/va108xx/vorago-reb1/CHANGELOG.md new file mode 100644 index 0000000..95d560c --- /dev/null +++ b/va108xx/vorago-reb1/CHANGELOG.md @@ -0,0 +1,74 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +## [unreleased] + +## [v0.9.0] 2025-09-03 + +- Bumped `va108xx-hal` dependency to 0.12 + +## [v0.8.1] 2025-03-07 + +- Bumped allowed `va108xx-hal` dependency to 0.11 +- Bumped `bitfield` dependency + +## [v0.8.0] 2025-02-17 + +- Bumped `va108xx-hal` dependency to 0.10 + +## [v0.7.0] 2025-02-13 + +- Bumped `va108xx-hal` dependency to 0.9 +- Minor adjustments to `Button` API. +- `Button`, `Led` and `Leds` now simply wrap a type using a tuple struct. + +## [v0.6.0] 2024-09-30 + +- Added M95M01 EEPROM module/API +- Update `va108xx-hal` dependency to range >=v0.8, <0.9 + +## [v0.5.1] 2024-07-04 + +- Update `va108xx-hal` dependency to v0.7.0 + +## [v0.5.0] 2024-06-16 + +- Updated `va108xx` to v0.3.0 and `va108xx-hal` dependency to v0.6.0 + +## [v0.4.0] + +- Update manifest file to have correct links and license +- Update some dependencies + - `cortex-m-rtic` (dev-depencency) to 1.1.2 + - Other dependencies: Only revision has changed + +## [v0.3.2] + +- Bump HAL dependency to v0.5.0. Changed API, especially for IRQ handling + +## [v0.3.1] + +- Updated ADC code and dependency + +## [v0.3.0] + +- Completed baseline features to support all sensors on the REB1 sevice +- Relicensed as Apache-2.0 and moved to https://egit.irs.uni-stuttgart.de/rust/vorago-reb1 + +## [v0.2.3] + +- Added basic accelerometer example. Board in not populated so it is not complete, but + it provides a starting point +- Added ADC base library and example building on the new max116xx-10bit device driver crate + +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.9.0...HEAD +[v0.9.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.8.1...vorago-reb1-v0.9.0 +[v0.8.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.8.0...vorago-reb1-v0.8.1 +[v0.8.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.7.0...vorago-reb1-v0.8.0 +[v0.7.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.6.0...vorago-reb1-v0.7.0 +[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.5.0...vorago-reb1-v0.6.0 diff --git a/va108xx/vorago-reb1/Cargo.toml b/va108xx/vorago-reb1/Cargo.toml new file mode 100644 index 0000000..626a6d1 --- /dev/null +++ b/va108xx/vorago-reb1/Cargo.toml @@ -0,0 +1,37 @@ +[package] +name = "vorago-reb1" +version = "0.9.0" +authors = ["Robin Mueller "] +edition = "2021" +description = "Board Support Crate for the Vorago REB1 development board" +homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs" +repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs" +license = "Apache-2.0" +keywords = ["no-std", "reb1", "cortex-m", "vorago", "va108xx"] +categories = ["aerospace", "embedded", "no-std", "hardware-support"] + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +cortex-m-rt = "0.7" +embedded-hal = "1" +nb = "1" +bitbybit = "1.3" +arbitrary-int = "2" +max116xx-10bit = "0.3" + +va108xx-hal = { version = "0.12", features = ["rt"] } + +[features] +rt = ["va108xx-hal/rt"] + +[dev-dependencies] +panic-halt = "1" +nb = "1" +rtt-target = "0.6" +panic-rtt-target = "0.2" +embedded-hal-bus = "0.3" +dummy-pin = "1" + +[package.metadata.docs.rs] +all-features = true +rustdoc-args = ["--generate-link-to-definition"] diff --git a/va108xx/vorago-reb1/LICENSE-APACHE b/va108xx/vorago-reb1/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va108xx/vorago-reb1/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va108xx/vorago-reb1/NOTICE b/va108xx/vorago-reb1/NOTICE new file mode 100644 index 0000000..d23e5ce --- /dev/null +++ b/va108xx/vorago-reb1/NOTICE @@ -0,0 +1,3 @@ +Rust Board Support Package (HAL) crate for the Vorago REB1 development board + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va108xx/vorago-reb1/README.md b/va108xx/vorago-reb1/README.md new file mode 100644 index 0000000..546c490 --- /dev/null +++ b/va108xx/vorago-reb1/README.md @@ -0,0 +1,10 @@ +[![Crates.io](https://img.shields.io/crates/v/vorago-reb1)](https://crates.io/crates/vorago-reb1) +[![docs.rs](https://img.shields.io/docsrs/vorago-reb1)](https://docs.rs/vorago-reb1) + +# Rust BSP for the Vorago REB1 development board + +This is the Rust **B**oard **S**upport **P**ackage crate for the Vorago REB1 development board. +Its aim is to provide drivers for the board features of the REB1 board + +The BSP builds on top of the [HAL crate for VA108xx devices](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-hal). +The example folder contains some example applications using the on-board peripherals. diff --git a/va108xx/vorago-reb1/automation/Dockerfile b/va108xx/vorago-reb1/automation/Dockerfile new file mode 100644 index 0000000..5fb8a3d --- /dev/null +++ b/va108xx/vorago-reb1/automation/Dockerfile @@ -0,0 +1,11 @@ +# Run the following commands from root directory to build and run locally +# docker build -f automation/Dockerfile -t . +# docker run -it +FROM rust:latest +RUN apt-get update +RUN apt-get --yes upgrade +# tzdata is a dependency, won't install otherwise +ARG DEBIAN_FRONTEND=noninteractive + +RUN rustup target add thumbv6m-none-eabi && \ + rustup component add rustfmt clippy diff --git a/va108xx/vorago-reb1/automation/Jenkinsfile b/va108xx/vorago-reb1/automation/Jenkinsfile new file mode 100644 index 0000000..c67b034 --- /dev/null +++ b/va108xx/vorago-reb1/automation/Jenkinsfile @@ -0,0 +1,50 @@ +pipeline { + agent any + + stages { + stage('Clippy') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo clippy' + } + } + stage('Rustfmt') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo fmt' + } + } + stage('Check') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo check --target thumbv6m-none-eabi' + } + } + stage('Check Examples') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo check --target thumbv6m-none-eabi --examples' + } + } + } +} \ No newline at end of file diff --git a/va108xx/vorago-reb1/examples/adt75-temp-sensor.rs b/va108xx/vorago-reb1/examples/adt75-temp-sensor.rs new file mode 100644 index 0000000..47b04c5 --- /dev/null +++ b/va108xx/vorago-reb1/examples/adt75-temp-sensor.rs @@ -0,0 +1,25 @@ +#![no_main] +#![no_std] +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va108xx_hal::{pac, prelude::*, timer::CountdownTimer}; +use vorago_reb1::temp_sensor::Adt75TempSensor; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("-- Vorago Temperature Sensor and I2C Example --"); + let dp = pac::Peripherals::take().unwrap(); + let mut delay = CountdownTimer::new(dp.tim0, 50.MHz()); + let mut temp_sensor = + Adt75TempSensor::new(50.MHz(), dp.i2ca).expect("Creating temperature sensor struct failed"); + loop { + let temp = temp_sensor + .read_temperature() + .expect("Failed reading temperature"); + rprintln!("Temperature in Celcius: {}", temp); + delay.delay_ms(500); + } +} diff --git a/va108xx/vorago-reb1/examples/adxl343-accelerometer.rs b/va108xx/vorago-reb1/examples/adxl343-accelerometer.rs new file mode 100644 index 0000000..7a00793 --- /dev/null +++ b/va108xx/vorago-reb1/examples/adxl343-accelerometer.rs @@ -0,0 +1,66 @@ +//! ADXL343 accelerometer example +//! +//! Please note that the default REB1 board is not populated with the ADXL343BCCZ-RL7. +//! To use this example, this chip needs to be soldered onto the board. +#![no_main] +#![no_std] +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use embedded_hal::spi::{SpiBus, MODE_3}; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va108xx_hal::gpio::{Output, PinState}; +use va108xx_hal::pins::PinsA; +use va108xx_hal::spi::{configure_pin_as_hw_cs_pin, SpiClockConfig}; +use va108xx_hal::timer::CountdownTimer; +use va108xx_hal::{ + pac, + prelude::*, + spi::{Spi, SpiConfig}, +}; + +const READ_MASK: u8 = 1 << 7; +const _MULTI_BYTE_MASK: u8 = 1 << 6; +const DEVID_REG: u8 = 0x00; + +const POWER_CTL_REG: u8 = 0x2D; +const PWR_MEASUREMENT_MODE_MASK: u8 = 1 << 3; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("-- Vorago Accelerometer Example --"); + let dp = pac::Peripherals::take().unwrap(); + let pinsa = PinsA::new(dp.porta); + let mut delay = CountdownTimer::new(dp.tim0, 50.MHz()); + let (sck, mosi, miso) = (pinsa.pa20, pinsa.pa19, pinsa.pa18); + let cs_pin = pinsa.pa16; + let hw_cs_id = configure_pin_as_hw_cs_pin(cs_pin); + + // Need to set the ADC chip select low + Output::new(pinsa.pa17, PinState::Low); + + let spi_cfg = SpiConfig::default() + .clk_cfg( + SpiClockConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed"), + ) + .mode(MODE_3) + .slave_output_disable(true); + let mut spi = Spi::new(dp.spib, (sck, miso, mosi), spi_cfg).unwrap(); + spi.cfg_hw_cs(hw_cs_id); + + let mut tx_rx_buf: [u8; 3] = [0; 3]; + tx_rx_buf[0] = READ_MASK | DEVID_REG; + spi.transfer_in_place(&mut tx_rx_buf[0..2]) + .expect("Reading DEVID register failed"); + rprintln!("DEVID register: {}", tx_rx_buf[1]); + + tx_rx_buf[0] = POWER_CTL_REG; + tx_rx_buf[1] = PWR_MEASUREMENT_MODE_MASK; + spi.write(&tx_rx_buf[0..2]) + .expect("Enabling measurement mode failed"); + + loop { + delay.delay_ms(500); + } +} diff --git a/va108xx/vorago-reb1/examples/blinky-button-irq.rs b/va108xx/vorago-reb1/examples/blinky-button-irq.rs new file mode 100644 index 0000000..d99e5ba --- /dev/null +++ b/va108xx/vorago-reb1/examples/blinky-button-irq.rs @@ -0,0 +1,89 @@ +//! Blinky button application for the REB1 board +#![no_main] +#![no_std] + +use core::cell::RefCell; + +use cortex_m::interrupt::Mutex; +use cortex_m_rt::entry; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va108xx_hal::{ + clock::{set_clk_div_register, FilterClockSelect}, + gpio::{FilterType, InterruptEdge}, + pac::{self, interrupt}, + pins::PinsA, + timer::InterruptConfig, +}; +use vorago_reb1::button::Button; +use vorago_reb1::leds::Leds; + +static LEDS: Mutex>> = Mutex::new(RefCell::new(None)); +static BUTTON: Mutex>> = Mutex::new(RefCell::new(None)); + +#[derive(Debug, PartialEq)] +pub enum PressMode { + Toggle, + Keep, +} + +// You can change the press mode here +const PRESS_MODE: PressMode = PressMode::Keep; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("-- Vorago Button IRQ Example --"); + let mut dp = pac::Peripherals::take().unwrap(); + let pinsa = PinsA::new(dp.porta); + let edge_irq = match PRESS_MODE { + PressMode::Toggle => InterruptEdge::HighToLow, + PressMode::Keep => InterruptEdge::BothEdges, + }; + + // Configure an edge interrupt on the button and route it to interrupt vector 15 + let mut button = Button::new(pinsa.pa11); + + if PRESS_MODE == PressMode::Toggle { + // This filter debounces the switch for edge based interrupts + button.configure_filter_type(FilterType::FilterFourCycles, FilterClockSelect::Clk1); + set_clk_div_register(&mut dp.sysconfig, FilterClockSelect::Clk1, 50_000); + } + button.configure_and_enable_edge_interrupt( + edge_irq, + InterruptConfig::new(pac::interrupt::OC15, true, true), + ); + + let mut leds = Leds::new(pinsa.pa10, pinsa.pa7, pinsa.pa6); + for led in leds.iter_mut() { + led.off(); + } + // Make both button and LEDs accessible from the IRQ handler as well + cortex_m::interrupt::free(|cs| { + LEDS.borrow(cs).replace(Some(leds)); + BUTTON.borrow(cs).replace(Some(button)); + }); + loop { + cortex_m::asm::nop(); + } +} + +#[interrupt] +fn OC15() { + cortex_m::interrupt::free(|cs| { + if PRESS_MODE == PressMode::Toggle { + if let Some(ref mut leds) = LEDS.borrow(cs).borrow_mut().as_deref_mut() { + leds[0].toggle(); + } + } else if let (Some(ref mut leds), Some(ref mut button)) = ( + LEDS.borrow(cs).borrow_mut().as_deref_mut(), + BUTTON.borrow(cs).borrow_mut().as_mut(), + ) { + if button.released() { + leds[0].off(); + } else { + leds[0].on(); + } + } + }); +} diff --git a/va108xx/vorago-reb1/examples/blinky-leds.rs b/va108xx/vorago-reb1/examples/blinky-leds.rs new file mode 100644 index 0000000..6ec3032 --- /dev/null +++ b/va108xx/vorago-reb1/examples/blinky-leds.rs @@ -0,0 +1,111 @@ +//! Blinky examples using the PAC directly, the HAL, or the BSP +//! +//! Additional note on LEDs: +//! Be not afraid: Pulling the GPIOs low makes the LEDs blink. See REB1 +//! schematic for more details. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use panic_halt as _; +use va108xx_hal::{ + gpio::{Output, PinState}, + pac, + pins::PinsA, + prelude::*, + timer::CountdownTimer, +}; +use vorago_reb1::leds::Leds; + +// REB LED pin definitions. All on port A +const LED_D2: u32 = 1 << 10; +const LED_D3: u32 = 1 << 7; +const LED_D4: u32 = 1 << 6; + +#[allow(dead_code)] +enum LibType { + Pac, + Hal, + Bsp, +} + +#[entry] +fn main() -> ! { + let dp = pac::Peripherals::take().unwrap(); + + let lib_type = LibType::Bsp; + + match lib_type { + LibType::Pac => { + // Enable all peripheral clocks + dp.sysconfig + .peripheral_clk_enable() + .modify(|_, w| unsafe { w.bits(0xffffffff) }); + dp.porta + .dir() + .modify(|_, w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + dp.porta + .datamask() + .modify(|_, w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + for _ in 0..10 { + dp.porta + .clrout() + .write(|w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + cortex_m::asm::delay(5_000_000); + dp.porta + .setout() + .write(|w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + cortex_m::asm::delay(5_000_000); + } + loop { + dp.porta + .togout() + .write(|w| unsafe { w.bits(LED_D2 | LED_D3 | LED_D4) }); + cortex_m::asm::delay(25_000_000); + } + } + LibType::Hal => { + let pins = PinsA::new(dp.porta); + let mut led1 = Output::new(pins.pa10, PinState::Low); + let mut led2 = Output::new(pins.pa7, PinState::Low); + let mut led3 = Output::new(pins.pa6, PinState::Low); + let mut delay = CountdownTimer::new(dp.tim0, 50.MHz()); + for _ in 0..10 { + led1.set_low(); + led2.set_low(); + led3.set_low(); + delay.delay_ms(200); + led1.set_high(); + led2.set_high(); + led3.set_high(); + delay.delay_ms(200); + } + loop { + led1.toggle(); + delay.delay_ms(200); + led2.toggle(); + delay.delay_ms(200); + } + } + LibType::Bsp => { + let pinsa = PinsA::new(dp.porta); + let mut leds = Leds::new(pinsa.pa10, pinsa.pa7, pinsa.pa6); + let mut delay = CountdownTimer::new(dp.tim0, 50.MHz()); + for _ in 0..10 { + // Blink all LEDs quickly + for led in leds.iter_mut() { + led.toggle(); + } + delay.delay_ms(500); + } + // Now use a wave pattern + loop { + for led in leds.iter_mut() { + led.toggle(); + delay.delay_ms(200); + } + } + } + } +} diff --git a/va108xx/vorago-reb1/examples/max11619-adc.rs b/va108xx/vorago-reb1/examples/max11619-adc.rs new file mode 100644 index 0000000..99adedc --- /dev/null +++ b/va108xx/vorago-reb1/examples/max11619-adc.rs @@ -0,0 +1,328 @@ +//! MAX11619 ADC example application. +//! +//! You can turn the potentiometer knob of the REB1 board to measure +//! different ADC values. +#![no_main] +#![no_std] + +use core::convert::Infallible; + +use cortex_m_rt::entry; +use embedded_hal::spi::{SpiBus, SpiDevice, MODE_0}; +use embedded_hal::{delay::DelayNs, spi}; +use max116xx_10bit::VoltageRefMode; +use max116xx_10bit::{AveragingConversions, AveragingResults}; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va108xx_hal::gpio::{Input, Output, PinState, Port}; +use va108xx_hal::pins::PinsA; +use va108xx_hal::spi::{configure_pin_as_hw_cs_pin, SpiClockConfig}; +use va108xx_hal::timer::CountdownTimer; +use va108xx_hal::{ + pac, + prelude::*, + spi::{HwChipSelectId, Spi, SpiConfig}, +}; +use va108xx_hal::{port_function_select, FunctionSelect}; +use vorago_reb1::max11619::{ + max11619_externally_clocked_no_wakeup, max11619_externally_clocked_with_wakeup, + max11619_internally_clocked, AN2_CHANNEL, POTENTIOMETER_CHANNEL, +}; + +#[derive(Debug, PartialEq, Copy, Clone)] +pub enum ExampleMode { + UsingEoc, + NotUsingEoc, + NotUsingEocWithDelay, +} + +#[derive(Debug, PartialEq, Copy, Clone)] +pub enum ReadMode { + Single, + Multiple, + MultipleNToHighest, + AverageN, +} + +#[derive(Debug, PartialEq, Copy, Clone)] +pub enum MuxMode { + None, + PortB19to17, +} + +const EXAMPLE_MODE: ExampleMode = ExampleMode::NotUsingEoc; +const READ_MODE: ReadMode = ReadMode::Multiple; +const MUX_MODE: MuxMode = MuxMode::None; + +// This is probably more or less a re-implementation of https://docs.rs/embedded-hal-bus/latest/embedded_hal_bus/spi/struct.ExclusiveDevice.html. +// Users should look at the embedded-hal-bus crate for sharing the bus. +pub struct SpiWithHwCs { + inner: Spi, + delay_provider: Delay, + hw_cs_id: HwChipSelectId, +} + +impl SpiWithHwCs { + pub fn new(spi: Spi, hw_cs_id: HwChipSelectId, delay_provider: Delay) -> Self { + Self { + inner: spi, + hw_cs_id, + delay_provider, + } + } +} + +impl embedded_hal::spi::ErrorType for SpiWithHwCs { + type Error = Infallible; +} + +impl SpiDevice for SpiWithHwCs { + fn transaction( + &mut self, + operations: &mut [spi::Operation<'_, u8>], + ) -> Result<(), Self::Error> { + // Only the HW CS is configured here. This is not really necessary, but showcases + // that we could scale this multiple SPI devices. + self.inner.cfg_hw_cs(self.hw_cs_id); + for operation in operations { + match operation { + spi::Operation::Read(buf) => self.inner.read(buf).ok().unwrap(), + spi::Operation::Write(buf) => self.inner.write(buf).ok().unwrap(), + spi::Operation::Transfer(read, write) => { + self.inner.transfer(read, write).ok().unwrap() + } + spi::Operation::TransferInPlace(buf) => { + self.inner.transfer_in_place(buf).ok().unwrap() + } + spi::Operation::DelayNs(delay) => self.delay_provider.delay_ns(*delay), + }; + } + self.inner.cfg_hw_cs_disable(); + Ok(()) + } +} + +const SYS_CLK: Hertz = Hertz::from_raw(50_000_000); + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("-- Vorago ADC Example --"); + + let mut dp = pac::Peripherals::take().unwrap(); + let mut delay = CountdownTimer::new(dp.tim0, SYS_CLK); + unsafe { + cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0); + } + + let pinsa = PinsA::new(dp.porta); + let spi_cfg = SpiConfig::default() + .clk_cfg(SpiClockConfig::from_clk(SYS_CLK, 3.MHz()).unwrap()) + .mode(MODE_0) + .blockmode(true); + let (sck, mosi, miso) = (pinsa.pa20, pinsa.pa19, pinsa.pa18); + + if MUX_MODE == MuxMode::PortB19to17 { + port_function_select(&mut dp.ioconfig, Port::B, 19, FunctionSelect::Sel1).ok(); + port_function_select(&mut dp.ioconfig, Port::B, 18, FunctionSelect::Sel2).ok(); + port_function_select(&mut dp.ioconfig, Port::B, 17, FunctionSelect::Sel1).ok(); + port_function_select(&mut dp.ioconfig, Port::B, 16, FunctionSelect::Sel1).ok(); + } + // Set the accelerometer chip select low in case the board slot is populated + Output::new(pinsa.pa16, PinState::Low); + + let hw_cs_id = configure_pin_as_hw_cs_pin(pinsa.pa17); + let spi = Spi::new(dp.spib, (sck, miso, mosi), spi_cfg).unwrap(); + + let delay_spi = CountdownTimer::new(dp.tim1, SYS_CLK); + let spi_with_hwcs = SpiWithHwCs::new(spi, hw_cs_id, delay_spi); + match EXAMPLE_MODE { + ExampleMode::NotUsingEoc => spi_example_externally_clocked(spi_with_hwcs, &mut delay), + ExampleMode::UsingEoc => { + spi_example_internally_clocked( + spi_with_hwcs, + &mut delay, + Input::new_floating(pinsa.pa14), + ); + } + ExampleMode::NotUsingEocWithDelay => { + spi_example_externally_clocked_with_delay(spi_with_hwcs, &mut delay); + } + } +} + +/// Use the SPI clock as the conversion clock +fn spi_example_externally_clocked(spi: impl SpiDevice, delay: &mut impl DelayNs) -> ! { + let mut adc = max11619_externally_clocked_no_wakeup(spi) + .expect("Creating externally clocked MAX11619 device failed"); + if READ_MODE == ReadMode::AverageN { + adc.averaging( + AveragingConversions::FourConversions, + AveragingResults::FourResults, + ) + .expect("Error setting up averaging register"); + } + let mut cmd_buf: [u8; 32] = [0; 32]; + let mut counter = 0; + loop { + rprintln!("-- Measurement {} --", counter); + + match READ_MODE { + ReadMode::Single => { + rprintln!("Reading single potentiometer channel"); + let pot_val = adc + .read_single_channel(&mut cmd_buf, POTENTIOMETER_CHANNEL) + .expect("Creating externally clocked MAX11619 ADC failed"); + rprintln!("Single channel read:"); + rprintln!("\tPotentiometer value: {}", pot_val); + } + ReadMode::Multiple => { + let mut res_buf: [u16; 4] = [0; 4]; + adc.read_multiple_channels_0_to_n( + &mut cmd_buf, + &mut res_buf.iter_mut(), + POTENTIOMETER_CHANNEL, + ) + .expect("Multi-Channel read failed"); + print_res_buf(&res_buf); + } + ReadMode::MultipleNToHighest => { + let mut res_buf: [u16; 2] = [0; 2]; + adc.read_multiple_channels_n_to_highest( + &mut cmd_buf, + &mut res_buf.iter_mut(), + AN2_CHANNEL, + ) + .expect("Multi-Channel read failed"); + rprintln!("Multi channel read from 2 to 3:"); + rprintln!("\tAN2 value: {}", res_buf[0]); + rprintln!("\tAN3 / Potentiometer value: {}", res_buf[1]); + } + ReadMode::AverageN => { + rprintln!("Scanning and averaging not possible for externally clocked mode"); + } + } + counter += 1; + delay.delay_ms(500); + } +} + +fn spi_example_externally_clocked_with_delay(spi: impl SpiDevice, delay: &mut impl DelayNs) -> ! { + let mut adc = + max11619_externally_clocked_with_wakeup(spi).expect("Creating MAX116xx device failed"); + let mut cmd_buf: [u8; 32] = [0; 32]; + let mut counter = 0; + loop { + rprintln!("-- Measurement {} --", counter); + + match READ_MODE { + ReadMode::Single => { + rprintln!("Reading single potentiometer channel"); + let pot_val = adc + .read_single_channel(&mut cmd_buf, POTENTIOMETER_CHANNEL, delay) + .expect("Creating externally clocked MAX11619 ADC failed"); + rprintln!("Single channel read:"); + rprintln!("\tPotentiometer value: {}", pot_val); + } + ReadMode::Multiple => { + let mut res_buf: [u16; 4] = [0; 4]; + adc.read_multiple_channels_0_to_n( + &mut cmd_buf, + &mut res_buf.iter_mut(), + POTENTIOMETER_CHANNEL, + delay, + ) + .expect("Multi-Channel read failed"); + print_res_buf(&res_buf); + } + ReadMode::MultipleNToHighest => { + let mut res_buf: [u16; 2] = [0; 2]; + adc.read_multiple_channels_n_to_highest( + &mut cmd_buf, + &mut res_buf.iter_mut(), + AN2_CHANNEL, + delay, + ) + .expect("Multi-Channel read failed"); + rprintln!("Multi channel read from 2 to 3:"); + rprintln!("\tAN2 value: {}", res_buf[0]); + rprintln!("\tAN3 / Potentiometer value: {}", res_buf[1]); + } + ReadMode::AverageN => { + rprintln!("Scanning and averaging not possible for externally clocked mode"); + } + } + counter += 1; + delay.delay_ms(500); + } +} + +/// This function uses the EOC pin to determine whether the conversion finished +fn spi_example_internally_clocked( + spi: impl SpiDevice, + delay: &mut impl DelayNs, + eoc_pin: Input, +) -> ! { + let mut adc = max11619_internally_clocked( + spi, + eoc_pin, + VoltageRefMode::ExternalSingleEndedNoWakeupDelay, + ) + .expect("Creating MAX116xx device failed"); + let mut counter = 0; + loop { + rprintln!("-- Measurement {} --", counter); + + match READ_MODE { + ReadMode::Single => { + adc.request_single_channel(POTENTIOMETER_CHANNEL) + .expect("Requesting single channel value failed"); + + let pot_val = nb::block!(adc.get_single_channel()) + .expect("Reading single channel value failed"); + rprintln!("\tPotentiometer value: {}", pot_val); + } + ReadMode::Multiple => { + adc.request_multiple_channels_0_to_n(POTENTIOMETER_CHANNEL) + .expect("Requesting single channel value failed"); + let mut res_buf: [u16; 4] = [0; 4]; + nb::block!(adc.get_multi_channel(&mut res_buf.iter_mut())) + .expect("Requesting multiple channel values failed"); + print_res_buf(&res_buf); + } + ReadMode::MultipleNToHighest => { + adc.request_multiple_channels_n_to_highest(AN2_CHANNEL) + .expect("Requesting single channel value failed"); + let mut res_buf: [u16; 4] = [0; 4]; + nb::block!(adc.get_multi_channel(&mut res_buf.iter_mut())) + .expect("Requesting multiple channel values failed"); + rprintln!("Multi channel read from 2 to 3:"); + rprintln!("\tAN2 value: {}", res_buf[0]); + rprintln!("\tAN3 / Potentiometer value: {}", res_buf[1]); + } + ReadMode::AverageN => { + adc.request_channel_n_repeatedly(POTENTIOMETER_CHANNEL) + .expect("Reading channel multiple times failed"); + let mut res_buf: [u16; 16] = [0; 16]; + nb::block!(adc.get_multi_channel(&mut res_buf.iter_mut())) + .expect("Requesting multiple channel values failed"); + rprintln!("Reading potentiometer 4 times"); + rprintln!("\tValue 0: {}", res_buf[0]); + rprintln!("\tValue 1: {}", res_buf[1]); + rprintln!("\tValue 2: {}", res_buf[2]); + rprintln!("\tValue 3: {}", res_buf[3]); + } + } + + counter += 1; + delay.delay_ms(500); + } +} + +fn print_res_buf(buf: &[u16; 4]) { + rprintln!("Multi channel read from 0 to 3:"); + rprintln!("\tAN0 value: {}", buf[0]); + rprintln!("\tAN1 value: {}", buf[1]); + rprintln!("\tAN2 value: {}", buf[2]); + rprintln!("\tAN3 / Potentiometer value: {}", buf[3]); +} diff --git a/va108xx/vorago-reb1/examples/nvm.rs b/va108xx/vorago-reb1/examples/nvm.rs new file mode 100644 index 0000000..fe6f77b --- /dev/null +++ b/va108xx/vorago-reb1/examples/nvm.rs @@ -0,0 +1,57 @@ +//! Example application which interfaces with the boot EEPROM. +#![no_main] +#![no_std] +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va108xx_hal::{pac, spi::SpiClockConfig, time::Hertz, timer::CountdownTimer}; +use vorago_reb1::m95m01::{M95M01, PAGE_SIZE}; + +const CLOCK_FREQ: Hertz = Hertz::from_raw(50_000_000); + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("-- VA108XX REB1 NVM example --"); + + let dp = pac::Peripherals::take().unwrap(); + + let mut delay = CountdownTimer::new(dp.tim0, CLOCK_FREQ); + let clk_config = SpiClockConfig::new(2, 4); + let mut nvm = M95M01::new(dp.spic, clk_config); + let status_reg = nvm.read_status_reg().expect("reading status reg failed"); + if status_reg.zero_segment().value() == 0b111 { + panic!("status register unexpected values"); + } + + let mut orig_content: [u8; 512] = [0; 512]; + let mut read_buf: [u8; 512] = [0; 512]; + let mut write_buf: [u8; 512] = [0; 512]; + for (idx, val) in write_buf.iter_mut().enumerate() { + *val = ((idx as u16) % (u8::MAX as u16 + 1)) as u8; + } + nvm.read(0, &mut orig_content).unwrap(); + + nvm.write_page(0, 0, &[1, 2, 3, 4]).unwrap(); + nvm.read(0, &mut read_buf[0..4]).unwrap(); + + // Read the whole content. Write will internally be split across two page bounaries. + nvm.write(0, &write_buf).unwrap(); + // Memory can be read in one go. + nvm.read(0, &mut read_buf).unwrap(); + assert_eq!(&read_buf, &write_buf); + assert!(nvm.verify(0, &write_buf).unwrap()); + read_buf.fill(0); + + // Write along page boundary + nvm.write(PAGE_SIZE - 2, &write_buf[0..8]).unwrap(); + nvm.read(PAGE_SIZE - 2, &mut read_buf[0..8]).unwrap(); + assert_eq!(&read_buf[0..8], &write_buf[0..8]); + assert!(nvm.verify(PAGE_SIZE - 2, &write_buf[0..8]).unwrap()); + + nvm.write(0, &orig_content).unwrap(); + loop { + delay.delay_ms(500); + } +} diff --git a/va108xx/vorago-reb1/jlink.gdb b/va108xx/vorago-reb1/jlink.gdb new file mode 100644 index 0000000..20ff2d5 --- /dev/null +++ b/va108xx/vorago-reb1/jlink.gdb @@ -0,0 +1,10 @@ +target remote localhost:2331 + +monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va108xx/vorago-reb1/memory.x b/va108xx/vorago-reb1/memory.x new file mode 100644 index 0000000..1ca0e97 --- /dev/null +++ b/va108xx/vorago-reb1/memory.x @@ -0,0 +1,10 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 0x20000 /* 128K */ + RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/va108xx/vorago-reb1/src/button.rs b/va108xx/vorago-reb1/src/button.rs new file mode 100644 index 0000000..f4bd487 --- /dev/null +++ b/va108xx/vorago-reb1/src/button.rs @@ -0,0 +1,59 @@ +//! # API for the REB1 button +//! +//! ## Examples +//! +//! - [Button Blinky with IRQs](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-irq.rs) +//! - [Button Blinky with IRQs and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-rtic.rs) +use va108xx_hal::{ + clock::FilterClockSelect, + gpio::{FilterType, Input, InterruptEdge, InterruptLevel, Pin}, + pins::Pa11, + InterruptConfig, +}; + +#[derive(Debug)] +pub struct Button(pub Input); + +impl Button { + pub fn new(pin: Pin) -> Button { + Button(Input::new_floating(pin)) + } + + #[inline] + pub fn pressed(&mut self) -> bool { + self.0.is_low() + } + + #[inline] + pub fn released(&mut self) -> bool { + self.0.is_high() + } + + /// Configures an IRQ on edge. + pub fn configure_and_enable_edge_interrupt( + &mut self, + edge_type: InterruptEdge, + irq_cfg: InterruptConfig, + ) { + self.0.configure_edge_interrupt(edge_type); + self.0.enable_interrupt(irq_cfg); + } + + /// Configures an IRQ on level. + pub fn configure_and_enable_level_interrupt( + &mut self, + level: InterruptLevel, + irq_cfg: InterruptConfig, + ) { + self.0.configure_level_interrupt(level); + self.0.enable_interrupt(irq_cfg); + } + + /// Configures a filter on the button. This can be useful for debouncing the switch. + /// + /// Please note that you still have to set a clock divisor yourself using the + /// [`va108xx_hal::clock::set_clk_div_register`] function in order for this to work. + pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClockSelect) { + self.0.configure_filter_type(filter, clksel); + } +} diff --git a/va108xx/vorago-reb1/src/leds.rs b/va108xx/vorago-reb1/src/leds.rs new file mode 100644 index 0000000..560e5a2 --- /dev/null +++ b/va108xx/vorago-reb1/src/leds.rs @@ -0,0 +1,75 @@ +//! # API for using the REB1 LEDs +//! +//! ## Examples +//! +//! - [LED example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-leds.rs) +//! - [Button Blinky using IRQs](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-irq.rs) +//! - [Button Blinky using IRQs and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-rtic.rs) +use va108xx_hal::{ + gpio::{Output, PinState}, + pins::{Pa10, Pa6, Pa7, Pin}, +}; + +#[derive(Debug)] +pub struct Leds(pub [Led; 3]); + +impl Leds { + pub fn new(led_pin1: Pin, led_pin2: Pin, led_pin3: Pin) -> Leds { + Leds([ + Led(Output::new(led_pin1, PinState::Low)), + Led(Output::new(led_pin2, PinState::Low)), + Led(Output::new(led_pin3, PinState::Low)), + ]) + } +} + +impl core::ops::Deref for Leds { + type Target = [Led]; + + fn deref(&self) -> &[Led] { + &self.0 + } +} + +impl core::ops::DerefMut for Leds { + fn deref_mut(&mut self) -> &mut [Led] { + &mut self.0 + } +} + +impl core::ops::Index for Leds { + type Output = Led; + + fn index(&self, i: usize) -> &Led { + &self.0[i] + } +} + +impl core::ops::IndexMut for Leds { + fn index_mut(&mut self, i: usize) -> &mut Led { + &mut self.0[i] + } +} + +#[derive(Debug)] +pub struct Led(Output); + +impl Led { + /// Turns the LED off. Setting the pin high actually turns the LED off + #[inline] + pub fn off(&mut self) { + self.0.set_high(); + } + + /// Turns the LED on. Setting the pin low actually turns the LED on + #[inline] + pub fn on(&mut self) { + self.0.set_low(); + } + + /// Toggles the LED + #[inline] + pub fn toggle(&mut self) { + self.0.toggle(); + } +} diff --git a/va108xx/vorago-reb1/src/lib.rs b/va108xx/vorago-reb1/src/lib.rs new file mode 100644 index 0000000..1ccd544 --- /dev/null +++ b/va108xx/vorago-reb1/src/lib.rs @@ -0,0 +1,8 @@ +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] + +pub mod button; +pub mod leds; +pub mod m95m01; +pub mod max11619; +pub mod temp_sensor; diff --git a/va108xx/vorago-reb1/src/m95m01.rs b/va108xx/vorago-reb1/src/m95m01.rs new file mode 100644 index 0000000..eb3778d --- /dev/null +++ b/va108xx/vorago-reb1/src/m95m01.rs @@ -0,0 +1,212 @@ +//! Basic driver for the ST M95M01 EEPROM memory. +//! +//! This driver is used by the provided bootloader application for the REB1 +//! board. It provides a convenient wrapper around the HAL SPI to interface +//! with the EEPROM memory of the REB1 board. +//! +//! # Example +//! +//! - [REB1 EEPROM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/nvm.rs) +use arbitrary_int::{u2, u3}; +use core::convert::Infallible; +use embedded_hal::spi::SpiBus; + +pub const PAGE_SIZE: usize = 256; + +#[bitbybit::bitfield(u8)] +#[derive(Debug)] +pub struct StatusReg { + #[bit(7, r)] + status_register_write_protect: bool, + #[bits(4..=6, r)] + zero_segment: u3, + #[bits(2..=3, rw)] + block_protection_bits: u2, + #[bit(1, r)] + write_enable_latch: bool, + #[bit(0, r)] + write_in_progress: bool, +} + +// Registers. +pub mod regs { + /// Write status register command. + pub const WRSR: u8 = 0x01; + // Write command. + pub const WRITE: u8 = 0x02; + // Read command. + pub const READ: u8 = 0x03; + /// Write disable command. + pub const WRDI: u8 = 0x04; + /// Read status register command. + pub const RDSR: u8 = 0x05; + /// Write enable command. + pub const WREN: u8 = 0x06; +} + +use regs::*; +use va108xx_hal::{ + pac, + spi::{Spi, SpiClockConfig, SpiConfig, SpiLowLevel, BMSTART_BMSTOP_MASK}, +}; + +pub type RomSpi = Spi; + +/// Driver for the ST device M95M01 EEPROM memory. +/// +/// Specialized for the requirements of the VA108XX MCUs. +pub struct M95M01 { + pub spi: RomSpi, +} + +#[derive(Debug, PartialEq, Eq)] +pub struct PageBoundaryExceededError; + +impl M95M01 { + pub fn new(spi: pac::Spic, clk_config: SpiClockConfig) -> Self { + let spi = RomSpi::new_for_rom(spi, SpiConfig::default().clk_cfg(clk_config)).unwrap(); + let mut spi_dev = Self { spi }; + spi_dev.clear_block_protection().unwrap(); + spi_dev + } + + pub fn release(mut self) -> pac::Spic { + self.set_block_protection().unwrap(); + unsafe { pac::Spic::steal() } + } + + // Wait until the write-in-progress state is cleared. This exposes a [nb] API, so this function + // will return [nb::Error::WouldBlock] if the EEPROM is still busy. + pub fn writes_are_done(&mut self) -> nb::Result<(), Infallible> { + let rdsr = self.read_status_reg()?; + if rdsr.write_in_progress() { + return Err(nb::Error::WouldBlock); + } + Ok(()) + } + + pub fn read_status_reg(&mut self) -> Result { + let mut write_read: [u8; 2] = [regs::RDSR, 0x00]; + self.spi.transfer_in_place(&mut write_read)?; + Ok(StatusReg::new_with_raw_value(write_read[1])) + } + + pub fn write_enable(&mut self) -> Result<(), Infallible> { + self.spi.write(&[regs::WREN]) + } + + pub fn clear_block_protection(&mut self) -> Result<(), Infallible> { + // Has to be written separately. + self.write_enable()?; + self.spi.write(&[WRSR, 0x00]) + } + + pub fn set_block_protection(&mut self) -> Result<(), Infallible> { + let mut reg = StatusReg::new_with_raw_value(0); + reg.set_block_protection_bits(u2::new(0b11)); + self.write_enable()?; + self.spi.write(&[WRSR, reg.raw_value()]) + } + + fn common_init_write_and_read(&mut self, address: usize, reg: u8) -> Result<(), Infallible> { + nb::block!(self.writes_are_done())?; + self.spi.flush()?; + if reg == WRITE { + self.write_enable()?; + self.spi.write_fifo_unchecked(WRITE as u32); + } else { + self.spi.write_fifo_unchecked(READ as u32); + } + self.spi.write_fifo_unchecked((address as u32 >> 16) & 0xff); + self.spi + .write_fifo_unchecked((address as u32 & 0x00ff00) >> 8); + self.spi.write_fifo_unchecked(address as u32 & 0xff); + Ok(()) + } + + fn common_read(&mut self, address: usize) -> Result<(), Infallible> { + self.common_init_write_and_read(address, READ)?; + for _ in 0..4 { + // Pump the FIFO. + self.spi.write_fifo_unchecked(0); + // Ignore the first 4 bytes. + nb::block!(self.spi.read_fifo())?; + } + Ok(()) + } + + pub fn write(&mut self, mut address: usize, mut data: &[u8]) -> Result<(), Infallible> { + // Loop until all data is written + while !data.is_empty() { + // Calculate the page and the offset within the page from the address + let page = address / PAGE_SIZE; + let offset = address % PAGE_SIZE; + + // Calculate how much space is left in the current page + let space_left = PAGE_SIZE - offset; + + // Determine how much data to write in the current page + let to_write = data.len().min(space_left); + + // Write the current portion of the data + self.write_page(page, offset, &data[..to_write]).unwrap(); + + // Update the address and data for the next iteration + address += to_write; + data = &data[to_write..]; + } + + Ok(()) + } + + pub fn write_page( + &mut self, + page: usize, + offset: usize, + data: &[u8], + ) -> Result<(), PageBoundaryExceededError> { + // Check that the total data to be written does not exceed the page boundary + if offset + data.len() > PAGE_SIZE { + return Err(PageBoundaryExceededError); + } + + self.common_init_write_and_read(page * PAGE_SIZE + offset, WRITE) + .unwrap(); + for val in data.iter().take(data.len() - 1) { + nb::block!(self.spi.write_fifo(*val as u32)).unwrap(); + nb::block!(self.spi.read_fifo()).unwrap(); + } + nb::block!(self + .spi + .write_fifo(*data.last().unwrap() as u32 | BMSTART_BMSTOP_MASK)) + .unwrap(); + self.spi.flush().unwrap(); + nb::block!(self.writes_are_done()).unwrap(); + Ok(()) + } + + pub fn read(&mut self, address: usize, buf: &mut [u8]) -> Result<(), Infallible> { + self.common_read(address)?; + for val in buf.iter_mut() { + self.spi.write_fifo_unchecked(0); + *val = (nb::block!(self.spi.read_fifo()).unwrap() & 0xff) as u8; + } + nb::block!(self.spi.write_fifo(BMSTART_BMSTOP_MASK))?; + self.spi.flush()?; + Ok(()) + } + + pub fn verify(&mut self, address: usize, data: &[u8]) -> Result { + self.common_read(address)?; + for val in data.iter() { + self.spi.write_fifo_unchecked(0); + let read_val = (nb::block!(self.spi.read_fifo()).unwrap() & 0xff) as u8; + if read_val != *val { + return Ok(false); + } + } + nb::block!(self.spi.write_fifo(BMSTART_BMSTOP_MASK))?; + self.spi.flush()?; + Ok(true) + } +} diff --git a/va108xx/vorago-reb1/src/max11619.rs b/va108xx/vorago-reb1/src/max11619.rs new file mode 100644 index 0000000..eb15b82 --- /dev/null +++ b/va108xx/vorago-reb1/src/max11619.rs @@ -0,0 +1,54 @@ +//! This module provides a thin REB1 specific layer on top of the `max116xx_10bit` driver crate +//! +//! ## Examples +//! +//! - [ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11619-adc.rs) +use core::convert::Infallible; +use embedded_hal::spi::SpiDevice; +use max116xx_10bit::{ + Error, ExternallyClocked, InternallyClockedInternallyTimedSerialInterface, Max116xx10Bit, + Max116xx10BitEocExt, VoltageRefMode, WithWakeupDelay, WithoutWakeupDelay, +}; +use va108xx_hal::gpio::Input; + +pub type Max11619ExternallyClockedNoWakeup = + Max116xx10Bit; +pub type Max11619ExternallyClockedWithWakeup = + Max116xx10Bit; +pub type Max11619InternallyClocked = + Max116xx10BitEocExt; + +pub const AN0_CHANNEL: u8 = 0; +pub const AN1_CHANNEL: u8 = 1; +pub const AN2_CHANNEL: u8 = 2; +pub const POTENTIOMETER_CHANNEL: u8 = 3; + +pub fn max11619_externally_clocked_no_wakeup( + spi: Spi, +) -> Result, Error> { + let mut adc = Max116xx10Bit::max11619(spi)?; + adc.reset(false)?; + adc.setup()?; + Ok(adc) +} + +pub fn max11619_externally_clocked_with_wakeup( + spi: Spi, +) -> Result, Error> { + let mut adc = Max116xx10Bit::max11619(spi)?.into_ext_clkd_with_int_ref_wakeup_delay(); + adc.reset(false)?; + adc.setup()?; + Ok(adc) +} + +pub fn max11619_internally_clocked( + spi: Spi, + eoc: Input, + v_ref: VoltageRefMode, +) -> Result, Error> { + let mut adc = Max116xx10Bit::max11619(spi)? + .into_int_clkd_int_timed_through_ser_if_without_wakeup(v_ref, eoc)?; + adc.reset(false)?; + adc.setup()?; + Ok(adc) +} diff --git a/va108xx/vorago-reb1/src/temp_sensor.rs b/va108xx/vorago-reb1/src/temp_sensor.rs new file mode 100644 index 0000000..163bc28 --- /dev/null +++ b/va108xx/vorago-reb1/src/temp_sensor.rs @@ -0,0 +1,94 @@ +//! # API for the On-Board Analog Devices ADT75 temperature sensor +//! +//! [Datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADT75.pdf) +//! +//! ## Examples +//! +//! - [Temperature Sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs) +use embedded_hal::i2c::{I2c, SevenBitAddress}; +use va108xx_hal::{ + i2c::{Error, I2cMaster, I2cSpeed, InitError, MasterConfig}, + pac, + time::Hertz, +}; + +const ADT75_I2C_ADDR: u8 = 0b1001000; + +pub struct Adt75TempSensor { + sensor_if: I2cMaster, + cmd_buf: [u8; 1], + current_reg: RegAddresses, +} + +#[derive(PartialEq, Eq, Debug, Copy, Clone)] +pub enum RegAddresses { + Temperature = 0x00, + Configuration = 0x01, + THystSetpoint = 0x02, + TOsSetPoint = 0x03, + OneShot = 0x04, +} + +#[derive(Debug)] +pub enum AdtInitError { + Init(InitError), + I2c(Error), +} + +impl From for AdtInitError { + fn from(value: InitError) -> Self { + Self::Init(value) + } +} + +impl From for AdtInitError { + fn from(value: Error) -> Self { + Self::I2c(value) + } +} + +impl Adt75TempSensor { + pub fn new(sys_clk: Hertz, i2ca: pac::I2ca) -> Result { + let mut sensor = Adt75TempSensor { + // The master construction can not fail for regular I2C speed. + sensor_if: I2cMaster::new( + i2ca, + sys_clk, + MasterConfig::default(), + I2cSpeed::Regular100khz, + ) + .unwrap(), + cmd_buf: [RegAddresses::Temperature as u8], + current_reg: RegAddresses::Temperature, + }; + sensor.select_reg(RegAddresses::Temperature)?; + Ok(sensor) + } + + pub fn select_reg(&mut self, reg: RegAddresses) -> Result<(), Error> { + if reg != self.current_reg { + self.cmd_buf[0] = reg as u8; + self.current_reg = reg; + self.sensor_if.write(ADT75_I2C_ADDR, &self.cmd_buf[0..1])?; + } + Ok(()) + } + + pub fn read_temperature(&mut self) -> Result { + if self.current_reg != RegAddresses::Temperature { + self.select_reg(RegAddresses::Temperature)?; + } + let mut reply: [u8; 2] = [0; 2]; + self.sensor_if.read(ADT75_I2C_ADDR, &mut reply)?; + let adc_code = (((reply[0] as u16) << 8) | reply[1] as u16) >> 4; + let temp_celcius: f32 = if ((adc_code >> 11) & 0x01) == 0 { + // Sign bit not set, positiv value + // Divide ADC code by 16 according to datasheet + adc_code as f32 / 16.0 + } else { + // Calculation for negative values, assuming all 12 bits are used + (adc_code - 4096) as f32 / 16.0 + }; + Ok(temp_celcius) + } +} diff --git a/va108xx/vscode/launch.json b/va108xx/vscode/launch.json new file mode 100644 index 0000000..a57fb55 --- /dev/null +++ b/va108xx/vscode/launch.json @@ -0,0 +1,626 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + // You can set the "gdbPath" setting in a custom settings.json to use a non-default + // GDB application + "version": "0.2.0", + "configurations": [ + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug LED Blinky", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "preLaunchTask": "rust: cargo build led blinky", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/blinky-leds", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug Tests HAL", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "preLaunchTask": "rust: cargo build hal tests", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/board-tests", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug Blinky Button IRQ", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "preLaunchTask": "rust: cargo build button blinky", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/blinky-button-irq", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug Timer MS Ticks", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "preLaunchTask": "rust: cargo build systick", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/timer-ticks", + "interface": "jtag", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "UART Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "rust: cargo build uart", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/uart", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug SPI", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "rust: cargo build spi", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/spi", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug I2C / Temperature Sensor", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx-base.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "rust: cargo build temp sensor", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/adt75-temp-sensor", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Button Blinky RTIC Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx-base.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "rust: cargo build button blinky rtic", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/blinky-button-rtic", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "UART Echo with RTIC", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx-base.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "uart-echo-rtic-example", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/uart-echo-rtic", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "PWM Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "rust: cargo build pwm", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/pwm", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Cascade Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "rust: cargo build cascade", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/cascade", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "0x10000000", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Accelerometer Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "rust: cargo build accelerometer", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/adxl343-accelerometer", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "ADC Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "rust: cargo build adc", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/max11619-adc", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "UART IRQ Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "uart-echo-rtic-example", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/uart-echo-rtic", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "REB1 NVM Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "reb1-nvm", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/nvm", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "RTIC Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "rtic-example", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/rtic-example", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Embassy Example", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "embassy-example", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/embassy-example", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Bootloader", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "bootloader", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/release/bootloader", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Flashloader", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "flashloader", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/release/flashloader", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Async GPIO", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "async-gpio", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/async-gpio", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Async UART TX", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "async-uart-tx", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/async-uart-tx", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Async UART RX", + "servertype": "jlink", + "cwd": "${workspaceRoot}", + "device": "Cortex-M0", + "svdFile": "./va108xx/svd/va108xx.svd.patched", + "serverArgs": [ + "-jtagconf", + "-1,-1" + ], + "preLaunchTask": "async-uart-rx", + "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/async-uart-rx", + "interface": "jtag", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + ] +} \ No newline at end of file diff --git a/va108xx/vscode/settings.json b/va108xx/vscode/settings.json new file mode 100644 index 0000000..e2ecf80 --- /dev/null +++ b/va108xx/vscode/settings.json @@ -0,0 +1,3 @@ +{ + "cortex-debug.gdbPath.linux": "gdb-multiarch" +} \ No newline at end of file diff --git a/va108xx/vscode/tasks.json b/va108xx/vscode/tasks.json new file mode 100644 index 0000000..5b26aec --- /dev/null +++ b/va108xx/vscode/tasks.json @@ -0,0 +1,308 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "rust: cargo build", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build hal tests", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "board-tests", + "--features", + "rt" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build systick", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "timer-ticks", + "--features", + "rt" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build uart", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "uart" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build spi", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "spi" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build pwm", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "pwm", + "--features", + "rt" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build cascade", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "cascade", + "--features", + "rt" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "uart-echo-rtic-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "uart-echo-rtic" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "blinky-hal", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "blinky" + ], + "group": { + "kind": "build" + } + }, + { + "label": "rust: cargo build led blinky", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "blinky-leds" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build button blinky", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "blinky-button-irq" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build temp sensor", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "adt75-temp-sensor" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build button blinky rtic", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "blinky-button-rtic" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build accelerometer", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "adxl343-accelerometer" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rust: cargo build adc", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "max11619-adc" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "reb1-nvm", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "nvm" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "rtic-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "rtic-example" + ] + }, + { + "label": "embassy-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "embassy-example" + ] + }, + { + "label": "async-gpio", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "async-gpio" + ] + }, + { + "label": "async-uart-tx", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "async-uart-tx" + ] + }, + { + "label": "async-uart-rx", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "async-uart-rx" + ] + }, + { + "label": "bootloader", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "bootloader", + "--release", + ] + }, + { + "label": "flashloader", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "flashloader", + "--release" + ] + } + ] +} \ No newline at end of file diff --git a/va416xx/.cargo/config.toml.template b/va416xx/.cargo/config.toml.template new file mode 100644 index 0000000..11cf15a --- /dev/null +++ b/va416xx/.cargo/config.toml.template @@ -0,0 +1,37 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# runner = "gdb-multiarch -q -x jlink/jlink.gdb" +# runner = "arm-none-eabi-gdb -q -x jlink/jlink-reva.gdb" +# runner = "gdb-multiarch -q -x jlink/jlink-reva.gdb" +runner = "probe-rs run --chip VA416xx_RAM --protocol swd" + +rustflags = [ + "-C", + "link-arg=-Tlink.x", + "-C", + "linker=flip-link", + "-C", + "link-arg=-Tdefmt.x", + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", + "link-arg=--nmagic", + # Can be useful for debugging. + # "-Clink-args=-Map=app.map" +] + +[build] +# (`thumbv6m-*` is compatible with all ARM Cortex-M chips but using the right +# target improves performance) +# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) + +[alias] +rb = "run --bin" +rrb = "run --release --bin" +ut = "test --target=x86_64-unknown-linux-gnu" +genbin = "objcopy --release -- -O binary app.bin" + +[env] +DEFMT_LOG = "debug" diff --git a/va416xx/.gitignore b/va416xx/.gitignore new file mode 100644 index 0000000..89cc778 --- /dev/null +++ b/va416xx/.gitignore @@ -0,0 +1,16 @@ +/.vscode + +# Ignore user config +/.cargo/config.toml + +# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries +# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html +Cargo.lock + +# These are backup files generated by rustfmt +**/*.rs.bk + +/app.map +/app.bin + +/Embed.toml diff --git a/va416xx/.gitmodules b/va416xx/.gitmodules new file mode 100644 index 0000000..e69de29 diff --git a/va416xx/Cargo.toml b/va416xx/Cargo.toml new file mode 100644 index 0000000..645a69b --- /dev/null +++ b/va416xx/Cargo.toml @@ -0,0 +1,45 @@ +[workspace] +resolver = "2" +members = [ + "va416xx", + "va416xx-hal", + "va416xx-embassy", + "vorago-peb1", + "bootloader", + "flashloader", + "examples/simple", + "examples/embassy", + "examples/rtic", +] +exclude = [ + "flashloader/slot-a-blinky", + "flashloader/slot-b-blinky", +] + +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +# This is problematic for stepping.. +# opt-level = 'z' # <- +overflow-checks = true # <- + +# cargo build/run --release +[profile.release] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = 3 # <- +overflow-checks = false # <- + +[profile.small] +inherits = "release" +codegen-units = 1 +debug-assertions = false # <- +lto = true +opt-level = 'z' # <- +overflow-checks = false # <- +strip = true # Automatically strip symbols from the binary. diff --git a/va416xx/Embed.toml.template b/va416xx/Embed.toml.template new file mode 100644 index 0000000..9be34d7 --- /dev/null +++ b/va416xx/Embed.toml.template @@ -0,0 +1,5 @@ +[default.general] +chip = "VA416xx_RAM" + +[default.rtt] +enabled = true diff --git a/va416xx/LICENSE-APACHE b/va416xx/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va416xx/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + +4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va416xx/NOTICE b/va416xx/NOTICE new file mode 100644 index 0000000..f2f635d --- /dev/null +++ b/va416xx/NOTICE @@ -0,0 +1,3 @@ +Workspace to develop Rust for the VA416xx devices + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va416xx/README.md b/va416xx/README.md new file mode 100644 index 0000000..5391641 --- /dev/null +++ b/va416xx/README.md @@ -0,0 +1,202 @@ +[![build](https://github.com/us-irs/va416xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va416xx-rs/actions/workflows/ci.yml) + +Vorago VA416xx Rust Support +========= + +This crate collection provides support to write Rust applications for the VA416XX family +of devices. + +## List of crates + +This workspace contains the following crates: + +- The [`va416xx`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx) + PAC crate containing basic low-level register definition +- The [`va416xx-hal`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-hal) + HAL crate containing higher-level abstractions on top of the PAC register crate. +- The [`va416xx-embassy`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-embassy) + crate containing support for running the embassy-rs RTOS. +- The [`vorago-peb1`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/vorago-peb1) + BSP crate containing support for the PEB1 development board. + +It also contains the following helper crates: + +- The [`bootloader`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/bootloader) + crate contains a sample bootloader strongly based on the one provided by Vorago. +- The [`flashloader`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/flashloader) + crate contains a sample flashloader which is able to update the redundant images in the NVM which + is compatible to the provided bootloader as well. +- The [`examples`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples) + folder contains various example applications crates using the HAL and the PAC. + This folder also contains dedicated example applications using the + [`RTIC`](https://rtic.rs/2/book/en/) and [`embassy`](https://github.com/embassy-rs/embassy) + native Rust RTOSes. + +Some parts of the HAL implementation and the Embassy-rs support are contained in the external +[`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) crate. + +## Using the `.cargo/config.toml` file + +Use the following command to have a starting `config.toml` file + +```sh +cp .cargo/config.toml.template .cargo/config.toml +``` + +You then can adapt the `config.toml` to your needs. For example, you can configure runners +to conveniently flash with `cargo run`. + +## Using the sample VS Code files + +Use the following command to have a starting configuration for VS Code: + +```sh +cp -rT vscode .vscode +``` + +You can then adapt the files in `.vscode` to your needs. + +## Building projects + +Building an application requires the `thumbv7em-none-eabihf` cross-compiler toolchain. +If you have not installed it yet, you can do so with + +```sh +rustup target add thumbv7em-none-eabihf +``` + +After that, you can use `cargo build` to build the development version of the crate. +For example, you can use + +```sh +cargo build --example blinky +``` + +to build a simple blinky app. + +## Flashing, running and debugging the software + +You can use CLI or VS Code for flashing, running and debugging. + +### Using CLI with probe-rs + +Install [probe-rs](https://probe.rs/docs/getting-started/installation/) first. + +You can use `probe-rs` to run the software and display RTT log output. However, debugging does not +work yet. + +After installation, you can run the following command + +```sh +probe-rs run --chip VA416xx_RAM --protocol jtag target/thumbv7em-none-eabihf/debug/examples/blinky +``` + +to flash and run the blinky program on the RAM. There is also a `VA416xx` chip target +available for persistent flashing. + +Runner configuration is available in the `.cargo/def-config.toml` file to use `probe-rs` for +convenience. `probe-rs` is also able to process and display `defmt` strings directly. + +### Using VS Code + +Following tools are required: + +1. [SEGGER J-Link tools](https://www.segger.com/downloads/jlink/) installed +2. [gdb-multiarch](https://packages.debian.org/sid/gdb-multiarch) or similar + cross-architecture debugger installed. All commands here assume `gdb-multiarch`. + +Assuming a working debug connection to your VA416xx board, you can debug using VS Code with +the [`Cortex-Debug` plugin](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug). +Please make sure that [`objdump-multiarch` and `nm-multiarch`](https://forums.raspberrypi.com/viewtopic.php?t=333146) +are installed as well. + +Some sample configuration files for VS code were provided and can be used by running +`cp -rT vscode .vscode` like specified above. After that, you can use `Run and Debug` +to automatically rebuild and flash your application. + +If you would like to use a custom GDB application, you can specify the gdb binary in the following +configuration variables in your `settings.json`: + +- `"cortex-debug.gdbPath"` +- `"cortex-debug.gdbPath.linux"` +- `"cortex-debug.gdbPath.windows"` +- `"cortex-debug.gdbPath.osx"` + +The provided VS Code configurations also provide an integrated RTT logger, which you can access +via the terminal at `RTT Ch:0 console`. In order for the RTT block address detection to +work properly, `objdump-multiarch` and `nm-multiarch` need to be installed. + +### Using CLI with GDB and Segger J-Link Tools + +Following tools are required: + +1. [SEGGER J-Link tools](https://www.segger.com/downloads/jlink/) installed +2. [gdb-multiarch](https://packages.debian.org/sid/gdb-multiarch) or similar + cross-architecture debugger installed. All commands here assume `gdb-multiarch`. + +You can build the blinky example application with the following command + +```sh +cargo build --example blinky +``` + +Start the GDB server first. Depending on whether the application is flashed to RAM or the NVM +flash memory, the server needs to be started with a different configuration +For example, on Debian based system the following command can be used to do this (this command +is also run when running the `jlink-gdb.sh` script) + +**RAM Flash** + +```sh +JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript +``` + +**NVM Flash** + +```sh +JLinkGDBServer -select USB -device VA416xx -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd +``` + +After this, you can flash and debug the application with the following command + +```sh +gdb-mutliarch -q -x jlink/jlink.gdb target/thumbv7em-none-eabihf/debug/examples/blinky +``` + +Please note that you can automate all steps except starting the GDB server by using a cargo +runner configuration, for example with the following lines in your `.cargo/config.toml` file: + +```toml +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +runner = "gdb-multiarch -q -x jlink/jlink.gdb -tui" +``` + +After that, you can simply use `cargo run --example blinky` to flash the blinky +example. + +### Using the RTT Viewer + +The Segger RTT viewer can be used to display log messages received from the target. The base +address for the RTT block placement is 0x1fff8000. It is recommended to use a search range of +0x1000 around that base address when using the RTT viewer. + +The RTT viewer will not be able to process `defmt` printouts. However, you can view the defmt +logs by [installing defmt-print](https://crates.io/crates/defmt-print) first and then running + +```sh +defmt-print -e tcp +``` + +The path of the ELF file which is being debugged needs to be specified for this to work. + +## Learning (Embedded) Rust + +If you are unfamiliar with Rust on Embedded Systems or Rust in general, the following resources +are recommended: + +- [Rust Book](https://doc.rust-lang.org/book/) +- [Embedded Rust Book](https://docs.rust-embedded.org/book/) +- [Embedded Rust Discovery](https://docs.rust-embedded.org/discovery/microbit/) +- [Awesome Embedded Rust](https://github.com/rust-embedded/awesome-embedded-rust) diff --git a/va416xx/automation/Dockerfile b/va416xx/automation/Dockerfile new file mode 100644 index 0000000..48c8e1d --- /dev/null +++ b/va416xx/automation/Dockerfile @@ -0,0 +1,13 @@ +# Run the following commands from root directory to build and run locally +# docker build -f automation/Dockerfile -t . +# docker run -it +FROM rust:latest +RUN apt-get update +RUN apt-get --yes upgrade +# tzdata is a dependency, won't install otherwise +ARG DEBIAN_FRONTEND=noninteractive + +RUN rustup install nightly && \ + rustup target add thumbv7em-none-eabihf && \ + rustup +nightly target add thumbv7em-none-eabihf && \ + rustup component add rustfmt clippy diff --git a/va416xx/automation/Jenkinsfile b/va416xx/automation/Jenkinsfile new file mode 100644 index 0000000..7fe8c1e --- /dev/null +++ b/va416xx/automation/Jenkinsfile @@ -0,0 +1,47 @@ +pipeline { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + + stages { + stage('Rust Toolchain Info') { + steps { + sh 'rustc --version' + } + } + stage('Clippy') { + steps { + sh 'cargo clippy --target thumbv7em-none-eabihf' + } + } + stage('Rustfmt') { + steps { + sh 'cargo fmt' + } + } + stage('Docs') { + steps { + sh """ + RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p vorago-peb1 + RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va416xx-hal --features va41630 + RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va416xx + """ + } + } + stage('Check') { + steps { + sh 'cargo check --target thumbv7em-none-eabihf' + } + } + stage('Check Examples') { + steps { + sh """ + cargo check --target thumbv7em-none-eabihf --examples + """ + } + } + } +} diff --git a/va416xx/bootloader/Cargo.toml b/va416xx/bootloader/Cargo.toml new file mode 100644 index 0000000..f3b5bdf --- /dev/null +++ b/va416xx/bootloader/Cargo.toml @@ -0,0 +1,18 @@ +[package] +name = "bootloader" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +cortex-m-rt = "0.7" +defmt-rtt = "1" +defmt = "1" +panic-probe = { version = "1", features = ["defmt"] } +crc = "3" +static_assertions = "1" + +[dependencies.va416xx-hal] +version = "0.6" +features = ["va41630", "defmt"] +path = "../va416xx-hal" diff --git a/va416xx/bootloader/README.md b/va416xx/bootloader/README.md new file mode 100644 index 0000000..ee9b538 --- /dev/null +++ b/va416xx/bootloader/README.md @@ -0,0 +1,47 @@ +VA416xx Bootloader Application +======= + +This is the Rust version of the bootloader supplied by Vorago. + +## Memory Map + +The bootloader uses the following memory map: + +| Address | Notes | Size | +| ------ | ---- | ---- | +| 0x0 | Bootloader start | code up to 0x3FFC bytes | +| 0x3FFC | Bootloader CRC | word | +| 0x4000 | App image A start | code up to 0x1DFF8 (~120K) bytes | +| 0x21FF8 | App image A CRC check length | word | +| 0x21FFC | App image A CRC check value | word | +| 0x22000 | App image B start | code up to 0x1DFF8 (~120K) bytes | +| 0x3FFF8 | App image B CRC check length | word | +| 0x3FFFC | App image B CRC check value | word | +| 0x40000 | End of NVM | end | + +## Additional Information + +As opposed to the Vorago example code, this bootloader assumes a 40 MHz external clock +but does not scale that clock up. It also uses a word (4 bytes) instead of a half-word for the CRC +and uses the ISO 3309 CRC32 standard checksum. + +This bootloader does not provide tools to flash the NVM memories by itself. Instead, you can use +the [flashloader](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/flashloader) +application to perform this task using a CCSDS interface via a UART. + +The bootloader performs the following steps: + +1. The application will calculate the checksum of itself if the bootloader CRC is blank (all zeroes + or all ones). If the CRC is not blank and the checksum check fails, it will immediately boot + application image A. Otherwise, it proceeds to the next step. +2. Check the checksum of App A. If that checksum is valid, it will boot App A. If not, it will + proceed to the next step. +3. Check the checksum of App B. If that checksum is valid, it will boot App B. If not, it will + boot App A as the fallback image. + +You could adapt and combine this bootloader with a non-volatile memory to select a prefered app +image, which would be a first step towards an updatable flight software. + +Please note that you *MUST* compile the application at slot A and slot B with an appropriate +`memory.x` file where the base address of the `FLASH` was adapted according to the base address +shown in the memory map above. The memory files to do this were provided in the `scripts` folder. diff --git a/va416xx/bootloader/src/main.rs b/va416xx/bootloader/src/main.rs new file mode 100644 index 0000000..f60de93 --- /dev/null +++ b/va416xx/bootloader/src/main.rs @@ -0,0 +1,347 @@ +//! Vorago bootloader which can boot from two images. +//! +//! As opposed to the Vorago example code, this bootloader assumes a 40 MHz external clock +//! but does not scale that clock up. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use crc::{Crc, CRC_32_ISO_HDLC}; +use defmt_rtt as _; +use panic_probe as _; +use va416xx_hal::{ + clock::{pll_setup_delay, ClockConfigurator, ClockDivisorSelect, ClockSelect}, + edac, + nvm::Nvm, + pac::{self, interrupt}, + time::Hertz, + wdt::Wdt, +}; + +const EXTCLK_FREQ: u32 = 40_000_000; +const WITH_WDT: bool = false; +const WDT_FREQ_MS: u32 = 50; +const DEBUG_PRINTOUTS: bool = true; + +// Dangerous option! An image with this option set to true will flash itself from RAM directly +// into the NVM. This can be used as a recovery option from a direct RAM flash to fix the NVM +// boot process. Please note that this will flash an image which will also always perform the +// self-flash itself. It is recommended that you use a tool like probe-rs, Keil IDE, or a flash +// loader to boot a bootloader without this feature. +const FLASH_SELF: bool = false; +// Useful for debugging and see what the bootloader is doing. Enabled currently, because +// the binary stays small enough. +const DEFMT_PRINTOUTS: bool = true; + +// Important bootloader addresses and offsets, vector table information. + +const NVM_SIZE: u32 = 0x40000; + +const BOOTLOADER_START_ADDR: u32 = 0x0; +const BOOTLOADER_CRC_ADDR: u32 = BOOTLOADER_END_ADDR - 4; +const BOOTLOADER_END_ADDR: u32 = 0x4000; + +// 0x4000 +const APP_A_START_ADDR: u32 = BOOTLOADER_END_ADDR; +// The actual size of the image which is relevant for CRC calculation will be store at this +// address. +// 0x21FF8 +const APP_A_SIZE_ADDR: u32 = APP_B_END_ADDR - 8; +// 0x21FFC +const APP_A_CRC_ADDR: u32 = APP_B_END_ADDR - 4; +pub const APP_A_END_ADDR: u32 = BOOTLOADER_END_ADDR + APP_IMG_SZ; + +// 0x22000 +const APP_B_START_ADDR: u32 = APP_A_END_ADDR; +// The actual size of the image which is relevant for CRC calculation will be stored at this +// address. +// 0x3FFF8 +const APP_B_SIZE_ADDR: u32 = APP_B_END_ADDR - 8; +// 0x3FFFC +const APP_B_CRC_ADDR: u32 = APP_B_END_ADDR - 4; +// 0x40000 +pub const APP_B_END_ADDR: u32 = NVM_SIZE; + +pub const APP_IMG_SZ: u32 = APP_B_END_ADDR - APP_A_START_ADDR / 2; + +static_assertions::const_assert!((APP_B_END_ADDR - BOOTLOADER_END_ADDR) % 2 == 0); + +pub const VECTOR_TABLE_OFFSET: u32 = 0x0; +pub const VECTOR_TABLE_LEN: u32 = 0x350; +pub const RESET_VECTOR_OFFSET: u32 = 0x4; + +const CRC_ALGO: Crc = Crc::::new(&CRC_32_ISO_HDLC); + +#[derive(Debug, Copy, Clone, PartialEq, Eq, defmt::Format)] +enum AppSel { + A, + B, +} + +pub trait WdtInterface { + fn feed(&self); +} + +pub struct OptWdt(Option); + +impl WdtInterface for OptWdt { + fn feed(&self) { + if self.0.is_some() { + self.0.as_ref().unwrap().feed(); + } + } +} + +#[entry] +fn main() -> ! { + if DEFMT_PRINTOUTS { + defmt::println!("-- VA416xx bootloader --"); + } + let mut dp = pac::Peripherals::take().unwrap(); + let cp = cortex_m::Peripherals::take().unwrap(); + // Disable ROM protection. + dp.sysconfig.rom_prot().write(|w| unsafe { w.bits(1) }); + setup_edac(&mut dp.sysconfig); + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ)) + .freeze() + .unwrap(); + let mut opt_wdt = OptWdt(None); + if WITH_WDT { + opt_wdt.0 = Some(Wdt::start(dp.watch_dog, &clocks, WDT_FREQ_MS)); + } + + let nvm = Nvm::new(dp.spi3, &clocks); + + if FLASH_SELF { + let mut first_four_bytes: [u8; 4] = [0; 4]; + read_four_bytes_at_addr_zero(&mut first_four_bytes); + let bootloader_data = { + unsafe { + &*core::ptr::slice_from_raw_parts( + (BOOTLOADER_START_ADDR + 4) as *const u8, + (BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 8) as usize, + ) + } + }; + let mut digest = CRC_ALGO.digest(); + digest.update(&first_four_bytes); + digest.update(bootloader_data); + let bootloader_crc = digest.finalize(); + + nvm.write_data(0x0, &first_four_bytes); + nvm.write_data(0x4, bootloader_data); + if let Err(e) = nvm.verify_data(0x0, &first_four_bytes) { + if DEFMT_PRINTOUTS { + defmt::error!("verification of self-flash to NVM failed: {:?}", e); + } + } + if let Err(e) = nvm.verify_data(0x4, bootloader_data) { + if DEFMT_PRINTOUTS { + defmt::error!("verification of self-flash to NVM failed: {:?}", e); + } + } + + nvm.write_data(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes()); + if let Err(e) = nvm.verify_data(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes()) { + if DEFMT_PRINTOUTS { + defmt::error!( + "error: CRC verification for bootloader self-flash failed: {:?}", + e + ); + } + } + } + + // Check bootloader's CRC (and write it if blank) + check_own_crc(&opt_wdt, &nvm, &cp); + + if check_app_crc(AppSel::A, &opt_wdt) { + boot_app(AppSel::A, &cp) + } else if check_app_crc(AppSel::B, &opt_wdt) { + boot_app(AppSel::B, &cp) + } else { + if DEBUG_PRINTOUTS && DEFMT_PRINTOUTS { + defmt::println!("both images corrupt! booting image A"); + } + // TODO: Shift a CCSDS packet out to inform host/OBC about image corruption. + // Both images seem to be corrupt. Boot default image A. + boot_app(AppSel::A, &cp) + } +} + +fn check_own_crc(wdt: &OptWdt, nvm: &Nvm, cp: &cortex_m::Peripherals) { + let crc_exp = unsafe { (BOOTLOADER_CRC_ADDR as *const u32).read_unaligned().to_be() }; + wdt.feed(); + // I'd prefer to use [core::slice::from_raw_parts], but that is problematic + // because the address of the bootloader is 0x0, so the NULL check fails and the functions + // panics. + let mut first_four_bytes: [u8; 4] = [0; 4]; + read_four_bytes_at_addr_zero(&mut first_four_bytes); + let mut digest = CRC_ALGO.digest(); + digest.update(&first_four_bytes); + digest.update(unsafe { + &*core::ptr::slice_from_raw_parts( + (BOOTLOADER_START_ADDR + 4) as *const u8, + (BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 8) as usize, + ) + }); + let crc_calc = digest.finalize(); + wdt.feed(); + if crc_exp == 0x0000 || crc_exp == 0xffff { + if DEBUG_PRINTOUTS && DEFMT_PRINTOUTS { + defmt::info!("BL CRC blank - prog new CRC"); + } + // Blank CRC, write it to NVM. + nvm.write_data(BOOTLOADER_CRC_ADDR, &crc_calc.to_be_bytes()); + // The Vorago bootloader resets here. I am not sure why this is done but I think it is + // necessary because somehow the boot will not work if we just continue as usual. + // cortex_m::peripheral::SCB::sys_reset(); + } else if crc_exp != crc_calc { + // Bootloader is corrupted. Try to run App A. + if DEBUG_PRINTOUTS && DEFMT_PRINTOUTS { + defmt::info!( + "bootloader CRC corrupt, read {} and expected {}. booting image A immediately", + crc_calc, + crc_exp + ); + } + // TODO: Shift out minimal CCSDS frame to notify about bootloader corruption. + boot_app(AppSel::A, cp); + } +} + +fn read_four_bytes_at_addr_zero(buf: &mut [u8; 4]) { + unsafe { + core::arch::asm!( + "ldr r0, [{0}]", // Load 4 bytes from src into r0 register + "str r0, [{1}]", // Store r0 register into first_four_bytes + in(reg) BOOTLOADER_START_ADDR as *const u8, // Input: src pointer (0x0) + in(reg) buf as *mut [u8; 4], // Input: destination pointer + ); + } +} +fn check_app_crc(app_sel: AppSel, wdt: &OptWdt) -> bool { + if DEBUG_PRINTOUTS && DEFMT_PRINTOUTS { + defmt::info!("Checking image {:?}", app_sel); + } + if app_sel == AppSel::A { + check_app_given_addr(APP_A_CRC_ADDR, APP_A_START_ADDR, APP_A_SIZE_ADDR, wdt) + } else { + check_app_given_addr(APP_B_CRC_ADDR, APP_B_START_ADDR, APP_B_SIZE_ADDR, wdt) + } +} + +fn check_app_given_addr( + crc_addr: u32, + start_addr: u32, + image_size_addr: u32, + wdt: &OptWdt, +) -> bool { + let crc_exp = unsafe { (crc_addr as *const u32).read_unaligned().to_be() }; + let image_size = unsafe { (image_size_addr as *const u32).read_unaligned().to_be() }; + // Sanity check. + if image_size > APP_A_END_ADDR - APP_A_START_ADDR - 8 { + if DEFMT_PRINTOUTS { + defmt::info!("detected invalid app size {}", image_size); + } + return false; + } + wdt.feed(); + let crc_calc = CRC_ALGO.checksum(unsafe { + core::slice::from_raw_parts(start_addr as *const u8, image_size as usize) + }); + wdt.feed(); + if crc_calc == crc_exp { + return true; + } + false +} + +fn boot_app(app_sel: AppSel, cp: &cortex_m::Peripherals) -> ! { + if DEBUG_PRINTOUTS && DEFMT_PRINTOUTS { + defmt::info!("booting app {:?}", app_sel); + } + let clkgen = unsafe { pac::Clkgen::steal() }; + clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clksel_sys().bits(ClockSelect::Hbo as u8) }); + pll_setup_delay(); + clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clk_div_sel().bits(ClockDivisorSelect::Div1 as u8) }); + // Clear all interrupts set. + unsafe { + cp.NVIC.icer[0].write(0xFFFFFFFF); + cp.NVIC.icpr[0].write(0xFFFFFFFF); + } + cortex_m::asm::dsb(); + cortex_m::asm::isb(); + unsafe { + if app_sel == AppSel::A { + cp.SCB.vtor.write(APP_A_START_ADDR); + } else { + cp.SCB.vtor.write(APP_B_START_ADDR); + } + } + cortex_m::asm::dsb(); + cortex_m::asm::isb(); + vector_reset(); +} + +pub fn vector_reset() -> ! { + unsafe { + // Set R0 to VTOR address (0xE000ED08) + let vtor_address: u32 = 0xE000ED08; + + // Load VTOR + let vtor: u32 = *(vtor_address as *const u32); + + // Load initial MSP value + let initial_msp: u32 = *(vtor as *const u32); + + // Set SP value (assume MSP is selected) + core::arch::asm!("mov sp, {0}", in(reg) initial_msp); + + // Load reset vector + let reset_vector: u32 = *((vtor + 4) as *const u32); + + // Branch to reset handler + core::arch::asm!("bx {0}", in(reg) reset_vector); + } + unreachable!(); +} + +fn setup_edac(syscfg: &mut pac::Sysconfig) { + // The scrub values are based on the Vorago provided bootloader. + edac::enable_rom_scrub(syscfg, 125); + edac::enable_ram0_scrub(syscfg, 1000); + edac::enable_ram1_scrub(syscfg, 1000); + edac::enable_sbe_irq(); + edac::enable_mbe_irq(); +} + +#[interrupt] +#[allow(non_snake_case)] +fn WATCHDOG() { + let wdt = unsafe { pac::WatchDog::steal() }; + // Clear interrupt. + wdt.wdogintclr().write(|w| unsafe { w.bits(1) }); +} + +#[interrupt] +#[allow(non_snake_case)] +fn EDAC_SBE() { + // TODO: Send some command via UART for notification purposes. Also identify the problematic + // memory. + edac::clear_sbe_irq(); +} + +#[interrupt] +#[allow(non_snake_case)] +fn EDAC_MBE() { + // TODO: Send some command via UART for notification purposes. + edac::clear_mbe_irq(); + // TODO: Reset like the vorago example? +} diff --git a/va416xx/examples/README.md b/va416xx/examples/README.md new file mode 100644 index 0000000..83a27ad --- /dev/null +++ b/va416xx/examples/README.md @@ -0,0 +1,33 @@ +VA416xx Example Applications +======== + +This folder contains various examples +Consult the main README first for setup of the repository. + +## Simple examples + +```rs +cargo run --example blinky +``` + +You can have a look at the `simple/examples` folder to see all available simple examples + +## RTIC example + +```rs +cargo run --bin rtic-example +``` + +## Embassy example + +Blinky with time driver IRQs in library + +```rs +cargo run --bin embassy-example +``` + +Blinky with custom time driver IRQs + +```rs +cargo run --bin embassy-example --no-default-features --features custom-irqs +``` diff --git a/va416xx/examples/embassy/Cargo.toml b/va416xx/examples/embassy/Cargo.toml new file mode 100644 index 0000000..5bc67d6 --- /dev/null +++ b/va416xx/examples/embassy/Cargo.toml @@ -0,0 +1,41 @@ +[package] +name = "embassy-example" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +cortex-m-rt = "0.7" +cfg-if = "1" +embedded-io = "0.6" +embedded-hal-async = "1" +embedded-io-async = "0.6" + +heapless = "0.9" +defmt-rtt = "1" +defmt = "1" +panic-probe = { version = "1", features = ["print-defmt"] } +static_cell = "2" +critical-section = "1" +ringbuf = { version = "0.4", default-features = false } + +nb = "1" +embassy-sync = "0.7" +embassy-time = "0.5" +embassy-executor = { version = "0.9", features = [ + "arch-cortex-m", + "executor-thread", + "executor-interrupt" +]} + +va416xx-hal = { version = "0.6", path = "../../va416xx-hal", features = ["defmt"] } +va416xx-embassy = { version = "0.1", path = "../../va416xx-embassy", default-features = false } + +[features] +default = ["ticks-hz-1_000", "va416xx-embassy/irq-tim14-tim15"] +custom-irqs = [] +ticks-hz-1_000 = ["embassy-time/tick-hz-1_000"] +ticks-hz-32_768 = ["embassy-time/tick-hz-32_768"] + +[package.metadata.cargo-machete] +ignored = ["cortex-m-rt"] diff --git a/va416xx/examples/embassy/src/bin/async-gpio.rs b/va416xx/examples/embassy/src/bin/async-gpio.rs new file mode 100644 index 0000000..e62e536 --- /dev/null +++ b/va416xx/examples/embassy/src/bin/async-gpio.rs @@ -0,0 +1,353 @@ +//! This example demonstrates the usage of async GPIO operations on VA416xx. +//! +//! You need to tie the PA0 to the PA1 pin for this example to work. You can optionally also tie +//! more pin combinations together and test other ports by setting the appropriate +//! [CHECK_XXX_TO_XXX] constants to true. +#![no_std] +#![no_main] + +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use embassy_example::EXTCLK_FREQ; +use embassy_executor::Spawner; +use embassy_sync::channel::{Receiver, Sender}; +use embassy_sync::{blocking_mutex::raw::ThreadModeRawMutex, channel::Channel}; +use embassy_time::{Duration, Instant, Timer}; +use embedded_hal_async::digital::Wait; +use va416xx_hal::clock::ClockConfigurator; +use va416xx_hal::gpio::asynch::{on_interrupt_for_async_gpio_for_port, InputPinAsync}; +use va416xx_hal::gpio::{Input, Output, PinState, Port}; +use va416xx_hal::pac::{self, interrupt}; +use va416xx_hal::pins::{PinsA, PinsB, PinsC, PinsD, PinsE, PinsF, PinsG}; +use va416xx_hal::time::Hertz; + +const CHECK_PA0_TO_PA1: bool = true; +const CHECK_PB0_TO_PB1: bool = false; +const CHECK_PC14_TO_PC15: bool = false; +const CHECK_PD2_TO_PD3: bool = false; +const CHECK_PE0_TO_PE1: bool = false; +const CHECK_PF0_TO_PF1: bool = false; + +#[derive(Clone, Copy)] +pub struct GpioCmd { + cmd_type: GpioCmdType, + after_delay: u32, +} + +impl GpioCmd { + pub fn new(cmd_type: GpioCmdType, after_delay: u32) -> Self { + Self { + cmd_type, + after_delay, + } + } +} + +#[derive(Clone, Copy)] +pub enum GpioCmdType { + SetHigh, + SetLow, + RisingEdge, + FallingEdge, + CloseTask, +} + +// Declare a bounded channel of 3 u32s. +static CHANNEL_PA0_TO_PA1: Channel = Channel::new(); +static CHANNEL_PB0_TO_PB1: Channel = Channel::new(); +static CHANNEL_PC14_TO_PC15: Channel = Channel::new(); +static CHANNEL_PD2_TO_PD3: Channel = Channel::new(); +static CHANNEL_PE0_TO_PE1: Channel = Channel::new(); +static CHANNEL_PF0_TO_PF1: Channel = Channel::new(); + +#[embassy_executor::main] +async fn main(spawner: Spawner) { + defmt::println!("-- VA416xx Async GPIO Demo --"); + + let dp = pac::Peripherals::take().unwrap(); + + // Initialize the systick interrupt & obtain the token to prove that we did + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ)) + .freeze() + .unwrap(); + // Safety: Only called once here. + va416xx_embassy::init(dp.tim15, dp.tim14, &clocks); + + let porta = PinsA::new(dp.porta); + let portb = PinsB::new(dp.portb); + let portc = PinsC::new(dp.portc); + let portd = PinsD::new(dp.portd); + let porte = PinsE::new(dp.porte); + let portf = PinsF::new(dp.portf); + + let portg = PinsG::new(dp.portg); + let mut led = Output::new(portg.pg5, PinState::Low); + + if CHECK_PA0_TO_PA1 { + let out_pin = Output::new(porta.pa0, PinState::Low); + let in_pin = Input::new_floating(porta.pa1); + let in_pin = InputPinAsync::new(in_pin).unwrap(); + + spawner + .spawn(output_task( + "PA0 to PA1", + out_pin, + CHANNEL_PA0_TO_PA1.receiver(), + )) + .unwrap(); + check_pin_to_pin_async_ops("PA0 to PA1", CHANNEL_PA0_TO_PA1.sender(), in_pin).await; + defmt::info!("Example PA0 to PA1 done"); + } + + if CHECK_PB0_TO_PB1 { + let out_pin = Output::new(portb.pb0, PinState::Low); + let in_pin = Input::new_floating(portb.pb1); + let in_pin = InputPinAsync::new(in_pin).unwrap(); + + spawner + .spawn(output_task( + "PB0 to PB1", + out_pin, + CHANNEL_PB0_TO_PB1.receiver(), + )) + .unwrap(); + check_pin_to_pin_async_ops("PB0 to PB1", CHANNEL_PB0_TO_PB1.sender(), in_pin).await; + defmt::info!("Example PB0 to PB1 done"); + } + + if CHECK_PC14_TO_PC15 { + let out_pin = Output::new(portc.pc14, PinState::Low); + let in_pin = Input::new_floating(portc.pc15); + let in_pin = InputPinAsync::new(in_pin).unwrap(); + spawner + .spawn(output_task( + "PC14 to PC15", + out_pin, + CHANNEL_PC14_TO_PC15.receiver(), + )) + .unwrap(); + check_pin_to_pin_async_ops("PC14 to PC15", CHANNEL_PC14_TO_PC15.sender(), in_pin).await; + defmt::info!("Example PC14 to PC15 done"); + } + + if CHECK_PD2_TO_PD3 { + let out_pin = Output::new(portd.pd2, PinState::Low); + let in_pin = Input::new_floating(portd.pd3); + let in_pin = InputPinAsync::new(in_pin).unwrap(); + spawner + .spawn(output_task( + "PD2 to PD3", + out_pin, + CHANNEL_PD2_TO_PD3.receiver(), + )) + .unwrap(); + check_pin_to_pin_async_ops("PD2 to PD3", CHANNEL_PD2_TO_PD3.sender(), in_pin).await; + defmt::info!("Example PD2 to PD3 done"); + } + + if CHECK_PE0_TO_PE1 { + let out_pin = Output::new(porte.pe0, PinState::Low); + let in_pin = Input::new_floating(porte.pe1); + let in_pin = InputPinAsync::new(in_pin).unwrap(); + spawner + .spawn(output_task( + "PE0 to PE1", + out_pin, + CHANNEL_PE0_TO_PE1.receiver(), + )) + .unwrap(); + check_pin_to_pin_async_ops("PE0 to PE1", CHANNEL_PE0_TO_PE1.sender(), in_pin).await; + defmt::info!("Example PE0 to PE1 done"); + } + + if CHECK_PF0_TO_PF1 { + let out_pin = Output::new(portf.pf0, PinState::Low); + let in_pin = Input::new_floating(portf.pf1); + let in_pin = InputPinAsync::new(in_pin).unwrap(); + spawner + .spawn(output_task( + "PF0 to PF1", + out_pin, + CHANNEL_PF0_TO_PF1.receiver(), + )) + .unwrap(); + check_pin_to_pin_async_ops("PF0 to PF1", CHANNEL_PF0_TO_PF1.sender(), in_pin).await; + defmt::info!("Example PF0 to PF1 done"); + } + + defmt::info!("Example done, toggling LED0"); + loop { + led.toggle(); + Timer::after(Duration::from_millis(500)).await; + } +} + +async fn check_pin_to_pin_async_ops( + ctx: &'static str, + sender: Sender<'static, ThreadModeRawMutex, GpioCmd, 3>, + mut async_input: impl Wait, +) { + defmt::info!( + "{}: sending SetHigh command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender.send(GpioCmd::new(GpioCmdType::SetHigh, 20)).await; + async_input.wait_for_high().await.unwrap(); + defmt::info!( + "{}: Input pin is high now ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending SetLow command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender.send(GpioCmd::new(GpioCmdType::SetLow, 20)).await; + async_input.wait_for_low().await.unwrap(); + defmt::info!( + "{}: Input pin is low now ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending RisingEdge command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender.send(GpioCmd::new(GpioCmdType::RisingEdge, 20)).await; + async_input.wait_for_rising_edge().await.unwrap(); + defmt::info!( + "{}: input pin had rising edge ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending Falling command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender + .send(GpioCmd::new(GpioCmdType::FallingEdge, 20)) + .await; + async_input.wait_for_falling_edge().await.unwrap(); + defmt::info!( + "{}: input pin had a falling edge ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending Falling command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender + .send(GpioCmd::new(GpioCmdType::FallingEdge, 20)) + .await; + async_input.wait_for_any_edge().await.unwrap(); + defmt::info!( + "{}: input pin had a falling (any) edge ({} ms)", + ctx, + Instant::now().as_millis() + ); + + defmt::info!( + "{}: sending Falling command ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender.send(GpioCmd::new(GpioCmdType::RisingEdge, 20)).await; + async_input.wait_for_any_edge().await.unwrap(); + defmt::info!( + "{}: input pin had a rising (any) edge ({} ms)", + ctx, + Instant::now().as_millis() + ); + sender.send(GpioCmd::new(GpioCmdType::CloseTask, 0)).await; +} + +#[embassy_executor::task(pool_size = 8)] +async fn output_task( + ctx: &'static str, + mut out: Output, + receiver: Receiver<'static, ThreadModeRawMutex, GpioCmd, 3>, +) { + loop { + let next_cmd = receiver.receive().await; + Timer::after(Duration::from_millis(next_cmd.after_delay.into())).await; + match next_cmd.cmd_type { + GpioCmdType::SetHigh => { + defmt::info!("{}: Set output high", ctx); + out.set_high(); + } + GpioCmdType::SetLow => { + defmt::info!("{}: Set output low", ctx); + out.set_low(); + } + GpioCmdType::RisingEdge => { + defmt::info!("{}: Rising edge", ctx); + if !out.is_set_low() { + out.set_low(); + } + out.set_high(); + } + GpioCmdType::FallingEdge => { + defmt::info!("{}: Falling edge", ctx); + if !out.is_set_high() { + out.set_high(); + } + out.set_low(); + } + GpioCmdType::CloseTask => { + defmt::info!("{}: Closing task", ctx); + break; + } + } + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn PORTA1() { + on_interrupt_for_async_gpio_for_port(Port::A).unwrap(); +} + +#[interrupt] +#[allow(non_snake_case)] +fn PORTB1() { + on_interrupt_for_async_gpio_for_port(Port::B).unwrap(); +} + +#[interrupt] +#[allow(non_snake_case)] +fn PORTC15() { + on_interrupt_for_async_gpio_for_port(Port::C).unwrap(); +} + +#[interrupt] +#[allow(non_snake_case)] +fn PORTD3() { + on_interrupt_for_async_gpio_for_port(Port::D).unwrap(); +} + +#[interrupt] +#[allow(non_snake_case)] +fn PORTE1() { + on_interrupt_for_async_gpio_for_port(Port::E).unwrap(); +} + +#[interrupt] +#[allow(non_snake_case)] +fn PORTF1() { + on_interrupt_for_async_gpio_for_port(Port::F).unwrap(); +} diff --git a/va416xx/examples/embassy/src/bin/async-uart-rx.rs b/va416xx/examples/embassy/src/bin/async-uart-rx.rs new file mode 100644 index 0000000..3ec3449 --- /dev/null +++ b/va416xx/examples/embassy/src/bin/async-uart-rx.rs @@ -0,0 +1,103 @@ +//! Asynchronous UART reception example application. +//! +//! This application receives data on two UARTs permanently using a ring buffer. +//! The ring buffer are read them asynchronously. +//! It uses PORTG0 as TX pin and PORTG1 as RX pin, which is the UART0 on the PEB1 board. +//! +//! Instructions: +//! +//! 1. Tie a USB to UART converter with RX to PORTG0 and TX to PORTG1. +//! 2. Connect to the serial interface by using an application like Putty or picocom. You can +//! type something in the terminal and check if the data is echoed back. You can also check the +//! RTT logs to see received data. +#![no_std] +#![no_main] +// Import panic provider. +use panic_probe as _; +// Import logger. +use core::cell::RefCell; +use defmt_rtt as _; +use defmt_rtt as _; + +use critical_section::Mutex; +use embassy_example::EXTCLK_FREQ; +use embassy_executor::Spawner; +use embassy_time::Instant; +use embedded_io::Write; +use embedded_io_async::Read; +use heapless::spsc::{Producer, Queue}; +use va416xx_hal::{ + clock::ClockConfigurator, + gpio::{Output, PinState}, + pac::{self, interrupt}, + pins::PinsG, + prelude::*, + time::Hertz, + uart::{ + self, + rx_asynch::{on_interrupt_rx, RxAsync}, + Bank, + }, +}; + +static QUEUE_UART_A: static_cell::ConstStaticCell> = + static_cell::ConstStaticCell::new(Queue::new()); +static PRODUCER_UART_A: Mutex>>> = Mutex::new(RefCell::new(None)); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + defmt::println!("-- VA108xx Async UART RX Demo --"); + + let dp = pac::Peripherals::take().unwrap(); + + // Initialize the systick interrupt & obtain the token to prove that we did + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ)) + .freeze() + .unwrap(); + // Safety: Only called once here. + va416xx_embassy::init(dp.tim15, dp.tim14, &clocks); + + let portg = PinsG::new(dp.portg); + let mut led = Output::new(portg.pg5, PinState::Low); + + let uarta = + uart::Uart::new(dp.uart0, portg.pg0, portg.pg1, &clocks, 115200.Hz().into()).unwrap(); + + let (mut tx_uart_a, rx_uart_a) = uarta.split(); + let (prod_uart_a, cons_uart_a) = QUEUE_UART_A.take().split(); + // Pass the producer to the interrupt handler. + critical_section::with(|cs| { + *PRODUCER_UART_A.borrow(cs).borrow_mut() = Some(prod_uart_a); + }); + + // TODO: Add example for RxAsyncOverwriting using another UART. + let mut async_uart_rx = RxAsync::new(rx_uart_a, cons_uart_a); + let mut buf = [0u8; 256]; + loop { + defmt::info!("Current time UART A: {}", Instant::now().as_secs()); + led.toggle(); + let read_bytes = async_uart_rx.read(&mut buf).await.unwrap(); + let read_str = core::str::from_utf8(&buf[..read_bytes]).unwrap(); + defmt::info!( + "Read {} bytes asynchronously on UART A: {:?}", + read_bytes, + read_str + ); + tx_uart_a.write_all(read_str.as_bytes()).unwrap(); + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn UART0_RX() { + let mut prod = + critical_section::with(|cs| PRODUCER_UART_A.borrow(cs).borrow_mut().take().unwrap()); + let errors = on_interrupt_rx(Bank::Uart0, &mut prod); + critical_section::with(|cs| *PRODUCER_UART_A.borrow(cs).borrow_mut() = Some(prod)); + // In a production app, we could use a channel to send the errors to the main task. + if let Err(errors) = errors { + defmt::info!("UART A errors: {:?}", errors); + } +} diff --git a/va416xx/examples/embassy/src/bin/async-uart-tx.rs b/va416xx/examples/embassy/src/bin/async-uart-tx.rs new file mode 100644 index 0000000..ee4bae9 --- /dev/null +++ b/va416xx/examples/embassy/src/bin/async-uart-tx.rs @@ -0,0 +1,88 @@ +//! Asynchronous UART transmission example application. +//! +//! This application receives sends 4 strings with different sizes permanently. +//! It uses PORTG0 as TX pin and PORTG1 as RX pin, which is the UART0 on the PEB1 board. +//! +//! Instructions: +//! +//! 1. Tie a USB to UART converter with RX to PORTG0 and TX to PORTG1. +//! 2. Connect to the serial interface by using an application like Putty or picocom. You can +//! type something in the terminal and check if the data is echoed back. You can also check the +//! RTT logs to see received data. +#![no_std] +#![no_main] +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use embassy_example::EXTCLK_FREQ; +use embassy_executor::Spawner; +use embassy_time::{Duration, Instant, Ticker}; +use embedded_io_async::Write; +use va416xx_hal::{ + clock::ClockConfigurator, + gpio::{Output, PinState}, + pac::{self, interrupt}, + pins::PinsG, + prelude::*, + time::Hertz, + uart::{ + self, + tx_asynch::{on_interrupt_tx, TxAsync}, + Bank, + }, +}; + +const STR_LIST: &[&str] = &[ + "Hello World\r\n", + "Smoll\r\n", + "A string which is larger than the FIFO size\r\n", + "A really large string which is significantly larger than the FIFO size\r\n", +]; + +// main is itself an async function. +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + defmt::println!("-- VA108xx Async UART TX Demo --"); + + let dp = pac::Peripherals::take().unwrap(); + + // Initialize the systick interrupt & obtain the token to prove that we did + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ)) + .freeze() + .unwrap(); + // Safety: Only called once here. + va416xx_embassy::init(dp.tim15, dp.tim14, &clocks); + + let pinsg = PinsG::new(dp.portg); + let mut led = Output::new(pinsg.pg5, PinState::Low); + + let uarta = + uart::Uart::new(dp.uart0, pinsg.pg0, pinsg.pg1, &clocks, 115200.Hz().into()).unwrap(); + let (tx, _rx) = uarta.split(); + let mut async_tx = TxAsync::new(tx); + let mut ticker = Ticker::every(Duration::from_secs(1)); + let mut idx = 0; + loop { + defmt::println!("Current time: {}", Instant::now().as_secs()); + led.toggle(); + let _written = async_tx + .write(STR_LIST[idx].as_bytes()) + .await + .expect("writing failed"); + idx += 1; + if idx == STR_LIST.len() { + idx = 0; + } + ticker.next().await; + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn UART0_TX() { + on_interrupt_tx(Bank::Uart0); +} diff --git a/va416xx/examples/embassy/src/bin/can.rs b/va416xx/examples/embassy/src/bin/can.rs new file mode 100644 index 0000000..7907d70 --- /dev/null +++ b/va416xx/examples/embassy/src/bin/can.rs @@ -0,0 +1,239 @@ +#![no_std] +#![no_main] + +use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex; +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use embassy_example::EXTCLK_FREQ; +use embassy_executor::Spawner; +use va416xx_hal::can::asynch::{on_interrupt_can, CanTxAsync}; +use va416xx_hal::can::{ + Can, CanFrame, CanFrameNormal, CanFrameRtr, CanId, CanRx, CanTx, ClockConfig, +}; +use va416xx_hal::clock::ClockConfigurator; +use va416xx_hal::pac::{self, interrupt}; +use va416xx_hal::time::Hertz; +use va416xx_hal::{can, prelude::*}; + +const STANDARD_ID_0: can::StandardId = can::StandardId::new(0x42).unwrap(); +const STANDARD_ID_1: can::StandardId = can::StandardId::new(0x5).unwrap(); +const EXTENDED_ID_0: can::ExtendedId = can::ExtendedId::new(0x10).unwrap(); + +// Declare a bounded channel of 3 u32s. +static CAN_RX_CHANNEL: embassy_sync::channel::Channel< + CriticalSectionRawMutex, + (usize, CanFrame), + 3, +> = embassy_sync::channel::Channel::::new(); + +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + defmt::println!("-- VA416xx CAN Demo --"); + + let dp = pac::Peripherals::take().unwrap(); + + // Initialize the systick interrupt & obtain the token to prove that we did + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ)) + .freeze() + .unwrap(); + // Safety: Only called once here. + va416xx_embassy::init(dp.tim15, dp.tim14, &clocks); + defmt::info!("creating CAN peripheral driver"); + defmt::info!("clocks: {}", clocks); + let clk_config = ClockConfig::from_bitrate_and_segments(&clocks, 250.kHz(), 14, 5, 4) + .expect("CAN clock config error"); + let mut can = Can::new(dp.can0, clk_config); + can.modify_control(|mut val| { + val.set_loopback(true); + val.set_ignore_ack(true); + val.set_internal(true); + val.set_bufflock(true); + val.set_diag_enable(true); + val + }); + can.set_global_mask_for_exact_id_match_with_rtr_masked(); + can.set_base_mask_for_all_match(); + can.enable(); + let mut channels = can.take_channels().unwrap(); + // Transmit channel. + let mut tx = CanTx::new(channels.take(0).unwrap(), None); + // Base channel which has dedicated mask. + let mut rx_dedicated = CanRx::new(channels.take(1).unwrap()); + // Base channel which has dedicated mask. + let mut rx_base = CanRx::new(channels.take(14).unwrap()); + rx_base.configure_for_reception(); + + defmt::info!("Running blocking examples"); + + send_and_receive_on_dedicated_channel(&mut can, &mut tx, &mut rx_dedicated); + send_and_receive_rtr_on_dedicated_channel(&mut can, &mut tx, &mut rx_dedicated); + send_extended_on_base_channel(&mut can, &mut tx, &mut rx_base); + + defmt::info!("Running non-blocking (asycnhronous) examples"); + + non_blocking_example(&mut can, &mut rx_dedicated, &mut rx_base).await; + + defmt::info!("Non-blocking (asycnhronous) examples done"); + + loop { + cortex_m::asm::nop(); + } +} + +fn send_and_receive_on_dedicated_channel(can: &mut Can, tx: &mut CanTx, rx_dedicated: &mut CanRx) { + let send_data = &[1, 2, 3, 4]; + let sent_frame = + CanFrame::Normal(CanFrameNormal::new(can::Id::Standard(STANDARD_ID_0), send_data).unwrap()); + defmt::info!( + "sending CAN frame with ID {:#X} and data {}", + STANDARD_ID_0.as_raw(), + send_data + ); + rx_dedicated.configure_for_reception_with_standard_id(STANDARD_ID_0, false); + tx.transmit_frame(sent_frame).unwrap(); + // Await frame transmission completion. + nb::block!(tx.transfer_done()).unwrap(); + check_and_handle_errors(can); + let received_frame = nb::block!(rx_dedicated.receive(true)).expect("invalid CAN rx state"); + check_and_handle_errors(can); + assert_eq!(received_frame, sent_frame); + if let CanFrame::Normal(can_frame_normal) = received_frame { + if let can::Id::Standard(standard_id) = can_frame_normal.id() { + defmt::info!( + "received CAN frame with ID {:#X} and data {}", + standard_id.as_raw(), + can_frame_normal.data() + ); + } else { + panic!("unexpected CAN extended frame ID"); + } + } else { + defmt::error!("received unexpected CAN remote frame"); + } +} + +fn send_and_receive_rtr_on_dedicated_channel( + can: &mut Can, + tx: &mut CanTx, + rx_dedicated: &mut CanRx, +) { + let rtr_frame = CanFrame::Rtr(CanFrameRtr::new(can::Id::Standard(STANDARD_ID_1), 0)); + // RTR bit is masked, so the setting should not matter. + rx_dedicated.configure_for_reception_with_standard_id(STANDARD_ID_1, false); + tx.transmit_frame(rtr_frame).unwrap(); + // Await frame transmission completion. + nb::block!(tx.remote_transfer_done_with_tx_reconfig()).unwrap(); + check_and_handle_errors(can); + let received_frame = nb::block!(rx_dedicated.receive(true)).expect("invalid CAN rx state"); + check_and_handle_errors(can); + assert_eq!(received_frame, rtr_frame); + if let CanFrame::Rtr(can_frame_rtr) = received_frame { + if let can::Id::Standard(standard_id) = can_frame_rtr.id() { + defmt::info!("received CAN RTR frame with ID {:#X}", standard_id.as_raw(),); + } else { + panic!("unexpected CAN extended frame ID"); + } + } else { + defmt::error!("received unexpected CAN data frame"); + } +} + +fn check_and_handle_errors(can: &mut Can) { + let err_counter = can.read_error_counters(); + if err_counter.transmit() > 0 || err_counter.receive() > 0 { + defmt::warn!( + "error count tx {}, error count rx {}", + err_counter.transmit(), + err_counter.receive() + ); + let diag = can.read_error_diagnostics(); + defmt::warn!("EFID: {}, EBID: {}", diag.efid(), diag.ebid()); + } +} + +fn send_extended_on_base_channel(can: &mut Can, tx: &mut CanTx, rx: &mut CanRx) { + let send_data = &[4, 3, 2, 1]; + let sent_frame = + CanFrame::Normal(CanFrameNormal::new(can::Id::Extended(EXTENDED_ID_0), send_data).unwrap()); + tx.transmit_frame(sent_frame).unwrap(); + // Await frame transmission completion. + nb::block!(tx.transfer_done()).unwrap(); + check_and_handle_errors(can); + let received_frame = nb::block!(rx.receive(true)).expect("invalid CAN rx state"); + check_and_handle_errors(can); + assert_eq!(sent_frame, received_frame); + if let CanFrame::Normal(can_frame_normal) = received_frame { + if let can::Id::Extended(extended_id) = can_frame_normal.id() { + defmt::info!( + "received CAN frame with ID {:#X} and data {}", + extended_id.as_raw(), + can_frame_normal.data() + ); + } else { + panic!("unexpected CAN extended frame ID"); + } + } else { + defmt::error!("received unexpected CAN data frame"); + } +} + +async fn non_blocking_example(can: &mut Can, rx_dedicated: &mut CanRx, rx_base: &mut CanRx) { + let mut tx_async = CanTxAsync::new(can); + // Enable interrupts for RX channels. + rx_dedicated.enable_interrupt(true); + rx_base.enable_interrupt(true); + + // For asynchronous mode, all TX channels needs to be configured explicitely. Configuring more + // channels allows multiple active transfers when using the async API. + tx_async.configure_channel(0).unwrap(); + let send_data = &[1, 2, 3, 4]; + let send_frame = + CanFrame::Normal(CanFrameNormal::new(can::Id::Standard(STANDARD_ID_0), send_data).unwrap()); + let fut = tx_async.start_transmit(send_frame).unwrap(); + fut.await; + let (ch_idx, frame) = CAN_RX_CHANNEL.receive().await; + assert_eq!(send_frame, frame); + // Received on base channel. + assert_eq!(ch_idx, 14); + if let CanFrame::Normal(can_frame_normal) = frame { + if let can::Id::Standard(standard_id) = can_frame_normal.id() { + defmt::info!( + "received CAN frame with ID {:#X} and data {}", + standard_id.as_raw(), + can_frame_normal.data() + ); + } else { + panic!("unexpected CAN extended frame ID"); + } + } else { + defmt::error!("received unexpected CAN remote frame"); + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn CAN0() { + match on_interrupt_can(CanId::Can0, false).unwrap() { + can::asynch::InterruptResult::NoInterrupt => { + defmt::warn!("unexpected interrupt on CAN0"); + } + can::asynch::InterruptResult::ReceivedFrame { + channel_index, + frame, + } => { + CAN_RX_CHANNEL.try_send((channel_index, frame)).unwrap(); + } + can::asynch::InterruptResult::TransmissionEvent { channel_index, id } => { + defmt::info!( + "transmission event on channel {} with event ID {}", + channel_index, + id + ); + } + } +} diff --git a/va416xx/examples/embassy/src/bin/uart-echo-with-irq.rs b/va416xx/examples/embassy/src/bin/uart-echo-with-irq.rs new file mode 100644 index 0000000..769a471 --- /dev/null +++ b/va416xx/examples/embassy/src/bin/uart-echo-with-irq.rs @@ -0,0 +1,151 @@ +//! This is an example of using the UART HAL abstraction with the IRQ support and embassy. +//! +//! It uses the UART0 for communication with another MCU or a host computer (recommended). +//! You can connect a USB-to-Serial converter to the UART0 pins and then use a serial terminal +//! application like picocom to send data to the microcontroller, which should be echoed +//! back to the sender. +//! +//! This application uses the interrupt support of the VA416xx to read the data arriving +//! on the UART without requiring polling. +#![no_std] +#![no_main] +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use core::cell::RefCell; + +use embassy_example::EXTCLK_FREQ; +use embassy_executor::Spawner; +use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex; +use embassy_sync::blocking_mutex::Mutex; +use embassy_time::{Duration, Ticker}; +use embedded_io::Write; +use ringbuf::{ + traits::{Consumer, Observer, Producer}, + StaticRb, +}; +use va416xx_hal::{ + clock::ClockConfigurator, + gpio::{Output, PinState}, + pac::{self, interrupt}, + pins::PinsG, + time::Hertz, + uart, +}; + +pub type SharedUart = Mutex>>; +static RX: SharedUart = Mutex::new(RefCell::new(None)); + +const BAUDRATE: u32 = 115200; + +// Ring buffer size. +const RING_BUF_SIZE: usize = 2048; + +pub type SharedRingBuf = + Mutex>>>; +// Ring buffers to handling variable sized telemetry +static RINGBUF: SharedRingBuf = Mutex::new(RefCell::new(None)); + +// See https://embassy.dev/book/#_sharing_using_a_mutex for background information about sharing +// a peripheral with embassy. +#[embassy_executor::main] +async fn main(spawner: Spawner) { + defmt::println!("VA416xx UART-Embassy Example"); + + let dp = pac::Peripherals::take().unwrap(); + + // Initialize the systick interrupt & obtain the token to prove that we did + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ)) + .freeze() + .unwrap(); + // Safety: Only called once here. + va416xx_embassy::init(dp.tim15, dp.tim14, &clocks); + + let portg = PinsG::new(dp.portg); + + let uart0 = uart::Uart::new( + dp.uart0, + portg.pg0, + portg.pg1, + &clocks, + Hertz::from_raw(BAUDRATE).into(), + ) + .unwrap(); + let (mut tx, rx) = uart0.split(); + let mut rx = rx.into_rx_with_irq(); + rx.start(); + RX.lock(|static_rx| { + static_rx.borrow_mut().replace(rx); + }); + RINGBUF.lock(|static_rb| { + static_rb.borrow_mut().replace(StaticRb::default()); + }); + + let led = Output::new(portg.pg5, PinState::Low); + let mut ticker = Ticker::every(Duration::from_millis(50)); + let mut processing_buf: [u8; RING_BUF_SIZE] = [0; RING_BUF_SIZE]; + let mut read_bytes = 0; + spawner.spawn(blinky(led)).expect("failed to spawn blinky"); + loop { + RINGBUF.lock(|static_rb| { + let mut rb_borrow = static_rb.borrow_mut(); + let rb_mut = rb_borrow.as_mut().unwrap(); + read_bytes = rb_mut.occupied_len(); + rb_mut.pop_slice(&mut processing_buf[0..read_bytes]); + }); + // Simply send back all received data. + tx.write_all(&processing_buf[0..read_bytes]) + .expect("sending back read data failed"); + ticker.next().await; + } +} + +#[embassy_executor::task] +async fn blinky(mut led: Output) { + let mut ticker = Ticker::every(Duration::from_millis(500)); + loop { + led.toggle(); + ticker.next().await; + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn UART0_RX() { + let mut buf: [u8; 16] = [0; 16]; + let mut read_len: usize = 0; + let mut errors = None; + RX.lock(|static_rx| { + let mut rx_borrow = static_rx.borrow_mut(); + let rx_mut_ref = rx_borrow.as_mut().unwrap(); + let result = rx_mut_ref.on_interrupt(&mut buf); + read_len = result.bytes_read; + if result.errors.is_some() { + errors = result.errors; + } + }); + let mut ringbuf_full = false; + if read_len > 0 { + // Send the received buffer to the main thread for processing via a ring buffer. + RINGBUF.lock(|static_rb| { + let mut rb_borrow = static_rb.borrow_mut(); + let rb_mut_ref = rb_borrow.as_mut().unwrap(); + if rb_mut_ref.vacant_len() < read_len { + ringbuf_full = true; + for _ in rb_mut_ref.pop_iter() {} + } + rb_mut_ref.push_slice(&buf[0..read_len]); + }); + } + + if errors.is_some() { + defmt::info!("UART error: {:?}", errors); + } + if ringbuf_full { + defmt::info!("ringbuffer is full, deleted oldest data"); + } +} diff --git a/va416xx/examples/embassy/src/lib.rs b/va416xx/examples/embassy/src/lib.rs new file mode 100644 index 0000000..a0e30ef --- /dev/null +++ b/va416xx/examples/embassy/src/lib.rs @@ -0,0 +1,2 @@ +#![no_std] +pub const EXTCLK_FREQ: u32 = 40_000_000; diff --git a/va416xx/examples/embassy/src/main.rs b/va416xx/examples/embassy/src/main.rs new file mode 100644 index 0000000..c6d3da0 --- /dev/null +++ b/va416xx/examples/embassy/src/main.rs @@ -0,0 +1,63 @@ +#![no_std] +#![no_main] +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use embassy_example::EXTCLK_FREQ; +use embassy_executor::Spawner; +use embassy_time::{Duration, Instant, Ticker}; +use va416xx_hal::{ + clock::ClockConfigurator, + gpio::{Output, PinState}, + pac, + pins::PinsG, + time::Hertz, +}; + +cfg_if::cfg_if! { + if #[cfg(feature = "custom-irqs")] { + use va416xx_hal::pac::interrupt; + va416xx_embassy::embassy_time_driver_irqs!(timekeeper_irq = TIM12, alarm_irq = TIM11); + } +} + +// main is itself an async function. +#[embassy_executor::main] +async fn main(_spawner: Spawner) { + defmt::println!("VA416xx Embassy Demo"); + + let dp = pac::Peripherals::take().unwrap(); + + // Initialize the systick interrupt & obtain the token to prove that we did + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ)) + .freeze() + .unwrap(); + // Safety: Only called once here. + cfg_if::cfg_if! { + if #[cfg(not(feature = "custom-irqs"))] { + va416xx_embassy::init( + dp.tim15, + dp.tim14, + &clocks + ); + } else { + va416xx_embassy::init( + dp.tim12, + dp.tim11, + &clocks + ); + } + } + let pinsg = PinsG::new(dp.portg); + let mut led = Output::new(pinsg.pg5, PinState::Low); + let mut ticker = Ticker::every(Duration::from_secs(1)); + loop { + ticker.next().await; + defmt::info!("Current time: {}", Instant::now().as_secs()); + led.toggle(); + } +} diff --git a/va416xx/examples/rtic/Cargo.toml b/va416xx/examples/rtic/Cargo.toml new file mode 100644 index 0000000..6d65e71 --- /dev/null +++ b/va416xx/examples/rtic/Cargo.toml @@ -0,0 +1,20 @@ +[package] +name = "rtic-example" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +defmt-rtt = "1" +defmt = "1" +panic-probe = { version = "1", features = ["defmt"] } + +va416xx-hal = { version = "0.6", path = "../../va416xx-hal", features = ["va41630"] } + +[dependencies.rtic] +version = "2" +features = ["thumbv7-backend"] + +[dependencies.rtic-monotonics] +version = "2" +features = ["cortex-m-systick"] diff --git a/va416xx/examples/rtic/src/bin/rtic-empty.rs b/va416xx/examples/rtic/src/bin/rtic-empty.rs new file mode 100644 index 0000000..d0e7a19 --- /dev/null +++ b/va416xx/examples/rtic/src/bin/rtic-empty.rs @@ -0,0 +1,31 @@ +//! Empty RTIC project template +#![no_main] +#![no_std] + +#[rtic::app(device = pac)] +mod app { + // Import panic provider. + use panic_probe as _; + // Import logger. + use defmt_rtt as _; + use va416xx_hal::pac; + + #[local] + struct Local {} + + #[shared] + struct Shared {} + + #[init] + fn init(_ctx: init::Context) -> (Shared, Local) { + defmt::println!("-- Vorago RTIC template --"); + (Shared {}, Local {}) + } + + // `shared` cannot be accessed from this context + #[idle] + fn idle(_cx: idle::Context) -> ! { + #[allow(clippy::empty_loop)] + loop {} + } +} diff --git a/va416xx/examples/rtic/src/main.rs b/va416xx/examples/rtic/src/main.rs new file mode 100644 index 0000000..5e2e9d7 --- /dev/null +++ b/va416xx/examples/rtic/src/main.rs @@ -0,0 +1,69 @@ +//! RTIC minimal blinky +#![no_main] +#![no_std] + +use va416xx_hal::time::Hertz; + +const EXTCLK_FREQ: Hertz = Hertz::from_raw(40_000_000); + +#[rtic::app(device = pac, dispatchers = [U1, U2, U3])] +mod app { + use super::*; + // Import panic provider. + use panic_probe as _; + // Import logger. + use cortex_m::asm; + use defmt_rtt as _; + use rtic_monotonics::systick::prelude::*; + use rtic_monotonics::Monotonic; + use va416xx_hal::{ + clock::ClockConfigurator, + gpio::{Output, PinState}, + pac, + pins::PinsG, + }; + + #[local] + struct Local { + led: Output, + } + + #[shared] + struct Shared {} + + rtic_monotonics::systick_monotonic!(Mono, 1_000); + + #[init] + fn init(cx: init::Context) -> (Shared, Local) { + defmt::println!("-- Vorago RTIC example application --"); + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(cx.device.clkgen) + .xtal_n_clk_with_src_freq(EXTCLK_FREQ) + .freeze() + .unwrap(); + Mono::start(cx.core.SYST, clocks.sysclk().raw()); + let pinsg = PinsG::new(cx.device.portg); + let led = Output::new(pinsg.pg5, PinState::Low); + blinky::spawn().ok(); + (Shared {}, Local { led }) + } + + // `shared` cannot be accessed from this context + #[idle] + fn idle(_cx: idle::Context) -> ! { + loop { + asm::nop(); + } + } + + #[task( + priority = 3, + local=[led], + )] + async fn blinky(cx: blinky::Context) { + loop { + cx.local.led.toggle(); + Mono::delay(200.millis()).await; + } + } +} diff --git a/va416xx/examples/simple/Cargo.toml b/va416xx/examples/simple/Cargo.toml new file mode 100644 index 0000000..9b6053b --- /dev/null +++ b/va416xx/examples/simple/Cargo.toml @@ -0,0 +1,43 @@ +[package] +name = "simple_examples" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +cortex-m-rt = "0.7" +critical-section = "1" +defmt-rtt = "1" +defmt = "1" +panic-probe = { version = "1", features = ["defmt"] } +embedded-hal = "1" +embedded-hal-nb = "1" +nb = "1" +embedded-io = "0.6" +panic-halt = "1" +accelerometer = "0.12" + +va416xx-hal = { version = "0.6", path = "../../va416xx-hal", features = ["va41630", "defmt"] } + +[dependencies.vorago-peb1] +path = "../../vorago-peb1" +optional = true + +[features] +default = ["va41630"] +va41630 = ["va416xx-hal/va41630", "has-adc-dac"] +va41629 = ["va416xx-hal/va41629", "has-adc-dac"] +va41628 = ["va416xx-hal/va41628"] +has-adc-dac = [] + +[[example]] +name = "peb1-accelerometer" +required-features = ["vorago-peb1"] + +[[example]] +name = "dac-adc" +required-features = ["has-adc-dac"] + +[[example]] +name = "adc" +required-features = ["has-adc-dac"] diff --git a/va416xx/examples/simple/examples/adc.rs b/va416xx/examples/simple/examples/adc.rs new file mode 100644 index 0000000..fe11eff --- /dev/null +++ b/va416xx/examples/simple/examples/adc.rs @@ -0,0 +1,73 @@ +//! Simple ADC example. +#![no_main] +#![no_std] + +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use simple_examples::peb1; +use va416xx_hal::{ + adc::{Adc, ChannelSelect, ChannelValue, MultiChannelSelect}, + clock::ClockConfigurator, + pac, + timer::CountdownTimer, +}; + +// Quite spammy and disabled by default. +const ENABLE_BUF_PRINTOUT: bool = false; + +#[entry] +fn main() -> ! { + defmt::println!("VA416xx ADC example"); + + let dp = pac::Peripherals::take().unwrap(); + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze() + .unwrap(); + + let adc = Adc::new_with_channel_tag(dp.adc, &clocks); + let mut delay = CountdownTimer::new(dp.tim0, &clocks); + let mut read_buf: [ChannelValue; 8] = [ChannelValue::default(); 8]; + loop { + let single_value = adc + .trigger_and_read_single_channel(va416xx_hal::adc::ChannelSelect::TempSensor) + .expect("reading single channel value failed"); + defmt::info!( + "Read single ADC value on temperature sensor channel: {:?}", + single_value + ); + let read_num = adc + .sweep_and_read_range(0, 7, &mut read_buf) + .expect("ADC range read failed"); + if ENABLE_BUF_PRINTOUT { + defmt::info!("ADC Range Read (0-8) read {} values", read_num); + defmt::info!("ADC Range Read (0-8): {:?}", read_buf); + } + assert_eq!(read_num, 8); + for (idx, ch_val) in read_buf.iter().enumerate() { + assert_eq!( + ch_val.channel(), + ChannelSelect::try_from(idx as u8).unwrap() + ); + } + + adc.sweep_and_read_multiselect( + MultiChannelSelect::AnIn0 | MultiChannelSelect::AnIn2 | MultiChannelSelect::TempSensor, + &mut read_buf[0..3], + ) + .expect("ADC multiselect read failed"); + if ENABLE_BUF_PRINTOUT { + defmt::info!("ADC Multiselect Read(0, 2 and 10): {:?}", &read_buf[0..3]); + } + assert_eq!(read_buf[0].channel(), ChannelSelect::AnIn0); + assert_eq!(read_buf[1].channel(), ChannelSelect::AnIn2); + assert_eq!(read_buf[2].channel(), ChannelSelect::TempSensor); + delay.delay_ms(500); + } +} diff --git a/va416xx/examples/simple/examples/blinky-pac.rs b/va416xx/examples/simple/examples/blinky-pac.rs new file mode 100644 index 0000000..1f99f28 --- /dev/null +++ b/va416xx/examples/simple/examples/blinky-pac.rs @@ -0,0 +1,33 @@ +//! Simple blinky example +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use panic_halt as _; +use va416xx_hal::pac; + +// Mask for the LED +const LED_PG5: u32 = 1 << 5; + +#[entry] +fn main() -> ! { + let dp = pac::Peripherals::take().unwrap(); + // Enable all peripheral clocks + dp.sysconfig + .peripheral_clk_enable() + .modify(|_, w| unsafe { w.bits(0xffffffff) }); + dp.portg.dir().modify(|_, w| unsafe { w.bits(LED_PG5) }); + dp.portg + .datamask() + .modify(|_, w| unsafe { w.bits(LED_PG5) }); + for _ in 0..10 { + dp.portg.clrout().write(|w| unsafe { w.bits(LED_PG5) }); + cortex_m::asm::delay(2_000_000); + dp.portg.setout().write(|w| unsafe { w.bits(LED_PG5) }); + cortex_m::asm::delay(2_000_000); + } + loop { + dp.portg.togout().write(|w| unsafe { w.bits(LED_PG5) }); + cortex_m::asm::delay(2_000_000); + } +} diff --git a/va416xx/examples/simple/examples/blinky.rs b/va416xx/examples/simple/examples/blinky.rs new file mode 100644 index 0000000..2c29855 --- /dev/null +++ b/va416xx/examples/simple/examples/blinky.rs @@ -0,0 +1,28 @@ +//! Simple blinky example using the HAL +#![no_main] +#![no_std] + +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use cortex_m_rt::entry; +use va416xx_hal::{ + gpio::{Output, PinState}, + pac, + pins::PinsG, +}; + +#[entry] +fn main() -> ! { + defmt::println!("VA416xx HAL blinky example"); + + let dp = pac::Peripherals::take().unwrap(); + let portg = PinsG::new(dp.portg); + let mut led = Output::new(portg.pg5, PinState::Low); + loop { + cortex_m::asm::delay(2_000_000); + led.toggle(); + } +} diff --git a/va416xx/examples/simple/examples/dac-adc.rs b/va416xx/examples/simple/examples/dac-adc.rs new file mode 100644 index 0000000..3d326fe --- /dev/null +++ b/va416xx/examples/simple/examples/dac-adc.rs @@ -0,0 +1,77 @@ +//! Simple DAC-ADC example. +#![no_main] +#![no_std] + +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use simple_examples::peb1; +use va416xx_hal::{adc::Adc, clock::ClockConfigurator, dac::Dac, pac, timer::CountdownTimer}; + +const DAC_INCREMENT: u16 = 256; + +#[derive(Debug, PartialEq, Eq)] +pub enum AppMode { + // Measurements on AIN0. + AdcOnly, + // AOUT0. You can use a multi-meter to measure the changing voltage on the pin. + DacOnly, + /// AOUT0 needs to be wired to AIN0. + DacAndAdc, +} + +const APP_MODE: AppMode = AppMode::DacAndAdc; + +#[entry] +fn main() -> ! { + defmt::println!("VA416xx DAC/ADC example"); + + let dp = pac::Peripherals::take().unwrap(); + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze() + .unwrap(); + let mut dac = None; + if APP_MODE == AppMode::DacOnly || APP_MODE == AppMode::DacAndAdc { + dac = Some(Dac::new( + dp.dac0, + va416xx_hal::dac::DacSettling::Apb2Times100, + &clocks, + )); + } + let mut adc = None; + if APP_MODE == AppMode::AdcOnly || APP_MODE == AppMode::DacAndAdc { + adc = Some(Adc::new(dp.adc, &clocks)); + } + let mut delay_provider = CountdownTimer::new(dp.tim0, &clocks); + let mut current_val = 0; + loop { + if let Some(dac) = &mut dac { + defmt::info!("loading DAC with value {}", current_val); + dac.load_and_trigger_manually(current_val) + .expect("loading DAC value failed"); + if current_val + DAC_INCREMENT >= 4096 { + current_val = 0; + } else { + current_val += DAC_INCREMENT; + } + } + if let Some(dac) = &dac { + // This should never block. + nb::block!(dac.is_settled()).unwrap(); + } + if let Some(adc) = &adc { + let ch_value = adc + .trigger_and_read_single_channel(va416xx_hal::adc::ChannelSelect::AnIn0) + .expect("reading ADC channel 0 failed"); + defmt::info!("Received channel value {:?}", ch_value); + } + + delay_provider.delay_ms(500); + } +} diff --git a/va416xx/examples/simple/examples/dma.rs b/va416xx/examples/simple/examples/dma.rs new file mode 100644 index 0000000..f44e7bf --- /dev/null +++ b/va416xx/examples/simple/examples/dma.rs @@ -0,0 +1,277 @@ +//! Simple DMA example +#![no_main] +#![no_std] + +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; +use va416xx_hal::clock::ClockConfigurator; + +use core::cell::Cell; + +use cortex_m_rt::entry; +use critical_section::Mutex; +use embedded_hal::delay::DelayNs; +use simple_examples::peb1; +use va416xx_hal::dma::{Dma, DmaChannel, DmaConfig, DmaCtrlBlock}; +use va416xx_hal::irq_router::enable_and_init_irq_router; +use va416xx_hal::pac::{self, interrupt}; +use va416xx_hal::timer::CountdownTimer; + +static DMA_DONE_FLAG: Mutex> = Mutex::new(Cell::new(false)); +static DMA_ACTIVE_FLAG: Mutex> = Mutex::new(Cell::new(false)); + +// Place the DMA control block into SRAM1 statically. This section needs to be defined in +// memory.x +#[link_section = ".sram1"] +static mut DMA_CTRL_BLOCK: DmaCtrlBlock = DmaCtrlBlock::new(); + +// We can use statically allocated buffers for DMA transfers as well, and we can also place +// those into SRAM1. +#[link_section = ".sram1"] +static mut DMA_SRC_BUF: [u16; 36] = [0; 36]; +#[link_section = ".sram1"] +static mut DMA_DEST_BUF: [u16; 36] = [0; 36]; + +#[entry] +fn main() -> ! { + defmt::println!("VA416xx DMA example"); + + let dp = pac::Peripherals::take().unwrap(); + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze() + .unwrap(); + enable_and_init_irq_router(); + // Safety: The DMA control block has an alignment rule of 128 and we constructed it directly + // statically. + let dma = Dma::new( + dp.dma, + DmaConfig::default(), + core::ptr::addr_of_mut!(DMA_CTRL_BLOCK), + ) + .expect("error creating DMA"); + let (mut dma0, _, _, _) = dma.split(); + let mut delay_ms = CountdownTimer::new(dp.tim0, &clocks); + let mut src_buf_8_bit: [u8; 65] = [0; 65]; + let mut dest_buf_8_bit: [u8; 65] = [0; 65]; + let mut src_buf_32_bit: [u32; 17] = [0; 17]; + let mut dest_buf_32_bit: [u32; 17] = [0; 17]; + loop { + // This example uses stack-allocated buffers. + transfer_example_8_bit( + &mut src_buf_8_bit, + &mut dest_buf_8_bit, + &mut dma0, + &mut delay_ms, + ); + delay_ms.delay_ms(500); + // This example uses statically allocated buffers. + transfer_example_16_bit(&mut dma0, &mut delay_ms); + delay_ms.delay_ms(500); + transfer_example_32_bit( + &mut src_buf_32_bit, + &mut dest_buf_32_bit, + &mut dma0, + &mut delay_ms, + ); + delay_ms.delay_ms(500); + } +} + +fn transfer_example_8_bit( + src_buf: &mut [u8; 65], + dest_buf: &mut [u8; 65], + dma0: &mut DmaChannel, + delay: &mut CountdownTimer, +) { + (0..64).for_each(|i| { + src_buf[i] = i as u8; + }); + critical_section::with(|cs| { + DMA_DONE_FLAG.borrow(cs).set(false); + }); + critical_section::with(|cs| { + DMA_ACTIVE_FLAG.borrow(cs).set(false); + }); + // Safety: The source and destination buffer are valid for the duration of the DMA transfer. + unsafe { + dma0.prepare_mem_to_mem_transfer_8_bit(src_buf, dest_buf) + .expect("error preparing transfer"); + } + // Enable all interrupts. + // Safety: Not using mask based critical sections. + unsafe { + dma0.enable_done_interrupt(); + dma0.enable_active_interrupt(); + }; + // Enable the individual channel. + dma0.enable(); + // We still need to manually trigger the DMA request. + dma0.trigger_with_sw_request(); + // Use polling for completion status. + loop { + let mut dma_done = false; + critical_section::with(|cs| { + if DMA_ACTIVE_FLAG.borrow(cs).get() { + defmt::info!("DMA0 is active with 8 bit transfer"); + DMA_ACTIVE_FLAG.borrow(cs).set(false); + } + if DMA_DONE_FLAG.borrow(cs).get() { + dma_done = true; + } + }); + if dma_done { + defmt::info!("8-bit transfer done"); + break; + } + delay.delay_ms(1); + } + (0..64).for_each(|i| { + assert_eq!(dest_buf[i], i as u8); + }); + // Sentinel value, should be 0. + assert_eq!(dest_buf[64], 0); + dest_buf.fill(0); +} + +fn transfer_example_16_bit(dma0: &mut DmaChannel, delay_ms: &mut CountdownTimer) { + let dest_buf_ref = unsafe { &mut *core::ptr::addr_of_mut!(DMA_DEST_BUF[0..33]) }; + unsafe { + // Set values scaled from 0 to 65535 to verify this is really a 16-bit transfer. + (0..32).for_each(|i| { + DMA_SRC_BUF[i] = (i as u32 * u16::MAX as u32 / (dest_buf_ref.len() as u32 - 1)) as u16; + }); + } + critical_section::with(|cs| { + DMA_DONE_FLAG.borrow(cs).set(false); + }); + critical_section::with(|cs| { + DMA_ACTIVE_FLAG.borrow(cs).set(false); + }); + // Safety: The source and destination buffer are valid for the duration of the DMA transfer. + unsafe { + dma0.prepare_mem_to_mem_transfer_16_bit( + &*core::ptr::addr_of!(DMA_SRC_BUF[0..32]), + &mut dest_buf_ref[0..32], + ) + .expect("error preparing transfer"); + } + // Enable all interrupts. + // Safety: Not using mask based critical sections. + unsafe { + dma0.enable_done_interrupt(); + dma0.enable_active_interrupt(); + }; + // Enable the individual channel. + dma0.enable(); + // We still need to manually trigger the DMA request. + dma0.trigger_with_sw_request(); + // Use polling for completion status. + loop { + let mut dma_done = false; + critical_section::with(|cs| { + if DMA_ACTIVE_FLAG.borrow(cs).get() { + defmt::info!("DMA0 is active with 16-bit transfer"); + DMA_ACTIVE_FLAG.borrow(cs).set(false); + } + if DMA_DONE_FLAG.borrow(cs).get() { + dma_done = true; + } + }); + if dma_done { + defmt::info!("16-bit transfer done"); + break; + } + delay_ms.delay_ms(1); + } + (0..32).for_each(|i| { + assert_eq!( + dest_buf_ref[i], + (i as u32 * u16::MAX as u32 / (dest_buf_ref.len() as u32 - 1)) as u16 + ); + }); + // Sentinel value, should be 0. + assert_eq!(dest_buf_ref[32], 0); + dest_buf_ref.fill(0); +} + +fn transfer_example_32_bit( + src_buf: &mut [u32; 17], + dest_buf: &mut [u32; 17], + dma0: &mut DmaChannel, + delay_ms: &mut CountdownTimer, +) { + // Set values scaled from 0 to 65535 to verify this is really a 16-bit transfer. + (0..16).for_each(|i| { + src_buf[i] = (i as u64 * u32::MAX as u64 / (src_buf.len() - 1) as u64) as u32; + }); + critical_section::with(|cs| { + DMA_DONE_FLAG.borrow(cs).set(false); + }); + critical_section::with(|cs| { + DMA_ACTIVE_FLAG.borrow(cs).set(false); + }); + // Safety: The source and destination buffer are valid for the duration of the DMA transfer. + unsafe { + dma0.prepare_mem_to_mem_transfer_32_bit(src_buf, dest_buf) + .expect("error preparing transfer"); + } + // Enable all interrupts. + // Safety: Not using mask based critical sections. + unsafe { + dma0.enable_done_interrupt(); + dma0.enable_active_interrupt(); + }; + // Enable the individual channel. + dma0.enable(); + // We still need to manually trigger the DMA request. + dma0.trigger_with_sw_request(); + // Use polling for completion status. + loop { + let mut dma_done = false; + critical_section::with(|cs| { + if DMA_ACTIVE_FLAG.borrow(cs).get() { + defmt::info!("DMA0 is active with 32-bit transfer"); + DMA_ACTIVE_FLAG.borrow(cs).set(false); + } + if DMA_DONE_FLAG.borrow(cs).get() { + dma_done = true; + } + }); + if dma_done { + defmt::info!("32-bit transfer done"); + break; + } + delay_ms.delay_ms(1); + } + (0..16).for_each(|i| { + assert_eq!( + dest_buf[i], + (i as u64 * u32::MAX as u64 / (src_buf.len() - 1) as u64) as u32 + ); + }); + // Sentinel value, should be 0. + assert_eq!(dest_buf[16], 0); + dest_buf.fill(0); +} + +#[interrupt] +#[allow(non_snake_case)] +fn DMA_DONE0() { + // Notify the main loop that the DMA transfer is finished. + critical_section::with(|cs| { + DMA_DONE_FLAG.borrow(cs).set(true); + }); +} + +#[interrupt] +#[allow(non_snake_case)] +fn DMA_ACTIVE0() { + // Notify the main loop that the DMA 0 is active now. + critical_section::with(|cs| { + DMA_ACTIVE_FLAG.borrow(cs).set(true); + }); +} diff --git a/va416xx/examples/simple/examples/peb1-accelerometer.rs b/va416xx/examples/simple/examples/peb1-accelerometer.rs new file mode 100644 index 0000000..3e19cf2 --- /dev/null +++ b/va416xx/examples/simple/examples/peb1-accelerometer.rs @@ -0,0 +1,100 @@ +//! Example code for the PEB1 development board accelerometer. +#![no_main] +#![no_std] + +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use accelerometer::{Accelerometer, RawAccelerometer}; +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use simple_examples::peb1; +use va416xx_hal::{ + clock::ClockConfigurator, + i2c, + pac::{self}, + prelude::*, + timer::CountdownTimer, +}; +use vorago_peb1::lis2dh12::{self, detect_i2c_addr, FullScale, Odr}; + +pub enum DisplayMode { + Raw, + Normalized, +} + +const DISPLAY_MODE: DisplayMode = DisplayMode::Normalized; + +#[entry] +fn main() -> ! { + let mut dp = pac::Peripherals::take().unwrap(); + defmt::println!("-- Vorago PEB1 accelerometer example --"); + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze() + .unwrap(); + let mut i2c_master = i2c::I2cMaster::new( + dp.i2c0, + &clocks, + i2c::MasterConfig::default(), + i2c::I2cSpeed::Regular100khz, + ) + .expect("creating I2C master failed"); + let mut delay_provider = CountdownTimer::new(dp.tim1, &clocks); + // Detect the I2C address of the accelerometer by scanning all possible values. + let slave_addr = detect_i2c_addr(&mut i2c_master).expect("detecting I2C address failed"); + // Create the accelerometer driver using the PEB1 BSP. + let mut accelerometer = vorago_peb1::accelerometer::new_with_i2cm(i2c_master, slave_addr) + .expect("creating accelerometer driver failed"); + let device_id = accelerometer.get_device_id().unwrap(); + accelerometer + .set_mode(lis2dh12::Mode::Normal) + .expect("setting mode failed"); + accelerometer + .set_odr(Odr::Hz100) + .expect("setting ODR failed"); + accelerometer + .set_fs(FullScale::G4) + .expect("setting full scale failed"); + // This function also enabled BDU. + accelerometer + .enable_temp(true) + .expect("enabling temperature sensor failed"); + defmt::info!("Device ID: 0x{:02X}", device_id); + // Start reading the accelerometer periodically. + loop { + let temperature = accelerometer + .get_temp_outf() + .expect("reading temperature failed"); + match DISPLAY_MODE { + DisplayMode::Normalized => { + let value = accelerometer + .accel_norm() + .expect("reading normalized accelerometer data failed"); + defmt::info!( + "Accel Norm F32x3 {{ x: {:05}, y: {:05}, z:{:05}}} | Temp {} °C", + value.x, + value.y, + value.z, + temperature + ); + } + DisplayMode::Raw => { + let value_raw = accelerometer + .accel_raw() + .expect("reading raw accelerometer data failed"); + defmt::info!( + "Accel Raw I32x3 {{ x: {:05}, y: {:05}, z:{:05}}} | Temp {} °C", + value_raw.x, + value_raw.y, + value_raw.z, + temperature + ); + } + } + delay_provider.delay_ms(100); + } +} diff --git a/va416xx/examples/simple/examples/pwm.rs b/va416xx/examples/simple/examples/pwm.rs new file mode 100644 index 0000000..b5a76f1 --- /dev/null +++ b/va416xx/examples/simple/examples/pwm.rs @@ -0,0 +1,77 @@ +//! Simple PWM example +//! +//! Outputs a PWM waveform on pin PG2. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::{delay::DelayNs, pwm::SetDutyCycle}; +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; +use simple_examples::peb1; +use va416xx_hal::{ + clock::ClockConfigurator, + pac, + pins::PinsG, + prelude::*, + pwm::{get_duty_from_percent, PwmA, PwmB, PwmPin}, + timer::CountdownTimer, +}; + +#[entry] +fn main() -> ! { + defmt::println!("-- VA108xx PWM example application--"); + let dp = pac::Peripherals::take().unwrap(); + + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze() + .unwrap(); + + let pinsg = PinsG::new(dp.portg); + let mut pwm = PwmPin::new(pinsg.pg2, dp.tim9, &clocks, 10.Hz()).unwrap(); + let mut delay_timer = CountdownTimer::new(dp.tim0, &clocks); + let mut current_duty_cycle = 0.0; + pwm.set_duty_cycle(get_duty_from_percent(current_duty_cycle)) + .unwrap(); + pwm.enable(); + + // Delete type information, increased code readibility for the rest of the code + loop { + let mut counter = 0; + // Increase duty cycle continuously + while current_duty_cycle < 1.0 { + delay_timer.delay_ms(400); + current_duty_cycle += 0.02; + counter += 1; + if counter % 10 == 0 { + defmt::info!("current duty cycle: {}", current_duty_cycle); + } + + pwm.set_duty_cycle(get_duty_from_percent(current_duty_cycle)) + .unwrap(); + } + + // Switch to PWMB and decrease the window with a high signal from 100 % to 0 % + // continously + current_duty_cycle = 0.0; + let mut upper_limit = 1.0; + let mut lower_limit = 0.0; + let mut pwmb: PwmPin = PwmPin::from(pwm); + pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit)); + pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit)); + while lower_limit < 0.5 { + delay_timer.delay_ms(400); + lower_limit += 0.01; + upper_limit -= 0.01; + pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit)); + pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit)); + defmt::info!("Lower limit: {}", pwmb.pwmb_lower_limit()); + defmt::info!("Upper limit: {}", pwmb.pwmb_upper_limit()); + } + pwm = PwmPin::::from(pwmb); + } +} diff --git a/va416xx/examples/simple/examples/spi.rs b/va416xx/examples/simple/examples/spi.rs new file mode 100644 index 0000000..092f6b3 --- /dev/null +++ b/va416xx/examples/simple/examples/spi.rs @@ -0,0 +1,87 @@ +//! SPI example application. +//! +//! If you do not use the loopback mode, MOSI and MISO need to be tied together on the board. +#![no_main] +#![no_std] +use embedded_hal::delay::DelayNs; +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use cortex_m_rt::entry; +use embedded_hal::spi::{Mode, SpiBus, MODE_0}; +use simple_examples::peb1; +use va416xx_hal::clock::ClockConfigurator; +use va416xx_hal::spi::{Spi, SpiClockConfig}; +use va416xx_hal::timer::CountdownTimer; +use va416xx_hal::{ + pac, + pins::{PinsB, PinsC}, + spi::SpiConfig, + time::Hertz, +}; + +#[derive(PartialEq, Debug)] +pub enum ExampleSelect { + // Enter loopback mode. It is not necessary to tie MOSI/MISO together for this + Loopback, + // You need to tie together MOSI/MISO in this mode. + MosiMisoTiedTogether, +} + +const EXAMPLE_SEL: ExampleSelect = ExampleSelect::Loopback; +const SPI_SPEED_KHZ: u32 = 1000; +const SPI_MODE: Mode = MODE_0; +const BLOCKMODE: bool = true; +const FILL_WORD: u8 = 0x0f; + +#[entry] +fn main() -> ! { + defmt::println!("-- VA108xx SPI example application--"); + let dp = pac::Peripherals::take().unwrap(); + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze() + .unwrap(); + let mut delay = CountdownTimer::new(dp.tim1, &clocks); + + let pins_b = PinsB::new(dp.portb); + let pins_c = PinsC::new(dp.portc); + + let mut spi_cfg = SpiConfig::default() + .clk_cfg( + SpiClockConfig::from_clks(&clocks, Hertz::from_raw(SPI_SPEED_KHZ)) + .expect("invalid target clock"), + ) + .mode(SPI_MODE) + .blockmode(BLOCKMODE); + if EXAMPLE_SEL == ExampleSelect::Loopback { + spi_cfg = spi_cfg.loopback(true) + } + // Create SPI peripheral. + let mut spi0 = Spi::new(dp.spi0, (pins_b.pb15, pins_c.pc0, pins_c.pc1), spi_cfg).unwrap(); + spi0.set_fill_word(FILL_WORD); + loop { + let tx_buf: [u8; 4] = [1, 2, 3, 0]; + let mut rx_buf: [u8; 4] = [0; 4]; + // Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up. + spi0.write(&[0x42, 0x43]).expect("write failed"); + + // Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up. + spi0.read(&mut rx_buf[0..2]).unwrap(); + + // If the pins are tied together, we should received exactly what we send. + + let mut inplace_buf = tx_buf; + spi0.transfer_in_place(&mut inplace_buf) + .expect("SPI transfer_in_place failed"); + assert_eq!([1, 2, 3, 0], inplace_buf); + + spi0.transfer(&mut rx_buf, &tx_buf) + .expect("SPI transfer failed"); + assert_eq!(rx_buf, [1, 2, 3, 0]); + delay.delay_ms(500); + } +} diff --git a/va416xx/examples/simple/examples/timer-ticks.rs b/va416xx/examples/simple/examples/timer-ticks.rs new file mode 100644 index 0000000..a9cda46 --- /dev/null +++ b/va416xx/examples/simple/examples/timer-ticks.rs @@ -0,0 +1,70 @@ +//! MS and Second counter implemented using the TIM0 and TIM1 peripheral +#![no_main] +#![no_std] +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use core::sync::atomic::{AtomicU32, Ordering}; +use cortex_m::asm; +use cortex_m_rt::entry; +use simple_examples::peb1; +use va416xx_hal::{ + clock::ClockConfigurator, + irq_router::enable_and_init_irq_router, + pac::{self, interrupt}, + prelude::*, + timer::CountdownTimer, +}; + +#[allow(dead_code)] +enum LibType { + Pac, + Hal, +} + +static MS_COUNTER: AtomicU32 = AtomicU32::new(0); +static SEC_COUNTER: AtomicU32 = AtomicU32::new(0); + +#[entry] +fn main() -> ! { + let dp = pac::Peripherals::take().unwrap(); + let mut last_ms = 0; + defmt::println!("-- Vorago system ticks using timers --"); + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze() + .unwrap(); + enable_and_init_irq_router(); + let mut ms_timer = CountdownTimer::new(dp.tim0, &clocks); + ms_timer.enable_interrupt(true); + ms_timer.start(1.Hz()); + let mut second_timer = CountdownTimer::new(dp.tim1, &clocks); + second_timer.enable_interrupt(true); + second_timer.start(1.Hz()); + loop { + let current_ms = MS_COUNTER.load(Ordering::Relaxed); + if current_ms >= last_ms + 1000 { + // To prevent drift. + last_ms += 1000; + defmt::info!("MS counter: {}", current_ms); + let second = SEC_COUNTER.load(Ordering::Relaxed); + defmt::info!("Second counter: {}", second); + } + asm::delay(1000); + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn TIM0() { + MS_COUNTER.fetch_add(1, Ordering::Relaxed); +} + +#[interrupt] +#[allow(non_snake_case)] +fn TIM1() { + SEC_COUNTER.fetch_add(1, Ordering::Relaxed); +} diff --git a/va416xx/examples/simple/examples/uart.rs b/va416xx/examples/simple/examples/uart.rs new file mode 100644 index 0000000..e2308e9 --- /dev/null +++ b/va416xx/examples/simple/examples/uart.rs @@ -0,0 +1,55 @@ +// UART example application. Sends a test string over a UART and then enters +// echo mode +#![no_main] +#![no_std] +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; + +use cortex_m_rt::entry; +use embedded_hal_nb::serial::Read; +use embedded_io::Write; +use simple_examples::peb1; +use va416xx_hal::clock::ClockConfigurator; +use va416xx_hal::pins::PinsG; +use va416xx_hal::time::Hertz; +use va416xx_hal::{pac, uart}; + +#[entry] +fn main() -> ! { + defmt::println!("-- VA416xx UART example application--"); + + let dp = pac::Peripherals::take().unwrap(); + + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze() + .unwrap(); + + let gpiog = PinsG::new(dp.portg); + + let uart0 = uart::Uart::new( + dp.uart0, + gpiog.pg0, + gpiog.pg1, + &clocks, + Hertz::from_raw(115200).into(), + ) + .unwrap(); + let (mut tx, mut rx) = uart0.split(); + writeln!(tx, "Hello World\n\r").unwrap(); + loop { + // Echo what is received on the serial link. + match nb::block!(rx.read()) { + Ok(recvd) => { + // Infallible operation. + embedded_hal_nb::serial::Write::write(&mut tx, recvd).unwrap(); + } + Err(e) => { + defmt::info!("UART RX error {:?}", e); + } + } + } +} diff --git a/va416xx/examples/simple/examples/wdt.rs b/va416xx/examples/simple/examples/wdt.rs new file mode 100644 index 0000000..3fa3119 --- /dev/null +++ b/va416xx/examples/simple/examples/wdt.rs @@ -0,0 +1,80 @@ +// Code to test the watchdog timer. +#![no_main] +#![no_std] +// Import panic provider. +use panic_probe as _; +// Import logger. +use defmt_rtt as _; +use va416xx_hal::clock::ClockConfigurator; + +use core::sync::atomic::{AtomicU32, Ordering}; +use cortex_m_rt::entry; +use simple_examples::peb1; +use va416xx_hal::irq_router::enable_and_init_irq_router; +use va416xx_hal::pac::{self, interrupt}; +use va416xx_hal::wdt::Wdt; + +static WDT_INTRPT_COUNT: AtomicU32 = AtomicU32::new(0); + +#[derive(Debug, PartialEq, Eq)] +#[allow(dead_code)] +enum TestMode { + // Watchdog is fed by main loop, which runs with high period. + FedByMain, + // Watchdog is fed by watchdog IRQ. + FedByIrq, + AllowReset, +} +const TEST_MODE: TestMode = TestMode::FedByMain; +const WDT_ROLLOVER_MS: u32 = 100; + +#[entry] +fn main() -> ! { + defmt::println!("-- VA416xx WDT example application--"); + let cp = cortex_m::Peripherals::take().unwrap(); + let dp = pac::Peripherals::take().unwrap(); + + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(dp.clkgen) + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze() + .unwrap(); + enable_and_init_irq_router(); + let mut delay = cortex_m::delay::Delay::new(cp.SYST, clocks.apb0().raw()); + + let mut last_interrupt_counter = 0; + let mut wdt_ctrl = Wdt::start(dp.watch_dog, &clocks, WDT_ROLLOVER_MS); + wdt_ctrl.enable_reset(); + let log_divisor = 25; + let mut counter: u32 = 0; + loop { + counter = counter.wrapping_add(1); + if counter % log_divisor == 0 { + defmt::info!("wdt example main loop alive"); + } + if TEST_MODE != TestMode::AllowReset { + wdt_ctrl.feed(); + } + let interrupt_counter = WDT_INTRPT_COUNT.load(Ordering::Relaxed); + if interrupt_counter > last_interrupt_counter { + defmt::info!("interrupt counter has increased to {}", interrupt_counter); + last_interrupt_counter = interrupt_counter; + } + match TEST_MODE { + TestMode::FedByMain => delay.delay_ms(WDT_ROLLOVER_MS / 5), + TestMode::FedByIrq => delay.delay_ms(WDT_ROLLOVER_MS), + _ => (), + } + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn WATCHDOG() { + WDT_INTRPT_COUNT.fetch_add(1, Ordering::Relaxed); + let wdt = unsafe { pac::WatchDog::steal() }; + // Clear interrupt. + if TEST_MODE != TestMode::AllowReset { + wdt.wdogintclr().write(|w| unsafe { w.bits(1) }); + } +} diff --git a/va416xx/examples/simple/src/lib.rs b/va416xx/examples/simple/src/lib.rs new file mode 100644 index 0000000..c5a45f0 --- /dev/null +++ b/va416xx/examples/simple/src/lib.rs @@ -0,0 +1,11 @@ +#![no_std] + +/// PEB1 board specific configuration. +pub mod peb1 { + use va416xx_hal::time::Hertz; + + // The clock on the PEB1 board has a 20 MHz clock which is increased to 40 MHz with a configurable + // PLL by default. + pub const EXTCLK_FREQ: Hertz = Hertz::from_raw(40_000_000); + pub const XTAL_FREQ: Hertz = Hertz::from_raw(10_000_000); +} diff --git a/va416xx/examples/simple/src/main.rs b/va416xx/examples/simple/src/main.rs new file mode 100644 index 0000000..70a3422 --- /dev/null +++ b/va416xx/examples/simple/src/main.rs @@ -0,0 +1,13 @@ +//! Dummy app which does not do anything. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use panic_halt as _; + +#[entry] +fn main() -> ! { + loop { + cortex_m::asm::nop(); + } +} diff --git a/va416xx/flashloader/.gitignore b/va416xx/flashloader/.gitignore new file mode 100644 index 0000000..f9606a3 --- /dev/null +++ b/va416xx/flashloader/.gitignore @@ -0,0 +1 @@ +/venv diff --git a/va416xx/flashloader/Cargo.toml b/va416xx/flashloader/Cargo.toml new file mode 100644 index 0000000..f9f86ee --- /dev/null +++ b/va416xx/flashloader/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "flashloader" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m = "0.7" +embedded-io = "0.6" +defmt-rtt = "1" +defmt = "1" +panic-probe = { version = "1", features = ["defmt"] } +static_cell = "2" +satrs = { version = "0.3.0-alpha.1", default-features = false } +ringbuf = { version = "0.4", default-features = false } +once_cell = { version = "1", default-features = false, features = ["critical-section"] } +spacepackets = { version = "0.15", default-features = false, features = ["defmt"] } +cobs = { version = "0.4", default-features = false } + +va416xx-hal = { version = "0.6", features = ["va41630", "defmt"], path = "../va416xx-hal" } + +rtic = { version = "2", features = ["thumbv7-backend"] } +rtic-monotonics = { version = "2", features = ["cortex-m-systick"] } diff --git a/va416xx/flashloader/README.md b/va416xx/flashloader/README.md new file mode 100644 index 0000000..885ead1 --- /dev/null +++ b/va416xx/flashloader/README.md @@ -0,0 +1,66 @@ +VA416xx Flashloader Application +======== + +This flashloader shows a minimal example for a self-updatable Rust software which exposes +a simple PUS (CCSDS) interface to update the software. It also provides a Python application +called the `image-loader.py` which can be used to upload compiled images to the flashloader +application to write them to the NVM. + +Please note that the both the application and the image loader are tailored towards usage +with the [bootloader provided by this repository](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/bootloader). + +The software can quickly be adapted to interface with a real primary on-board software instead of +the Python script provided here to upload images because it uses a low-level CCSDS based packet +interface. + +## Using the Python image loader + +The Python image loader communicates with the Rust flashload application using a dedicated serial +port with a baudrate of 115200. + +It is recommended to run the script in a dedicated virtual environment. For example, on UNIX +systems you can use `python3 -m venv venv` and then `source venv/bin/activate` to create +and activate a virtual environment. + +After that, you can use + +```sh +pip install -r requirements.txt +``` + +to install all required dependencies. + +After that, it is recommended to use `./image-load.py -h` to get an overview of some options. +The flash loader uses the UART0 interface of the VA416xx board to perform CCSDS based +communication. The Python image loader application will search for a file named `loader.toml` and +use the `serial_port` key to determine the serial port to use for serial communication. + +### Examples + +You can use + +```sh +./image-loader.py -p +``` + +to send a ping an verify the connection. + +You can use + +```sh +cd flashloader/slot-a-blinky +cargo build --release +cd ../.. +./image-loader.py -t a ./slot-a-blinky/target/thumbv7em-none-eabihf/release/slot-a-blinky +``` + +to build the slot A sample application and upload it to a running flash loader application +to write it to slot A. + +You can use + +```sh +./image-loader.py -c -t a +``` + +to corrupt the image A and test that it switches to image B after a failed CRC check instead. diff --git a/va416xx/flashloader/image-loader.py b/va416xx/flashloader/image-loader.py new file mode 100755 index 0000000..336d342 --- /dev/null +++ b/va416xx/flashloader/image-loader.py @@ -0,0 +1,457 @@ +#!/usr/bin/env python3 +from typing import List, Tuple +from spacepackets.ecss.defs import PusService +from spacepackets.ecss.tm import PusTm +from com_interface import ComInterface +import toml +import struct +import logging +import argparse +import time +import enum +from com_interface.serial_base import SerialCfg +from com_interface.serial_cobs import SerialCobsComIF +from crcmod.predefined import PredefinedCrc +from spacepackets.ecss.tc import PusTc +from spacepackets.ecss.pus_verificator import PusVerificator, StatusField +from spacepackets.ecss.pus_1_verification import Service1Tm, UnpackParams +from spacepackets.seqcount import SeqCountProvider +from pathlib import Path +import dataclasses +from elftools.elf.elffile import ELFFile + + +BAUD_RATE = 115200 + +BOOTLOADER_START_ADDR = 0x0 +BOOTLOADER_END_ADDR = 0x4000 +BOOTLOADER_CRC_ADDR = BOOTLOADER_END_ADDR - 4 +BOOTLOADER_MAX_SIZE = BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 4 + +APP_A_START_ADDR = 0x4000 +APP_A_END_ADDR = 0x22000 +# The actual size of the image which is relevant for CRC calculation. +APP_A_SIZE_ADDR = APP_A_END_ADDR - 8 +APP_A_CRC_ADDR = APP_A_END_ADDR - 4 +APP_A_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8 + +APP_B_START_ADDR = 0x22000 +APP_B_END_ADDR = 0x40000 +# The actual size of the image which is relevant for CRC calculation. +APP_B_SIZE_ADDR = APP_B_END_ADDR - 8 +APP_B_CRC_ADDR = APP_B_END_ADDR - 4 +APP_B_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8 + +APP_IMG_SZ = (APP_B_END_ADDR - APP_A_START_ADDR) // 2 + +CHUNK_SIZE = 896 + +MEMORY_SERVICE = 6 +ACTION_SERVICE = 8 + +RAW_MEMORY_WRITE_SUBSERVICE = 2 +BOOT_NVM_MEMORY_ID = 1 +PING_PAYLOAD_SIZE = 0 + + +class ActionId(enum.IntEnum): + CORRUPT_APP_A = 128 + CORRUPT_APP_B = 129 + SET_BOOT_SLOT = 130 + + +_LOGGER = logging.getLogger(__name__) +SEQ_PROVIDER = SeqCountProvider(bit_width=14) + + +@dataclasses.dataclass +class LoadableSegment: + name: str + offset: int + size: int + data: bytes + + +class Target(enum.Enum): + BOOTLOADER = 0 + APP_A = 1 + APP_B = 2 + + +class AppSel(enum.IntEnum): + APP_A = 0 + APP_B = 1 + + +class ImageLoader: + def __init__(self, com_if: ComInterface, verificator: PusVerificator) -> None: + self.com_if = com_if + self.verificator = verificator + + def handle_boot_sel_cmd(self, target: AppSel): + _LOGGER.info("Sending ping command") + action_tc = PusTc( + apid=0x00, + service=PusService.S8_FUNC_CMD, + subservice=ActionId.SET_BOOT_SLOT, + seq_count=SEQ_PROVIDER.get_and_increment(), + app_data=bytes([target]), + ) + self.verificator.add_tc(action_tc) + self.com_if.send(bytes(action_tc.pack())) + self.await_for_command_completion("boot image selection command") + + def handle_ping_cmd(self): + _LOGGER.info("Sending ping command") + ping_tc = PusTc( + apid=0x00, + service=PusService.S17_TEST, + subservice=1, + seq_count=SEQ_PROVIDER.get_and_increment(), + app_data=bytes(PING_PAYLOAD_SIZE), + ) + self.verificator.add_tc(ping_tc) + self.com_if.send(bytes(ping_tc.pack())) + self.await_for_command_completion("ping command") + + def handle_corruption_cmd(self, target: Target): + if target == Target.BOOTLOADER: + _LOGGER.error("can not corrupt bootloader") + if target == Target.APP_A: + self.send_tc( + PusTc( + apid=0, + service=ACTION_SERVICE, + subservice=ActionId.CORRUPT_APP_A, + ), + ) + if target == Target.APP_B: + self.send_tc( + PusTc( + apid=0, + service=ACTION_SERVICE, + subservice=ActionId.CORRUPT_APP_B, + ), + ) + + def await_for_command_completion(self, context: str): + done = False + now = time.time() + while time.time() - now < 2.0: + if self.com_if.data_available() == 0: + time.sleep(0.2) + continue + for reply in self.com_if.receive(): + result = self.verificator.add_tm( + Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0)) + ) + if result is not None and result.completed: + _LOGGER.info(f"received {context} reply") + done = True + if done: + break + if not done: + _LOGGER.warning(f"no {context} reply received") + + def handle_flash_cmd(self, target: Target, file_path: Path) -> int: + loadable_segments = [] + _LOGGER.info("Parsing ELF file for loadable sections") + total_size = 0 + loadable_segments, total_size = create_loadable_segments(target, file_path) + segments_info_str(target, loadable_segments, total_size, file_path) + result = self._perform_flashing_algorithm(loadable_segments) + if result != 0: + return result + self._crc_and_app_size_postprocessing(target, total_size, loadable_segments) + return 0 + + def _perform_flashing_algorithm( + self, + loadable_segments: List[LoadableSegment], + ) -> int: + # Perform the flashing algorithm. + for segment in loadable_segments: + segment_end = segment.offset + segment.size + current_addr = segment.offset + pos_in_segment = 0 + while pos_in_segment < segment.size: + next_chunk_size = min(segment_end - current_addr, CHUNK_SIZE) + data = segment.data[pos_in_segment : pos_in_segment + next_chunk_size] + next_packet = pack_memory_write_command(current_addr, data) + _LOGGER.info( + f"Sending memory write command for address {current_addr:#08x} and data with " + f"length {len(data)}" + ) + self.verificator.add_tc(next_packet) + self.com_if.send(bytes(next_packet.pack())) + current_addr += next_chunk_size + pos_in_segment += next_chunk_size + start_time = time.time() + while True: + if time.time() - start_time > 1.0: + _LOGGER.error("Timeout while waiting for reply") + return -1 + data_available = self.com_if.data_available(0.1) + done = False + if not data_available: + continue + replies = self.com_if.receive() + for reply in replies: + tm = PusTm.unpack(reply, 0) + if tm.service != 1: + continue + service_1_tm = Service1Tm.from_tm(tm, UnpackParams(0)) + check_result = self.verificator.add_tm(service_1_tm) + # We could send after we have received the step reply, but that can + # somehow lead to overrun errors. I think it's okay to do it like + # this as long as the flash loader only uses polling.. + if ( + check_result is not None + and check_result.status.completed == StatusField.SUCCESS + ): + done = True + + # This is an optimized variant, but I think the small delay is not an issue. + """ + if ( + check_result is not None + and check_result.status.step == StatusField.SUCCESS + and len(check_result.status.step_list) == 1 + ): + done = True + """ + self.verificator.remove_completed_entries() + if done: + break + return 0 + + def _crc_and_app_size_postprocessing( + self, + target: Target, + total_size: int, + loadable_segments: List[LoadableSegment], + ): + if target == Target.BOOTLOADER: + _LOGGER.info("Blanking the bootloader checksum") + # Blank the checksum. For the bootloader, the bootloader will calculate the + # checksum itself on the initial run. + checksum_write_packet = pack_memory_write_command( + BOOTLOADER_CRC_ADDR, bytes([0x00, 0x00, 0x00, 0x00]) + ) + self.send_tc(checksum_write_packet) + else: + crc_addr = None + size_addr = None + if target == Target.APP_A: + crc_addr = APP_A_CRC_ADDR + size_addr = APP_A_SIZE_ADDR + elif target == Target.APP_B: + crc_addr = APP_B_CRC_ADDR + size_addr = APP_B_SIZE_ADDR + assert crc_addr is not None + assert size_addr is not None + _LOGGER.info(f"Writing app size {total_size} at address {size_addr:#08x}") + size_write_packet = pack_memory_write_command( + size_addr, struct.pack("!I", total_size) + ) + self.com_if.send(bytes(size_write_packet.pack())) + time.sleep(0.2) + crc_calc = PredefinedCrc("crc-32") + for segment in loadable_segments: + crc_calc.update(segment.data) + checksum = crc_calc.digest() + _LOGGER.info( + f"Writing checksum 0x[{checksum.hex(sep=',')}] at address {crc_addr:#08x}" + ) + self.send_tc(pack_memory_write_command(crc_addr, checksum)) + + def send_tc(self, tc: PusTc): + self.com_if.send(bytes(tc.pack())) + + +def main() -> int: + print("Python VA416XX Image Loader Application") + logging.basicConfig( + format="[%(asctime)s] [%(levelname)s] %(message)s", level=logging.DEBUG + ) + parser = argparse.ArgumentParser( + prog="image-loader", description="Python VA416XX Image Loader Application" + ) + parser.add_argument("-p", "--ping", action="store_true", help="Send ping command") + parser.add_argument("-c", "--corrupt", action="store_true", help="Corrupt a target") + parser.add_argument( + "-t", + "--target", + choices=["bl", "a", "b"], + help="Target (Bootloader or slot A or B)", + ) + parser.add_argument( + "path", nargs="?", default=None, help="Path to the App to flash" + ) + args = parser.parse_args() + serial_port = None + if Path("loader.toml").exists(): + with open("loader.toml", "r") as toml_file: + parsed_toml = toml.loads(toml_file.read()) + if "serial_port" in parsed_toml: + serial_port = parsed_toml["serial_port"] + if serial_port is None: + serial_port = input("Please specify the serial port manually: ") + serial_cfg = SerialCfg( + com_if_id="ser_cobs", + serial_port=serial_port, + baud_rate=BAUD_RATE, + polling_frequency=0.1, + ) + verificator = PusVerificator() + com_if = SerialCobsComIF(serial_cfg) + com_if.open() + target = None + if args.target == "bl": + target = Target.BOOTLOADER + elif args.target == "a": + target = Target.APP_A + elif args.target == "b": + target = Target.APP_B + image_loader = ImageLoader(com_if, verificator) + file_path = None + result = -1 + if args.ping: + image_loader.handle_ping_cmd() + com_if.close() + return 0 + if target: + if not args.corrupt: + if not args.path: + _LOGGER.error("App Path needs to be specified for the flash process") + file_path = Path(args.path) + if not file_path.exists(): + _LOGGER.error("File does not exist") + if args.corrupt: + if not target: + _LOGGER.error("target for corruption command required") + com_if.close() + return -1 + image_loader.handle_corruption_cmd(target) + else: + assert file_path is not None + assert target is not None + result = image_loader.handle_flash_cmd(target, file_path) + + com_if.close() + return result + + +def create_loadable_segments( + target: Target, file_path: Path +) -> Tuple[List[LoadableSegment], int]: + loadable_segments = [] + total_size = 0 + with open(file_path, "rb") as app_file: + elf_file = ELFFile(app_file) + + for idx, segment in enumerate(elf_file.iter_segments("PT_LOAD")): + if segment.header.p_filesz == 0: + continue + # Basic validity checks of the base addresses. + if idx == 0: + if ( + target == Target.BOOTLOADER + and segment.header.p_paddr != BOOTLOADER_START_ADDR + ): + raise ValueError( + f"detected possibly invalid start address {segment.header.p_paddr:#08x} for " + f"bootloader, expected {BOOTLOADER_START_ADDR}" + ) + if ( + target == Target.APP_A + and segment.header.p_paddr != APP_A_START_ADDR + ): + raise ValueError( + f"detected possibly invalid start address {segment.header.p_paddr:#08x} for " + f"App A, expected {APP_A_START_ADDR}" + ) + if ( + target == Target.APP_B + and segment.header.p_paddr != APP_B_START_ADDR + ): + raise ValueError( + f"detected possibly invalid start address {segment.header.p_paddr:#08x} for " + f"App B, expected {APP_B_START_ADDR}" + ) + name = None + for section in elf_file.iter_sections(): + if ( + section.header.sh_offset == segment.header.p_offset + and section.header.sh_size > 0 + ): + name = section.name + if name is None: + _LOGGER.warning("no fitting section found for segment") + continue + # print(f"Segment Addr: {segment.header.p_paddr}") + # print(f"Segment Offset: {segment.header.p_offset}") + # print(f"Segment Filesize: {segment.header.p_filesz}") + loadable_segments.append( + LoadableSegment( + name=name, + offset=segment.header.p_paddr, + size=segment.header.p_filesz, + data=segment.data(), + ) + ) + total_size += segment.header.p_filesz + return loadable_segments, total_size + + +def segments_info_str( + target: Target, + loadable_segments: List[LoadableSegment], + total_size: int, + file_path: Path, +): + # Set context string and perform basic sanity checks. + if target == Target.BOOTLOADER: + if total_size > BOOTLOADER_MAX_SIZE: + _LOGGER.error( + f"provided bootloader app larger than allowed {total_size} bytes" + ) + return -1 + context_str = "Bootloader" + elif target == Target.APP_A: + if total_size > APP_A_MAX_SIZE: + _LOGGER.error(f"provided App A larger than allowed {total_size} bytes") + return -1 + context_str = "App Slot A" + elif target == Target.APP_B: + if total_size > APP_B_MAX_SIZE: + _LOGGER.error(f"provided App B larger than allowed {total_size} bytes") + return -1 + context_str = "App Slot B" + _LOGGER.info(f"Flashing {context_str} with image {file_path} (size {total_size})") + for idx, segment in enumerate(loadable_segments): + _LOGGER.info( + f"Loadable section {idx} {segment.name} with offset {segment.offset:#08x} and " + f"size {segment.size}" + ) + + +def pack_memory_write_command(addr: int, data: bytes) -> PusTc: + app_data = bytearray() + app_data.append(BOOT_NVM_MEMORY_ID) + # N parameter is always 1 here. + app_data.append(1) + app_data.extend(struct.pack("!I", addr)) + app_data.extend(struct.pack("!I", len(data))) + app_data.extend(data) + return PusTc( + apid=0, + service=MEMORY_SERVICE, + subservice=RAW_MEMORY_WRITE_SUBSERVICE, + seq_count=SEQ_PROVIDER.get_and_increment(), + app_data=bytes(app_data), + ) + + +if __name__ == "__main__": + main() diff --git a/va416xx/flashloader/loader.toml b/va416xx/flashloader/loader.toml new file mode 100644 index 0000000..bfcf1ac --- /dev/null +++ b/va416xx/flashloader/loader.toml @@ -0,0 +1 @@ +serial_port = "/dev/ttyUSB0" diff --git a/va416xx/flashloader/requirements.txt b/va416xx/flashloader/requirements.txt new file mode 100644 index 0000000..723ead9 --- /dev/null +++ b/va416xx/flashloader/requirements.txt @@ -0,0 +1,5 @@ +spacepackets == 0.28 +com-interface == 0.1.0 +toml == 0.10 +pyelftools == 0.31 +crcmod == 1.7 diff --git a/va416xx/flashloader/slot-a-blinky/.gitignore b/va416xx/flashloader/slot-a-blinky/.gitignore new file mode 100644 index 0000000..7f153fc --- /dev/null +++ b/va416xx/flashloader/slot-a-blinky/.gitignore @@ -0,0 +1,2 @@ +/target +/app.map diff --git a/va416xx/flashloader/slot-a-blinky/Cargo.toml b/va416xx/flashloader/slot-a-blinky/Cargo.toml new file mode 100644 index 0000000..d78fb23 --- /dev/null +++ b/va416xx/flashloader/slot-a-blinky/Cargo.toml @@ -0,0 +1,42 @@ +[package] +name = "slot-a-blinky" +version = "0.1.0" +edition = "2021" + +[workspace] + +[dependencies] +cortex-m-rt = "0.7" +panic-rtt-target = { version = "0.2" } +rtt-target = { version = "0.6" } +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +embedded-hal = "1" +va416xx-hal = { path = "0.4", features = ["va41630"] } + +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +# This is problematic for stepping.. +# opt-level = 'z' # <- +overflow-checks = true # <- + +# cargo build/run --release +[profile.release] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = 3 # <- +overflow-checks = false # <- + +[profile.small] +inherits = "release" +codegen-units = 1 +debug-assertions = false # <- +lto = true +opt-level = 'z' # <- +overflow-checks = false # <- +# strip = true # Automatically strip symbols from the binary. diff --git a/va416xx/flashloader/slot-a-blinky/memory.x b/va416xx/flashloader/slot-a-blinky/memory.x new file mode 100644 index 0000000..9d8c317 --- /dev/null +++ b/va416xx/flashloader/slot-a-blinky/memory.x @@ -0,0 +1,24 @@ +/* Special linker script for application slot A with an offset at address 0x4000 */ +MEMORY +{ + FLASH : ORIGIN = 0x00004000, LENGTH = 256K + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +SECTIONS { + .sram1 (NOLOAD) : ALIGN(8) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM_1 +}; diff --git a/va416xx/flashloader/slot-a-blinky/src/main.rs b/va416xx/flashloader/slot-a-blinky/src/main.rs new file mode 100644 index 0000000..517b20c --- /dev/null +++ b/va416xx/flashloader/slot-a-blinky/src/main.rs @@ -0,0 +1,23 @@ +//! Simple blinky example using the HAL +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::digital::StatefulOutputPin; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va416xx_hal::{gpio::PinsG, pac}; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("VA416xx HAL blinky example for App Slot A"); + + let mut dp = pac::Peripherals::take().unwrap(); + let portg = PinsG::new(&mut dp.sysconfig, dp.portg); + let mut led = portg.pg5.into_readable_push_pull_output(); + loop { + cortex_m::asm::delay(1_000_000); + led.toggle().ok(); + } +} diff --git a/va416xx/flashloader/slot-b-blinky/.gitignore b/va416xx/flashloader/slot-b-blinky/.gitignore new file mode 100644 index 0000000..7f153fc --- /dev/null +++ b/va416xx/flashloader/slot-b-blinky/.gitignore @@ -0,0 +1,2 @@ +/target +/app.map diff --git a/va416xx/flashloader/slot-b-blinky/Cargo.toml b/va416xx/flashloader/slot-b-blinky/Cargo.toml new file mode 100644 index 0000000..2240360 --- /dev/null +++ b/va416xx/flashloader/slot-b-blinky/Cargo.toml @@ -0,0 +1,42 @@ +[package] +name = "slot-b-blinky" +version = "0.1.0" +edition = "2021" + +[workspace] + +[dependencies] +cortex-m-rt = "0.7" +panic-rtt-target = { version = "0.2" } +rtt-target = { version = "0.6" } +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +embedded-hal = "1" +va416xx-hal = { path = "0.4", features = ["va41630"] } + +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +# This is problematic for stepping.. +# opt-level = 'z' # <- +overflow-checks = true # <- + +# cargo build/run --release +[profile.release] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = 3 # <- +overflow-checks = false # <- + +[profile.small] +inherits = "release" +codegen-units = 1 +debug-assertions = false # <- +lto = true +opt-level = 'z' # <- +overflow-checks = false # <- +# strip = true # Automatically strip symbols from the binary. diff --git a/va416xx/flashloader/slot-b-blinky/memory.x b/va416xx/flashloader/slot-b-blinky/memory.x new file mode 100644 index 0000000..4a9dcb0 --- /dev/null +++ b/va416xx/flashloader/slot-b-blinky/memory.x @@ -0,0 +1,24 @@ +/* Special linker script for application slot B with an offset at address 0x22000 */ +MEMORY +{ + FLASH : ORIGIN = 0x00022000, LENGTH = 256K + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +SECTIONS { + .sram1 (NOLOAD) : ALIGN(8) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM_1 +}; diff --git a/va416xx/flashloader/slot-b-blinky/src/main.rs b/va416xx/flashloader/slot-b-blinky/src/main.rs new file mode 100644 index 0000000..5663410 --- /dev/null +++ b/va416xx/flashloader/slot-b-blinky/src/main.rs @@ -0,0 +1,23 @@ +//! Simple blinky example using the HAL +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::digital::StatefulOutputPin; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va416xx_hal::{gpio::PinsG, pac}; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("VA416xx HAL blinky example for App Slot B"); + + let mut dp = pac::Peripherals::take().unwrap(); + let portg = PinsG::new(&mut dp.sysconfig, dp.portg); + let mut led = portg.pg5.into_readable_push_pull_output(); + loop { + cortex_m::asm::delay(8_000_000); + led.toggle().ok(); + } +} diff --git a/va416xx/flashloader/src/main.rs b/va416xx/flashloader/src/main.rs new file mode 100644 index 0000000..7a2a91c --- /dev/null +++ b/va416xx/flashloader/src/main.rs @@ -0,0 +1,537 @@ +//! Vorago flashloader which can be used to flash image A and image B via a simple +//! low-level CCSDS memory interface via a UART wire. +//! +//! This flash loader can be used after the bootloader was flashed to flash the images. +//! You can also use this as an starting application for a software update mechanism. +//! +//! Bootloader memory map +//! +//! * <0x0> Bootloader start +//! * <0x3FFE> Bootloader CRC +//! * <0x4000> App image A start +//! * <0x21FFC> App image A CRC check length +//! * <0x21FFE> App image A CRC check value +//! * <0x22000> App image B start +//! * <0x3FFFC> App image B CRC check length +//! * <0x3FFFE> App image B CRC check value +//! * <0x40000> +#![no_main] +#![no_std] + +use once_cell::sync::OnceCell; +use va416xx_hal::{clock::Clocks, edac, pac, time::Hertz, wdt::Wdt}; + +const EXTCLK_FREQ: u32 = 40_000_000; + +const MAX_TC_SIZE: usize = 1024; +const MAX_TC_FRAME_SIZE: usize = cobs::max_encoding_length(MAX_TC_SIZE); + +const MAX_TM_SIZE: usize = 128; +const MAX_TM_FRAME_SIZE: usize = cobs::max_encoding_length(MAX_TM_SIZE); + +const UART_BAUDRATE: u32 = 115200; +const BOOT_NVM_MEMORY_ID: u8 = 1; +const RX_DEBUGGING: bool = false; +const TX_DEBUGGING: bool = false; + +pub enum ActionId { + CorruptImageA = 128, + CorruptImageB = 129, +} +pub trait WdtInterface { + fn feed(&self); +} + +pub struct OptWdt(Option); + +impl WdtInterface for OptWdt { + fn feed(&self) { + if self.0.is_some() { + self.0.as_ref().unwrap().feed(); + } + } +} + +use ringbuf::{ + traits::{Consumer, Observer, Producer, SplitRef}, + CachingCons, StaticProd, StaticRb, +}; +use static_cell::StaticCell; + +// Larger buffer for TC to be able to hold the possibly large memory write packets. +const BUF_RB_SIZE_TC: usize = 2048; +const SIZES_RB_SIZE_TC: usize = 16; + +const BUF_RB_SIZE_TM: usize = 512; +const SIZES_RB_SIZE_TM: usize = 16; + +// Ring buffers to handling variable sized telemetry +static BUF_RB_TM: StaticCell> = StaticCell::new(); +static SIZES_RB_TM: StaticCell> = StaticCell::new(); + +// Ring buffers to handling variable sized telecommands +static BUF_RB_TC: StaticCell> = StaticCell::new(); +static SIZES_RB_TC: StaticCell> = StaticCell::new(); + +pub struct DataProducer { + pub buf_prod: StaticProd<'static, u8, BUF_SIZE>, + pub sizes_prod: StaticProd<'static, usize, SIZES_LEN>, +} + +pub struct DataConsumer { + pub buf_cons: CachingCons<&'static StaticRb>, + pub sizes_cons: CachingCons<&'static StaticRb>, +} + +static CLOCKS: OnceCell = OnceCell::new(); + +pub const APP_A_START_ADDR: u32 = 0x4000; +pub const APP_A_END_ADDR: u32 = 0x22000; +pub const APP_B_START_ADDR: u32 = 0x22000; +pub const APP_B_END_ADDR: u32 = 0x40000; + +#[rtic::app(device = pac, dispatchers = [U1, U2, U3])] +mod app { + use super::*; + use cortex_m::asm; + use embedded_io::Write; + // Import panic provider. + use panic_probe as _; + // Import logger. + use defmt_rtt as _; + use rtic::Mutex; + use rtic_monotonics::systick::prelude::*; + use satrs::pus::verification::VerificationReportCreator; + use spacepackets::ecss::PusServiceId; + use spacepackets::ecss::{ + tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket, + }; + use va416xx_hal::clock::ClockConfigurator; + use va416xx_hal::irq_router::enable_and_init_irq_router; + use va416xx_hal::uart::InterruptContextTimeoutOrMaxSize; + use va416xx_hal::{ + edac, + nvm::Nvm, + pac, + pins::PinsG, + uart::{self, Uart}, + }; + + use crate::{setup_edac, EXTCLK_FREQ}; + + #[derive(Default, Debug, Copy, Clone, PartialEq, Eq)] + pub enum CobsReaderStates { + #[default] + WaitingForStart, + WatingForEnd, + FrameOverflow, + } + + #[local] + struct Local { + uart_rx: uart::RxWithInterrupt, + uart_tx: uart::Tx, + rx_context: InterruptContextTimeoutOrMaxSize, + rom_spi: Option, + // We handle all TM in one task. + tm_cons: DataConsumer, + // We consume all TC in one task. + tc_cons: DataConsumer, + // We produce all TC in one task. + tc_prod: DataProducer, + verif_reporter: VerificationReportCreator, + } + + #[shared] + struct Shared { + // Having this shared allows multiple tasks to generate telemetry. + tm_prod: DataProducer, + } + + rtic_monotonics::systick_monotonic!(Mono, 10_000); + + #[init] + fn init(mut cx: init::Context) -> (Shared, Local) { + defmt::println!("-- Vorago flashloader --"); + // Initialize the systick interrupt & obtain the token to prove that we did + // Use the external clock connected to XTAL_N. + let clocks = ClockConfigurator::new(cx.device.clkgen) + .xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ)) + .freeze() + .unwrap(); + + enable_and_init_irq_router(); + setup_edac(&mut cx.device.sysconfig); + + let gpiog = PinsG::new(cx.device.portg); + + let uart0 = Uart::new( + cx.device.uart0, + gpiog.pg0, + gpiog.pg1, + &clocks, + Hertz::from_raw(UART_BAUDRATE).into(), + ) + .unwrap(); + let (tx, rx) = uart0.split(); + + let verif_reporter = VerificationReportCreator::new(0).unwrap(); + + let (buf_prod_tm, buf_cons_tm) = BUF_RB_TM + .init(StaticRb::::default()) + .split_ref(); + let (sizes_prod_tm, sizes_cons_tm) = SIZES_RB_TM + .init(StaticRb::::default()) + .split_ref(); + + let (buf_prod_tc, buf_cons_tc) = BUF_RB_TC + .init(StaticRb::::default()) + .split_ref(); + let (sizes_prod_tc, sizes_cons_tc) = SIZES_RB_TC + .init(StaticRb::::default()) + .split_ref(); + + Mono::start(cx.core.SYST, clocks.sysclk().raw()); + CLOCKS.set(clocks).unwrap(); + + let mut rx = rx.into_rx_with_irq(); + let mut rx_context = InterruptContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE); + rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context) + .expect("initiating UART RX failed"); + pus_tc_handler::spawn().unwrap(); + pus_tm_tx_handler::spawn().unwrap(); + ( + Shared { + tm_prod: DataProducer { + buf_prod: buf_prod_tm, + sizes_prod: sizes_prod_tm, + }, + }, + Local { + uart_rx: rx, + uart_tx: tx, + rx_context, + rom_spi: Some(cx.device.spi3), + tm_cons: DataConsumer { + buf_cons: buf_cons_tm, + sizes_cons: sizes_cons_tm, + }, + tc_cons: DataConsumer { + buf_cons: buf_cons_tc, + sizes_cons: sizes_cons_tc, + }, + tc_prod: DataProducer { + buf_prod: buf_prod_tc, + sizes_prod: sizes_prod_tc, + }, + verif_reporter, + }, + ) + } + + // `shared` cannot be accessed from this context + #[idle] + fn idle(_cx: idle::Context) -> ! { + loop { + asm::nop(); + } + } + + // This is the interrupt handler to read all bytes received on the UART0. + #[task( + binds = UART0_RX, + local = [ + cnt: u32 = 0, + rx_buf: [u8; MAX_TC_FRAME_SIZE] = [0; MAX_TC_FRAME_SIZE], + rx_context, + uart_rx, + tc_prod + ], + )] + fn uart_rx_irq(cx: uart_rx_irq::Context) { + match cx + .local + .uart_rx + .on_interrupt_max_size_or_timeout_based(cx.local.rx_context, cx.local.rx_buf) + { + Ok(result) => { + if RX_DEBUGGING { + defmt::info!("RX Info: {:?}", cx.local.rx_context); + defmt::info!("RX Result: {:?}", result); + } + if result.complete() { + // Check frame validity (must have COBS format) and decode the frame. + // Currently, we expect a full frame or a frame received through a timeout + // to be one COBS frame. We could parse for multiple COBS packets in one + // frame, but the additional complexity is not necessary here.. + if cx.local.rx_buf[0] == 0 && cx.local.rx_buf[result.bytes_read - 1] == 0 { + let decoded_size = + cobs::decode_in_place(&mut cx.local.rx_buf[1..result.bytes_read]); + if decoded_size.is_err() { + defmt::warn!("COBS decoding failed"); + } else { + let decoded_size = decoded_size.unwrap(); + if cx.local.tc_prod.sizes_prod.vacant_len() >= 1 + && cx.local.tc_prod.buf_prod.vacant_len() >= decoded_size + { + // Should never fail, we checked there is enough space. + cx.local.tc_prod.sizes_prod.try_push(decoded_size).unwrap(); + cx.local + .tc_prod + .buf_prod + .push_slice(&cx.local.rx_buf[1..1 + decoded_size]); + } else { + defmt::warn!("COBS TC queue full"); + } + } + } else { + defmt::warn!( + "COBS frame with invalid format, start and end bytes are not 0" + ); + } + + // Initiate next transfer. + cx.local + .uart_rx + .read_fixed_len_or_timeout_based_using_irq(cx.local.rx_context) + .expect("read operation failed"); + } + if result.has_errors() { + defmt::warn!("UART error: {:?}", result.errors.unwrap()); + } + } + Err(e) => { + defmt::warn!("UART error: {:?}", e); + } + } + } + + #[task( + priority = 2, + local=[ + tc_buf: [u8; MAX_TC_SIZE] = [0; MAX_TC_SIZE], + src_data_buf: [u8; 16] = [0; 16], + verif_buf: [u8; 32] = [0; 32], + tc_cons, + rom_spi, + verif_reporter + ], + shared=[tm_prod] + )] + async fn pus_tc_handler(mut cx: pus_tc_handler::Context) { + loop { + // Try to read a TC from the ring buffer. + let packet_len = cx.local.tc_cons.sizes_cons.try_pop(); + if packet_len.is_none() { + // Small delay, TCs might arrive very quickly. + Mono::delay(20.millis()).await; + continue; + } + let packet_len = packet_len.unwrap(); + defmt::info!("received packet with length {}", packet_len); + assert_eq!( + cx.local + .tc_cons + .buf_cons + .pop_slice(&mut cx.local.tc_buf[0..packet_len]), + packet_len + ); + // Read a telecommand, now handle it. + handle_valid_pus_tc(&mut cx); + } + } + + fn handle_valid_pus_tc(cx: &mut pus_tc_handler::Context) { + let pus_tc = PusTcReader::new(cx.local.tc_buf); + if pus_tc.is_err() { + defmt::warn!("PUS TC error: {}", pus_tc.unwrap_err()); + return; + } + let pus_tc = pus_tc.unwrap(); + let mut write_and_send = |tm: &PusTmCreator| { + let written_size = tm.write_to_bytes(cx.local.verif_buf).unwrap(); + cx.shared.tm_prod.lock(|prod| { + prod.sizes_prod.try_push(tm.len_written()).unwrap(); + prod.buf_prod + .push_slice(&cx.local.verif_buf[0..written_size]); + }); + }; + let request_id = VerificationReportCreator::read_request_id_from_tc(&pus_tc); + let tm = cx + .local + .verif_reporter + .acceptance_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("acceptance success failed"); + write_and_send(&tm); + + let tm = cx + .local + .verif_reporter + .start_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("acceptance success failed"); + write_and_send(&tm); + + if pus_tc.service() == PusServiceId::Action as u8 { + let mut corrupt_image = |base_addr: u32| { + // Safety: We only use this for NVM handling and we only do NVM + // handling here. + let nvm = Nvm::new( + cx.local.rom_spi.take().unwrap(), + CLOCKS.get().as_ref().unwrap(), + ); + let mut buf = [0u8; 4]; + nvm.read_data(base_addr + 32, &mut buf); + buf[0] += 1; + nvm.write_data(base_addr + 32, &buf); + *cx.local.rom_spi = Some(nvm.release()); + let tm = cx + .local + .verif_reporter + .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("completion success failed"); + write_and_send(&tm); + }; + if pus_tc.subservice() == ActionId::CorruptImageA as u8 { + defmt::info!("corrupting App Image A"); + corrupt_image(APP_A_START_ADDR); + } + if pus_tc.subservice() == ActionId::CorruptImageB as u8 { + defmt::info!("corrupting App Image B"); + corrupt_image(APP_B_START_ADDR); + } + } + if pus_tc.service() == PusServiceId::Test as u8 && pus_tc.subservice() == 1 { + defmt::info!("received ping TC"); + let tm = cx + .local + .verif_reporter + .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("completion success failed"); + write_and_send(&tm); + } else if pus_tc.service() == PusServiceId::MemoryManagement as u8 { + let tm = cx + .local + .verif_reporter + .step_success( + cx.local.src_data_buf, + &request_id, + 0, + 0, + &[], + EcssEnumU8::new(0), + ) + .expect("step success failed"); + write_and_send(&tm); + // Raw memory write TC + if pus_tc.subservice() == 2 { + let app_data = pus_tc.app_data(); + if app_data.len() < 10 { + defmt::warn!( + "app data for raw memory write is too short: {}", + app_data.len() + ); + } + let memory_id = app_data[0]; + if memory_id != BOOT_NVM_MEMORY_ID { + defmt::warn!("memory ID {} not supported", memory_id); + // TODO: Error reporting + return; + } + let offset = u32::from_be_bytes(app_data[2..6].try_into().unwrap()); + let data_len = u32::from_be_bytes(app_data[6..10].try_into().unwrap()); + if 10 + data_len as usize > app_data.len() { + defmt::warn!( + "invalid data length {} for raw mem write detected", + data_len + ); + // TODO: Error reporting + return; + } + let data = &app_data[10..10 + data_len as usize]; + defmt::info!("writing {} bytes at offset {} to NVM", data_len, offset); + // Safety: We only use this for NVM handling and we only do NVM + // handling here. + let nvm = Nvm::new( + cx.local.rom_spi.take().unwrap(), + CLOCKS.get().as_ref().unwrap(), + ); + nvm.write_data(offset, data); + *cx.local.rom_spi = Some(nvm.release()); + let tm = cx + .local + .verif_reporter + .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[]) + .expect("completion success failed"); + write_and_send(&tm); + defmt::info!("NVM operation done"); + } + } + } + + #[task( + priority = 1, + local=[ + read_buf: [u8;MAX_TM_SIZE] = [0; MAX_TM_SIZE], + encoded_buf: [u8;MAX_TM_FRAME_SIZE] = [0; MAX_TM_FRAME_SIZE], + uart_tx, + tm_cons + ], + shared=[] + )] + async fn pus_tm_tx_handler(cx: pus_tm_tx_handler::Context) { + loop { + while cx.local.tm_cons.sizes_cons.occupied_len() > 0 { + let next_size = cx.local.tm_cons.sizes_cons.try_pop().unwrap(); + cx.local + .tm_cons + .buf_cons + .pop_slice(&mut cx.local.read_buf[0..next_size]); + cx.local.encoded_buf[0] = 0; + let send_size = cobs::encode( + &cx.local.read_buf[0..next_size], + &mut cx.local.encoded_buf[1..], + ); + cx.local.encoded_buf[send_size + 1] = 0; + if TX_DEBUGGING { + defmt::debug!("UART TX: Sending data with size {}", send_size + 2); + } + cx.local + .uart_tx + .write_all(&cx.local.encoded_buf[0..send_size + 2]) + .unwrap(); + Mono::delay(2.millis()).await; + } + Mono::delay(50.millis()).await; + } + } + + #[task(binds = EDAC_SBE, priority = 1)] + fn edac_sbe_isr(_cx: edac_sbe_isr::Context) { + // TODO: Send some command via UART for notification purposes. Also identify the problematic + // memory. + edac::clear_sbe_irq(); + } + + #[task(binds = EDAC_MBE, priority = 1)] + fn edac_mbe_isr(_cx: edac_mbe_isr::Context) { + // TODO: Send some command via UART for notification purposes. + edac::clear_mbe_irq(); + // TODO: Reset like the vorago example? + } + + #[task(binds = WATCHDOG, priority = 1)] + fn watchdog_isr(_cx: watchdog_isr::Context) { + let wdt = unsafe { pac::WatchDog::steal() }; + // Clear interrupt. + wdt.wdogintclr().write(|w| unsafe { w.bits(1) }); + } +} + +fn setup_edac(syscfg: &mut pac::Sysconfig) { + // The scrub values are based on the Vorago provided bootloader. + edac::enable_rom_scrub(syscfg, 125); + edac::enable_ram0_scrub(syscfg, 1000); + edac::enable_ram1_scrub(syscfg, 1000); + edac::enable_sbe_irq(); + edac::enable_mbe_irq(); +} diff --git a/va416xx/jlink-gdb-ram.sh b/va416xx/jlink-gdb-ram.sh new file mode 100755 index 0000000..f0ac97f --- /dev/null +++ b/va416xx/jlink-gdb-ram.sh @@ -0,0 +1,5 @@ +#!/bin/bash +# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary +# to disable ROM protection to allow flashing +JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript diff --git a/va416xx/jlink-gdb.sh b/va416xx/jlink-gdb.sh new file mode 100755 index 0000000..c5385d1 --- /dev/null +++ b/va416xx/jlink-gdb.sh @@ -0,0 +1,5 @@ +#!/bin/bash +# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary +# to disable ROM protection to allow flashing +JLinkGDBServer -select USB -device VA416xx -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd diff --git a/va416xx/jlink/JLinkSettings.JLinkScript b/va416xx/jlink/JLinkSettings.JLinkScript new file mode 100644 index 0000000..b6b83a6 --- /dev/null +++ b/va416xx/jlink/JLinkSettings.JLinkScript @@ -0,0 +1,62 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 1995 - 2018 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +---------------------------------------------------------------------- +File : JLinkSettings.JLinkScript +Purpose : J-Link target setup file for VORAGO VA416xx +---------------------------END-OF-HEADER------------------------------ +*/ + +/********************************************************************* +* +* AfterResetTarget +*/ +int AfterResetTarget (void) { + JLINK_SYS_Report("AfterResetTarget()"); + JLINK_MEM_WriteU32(0x400210C0, 0x1ACCE551); // WDOGLOCK = 0x1ACCE551 + JLINK_MEM_WriteU32(0x40021008, 0x0); // WDOGCONTROL = 0x0 (diable) + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* BeforeTargetDownload +*/ +int BeforeTargetDownload (void) { + JLINK_SYS_Report("BeforeTargetDownload()"); + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterTargetDownload +*/ +int AfterTargetDownload (void) { + JLINK_SYS_Report("AfterTargetDownload()"); + return JLINK_MEM_WriteU32(0x40010010, 0x0); // ROM_PROT = 0x0 +} + +/********************************************************************* +* +* HandleBeforeFlashProg +*/ +int HandleBeforeFlashProg(void) { + JLINK_SYS_Report("HandleBeforeFlashProg()"); + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* HandleAfterFlashProg +*/ +int HandleAfterFlashProg(void) { + JLINK_SYS_Report("HandleAfterFlashProg()"); + return JLINK_MEM_WriteU32(0x40010010, 0x0); // ROM_PROT = 0x0 +} diff --git a/va416xx/jlink/jlink-reva.gdb b/va416xx/jlink/jlink-reva.gdb new file mode 100644 index 0000000..8712a8e --- /dev/null +++ b/va416xx/jlink/jlink-reva.gdb @@ -0,0 +1,13 @@ +target remote localhost:2331 + +# For some reason, this is problematic even if the JLinkScript disabled the remote +# write protection. Therefore, don't do it for now +# This is only problematic on board RevA +# monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va416xx/jlink/jlink.gdb b/va416xx/jlink/jlink.gdb new file mode 100644 index 0000000..b7220cf --- /dev/null +++ b/va416xx/jlink/jlink.gdb @@ -0,0 +1,8 @@ +target remote localhost:2331 + +monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load diff --git a/va416xx/memory.x b/va416xx/memory.x new file mode 100644 index 0000000..a00615d --- /dev/null +++ b/va416xx/memory.x @@ -0,0 +1,22 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 256K + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +SECTIONS { + .sram1 (NOLOAD) : ALIGN(8) { + *(.sram1 .sram1.*); + } > SRAM_1 +}; diff --git a/va416xx/scripts/VA416xx_Series.yaml b/va416xx/scripts/VA416xx_Series.yaml new file mode 100644 index 0000000..38b4705 --- /dev/null +++ b/va416xx/scripts/VA416xx_Series.yaml @@ -0,0 +1,101 @@ +name: VA416xx Series +generated_from_pack: true +pack_file_release: 1.0.5 +variants: +- name: VA416xx + cores: + - name: main + type: armv7em + core_access_options: !Arm + ap: 0 + psel: 0x0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x1fff8000 + end: 0x20000000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x40000 + access: + boot: true + cores: + - main + - !Generic + name: IRAM2 + range: + start: 0x20000000 + end: 0x20008000 + cores: + - main + flash_algorithms: + - va416_spi_fram_256kb + - va416_ebiboot_fram_256kb + - va416_ebi_fram_512kb +flash_algorithms: +- name: va416_spi_fram_256kb + default: true + description: VA416_SPI_FRAM_256KB + instructions: RfYMQMTyAQABaMkHCtEBaMkHBL8BaF/qwXED0QFoyQfy0AC/AWjJBgnVAWjJBkS/AWhf6sFhAtUBaMkG8tQDIQFicEdwRwC/WCAIIcTyAQDA8qgBQWBB8ggBTvJRUsTyAgHB9swiwfi4IAAiCmABaCHwCAEBYAC/AL8CaEX2DEFC8AgCxPIBAQJgAiAAv0hgQPIHQEH4DAxA8oIgQfgIDAMgCGIIaMAHCtEIaMAHBL8IaF/qwHAD0QhowAfy0AC/CGjABgnVCGjABkS/CGhf6sBgAtUIaMAG8tQGIMjyAAADIgpiQfgEDApo0gcK0Qpo0gcEvwpoX+rCcgPRCmjSB/LQAL8KaNIGCdUKaNIGRL8KaF/qwmIC1Qpo0gby1AMiCmJB+AQMCGjABwnRCGjABwS/CGhf6sBwAtEIaMAH8tAIaMAGCdUIaMAGRL8IaF/qwGAC1QhowAby1AMgCGIBIEH4BAxP8ABAQfgEDAhowAcK0QhowAcEvwhoX+rAcAPRCGjAB/LQAL8IaMAGCdUIaMAGRL8IaF/qwGAC1QhowAby1AMiACAKYnBHAL9F9gxBxPIBAQhowAcK0QhowAcEvwhoX+rAcAPRCGjAB/LQAL8IaMAGCdUIaMAGRL8IaF/qwGAC1QhowAby1AYgyPIAAAMiCmJB+AQMCmjSBwrRCmjSBwS/Cmhf6sJyA9EKaNIH8tAAvwpo0gYJ1Qpo0gZEvwpoX+rCYgLVCmjSBvLUAyIKYgEi9zBB+AQsQfgEDAhowAcJ0QhowAcEvwhoX+rAcALRCGjAB/LQCGjABgnVCGjABkS/CGhf6sBgAtUIaMAG8tQDIgAgCmJwRwC/cLVF9gxBQPIGDAAgxPIBAcjyAAwDI0/wAg5P8ABCACQG4AC/ATS09YBvC2IA8KyAQfgEzA1o7QcK0Q1o7QcEvw1oX+rFdQPRDWjtB/LQAL8NaO0GCtUNaO0GRL8NaF/qxWUD1Q1o7Qby1AC/xPMHJQtiQfgE7EH4BFzlskH4BFwAJUH4BFwE4AU1/y1B+AQMTNAOaLYHBtQOaLYHXL8OaF/qhnY+1UH4BAwOaLYHCdQOaLYHXL8OaF/qhnYC1A5otgfy1UH4BAwOaLYHCtQOaLYHXL8OaF/qhnYD1A5otgfy1QC/QfgEDA5otgcK1A5otgdcvw5oX+qGdgPUDmi2B/LVAL9B+AQMDmi2B7zUDmi2B1y/Dmhf6oZ2tdQOaLYH8tWx5w5otgez1bznDWitBwrUDWitB1y/DWhf6oV1A9QNaK0H8tUAv0H4BCwNaO0HCtENaO0HBL8NaF/qxXUD0Q1o7Qfy0AC/DWjtBn/1Wq8NaO0GRL8NaF/qxWV/9VKvDWjtBvDUTecAIHC9ACBwR4C1grBF9gxOxPIBDgAjAZPe+AAw2wcN0d74ADDbBwS/3vgAMF/qw3ME0d74ADDbB+7QAL/e+AAw2wYM1d74ADDbBkS/3vgAMF/qw2MD1d74ADDbBu7UAyPO+CAwBiPI8gADTvgEPN74ADDbBwzR3vgAMNsHBL/e+AAwX+rDcwPR3vgAMNsH7tDe+AAw2wYM1d74ADDbBkS/3vgAMF/qw2MD1d74ADDbBu7UAyPO+CAwAiNN9vAMTvgEPMDzB0PP9v98TvgEPMDzByPAsgEpTvgEPE74BAxA8JKA3vgAAIAHAPEGgd74AACAB1y/3vgAAF/qgHAA8fyA3vgAAIAHXL/e+AAAX+qAcADx8oDe+AAAgAdcv974AABf6oBwAPHogN74AACAB1y/3vgAAF/qgHAA8d6A3vgAAIAHXL/e+AAAX+qAcADx1IDe+AAAgAdcv974AABf6oBwAPHKgN74AACAB1y/3vgAAF/qgHAA8cCA3vgAAIAHXL/e+AAAX+qAcADxtoDe+AAAgAdcv974AABf6oBwAPGsgN74AACAB1y/3vgAAF/qgHAA8aKA3vgAAIAHXL/e+AAAX+qAcADxmIDe+AAAgAdcv974AABf6oBwAPGOgBzxGQx/9H+vheAAvxL4AQsBOU74BAxe+AQMASkAkAGYAPEBAAGQP/Rur2BG3vgAMJsH69Te+AAwmwdcv974ADBf6oNz4tTe+AAwmwdcv974ADBf6oNz2dTe+AAwmwdcv974ADBf6oNz0NTe+AAwmwdcv974ADBf6oNzx9Te+AAwmwdcv974ADBf6oNzvtTe+AAwmwdcv974ADBf6oNztdTe+AAwmwdcv974ADBf6oNzrNTe+AAwmwdcv974ADBf6oNzo9Te+AAwmwdcv974ADBf6oNzmtTe+AAwmwdcv974ADBf6oNzkdTe+AAwmwdcv974ADBf6oNzP/WIr974ADCbB1y/3vgAMF/qg3M/9X6vGTB/9IuvASACsIC9EHgA8QBATvgEDN74AADABwzR3vgAAMAHBL/e+AAAX+rAcAPR3vgAAMAH7tDe+AAAwAYM1d74AADABkS/3vgAAF/qwGAD1d74AADABu7UAyDO+CAAACACsIC9AL8AIHBHsLVF9gxExPIBBCNo2wcJ0SNo2wcEvyNoX+rDcwLRI2jbB/LQI2jbBgnVI2jbBkS/I2hf6sNjAtUjaNsG8tQDIyNiRPgEPMDzB0NE+AQ8wPMHI0T4BDzDskT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwBs0/wAAxP8AAOAL9E+ATMI2hbBwrUI2hbB1y/I2hf6kNzA9QjaFsH8tUAv1T4BDwVeNuynUIo0Q7xAQ6ORQLxAQLj0U/wAEJE+AQsImjSBwrRImjSBwS/Imhf6sJyA9EiaNIH8tAAvyJo0gYJ1SJo0gZEvyJoX+rCYgLVImjSBvLUAyIIRCJisL1wRLC9AAAAAAAA + pc_init: 0x49 + pc_uninit: 0x1ad + pc_program_page: 0x40d + pc_erase_sector: 0x409 + pc_erase_all: 0x27d + data_section_offset: 0x8d8 + flash_properties: + address_range: + start: 0x0 + end: 0x40000 + page_size: 0x100 + erased_byte_value: 0x0 + program_page_timeout: 3000 + erase_sector_timeout: 3000 + sectors: + - size: 0x2000 + address: 0x0 +- name: va416_ebiboot_fram_256kb + description: VA416_EBIBOOT_256KB + instructions: QfKAAsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HywALE8gECUvggMCP0wEND6kExQvggEHBHAL9B8gASxPIBAlL4IDAj9MBDQ+pBMUL4IBBwRwC/QfJAEsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HyiADE8gEAAmgBIWHzTjICYEJoYfNOMkJggmhh804ygmDCaGHzTjLCYAJpYfNOMgJhQmlh804yQmGCaWHzTjKCYcJpYfNOMsJhAmph804yAmJCamHzTjJCYoJqYfNOMoJiwmph804ywmICa2HzTjICY0JrYfNOMkJjgmth804ygmPCa2HzTjLCYwJsYfNOMgJkQmxh804yQmSCbGHzTjKCZMJsYfNOMsJkAm1h804yAmVCbWHzTjJCZYJtYfNOMoJlwm1h804ywmUCbmHzTjICZkJuYfNOMkJmgm5h804ygmbCbmHzTjLCZgJvYfNOMgJnQm9h804yQmeCb2HzTjKCZ8JvYfNOMsJn0PiAIGHzTjLA+IAg0PiEIGHzTjLA+IQg0PiIIGHzTjLA+Igg0PiMIGHzTjLA+Iwg0PiQIGHzTjLA+JAg0PiUIGHzTjLA+JQg0PiYIGHzTjLA+Jgg0PicIGHzTjLA+Jwg0PioIGHzTjLA+Kgg0PisIGHzTjLA+Kwg0PiwIGHzTjLA+LAg0Pi0IGHzTjLA+LQg0Pi4IGHzTjLA+Lgg0Pi8IGHzTjLA+LwgcEcQtVgkACDE8gEEw/Y5QGBgIGhA9IAwIGD/9xj/T/YAccDytjEAIGFhEL0AvwAgcEeAtU/wwEBP9IAhAPA7+AAggL0AvwAgcEcB8AEDGURLCCnQWR4A8cBAAykD8AMME9Mj8AMDMvgIGwQ7IPgIGzL4Bhwg+AYcMvgEHCD4BBwy+AIcIPgCHO3RvPEADwvQEYi88QEPAYAG0FGIvPECD0GAHL+RiIGAACBwRwC/ACBwRwhEcEdP8AACALUTRpRGlkYgOSK/oOgMUKDoDFCx8SABv/T3rwkHKL+g6AxQSL8MwF34BOuJACi/QPgEKwi/cEdIvyD4AisR8IBPGL8A+AErcEcAAAAAAAA= + pc_init: 0x225 + pc_uninit: 0x251 + pc_program_page: 0x26d + pc_erase_sector: 0x269 + pc_erase_all: 0x255 + data_section_offset: 0x328 + flash_properties: + address_range: + start: 0x0 + end: 0x40000 + page_size: 0x100 + erased_byte_value: 0x0 + program_page_timeout: 3000 + erase_sector_timeout: 3000 + sectors: + - size: 0x2000 + address: 0x0 +- name: va416_ebi_fram_512kb + description: VA416_EBI_512KB + instructions: QfKAAsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HywALE8gECUvggMCP0wEND6kExQvggEHBHAL9B8gASxPIBAlL4IDAj9MBDQ+pBMUL4IBBwRwC/QfJAEsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HyiADE8gEAAmgBIWHzTjICYEJoYfNOMkJggmhh804ygmDCaGHzTjLCYAJpYfNOMgJhQmlh804yQmGCaWHzTjKCYcJpYfNOMsJhAmph804yAmJCamHzTjJCYoJqYfNOMoJiwmph804ywmICa2HzTjICY0JrYfNOMkJjgmth804ygmPCa2HzTjLCYwJsYfNOMgJkQmxh804yQmSCbGHzTjKCZMJsYfNOMsJkAm1h804yAmVCbWHzTjJCZYJtYfNOMoJlwm1h804ywmUCbmHzTjICZkJuYfNOMkJmgm5h804ygmbCbmHzTjLCZgJvYfNOMgJnQm9h804yQmeCb2HzTjKCZ8JvYfNOMsJn0PiAIGHzTjLA+IAg0PiEIGHzTjLA+IQg0PiIIGHzTjLA+Igg0PiMIGHzTjLA+Iwg0PiQIGHzTjLA+JAg0PiUIGHzTjLA+JQg0PiYIGHzTjLA+Jgg0PicIGHzTjLA+Jwg0PioIGHzTjLA+Kgg0PisIGHzTjLA+Kwg0PiwIGHzTjLA+LAg0Pi0IGHzTjLA+LQg0Pi4IGHzTjLA+Lgg0Pi8IGHzTjLA+LwgcEcQtVgkxPIBBCBoQPSAMCBgACDD9jlAYGD/9xj/T/YAcMDytjBgYU7yhBDO8gAAT/QAUQFgRvIAAb/zT4/E8gABGCC/82+PiGAwIgAgCmAQvQAgcEeAtU/wgFBP9AAhAPB4+AAggL0AvwAgcEcB8AEDGURLCCfQWR4DKQPwAwwT0yPwAwMy+AgbBDsg+AgbMvgGHCD4Bhwy+AQcIPgEHDL4Ahwg+AIc7dG88QAPC9ARiLzxAQ8BgAbQUYi88QIPQYAcv5GIgYAAIHBHAL8AIHBHLenwRQHwAQMZRF/qUQwr0OJGvPEBD5i/T/ABCsrxAA6q8QEIACMw+BNQMvgTYLVCItGYRRjQAutDBQDrQwZ3iGyIp0IT0Q7rAwe8HAzQtIipiIxCDdH5HAbQ8YjsiKFCCdEEM5pF3tFgRL3o8IUBMwLgAjMA4AMzT+pDDGBEvejwhU/wAAIAtRNGlEaWRiA5Ir+g6AxQoOgMULHxIAG/9PevCQcov6DoDFBIvwzAXfgE64kAKL9A+AQrCL9wR0i/IPgCKxHwgE8YvwD4AStwRwAAAAA= + pc_init: 0x225 + pc_uninit: 0x275 + pc_program_page: 0x291 + pc_erase_sector: 0x28d + pc_erase_all: 0x279 + data_section_offset: 0x3c4 + flash_properties: + address_range: + start: 0x10000000 + end: 0x10080000 + page_size: 0x100 + erased_byte_value: 0x0 + program_page_timeout: 3000 + erase_sector_timeout: 3000 + sectors: + - size: 0x2000 + address: 0x0 diff --git a/va416xx/scripts/can-clk-calc/.gitignore b/va416xx/scripts/can-clk-calc/.gitignore new file mode 100644 index 0000000..ea8c4bf --- /dev/null +++ b/va416xx/scripts/can-clk-calc/.gitignore @@ -0,0 +1 @@ +/target diff --git a/va416xx/scripts/can-clk-calc/Cargo.toml b/va416xx/scripts/can-clk-calc/Cargo.toml new file mode 100644 index 0000000..ad25349 --- /dev/null +++ b/va416xx/scripts/can-clk-calc/Cargo.toml @@ -0,0 +1,9 @@ +[workspace] + +[package] +name = "can-clk-calc" +version = "0.1.0" +edition = "2024" + +[dependencies] +va416xx-hal = { path = "../../va416xx-hal", features = ["alloc", "revb"], default-features = false } diff --git a/va416xx/scripts/can-clk-calc/src/main.rs b/va416xx/scripts/can-clk-calc/src/main.rs new file mode 100644 index 0000000..0031a05 --- /dev/null +++ b/va416xx/scripts/can-clk-calc/src/main.rs @@ -0,0 +1,14 @@ +use va416xx_hal::can::calculate_all_viable_clock_configs; +use va416xx_hal::time::Hertz; + +fn main() { + let cfgs = calculate_all_viable_clock_configs( + Hertz::from_raw(20_000_000), + Hertz::from_raw(250_000), + 0.75, + ) + .unwrap(); + for cfg in &cfgs { + println!("Config: {:#?}", cfg); + } +} diff --git a/va416xx/scripts/defmt-telnet.sh b/va416xx/scripts/defmt-telnet.sh new file mode 100755 index 0000000..0339483 --- /dev/null +++ b/va416xx/scripts/defmt-telnet.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +# Check if binary path was provided +if [ "$#" -ne 1 ]; then + echo "Usage: $0 " + exit 1 +fi + +BINARY="$1" + +# Check if file exists +if [ ! -f "$BINARY" ]; then + echo "Error: File '$BINARY' not found." + exit 1 +fi + +# Run the command +defmt-print -e "$BINARY" tcp diff --git a/va416xx/scripts/memory.x b/va416xx/scripts/memory.x new file mode 100644 index 0000000..811b87a --- /dev/null +++ b/va416xx/scripts/memory.x @@ -0,0 +1,23 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 256K + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +SECTIONS { + .sram1 (NOLOAD) : ALIGN(8) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM_1 +}; diff --git a/va416xx/scripts/memory_app_a.x b/va416xx/scripts/memory_app_a.x new file mode 100644 index 0000000..6edd645 --- /dev/null +++ b/va416xx/scripts/memory_app_a.x @@ -0,0 +1,24 @@ +/* Special linker script for application slot A with an offset at address 0x4000 */ +MEMORY +{ + FLASH : ORIGIN = 0x00004000, LENGTH = 0x1DFF8 + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +SECTIONS { + .sram1 (NOLOAD) : ALIGN(8) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM_1 +}; diff --git a/va416xx/scripts/memory_app_b.x b/va416xx/scripts/memory_app_b.x new file mode 100644 index 0000000..e15b43f --- /dev/null +++ b/va416xx/scripts/memory_app_b.x @@ -0,0 +1,24 @@ +/* Special linker script for application slot B with an offset at address 0x22000 */ +MEMORY +{ + FLASH : ORIGIN = 0x00022000, LENGTH = 0x1DFF8 + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +SECTIONS { + .sram1 (NOLOAD) : ALIGN(8) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM_1 +}; diff --git a/va416xx/scripts/prep-flash.gdb b/va416xx/scripts/prep-flash.gdb new file mode 100644 index 0000000..e7b843c --- /dev/null +++ b/va416xx/scripts/prep-flash.gdb @@ -0,0 +1,8 @@ +target remote localhost:2331 + +echo Disabling watchdog\n +set *0x400210C0 = 0x1ACCE551 +set *0x40021008 = 0x0 + +echo Disabling Instruction Memory protection\n +set *0x40010010 = 0x1 diff --git a/va416xx/scripts/prep-flash.sh b/va416xx/scripts/prep-flash.sh new file mode 100755 index 0000000..1afc35a --- /dev/null +++ b/va416xx/scripts/prep-flash.sh @@ -0,0 +1,3 @@ +#!/bin/bash +# Alternative way to unlock the ROM protection of the VA416XX to allow flashing +gdb-multiarch -q --batch -ex 'source prep-flash.gdb' \ No newline at end of file diff --git a/va416xx/va416xx-embassy/CHANGELOG.md b/va416xx/va416xx-embassy/CHANGELOG.md new file mode 100644 index 0000000..4170b18 --- /dev/null +++ b/va416xx/va416xx-embassy/CHANGELOG.md @@ -0,0 +1,26 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +## [unreleased] + +## [v0.1.2] 2025-09-03 + +- Bumped HAL dependency to v0.6 + +## [v0.1.1] 2025-03-07 + +- Bumped allowed HAL dependency to v0.5 + +## [v0.1.0] 2025-02-18 + +Initial release + +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-embassy-v0.1.2...HEAD +[v0.1.2]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-embassy-v0.1.1...va416xx-embassy-v0.1.2 +[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-embassy-v0.1.0...va416xx-embassy-v0.1.1 +[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/tag/va416xx-embassy-v0.1.0 diff --git a/va416xx/va416xx-embassy/Cargo.toml b/va416xx/va416xx-embassy/Cargo.toml new file mode 100644 index 0000000..737da12 --- /dev/null +++ b/va416xx/va416xx-embassy/Cargo.toml @@ -0,0 +1,31 @@ +[package] +name = "va416xx-embassy" +version = "0.1.2" +edition = "2021" +authors = ["Robin Mueller "] +description = "Embassy-rs support for the Vorago VA416xx family of microcontrollers" +homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs" +repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs" +license = "Apache-2.0" +keywords = ["no-std", "hal", "cortex-m", "vorago", "va416xx"] +categories = ["aerospace", "embedded", "no-std", "hardware-support"] + +[dependencies] +vorago-shared-hal = { version = "0.2", features = ["vor4x"] } +va416xx-hal = { version = "0.6", path = "../va416xx-hal" } + +[features] +default = ["irq-tim14-tim15"] + +# This determines the reserved interrupt functions for the embassy time drivers. Only one +# is allowed to be selected! +irq-tim14-tim15 = ["_irqs-in-lib"] +irq-tim13-tim14 = ["_irqs-in-lib"] +# These TIMs are clocked slower! +irq-tim22-tim23 = ["_irqs-in-lib"] + +# Private feature. +_irqs-in-lib = [] + +[package.metadata.docs.rs] +rustdoc-args = ["--generate-link-to-definition"] diff --git a/va416xx/va416xx-embassy/README.md b/va416xx/va416xx-embassy/README.md new file mode 100644 index 0000000..813d60e --- /dev/null +++ b/va416xx/va416xx-embassy/README.md @@ -0,0 +1,10 @@ +[![Crates.io](https://img.shields.io/crates/v/va416xx-embassy)](https://crates.io/crates/va416xx-embassy) +[![docs.rs](https://img.shields.io/docsrs/va416xx-embassy)](https://docs.rs/va416xx-embassy) + +# Embassy-rs support for the Vorago VA416xx MCU family + +This repository contains the [embassy-rs](https://github.com/embassy-rs/embassy) support for the +VA416xx family. Currently, it contains the time driver to allow using embassy-rs. It uses the TIM +peripherals provided by the VA416xx family for this purpose. + +The documentation contains more information on how to use this crate. diff --git a/va416xx/va416xx-embassy/docs.sh b/va416xx/va416xx-embassy/docs.sh new file mode 100644 index 0000000..c8ddd4e --- /dev/null +++ b/va416xx/va416xx-embassy/docs.sh @@ -0,0 +1,3 @@ +#!/bin/bash +export RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" +cargo +nightly doc --open diff --git a/va416xx/va416xx-embassy/src/lib.rs b/va416xx/va416xx-embassy/src/lib.rs new file mode 100644 index 0000000..a6865c7 --- /dev/null +++ b/va416xx/va416xx-embassy/src/lib.rs @@ -0,0 +1,117 @@ +//! # Embassy-rs support for the Vorago VA416xx MCU family +//! +//! This repository contains the [embassy-rs](https://github.com/embassy-rs/embassy) support for the +//! VA416xx family. Currently, it contains the time driver to allow using embassy-rs. It uses the TIM +//! peripherals provided by the VA416xx family for this purpose. +//! +//! ## Usage +//! +//! This library only exposes the [embassy::init] method which sets up the time driver. This +//! function must be called once at the start of the application. +//! +//! This implementation requires two TIM peripherals provided by the VA108xx device. +//! The user can freely specify the two used TIM peripheral by passing the concrete TIM instances +//! into the [init] method. If the interrupt handlers are provided by the library, the ID of the +//! used TIM peripherals has to match the ID of the passed timer peripherals. Currently, this +//! can only be checked at run-time, and a run-time assertion will panic on the embassy +//! initialization in case of a missmatch. +//! +//! The application also requires two interrupt handlers to handle the timekeeper and alarm +//! interrupts. By default, this library will define the interrupt handler inside the library +//! itself by using the `irq-tim14-tim15` feature flag. This library exposes three combinations: +//! +//! - `irq-tim14-tim15`: Uses [pac::Interrupt::TIM14] for alarm and [pac::Interrupt::TIM15] +//! for timekeeper +//! - `irq-tim13-tim14`: Uses [pac::Interrupt::TIM13] for alarm and [pac::Interrupt::TIM14] +//! for timekeeper +//! - `irq-tim22-tim23`: Uses [pac::Interrupt::TIM22] for alarm and [pac::Interrupt::TIM23] +//! for timekeeper +//! +//! You can disable the default features and then specify one of the features above to use the +//! documented combination of IRQs. It is also possible to specify custom IRQs by importing and +//! using the [embassy_time_driver_irqs] macro to declare the IRQ handlers in the +//! application code. If this is done, [embassy::init_with_custom_irqs] must be used +//! method to pass the IRQ numbers to the library. +//! +//! ## Examples +//! +//! [embassy example projects](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy) +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] +use va416xx_hal::{ + clock::Clocks, + irq_router::enable_and_init_irq_router, + pac::{self, interrupt}, + timer::{TimInstance, TIM_IRQ_OFFSET}, +}; +use vorago_shared_hal::embassy::time_driver; + +/// Macro to define the IRQ handlers for the time driver. +/// +/// By default, the code generated by this macro will be defined inside the library depending on +/// the feature flags specified. However, the macro is exported to allow users to specify the +/// interrupt handlers themselves. +/// +/// Please note that you have to explicitely import the [macro@va108xx_hal::pac::interrupt] +/// macro in the application code in case this macro is used there. +#[macro_export] +macro_rules! embassy_time_driver_irqs { + ( + timekeeper_irq = $timekeeper_irq:ident, + alarm_irq = $alarm_irq:ident + ) => { + const TIMEKEEPER_IRQ: pac::Interrupt = pac::Interrupt::$timekeeper_irq; + + #[interrupt] + #[allow(non_snake_case)] + fn $timekeeper_irq() { + // Safety: We call it once here. + unsafe { $crate::time_driver().on_interrupt_timekeeping() } + } + + const ALARM_IRQ: pac::Interrupt = pac::Interrupt::$alarm_irq; + + #[interrupt] + #[allow(non_snake_case)] + fn $alarm_irq() { + // Safety: We call it once here. + unsafe { $crate::time_driver().on_interrupt_alarm() } + } + }; +} + +// Provide three combinations of IRQs for the time driver by default. + +#[cfg(feature = "irq-tim14-tim15")] +embassy_time_driver_irqs!(timekeeper_irq = TIM15, alarm_irq = TIM14); +#[cfg(feature = "irq-tim13-tim14")] +embassy_time_driver_irqs!(timekeeper_irq = TIM14, alarm_irq = TIM13); +#[cfg(feature = "irq-tim22-tim23")] +embassy_time_driver_irqs!(timekeeper_irq = TIM23, alarm_irq = TIM22); + +/// Initialization method for embassy +/// +/// If the interrupt handlers are provided by the library, the ID of the +/// used TIM peripherals has to match the ID of the passed timer peripherals. Currently, this +/// can only be checked at run-time, and a run-time assertion will panic on the embassy +/// initialization in case of a missmatch. +pub fn init( + timekeeper: TimekeeperTim, + alarm: AlarmTim, + clocks: &Clocks, +) { + #[cfg(feature = "_irqs-in-lib")] + assert_eq!( + TimekeeperTim::ID.value(), + TIMEKEEPER_IRQ as u8 - TIM_IRQ_OFFSET as u8, + "Timekeeper TIM and IRQ missmatch" + ); + #[cfg(feature = "_irqs-in-lib")] + assert_eq!( + AlarmTim::ID.value(), + ALARM_IRQ as u8 - TIM_IRQ_OFFSET as u8, + "Alarm TIM and IRQ missmatch" + ); + enable_and_init_irq_router(); + time_driver().__init(timekeeper, alarm, clocks) +} diff --git a/va416xx/va416xx-hal/.gitignore b/va416xx/va416xx-hal/.gitignore new file mode 100644 index 0000000..96ef6c0 --- /dev/null +++ b/va416xx/va416xx-hal/.gitignore @@ -0,0 +1,2 @@ +/target +Cargo.lock diff --git a/va416xx/va416xx-hal/CHANGELOG.md b/va416xx/va416xx-hal/CHANGELOG.md new file mode 100644 index 0000000..7db5166 --- /dev/null +++ b/va416xx/va416xx-hal/CHANGELOG.md @@ -0,0 +1,138 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +# [unreleased] + +# [v0.6.0] 2025-09-03 + +- Use `vorago-shared-hal` dependency to provide shared peripherals. +- Bump `va416xx` to v0.5 + +## Changed + +- Replaced `*Cfg`, `*Clk`, `*Sel` abbreviations in names by written out variant. + +# [v0.5.1] 2025-03-10 + +## Fixed + +- Fix `embedded_io` UART implementation to implement the documented contract properly. + The implementation will now block until at least one byte is available or can be written, unless + the send or receive buffer is empty. + +# [v0.5.0] 2025-03-07 + +- Bugfix for I2C `TimingCfg::reg` +- Simplified UART error handling. All APIs are now infallible because writing to a FIFO or + reading from a FIFO never fails. Users can either poll errors using `Rx::poll_errors` or + `Uart::poll_rx_errors` / `UartBase::poll_rx_errors`, or detect errors using the provided + interrupt handlers. + +# [v0.4.1] 2025-02-18 + +- Chip selection is not enforced anymore, but advised through documentation. This makes using + the HAL in libraries a lot easier. + +# [v0.4.0] 2025-02-18 + +## Changed + +- GPIO API: Interrupt, pulse and filter and `set_datamask` and `clear_datamask` APIs are now + methods which mutable modify the pin instead of consuming and returning it. +- Simplified PWM module implementation. +- All error types now implement `core::error::Error` by using the `thiserror::Error` derive. +- `InvalidPinTypeError` now wraps the pin mode. +- I2C `TimingCfg` constructor now returns explicit error instead of generic Error. + Removed the timing configuration error type from the generic I2C error enumeration. +- `PinsA` and `PinsB` constructor do not expect an optional `pac::Ioconfig` argument anymore. +- `IrqCfg` renamed to `InterruptConfig`, kept alias for old name. +- All library provided interrupt handlers now start with common prefix `on_interrupt_*` +- `RxWithIrq` renamed to `RxWithInterrupt` +- `Rx::into_rx_with_irq` does not expect any arguments any more. +- `filter_type` renamed to `configure_filter_type`. +- `level_irq` renamed to `configure_level_interrupt`. +- `edge_irq` renamed to `configure_edge_interrupt`. +- UART interrupt management is now handled by the main constructor instead of later stages to + statically ensure one interrupt vector for the UART peripheral. `Uart::new` expects an + optional `InterruptConfig` argument. +- `enable_interrupt` and `disable_interrupt` renamed to `enable_nvic_interrupt` and + `disable_nvic_interrupt` to distinguish them from peripheral interrupts more clearly. +- `port_mux` renamed to `port_function_select` +- Renamed `IrqUartErrors` to `UartErrors`. + +## Added + +- Add `downgrade` method for `Pin` and `upgrade` method for `DynPin` as explicit conversion + methods. +- Asynchronous GPIO support. +- Asynchronous UART TX support. +- Asynchronous UART RX support. +- Add new `get_tim_raw` unsafe method to retrieve TIM peripheral blocks. +- `Uart::with_with_interrupt` and `Uart::new_without_interrupt` +- A lot of missing `defmt::Format` implementations. + +# [v0.3.0] 2024-30-09 + +## Changed + +- Improve and fix SPI abstractions. Add new low level interface. The primary SPI constructor now + only expects a configuration structure and the transfer configuration needs to be applied in a + separate step. +- Added an additional way to read the UART RX with IRQs. The module documentation provides + more information. +- Made the UART with IRQ API more flexible for future additions. +- Improved UART API result and error handling, added low level API to read from and write + to the FIFO directly + +## Fixed + +- Fixes for SPI peripheral: Flush implementation was incorrect and should now flush properly. +- Fixes for SPI example +- Fixes for RTIC example + +# [v0.2.0] 2024-09-18 + +- Documentation improvements +- Improved UART typing support: Validity of passed pins is now checked properly + +## Changed + +- Added `va41620`, `va41630`, `va41628` and `va41629` device features. A device now has to be + selected for HAL compilation to work properly +- Adaptions for the UART IRQ feature which are now only implemented for the RX part of the UART. + +## Fixed + +- Small fixes and improvements for ADC drivers +- Fixes for the SPI implementation where the clock divider values were not calculated + correctly +- Fixes for UART IRQ handler implementation +- Add new IRQ router initialization method `irq_router::enable_and_init_irq_router`. This method + also sets the initial values of some registers to 0 where the datasheet and the actual reset + value are inconsistent, which can lead to weird bugs like IRQs not being triggered properly. + +## Added + +- Added basic DMA driver +- Added basic EDAC module +- Added bootloader and flashloader example application +- Added NVM module which exposes a simple API to write to the NVM memory used for the boot process + +# [v0.1.0] 2024-07-01 + +- Initial release with basic HAL drivers + +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.6.0...HEAD +[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.5.1...va416xx-hal-v0.6.0 +[v0.5.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.5.0...va416xx-hal-v0.5.1 +[v0.5.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.4.1...va416xx-hal-v0.5.0 +[v0.4.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.4.0...va416xx-hal-v0.4.1 +[v0.4.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.3.0...va416xx-hal-v0.4.0 +[v0.3.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.2.0...va108xx-hal-v0.3.0 +[v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.1.0...va108xx-hal-v0.2.0 +[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/tag/va416xx-hal-v0.1.0 diff --git a/va416xx/va416xx-hal/Cargo.toml b/va416xx/va416xx-hal/Cargo.toml new file mode 100644 index 0000000..7152ac9 --- /dev/null +++ b/va416xx/va416xx-hal/Cargo.toml @@ -0,0 +1,51 @@ +[package] +name = "va416xx-hal" +version = "0.6.0" +authors = ["Robin Mueller "] +edition = "2021" +description = "HAL for the Vorago VA416xx family of MCUs" +homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs" +repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs" +license = "Apache-2.0" +keywords = ["no-std", "hal", "cortex-m", "vorago", "va416xx"] +categories = ["embedded", "no-std", "hardware-support"] + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +va416xx = { version = "0.5", features = ["critical-section"], default-features = false } +derive-mmio = "0.6.1" +static_assertions = "1.1" +vorago-shared-hal = { version = "0.2", features = ["vor4x"] } + +libm = "0.2" +nb = "1" +embedded-hal = "1" +num_enum = { version = "0.7", default-features = false } +bitflags = "2" +bitbybit = "1.3" +arbitrary-int = "2" +fugit = "0.3" +embedded-can = "0.4" +embassy-sync = "0.7" +thiserror = { version = "2", default-features = false } + +defmt = { version = "1", optional = true } + +[features] +default = ["rt", "revb"] +rt = ["va416xx/rt"] +alloc = [] +defmt = ["dep:defmt", "fugit/defmt", "vorago-shared-hal/defmt"] + +va41630 = ["device-selected"] +va41620 = ["device-selected"] + +va41629 = ["device-selected"] +va41628 = ["device-selected", "vorago-shared-hal/va41628"] + +device-selected = [] +revb = [] + +[package.metadata.docs.rs] +features = ["va41630", "defmt"] +rustdoc-args = ["--generate-link-to-definition"] diff --git a/va416xx/va416xx-hal/LICENSE-APACHE b/va416xx/va416xx-hal/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va416xx/va416xx-hal/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va416xx/va416xx-hal/NOTICE b/va416xx/va416xx-hal/NOTICE new file mode 100644 index 0000000..5a0a3dc --- /dev/null +++ b/va416xx/va416xx-hal/NOTICE @@ -0,0 +1,3 @@ +Rust Hardware Abstraction Layer (HAL) crate for the Vorago VA416xx family of MCUs + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va416xx/va416xx-hal/README.md b/va416xx/va416xx-hal/README.md new file mode 100644 index 0000000..1ce98ba --- /dev/null +++ b/va416xx/va416xx-hal/README.md @@ -0,0 +1,78 @@ +[![Crates.io](https://img.shields.io/crates/v/va416xx-hal)](https://crates.io/crates/va416xx-hal) +[![docs.rs](https://img.shields.io/docsrs/va416xx-hal)](https://docs.rs/va416xx-hal) + +# HAL for the Vorago VA416xx MCU family + +This repository contains the **H**ardware **A**bstraction **L**ayer (HAL), which is an additional +hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx). + +It is the result of reading the datasheet for the device and encoding a type-safe layer over the +raw PAC. This crate also implements traits specified by the +[embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with +various drivers in the embedded rust ecosystem. + +It is generally advised to enable ONE of the following device features to use this crate +depending on which chip you are using: + +- `va41630` +- `va41629` +- `va41628` +- `va41620` + +If no chip is specified, only access to APIs which are common for all families or +which are not disabled for specific families is granted. + +## Building + +Building an application requires the `thumbv7em-none-eabihf` cross-compiler toolchain. +If you have not installed it yet, you can do so with + +```sh +rustup target add thumbv7em-none-eabihf +``` + +After that, you can use `cargo build` to build the development version of the crate. + +## Setting up your own binary crate + +If you have a custom board, you might be interested in setting up a new binary crate for your +project. These steps aim to provide a complete list to get a binary crate working to flash +your custom board. + +The hello world of embedded development is usually to blinky a LED. This example +is contained within the +[examples folder](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/blinky.rs). + +1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building) +2. Create a new binary crate with `cargo init` +3. To ensure that `cargo build` cross-compiles, it is recommended to create a `.cargo/config.toml` + file. You can use [this](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/.cargo/def-config.toml) + sample file as a starting point. +4. Copy the `memory.x` file into your project. This file contains information required by the linker. +5. Copy the `blinky.rs` file to the `src/main.rs` file in your binary crate +6. You need to add some dependencies to your `Cargo.toml` file + + ```toml + [dependencies] + cortex-m = "" + cortex-m-rt = "" + panic-halt = "" + embedded-hal = "" + + [dependencies.va416xx-hal] + version = "" + features = ["va41630"] + ``` + +6. Build the application with `cargo build` + +7. Flashing the board might work differently for different boards and there is usually + more than one way. You can find example instructions in primary README. + +## Embedded Rust + +If you have not done this yet, it is recommended to read some of the excellent resources +available to learn Rust: + +- [Rust Embedded Book](https://docs.rust-embedded.org/book/) +- [Rust Discovery Book](https://docs.rust-embedded.org/discovery/) diff --git a/va416xx/va416xx-hal/docs.sh b/va416xx/va416xx-hal/docs.sh new file mode 100755 index 0000000..aa550c7 --- /dev/null +++ b/va416xx/va416xx-hal/docs.sh @@ -0,0 +1,3 @@ +#!/bin/sh +export RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" +cargo +nightly doc --features "defmt va41630" --open diff --git a/va416xx/va416xx-hal/jlink-gdb.sh b/va416xx/va416xx-hal/jlink-gdb.sh new file mode 100755 index 0000000..65e187f --- /dev/null +++ b/va416xx/va416xx-hal/jlink-gdb.sh @@ -0,0 +1,5 @@ +#!/bin/bash +# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary +# to disable ROM protection to allow flashing +JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript diff --git a/va416xx/va416xx-hal/jlink/JLinkSettings.JLinkScript b/va416xx/va416xx-hal/jlink/JLinkSettings.JLinkScript new file mode 100644 index 0000000..59cff80 --- /dev/null +++ b/va416xx/va416xx-hal/jlink/JLinkSettings.JLinkScript @@ -0,0 +1,77 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 1995 - 2018 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +---------------------------------------------------------------------- +File : JLinkSettings.JLinkScript +Purpose : J-Link target setup file for VORAGO VA416xx +---------------------------END-OF-HEADER------------------------------ +*/ + +int DisableRomProt(void) { + JLINK_SYS_Report("VA416XX: Disabling ROM protection"); + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +int DisableWatchdog(void) { + JLINK_MEM_WriteU32(0x400210C0, 0x1ACCE551); // WDOGLOCK = 0x1ACCE551 + JLINK_MEM_WriteU32(0x40021008, 0x0); // WDOGCONTROL = 0x0 (diable) +} + +int SetupTarget (void) { + JLINK_SYS_Report("SetupTarget()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterResetTarget +*/ +int AfterResetTarget (void) { + JLINK_SYS_Report("AfterResetTarget()"); + // disable watchdog and unlock code RAM for write + DisableWatchdog(); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* BeforeTargetDownload +*/ +int BeforeTargetDownload (void) { + JLINK_SYS_Report("BeforeTargetDownload()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterTargetDownload +*/ +int AfterTargetDownload (void) { + JLINK_SYS_Report("AfterTargetDownload()"); + return DisableRomProt(); // ROM_PROT = 0x0 +} + +/********************************************************************* +* +* HandleBeforeFlashProg +*/ +int HandleBeforeFlashProg(void) { + JLINK_SYS_Report("HandleBeforeFlashProg()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* HandleAfterFlashProg +*/ +int HandleAfterFlashProg(void) { + JLINK_SYS_Report("HandleAfterFlashProg()"); + return DisableRomProt(); // ROM_PROT = 0x0 +} \ No newline at end of file diff --git a/va416xx/va416xx-hal/jlink/jlink-reva.gdb b/va416xx/va416xx-hal/jlink/jlink-reva.gdb new file mode 100644 index 0000000..8712a8e --- /dev/null +++ b/va416xx/va416xx-hal/jlink/jlink-reva.gdb @@ -0,0 +1,13 @@ +target remote localhost:2331 + +# For some reason, this is problematic even if the JLinkScript disabled the remote +# write protection. Therefore, don't do it for now +# This is only problematic on board RevA +# monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va416xx/va416xx-hal/jlink/jlink.gdb b/va416xx/va416xx-hal/jlink/jlink.gdb new file mode 100644 index 0000000..615efdc --- /dev/null +++ b/va416xx/va416xx-hal/jlink/jlink.gdb @@ -0,0 +1,11 @@ +target remote localhost:2331 + +# Reset is problematic on RevA, okay for RevB +monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va416xx/va416xx-hal/src/adc.rs b/va416xx/va416xx-hal/src/adc.rs new file mode 100644 index 0000000..d404e2c --- /dev/null +++ b/va416xx/va416xx-hal/src/adc.rs @@ -0,0 +1,425 @@ +//! Analog to Digital Converter (ADC) driver. +//! +//! ## Examples +//! +//! - [ADC and DAC example](https://github.com/us-irs/va416xx-rs/blob/main/examples/simple/examples/dac-adc.rs) +//! - [ADC](https://github.com/us-irs/va416xx-rs/blob/main/examples/simple/examples/adc.rs) +use core::marker::PhantomData; + +use crate::clock::Clocks; +use crate::pac; +use crate::time::Hertz; +use num_enum::{IntoPrimitive, TryFromPrimitive}; +use vorago_shared_hal::{enable_peripheral_clock, PeripheralSelect}; + +pub const ADC_MIN_CLK: Hertz = Hertz::from_raw(2_000_000); +pub const ADC_MAX_CLK: Hertz = Hertz::from_raw(12_500_000); + +#[derive(Debug, PartialEq, Eq, Copy, Clone, TryFromPrimitive, IntoPrimitive)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[repr(u8)] +pub enum ChannelSelect { + /// Analogue Input 0 external channel + AnIn0 = 0, + /// Analogue Input 1 external channel + AnIn1 = 1, + /// Analogue Input 2 external channel + AnIn2 = 2, + /// Analogue Input 3 external channel + AnIn3 = 3, + /// Analogue Input 4 external channel + AnIn4 = 4, + /// Analogue Input 5 external channel + AnIn5 = 5, + /// Analogue Input 6 external channel + AnIn6 = 6, + /// Analogue Input 7 external channel + AnIn7 = 7, + /// DAC 0 internal channel + Dac0 = 8, + /// DAC 1 internal channel + Dac1 = 9, + /// Internal temperature sensor + TempSensor = 10, + /// Internal bandgap 1 V reference + Bandgap1V = 11, + /// Internal bandgap 1.5 V reference + Bandgap1_5V = 12, + Avdd1_5 = 13, + Dvdd1_5 = 14, + /// Internally generated Voltage equal to VREFH / 2 + Vrefp5 = 15, +} + +bitflags::bitflags! { + /// This structure is used by the ADC multi-select API to + /// allow selecting multiple channels in a convenient manner. + #[derive(Debug)] + pub struct MultiChannelSelect: u16 { + const AnIn0 = 1; + const AnIn1 = 1 << 1; + const AnIn2 = 1 << 2; + const AnIn3 = 1 << 3; + const AnIn4 = 1 << 4; + const AnIn5 = 1 << 5; + const AnIn6 = 1 << 6; + const AnIn7 = 1 << 7; + const Dac0 = 1 << 8; + const Dac1 = 1 << 9; + const TempSensor = 1 << 10; + const Bandgap1V = 1 << 11; + const Bandgap1_5V = 1 << 12; + const Avdd1_5 = 1 << 13; + const Dvdd1_5 = 1 << 14; + const Vrefp5 = 1 << 15; + } +} + +#[derive(Debug, PartialEq, Eq, Copy, Clone, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("ADC empty error")] +pub struct AdcEmptyError; + +#[derive(Debug, PartialEq, Eq, Copy, Clone, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("invalid channel range error")] +pub struct InvalidChannelRangeError; + +#[derive(Debug, PartialEq, Eq, Copy, Clone, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("buffer too small")] +pub struct BufferTooSmallError; + +#[derive(Debug, PartialEq, Eq, Copy, Clone, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AdcRangeReadError { + #[error("invalid channel range: {0}")] + InvalidChannelRange(#[from] InvalidChannelRangeError), + #[error("buffer too small: {0}")] + BufferTooSmall(#[from] BufferTooSmallError), +} + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct ChannelValue { + /// If the channel tag is enabled, this field will contain the determined channel tag. + channel: ChannelSelect, + /// Raw value. + value: u16, +} + +impl Default for ChannelValue { + fn default() -> Self { + Self { + channel: ChannelSelect::AnIn0, + value: Default::default(), + } + } +} + +impl ChannelValue { + #[inline] + pub fn value(&self) -> u16 { + self.value + } + + #[inline] + pub fn channel(&self) -> ChannelSelect { + self.channel + } +} + +pub enum ChannelTagEnabled {} +pub enum ChannelTagDisabled {} + +/// ADC driver structure. +/// +/// Currently, this structure supports three primary ways to measure channel value(s): +/// +/// * Trigger and read a single value +/// * Trigger and read a range of ADC values using the sweep functionality +/// * Trigger and read multiple ADC values using the sweep functionality +/// +/// The ADC channel tag feature is enabled or disabled at compile time using the +/// [ChannelTagEnabled] and [ChannelTagDisabled]. The [Adc::new] method returns a driver instance +/// with the channel tag enabled, while the [Adc::new_with_channel_tag] method can be used to +/// return an instance with the channel tag enabled. +pub struct Adc { + adc: pac::Adc, + phantom: PhantomData, +} + +impl Adc {} + +impl Adc { + pub fn new(adc: pac::Adc, clocks: &Clocks) -> Self { + Self::generic_new(adc, clocks) + } + + pub fn trigger_and_read_single_channel(&self, ch: ChannelSelect) -> Result { + self.generic_trigger_and_read_single_channel(ch) + .map(|v| v & 0xfff) + } + + /// Perform a sweep for a specified range of ADC channels. + /// + /// Returns the number of read values which were written to the passed RX buffer. + pub fn sweep_and_read_range( + &self, + lower_bound_idx: u8, + upper_bound_idx: u8, + rx_buf: &mut [u16], + ) -> Result { + self.generic_prepare_range_sweep_and_wait_until_ready( + lower_bound_idx, + upper_bound_idx, + rx_buf.len(), + )?; + let fifo_entry_count = self.adc.status().read().fifo_entry_cnt().bits(); + for i in 0..core::cmp::min(fifo_entry_count, rx_buf.len() as u8) { + rx_buf[i as usize] = self.adc.fifo_data().read().bits() as u16 & 0xfff; + } + Ok(fifo_entry_count as usize) + } + + /// Perform a sweep for selected ADC channels. + /// + /// Returns the number of read values which were written to the passed RX buffer. + pub fn sweep_and_read_multiselect( + &self, + ch_select: MultiChannelSelect, + rx_buf: &mut [u16], + ) -> Result { + self.generic_prepare_multiselect_sweep_and_wait_until_ready(ch_select, rx_buf.len())?; + let fifo_entry_count = self.adc.status().read().fifo_entry_cnt().bits(); + for i in 0..core::cmp::min(fifo_entry_count, rx_buf.len() as u8) { + rx_buf[i as usize] = self.adc.fifo_data().read().bits() as u16 & 0xfff; + } + Ok(fifo_entry_count as usize) + } + + pub fn try_read_single_value(&self) -> nb::Result, ()> { + self.generic_try_read_single_value() + .map(|v| v.map(|v| v & 0xfff)) + } + + #[inline(always)] + pub fn channel_tag_enabled(&self) -> bool { + false + } +} + +impl Adc { + pub fn new_with_channel_tag(adc: pac::Adc, clocks: &Clocks) -> Self { + let mut adc = Self::generic_new(adc, clocks); + adc.enable_channel_tag(); + adc + } + + pub fn trigger_and_read_single_channel( + &self, + ch: ChannelSelect, + ) -> Result { + self.generic_trigger_and_read_single_channel(ch) + .map(|v| self.create_channel_value(v)) + } + + pub fn try_read_single_value(&self) -> nb::Result, ()> { + self.generic_try_read_single_value() + .map(|v| v.map(|v| self.create_channel_value(v))) + } + + /// Perform a sweep for a specified range of ADC channels. + /// + /// Returns the number of read values which were written to the passed RX buffer. + pub fn sweep_and_read_range( + &self, + lower_bound_idx: u8, + upper_bound_idx: u8, + rx_buf: &mut [ChannelValue], + ) -> Result { + self.generic_prepare_range_sweep_and_wait_until_ready( + lower_bound_idx, + upper_bound_idx, + rx_buf.len(), + )?; + let fifo_entry_count = self.adc.status().read().fifo_entry_cnt().bits(); + for i in 0..core::cmp::min(fifo_entry_count, rx_buf.len() as u8) { + rx_buf[i as usize] = + self.create_channel_value(self.adc.fifo_data().read().bits() as u16); + } + Ok(fifo_entry_count as usize) + } + + /// Perform a sweep for selected ADC channels. + /// + /// Returns the number of read values which were written to the passed RX buffer. + pub fn sweep_and_read_multiselect( + &self, + ch_select: MultiChannelSelect, + rx_buf: &mut [ChannelValue], + ) -> Result { + self.generic_prepare_multiselect_sweep_and_wait_until_ready(ch_select, rx_buf.len())?; + let fifo_entry_count = self.adc.status().read().fifo_entry_cnt().bits(); + for i in 0..core::cmp::min(fifo_entry_count, rx_buf.len() as u8) { + rx_buf[i as usize] = + self.create_channel_value(self.adc.fifo_data().read().bits() as u16); + } + Ok(fifo_entry_count as usize) + } + + #[inline] + pub fn create_channel_value(&self, raw_value: u16) -> ChannelValue { + ChannelValue { + value: raw_value & 0xfff, + channel: ChannelSelect::try_from(((raw_value >> 12) & 0xf) as u8).unwrap(), + } + } + + #[inline(always)] + pub fn channel_tag_enabled(&self) -> bool { + true + } +} + +impl Adc { + fn generic_new(adc: pac::Adc, _clocks: &Clocks) -> Self { + enable_peripheral_clock(PeripheralSelect::Adc); + adc.ctrl().write(|w| unsafe { w.bits(0) }); + let adc = Self { + adc, + phantom: PhantomData, + }; + adc.clear_fifo(); + adc + } + + #[inline(always)] + fn enable_channel_tag(&mut self) { + self.adc.ctrl().modify(|_, w| w.chan_tag_en().set_bit()); + } + + #[inline(always)] + fn disable_channel_tag(&mut self) { + self.adc.ctrl().modify(|_, w| w.chan_tag_en().clear_bit()); + } + + #[inline(always)] + pub fn clear_fifo(&self) { + self.adc.fifo_clr().write(|w| unsafe { w.bits(1) }); + } + + pub fn generic_try_read_single_value(&self) -> nb::Result, ()> { + if self.adc.status().read().adc_busy().bit_is_set() { + return Err(nb::Error::WouldBlock); + } + if self.adc.status().read().fifo_entry_cnt().bits() == 0 { + return Ok(None); + } + Ok(Some(self.adc.fifo_data().read().bits() as u16)) + } + + fn generic_trigger_single_channel(&self, ch: ChannelSelect) { + self.adc.ctrl().modify(|_, w| { + w.ext_trig_en().clear_bit(); + unsafe { + // N + 1 conversions, so set set 0 here. + w.conv_cnt().bits(0); + w.chan_en().bits(1 << ch as u8) + } + }); + self.clear_fifo(); + + self.adc.ctrl().modify(|_, w| w.manual_trig().set_bit()); + } + + fn generic_prepare_range_sweep_and_wait_until_ready( + &self, + lower_bound_idx: u8, + upper_bound_idx: u8, + buf_len: usize, + ) -> Result<(), AdcRangeReadError> { + if (lower_bound_idx > 15 || upper_bound_idx > 15) || lower_bound_idx > upper_bound_idx { + return Err(InvalidChannelRangeError.into()); + } + let ch_count = upper_bound_idx - lower_bound_idx + 1; + if buf_len < ch_count as usize { + return Err(BufferTooSmallError.into()); + } + let mut ch_select = 0; + for i in lower_bound_idx..upper_bound_idx + 1 { + ch_select |= 1 << i; + } + self.generic_trigger_sweep(ch_select); + while self.adc.status().read().adc_busy().bit_is_set() { + cortex_m::asm::nop(); + } + Ok(()) + } + + fn generic_prepare_multiselect_sweep_and_wait_until_ready( + &self, + ch_select: MultiChannelSelect, + buf_len: usize, + ) -> Result<(), BufferTooSmallError> { + let ch_select = ch_select.bits(); + let ch_count = ch_select.count_ones(); + if buf_len < ch_count as usize { + return Err(BufferTooSmallError); + } + self.generic_trigger_sweep(ch_select); + while self.adc.status().read().adc_busy().bit_is_set() { + cortex_m::asm::nop(); + } + Ok(()) + } + + fn generic_trigger_sweep(&self, ch_select: u16) { + let ch_num = ch_select.count_ones() as u8; + assert!(ch_num > 0); + self.adc.ctrl().modify(|_, w| { + w.ext_trig_en().clear_bit(); + unsafe { + // N + 1 conversions. + w.conv_cnt().bits(0); + w.chan_en().bits(ch_select); + w.sweep_en().set_bit() + } + }); + self.clear_fifo(); + + self.adc.ctrl().modify(|_, w| w.manual_trig().set_bit()); + } + + fn generic_trigger_and_read_single_channel( + &self, + ch: ChannelSelect, + ) -> Result { + self.generic_trigger_single_channel(ch); + nb::block!(self.generic_try_read_single_value()) + .unwrap() + .ok_or(AdcEmptyError) + } +} + +impl From> for Adc { + fn from(value: Adc) -> Self { + let mut adc = Self { + adc: value.adc, + phantom: PhantomData, + }; + adc.enable_channel_tag(); + adc + } +} + +impl From> for Adc { + fn from(value: Adc) -> Self { + let mut adc = Self { + adc: value.adc, + phantom: PhantomData, + }; + adc.disable_channel_tag(); + adc + } +} diff --git a/va416xx/va416xx-hal/src/can/asynch.rs b/va416xx/va416xx-hal/src/can/asynch.rs new file mode 100644 index 0000000..89cefa7 --- /dev/null +++ b/va416xx/va416xx-hal/src/can/asynch.rs @@ -0,0 +1,311 @@ +use core::{ + future::Future, + sync::atomic::{AtomicU8, Ordering}, +}; + +use crate::can::regs::BufferState; + +use super::{ + regs::{DiagnosticRegister, InterruptClear, MmioCan, StatusPending}, + CanChannelLowLevel, CanFrame, CanId, InvalidBufferIndexError, +}; + +#[derive(Debug)] +pub enum TxChannelState { + Unconfigured = 0, + Idle = 1, + TxDataFrame = 2, + TxRtrTransmission = 3, + TxRtrReception = 4, + Finished = 5, +} + +static TX_STATES: [AtomicU8; 15] = [const { AtomicU8::new(0) }; 15]; +static TX_WAKERS: [embassy_sync::waitqueue::AtomicWaker; 15] = + [const { embassy_sync::waitqueue::AtomicWaker::new() }; 15]; + +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum TxEventId { + /// Buffer state went from [BufferState::TxOnce] to [BufferState::TxNotActive]. + TxDataFrame, + /// Buffer state went from [BufferState::TxOnce] to [BufferState::TxNotActive] for a remote + /// frame (RTR bit set). Channel might be in reception mode [BufferState::RxReady] now. + TxRemoteFrame, + /// A response to a remote frame was performed successfully, and the buffer state went from + /// [BufferState::TxOnceRtr] to [BufferState::TxRtr]. + RtrResponse, + /// A remote frame was received and the transmission of a response frame was scheduled. The + /// buffer state went from [BufferState::TxRtr] to [BufferState::TxOnceRtr]. + TransmitScheduling, +} + +#[derive(Debug)] +pub enum InterruptResult { + NoInterrupt, + ReceivedFrame { + channel_index: usize, + frame: CanFrame, + }, + TransmissionEvent { + channel_index: usize, + id: TxEventId, + }, +} + +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum InterruptError { + UnexpectedError, + InvalidInterruptId(StatusPending), + InvalidStatus(u8), + UnexpectedState(BufferState), + CanError(DiagnosticRegister), +} + +/// This interrupt handler allow asynchronous transmission and reception of CAN frames. +/// +/// This handler will re-configure a channel to [BufferState::RxReady] after successfull reception +/// of a frame without disabling the interrupts, assuming that the user wants to immediately +/// receive the next frame on the channel. +/// The user should re-configure the buffer state to [BufferState::RxNotActive] if the reception +/// should be disabled. +/// +/// The handler will re-configure a channel to [BufferState::TxNotActive] instead of +/// [BufferState::RxReady] if the completed frame transmission was a remote frame and after +/// successfully having received a response to that remote frame. The assumption is that this +/// channel is used to request more frames. If the argument `reconfigure_tx_rtr_to_tx` is set to +/// true, the channel will automatically be configured back to [BufferState::TxNotActive] with +/// interrupts for the respective channel disabled after transmission of a remote frame. +/// +/// The handler will not disable the interrupts realted to the TX RTR and TX RTR ONCE auto-response +/// functionality of the CAN peripheral. It will report the event type to the caller via the +/// [TxEventId] enumeration. +pub fn on_interrupt_can( + id: CanId, + reconfigure_tx_rtr_to_tx: bool, +) -> Result { + let mut regs = unsafe { id.steal_regs() }; + // Check if any interrupts are enabled. + let ie = regs.read_ien(); + if ie.raw_value() == 0 { + return Ok(InterruptResult::NoInterrupt); + } + let pending_id = regs.read_status_pending(); + if pending_id.interrupt_id().is_none() { + regs.write_iclr(InterruptClear::new_with_raw_value(0xFFFF_FFFF)); + return Err(InterruptError::InvalidInterruptId(pending_id)); + } + match pending_id.interrupt_id().unwrap() { + super::regs::CanInterruptId::None => Ok(InterruptResult::NoInterrupt), + super::regs::CanInterruptId::Error => Err(InterruptError::CanError(regs.read_diag())), + super::regs::CanInterruptId::Buffer(idx) => { + let mut channel = unsafe { CanChannelLowLevel::steal_unchecked(id, idx) }; + let status = channel.read_state(); + if let Err(e) = status { + let mut clr = InterruptClear::new_with_raw_value(0); + clr.set_buffer(idx, true); + regs.write_iclr(clr); + regs.modify_ien(|mut val| { + val.set_buffer(idx, false); + val + }); + return Err(InterruptError::InvalidStatus(e)); + } + let buf_state = status.unwrap(); + if buf_state == BufferState::TxNotActive { + let tx_state = TX_STATES[idx].load(Ordering::Relaxed); + clear_and_disable_interrupt(&mut regs, idx); + // Handle reading frames, updating states etc. + if tx_state == TxChannelState::TxDataFrame as u8 { + // Transmission complete. + TX_STATES[idx].store(TxChannelState::Finished as u8, Ordering::Relaxed); + TX_WAKERS[idx].wake(); + return Ok(InterruptResult::TransmissionEvent { + channel_index: idx, + id: TxEventId::TxDataFrame, + }); + } + } + if buf_state == BufferState::RxReady { + let tx_state = TX_STATES[idx].load(Ordering::Relaxed); + if tx_state == TxChannelState::TxRtrTransmission as u8 { + if reconfigure_tx_rtr_to_tx { + channel.write_state(BufferState::TxNotActive); + clear_and_disable_interrupt(&mut regs, idx); + // Transmission complete. + TX_STATES[idx].store(TxChannelState::Idle as u8, Ordering::Relaxed); + } else { + // Do not disable interrupt, channel is now used to receive the frame. + clear_interrupt(&mut regs, idx); + // Transmission complete. + TX_STATES[idx] + .store(TxChannelState::TxRtrReception as u8, Ordering::Relaxed); + } + TX_WAKERS[idx].wake(); + return Ok(InterruptResult::TransmissionEvent { + channel_index: idx, + id: TxEventId::TxRemoteFrame, + }); + } + } + if buf_state == BufferState::RxOverrun || buf_state == BufferState::RxFull { + let tx_state = TX_STATES[idx].load(Ordering::Relaxed); + // Do not disable interrupt and assume continuous reception. + clear_interrupt(&mut regs, idx); + let frame = channel.read_frame_unchecked(); + if tx_state == TxChannelState::TxRtrReception as u8 { + // Reception of response complete. We can release the channel for TX (or RX) + // usage again. + TX_STATES[idx].store(TxChannelState::Idle as u8, Ordering::Relaxed); + channel.write_state(BufferState::TxNotActive); + } else { + // Assume continous reception of frames. + channel.write_state(BufferState::RxReady); + } + return Ok(InterruptResult::ReceivedFrame { + channel_index: idx, + frame, + }); + } + if buf_state == BufferState::TxRtr { + // Do not disable interrupt and assume continuous transmission. + clear_interrupt(&mut regs, idx); + return Ok(InterruptResult::TransmissionEvent { + channel_index: idx, + id: TxEventId::RtrResponse, + }); + } + if buf_state == BufferState::TxOnceRtr { + // Do not disable interrupt and assume continuous transmission. + clear_interrupt(&mut regs, idx); + return Ok(InterruptResult::TransmissionEvent { + channel_index: idx, + id: TxEventId::TransmitScheduling, + }); + } + + Err(InterruptError::UnexpectedState(buf_state)) + } + } +} + +#[inline(always)] +fn clear_interrupt(regs: &mut MmioCan<'static>, idx: usize) { + let mut clr = InterruptClear::new_with_raw_value(0); + clr.set_buffer(idx, true); + regs.write_iclr(clr); +} + +#[inline(always)] +fn clear_and_disable_interrupt(regs: &mut MmioCan<'static>, idx: usize) { + clear_interrupt(regs, idx); + regs.modify_ien(|mut val| { + val.set_buffer(idx, false); + val + }); +} + +#[derive(Debug, thiserror::Error)] +#[error("all channels are unconfigured, none available for TX")] +pub struct AllTxChannelsUnconfiguredError; + +pub struct CanTxFuture(usize); + +impl Future for CanTxFuture { + type Output = (); + + fn poll( + self: core::pin::Pin<&mut Self>, + cx: &mut core::task::Context<'_>, + ) -> core::task::Poll { + TX_WAKERS[self.0].register(cx.waker()); + if TX_STATES[self.0].load(Ordering::Relaxed) == TxChannelState::Finished as u8 { + TX_STATES[self.0].store(TxChannelState::Idle as u8, Ordering::Relaxed); + return core::task::Poll::Ready(()); + } + core::task::Poll::Pending + } +} + +impl CanTxFuture { + pub fn new(frame: CanFrame) -> nb::Result { + let mut channel_is_free = [false; 15]; + let mut all_channels_unused = true; + for (idx, state) in TX_STATES.iter().enumerate() { + let state = state.load(Ordering::Relaxed); + if state == TxChannelState::Idle as u8 { + channel_is_free[idx] = true; + } + if state != TxChannelState::Unconfigured as u8 { + all_channels_unused = false; + } + } + if channel_is_free.iter().all(|&x| !x) { + return Err(nb::Error::WouldBlock); + } + if all_channels_unused { + return Err(nb::Error::Other(AllTxChannelsUnconfiguredError)); + } + let free_channel_id = channel_is_free.iter().position(|&x| x).unwrap(); + let mut channel = + unsafe { CanChannelLowLevel::steal_unchecked(CanId::Can0, free_channel_id) }; + TX_STATES[free_channel_id].store(TxChannelState::TxDataFrame as u8, Ordering::Relaxed); + channel.write_state(BufferState::TxNotActive); + channel.transmit_frame_unchecked(frame); + channel.clear_interrupt(); + channel.enable_interrupt(true); + channel.enable_error_interrupt(true); + Ok(CanTxFuture(free_channel_id)) + } +} + +#[derive(Debug, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ChannelConfigError { + #[error("channel is busy")] + Busy, + #[error("invalid offset: {0}")] + Offset(#[from] InvalidBufferIndexError), +} + +pub struct CanTxAsync; + +impl CanTxAsync { + pub fn new(can: &mut super::Can) -> Self { + can.clear_interrupts(); + can.enable_nvic_interrupt(); + CanTxAsync + } + + pub fn configure_channel(&mut self, channel_idx: usize) -> Result<(), ChannelConfigError> { + if channel_idx >= TX_STATES.len() { + return Err(ChannelConfigError::Offset(InvalidBufferIndexError( + channel_idx, + ))); + } + let state = TX_STATES[channel_idx].load(Ordering::Relaxed); + if state != TxChannelState::Idle as u8 && state != TxChannelState::Unconfigured as u8 { + return Err(ChannelConfigError::Busy); + } + TX_STATES[channel_idx].store(TxChannelState::Idle as u8, Ordering::Relaxed); + Ok(()) + } + + /// Start a transmission and returns the future which can be polled to completion. + pub fn start_transmit( + &mut self, + frame: CanFrame, + ) -> nb::Result { + CanTxFuture::new(frame) + } + + /// Calls [Self::start_transmit] and awaits the returned future to completion immediately. + pub async fn transmit( + &mut self, + frame: CanFrame, + ) -> nb::Result<(), AllTxChannelsUnconfiguredError> { + self.start_transmit(frame)?.await; + Ok(()) + } +} diff --git a/va416xx/va416xx-hal/src/can/frame.rs b/va416xx/va416xx-hal/src/can/frame.rs new file mode 100644 index 0000000..0f2989e --- /dev/null +++ b/va416xx/va416xx-hal/src/can/frame.rs @@ -0,0 +1,131 @@ +pub use embedded_can::{ExtendedId, Id, StandardId}; + +#[derive(Debug, thiserror::Error)] +#[error("invalid data size error {0}")] +pub struct InvalidDataSizeError(usize); + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub struct CanFrameNormal { + id: embedded_can::Id, + size: usize, + data: [u8; 8], +} + +impl CanFrameNormal { + pub fn new(id: embedded_can::Id, data: &[u8]) -> Result { + if data.len() > 8 { + return Err(InvalidDataSizeError(data.len())); + } + let size = data.len(); + let mut data_array = [0; 8]; + data_array[0..size].copy_from_slice(data); + Ok(Self { + id, + size, + data: data_array, + }) + } + + #[inline] + pub fn id(&self) -> embedded_can::Id { + self.id + } + + #[inline] + pub fn data(&self) -> &[u8] { + &self.data[0..self.dlc()] + } + + #[inline] + pub fn dlc(&self) -> usize { + self.size + } +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub struct CanFrameRtr { + id: embedded_can::Id, + dlc: usize, +} + +impl CanFrameRtr { + pub fn new(id: embedded_can::Id, dlc: usize) -> Self { + Self { id, dlc } + } + + pub fn id(&self) -> embedded_can::Id { + self.id + } + + pub fn dlc(&self) -> usize { + self.dlc + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum CanFrame { + Normal(CanFrameNormal), + Rtr(CanFrameRtr), +} + +impl From for CanFrame { + fn from(value: CanFrameNormal) -> Self { + Self::Normal(value) + } +} + +impl From for CanFrame { + fn from(value: CanFrameRtr) -> Self { + Self::Rtr(value) + } +} + +impl embedded_can::Frame for CanFrame { + fn new(id: impl Into, data: &[u8]) -> Option { + if data.len() > 8 { + return None; + } + let id: embedded_can::Id = id.into(); + Some(Self::Normal(CanFrameNormal::new(id, data).unwrap())) + } + + fn new_remote(id: impl Into, dlc: usize) -> Option { + let id: embedded_can::Id = id.into(); + Some(Self::Rtr(CanFrameRtr::new(id, dlc))) + } + + fn is_extended(&self) -> bool { + match self.id() { + embedded_can::Id::Extended(_) => true, + embedded_can::Id::Standard(_) => false, + } + } + + fn is_remote_frame(&self) -> bool { + match self { + CanFrame::Normal(_) => false, + CanFrame::Rtr(_) => true, + } + } + + fn id(&self) -> embedded_can::Id { + match self { + CanFrame::Normal(can_frame_normal) => can_frame_normal.id(), + CanFrame::Rtr(can_frame_rtr) => can_frame_rtr.id(), + } + } + + fn dlc(&self) -> usize { + match self { + CanFrame::Normal(can_frame_normal) => can_frame_normal.dlc(), + CanFrame::Rtr(can_frame_rtr) => can_frame_rtr.dlc(), + } + } + + fn data(&self) -> &[u8] { + match self { + CanFrame::Normal(can_frame_normal) => can_frame_normal.data(), + CanFrame::Rtr(_) => &[], + } + } +} diff --git a/va416xx/va416xx-hal/src/can/ll.rs b/va416xx/va416xx-hal/src/can/ll.rs new file mode 100644 index 0000000..bdb28df --- /dev/null +++ b/va416xx/va416xx-hal/src/can/ll.rs @@ -0,0 +1,318 @@ +use arbitrary_int::{prelude::*, u11, u15, u3, u4}; +use embedded_can::Frame; + +use super::{ + regs::{ + self, BaseId, BufStatusAndControl, BufferState, ExtendedId, MmioCanMessageBuffer, + TwoBytesData, + }, + CanFrame, CanFrameNormal, CanFrameRtr, CanId, InvalidBufferIndexError, +}; + +pub struct CanChannelLowLevel { + id: CanId, + /// Message buffer index. + idx: usize, + msg_buf: MmioCanMessageBuffer<'static>, +} + +impl core::fmt::Debug for CanChannelLowLevel { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + f.debug_struct("CanChannel") + .field("can_id", &self.id) + .field("idx", &self.idx) + .finish() + } +} + +impl CanChannelLowLevel { + /// Steal a low level instance of a CAN channel. + /// + /// # Safety + /// + /// Circumvents ownership and safety guarantees of the HAL. + #[inline] + pub unsafe fn steal(can: CanId, idx: usize) -> Result { + if idx > 14 { + return Err(InvalidBufferIndexError(idx)); + } + let msg_buf = unsafe { can.steal_regs().steal_cmbs_unchecked(idx) }; + Ok(Self { + id: can, + idx, + msg_buf, + }) + } + + /// Steal a low level instance of a CAN channel without and index checks. + /// + /// # Safety + /// + /// Does not perform any bound checks. Passing an invalid index of 15 or higher leads to + /// undefined behaviour. + #[inline] + pub const unsafe fn steal_unchecked(can: CanId, idx: usize) -> Self { + if idx > 14 { + panic!("invalid buffer index for CAN low level channel"); + } + let msg_buf = unsafe { can.steal_regs().steal_cmbs_unchecked(idx) }; + Self { + id: can, + idx, + msg_buf, + } + } + + /// # Safety + /// + /// Allows to create an aribtrary amoutn of driver handles to the same message block, which + /// might lead to data races on invalid usage. + #[inline] + pub const unsafe fn clone(&self) -> Self { + Self { + id: self.id, + idx: self.idx, + msg_buf: unsafe { self.msg_buf.clone() }, + } + } + + pub fn reset(&mut self) { + self.msg_buf.reset(); + } + + #[inline] + pub fn read_state(&self) -> Result { + self.msg_buf.read_stat_ctrl().state() + } + + #[inline] + pub fn write_state(&mut self, buffer_state: BufferState) { + self.msg_buf.modify_stat_ctrl(|mut val| { + val.set_state(buffer_state); + val + }); + } + + pub fn configure_for_transmission(&mut self, tx_priority: Option) { + self.msg_buf.modify_stat_ctrl(|mut val| { + val.set_dlc(u4::new(0)); + if let Some(tx_priority) = tx_priority { + val.set_priority(tx_priority); + } + val.set_state(BufferState::TxNotActive); + val + }); + } + + pub fn set_standard_id(&mut self, standard_id: embedded_can::StandardId, set_rtr: bool) { + let mut id1_reg = standard_id.as_raw() << 5; + if set_rtr { + id1_reg |= 1 << 4; + } + self.msg_buf + .write_id1(BaseId::new_with_raw_value(id1_reg as u32)); + } + + pub fn set_extended_id(&mut self, extended_id: embedded_can::ExtendedId, set_rtr: bool) { + let id_raw = extended_id.as_raw(); + let id1_reg = (((id_raw >> 18) & 0x7FF) << 4) as u16 | ((id_raw >> 15) & 0b111) as u16; + self.msg_buf + .write_id1(BaseId::new_with_raw_value(id1_reg as u32)); + let id0_reg = ((id_raw & 0x7FFF) << 1) as u16 | set_rtr as u16; + self.msg_buf + .write_id0(ExtendedId::new_with_raw_value(id0_reg as u32)); + } + + pub fn configure_for_reception(&mut self) { + self.msg_buf.write_stat_ctrl( + BufStatusAndControl::builder() + .with_dlc(u4::new(0)) + .with_priority(u4::new(0)) + .with_state(BufferState::RxReady) + .build(), + ); + } + + pub fn transmit_frame_unchecked(&mut self, frame: CanFrame) { + let is_remote = frame.is_remote_frame(); + self.write_id(frame.id(), is_remote); + let dlc = frame.dlc(); + self.msg_buf.modify_stat_ctrl(|mut ctrl| { + ctrl.set_dlc(u4::new(dlc as u8)); + ctrl + }); + if !is_remote { + self.msg_buf + .write_data0(TwoBytesData::new_with_raw_value(0)); + self.msg_buf + .write_data1(TwoBytesData::new_with_raw_value(0)); + self.msg_buf + .write_data2(TwoBytesData::new_with_raw_value(0)); + self.msg_buf + .write_data3(TwoBytesData::new_with_raw_value(0)); + for idx in 0..dlc { + match idx { + 0 => self.msg_buf.modify_data0(|mut val| { + val.set_data_upper_byte(frame.data()[idx]); + val + }), + 1 => self.msg_buf.modify_data0(|mut val| { + val.set_data_lower_byte(frame.data()[idx]); + val + }), + 2 => self.msg_buf.modify_data1(|mut val| { + val.set_data_upper_byte(frame.data()[idx]); + val + }), + 3 => self.msg_buf.modify_data1(|mut val| { + val.set_data_lower_byte(frame.data()[idx]); + val + }), + 4 => self.msg_buf.modify_data2(|mut val| { + val.set_data_upper_byte(frame.data()[idx]); + val + }), + 5 => self.msg_buf.modify_data2(|mut val| { + val.set_data_lower_byte(frame.data()[idx]); + val + }), + 6 => self.msg_buf.modify_data3(|mut val| { + val.set_data_upper_byte(frame.data()[idx]); + val + }), + 7 => self.msg_buf.modify_data3(|mut val| { + val.set_data_lower_byte(frame.data()[idx]); + val + }), + _ => unreachable!(), + } + } + } + self.write_state(BufferState::TxOnce); + } + + #[inline] + pub fn clear_interrupt(&mut self) { + let mut regs = unsafe { self.id.steal_regs() }; + let mut clear = regs::InterruptClear::new_with_raw_value(0); + clear.set_buffer(self.idx, true); + regs.write_iclr(clear); + } + + pub fn enable_error_interrupt(&mut self, enable_translation: bool) { + let mut regs = unsafe { self.id.steal_regs() }; + if enable_translation { + regs.modify_icen(|mut val| { + val.set_error(true); + val + }); + } + regs.modify_ien(|mut val| { + val.set_error(true); + val + }); + } + + pub fn enable_interrupt(&mut self, enable_translation: bool) { + let mut regs = unsafe { self.id.steal_regs() }; + if enable_translation { + regs.modify_icen(|mut val| { + val.set_buffer(self.idx, true); + val + }); + } + regs.modify_ien(|mut val| { + val.set_buffer(self.idx, true); + val + }); + } + + fn write_id(&mut self, id: embedded_can::Id, is_remote: bool) { + match id { + embedded_can::Id::Standard(standard_id) => { + self.msg_buf.write_id1( + BaseId::builder() + .with_mask_28_18(u11::new(standard_id.as_raw())) + .with_rtr_or_srr(is_remote) + .with_ide(false) + .with_mask_17_15(u3::new(0)) + .build(), + ); + self.msg_buf.write_id0(ExtendedId::new_with_raw_value(0)); + } + embedded_can::Id::Extended(extended_id) => { + let id_raw = extended_id.as_raw(); + self.msg_buf.write_id1( + BaseId::builder() + .with_mask_28_18(u11::new(((id_raw >> 18) & 0x7FF) as u16)) + .with_rtr_or_srr(true) + .with_ide(true) + .with_mask_17_15(u3::new(((id_raw >> 15) & 0b111) as u8)) + .build(), + ); + self.msg_buf.write_id0( + ExtendedId::builder() + .with_mask_14_0(u15::new((id_raw & 0x7FFF) as u16)) + .with_xrtr(is_remote) + .build(), + ); + } + } + } + + /// Reads a received CAN frame from the message buffer. + /// + /// This function does not check whether the pre-requisites for reading a CAN frame were + /// met and assumes this was already checked by the user. + pub fn read_frame_unchecked(&self) -> CanFrame { + let id0 = self.msg_buf.read_id0(); + let id1 = self.msg_buf.read_id1(); + let data0 = self.msg_buf.read_data0(); + let data1 = self.msg_buf.read_data1(); + let data2 = self.msg_buf.read_data2(); + let data3 = self.msg_buf.read_data3(); + let mut data: [u8; 8] = [0; 8]; + let mut read_data = |dlc: u4| { + (0..dlc.as_usize()).for_each(|i| match i { + 0 => data[i] = data0.data_upper_byte().as_u8(), + 1 => data[i] = data0.data_lower_byte().as_u8(), + 2 => data[i] = data1.data_upper_byte().as_u8(), + 3 => data[i] = data1.data_lower_byte().as_u8(), + 4 => data[i] = data2.data_upper_byte().as_u8(), + 5 => data[i] = data2.data_lower_byte().as_u8(), + 6 => data[i] = data3.data_upper_byte().as_u8(), + 7 => data[i] = data3.data_lower_byte().as_u8(), + _ => unreachable!(), + }); + }; + let (id, rtr) = if !id1.ide() { + let id = embedded_can::Id::Standard( + embedded_can::StandardId::new(id1.mask_28_18().as_u16()).unwrap(), + ); + if id1.rtr_or_srr() { + (id, true) + } else { + (id, false) + } + } else { + let id_raw = (id1.mask_28_18().as_u32() << 18) + | (id1.mask_17_15().as_u32() << 15) + | id0.mask_14_0().as_u32(); + let id = embedded_can::Id::Extended(embedded_can::ExtendedId::new(id_raw).unwrap()); + if id0.xrtr() { + (id, true) + } else { + (id, false) + } + }; + if rtr { + CanFrameRtr::new(id, self.msg_buf.read_stat_ctrl().dlc().as_usize()).into() + } else { + let dlc = self.msg_buf.read_stat_ctrl().dlc(); + read_data(dlc); + CanFrameNormal::new(id, &data[0..dlc.as_usize()]) + .unwrap() + .into() + } + } +} diff --git a/va416xx/va416xx-hal/src/can/mod.rs b/va416xx/va416xx-hal/src/can/mod.rs new file mode 100644 index 0000000..d89f993 --- /dev/null +++ b/va416xx/va416xx-hal/src/can/mod.rs @@ -0,0 +1,834 @@ +//! # CAN peripheral driver. +//! +//! The VA416xx CAN module is based on the CP3UB26 module. +//! +//! Using the CAN bus generally involves the following steps: +//! +//! 1. Create a [Can] instance +//! 2. The [CanChannels] resource management singleton can be retrieved by using +//! [Can::take_channels]. +//! 3. Individual [CanRx] and [CanTx] channels can be created using the [CanChannels::take] +//! function. These allow to send or receive CAN frames on individual channels. +//! 4. The [asynch::CanTxAsync] structure can be created to transmit frames asynchronously. +//! The [asynch::on_interrupt_can] function should be called in the user interrupt handler +//! for CAN0 and CAN1 for this to work properly. The interrupt handler can also take care of +//! receiving frames on [CanRx] channels with enabled interrupts. +//! +//! # Example +//! +//! - [CAN example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/embassy/src/bin/can.rs) +use core::sync::atomic::AtomicBool; + +use arbitrary_int::{prelude::*, u11, u15, u2, u3, u4, u7}; +use embedded_can::Frame; +use ll::CanChannelLowLevel; +use regs::{BaseId, BufferState, Control, MmioCan, TimingConfig}; +use vorago_shared_hal::enable_nvic_interrupt; + +use crate::{clock::Clocks, enable_peripheral_clock, time::Hertz, PeripheralSelect}; +use libm::roundf; + +pub mod frame; +pub use frame::*; + +pub mod asynch; +pub mod ll; +pub mod regs; + +pub const PRESCALER_MIN: u8 = 2; +pub const PRESCALER_MAX: u8 = 128; +/// 1 is the minimum value, but not recommended by Vorago. +pub const TSEG1_MIN: u8 = 1; +pub const TSEG1_MAX: u8 = 16; +pub const TSEG2_MAX: u8 = 8; +/// In addition, SJW may not be larger than TSEG2. +pub const SJW_MAX: u8 = 4; + +pub const MIN_SAMPLE_POINT: f32 = 0.5; +pub const MAX_BITRATE_DEVIATION: f32 = 0.005; + +static CHANNELS_TAKEN: [AtomicBool; 2] = [AtomicBool::new(false), AtomicBool::new(false)]; + +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum CanId { + Can0 = 0, + Can1 = 1, +} + +impl CanId { + /// Steal the register block for the CAN ID. + /// + /// # Safety + /// + /// See safety of the [regs::Can::new_mmio_fixed_0]. + #[inline] + pub const unsafe fn steal_regs(&self) -> regs::MmioCan<'static> { + match self { + CanId::Can0 => unsafe { regs::Can::new_mmio_fixed_0() }, + CanId::Can1 => unsafe { regs::Can::new_mmio_fixed_1() }, + } + } + + #[inline] + pub const fn irq_id(&self) -> va416xx::Interrupt { + match self { + CanId::Can0 => va416xx::Interrupt::CAN0, + CanId::Can1 => va416xx::Interrupt::CAN1, + } + } +} + +/// Sample point between 0 and 1.0 for the given time segments. +pub const fn calculate_sample_point(tseg1: u8, tseg2: u8) -> f32 { + let tseg1_val = tseg1 as f32; + (tseg1_val + 1.0) / (1.0 + tseg1_val + tseg2 as f32) +} + +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct ClockConfig { + prescaler: u8, + tseg1: u8, + tseg2: u8, + sjw: u8, +} + +impl ClockConfig { + /// New clock configuration from the raw configuration values. + /// + /// The values specified here are not the register values, but the actual numerical values + /// relevant for calculations. + /// + /// The values have the following requirements: + /// + /// - Prescaler must be between 2 and 128. + /// - TSEG1 must be smaller than 16 and should be larger than 1. + /// - TSEG2 must be smaller than 8 and small enough so that the calculated sample point + /// is larger than 0.5 (50 %). + /// - SJW (Synchronization Jump Width) must be smaller than the smaller of the time segment + /// configuration values and smaller than 4. + pub fn new(prescaler: u8, tseg1: u8, tseg2: u8, sjw: u8) -> Result { + if !(PRESCALER_MIN..=PRESCALER_MAX).contains(&prescaler.value()) { + return Err(ClockConfigError::CanNotFindPrescaler); + } + if tseg1 == 0 || tseg2 == 0 { + return Err(ClockConfigError::TsegIsZero); + } + if tseg1 > TSEG1_MAX { + return Err(ClockConfigError::InvalidTseg1); + } + if tseg2 > TSEG2_MAX { + return Err(ClockConfigError::InvalidTseg2); + } + let smaller_tseg = core::cmp::min(tseg1.value(), tseg2.value()); + if sjw.value() > smaller_tseg || sjw > SJW_MAX { + return Err(InvalidSjwError(sjw).into()); + } + let sample_point = calculate_sample_point(tseg1, tseg2); + if sample_point < MIN_SAMPLE_POINT { + return Err(InvalidSamplePointError { sample_point }.into()); + } + Ok(Self { + prescaler, + tseg1, + tseg2, + sjw, + }) + } + + /// Calculate the clock configuration for the given input clock, the target bitrate and for a + /// set of timing parameters. The CAN controller uses the APB1 clock. + /// + /// This function basically calculates the necessary prescaler to achieve the given timing + /// parameters. It also performs sanity and validity checks for the calculated prescaler: + /// The bitrate error for the given prescaler needs to be smaller than 0.5 %. + pub fn from_bitrate_and_segments( + clocks: &Clocks, + bitrate: Hertz, + tseg1: u8, + tseg2: u8, + sjw: u8, + ) -> Result { + if bitrate.raw() == 0 { + return Err(ClockConfigError::BitrateIsZero); + } + let nominal_bit_time = 1 + tseg1 as u32 + tseg2 as u32; + let prescaler = + roundf(clocks.apb1().raw() as f32 / (bitrate.raw() as f32 * nominal_bit_time as f32)) + as u32; + if !(PRESCALER_MIN as u32..=PRESCALER_MAX as u32).contains(&prescaler) { + return Err(ClockConfigError::CanNotFindPrescaler); + } + + let actual_bitrate = (clocks.apb1().raw() as f32) / (prescaler * nominal_bit_time) as f32; + let bitrate_deviation = calculate_bitrate_deviation(actual_bitrate, bitrate); + if bitrate_deviation > MAX_BITRATE_DEVIATION { + return Err(ClockConfigError::BitrateErrorTooLarge); + } + // The subtractions are fine because we made checks to avoid underflows. + Self::new(prescaler as u8, tseg1, tseg2, sjw) + } + + #[inline] + pub fn sjw_reg_value(&self) -> u2 { + u2::new(self.sjw.value() - 1) + } + + #[inline] + pub fn tseg1_reg_value(&self) -> u4 { + u4::new(self.tseg1.value() - 1) + } + + #[inline] + pub fn tseg2_reg_value(&self) -> u3 { + u3::new(self.tseg2.value() - 1) + } + + #[inline] + pub fn prescaler_reg_value(&self) -> u7 { + u7::new(self.prescaler.value() - 2) + } +} + +/// Calculate all viable clock configurations for the given input clock, the target bitrate and +/// for a sample point between 0.5 and 1.0. +/// +/// There are various recommendations for the sample point when using the CAN bus. The value +/// depends on different parameters like the bus length and propagation time, as well as +/// the information processing time of the nodes. It should always be at least 50 %. +/// In doubt, select a value like 0.75. +/// +/// - The [Python CAN library](https://python-can.readthedocs.io/en/stable/bit_timing.html) +/// assumes a default value of 69 % as the sample point if none is specified. +/// - CiA-301 recommends 87.5 % +/// - For simpler setups like laboratory setups, smaller values should work as well. +/// +/// A clock configuration is consideres viable when +/// +/// - The sample point deviation is less than 5 %. +/// - The bitrate error is less than +-0.5 %. +/// +/// SJW will be set to either TSEG2 or 4, whichever is smaller. +#[cfg(feature = "alloc")] +pub fn calculate_all_viable_clock_configs( + apb1_clock: Hertz, + bitrate: Hertz, + sample_point: f32, +) -> Result, InvalidSamplePointError> { + if sample_point < 0.5 || sample_point > 1.0 { + return Err(InvalidSamplePointError { sample_point }); + } + let mut configs = alloc::vec::Vec::new(); + for prescaler in PRESCALER_MIN..PRESCALER_MAX { + let nom_bit_time = calculate_nominal_bit_time(apb1_clock, bitrate, prescaler); + // This is taken from the Python CAN library. NBT should not be too small. + if nom_bit_time < 8 { + break; + } + let actual_bitrate = calculate_actual_bitrate(apb1_clock, prescaler, nom_bit_time); + let bitrate_deviation = calculate_bitrate_deviation(actual_bitrate, bitrate); + if bitrate_deviation > 0.05 { + continue; + } + let tseg1 = roundf(sample_point * nom_bit_time as f32) as u32 - 1; + if tseg1 > TSEG1_MAX as u32 || tseg1 < TSEG1_MIN as u32 { + continue; + } + // limit tseg1, so tseg2 is at least 1 TQ + let tseg1 = core::cmp::min(tseg1, nom_bit_time - 2) as u8; + let tseg2 = nom_bit_time - tseg1 as u32 - 1; + if tseg2 > TSEG2_MAX as u32 { + continue; + } + let tseg2 = tseg2 as u8; + let sjw = core::cmp::min(tseg2, 4) as u8; + // Use percent to have a higher resolution for the sample point deviation. + let sample_point_actual = roundf(calculate_sample_point(tseg1, tseg2) * 100.0) as u32; + let sample_point = roundf(sample_point * 100.0) as u32; + let deviation = (sample_point_actual as i32 - sample_point as i32).abs(); + if deviation > 5 { + continue; + } + configs.push(( + ClockConfig { + prescaler, + tseg1, + tseg2, + sjw, + }, + bitrate_deviation, + )); + } + Ok(configs) +} + +#[inline] +pub const fn calculate_nominal_bit_time( + apb1_clock: Hertz, + target_bitrate: Hertz, + prescaler: u8, +) -> u32 { + apb1_clock.raw() / (target_bitrate.raw() * prescaler as u32) +} + +#[inline] +pub const fn calculate_actual_bitrate(apb1_clock: Hertz, prescaler: u8, nom_bit_time: u32) -> f32 { + apb1_clock.raw() as f32 / (prescaler as u32 * nom_bit_time) as f32 +} + +#[inline] +pub const fn calculate_bitrate_deviation(actual_bitrate: f32, target_bitrate: Hertz) -> f32 { + (actual_bitrate - target_bitrate.raw() as f32).abs() / target_bitrate.raw() as f32 +} + +pub trait CanInstance { + const ID: CanId; + const IRQ: va416xx::Interrupt; + const PERIPH_SEL: PeripheralSelect; +} + +impl CanInstance for va416xx::Can0 { + const ID: CanId = CanId::Can0; + const IRQ: va416xx::Interrupt = va416xx::Interrupt::CAN0; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Can0; +} + +impl CanInstance for va416xx::Can1 { + const ID: CanId = CanId::Can1; + const IRQ: va416xx::Interrupt = va416xx::Interrupt::CAN1; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Can1; +} + +#[derive(Debug, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("invalid buffer index {0}")] +pub struct InvalidBufferIndexError(usize); + +#[derive(Debug, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("sjw must be less than or equal to the smaller tseg value")] +pub struct InvalidSjwError(u8); + +#[derive(Debug, thiserror::Error)] +#[error("invalid sample point {sample_point}")] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InvalidSamplePointError { + /// Sample point, should be larger than 0.5 (50 %) but was not. + sample_point: f32, +} + +#[derive(Debug, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClockConfigError { + #[error("invalid sjw: {0}")] + InvalidSjw(#[from] InvalidSjwError), + #[error("TSEG is zero which is not allowed")] + TsegIsZero, + #[error("TSEG1 is larger than 16")] + InvalidTseg1, + #[error("TSEG1 is larger than 8")] + InvalidTseg2, + #[error("invalid sample point: {0}")] + InvalidSamplePoint(#[from] InvalidSamplePointError), + #[error("bitrate is zero")] + BitrateIsZero, + #[error("bitrate error larger than +-0.5 %")] + BitrateErrorTooLarge, + #[error("maximum or minimum allowed prescaler is not sufficient for target bitrate clock")] + CanNotFindPrescaler, +} + +/// The main CAN peripheral driver. +pub struct Can { + regs: regs::MmioCan<'static>, + id: CanId, +} + +impl Can { + pub fn new(_can: CanI, clk_config: ClockConfig) -> Self { + enable_peripheral_clock(CanI::PERIPH_SEL); + let id = CanI::ID; + let mut regs = if id == CanId::Can0 { + unsafe { regs::Can::new_mmio_fixed_0() } + } else { + unsafe { regs::Can::new_mmio_fixed_1() } + }; + // Disable the CAN bus before configuring it. + regs.write_control(Control::new_with_raw_value(0)); + for i in 0..15 { + regs.cmbs(i).unwrap().reset(); + } + regs.write_timing( + TimingConfig::builder() + .with_tseg2(clk_config.tseg2_reg_value()) + .with_tseg1(clk_config.tseg1_reg_value()) + .with_sync_jump_width(clk_config.sjw_reg_value()) + .with_prescaler(clk_config.prescaler_reg_value()) + .build(), + ); + Self { regs, id } + } + + /// This configures the global mask so that acceptance is only determined by an exact match + /// with the ID in the receive message buffers. This is the default reset configuration for + /// the global mask as well. + pub fn set_global_mask_for_exact_id_match(&mut self) { + self.regs + .write_gmskx(regs::ExtendedId::new_with_raw_value(0)); + self.regs.write_gmskb(BaseId::new_with_raw_value(0)); + } + + /// Retrieve a resource management singleton for the 15 CAN channels. + pub fn take_channels(&self) -> Option { + if CHANNELS_TAKEN[self.id() as usize].swap(true, core::sync::atomic::Ordering::SeqCst) { + return None; + } + Some(CanChannels::new(self.id)) + } + + /// Similar to [Self::set_global_mask_for_exact_id_match] but masks the XRTR and RTR/SRR bits. + /// + /// This is useful for when transmitting remote frames with the RTR bit set. The hardware + /// will automatically go into the [regs::BufferState::RxReady] state after the transmission, + /// but the XRTR and RTR/SRR bits need to be masked for the response frame to be accepted + /// on that buffer. + pub fn set_global_mask_for_exact_id_match_with_rtr_masked(&mut self) { + self.regs.write_gmskx( + regs::ExtendedId::builder() + .with_mask_14_0(u15::new(0)) + .with_xrtr(true) + .build(), + ); + self.regs.write_gmskb( + BaseId::builder() + .with_mask_28_18(u11::new(0)) + .with_rtr_or_srr(true) + .with_ide(false) + .with_mask_17_15(u3::new(0)) + .build(), + ); + } + + /// This configures the base mask for buffer 14 so that acceptance is only determined by an + /// exact match with the ID in the receive message buffers. This is the default reset + /// configuration for the global mask as well. + #[inline] + pub fn set_base_mask_for_exact_id_match(&mut self) { + self.regs + .write_bmskx(regs::ExtendedId::new_with_raw_value(0)); + self.regs.write_bmskb(BaseId::new_with_raw_value(0)); + } + + /// This configures the base mask so that all CAN frames which are not handled by any other + /// buffers are accepted by the base buffer 14. + #[inline] + pub fn set_base_mask_for_all_match(&mut self) { + self.regs + .write_bmskx(regs::ExtendedId::new_with_raw_value(0xffff)); + self.regs.write_bmskb(BaseId::new_with_raw_value(0xffff)); + } + + #[inline] + pub fn regs(&mut self) -> &mut MmioCan<'static> { + &mut self.regs + } + + /// Clear all interrupts. + #[inline] + pub fn clear_interrupts(&mut self) { + self.regs + .write_iclr(regs::InterruptClear::new_with_raw_value(0xFFFF_FFFF)); + } + + /// This function only enable the CAN interrupt vector in the NVIC. + /// + /// The interrupts for the individual channels or errors still need to be enabled + /// separately. + #[inline] + pub fn enable_nvic_interrupt(&mut self) { + unsafe { + enable_nvic_interrupt(self.id().irq_id()); + } + } + + #[inline] + pub fn read_error_counters(&self) -> regs::ErrorCounter { + self.regs.read_error_counter() + } + + #[inline] + pub fn read_error_diagnostics(&self) -> regs::DiagnosticRegister { + self.regs.read_diag() + } + + #[inline] + pub fn id(&self) -> CanId { + self.id + } + + #[inline] + pub fn write_ctrl_reg(&mut self, ctrl: Control) { + self.regs.write_control(ctrl); + } + + #[inline] + pub fn modify_control(&mut self, f: F) + where + F: FnOnce(Control) -> Control, + { + self.regs.modify_control(f); + } + + #[inline] + pub fn set_bufflock(&mut self, enable: bool) { + self.regs.modify_control(|mut ctrl| { + ctrl.set_bufflock(enable); + ctrl + }); + } + + #[inline] + pub fn enable(&mut self) { + self.regs.modify_control(|mut ctrl| { + ctrl.set_enable(true); + ctrl + }); + } +} + +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum TxState { + Idle, + TransmittingDataFrame, + TransmittingRemoteFrame, + AwaitingRemoteFrameReply, +} + +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum InvalidTxState { + State(TxState), + BufferState(BufferState), +} + +impl From for InvalidTxState { + fn from(state: TxState) -> Self { + InvalidTxState::State(state) + } +} + +impl From for InvalidTxState { + fn from(state: BufferState) -> Self { + InvalidTxState::BufferState(state) + } +} + +#[derive(Debug, thiserror::Error)] +#[error("invalid tx state {0:?}")] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InvalidTxStateError(pub InvalidTxState); + +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum RxState { + Idle, + Receiving, +} + +#[derive(Debug, thiserror::Error)] +#[error("invalid rx state {0:?}")] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InvalidRxStateError(pub RxState); + +/// Driver instance to use an individual CAN channel as a transmission channel. +#[derive(Debug)] +pub struct CanTx { + ll: CanChannelLowLevel, + mode: TxState, +} + +impl CanTx { + pub fn new(mut ll: CanChannelLowLevel, tx_priority: Option) -> Self { + ll.reset(); + ll.configure_for_transmission(tx_priority); + Self { + ll, + mode: TxState::Idle, + } + } + + #[inline] + pub fn into_rx_channel(self) -> CanRx { + CanRx::new(self.ll) + } + + /// Start transmitting a frame. + /// + /// The frame transmission can be polled/awaited to completion using the [Self::transfer_done] + /// method. + /// + /// This function will return a [state error][InvalidTxStateError] if a transmission is already + /// active and/or the transmit buffer has an invalid state. + pub fn transmit_frame(&mut self, frame: CanFrame) -> Result<(), InvalidTxStateError> { + if self.mode == TxState::AwaitingRemoteFrameReply { + self.ll.configure_for_transmission(None); + self.mode = TxState::Idle; + } + if self.mode != TxState::Idle { + return Err(InvalidTxStateError(self.mode.into())); + } + if !frame.is_remote_frame() { + self.mode = TxState::TransmittingDataFrame; + } else { + self.mode = TxState::TransmittingRemoteFrame; + } + if let Ok(state) = self.ll.read_state() { + if state != BufferState::TxNotActive { + return Err(InvalidTxStateError(state.into())); + } + } + self.ll.transmit_frame_unchecked(frame); + Ok(()) + } + + /// Poll whether an active data frame transmission is done. + /// + /// Returns a [state error][InvalidTxStateError] if no transmission is active. + pub fn transfer_done(&mut self) -> nb::Result<(), InvalidTxStateError> { + if self.mode != TxState::TransmittingDataFrame { + return Err(nb::Error::Other(InvalidTxStateError(self.mode.into()))); + } + let status = self.ll.read_state(); + if status.is_err() { + return Err(nb::Error::WouldBlock); + } + let status = status.unwrap(); + if status == BufferState::TxNotActive { + self.mode = TxState::Idle; + return Ok(()); + } + Err(nb::Error::WouldBlock) + } + + /// Poll whether an active remote frame transmission is done. + /// + /// On success, returns the channel re-configured to a [CanRx] channel. This is because the + /// default behaviour of the hardware will be to re-configure the channel state to + /// [BufferState::RxReady] once the remote frame has been transmitted so that the response + /// frame can be awaited. + /// + /// If the channel should instead be re-configured for transmission again, + /// [Self::remote_transfer_done_with_tx_reconfig] can be used. + /// + /// Returns a [state error][InvalidTxStateError] if no transmission is active. + pub fn remote_transfer_done(&mut self) -> nb::Result { + if self.mode != TxState::TransmittingRemoteFrame { + return Err(nb::Error::Other(InvalidTxStateError(self.mode.into()))); + } + let status = self.ll.read_state(); + if status.is_err() { + return Err(nb::Error::WouldBlock); + } + let status = status.unwrap(); + if status == BufferState::RxReady { + self.mode = TxState::AwaitingRemoteFrameReply; + return Ok(CanRx { + ll: unsafe { self.ll.clone() }, + mode: RxState::Receiving, + }); + } + Err(nb::Error::WouldBlock) + } + + /// Poll whether an active remote frame transmission is done. + /// + /// This function will re-configure the buffer back for transmission once the + /// transmission has completed. + /// + /// Returns a [state error][InvalidTxStateError] if no transmission is active. + pub fn remote_transfer_done_with_tx_reconfig(&mut self) -> nb::Result<(), InvalidTxStateError> { + if self.mode != TxState::TransmittingRemoteFrame { + return Err(nb::Error::Other(InvalidTxStateError(self.mode.into()))); + } + let status = self.ll.read_state(); + if status.is_err() { + return Err(nb::Error::WouldBlock); + } + let status = status.unwrap(); + if status == BufferState::RxReady { + self.ll.write_state(BufferState::TxNotActive); + self.mode = TxState::Idle; + return Ok(()); + } + Err(nb::Error::WouldBlock) + } + + pub fn reset(&mut self) { + self.ll.reset(); + self.mode = TxState::Idle; + } +} + +/// Driver instance to use an individual CAN channel as a reception channel. +pub struct CanRx { + ll: CanChannelLowLevel, + mode: RxState, +} + +impl CanRx { + pub fn new(mut ll: CanChannelLowLevel) -> Self { + ll.reset(); + Self { + ll, + mode: RxState::Idle, + } + } + + #[inline] + pub fn into_tx_channel(self, tx_priority: Option) -> CanTx { + CanTx::new(self.ll, tx_priority) + } + + #[inline] + pub fn enable_interrupt(&mut self, enable_translation: bool) { + self.ll.enable_interrupt(enable_translation); + } + + pub fn configure_for_reception_with_standard_id( + &mut self, + standard_id: embedded_can::StandardId, + set_rtr: bool, + ) { + self.ll.set_standard_id(standard_id, set_rtr); + self.configure_for_reception(); + } + + pub fn configure_for_reception_with_extended_id( + &mut self, + extended_id: embedded_can::ExtendedId, + set_rtr: bool, + ) { + self.ll.set_extended_id(extended_id, set_rtr); + self.configure_for_reception(); + } + + pub fn configure_for_reception(&mut self) { + self.ll.configure_for_reception(); + self.mode = RxState::Receiving; + } + + #[inline] + pub fn frame_available(&self) -> bool { + self.ll + .read_state() + .is_ok_and(|state| state == BufferState::RxFull || state == BufferState::RxOverrun) + } + + /// Poll for frame reception. Returns the frame if one is available. + pub fn receive( + &mut self, + reconfigure_for_reception: bool, + ) -> nb::Result { + if self.mode != RxState::Receiving { + return Err(nb::Error::Other(InvalidRxStateError(self.mode))); + } + let status = self.ll.read_state(); + if status.is_err() { + return Err(nb::Error::WouldBlock); + } + let status = status.unwrap(); + if status == BufferState::RxFull || status == BufferState::RxOverrun { + self.mode = RxState::Idle; + if reconfigure_for_reception { + self.ll.write_state(BufferState::RxReady); + } + return Ok(self.ll.read_frame_unchecked()); + } + Err(nb::Error::WouldBlock) + } +} + +pub struct CanChannels { + id: CanId, + channels: [Option; 15], +} + +impl CanChannels { + const fn new(id: CanId) -> Self { + // Safety: Private function, ownership rules enforced by public API. + unsafe { + Self { + id, + channels: [ + Some(CanChannelLowLevel::steal_unchecked(id, 0)), + Some(CanChannelLowLevel::steal_unchecked(id, 1)), + Some(CanChannelLowLevel::steal_unchecked(id, 2)), + Some(CanChannelLowLevel::steal_unchecked(id, 3)), + Some(CanChannelLowLevel::steal_unchecked(id, 4)), + Some(CanChannelLowLevel::steal_unchecked(id, 5)), + Some(CanChannelLowLevel::steal_unchecked(id, 6)), + Some(CanChannelLowLevel::steal_unchecked(id, 7)), + Some(CanChannelLowLevel::steal_unchecked(id, 8)), + Some(CanChannelLowLevel::steal_unchecked(id, 9)), + Some(CanChannelLowLevel::steal_unchecked(id, 10)), + Some(CanChannelLowLevel::steal_unchecked(id, 11)), + Some(CanChannelLowLevel::steal_unchecked(id, 12)), + Some(CanChannelLowLevel::steal_unchecked(id, 13)), + Some(CanChannelLowLevel::steal_unchecked(id, 14)), + ], + } + } + } + + pub const fn can_id(&self) -> CanId { + self.id + } + + /// Take the indidivual CAN channel low level driver instance. + pub fn take(&mut self, idx: usize) -> Option { + if idx > 14 { + return None; + } + self.channels[idx].take() + } + + pub fn give(&mut self, idx: usize, channel: CanChannelLowLevel) { + if idx > 14 { + panic!("invalid buffer index for CAN channel"); + } + self.channels[idx] = Some(channel); + } +} + +#[cfg(test)] +mod tests { + #[cfg(feature = "alloc")] + use std::println; + + #[cfg(feature = "alloc")] + #[test] + pub fn test_clock_calculator_example_1() { + let configs = super::calculate_all_viable_clock_configs( + crate::time::Hertz::from_raw(50_000_000), + crate::time::Hertz::from_raw(25_000), + 0.75, + ) + .expect("clock calculation failed"); + // Bitrate: 25278.05 Hz. Sample point: 0.7391 + assert_eq!(configs[0].prescaler, 84); + assert_eq!(configs[0].tseg1, 16); + assert_eq!(configs[0].tseg2, 6); + assert_eq!(configs[0].sjw, 4); + // Vorago sample value. + let sample_cfg = configs + .iter() + .find(|c| c.prescaler == 100) + .expect("clock config not found"); + // Slightly different distribution because we use a different sample point, but + // the sum of TSEG1 and TSEG2 is the same as the Vorago example 1. + assert_eq!(sample_cfg.tseg1, 14); + assert_eq!(sample_cfg.tseg2, 5); + } +} diff --git a/va416xx/va416xx-hal/src/can/regs.rs b/va416xx/va416xx-hal/src/can/regs.rs new file mode 100644 index 0000000..aad0a6d --- /dev/null +++ b/va416xx/va416xx-hal/src/can/regs.rs @@ -0,0 +1,380 @@ +//! Custom register definitions for the CAN register block to circumvent PAC API / SVD +//! shortcomings. + +use arbitrary_int::{prelude::*, u11, u15, u2, u3, u4, u6, u7}; + +pub const CAN_0_BASE: usize = 0x4001_4000; +pub const CAN_1_BASE: usize = 0x4001_4400; + +#[derive(Debug, PartialEq, Eq)] +#[bitbybit::bitenum(u4)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum BufferState { + /// Passive channel. + RxNotActive = 0b0000, + /// This condition indicated that SW wrote RxNotActive to a buffer when a data copy + /// process is still active. + RxBusy = 0b0001, + RxReady = 0b0010, + /// Indicated that data is being copied for the first time (RxRead -> RxBusy0). + RxBusy0 = 0b0011, + RxFull = 0b0100, + /// Indicated that data is being copied for the second time (RxFull -> RxBusy2). + RxBusy1 = 0b0101, + RxOverrun = 0b0110, + RxBusy2 = 0b0111, + TxNotActive = 0b1000, + /// Automatical response to a remote frame. + TxRtr = 0b1010, + /// Transmit one frame. + TxOnce = 0b1100, + TxBusy0 = 0b1101, + /// Transmit one frame, and changes to TxRtr after that. This can either be written by + /// software, or it will be written by the hardware after an auto response of the + /// [BufferState::TxRtr] state. + TxOnceRtr = 0b1110, + TxBusy2 = 0b1111, +} + +/// Status control register for individual message buffers. +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))] +pub struct BufStatusAndControl { + /// Data length code. + #[bits(12..=15, rw)] + dlc: u4, + #[bits(4..=7, rw)] + priority: u4, + #[bits(0..=3, rw)] + state: Option, +} + +#[derive(Debug)] +pub struct Timestamp(arbitrary_int::UInt); + +impl Timestamp { + pub fn new(value: u16) -> Self { + Self(value.into()) + } + pub fn value(&self) -> u16 { + self.0.value() as u16 + } + + pub fn write(&mut self, value: u16) { + self.0 = value.into(); + } +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))] +pub struct TwoBytesData { + #[bits(0..=7, rw)] + data_lower_byte: u8, + #[bits(8..=15, rw)] + data_upper_byte: u8, +} + +#[derive(derive_mmio::Mmio)] +#[repr(C)] +pub struct CanMessageBuffer { + stat_ctrl: BufStatusAndControl, + timestamp: Timestamp, + data3: TwoBytesData, + data2: TwoBytesData, + data1: TwoBytesData, + data0: TwoBytesData, + id0: ExtendedId, + id1: BaseId, +} + +static_assertions::const_assert_eq!(core::mem::size_of::(), 0x20); + +impl MmioCanMessageBuffer<'_> { + pub fn reset(&mut self) { + self.write_stat_ctrl(BufStatusAndControl::new_with_raw_value(0)); + self.write_timestamp(Timestamp::new(0)); + self.write_data0(TwoBytesData::new_with_raw_value(0)); + self.write_data1(TwoBytesData::new_with_raw_value(0)); + self.write_data2(TwoBytesData::new_with_raw_value(0)); + self.write_data3(TwoBytesData::new_with_raw_value(0)); + self.write_id1(BaseId::new_with_raw_value(0)); + self.write_id0(ExtendedId::new_with_raw_value(0)); + } +} + +#[bitbybit::bitenum(u1, exhaustive = true)] +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum PinLogicLevel { + DominantIsZero = 0b0, + DominantIsOne = 0b1, +} + +#[bitbybit::bitenum(u1, exhaustive = true)] +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ErrorInterruptType { + /// EIPND bit is set on every error. + EveryError = 0b0, + /// EIPND bit is only set if error state changes as a result of a receive or transmit + /// error counter increment. + ErrorOnRxTxCounterChange = 0b1, +} + +#[bitbybit::bitenum(u1, exhaustive = true)] +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum DataDirection { + FirstByteAtHighestAddr = 0b0, + LastByteAtHighestAddr = 0b1, +} + +#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] +pub struct Control { + #[bit(11, rw)] + error_interrupt_type: ErrorInterruptType, + /// Enables special diagnostics features of the CAN like LO, IGNACK, LOOPBACK, INTERNAL. + #[bit(10, rw)] + diag_enable: bool, + /// CANTX and CANRX pins are internally connected to each other. + #[bit(9, rw)] + internal: bool, + /// All messages sent by the CAN controller can also be received by a CAN buffer with a + /// matching buffer ID. + #[bit(8, rw)] + loopback: bool, + /// IGNACK feature. The CAN does not expect to receive an ACK bit. + #[bit(7, rw)] + ignore_ack: bool, + /// LO feature. The CAN is only configured as a receiver. + #[bit(6, rw)] + listen_only: bool, + #[bit(5, rw)] + data_dir: DataDirection, + #[bit(4, rw)] + timestamp_enable: bool, + #[bit(3, rw)] + bufflock: bool, + #[bit(2, rw)] + tx_logic_level: PinLogicLevel, + #[bit(1, rw)] + rx_logic_level: PinLogicLevel, + #[bit(0, rw)] + enable: bool, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))] +pub struct TimingConfig { + #[bits(0..=2, rw)] + tseg2: u3, + #[bits(3..=6, rw)] + tseg1: u4, + #[bits(7..=8, rw)] + sync_jump_width: u2, + #[bits(9..=15, rw)] + prescaler: u7, +} + +#[bitbybit::bitfield(u32)] +#[derive(Debug)] +pub struct InterruptEnable { + #[bit(15, rw)] + error: bool, + #[bit(0, rw)] + buffer: [bool; 15], +} + +#[bitbybit::bitfield(u32)] +#[derive(Debug)] +pub struct InterruptClear { + #[bit(15, w)] + error: bool, + #[bit(0, w)] + buffer: [bool; 15], +} + +#[bitbybit::bitfield(u32)] +#[derive(Debug)] +pub struct InterruptPending { + #[bit(15, r)] + error: bool, + #[bit(0, r)] + buffer: [bool; 15], +} + +#[derive(Debug)] +#[repr(usize)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum CanInterruptId { + None = 0b00000, + Error = 0b10000, + Buffer(usize), +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct StatusPending { + #[bits(5..=7, r)] + ns: u3, + #[bit(4, r)] + irq: bool, + #[bits(0..=3, r)] + ist: u4, +} + +impl StatusPending { + pub fn interrupt_id(&self) -> Option { + if !self.irq() && self.ist().value() == 0 { + return Some(CanInterruptId::None); + } + + if self.irq() && self.ist().value() == 0 { + return Some(CanInterruptId::Error); + } + if !self.irq() { + return None; + } + Some(CanInterruptId::Buffer(self.ist().as_usize() - 1)) + } +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct ErrorCounter { + #[bits(0..=7, r)] + transmit: u8, + #[bits(8..=15, r)] + receive: u8, +} + +/// This register is unused for standard frames. +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))] +pub struct ExtendedId { + /// Mask for ID bits \[14:0\] of extended frames. + #[bits(1..=15, rw)] + mask_14_0: u15, + /// CAN XRTR bit. + #[bit(0, rw)] + xrtr: bool, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))] +pub struct BaseId { + /// This will contain ID\[10:0\] for standard frames and bits \[28:18\] for extended frames. + #[bits(5..=15, rw)] + mask_28_18: u11, + /// This is the RTR bit for standard frames, and the SRR bit for extended frames. + #[bit(4, rw)] + rtr_or_srr: bool, + /// Identifier extension bit. + #[bit(3, rw)] + ide: bool, + /// Mask for ID bits \[17:15\] of extended frames. + #[bits(0..=2, rw)] + mask_17_15: u3, +} + +#[derive(Debug, PartialEq, Eq)] +#[bitbybit::bitenum(u4, exhaustive = true)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ErrorFieldId { + Error = 0b0000, + ErrorDel = 0b0001, + ErrorEcho = 0b0010, + BusIdle = 0b0011, + Ack = 0b0100, + Eof = 0b0101, + Intermission = 0b0110, + SuspendTransmission = 0b0111, + Sof = 0b1000, + Arbitration = 0b1001, + Ide = 0b1010, + ExtendedArbitration = 0b1011, + R1R0 = 0b1100, + Dlc = 0b1101, + Data = 0b1110, + Crc = 0b1111, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct DiagnosticRegister { + /// Shows the output value on the CAN TX pin at the time of the error. + #[bit(14, r)] + drive: bool, + /// Shows the bus value on the CAN RX pin as sampled by the CAN module at the time of the + /// error. + #[bit(13, r)] + mon: bool, + /// Indicated whether the CRC is invalid. This bit should only be checked if the EFID field + /// is [ErrorFieldId::Ack]. + #[bit(12, r)] + crc: bool, + /// Indicated whether the bit stuffing rule was violated at the time the error occured. + #[bit(11, r)] + stuff: bool, + /// Indicated whether the CAN module was an active transmitter at the time the error occured. + #[bit(10, r)] + txe: bool, + #[bits(4..=9, r)] + ebid: u6, + #[bits(0..=3, r)] + efid: ErrorFieldId, +} + +#[derive(derive_mmio::Mmio)] +#[mmio(const_inner)] +#[repr(C)] +pub struct Can { + #[mmio(Inner)] + cmbs: [CanMessageBuffer; 15], + /// Hidden CAN message buffer. Only allowed to be used internally by the peripheral. + #[mmio(Inner)] + _hcmb: CanMessageBuffer, + control: Control, + timing: TimingConfig, + /// Global mask extension used for buffers 0 to 13. + gmskx: ExtendedId, + /// Global mask base used for buffers 0 to 13. + gmskb: BaseId, + /// Basic mask extension used for buffer 14. + bmskx: ExtendedId, + /// Basic mask base used for buffer 14. + bmskb: BaseId, + ien: InterruptEnable, + #[mmio(PureRead)] + ipnd: InterruptPending, + #[mmio(Write)] + iclr: InterruptClear, + /// Interrupt Code Enable Register. + icen: InterruptEnable, + #[mmio(PureRead)] + status_pending: StatusPending, + #[mmio(PureRead)] + error_counter: ErrorCounter, + #[mmio(PureRead)] + diag: DiagnosticRegister, + #[mmio(PureRead)] + timer: u32, +} + +static_assertions::const_assert_eq!(core::mem::size_of::(), 0x238); + +impl Can { + /// Create a new CAN MMIO instance for peripheral 0. + /// + /// # Safety + /// + /// This API can be used to potentially create a driver to the same peripheral structure + /// from multiple threads. The user must ensure that concurrent accesses are safe and do not + /// interfere with each other. + pub const unsafe fn new_mmio_fixed_0() -> MmioCan<'static> { + Self::new_mmio_at(CAN_0_BASE) + } + + /// Create a new CAN MMIO instance for peripheral 1. + /// + /// # Safety + /// + /// This API can be used to potentially create a driver to the same peripheral structure + /// from multiple threads. The user must ensure that concurrent accesses are safe and do not + /// interfere with each other. + pub const unsafe fn new_mmio_fixed_1() -> MmioCan<'static> { + Self::new_mmio_at(CAN_1_BASE) + } +} diff --git a/va416xx/va416xx-hal/src/clock.rs b/va416xx/va416xx-hal/src/clock.rs new file mode 100644 index 0000000..2f83974 --- /dev/null +++ b/va416xx/va416xx-hal/src/clock.rs @@ -0,0 +1,444 @@ +//! API for using the [crate::pac::Clkgen] peripheral. +//! +//! It also includes functionality to enable the peripheral clocks. +//! Calling [ClockConfigurator::new] returns a builder structure which allows +//! setting up the clock. +//! +//! Calling [ClockConfigurator::freeze] returns the frozen clock configuration inside the [Clocks] +//! structure. This structure can also be used to configure other structures provided by this HAL. +//! +//! # Examples +//! +//! - [UART example on the PEB1 board](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs) +#[cfg(not(feature = "va41628"))] +use crate::adc::ADC_MAX_CLK; +use crate::pac; + +use crate::time::Hertz; +pub use vorago_shared_hal::clock::{Clocks, HBO_FREQ}; +use vorago_shared_hal::{enable_peripheral_clock, PeripheralSelect}; + +pub const XTAL_OSC_TSTART_MS: u32 = 15; + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilterClockSelect { + SysClk = 0, + Clk1 = 1, + Clk2 = 2, + Clk3 = 3, + Clk4 = 4, + Clk5 = 5, + Clk6 = 6, + Clk7 = 7, +} + +/// Refer to chapter 8 (p.57) of the programmers guide for detailed information. +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClockSelect { + // Internal Heart-Beat Osciallator. Not tightly controlled (+/-20 %). Not recommended as the regular clock! + Hbo = 0b00, + // External clock signal on XTAL_N line, 1-100 MHz + XtalN = 0b01, + // Internal Phase-Locked Loop. + Pll = 0b10, + // Crystal oscillator amplified, 4-10 MHz. + XtalOsc = 0b11, +} + +/// This selects the input clock to the the CLKGEN peripheral in addition to the HBO clock. +/// +/// This can either be a clock connected directly on the XTAL_N line or a chrystal on the XTAL_P +/// line which goes through an oscillator amplifier. +/// +/// Refer to chapter 8 (p.57) of the programmers guide for detailed information. +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ReferenceClockSelect { + #[default] + None = 0b00, + XtalOsc = 0b01, + XtalN = 0b10, +} + +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClockDivisorSelect { + #[default] + Div1 = 0b00, + Div2 = 0b01, + Div4 = 0b10, + Div8 = 0b11, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AdcClockDivisorSelect { + Div8 = 0b00, + Div4 = 0b01, + Div2 = 0b10, + Div1 = 0b11, +} + +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct PllConfig { + /// Reference clock divider. + pub clkr: u8, + /// Clock divider on feedback path + pub clkf: u8, + // Output clock divider. + pub clkod: u8, + /// Bandwidth adjustment + pub bwadj: u8, +} + +#[inline] +pub const fn clock_after_division(clk: Hertz, div_sel: ClockDivisorSelect) -> Hertz { + match div_sel { + ClockDivisorSelect::Div1 => clk, + ClockDivisorSelect::Div2 => Hertz::from_raw(clk.raw() / 2), + ClockDivisorSelect::Div4 => Hertz::from_raw(clk.raw() / 4), + ClockDivisorSelect::Div8 => Hertz::from_raw(clk.raw() / 8), + } +} + +/// Wait for 500 reference clock cycles like specified in the datasheet. +pub fn pll_setup_delay() { + for _ in 0..500 { + cortex_m::asm::nop() + } +} + +pub trait ClkgenExt { + fn constrain(self) -> ClockConfigurator; +} + +impl ClkgenExt for pac::Clkgen { + fn constrain(self) -> ClockConfigurator { + ClockConfigurator { + source_clk: None, + ref_clk_sel: ReferenceClockSelect::None, + clksel_sys: ClockSelect::Hbo, + clk_div_sel: ClockDivisorSelect::Div1, + clk_lost_detection: false, + pll_lock_lost_detection: false, + pll_cfg: None, + clkgen: self, + } + } +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct ClockSourceFrequencyNotSet; + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClockConfigError { + ClkSourceFreqNotSet, + PllConfigNotSet, + PllInitError, + InconsistentCfg, +} + +pub struct ClockConfigurator { + ref_clk_sel: ReferenceClockSelect, + clksel_sys: ClockSelect, + clk_div_sel: ClockDivisorSelect, + /// The source clock frequency which is either an external clock connected to XTAL_N, or a + /// crystal connected to the XTAL_OSC input. + source_clk: Option, + pll_cfg: Option, + clk_lost_detection: bool, + /// Feature only works on revision B of the board. + #[cfg(feature = "revb")] + pll_lock_lost_detection: bool, + clkgen: pac::Clkgen, +} + +/// Delays a given amount of milliseconds. +/// +/// Taken from the HAL implementation. This implementation is probably not precise and it +/// also blocks! +pub fn hbo_clock_delay_ms(ms: u32) { + let wdt = unsafe { pac::WatchDog::steal() }; + for _ in 0..ms { + for _ in 0..10_000 { + cortex_m::asm::nop(); + } + wdt.wdogintclr().write(|w| unsafe { w.bits(1) }); + } +} + +impl ClockConfigurator { + /// Create a new clock configuration instance. + pub fn new(clkgen: pac::Clkgen) -> Self { + ClockConfigurator { + source_clk: None, + ref_clk_sel: ReferenceClockSelect::None, + clksel_sys: ClockSelect::Hbo, + clk_div_sel: ClockDivisorSelect::Div1, + clk_lost_detection: false, + pll_lock_lost_detection: false, + pll_cfg: None, + clkgen, + } + } + + /// Steals a new [ClockConfigurator] instance. + /// + /// # Safety + /// + /// Circumvents HAL ownership rules. + pub unsafe fn steal() -> Self { + Self::new(unsafe { pac::Clkgen::steal() }) + } + + #[inline] + pub fn source_clk(mut self, src_clk: Hertz) -> Self { + self.source_clk = Some(src_clk); + self + } + + /// This function can be used to utilize the XTAL_N clock input directly without the + /// oscillator. + /// + /// It sets the internal configuration to [ClkselSys::XtalN] and [RefClkSel::XtalN]. + #[inline] + pub fn xtal_n_clk(mut self) -> Self { + self.clksel_sys = ClockSelect::XtalN; + self.ref_clk_sel = ReferenceClockSelect::XtalN; + self + } + + #[inline] + pub fn xtal_n_clk_with_src_freq(mut self, src_clk: Hertz) -> Self { + self = self.xtal_n_clk(); + self.source_clk(src_clk) + } + + #[inline] + pub fn clksel_sys(mut self, clksel_sys: ClockSelect) -> Self { + self.clksel_sys = clksel_sys; + self + } + + #[inline] + pub fn pll_cfg(mut self, pll_cfg: PllConfig) -> Self { + self.pll_cfg = Some(pll_cfg); + self + } + + #[inline] + pub fn ref_clk_sel(mut self, ref_clk_sel: ReferenceClockSelect) -> Self { + self.ref_clk_sel = ref_clk_sel; + self + } + + /// Configures all clocks and return a clock configuration structure containing the final + /// frozen clocks. + /// + /// Internal implementation details: This implementation is based on the HAL implementation + /// which performs a lot of delays. I do not know if all of those are necessary, but + /// I am going to be conservative here and assume that the vendor has tested though and + /// might have had a reason for those, so I am going to keep them. Chances are, this + /// process only has to be performed once, and it does not matter if it takes a few + /// microseconds or milliseconds longer. + pub fn freeze(self) -> Result { + // Sanitize configuration. + if self.source_clk.is_none() { + return Err(ClockConfigError::ClkSourceFreqNotSet); + } + if self.clksel_sys == ClockSelect::XtalOsc + && self.ref_clk_sel != ReferenceClockSelect::XtalOsc + { + return Err(ClockConfigError::InconsistentCfg); + } + if self.clksel_sys == ClockSelect::XtalN && self.ref_clk_sel != ReferenceClockSelect::XtalN + { + return Err(ClockConfigError::InconsistentCfg); + } + if self.clksel_sys == ClockSelect::Pll && self.pll_cfg.is_none() { + return Err(ClockConfigError::PllConfigNotSet); + } + + enable_peripheral_clock(PeripheralSelect::Clkgen); + let mut final_sysclk = self.source_clk.unwrap(); + // The HAL forces back the HBO clock here with a delay.. Even though this is + // not stricly necessary when coming from a fresh start, it could be still become relevant + // later if the clock lost detection mechanism require a re-configuration of the clocks. + // Therefore, we do it here as well. + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clksel_sys().bits(ClockSelect::Hbo as u8) }); + pll_setup_delay(); + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clk_div_sel().bits(ClockDivisorSelect::Div1 as u8) }); + + // Set up oscillator and PLL input clock. + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.ref_clk_sel().bits(self.ref_clk_sel as u8) }); + self.clkgen.ctrl1().modify(|_, w| { + w.xtal_en().clear_bit(); + w.xtal_n_en().clear_bit(); + w + }); + match self.ref_clk_sel { + ReferenceClockSelect::None => pll_setup_delay(), + ReferenceClockSelect::XtalOsc => { + self.clkgen.ctrl1().modify(|_, w| w.xtal_en().set_bit()); + hbo_clock_delay_ms(XTAL_OSC_TSTART_MS); + } + ReferenceClockSelect::XtalN => { + self.clkgen.ctrl1().modify(|_, w| w.xtal_n_en().set_bit()); + pll_setup_delay() + } + } + + // Set up PLL configuration. + match self.pll_cfg { + Some(cfg) => { + self.clkgen.ctrl0().modify(|_, w| w.pll_pwdn().clear_bit()); + // Done in C HAL. I guess this gives the PLL some time to power down properly. + cortex_m::asm::nop(); + cortex_m::asm::nop(); + self.clkgen.ctrl0().modify(|_, w| { + unsafe { + w.pll_clkf().bits(cfg.clkf); + } + unsafe { + w.pll_clkr().bits(cfg.clkr); + } + unsafe { + w.pll_clkod().bits(cfg.clkod); + } + unsafe { + w.pll_bwadj().bits(cfg.bwadj); + } + w.pll_test().clear_bit(); + w.pll_bypass().clear_bit(); + w.pll_intfb().set_bit() + }); + // Taken from SystemCoreClockUpdate implementation from Vorago. + final_sysclk /= cfg.clkr as u32 + 1; + final_sysclk *= cfg.clkf as u32 + 1; + final_sysclk /= cfg.clkod as u32 + 1; + + // Reset PLL. + self.clkgen.ctrl0().modify(|_, w| w.pll_reset().set_bit()); + // The HAL does this, the datasheet specifies a delay of 5 us. I guess it does not + // really matter because the PLL lock detect is used later.. + pll_setup_delay(); + self.clkgen.ctrl0().modify(|_, w| w.pll_reset().clear_bit()); + pll_setup_delay(); + + // check for lock + let stat = self.clkgen.stat().read(); + if stat.fbslip().bit() || stat.rfslip().bit() { + pll_setup_delay(); + if stat.fbslip().bit() || stat.rfslip().bit() { + // This is what the HAL does. We could continue, but then we would at least + // have to somehow report a partial error.. Chances are, the user does not + // want to continue with a broken PLL clock. + return Err(ClockConfigError::PllInitError); + } + } + } + None => { + self.clkgen.ctrl0().modify(|_, w| w.pll_pwdn().set_bit()); + } + } + + if self.clk_lost_detection { + rearm_sysclk_lost_with_periph(&self.clkgen) + } + #[cfg(feature = "revb")] + if self.pll_lock_lost_detection { + rearm_pll_lock_lost_with_periph(&self.clkgen) + } + + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clk_div_sel().bits(self.clk_div_sel as u8) }); + final_sysclk = clock_after_division(final_sysclk, self.clk_div_sel); + + // The HAL does this. I don't know why.. + pll_setup_delay(); + + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clksel_sys().bits(self.clksel_sys as u8) }); + + Ok(Clocks::__new( + final_sysclk, + #[cfg(not(feature = "va41628"))] + self.cfg_adc_clk_div(final_sysclk), + )) + } + + #[cfg(not(feature = "va41628"))] + fn cfg_adc_clk_div(&self, final_sysclk: Hertz) -> Hertz { + // I will just do the ADC stuff like Vorago does it. + // ADC clock (must be 2-12.5 MHz) + // NOTE: Not using divide by 1 or /2 ratio in REVA silicon because of triggering issue + // For this reason, keep SYSCLK above 8MHz to have the ADC /4 ratio in range) + if final_sysclk.raw() <= ADC_MAX_CLK.raw() * 4 { + self.clkgen.ctrl1().modify(|_, w| unsafe { + w.adc_clk_div_sel().bits(AdcClockDivisorSelect::Div4 as u8) + }); + final_sysclk / 4 + } else { + self.clkgen.ctrl1().modify(|_, w| unsafe { + w.adc_clk_div_sel().bits(AdcClockDivisorSelect::Div8 as u8) + }); + final_sysclk / 8 + } + } +} + +pub fn rearm_sysclk_lost() { + rearm_sysclk_lost_with_periph(&unsafe { pac::Clkgen::steal() }) +} + +fn rearm_sysclk_lost_with_periph(clkgen: &pac::Clkgen) { + clkgen + .ctrl0() + .modify(|_, w| w.sys_clk_lost_det_en().set_bit()); + clkgen + .ctrl1() + .write(|w| w.sys_clk_lost_det_rearm().set_bit()); + clkgen + .ctrl1() + .write(|w| w.sys_clk_lost_det_rearm().clear_bit()); +} + +#[cfg(feature = "revb")] +pub fn rearm_pll_lock_lost() { + rearm_pll_lock_lost_with_periph(&unsafe { pac::Clkgen::steal() }) +} + +fn rearm_pll_lock_lost_with_periph(clkgen: &pac::Clkgen) { + clkgen + .ctrl1() + .modify(|_, w| w.pll_lost_lock_det_en().set_bit()); + clkgen.ctrl1().write(|w| w.pll_lck_det_rearm().set_bit()); + clkgen.ctrl1().write(|w| w.pll_lck_det_rearm().clear_bit()); +} + +#[cfg(test)] +mod tests { + + use super::*; + + #[test] + fn test_basic_div() { + assert_eq!( + clock_after_division(Hertz::from_raw(10_000_000), super::ClockDivisorSelect::Div2), + Hertz::from_raw(5_000_000) + ); + } +} diff --git a/va416xx/va416xx-hal/src/dac.rs b/va416xx/va416xx-hal/src/dac.rs new file mode 100644 index 0000000..e85881f --- /dev/null +++ b/va416xx/va416xx-hal/src/dac.rs @@ -0,0 +1,159 @@ +//! Digital to Analog Converter (DAC) driver. +//! +//! ## Examples +//! +//! - [ADC and DAC example](https://github.com/us-irs/va416xx-rs/blob/main/examples/simple/examples/dac-adc.rs) +use core::ops::Deref; + +use vorago_shared_hal::{ + disable_peripheral_clock, enable_peripheral_clock, reset_peripheral_for_cycles, + PeripheralSelect, +}; + +use crate::{clock::Clocks, pac}; + +pub type DacRegisterBlock = pac::dac0::RegisterBlock; + +/// Common trait implemented by all PAC peripheral access structures. The register block +/// format is the same for all DAC blocks. +pub trait DacInstance: Deref { + const IDX: u8; + + fn ptr() -> *const DacRegisterBlock; +} + +impl DacInstance for pac::Dac0 { + const IDX: u8 = 0; + + #[inline(always)] + fn ptr() -> *const DacRegisterBlock { + Self::ptr() + } +} + +impl DacInstance for pac::Dac1 { + const IDX: u8 = 1; + + #[inline(always)] + fn ptr() -> *const DacRegisterBlock { + Self::ptr() + } +} + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum DacSettling { + NoSettling = 0, + Apb2Times25 = 1, + Apb2Times50 = 2, + Apb2Times75 = 3, + Apb2Times100 = 4, + Apb2Times125 = 5, + Apb2Times150 = 6, +} + +pub struct Dac(*const DacRegisterBlock); + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct ValueTooLarge; + +impl Dac { + /// Create a new [Dac] driver instance. + /// + /// The [Clocks] structure is expected here as well to ensure the clock was set up properly. + pub fn new(dac: Dac, dac_settling: DacSettling, _clocks: &Clocks) -> Self { + enable_peripheral_clock(PeripheralSelect::Dac); + + dac.ctrl1().write(|w| { + w.dac_en().set_bit(); + // SAFETY: Enum values are valid values only. + unsafe { w.dac_settling().bits(dac_settling as u8) } + }); + let mut dac = Self(Dac::ptr()); + dac.clear_fifo(); + dac.clear_irqs(); + dac + } + + pub const fn regs(&self) -> &DacRegisterBlock { + unsafe { &*self.0 } + } + + #[inline(always)] + pub fn clear_irqs(&mut self) { + self.regs().irq_clr().write(|w| { + w.fifo_oflow().set_bit(); + w.fifo_uflow().set_bit(); + w.dac_done().set_bit(); + w.trig_error().set_bit() + }); + } + + #[inline(always)] + pub fn clear_fifo(&mut self) { + self.regs().fifo_clr().write(|w| unsafe { w.bits(1) }); + } + + /// Load next value into the FIFO. + /// + /// Uses the [nb] API to allow blocking and non-blocking usage. + #[inline(always)] + pub fn load_value(&mut self, val: u16) -> nb::Result<(), ValueTooLarge> { + if val > 2_u16.pow(12) - 1 { + return Err(nb::Error::Other(ValueTooLarge)); + } + let regs = self.regs(); + if regs.status().read().fifo_entry_cnt().bits() >= 32_u8 { + return Err(nb::Error::WouldBlock); + } + regs.fifo_data().write(|w| unsafe { w.bits(val.into()) }); + Ok(()) + } + + /// This loads and triggers the next value immediately. It also clears the FIFO before + /// loading the passed value. + #[inline(always)] + pub fn load_and_trigger_manually(&mut self, val: u16) -> Result<(), ValueTooLarge> { + if val > 2_u16.pow(12) - 1 { + return Err(ValueTooLarge); + } + self.clear_fifo(); + // This should never block, the FIFO was cleared. We checked the value as well, so unwrap + // is okay here. + nb::block!(self.load_value(val)).unwrap(); + self.trigger_manually(); + Ok(()) + } + + /// Manually trigger the DAC. This will de-queue the next value inside the FIFO + /// to be processed by the DAC. + #[inline(always)] + pub fn trigger_manually(&self) { + self.regs().ctrl0().write(|w| w.man_trig_en().set_bit()); + } + + #[inline(always)] + pub fn enable_external_trigger(&self) { + self.regs().ctrl0().write(|w| w.ext_trig_en().set_bit()); + } + + pub fn is_settled(&self) -> nb::Result<(), ()> { + if self.regs().status().read().dac_busy().bit_is_set() { + return Err(nb::Error::WouldBlock); + } + Ok(()) + } + + #[inline(always)] + pub fn reset(&mut self) { + enable_peripheral_clock(PeripheralSelect::Dac); + reset_peripheral_for_cycles(PeripheralSelect::Dac, 2); + } + + /// Stops the DAC, which disables its peripheral clock. + #[inline(always)] + pub fn stop(self) { + disable_peripheral_clock(PeripheralSelect::Dac); + } +} diff --git a/va416xx/va416xx-hal/src/dma.rs b/va416xx/va416xx-hal/src/dma.rs new file mode 100644 index 0000000..6afb4bc --- /dev/null +++ b/va416xx/va416xx-hal/src/dma.rs @@ -0,0 +1,577 @@ +//! API for the DMA peripheral +//! +//! ## Examples +//! +//! - [Simple DMA example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/dma.rs) +use arbitrary_int::{u10, u3}; +use vorago_shared_hal::{enable_peripheral_clock, reset_peripheral_for_cycles, PeripheralSelect}; + +use crate::{enable_nvic_interrupt, pac}; + +const MAX_DMA_TRANSFERS_PER_CYCLE: usize = 1024; +const BASE_PTR_ADDR_MASK: u32 = 0b1111111; + +/// DMA cycle control values. +/// +/// Refer to chapter 6.3.1 and 6.6.3 of the datasheet for more details. +#[bitbybit::bitenum(u3, exhaustive = true)] +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[repr(u8)] +pub enum CycleControl { + /// Indicates that the data structure is invalid. + Stop = 0b000, + /// The controller must receive a new request prior to entering the arbitration + /// process, to enable the DMA cycle to complete. This means that the DMA will only + /// continue to do transfers as long as a trigger signal is still active. Therefore, + /// this should not be used for momentary triggers like a timer. + Basic = 0b001, + /// The controller automatically inserts a request for the appropriate channel during the + /// arbitration process. This means that the initial request is sufficient to enable the + /// DMA cycle to complete. + Auto = 0b010, + /// This is used to support continuous data flow. Both primary and alternate data structure + /// are used. The primary data structure is used first. When the first transfer is complete, an + /// interrupt can be generated, and the DMA switches to the alternate data structure. When the + /// second transfer is complete, the primary data structure is used. This pattern continues + /// until software disables the channel. + PingPong = 0b011, + MemScatterGatherPrimary = 0b100, + MemScatterGatherAlternate = 0b101, + PeriphScatterGatherPrimary = 0b110, + PeriphScatterGatherAlternate = 0b111, +} + +#[bitbybit::bitenum(u2, exhaustive = true)] +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AddrIncrement { + Byte = 0b00, + Halfword = 0b01, + Word = 0b10, + None = 0b11, +} + +#[bitbybit::bitenum(u2, exhaustive = false)] +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum DataSize { + Byte = 0b00, + Halfword = 0b01, + Word = 0b10, +} + +/// This configuration controls how many DMA transfers can occur before the controller arbitrates. +#[bitbybit::bitenum(u4, exhaustive = true)] +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum RPower { + EachTransfer = 0b0000, + Every2 = 0b0001, + Every4 = 0b0010, + Every8 = 0b0011, + Every16 = 0b0100, + Every32 = 0b0101, + Every64 = 0b0110, + Every128 = 0b0111, + Every256 = 0b1000, + Every512 = 0b1001, + Every1024 = 0b1010, + Every1024Alt0 = 0b1011, + Every1024Alt1 = 0b1100, + Every1024Alt2 = 0b1101, + Every1024Alt3 = 0b1110, + Every1024Alt4 = 0b1111, +} + +#[derive(Debug, PartialEq, Eq, thiserror::Error)] +#[error("Invalid DMA control block address")] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InvalidCtrlBlockAddrError; + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))] +pub struct ChannelConfig { + #[bits(30..=31, rw)] + dst_inc: AddrIncrement, + #[bits(28..=29, rw)] + dst_size: Option, + #[bits(26..=27, rw)] + src_inc: AddrIncrement, + #[bits(24..=25, rw)] + src_size: Option, + #[bits(21..=23, rw)] + dest_prot_ctrl: u3, + #[bits(18..=20, rw)] + src_prot_ctrl: u3, + #[bits(14..=17, rw)] + r_power: RPower, + #[bits(4..=13, rw)] + n_minus_1: u10, + #[bit(3, rw)] + next_useburst: bool, + #[bits(0..=2, rw)] + cycle_ctrl: CycleControl, +} + +#[repr(C)] +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct DmaChannelControl { + pub src_end_ptr: u32, + pub dest_end_ptr: u32, + pub cfg: ChannelConfig, + padding: u32, +} + +impl DmaChannelControl { + const fn new() -> Self { + Self { + src_end_ptr: 0, + dest_end_ptr: 0, + cfg: ChannelConfig::new_with_raw_value(0), + padding: 0, + } + } +} +impl Default for DmaChannelControl { + fn default() -> Self { + Self::new() + } +} +#[repr(C)] +#[repr(align(128))] +pub struct DmaCtrlBlock { + pub pri: [DmaChannelControl; 4], + pub alt: [DmaChannelControl; 4], +} + +impl DmaCtrlBlock { + pub const fn new() -> Self { + Self { + pri: [DmaChannelControl::new(); 4], + alt: [DmaChannelControl::new(); 4], + } + } +} +impl Default for DmaCtrlBlock { + fn default() -> Self { + Self::new() + } +} + +impl DmaCtrlBlock { + /// This function creates a DMA control block at the specified memory address. + /// + /// The passed address must be 128-byte aligned. The user must also take care of specifying + /// a valid memory address for the DMA control block which is accessible by the system as well. + /// For example, the control block can be placed in the SRAM1. + pub fn new_at_addr(addr: u32) -> Result<*mut DmaCtrlBlock, InvalidCtrlBlockAddrError> { + if addr & BASE_PTR_ADDR_MASK > 0 { + return Err(InvalidCtrlBlockAddrError); + } + let ctrl_block_ptr = addr as *mut DmaCtrlBlock; + unsafe { core::ptr::write(ctrl_block_ptr, DmaCtrlBlock::default()) } + Ok(ctrl_block_ptr) + } +} + +pub struct Dma { + dma: pac::Dma, + ctrl_block: *mut DmaCtrlBlock, +} + +#[derive(Debug, Clone, Copy, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum DmaTransferInitError { + #[error("source and destination buffer length mismatch: {src_len} != {dest_len}")] + SourceDestLenMissmatch { src_len: usize, dest_len: usize }, + /// Overflow when calculating the source or destination end address. + #[error("address overflow")] + AddrOverflow, + /// Transfer size larger than 1024 units. + #[error("transfer size too large: {0}, 1024 is the allowed maximum")] + TransferSizeTooLarge(usize), +} + +#[derive(Debug, Clone, Copy, Default)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct DmaConfig { + pub bufferable: bool, + pub cacheable: bool, + pub privileged: bool, +} + +pub struct DmaChannel { + channel: u8, + done_interrupt: pac::Interrupt, + active_interrupt: pac::Interrupt, + pub dma: pac::Dma, + pub ch_ctrl_pri: &'static mut DmaChannelControl, + pub ch_ctrl_alt: &'static mut DmaChannelControl, +} + +impl DmaChannel { + #[inline(always)] + pub fn channel(&self) -> u8 { + self.channel + } + + #[inline(always)] + pub fn enable(&mut self) { + self.dma + .chnl_enable_set() + .write(|w| unsafe { w.bits(1 << self.channel) }); + } + + #[inline(always)] + pub fn is_enabled(&mut self) -> bool { + ((self.dma.chnl_enable_set().read().bits() >> self.channel) & 0b1) != 0 + } + + #[inline(always)] + pub fn disable(&mut self) { + self.dma + .chnl_enable_clr() + .write(|w| unsafe { w.bits(1 << self.channel) }); + } + + #[inline(always)] + pub fn trigger_with_sw_request(&mut self) { + self.dma + .chnl_sw_request() + .write(|w| unsafe { w.bits(1 << self.channel) }); + } + + #[inline(always)] + pub fn state_raw(&self) -> u8 { + self.dma.status().read().state().bits() + } + + #[inline(always)] + pub fn select_primary_structure(&self) { + self.dma + .chnl_pri_alt_clr() + .write(|w| unsafe { w.bits(1 << self.channel) }); + } + + #[inline(always)] + pub fn select_alternate_structure(&self) { + self.dma + .chnl_pri_alt_set() + .write(|w| unsafe { w.bits(1 << self.channel) }); + } + + /// Enables the DMA_DONE interrupt for the DMA channel. + /// + /// # Safety + /// + /// This function is `unsafe` because it can break mask-based critical sections. + pub unsafe fn enable_done_interrupt(&mut self) { + enable_nvic_interrupt(self.done_interrupt); + } + + /// Enables the DMA_ACTIVE interrupt for the DMA channel. + /// + /// # Safety + /// + /// This function is `unsafe` because it can break mask-based critical sections. + pub unsafe fn enable_active_interrupt(&mut self) { + enable_nvic_interrupt(self.active_interrupt); + } + + /// Prepares a 8-bit DMA transfer from memory to memory. + /// + /// This function does not enable the DMA channel and interrupts and only prepares + /// the DMA control block parameters for the transfer. It configures the primary channel control + /// structure to perform the transfer. + /// + /// You can use [Self::enable], [Self::enable_done_interrupt], [Self::enable_active_interrupt] + /// to finish the transfer preparation and then use [Self::trigger_with_sw_request] to + /// start the DMA transfer. + /// + /// # Safety + /// + /// You must ensure that the destination buffer is safe for DMA writes and the source buffer + /// is safe for DMA reads. The specific requirements can be read here: + /// + /// - [DMA source buffer](https://docs.rs/embedded-dma/latest/embedded_dma/trait.ReadBuffer.html) + /// - [DMA destination buffer](https://docs.rs/embedded-dma/latest/embedded_dma/trait.WriteBuffer.html) + /// + /// More specifically, you must ensure that the passed slice remains valid while the DMA is + /// active or until the DMA is stopped. + pub unsafe fn prepare_mem_to_mem_transfer_8_bit( + &mut self, + source: &[u8], + dest: &mut [u8], + ) -> Result<(), DmaTransferInitError> { + let len = Self::common_mem_transfer_checks(source.len(), dest.len())?; + self.generic_mem_to_mem_transfer_init( + len, + (source.as_ptr() as u32) + .checked_add(len as u32) + .ok_or(DmaTransferInitError::AddrOverflow)?, + (dest.as_ptr() as u32) + .checked_add(len as u32) + .ok_or(DmaTransferInitError::AddrOverflow)?, + DataSize::Byte, + AddrIncrement::Byte, + ); + Ok(()) + } + + /// Prepares a 16-bit DMA transfer from memory to memory. + /// + /// This function does not enable the DMA channel and interrupts and only prepares + /// the DMA control block parameters for the transfer. It configures the primary channel control + /// structure to perform the transfer. + /// + /// You can use [Self::enable], [Self::enable_done_interrupt], [Self::enable_active_interrupt] + /// to finish the transfer preparation and then use [Self::trigger_with_sw_request] to + /// start the DMA transfer. + /// + /// # Safety + /// + /// You must ensure that the destination buffer is safe for DMA writes and the source buffer + /// is safe for DMA reads. The specific requirements can be read here: + /// + /// - [DMA source buffer](https://docs.rs/embedded-dma/latest/embedded_dma/trait.ReadBuffer.html) + /// - [DMA destination buffer](https://docs.rs/embedded-dma/latest/embedded_dma/trait.WriteBuffer.html) + /// + /// More specifically, you must ensure that the passed slice remains valid while the DMA is + /// active or until the DMA is stopped. + pub unsafe fn prepare_mem_to_mem_transfer_16_bit( + &mut self, + source: &[u16], + dest: &mut [u16], + ) -> Result<(), DmaTransferInitError> { + let len = Self::common_mem_transfer_checks(source.len(), dest.len())?; + self.generic_mem_to_mem_transfer_init( + len, + (source.as_ptr() as u32) + .checked_add(len as u32 * core::mem::size_of::() as u32) + .ok_or(DmaTransferInitError::AddrOverflow)?, + (dest.as_ptr() as u32) + .checked_add(len as u32 * core::mem::size_of::() as u32) + .ok_or(DmaTransferInitError::AddrOverflow)?, + DataSize::Halfword, + AddrIncrement::Halfword, + ); + Ok(()) + } + + /// Prepares a 32-bit DMA transfer from memory to memory. + /// + /// This function does not enable the DMA channel and interrupts and only prepares + /// the DMA control block parameters for the transfer. It configures the primary channel control + /// structure to perform the transfer. + /// + /// You can use [Self::enable], [Self::enable_done_interrupt], [Self::enable_active_interrupt] + /// to finish the transfer preparation and then use [Self::trigger_with_sw_request] to + /// start the DMA transfer. + /// + /// # Safety + /// + /// You must ensure that the destination buffer is safe for DMA writes and the source buffer + /// is safe for DMA reads. The specific requirements can be read here: + /// + /// - [DMA source buffer](https://docs.rs/embedded-dma/latest/embedded_dma/trait.ReadBuffer.html) + /// - [DMA destination buffer](https://docs.rs/embedded-dma/latest/embedded_dma/trait.WriteBuffer.html) + /// + /// More specifically, you must ensure that the passed slice remains valid while the DMA is + /// active or until the DMA is stopped. + pub unsafe fn prepare_mem_to_mem_transfer_32_bit( + &mut self, + source: &[u32], + dest: &mut [u32], + ) -> Result<(), DmaTransferInitError> { + let len = Self::common_mem_transfer_checks(source.len(), dest.len())?; + self.generic_mem_to_mem_transfer_init( + len, + (source.as_ptr() as u32) + .checked_add(len as u32 * core::mem::size_of::() as u32) + .ok_or(DmaTransferInitError::AddrOverflow)?, + (dest.as_ptr() as u32) + .checked_add(len as u32 * core::mem::size_of::() as u32) + .ok_or(DmaTransferInitError::AddrOverflow)?, + DataSize::Word, + AddrIncrement::Word, + ); + Ok(()) + } + + /// Prepares a 8-bit DMA transfer from memory to a peripheral. + /// + /// It is assumed that a peripheral with a 16-byte FIFO is used here and that the + /// transfer is activated by an IRQ trigger when the half-full interrupt of the peripheral + /// is fired. Therefore, this function configured the DMA in [CycleControl::Basic] mode with + /// rearbitration happening every 8 DMA cycles. It also configures the primary channel control + /// structure to perform the transfer. + /// + /// # Safety + /// + /// You must ensure that the source buffer is safe for DMA reads. The specific requirements + /// can be read here: + /// + /// - [DMA source buffer](https://docs.rs/embedded-dma/latest/embedded_dma/trait.ReadBuffer.html) + /// + /// More specifically, you must ensure that the passed slice remains valid while the DMA is + /// active or until the DMA is stopped. + /// + /// The destination address must be the pointer address of a peripheral FIFO register address. + /// You must also ensure that the regular synchronous transfer API of the peripheral is NOT + /// used to perform transfers. + pub unsafe fn prepare_mem_to_periph_transfer_8_bit( + &mut self, + source: &[u8], + dest: *mut u32, + ) -> Result<(), DmaTransferInitError> { + if source.len() > MAX_DMA_TRANSFERS_PER_CYCLE { + return Err(DmaTransferInitError::TransferSizeTooLarge(source.len())); + } + let len = source.len() - 1; + self.ch_ctrl_pri.cfg = ChannelConfig::new_with_raw_value(0); + self.ch_ctrl_pri.src_end_ptr = (source.as_ptr() as u32) + .checked_add(len as u32) + .ok_or(DmaTransferInitError::AddrOverflow)?; + self.ch_ctrl_pri.dest_end_ptr = dest as u32; + self.ch_ctrl_pri.cfg.set_cycle_ctrl(CycleControl::Basic); + self.ch_ctrl_pri.cfg.set_src_size(DataSize::Byte); + self.ch_ctrl_pri.cfg.set_src_inc(AddrIncrement::Byte); + self.ch_ctrl_pri.cfg.set_dst_size(DataSize::Byte); + self.ch_ctrl_pri.cfg.set_dst_inc(AddrIncrement::None); + self.ch_ctrl_pri.cfg.set_n_minus_1(u10::new(len as u16)); + self.ch_ctrl_pri.cfg.set_r_power(RPower::Every8); + self.select_primary_structure(); + Ok(()) + } + + // This function performs common checks and returns the source length minus one which is + // relevant for further configuration of the DMA. This is because the DMA API expects N minus + // 1 and the source and end pointer need to point to the last transfer address. + fn common_mem_transfer_checks( + src_len: usize, + dest_len: usize, + ) -> Result { + if src_len != dest_len { + return Err(DmaTransferInitError::SourceDestLenMissmatch { src_len, dest_len }); + } + if src_len > MAX_DMA_TRANSFERS_PER_CYCLE { + return Err(DmaTransferInitError::TransferSizeTooLarge(src_len)); + } + Ok(src_len - 1) + } + + fn generic_mem_to_mem_transfer_init( + &mut self, + n_minus_one: usize, + src_end_ptr: u32, + dest_end_ptr: u32, + data_size: DataSize, + addr_incr: AddrIncrement, + ) { + self.ch_ctrl_pri.cfg = ChannelConfig::new_with_raw_value(0); + self.ch_ctrl_pri.src_end_ptr = src_end_ptr; + self.ch_ctrl_pri.dest_end_ptr = dest_end_ptr; + self.ch_ctrl_pri.cfg.set_cycle_ctrl(CycleControl::Auto); + self.ch_ctrl_pri.cfg.set_src_size(data_size); + self.ch_ctrl_pri.cfg.set_src_inc(addr_incr); + self.ch_ctrl_pri.cfg.set_dst_size(data_size); + self.ch_ctrl_pri.cfg.set_dst_inc(addr_incr); + self.ch_ctrl_pri + .cfg + .set_n_minus_1(u10::new(n_minus_one as u16)); + self.ch_ctrl_pri.cfg.set_r_power(RPower::Every4); + self.select_primary_structure(); + } +} + +impl Dma { + /// Create a new DMA instance. + /// + /// You can also place the [DmaCtrlBlock] statically using a global static mutable + /// instance and the [DmaCtrlBlock::new] const constructor This also allows to place the control + /// block in a memory section using the [link_section](https://doc.rust-lang.org/reference/abi.html#the-link_section-attribute) + /// attribute and then creating a mutable pointer to it using [core::ptr::addr_of_mut]. + /// + /// Alternatively, the [DmaCtrlBlock::new_at_addr] function can be used to create the DMA + /// control block at a specific address. + pub fn new( + dma: pac::Dma, + cfg: DmaConfig, + ctrl_block: *mut DmaCtrlBlock, + ) -> Result { + // The conversion to u32 is safe here because we are on a 32-bit system. + let raw_addr = ctrl_block as u32; + if raw_addr & BASE_PTR_ADDR_MASK > 0 { + return Err(InvalidCtrlBlockAddrError); + } + enable_peripheral_clock(PeripheralSelect::Dma); + reset_peripheral_for_cycles(PeripheralSelect::Dma, 2); + let dma = Dma { dma, ctrl_block }; + dma.dma + .ctrl_base_ptr() + .write(|w| unsafe { w.bits(raw_addr) }); + dma.set_protection_bits(&cfg); + dma.enable(); + Ok(dma) + } + + #[inline(always)] + pub fn enable(&self) { + self.dma.cfg().write(|w| w.master_enable().set_bit()); + } + + #[inline(always)] + pub fn disable(&self) { + self.dma.cfg().write(|w| w.master_enable().clear_bit()); + } + + #[inline(always)] + pub fn set_protection_bits(&self, cfg: &DmaConfig) { + self.dma.cfg().write(|w| unsafe { + w.chnl_prot_ctrl().bits( + cfg.privileged as u8 | ((cfg.bufferable as u8) << 1) | ((cfg.cacheable as u8) << 2), + ) + }); + } + + /// Split the DMA instance into four DMA channels which can be used individually. This allows + /// using the inidividual DMA channels in separate tasks. + pub fn split(self) -> (DmaChannel, DmaChannel, DmaChannel, DmaChannel) { + // Safety: The DMA channel API only operates on its respective channels. + ( + DmaChannel { + channel: 0, + done_interrupt: pac::Interrupt::DMA_DONE0, + active_interrupt: pac::Interrupt::DMA_ACTIVE0, + dma: unsafe { pac::Dma::steal() }, + ch_ctrl_pri: unsafe { &mut (*self.ctrl_block).pri[0] }, + ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[0] }, + }, + DmaChannel { + channel: 1, + done_interrupt: pac::Interrupt::DMA_DONE1, + active_interrupt: pac::Interrupt::DMA_ACTIVE1, + dma: unsafe { pac::Dma::steal() }, + ch_ctrl_pri: unsafe { &mut (*self.ctrl_block).pri[1] }, + ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[1] }, + }, + DmaChannel { + channel: 2, + done_interrupt: pac::Interrupt::DMA_DONE2, + active_interrupt: pac::Interrupt::DMA_ACTIVE2, + dma: unsafe { pac::Dma::steal() }, + ch_ctrl_pri: unsafe { &mut (*self.ctrl_block).pri[2] }, + ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[2] }, + }, + DmaChannel { + channel: 3, + done_interrupt: pac::Interrupt::DMA_DONE3, + active_interrupt: pac::Interrupt::DMA_ACTIVE3, + dma: unsafe { pac::Dma::steal() }, + ch_ctrl_pri: unsafe { &mut (*self.ctrl_block).pri[3] }, + ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[3] }, + }, + ) + } +} diff --git a/va416xx/va416xx-hal/src/edac.rs b/va416xx/va416xx-hal/src/edac.rs new file mode 100644 index 0000000..56eaf9b --- /dev/null +++ b/va416xx/va416xx-hal/src/edac.rs @@ -0,0 +1,66 @@ +use crate::{enable_nvic_interrupt, pac}; + +#[inline(always)] +pub fn enable_rom_scrub(syscfg: &mut pac::Sysconfig, counter_reset: u16) { + syscfg + .rom_scrub() + .write(|w| unsafe { w.bits(counter_reset as u32) }); +} + +#[inline(always)] +pub fn enable_ram0_scrub(syscfg: &mut pac::Sysconfig, counter_reset: u16) { + syscfg + .ram0_scrub() + .write(|w| unsafe { w.bits(counter_reset as u32) }); +} + +#[inline(always)] +pub fn enable_ram1_scrub(syscfg: &mut pac::Sysconfig, counter_reset: u16) { + syscfg + .ram1_scrub() + .write(|w| unsafe { w.bits(counter_reset as u32) }); +} + +/// This function enables the SBE related interrupts. The user should also provide a +/// `EDAC_SBE` ISR and use [clear_sbe_irq] inside that ISR at the very least. +#[inline(always)] +pub fn enable_sbe_irq() { + unsafe { + enable_nvic_interrupt(pac::Interrupt::EDAC_SBE); + } +} + +/// This function enables the SBE related interrupts. The user should also provide a +/// `EDAC_MBE` ISR and use [clear_mbe_irq] inside that ISR at the very least. +#[inline(always)] +pub fn enable_mbe_irq() { + unsafe { + enable_nvic_interrupt(pac::Interrupt::EDAC_MBE); + } +} + +/// This function should be called in the user provided `EDAC_SBE` interrupt-service routine +/// to clear the SBE related interrupts. +#[inline(always)] +pub fn clear_sbe_irq() { + // Safety: This function only clears SBE related IRQs + let syscfg = unsafe { pac::Sysconfig::steal() }; + syscfg.irq_clr().write(|w| { + w.romsbe().set_bit(); + w.ram0sbe().set_bit(); + w.ram1sbe().set_bit() + }); +} + +/// This function should be called in the user provided `EDAC_MBE` interrupt-service routine +/// to clear the MBE related interrupts. +#[inline(always)] +pub fn clear_mbe_irq() { + // Safety: This function only clears SBE related IRQs + let syscfg = unsafe { pac::Sysconfig::steal() }; + syscfg.irq_clr().write(|w| { + w.rommbe().set_bit(); + w.ram0mbe().set_bit(); + w.ram1mbe().set_bit() + }); +} diff --git a/va416xx/va416xx-hal/src/gpio/mod.rs b/va416xx/va416xx-hal/src/gpio/mod.rs new file mode 100644 index 0000000..c20e4f8 --- /dev/null +++ b/va416xx/va416xx-hal/src/gpio/mod.rs @@ -0,0 +1,20 @@ +//! # GPIO support module. +//! +//! Contains abstractions to use the pins provided by the [crate::pins] module as GPIO or +//! IO peripheral pins. +//! +//! The core data structures provided for this are the +//! +//! - [Output] for push-pull output pins. +//! - [Input] for input pins. +//! - [Flex] for pins with flexible configuration requirements. +//! - [IoPeriphPin] for IO peripheral pins. +//! +//! The [crate::pins] module exposes singletons to access the [Pin]s required by this module +//! in a type-safe way. +//! +//! # Examples +//! +//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/blinky.rs) +//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs) +pub use vorago_shared_hal::gpio::*; diff --git a/va416xx/va416xx-hal/src/i2c.rs b/va416xx/va416xx-hal/src/i2c.rs new file mode 100644 index 0000000..49f2417 --- /dev/null +++ b/va416xx/va416xx-hal/src/i2c.rs @@ -0,0 +1,6 @@ +//! API for the I2C peripheral +//! +//! ## Examples +//! +//! - [PEB1 accelerometer example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/peb1-accelerometer.rs) +pub use vorago_shared_hal::i2c::*; diff --git a/va416xx/va416xx-hal/src/irq_router.rs b/va416xx/va416xx-hal/src/irq_router.rs new file mode 100644 index 0000000..97781e0 --- /dev/null +++ b/va416xx/va416xx-hal/src/irq_router.rs @@ -0,0 +1,26 @@ +//! IRQ Router peripheral support. +use vorago_shared_hal::{enable_peripheral_clock, reset_peripheral_for_cycles, PeripheralSelect}; + +use crate::pac; + +/// This enables and initiates the peripheral. +/// +/// Please note that this method also writes 0 to the registers which do not have 0 as the default +/// reset value. The programmers guide v1.2 and the actual values inspected using a SVD viewer +/// are inconsistent here, and the registers being non-zero can actually lead to weird bugs +/// when working with interrupts. Registers DMASELx and ADCSEL/DMASELx will reset to 0x7f and 0x1f +/// respectively instead of 0x00. +pub fn enable_and_init_irq_router() { + let irq_router = unsafe { pac::IrqRouter::steal() }; + enable_peripheral_clock(PeripheralSelect::IrqRouter); + reset_peripheral_for_cycles(PeripheralSelect::IrqRouter, 2); + unsafe { + irq_router.dmasel0().write_with_zero(|w| w); + irq_router.dmasel1().write_with_zero(|w| w); + irq_router.dmasel2().write_with_zero(|w| w); + irq_router.dmasel3().write_with_zero(|w| w); + irq_router.adcsel().write_with_zero(|w| w); + irq_router.dacsel0().write_with_zero(|w| w); + irq_router.dacsel1().write_with_zero(|w| w); + } +} diff --git a/va416xx/va416xx-hal/src/lib.rs b/va416xx/va416xx-hal/src/lib.rs new file mode 100644 index 0000000..c7132e9 --- /dev/null +++ b/va416xx/va416xx-hal/src/lib.rs @@ -0,0 +1,139 @@ +//! This is the **H**ardware **A**bstraction **L**ayer (HAL) for the VA416xx MCU family. +//! +//! It is an additional hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx). +//! +//! It is the result of reading the datasheet for the device and encoding a type-safe layer over the +//! raw PAC. This crate also implements traits specified by the +//! [embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with +//! various drivers in the embedded rust ecosystem. +//! +//! It is generally advised to enable ONE of the following device features to use this crate +//! depending on which chip you are using: +//! +//! - `va41630` +//! - `va41629` +//! - `va41628` +//! - `va41620` +//! +//! If no option is specified, only access to APIs which are common for all families or +//! which are not disabled for specific families is granted. +//! +//! When using this HAL and writing applications for the VA416xx family in general, it is strongly +//! recommended that you set up the clock properly, because the default internal HBO clock +//! is not very accurate. You can use the [crate::clock] module for this. If you are working +//! with interrupts, it is strongly recommended to set up the IRQ router with the +//! [crate::irq_router] module at the very least because that peripheral has confusing and/or +//! faulty register reset values which might lead to weird bugs and glitches. +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] +#[cfg(feature = "alloc")] +extern crate alloc; +#[cfg(test)] +extern crate std; + +use gpio::Port; +pub use va416xx as device; +pub use va416xx as pac; + +pub mod can; +pub mod clock; +pub mod dma; +pub mod edac; +pub mod gpio; +pub mod i2c; +pub mod irq_router; +pub mod pins; +pub mod prelude; +pub mod pwm; +pub mod spi; +pub mod time; +pub mod timer; +pub mod uart; +pub mod wdt; + +#[cfg(feature = "va41630")] +pub mod nvm; + +#[cfg(not(feature = "va41628"))] +pub mod adc; +#[cfg(not(feature = "va41628"))] +pub mod dac; + +pub use vorago_shared_hal::{ + assert_peripheral_reset, deassert_peripheral_reset, disable_nvic_interrupt, + disable_peripheral_clock, enable_nvic_interrupt, enable_peripheral_clock, + reset_peripheral_for_cycles, FunctionSelect, PeripheralSelect, +}; + +#[derive(Debug, PartialEq, Eq, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("invalid pin with number {0}")] +pub struct InvalidPinError(u8); + +/// Can be used to manually manipulate the function select of port pins. +/// +/// The function selection table can be found on p.286 of the programmers guide. Please note +/// that most of the structures and APIs in this library will automatically correctly configure +/// the pin or statically expect the correct pin type. +#[inline] +pub fn port_function_select( + ioconfig: &mut pac::Ioconfig, + port: Port, + pin: u8, + funsel: FunctionSelect, +) -> Result<(), InvalidPinError> { + if (port == Port::G && pin >= 8) || pin >= 16 { + return Err(InvalidPinError(pin)); + } + let reg_block = match port { + Port::A => ioconfig.porta(pin as usize), + Port::B => ioconfig.portb(pin as usize), + Port::C => ioconfig.portc(pin as usize), + Port::D => ioconfig.portd(pin as usize), + Port::E => ioconfig.porte(pin as usize), + Port::F => ioconfig.portf(pin as usize), + Port::G => ioconfig.portg(pin as usize), + }; + + reg_block.modify(|_, w| unsafe { w.funsel().bits(funsel as u8) }); + Ok(()) +} + +pub trait SyscfgExt { + fn enable_peripheral_clock(&mut self, clock: PeripheralSelect); + + fn disable_peripheral_clock(&mut self, clock: PeripheralSelect); + + fn assert_periph_reset(&mut self, periph: PeripheralSelect); + + fn deassert_periph_reset(&mut self, periph: PeripheralSelect); + + fn reset_peripheral_reset_for_cycles(&mut self, periph: PeripheralSelect, cycles: usize); +} + +impl SyscfgExt for pac::Sysconfig { + #[inline(always)] + fn enable_peripheral_clock(&mut self, clock: PeripheralSelect) { + enable_peripheral_clock(clock) + } + + #[inline(always)] + fn disable_peripheral_clock(&mut self, clock: PeripheralSelect) { + disable_peripheral_clock(clock) + } + + #[inline(always)] + fn assert_periph_reset(&mut self, clock: PeripheralSelect) { + assert_peripheral_reset(clock) + } + + #[inline(always)] + fn deassert_periph_reset(&mut self, clock: PeripheralSelect) { + deassert_peripheral_reset(clock) + } + + #[inline(always)] + fn reset_peripheral_reset_for_cycles(&mut self, periph: PeripheralSelect, cycles: usize) { + reset_peripheral_for_cycles(periph, cycles) + } +} diff --git a/va416xx/va416xx-hal/src/nvm.rs b/va416xx/va416xx-hal/src/nvm.rs new file mode 100644 index 0000000..7d45e92 --- /dev/null +++ b/va416xx/va416xx-hal/src/nvm.rs @@ -0,0 +1,278 @@ +//! Non-volatile memory (NVM) driver. +//! +//! Provides a basic API to work with the internal NVM of the VA41630 MCU. +//! +//! # Examples +//! +//! - [Flashloader application](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/flashloader) +use embedded_hal::spi::MODE_0; +use vorago_shared_hal::{ + disable_peripheral_clock, enable_peripheral_clock, reset_peripheral_for_cycles, +}; + +use crate::clock::Clocks; +use crate::pac; +use crate::spi::{ + mode_to_cpo_cph_bit, spi_clk_config_from_div, SpiInstance, SpiWord, BMSTART_BMSTOP_MASK, +}; + +const NVM_CLOCK_DIV: u16 = 2; + +// Commands. The internal FRAM is based on the Cypress FM25V20A device. + +/// Write enable register. +pub const FRAM_WREN: u8 = 0x06; +pub const FRAM_WRDI: u8 = 0x04; +pub const FRAM_RDSR: u8 = 0x05; +/// Write single status register +pub const FRAM_WRSR: u8 = 0x01; +pub const FRAM_READ: u8 = 0x03; +pub const FRAM_WRITE: u8 = 0x02; +pub const FRAM_RDID: u8 = 0x9F; +pub const FRAM_SLEEP: u8 = 0xB9; + +// Address Masks + +const ADDR_MSB_MASK: u32 = 0xFF0000; +const ADDR_MID_MASK: u32 = 0x00FF00; +const ADDR_LSB_MASK: u32 = 0x0000FF; + +#[inline(always)] +const fn msb_addr_byte(addr: u32) -> u8 { + ((addr & ADDR_MSB_MASK) >> 16) as u8 +} + +#[inline(always)] +const fn mid_addr_byte(addr: u32) -> u8 { + ((addr & ADDR_MID_MASK) >> 8) as u8 +} + +#[inline(always)] +const fn lsb_addr_byte(addr: u32) -> u8 { + (addr & ADDR_LSB_MASK) as u8 +} + +pub const WPEN_ENABLE_MASK: u8 = 1 << 7; +pub const BP_0_ENABLE_MASK: u8 = 1 << 2; +pub const BP_1_ENABLE_MASK: u8 = 1 << 3; + +pub struct Nvm { + spi: Option, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct VerifyError { + addr: u32, + found: u8, + expected: u8, +} + +impl Nvm { + pub fn new(spi: pac::Spi3, _clocks: &Clocks) -> Self { + enable_peripheral_clock(pac::Spi3::PERIPH_SEL); + // This is done in the C HAL. + reset_peripheral_for_cycles(pac::Spi3::PERIPH_SEL, 2); + + let spi_clk_cfg = spi_clk_config_from_div(NVM_CLOCK_DIV).unwrap(); + let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(MODE_0); + spi.ctrl0().write(|w| { + unsafe { + w.size().bits(u8::word_reg()); + w.scrdv().bits(spi_clk_cfg.scrdv()); + // Clear clock phase and polarity. Will be set to correct value for each + // transfer + w.spo().bit(cpo_bit); + w.sph().bit(cph_bit) + } + }); + spi.ctrl1().write(|w| { + w.blockmode().set_bit(); + unsafe { w.ss().bits(0) }; + w.bmstart().set_bit(); + w.bmstall().set_bit() + }); + spi.clkprescale() + .write(|w| unsafe { w.bits(spi_clk_cfg.prescale_val() as u32) }); + + spi.fifo_clr().write(|w| { + w.rxfifo().set_bit(); + w.txfifo().set_bit() + }); + // Enable the peripheral as the last step as recommended in the + // programmers guide + spi.ctrl1().modify(|_, w| w.enable().set_bit()); + + let mut nvm = Self { spi: Some(spi) }; + nvm.disable_write_prot(); + nvm + } + + pub fn disable_write_prot(&mut self) { + self.wait_for_tx_idle(); + self.write_with_bmstop(FRAM_WREN); + self.wait_for_tx_idle(); + self.write_single(FRAM_WRSR); + self.write_with_bmstop(0x00); + self.wait_for_tx_idle(); + } + + pub fn read_rdsr(&self) -> u8 { + self.write_single(FRAM_RDSR); + self.write_with_bmstop(0x00); + self.wait_for_rx_available(); + self.read_single_word(); + self.wait_for_rx_available(); + (self.read_single_word() & 0xff) as u8 + } + + pub fn enable_write_prot(&mut self) { + self.wait_for_tx_idle(); + self.write_with_bmstop(FRAM_WREN); + self.wait_for_tx_idle(); + self.write_single(FRAM_WRSR); + self.write_with_bmstop(0x00); + } + #[inline(always)] + pub fn spi(&self) -> &pac::Spi3 { + self.spi.as_ref().unwrap() + } + + #[inline(always)] + pub fn write_single(&self, word: u8) { + self.spi().data().write(|w| unsafe { w.bits(word as u32) }); + } + + #[inline(always)] + pub fn write_with_bmstop(&self, word: u8) { + self.spi() + .data() + .write(|w| unsafe { w.bits(BMSTART_BMSTOP_MASK | word as u32) }); + } + + #[inline(always)] + pub fn wait_for_tx_idle(&self) { + while self.spi().status().read().tfe().bit_is_clear() { + cortex_m::asm::nop(); + } + while self.spi().status().read().busy().bit_is_set() { + cortex_m::asm::nop(); + } + self.clear_fifos() + } + + #[inline(always)] + pub fn clear_fifos(&self) { + self.spi().fifo_clr().write(|w| { + w.rxfifo().set_bit(); + w.txfifo().set_bit() + }); + } + + #[inline(always)] + pub fn wait_for_rx_available(&self) { + while !self.spi().status().read().rne().bit_is_set() { + cortex_m::asm::nop(); + } + } + + #[inline(always)] + pub fn read_single_word(&self) -> u32 { + self.spi().data().read().bits() + } + + pub fn write_data(&self, addr: u32, data: &[u8]) { + self.wait_for_tx_idle(); + self.write_with_bmstop(FRAM_WREN); + self.wait_for_tx_idle(); + self.write_single(FRAM_WRITE); + self.write_single(msb_addr_byte(addr)); + self.write_single(mid_addr_byte(addr)); + self.write_single(lsb_addr_byte(addr)); + for byte in data.iter().take(data.len() - 1) { + while self.spi().status().read().tnf().bit_is_clear() { + cortex_m::asm::nop(); + } + self.write_single(*byte); + self.read_single_word(); + } + while self.spi().status().read().tnf().bit_is_clear() { + cortex_m::asm::nop(); + } + self.write_with_bmstop(*data.last().unwrap()); + self.wait_for_tx_idle(); + } + + pub fn read_data(&self, addr: u32, buf: &mut [u8]) { + self.common_read_start(addr); + for byte in buf { + // Pump the SPI. + self.write_single(0); + self.wait_for_rx_available(); + *byte = self.read_single_word() as u8; + } + self.write_with_bmstop(0); + self.wait_for_tx_idle(); + } + + pub fn verify_data(&self, addr: u32, comp_buf: &[u8]) -> Result<(), VerifyError> { + self.common_read_start(addr); + for (idx, byte) in comp_buf.iter().enumerate() { + // Pump the SPI. + self.write_single(0); + self.wait_for_rx_available(); + let next_word = self.read_single_word() as u8; + if next_word != *byte { + self.write_with_bmstop(0); + self.wait_for_tx_idle(); + return Err(VerifyError { + addr: addr + idx as u32, + found: next_word, + expected: *byte, + }); + } + } + self.write_with_bmstop(0); + self.wait_for_tx_idle(); + Ok(()) + } + + /// Enable write-protection and disables the peripheral clock. + pub fn shutdown(&mut self) { + self.wait_for_tx_idle(); + self.write_with_bmstop(FRAM_WREN); + self.wait_for_tx_idle(); + self.write_single(WPEN_ENABLE_MASK | BP_0_ENABLE_MASK | BP_1_ENABLE_MASK); + disable_peripheral_clock(pac::Spi3::PERIPH_SEL); + } + + /// This function calls [Self::shutdown] and gives back the peripheral structure. + pub fn release(mut self) -> pac::Spi3 { + self.shutdown(); + self.spi.take().unwrap() + } + + fn common_read_start(&self, addr: u32) { + self.wait_for_tx_idle(); + self.write_single(FRAM_READ); + self.write_single(msb_addr_byte(addr)); + self.write_single(mid_addr_byte(addr)); + self.write_single(lsb_addr_byte(addr)); + for _ in 0..4 { + // Pump the SPI. + self.write_single(0); + self.wait_for_rx_available(); + // The first 4 data bytes received need to be ignored. + self.read_single_word(); + } + } +} + +/// Call [Self::shutdown] on drop. +impl Drop for Nvm { + fn drop(&mut self) { + if self.spi.is_some() { + self.shutdown(); + } + } +} diff --git a/va416xx/va416xx-hal/src/pins.rs b/va416xx/va416xx-hal/src/pins.rs new file mode 100644 index 0000000..1c46616 --- /dev/null +++ b/va416xx/va416xx-hal/src/pins.rs @@ -0,0 +1,6 @@ +//! Pin resource management singletons. +//! +//! This module contains the pin singletons. It allows creating those singletons +//! to access the [Pin] structures of individual ports in a safe way with checked ownership +//! rules. +pub use vorago_shared_hal::pins::*; diff --git a/va416xx/va416xx-hal/src/prelude.rs b/va416xx/va416xx-hal/src/prelude.rs new file mode 100644 index 0000000..1b86abe --- /dev/null +++ b/va416xx/va416xx-hal/src/prelude.rs @@ -0,0 +1,4 @@ +//! Prelude +pub use crate::clock::ClkgenExt; +pub use fugit::ExtU32 as _; +pub use fugit::RateExtU32 as _; diff --git a/va416xx/va416xx-hal/src/pwm.rs b/va416xx/va416xx-hal/src/pwm.rs new file mode 100644 index 0000000..fb0d911 --- /dev/null +++ b/va416xx/va416xx-hal/src/pwm.rs @@ -0,0 +1,8 @@ +//! API for Pulse-Width Modulation (PWM) +//! +//! The Vorago devices use the TIM peripherals to perform PWM related tasks +//! +//! ## Examples +//! +//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/pwm.rs) +pub use vorago_shared_hal::pwm::*; diff --git a/va416xx/va416xx-hal/src/spi.rs b/va416xx/va416xx-hal/src/spi.rs new file mode 100644 index 0000000..54ed7d4 --- /dev/null +++ b/va416xx/va416xx-hal/src/spi.rs @@ -0,0 +1,11 @@ +//! API for the SPI peripheral. +//! +//! The main abstraction provided by this module is the [Spi] an structure. +//! It provides the [SpiBus trait](https://docs.rs/embedded-hal/latest/embedded_hal/spi/trait.SpiBus.html), +//! but also offer a low level interface via the [SpiLowLevel] trait. +//! +//! ## Examples +//! +//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/spi.rs) +//! - [NVM library][crate::nvm] +pub use vorago_shared_hal::spi::*; diff --git a/va416xx/va416xx-hal/src/time.rs b/va416xx/va416xx-hal/src/time.rs new file mode 100644 index 0000000..9808028 --- /dev/null +++ b/va416xx/va416xx-hal/src/time.rs @@ -0,0 +1,26 @@ +//! Time units + +// Frequency based + +/// Hertz +pub type Hertz = fugit::HertzU32; + +/// KiloHertz +pub type KiloHertz = fugit::KilohertzU32; + +/// MegaHertz +pub type MegaHertz = fugit::MegahertzU32; + +// Period based + +/// Seconds +pub type Seconds = fugit::SecsDurationU32; + +/// Milliseconds +pub type Milliseconds = fugit::MillisDurationU32; + +/// Microseconds +pub type Microseconds = fugit::MicrosDurationU32; + +/// Nanoseconds +pub type Nanoseconds = fugit::NanosDurationU32; diff --git a/va416xx/va416xx-hal/src/timer.rs b/va416xx/va416xx-hal/src/timer.rs new file mode 100644 index 0000000..563a196 --- /dev/null +++ b/va416xx/va416xx-hal/src/timer.rs @@ -0,0 +1,9 @@ +//! API for the TIM peripherals +//! +//! ## Examples +//! +//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs) +//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/cascade.rs) +pub use vorago_shared_hal::timer::*; + +pub const TIM_IRQ_OFFSET: usize = 48; diff --git a/va416xx/va416xx-hal/src/uart/mod.rs b/va416xx/va416xx-hal/src/uart/mod.rs new file mode 100644 index 0000000..bb7db58 --- /dev/null +++ b/va416xx/va416xx-hal/src/uart/mod.rs @@ -0,0 +1,17 @@ +//! # API for the UART peripheral +//! +//! The core of this API are the [Uart], [Rx] and [Tx] structures. +//! The RX structure also has a dedicated [RxWithInterrupt] variant which allows reading the receiver +//! using interrupts. +//! +//! The [rx_asynch] and [tx_asynch] modules provide an asynchronous non-blocking API for the UART +//! peripheral. +//! +//! ## Examples +//! +//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs) +//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs) +//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/flashloader) +//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs) +//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs) +pub use vorago_shared_hal::uart::*; diff --git a/va416xx/va416xx-hal/src/wdt.rs b/va416xx/va416xx-hal/src/wdt.rs new file mode 100644 index 0000000..37d1b28 --- /dev/null +++ b/va416xx/va416xx-hal/src/wdt.rs @@ -0,0 +1,105 @@ +//! # API for the Watchdog peripheral +//! +//! ## Examples +//! +//! - [Watchdog simple example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/wdt.rs) +use vorago_shared_hal::{enable_peripheral_clock, reset_peripheral_for_cycles, PeripheralSelect}; + +use crate::time::Hertz; +use crate::{clock::Clocks, pac}; +use crate::{disable_nvic_interrupt, enable_nvic_interrupt}; + +pub const WDT_UNLOCK_VALUE: u32 = 0x1ACC_E551; + +/// Watchdog peripheral driver. +pub struct Wdt { + clock_freq: Hertz, + wdt: pac::WatchDog, +} + +/// Type alias for backwards compatibility +#[deprecated(since = "0.2.0", note = "Please use `Wdt` instead")] +pub type WdtController = Wdt; + +/// Enable the watchdog interrupt +/// +/// # Safety +/// +/// This function is `unsafe` because it can break mask-based critical sections. +#[inline] +pub unsafe fn enable_wdt_interrupts() { + enable_nvic_interrupt(pac::Interrupt::WATCHDOG) +} + +#[inline] +pub fn disable_wdt_interrupts() { + disable_nvic_interrupt(pac::Interrupt::WATCHDOG) +} + +impl Wdt { + pub fn new(wdt: pac::WatchDog, clocks: &Clocks, wdt_freq_ms: u32) -> Self { + Self::start(wdt, clocks, wdt_freq_ms) + } + + pub fn start(wdt: pac::WatchDog, clocks: &Clocks, wdt_freq_ms: u32) -> Self { + enable_peripheral_clock(PeripheralSelect::Watchdog); + reset_peripheral_for_cycles(PeripheralSelect::Watchdog, 2); + + let wdt_clock = clocks.apb2(); + let mut wdt_ctrl = Self { + clock_freq: wdt_clock, + wdt, + }; + wdt_ctrl.set_freq(wdt_freq_ms); + wdt_ctrl.wdt.wdogcontrol().write(|w| w.inten().set_bit()); + wdt_ctrl.feed(); + // Unmask the watchdog interrupt + unsafe { + enable_wdt_interrupts(); + } + wdt_ctrl + } + + #[inline] + pub fn set_freq(&mut self, freq_ms: u32) { + let counter = (self.clock_freq.raw() / 1000) * freq_ms; + self.wdt.wdogload().write(|w| unsafe { w.bits(counter) }); + } + + #[inline] + pub fn disable_reset(&mut self) { + self.wdt.wdogcontrol().modify(|_, w| w.resen().clear_bit()); + } + + #[inline] + pub fn enable_reset(&mut self) { + self.wdt.wdogcontrol().modify(|_, w| w.resen().set_bit()); + } + + #[inline] + pub fn counter(&self) -> u32 { + self.wdt.wdogvalue().read().bits() + } + + #[inline] + pub fn feed(&self) { + self.wdt.wdogintclr().write(|w| unsafe { w.bits(1) }); + } + + #[inline] + pub fn lock(&self) { + self.wdt.wdoglock().write(|w| unsafe { w.bits(0) }); + } + + #[inline] + pub fn unlock(&self) { + self.wdt + .wdoglock() + .write(|w| unsafe { w.bits(WDT_UNLOCK_VALUE) }); + } + + #[inline] + pub fn is_locked(&self) -> bool { + self.wdt.wdogload().read().bits() == 1 + } +} diff --git a/va416xx/va416xx/.github/bors.toml b/va416xx/va416xx/.github/bors.toml new file mode 100644 index 0000000..1779788 --- /dev/null +++ b/va416xx/va416xx/.github/bors.toml @@ -0,0 +1,2 @@ +status = ["ci"] +delete_merged_branches = true diff --git a/va416xx/va416xx/.github/workflows/changelog.yml b/va416xx/va416xx/.github/workflows/changelog.yml new file mode 100644 index 0000000..dbba297 --- /dev/null +++ b/va416xx/va416xx/.github/workflows/changelog.yml @@ -0,0 +1,20 @@ +on: + pull_request_target: + +name: Changelog check + +jobs: + changelog: + name: Changelog check + runs-on: ubuntu-latest + steps: + - name: Checkout sources + uses: actions/checkout@v2 + + - name: Changelog updated + uses: Zomzog/changelog-checker@v1.2.0 + with: + fileName: CHANGELOG.md + noChangelogLabel: no changelog + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} diff --git a/va416xx/va416xx/.github/workflows/ci.yml b/va416xx/va416xx/.github/workflows/ci.yml new file mode 100644 index 0000000..1afe688 --- /dev/null +++ b/va416xx/va416xx/.github/workflows/ci.yml @@ -0,0 +1,44 @@ +name: ci +on: [push, pull_request] + +jobs: + check: + name: Check build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv7em-none-eabihf" + - run: cargo check --target thumbv7em-none-eabihf + - run: cargo check --target thumbv7em-none-eabihf --examples + - run: cargo check -p va416xx --target thumbv7em-none-eabihf --all-features + - run: cargo check -p va416xx-hal --target thumbv7em-none-eabihf --features "defmt" + + fmt: + name: Check formatting + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + - run: cargo fmt --all -- --check + + docs: + name: Check Documentation Build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@nightly + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va416xx --all-features + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va416xx-hal --features "defmt va41630" + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p vorago-peb1 + + clippy: + name: Clippy + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv7em-none-eabihf" + - run: cargo clippy --target thumbv7em-none-eabihf -- -D warnings diff --git a/va416xx/va416xx/.gitignore b/va416xx/va416xx/.gitignore new file mode 100644 index 0000000..96ef6c0 --- /dev/null +++ b/va416xx/va416xx/.gitignore @@ -0,0 +1,2 @@ +/target +Cargo.lock diff --git a/va416xx/va416xx/CHANGELOG.md b/va416xx/va416xx/CHANGELOG.md new file mode 100644 index 0000000..5f9a68b --- /dev/null +++ b/va416xx/va416xx/CHANGELOG.md @@ -0,0 +1,47 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +## [unreleased] + +## [v0.5.0] 2025-09-03 + +- Re-generated PAC with `svd2rust` v0.37.0 + +## [v0.4.1] 2025-07-22 + +defmt v1 + +## [v0.4.0] 2025-02-18 + +- Re-generated PAC with `svd2rust` v0.35.0 and added optional `defmt` and `Debug` implementations + +## [v0.3.0] 2025-02-13 + +- Re-generated PAC with `svd2rust` v0.35.0 + +## [v0.2.0] 2024-06-25 + +- Re-Generated PAC with `svd2rust` v0.33.3 +- Improve documentation for generation of PAC. + +## [v0.1.1] + +- Clippy issue fixed by regenerating PAC with patched `svd2rust`: + https://github.com/rust-embedded/svd2rust/pull/558 + +## [v0.1.0] + +- Clippy currently complains about unsound code which should still work. + Related issue: https://github.com/rust-embedded/svd2rust/issues/557 + Clippy is disabled in CI/CD for now. +- Initial release + +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-v0.5.0...HEAD +[v0.5.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-v0.4.1...va416xx-v0.5.0 +[v0.4.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-v0.4.0...va416xx-v0.4.1 +[v0.4.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-v0.3.0...va416xx-v0.4.0 diff --git a/va416xx/va416xx/Cargo.toml b/va416xx/va416xx/Cargo.toml new file mode 100644 index 0000000..e446d2a --- /dev/null +++ b/va416xx/va416xx/Cargo.toml @@ -0,0 +1,33 @@ +[package] +name = "va416xx" +version = "0.5.0" +authors = ["Robin Mueller "] +edition = "2021" +description = "PAC for the Vorago VA416xx family of MCUs" +homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs" +repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx-rs" +license = "Apache-2.0" +keywords = ["no-std", "arm", "cortex-m", "vorago", "va416xx"] +categories = ["embedded", "no-std", "hardware-support"] + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +cortex-m = "0.7" +vcell = "0.1.3" + +defmt = { version = "1", optional = true } +critical-section = { version = "1", optional = true } + +[dependencies.cortex-m-rt] +optional = true +version = ">=0.6.15,<0.8" + +[features] +rt = ["cortex-m-rt/device"] +# Adds Debug implementation +debug = [] + +[package.metadata.docs.rs] +all-features = true +rustdoc-args = ["--generate-link-to-definition"] diff --git a/va416xx/va416xx/LICENSE-APACHE b/va416xx/va416xx/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va416xx/va416xx/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va416xx/va416xx/NOTICE b/va416xx/va416xx/NOTICE new file mode 100644 index 0000000..321b896 --- /dev/null +++ b/va416xx/va416xx/NOTICE @@ -0,0 +1,3 @@ +Rust Peripheral Access Crate (PAC) crate for the Vorago VA416xx family of MCUs + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va416xx/va416xx/README.md b/va416xx/va416xx/README.md new file mode 100644 index 0000000..0737264 --- /dev/null +++ b/va416xx/va416xx/README.md @@ -0,0 +1,58 @@ +[![Crates.io](https://img.shields.io/crates/v/va416xx)](https://crates.io/crates/va416xx) +[![docs.rs](https://img.shields.io/docsrs/va416xx)](https://docs.rs/va416xx) + +# PAC for the Vorago VA416xx microcontroller family + +This repository contains the Peripheral Access Crate (PAC) for +Voragos VA416xx series of Cortex-M4 based microcontrollers. + +The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust). + +## Usage + +To use this crate, add this to your `Cargo.toml` + +```toml +[dependencies.va416xx] +version = "" +features = ["rt"] +``` + +The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`. + +For full details on the autgenerated API, you can read the +[svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/). + +## Regenerating the PAC + +If you want to re-generate the PAC, for example if the register file `va416xx.svd` changes +or the `svd2rust` version is updated, you can do some using the following these steps: + +1. Make sure all necessary tools are installed: [`svd2rust`](https://docs.rs/svd2rust/latest/svd2rust/), + [`svdtools`](https://github.com/rust-embedded/svdtools) and [`form`](https://crates.io/crates/form). + You can install all tools with `cargo`: + + ```sh + cargo install --locked svd2rust svdtools form + ``` + +2. Patch the vendor-provided SVD file `svd/va41xx.svd`. This can be done using `svdtools` in + conjunction with the `svd/va416xx-patch.yml` file. + + ```sh + svdtools patch svd/va416xx-patch.yml + ``` + +3. Use `svd2rust` to generate the Rust library + + ```sh + svd2rust -i svd/va416xx.svd.patched + ``` + +4. Use the `form` tool to split the generated `lib.rs` into individual modules. + + ```sh + form -i lib.rs -o src/ + ``` + +The `gen-helper.sh` automates steps 2-4. diff --git a/va416xx/va416xx/automation/Dockerfile b/va416xx/va416xx/automation/Dockerfile new file mode 100644 index 0000000..b9a76c6 --- /dev/null +++ b/va416xx/va416xx/automation/Dockerfile @@ -0,0 +1,11 @@ +# Run the following commands from root directory to build and run locally +# docker build -f automation/Dockerfile -t . +# docker run -it +FROM rust:latest +RUN apt-get update +RUN apt-get --yes upgrade +# tzdata is a dependency, won't install otherwise +ARG DEBIAN_FRONTEND=noninteractive + +RUN rustup target add thumbv7em-none-eabihf && \ + rustup component add rustfmt clippy diff --git a/va416xx/va416xx/automation/Jenkinsfile b/va416xx/va416xx/automation/Jenkinsfile new file mode 100644 index 0000000..925c94e --- /dev/null +++ b/va416xx/va416xx/automation/Jenkinsfile @@ -0,0 +1,39 @@ +pipeline { + agent any + + stages { + stage('Clippy') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo clippy' + } + } + stage('Rustfmt') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo fmt' + } + } + stage('Check') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo check --target thumbv7em-none-eabihf' + } + } + } +} \ No newline at end of file diff --git a/va416xx/va416xx/build.rs b/va416xx/va416xx/build.rs new file mode 100644 index 0000000..d0781ac --- /dev/null +++ b/va416xx/va416xx/build.rs @@ -0,0 +1,17 @@ +#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/va416xx/va416xx/device.x b/va416xx/va416xx/device.x new file mode 100644 index 0000000..983fc7c --- /dev/null +++ b/va416xx/va416xx/device.x @@ -0,0 +1,197 @@ +PROVIDE(U0 = DefaultHandler); +PROVIDE(U1 = DefaultHandler); +PROVIDE(U2 = DefaultHandler); +PROVIDE(U3 = DefaultHandler); +PROVIDE(U4 = DefaultHandler); +PROVIDE(U5 = DefaultHandler); +PROVIDE(U6 = DefaultHandler); +PROVIDE(U7 = DefaultHandler); +PROVIDE(U8 = DefaultHandler); +PROVIDE(U9 = DefaultHandler); +PROVIDE(U10 = DefaultHandler); +PROVIDE(U11 = DefaultHandler); +PROVIDE(U12 = DefaultHandler); +PROVIDE(U13 = DefaultHandler); +PROVIDE(U14 = DefaultHandler); +PROVIDE(U15 = DefaultHandler); +PROVIDE(SPI0_TX = DefaultHandler); +PROVIDE(SPI0_RX = DefaultHandler); +PROVIDE(SPI1_TX = DefaultHandler); +PROVIDE(SPI1_RX = DefaultHandler); +PROVIDE(SPI2_TX = DefaultHandler); +PROVIDE(SPI2_RX = DefaultHandler); +PROVIDE(SPI3_TX = DefaultHandler); +PROVIDE(SPI3_RX = DefaultHandler); +PROVIDE(UART0_TX = DefaultHandler); +PROVIDE(UART0_RX = DefaultHandler); +PROVIDE(UART1_TX = DefaultHandler); +PROVIDE(UART1_RX = DefaultHandler); +PROVIDE(UART2_TX = DefaultHandler); +PROVIDE(UART2_RX = DefaultHandler); +PROVIDE(I2C0_MS = DefaultHandler); +PROVIDE(I2C0_SL = DefaultHandler); +PROVIDE(I2C1_MS = DefaultHandler); +PROVIDE(I2C1_SL = DefaultHandler); +PROVIDE(I2C2_MS = DefaultHandler); +PROVIDE(I2C2_SL = DefaultHandler); +PROVIDE(Ethernet = DefaultHandler); +PROVIDE(U37 = DefaultHandler); +PROVIDE(SpW = DefaultHandler); +PROVIDE(U39 = DefaultHandler); +PROVIDE(DAC0 = DefaultHandler); +PROVIDE(DAC1 = DefaultHandler); +PROVIDE(TRNG = DefaultHandler); +PROVIDE(DMA_ERROR = DefaultHandler); +PROVIDE(ADC = DefaultHandler); +PROVIDE(LoCLK = DefaultHandler); +PROVIDE(LVD = DefaultHandler); +PROVIDE(WATCHDOG = DefaultHandler); +PROVIDE(TIM0 = DefaultHandler); +PROVIDE(TIM1 = DefaultHandler); +PROVIDE(TIM2 = DefaultHandler); +PROVIDE(TIM3 = DefaultHandler); +PROVIDE(TIM4 = DefaultHandler); +PROVIDE(TIM5 = DefaultHandler); +PROVIDE(TIM6 = DefaultHandler); +PROVIDE(TIM7 = DefaultHandler); +PROVIDE(TIM8 = DefaultHandler); +PROVIDE(TIM9 = DefaultHandler); +PROVIDE(TIM10 = DefaultHandler); +PROVIDE(TIM11 = DefaultHandler); +PROVIDE(TIM12 = DefaultHandler); +PROVIDE(TIM13 = DefaultHandler); +PROVIDE(TIM14 = DefaultHandler); +PROVIDE(TIM15 = DefaultHandler); +PROVIDE(TIM16 = DefaultHandler); +PROVIDE(TIM17 = DefaultHandler); +PROVIDE(TIM18 = DefaultHandler); +PROVIDE(TIM19 = DefaultHandler); +PROVIDE(TIM20 = DefaultHandler); +PROVIDE(TIM21 = DefaultHandler); +PROVIDE(TIM22 = DefaultHandler); +PROVIDE(TIM23 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(U73 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(U75 = DefaultHandler); +PROVIDE(EDAC_MBE = DefaultHandler); +PROVIDE(EDAC_SBE = DefaultHandler); +PROVIDE(PORTA0 = DefaultHandler); +PROVIDE(PORTA1 = DefaultHandler); +PROVIDE(PORTA2 = DefaultHandler); +PROVIDE(PORTA3 = DefaultHandler); +PROVIDE(PORTA4 = DefaultHandler); +PROVIDE(PORTA5 = DefaultHandler); +PROVIDE(PORTA6 = DefaultHandler); +PROVIDE(PORTA7 = DefaultHandler); +PROVIDE(PORTA8 = DefaultHandler); +PROVIDE(PORTA9 = DefaultHandler); +PROVIDE(PORTA10 = DefaultHandler); +PROVIDE(PORTA11 = DefaultHandler); +PROVIDE(PORTA12 = DefaultHandler); +PROVIDE(PORTA13 = DefaultHandler); +PROVIDE(PORTA14 = DefaultHandler); +PROVIDE(PORTA15 = DefaultHandler); +PROVIDE(PORTB0 = DefaultHandler); +PROVIDE(PORTB1 = DefaultHandler); +PROVIDE(PORTB2 = DefaultHandler); +PROVIDE(PORTB3 = DefaultHandler); +PROVIDE(PORTB4 = DefaultHandler); +PROVIDE(PORTB5 = DefaultHandler); +PROVIDE(PORTB6 = DefaultHandler); +PROVIDE(PORTB7 = DefaultHandler); +PROVIDE(PORTB8 = DefaultHandler); +PROVIDE(PORTB9 = DefaultHandler); +PROVIDE(PORTB10 = DefaultHandler); +PROVIDE(PORTB11 = DefaultHandler); +PROVIDE(PORTB12 = DefaultHandler); +PROVIDE(PORTB13 = DefaultHandler); +PROVIDE(PORTB14 = DefaultHandler); +PROVIDE(PORTB15 = DefaultHandler); +PROVIDE(PORTC0 = DefaultHandler); +PROVIDE(PORTC1 = DefaultHandler); +PROVIDE(PORTC2 = DefaultHandler); +PROVIDE(PORTC3 = DefaultHandler); +PROVIDE(PORTC4 = DefaultHandler); +PROVIDE(PORTC5 = DefaultHandler); +PROVIDE(PORTC6 = DefaultHandler); +PROVIDE(PORTC7 = DefaultHandler); +PROVIDE(PORTC8 = DefaultHandler); +PROVIDE(PORTC9 = DefaultHandler); +PROVIDE(PORTC10 = DefaultHandler); +PROVIDE(PORTC11 = DefaultHandler); +PROVIDE(PORTC12 = DefaultHandler); +PROVIDE(PORTC13 = DefaultHandler); +PROVIDE(PORTC14 = DefaultHandler); +PROVIDE(PORTC15 = DefaultHandler); +PROVIDE(PORTD0 = DefaultHandler); +PROVIDE(PORTD1 = DefaultHandler); +PROVIDE(PORTD2 = DefaultHandler); +PROVIDE(PORTD3 = DefaultHandler); +PROVIDE(PORTD4 = DefaultHandler); +PROVIDE(PORTD5 = DefaultHandler); +PROVIDE(PORTD6 = DefaultHandler); +PROVIDE(PORTD7 = DefaultHandler); +PROVIDE(PORTD8 = DefaultHandler); +PROVIDE(PORTD9 = DefaultHandler); +PROVIDE(PORTD10 = DefaultHandler); +PROVIDE(PORTD11 = DefaultHandler); +PROVIDE(PORTD12 = DefaultHandler); +PROVIDE(PORTD13 = DefaultHandler); +PROVIDE(PORTD14 = DefaultHandler); +PROVIDE(PORTD15 = DefaultHandler); +PROVIDE(PORTE0 = DefaultHandler); +PROVIDE(PORTE1 = DefaultHandler); +PROVIDE(PORTE2 = DefaultHandler); +PROVIDE(PORTE3 = DefaultHandler); +PROVIDE(PORTE4 = DefaultHandler); +PROVIDE(PORTE5 = DefaultHandler); +PROVIDE(PORTE6 = DefaultHandler); +PROVIDE(PORTE7 = DefaultHandler); +PROVIDE(PORTE8 = DefaultHandler); +PROVIDE(PORTE9 = DefaultHandler); +PROVIDE(PORTE10 = DefaultHandler); +PROVIDE(PORTE11 = DefaultHandler); +PROVIDE(PORTE12 = DefaultHandler); +PROVIDE(PORTE13 = DefaultHandler); +PROVIDE(PORTE14 = DefaultHandler); +PROVIDE(PORTE15 = DefaultHandler); +PROVIDE(PORTF0 = DefaultHandler); +PROVIDE(PORTF1 = DefaultHandler); +PROVIDE(PORTF2 = DefaultHandler); +PROVIDE(PORTF3 = DefaultHandler); +PROVIDE(PORTF4 = DefaultHandler); +PROVIDE(PORTF5 = DefaultHandler); +PROVIDE(PORTF6 = DefaultHandler); +PROVIDE(PORTF7 = DefaultHandler); +PROVIDE(PORTF8 = DefaultHandler); +PROVIDE(PORTF9 = DefaultHandler); +PROVIDE(PORTF10 = DefaultHandler); +PROVIDE(PORTF11 = DefaultHandler); +PROVIDE(PORTF12 = DefaultHandler); +PROVIDE(PORTF13 = DefaultHandler); +PROVIDE(PORTF14 = DefaultHandler); +PROVIDE(PORTF15 = DefaultHandler); +PROVIDE(DMA_ACTIVE0 = DefaultHandler); +PROVIDE(DMA_ACTIVE1 = DefaultHandler); +PROVIDE(DMA_ACTIVE2 = DefaultHandler); +PROVIDE(DMA_ACTIVE3 = DefaultHandler); +PROVIDE(DMA_DONE0 = DefaultHandler); +PROVIDE(DMA_DONE1 = DefaultHandler); +PROVIDE(DMA_DONE2 = DefaultHandler); +PROVIDE(DMA_DONE3 = DefaultHandler); +PROVIDE(I2C0_MS_RX = DefaultHandler); +PROVIDE(I2C0_MS_TX = DefaultHandler); +PROVIDE(I2C0_SL_RX = DefaultHandler); +PROVIDE(I2C0_SL_TX = DefaultHandler); +PROVIDE(I2C1_MS_RX = DefaultHandler); +PROVIDE(I2C1_MS_TX = DefaultHandler); +PROVIDE(I2C1_SL_RX = DefaultHandler); +PROVIDE(I2C1_SL_TX = DefaultHandler); +PROVIDE(I2C2_MS_RX = DefaultHandler); +PROVIDE(I2C2_MS_TX = DefaultHandler); +PROVIDE(I2C2_SL_RX = DefaultHandler); +PROVIDE(I2C2_SL_TX = DefaultHandler); +PROVIDE(FPU = DefaultHandler); +PROVIDE(TXEV = DefaultHandler); + diff --git a/va416xx/va416xx/gen-helper.sh b/va416xx/va416xx/gen-helper.sh new file mode 100755 index 0000000..499e3c9 --- /dev/null +++ b/va416xx/va416xx/gen-helper.sh @@ -0,0 +1,42 @@ +#!/bin/bash + +# Use installed tool by default +svd2rust_bin="svd2rust" +# Automates the steps specified in https://docs.rs/svd2rust/0.19.0/svd2rust/ +if [ -f svd2rust ]; then + # If the local directory contains svd2rust, use that version instead + svd2rust_bin="./svd2rust" +elif [ -f ../svd2rust ]; then + # Keeps the repository clean + svd2rust_bin="../svd2rust" +fi +if [ -x "$(${svd2rust_bin} --version)" ]; then + echo "No svd2rust found locally or installed." \ + "Install it with cargo install svd2rust" + exit +fi + +if ! command -v form &> /dev/null +then + echo "form tool was not found" + exit 1 +fi + +if ! command -v svdtools &> /dev/null +then + echo "svdtools was not found" + exit 1 +fi + +svdtools patch svd/va416xx-patch.yml +${svd2rust_bin} --reexport-interrupt --impl-defmt defmt --impl-debug-feature debug -i svd/va416xx.svd.patched + +result=$? +if [ $result -ne 0 ]; then + echo "svd2rust failed with code $result" + exit +fi + +rm -rf src +form -i lib.rs -o src/ && rm lib.rs +cargo fmt diff --git a/va416xx/va416xx/src/adc.rs b/va416xx/va416xx/src/adc.rs new file mode 100644 index 0000000..f61d7b7 --- /dev/null +++ b/va416xx/va416xx/src/adc.rs @@ -0,0 +1,117 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + fifo_data: FifoData, + status: Status, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + fifo_clr: FifoClr, + _reserved9: [u8; 0x0fd8], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - FIFO data"] + #[inline(always)] + pub const fn fifo_data(&self) -> &FifoData { + &self.fifo_data + } + #[doc = "0x08 - Status"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x0c - Interrupt Enable"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x10 - Raw Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x14 - Enabled Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x18 - Clear Interrupt"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x1c - Receive FIFO Interrupt Trigger Value"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x20 - FIFO Clear"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "FIFO_DATA (r) register accessor: FIFO data\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_data`] module"] +#[doc(alias = "FIFO_DATA")] +pub type FifoData = crate::Reg; +#[doc = "FIFO data"] +pub mod fifo_data; +#[doc = "STATUS (r) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod irq_enb; +#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] module"] +#[doc(alias = "IRQ_RAW")] +pub type IrqRaw = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END (r) register accessor: Enabled Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] module"] +#[doc(alias = "IRQ_END")] +pub type IrqEnd = crate::Reg; +#[doc = "Enabled Interrupt Status"] +pub mod irq_end; +#[doc = "IRQ_CLR (w) register accessor: Clear Interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_clr`] module"] +#[doc(alias = "IRQ_CLR")] +pub type IrqClr = crate::Reg; +#[doc = "Clear Interrupt"] +pub mod irq_clr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Receive FIFO Interrupt Trigger Value"] +pub mod rxfifoirqtrg; +#[doc = "FIFO_CLR (rw) register accessor: FIFO Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "FIFO Clear"] +pub mod fifo_clr; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/adc/ctrl.rs b/va416xx/va416xx/src/adc/ctrl.rs new file mode 100644 index 0000000..3256cfa --- /dev/null +++ b/va416xx/va416xx/src/adc/ctrl.rs @@ -0,0 +1,105 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CHAN_EN` reader - Enables the channel for data collection"] +pub type ChanEnR = crate::FieldReader; +#[doc = "Field `CHAN_EN` writer - Enables the channel for data collection"] +pub type ChanEnW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CHAN_TAG_EN` reader - Enables the channel tag to be saved with the ADC data"] +pub type ChanTagEnR = crate::BitReader; +#[doc = "Field `CHAN_TAG_EN` writer - Enables the channel tag to be saved with the ADC data"] +pub type ChanTagEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SWEEP_EN` reader - ADC data acquisition for all enabled channel"] +pub type SweepEnR = crate::BitReader; +#[doc = "Field `SWEEP_EN` writer - ADC data acquisition for all enabled channel"] +pub type SweepEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXT_TRIG_EN` reader - Allows the external trigger to start analog acquisition"] +pub type ExtTrigEnR = crate::BitReader; +#[doc = "Field `EXT_TRIG_EN` writer - Allows the external trigger to start analog acquisition"] +pub type ExtTrigEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MANUAL_TRIG` reader - Starts analog acquisition"] +pub type ManualTrigR = crate::BitReader; +#[doc = "Field `MANUAL_TRIG` writer - Starts analog acquisition"] +pub type ManualTrigW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CONV_CNT` reader - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] +pub type ConvCntR = crate::FieldReader; +#[doc = "Field `CONV_CNT` writer - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] +pub type ConvCntW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - Enables the channel for data collection"] + #[inline(always)] + pub fn chan_en(&self) -> ChanEnR { + ChanEnR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"] + #[inline(always)] + pub fn chan_tag_en(&self) -> ChanTagEnR { + ChanTagEnR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - ADC data acquisition for all enabled channel"] + #[inline(always)] + pub fn sweep_en(&self) -> SweepEnR { + SweepEnR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"] + #[inline(always)] + pub fn ext_trig_en(&self) -> ExtTrigEnR { + ExtTrigEnR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Starts analog acquisition"] + #[inline(always)] + pub fn manual_trig(&self) -> ManualTrigR { + ManualTrigR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] + #[inline(always)] + pub fn conv_cnt(&self) -> ConvCntR { + ConvCntR::new(((self.bits >> 20) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Enables the channel for data collection"] + #[inline(always)] + pub fn chan_en(&mut self) -> ChanEnW<'_, CtrlSpec> { + ChanEnW::new(self, 0) + } + #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"] + #[inline(always)] + pub fn chan_tag_en(&mut self) -> ChanTagEnW<'_, CtrlSpec> { + ChanTagEnW::new(self, 16) + } + #[doc = "Bit 17 - ADC data acquisition for all enabled channel"] + #[inline(always)] + pub fn sweep_en(&mut self) -> SweepEnW<'_, CtrlSpec> { + SweepEnW::new(self, 17) + } + #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"] + #[inline(always)] + pub fn ext_trig_en(&mut self) -> ExtTrigEnW<'_, CtrlSpec> { + ExtTrigEnW::new(self, 18) + } + #[doc = "Bit 19 - Starts analog acquisition"] + #[inline(always)] + pub fn manual_trig(&mut self) -> ManualTrigW<'_, CtrlSpec> { + ManualTrigW::new(self, 19) + } + #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] + #[inline(always)] + pub fn conv_cnt(&mut self) -> ConvCntW<'_, CtrlSpec> { + ConvCntW::new(self, 20) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/va416xx/va416xx/src/adc/fifo_clr.rs b/va416xx/va416xx/src/adc/fifo_clr.rs new file mode 100644 index 0000000..d1a491b --- /dev/null +++ b/va416xx/va416xx/src/adc/fifo_clr.rs @@ -0,0 +1,26 @@ +#[doc = "Register `FIFO_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_CLR` writer - Clears the ADC FIFO. Always reads 0"] +pub type FifoClrW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clears the ADC FIFO. Always reads 0"] + #[inline(always)] + pub fn fifo_clr(&mut self) -> FifoClrW<'_, FifoClrSpec> { + FifoClrW::new(self, 0) + } +} +#[doc = "FIFO Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_clr::R`](R) reader structure"] +impl crate::Readable for FifoClrSpec {} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec {} diff --git a/va416xx/va416xx/src/adc/fifo_data.rs b/va416xx/va416xx/src/adc/fifo_data.rs new file mode 100644 index 0000000..70f03fa --- /dev/null +++ b/va416xx/va416xx/src/adc/fifo_data.rs @@ -0,0 +1,27 @@ +#[doc = "Register `FIFO_DATA` reader"] +pub type R = crate::R; +#[doc = "Field `ADC_DATA` reader - ADC acquisition data from the FIFO"] +pub type AdcDataR = crate::FieldReader; +#[doc = "Field `CHAN_TAG` reader - If enabled, this will include the number of the channel corresponding to the measurement"] +pub type ChanTagR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - ADC acquisition data from the FIFO"] + #[inline(always)] + pub fn adc_data(&self) -> AdcDataR { + AdcDataR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:15 - If enabled, this will include the number of the channel corresponding to the measurement"] + #[inline(always)] + pub fn chan_tag(&self) -> ChanTagR { + ChanTagR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +#[doc = "FIFO data\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoDataSpec; +impl crate::RegisterSpec for FifoDataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_data::R`](R) reader structure"] +impl crate::Readable for FifoDataSpec {} +#[doc = "`reset()` method sets FIFO_DATA to value 0"] +impl crate::Resettable for FifoDataSpec {} diff --git a/va416xx/va416xx/src/adc/irq_clr.rs b/va416xx/va416xx/src/adc/irq_clr.rs new file mode 100644 index 0000000..ba79a17 --- /dev/null +++ b/va416xx/va416xx/src/adc/irq_clr.rs @@ -0,0 +1,43 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_OFLOW` writer - Clears the FIFO overflow interrupt status. Always reads 0"] +pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_UFLOW` writer - Clears the FIFO underflow interrupt status. Always reads 0"] +pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_DONE` writer - Clears the ADC done interrupt status. Always reads 0"] +pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRIG_ERROR` writer - Clears the trigger error interrupt status. Always reads 0"] +pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"] + #[inline(always)] + pub fn fifo_oflow(&mut self) -> FifoOflowW<'_, IrqClrSpec> { + FifoOflowW::new(self, 0) + } + #[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"] + #[inline(always)] + pub fn fifo_uflow(&mut self) -> FifoUflowW<'_, IrqClrSpec> { + FifoUflowW::new(self, 1) + } + #[doc = "Bit 2 - Clears the ADC done interrupt status. Always reads 0"] + #[inline(always)] + pub fn adc_done(&mut self) -> AdcDoneW<'_, IrqClrSpec> { + AdcDoneW::new(self, 2) + } + #[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"] + #[inline(always)] + pub fn trig_error(&mut self) -> TrigErrorW<'_, IrqClrSpec> { + TrigErrorW::new(self, 3) + } +} +#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqClrSpec; +impl crate::RegisterSpec for IrqClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`irq_clr::W`](W) writer structure"] +impl crate::Writable for IrqClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IrqClrSpec {} diff --git a/va416xx/va416xx/src/adc/irq_enb.rs b/va416xx/va416xx/src/adc/irq_enb.rs new file mode 100644 index 0000000..f41514d --- /dev/null +++ b/va416xx/va416xx/src/adc/irq_enb.rs @@ -0,0 +1,119 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"] +pub type FifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"] +pub type FifoFullW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"] +pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"] +pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_DONE` reader - Enables the interrupt for an ADC data acquisition completion"] +pub type AdcDoneR = crate::BitReader; +#[doc = "Field `ADC_DONE` writer - Enables the interrupt for an ADC data acquisition completion"] +pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"] +pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub type FifoDepthTrigW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"] + #[inline(always)] + pub fn adc_done(&self) -> AdcDoneR { + AdcDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&mut self) -> FifoEmptyW<'_, IrqEnbSpec> { + FifoEmptyW::new(self, 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&mut self) -> FifoFullW<'_, IrqEnbSpec> { + FifoFullW::new(self, 1) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&mut self) -> FifoOflowW<'_, IrqEnbSpec> { + FifoOflowW::new(self, 2) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&mut self) -> FifoUflowW<'_, IrqEnbSpec> { + FifoUflowW::new(self, 3) + } + #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"] + #[inline(always)] + pub fn adc_done(&mut self) -> AdcDoneW<'_, IrqEnbSpec> { + AdcDoneW::new(self, 4) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&mut self) -> TrigErrorW<'_, IrqEnbSpec> { + TrigErrorW::new(self, 5) + } + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&mut self) -> FifoDepthTrigW<'_, IrqEnbSpec> { + FifoDepthTrigW::new(self, 6) + } +} +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va416xx/va416xx/src/adc/irq_end.rs b/va416xx/va416xx/src/adc/irq_end.rs new file mode 100644 index 0000000..54974cc --- /dev/null +++ b/va416xx/va416xx/src/adc/irq_end.rs @@ -0,0 +1,62 @@ +#[doc = "Register `IRQ_END` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty and the interrupt is enabled"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full and the interrupt is enabled"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred and the interrupt is enabled"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` reader - Indicates a FIFO underflow occurred and the interrupt is enabled"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done and the interrupt is enabled"] +pub type AdcDoneR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the FIFO is empty and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates a FIFO underflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates that a ADC conversion is done and the interrupt is enabled"] + #[inline(always)] + pub fn adc_done(&self) -> AdcDoneR { + AdcDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Enabled Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEndSpec; +impl crate::RegisterSpec for IrqEndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"] +impl crate::Readable for IrqEndSpec {} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IrqEndSpec {} diff --git a/va416xx/va416xx/src/adc/irq_raw.rs b/va416xx/va416xx/src/adc/irq_raw.rs new file mode 100644 index 0000000..5ca8edd --- /dev/null +++ b/va416xx/va416xx/src/adc/irq_raw.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` reader - Indicates data was unavailable when a new trigger for ADC update is received"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done"] +pub type AdcDoneR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the FIFO is empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates data was unavailable when a new trigger for ADC update is received"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates that a ADC conversion is done"] + #[inline(always)] + pub fn adc_done(&self) -> AdcDoneR { + AdcDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqRawSpec; +impl crate::RegisterSpec for IrqRawSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"] +impl crate::Readable for IrqRawSpec {} +#[doc = "`reset()` method sets IRQ_RAW to value 0x01"] +impl crate::Resettable for IrqRawSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/va416xx/va416xx/src/adc/perid.rs b/va416xx/va416xx/src/adc/perid.rs new file mode 100644 index 0000000..33365d7 --- /dev/null +++ b/va416xx/va416xx/src/adc/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0019_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0019_07e9; +} diff --git a/va416xx/va416xx/src/adc/rxfifoirqtrg.rs b/va416xx/va416xx/src/adc/rxfifoirqtrg.rs new file mode 100644 index 0000000..2fc9b76 --- /dev/null +++ b/va416xx/va416xx/src/adc/rxfifoirqtrg.rs @@ -0,0 +1,37 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub type LevelR = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&self) -> LevelR { + LevelR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&mut self) -> LevelW<'_, RxfifoirqtrgSpec> { + LevelW::new(self, 0) + } +} +#[doc = "Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0x10"] +impl crate::Resettable for RxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0x10; +} diff --git a/va416xx/va416xx/src/adc/status.rs b/va416xx/va416xx/src/adc/status.rs new file mode 100644 index 0000000..a5a3384 --- /dev/null +++ b/va416xx/va416xx/src/adc/status.rs @@ -0,0 +1,27 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_ENTRY_CNT` reader - Indicates the number of entries in the FIFO"] +pub type FifoEntryCntR = crate::FieldReader; +#[doc = "Field `ADC_BUSY` reader - Indicates an ADC data acquisition is in process"] +pub type AdcBusyR = crate::BitReader; +impl R { + #[doc = "Bits 0:5 - Indicates the number of entries in the FIFO"] + #[inline(always)] + pub fn fifo_entry_cnt(&self) -> FifoEntryCntR { + FifoEntryCntR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Indicates an ADC data acquisition is in process"] + #[inline(always)] + pub fn adc_busy(&self) -> AdcBusyR { + AdcBusyR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec {} diff --git a/va416xx/va416xx/src/can0.rs b/va416xx/va416xx/src/can0.rs new file mode 100644 index 0000000..46cda5e --- /dev/null +++ b/va416xx/va416xx/src/can0.rs @@ -0,0 +1,1568 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + cnstat_cmb0: CnstatCmb0, + tstp_cmb0: TstpCmb0, + data3_cmb0: Data3Cmb0, + data2_cmb0: Data2Cmb0, + data1_cmb0: Data1Cmb0, + data0_cmb0: Data0Cmb0, + id0_cmb0: Id0Cmb0, + id1_cmb0: Id1Cmb0, + cnstat_cmb1: CnstatCmb1, + tstp_cmb1: TstpCmb1, + data3_cmb1: Data3Cmb1, + data2_cmb1: Data2Cmb1, + data1_cmb1: Data1Cmb1, + data0_cmb1: Data0Cmb1, + id0_cmb1: Id0Cmb1, + id1_cmb1: Id1Cmb1, + cnstat_cmb2: CnstatCmb2, + tstp_cmb2: TstpCmb2, + data3_cmb2: Data3Cmb2, + data2_cmb2: Data2Cmb2, + data1_cmb2: Data1Cmb2, + data0_cmb2: Data0Cmb2, + id0_cmb2: Id0Cmb2, + id1_cmb2: Id1Cmb2, + cnstat_cmb3: CnstatCmb3, + tstp_cmb3: TstpCmb3, + data3_cmb3: Data3Cmb3, + data2_cmb3: Data2Cmb3, + data1_cmb3: Data1Cmb3, + data0_cmb3: Data0Cmb3, + id0_cmb3: Id0Cmb3, + id1_cmb3: Id1Cmb3, + cnstat_cmb4: CnstatCmb4, + tstp_cmb4: TstpCmb4, + data3_cmb4: Data3Cmb4, + data2_cmb4: Data2Cmb4, + data1_cmb4: Data1Cmb4, + data0_cmb4: Data0Cmb4, + id0_cmb4: Id0Cmb4, + id1_cmb4: Id1Cmb4, + cnstat_cmb5: CnstatCmb5, + tstp_cmb5: TstpCmb5, + data3_cmb5: Data3Cmb5, + data2_cmb5: Data2Cmb5, + data1_cmb5: Data1Cmb5, + data0_cmb5: Data0Cmb5, + id0_cmb5: Id0Cmb5, + id1_cmb5: Id1Cmb5, + cnstat_cmb6: CnstatCmb6, + tstp_cmb6: TstpCmb6, + data3_cmb6: Data3Cmb6, + data2_cmb6: Data2Cmb6, + data1_cmb6: Data1Cmb6, + data0_cmb6: Data0Cmb6, + id0_cmb6: Id0Cmb6, + id1_cmb6: Id1Cmb6, + cnstat_cmb7: CnstatCmb7, + tstp_cmb7: TstpCmb7, + data3_cmb7: Data3Cmb7, + data2_cmb7: Data2Cmb7, + data1_cmb7: Data1Cmb7, + data0_cmb7: Data0Cmb7, + id0_cmb7: Id0Cmb7, + id1_cmb7: Id1Cmb7, + cnstat_cmb8: CnstatCmb8, + tstp_cmb8: TstpCmb8, + data3_cmb8: Data3Cmb8, + data2_cmb8: Data2Cmb8, + data1_cmb8: Data1Cmb8, + data0_cmb8: Data0Cmb8, + id0_cmb8: Id0Cmb8, + id1_cmb8: Id1Cmb8, + cnstat_cmb9: CnstatCmb9, + tstp_cmb9: TstpCmb9, + data3_cmb9: Data3Cmb9, + data2_cmb9: Data2Cmb9, + data1_cmb9: Data1Cmb9, + data0_cmb9: Data0Cmb9, + id0_cmb9: Id0Cmb9, + id1_cmb9: Id1Cmb9, + cnstat_cmb10: CnstatCmb10, + tstp_cmb10: TstpCmb10, + data3_cmb10: Data3Cmb10, + data2_cmb10: Data2Cmb10, + data1_cmb10: Data1Cmb10, + data0_cmb10: Data0Cmb10, + id0_cmb10: Id0Cmb10, + id1_cmb10: Id1Cmb10, + cnstat_cmb11: CnstatCmb11, + tstp_cmb11: TstpCmb11, + data3_cmb11: Data3Cmb11, + data2_cmb11: Data2Cmb11, + data1_cmb11: Data1Cmb11, + data0_cmb11: Data0Cmb11, + id0_cmb11: Id0Cmb11, + id1_cmb11: Id1Cmb11, + cnstat_cmb12: CnstatCmb12, + tstp_cmb12: TstpCmb12, + data3_cmb12: Data3Cmb12, + data2_cmb12: Data2Cmb12, + data1_cmb12: Data1Cmb12, + data0_cmb12: Data0Cmb12, + id0_cmb12: Id0Cmb12, + id1_cmb12: Id1Cmb12, + cnstat_cmb13: CnstatCmb13, + tstp_cmb13: TstpCmb13, + data3_cmb13: Data3Cmb13, + data2_cmb13: Data2Cmb13, + data1_cmb13: Data1Cmb13, + data0_cmb13: Data0Cmb13, + id0_cmb13: Id0Cmb13, + id1_cmb13: Id1Cmb13, + cnstat_cmb14: CnstatCmb14, + tstp_cmb14: TstpCmb14, + data3_cmb14: Data3Cmb14, + data2_cmb14: Data2Cmb14, + data1_cmb14: Data1Cmb14, + data0_cmb14: Data0Cmb14, + id0_cmb14: Id0Cmb14, + id1_cmb14: Id1Cmb14, + cnstat_hcmb: CnstatHcmb, + tstp_hcmb: TstpHcmb, + data3_hcmb: Data3Hcmb, + data2_hcmb: Data2Hcmb, + data1_hcmb: Data1Hcmb, + data0_hcmb: Data0Hcmb, + id0_hcmb: Id0Hcmb, + id1_hcmb: Id1Hcmb, + cgcr: Cgcr, + ctim: Ctim, + gmskx: Gmskx, + gmskb: Gmskb, + bmskx: Bmskx, + bmskb: Bmskb, + cien: Cien, + cipnd: Cipnd, + ciclr: Ciclr, + cicen: Cicen, + cstpnd: Cstpnd, + canec: Canec, + cediag: Cediag, + ctmr: Ctmr, +} +impl RegisterBlock { + #[doc = "0x00 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb0(&self) -> &CnstatCmb0 { + &self.cnstat_cmb0 + } + #[doc = "0x04 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb0(&self) -> &TstpCmb0 { + &self.tstp_cmb0 + } + #[doc = "0x08 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb0(&self) -> &Data3Cmb0 { + &self.data3_cmb0 + } + #[doc = "0x0c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb0(&self) -> &Data2Cmb0 { + &self.data2_cmb0 + } + #[doc = "0x10 - CAN Frame Data Word 1"] + #[inline(always)] + pub const fn data1_cmb0(&self) -> &Data1Cmb0 { + &self.data1_cmb0 + } + #[doc = "0x14 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb0(&self) -> &Data0Cmb0 { + &self.data0_cmb0 + } + #[doc = "0x18 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb0(&self) -> &Id0Cmb0 { + &self.id0_cmb0 + } + #[doc = "0x1c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb0(&self) -> &Id1Cmb0 { + &self.id1_cmb0 + } + #[doc = "0x20 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb1(&self) -> &CnstatCmb1 { + &self.cnstat_cmb1 + } + #[doc = "0x24 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb1(&self) -> &TstpCmb1 { + &self.tstp_cmb1 + } + #[doc = "0x28 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb1(&self) -> &Data3Cmb1 { + &self.data3_cmb1 + } + #[doc = "0x2c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb1(&self) -> &Data2Cmb1 { + &self.data2_cmb1 + } + #[doc = "0x30 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb1(&self) -> &Data1Cmb1 { + &self.data1_cmb1 + } + #[doc = "0x34 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb1(&self) -> &Data0Cmb1 { + &self.data0_cmb1 + } + #[doc = "0x38 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb1(&self) -> &Id0Cmb1 { + &self.id0_cmb1 + } + #[doc = "0x3c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb1(&self) -> &Id1Cmb1 { + &self.id1_cmb1 + } + #[doc = "0x40 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb2(&self) -> &CnstatCmb2 { + &self.cnstat_cmb2 + } + #[doc = "0x44 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb2(&self) -> &TstpCmb2 { + &self.tstp_cmb2 + } + #[doc = "0x48 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb2(&self) -> &Data3Cmb2 { + &self.data3_cmb2 + } + #[doc = "0x4c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb2(&self) -> &Data2Cmb2 { + &self.data2_cmb2 + } + #[doc = "0x50 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb2(&self) -> &Data1Cmb2 { + &self.data1_cmb2 + } + #[doc = "0x54 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb2(&self) -> &Data0Cmb2 { + &self.data0_cmb2 + } + #[doc = "0x58 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb2(&self) -> &Id0Cmb2 { + &self.id0_cmb2 + } + #[doc = "0x5c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb2(&self) -> &Id1Cmb2 { + &self.id1_cmb2 + } + #[doc = "0x60 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb3(&self) -> &CnstatCmb3 { + &self.cnstat_cmb3 + } + #[doc = "0x64 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb3(&self) -> &TstpCmb3 { + &self.tstp_cmb3 + } + #[doc = "0x68 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb3(&self) -> &Data3Cmb3 { + &self.data3_cmb3 + } + #[doc = "0x6c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb3(&self) -> &Data2Cmb3 { + &self.data2_cmb3 + } + #[doc = "0x70 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb3(&self) -> &Data1Cmb3 { + &self.data1_cmb3 + } + #[doc = "0x74 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb3(&self) -> &Data0Cmb3 { + &self.data0_cmb3 + } + #[doc = "0x78 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb3(&self) -> &Id0Cmb3 { + &self.id0_cmb3 + } + #[doc = "0x7c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb3(&self) -> &Id1Cmb3 { + &self.id1_cmb3 + } + #[doc = "0x80 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb4(&self) -> &CnstatCmb4 { + &self.cnstat_cmb4 + } + #[doc = "0x84 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb4(&self) -> &TstpCmb4 { + &self.tstp_cmb4 + } + #[doc = "0x88 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb4(&self) -> &Data3Cmb4 { + &self.data3_cmb4 + } + #[doc = "0x8c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb4(&self) -> &Data2Cmb4 { + &self.data2_cmb4 + } + #[doc = "0x90 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb4(&self) -> &Data1Cmb4 { + &self.data1_cmb4 + } + #[doc = "0x94 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb4(&self) -> &Data0Cmb4 { + &self.data0_cmb4 + } + #[doc = "0x98 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb4(&self) -> &Id0Cmb4 { + &self.id0_cmb4 + } + #[doc = "0x9c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb4(&self) -> &Id1Cmb4 { + &self.id1_cmb4 + } + #[doc = "0xa0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb5(&self) -> &CnstatCmb5 { + &self.cnstat_cmb5 + } + #[doc = "0xa4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb5(&self) -> &TstpCmb5 { + &self.tstp_cmb5 + } + #[doc = "0xa8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb5(&self) -> &Data3Cmb5 { + &self.data3_cmb5 + } + #[doc = "0xac - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb5(&self) -> &Data2Cmb5 { + &self.data2_cmb5 + } + #[doc = "0xb0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb5(&self) -> &Data1Cmb5 { + &self.data1_cmb5 + } + #[doc = "0xb4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb5(&self) -> &Data0Cmb5 { + &self.data0_cmb5 + } + #[doc = "0xb8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb5(&self) -> &Id0Cmb5 { + &self.id0_cmb5 + } + #[doc = "0xbc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb5(&self) -> &Id1Cmb5 { + &self.id1_cmb5 + } + #[doc = "0xc0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb6(&self) -> &CnstatCmb6 { + &self.cnstat_cmb6 + } + #[doc = "0xc4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb6(&self) -> &TstpCmb6 { + &self.tstp_cmb6 + } + #[doc = "0xc8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb6(&self) -> &Data3Cmb6 { + &self.data3_cmb6 + } + #[doc = "0xcc - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb6(&self) -> &Data2Cmb6 { + &self.data2_cmb6 + } + #[doc = "0xd0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb6(&self) -> &Data1Cmb6 { + &self.data1_cmb6 + } + #[doc = "0xd4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb6(&self) -> &Data0Cmb6 { + &self.data0_cmb6 + } + #[doc = "0xd8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb6(&self) -> &Id0Cmb6 { + &self.id0_cmb6 + } + #[doc = "0xdc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb6(&self) -> &Id1Cmb6 { + &self.id1_cmb6 + } + #[doc = "0xe0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb7(&self) -> &CnstatCmb7 { + &self.cnstat_cmb7 + } + #[doc = "0xe4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb7(&self) -> &TstpCmb7 { + &self.tstp_cmb7 + } + #[doc = "0xe8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb7(&self) -> &Data3Cmb7 { + &self.data3_cmb7 + } + #[doc = "0xec - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb7(&self) -> &Data2Cmb7 { + &self.data2_cmb7 + } + #[doc = "0xf0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb7(&self) -> &Data1Cmb7 { + &self.data1_cmb7 + } + #[doc = "0xf4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb7(&self) -> &Data0Cmb7 { + &self.data0_cmb7 + } + #[doc = "0xf8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb7(&self) -> &Id0Cmb7 { + &self.id0_cmb7 + } + #[doc = "0xfc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb7(&self) -> &Id1Cmb7 { + &self.id1_cmb7 + } + #[doc = "0x100 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb8(&self) -> &CnstatCmb8 { + &self.cnstat_cmb8 + } + #[doc = "0x104 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb8(&self) -> &TstpCmb8 { + &self.tstp_cmb8 + } + #[doc = "0x108 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb8(&self) -> &Data3Cmb8 { + &self.data3_cmb8 + } + #[doc = "0x10c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb8(&self) -> &Data2Cmb8 { + &self.data2_cmb8 + } + #[doc = "0x110 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb8(&self) -> &Data1Cmb8 { + &self.data1_cmb8 + } + #[doc = "0x114 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb8(&self) -> &Data0Cmb8 { + &self.data0_cmb8 + } + #[doc = "0x118 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb8(&self) -> &Id0Cmb8 { + &self.id0_cmb8 + } + #[doc = "0x11c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb8(&self) -> &Id1Cmb8 { + &self.id1_cmb8 + } + #[doc = "0x120 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb9(&self) -> &CnstatCmb9 { + &self.cnstat_cmb9 + } + #[doc = "0x124 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb9(&self) -> &TstpCmb9 { + &self.tstp_cmb9 + } + #[doc = "0x128 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb9(&self) -> &Data3Cmb9 { + &self.data3_cmb9 + } + #[doc = "0x12c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb9(&self) -> &Data2Cmb9 { + &self.data2_cmb9 + } + #[doc = "0x130 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb9(&self) -> &Data1Cmb9 { + &self.data1_cmb9 + } + #[doc = "0x134 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb9(&self) -> &Data0Cmb9 { + &self.data0_cmb9 + } + #[doc = "0x138 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb9(&self) -> &Id0Cmb9 { + &self.id0_cmb9 + } + #[doc = "0x13c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb9(&self) -> &Id1Cmb9 { + &self.id1_cmb9 + } + #[doc = "0x140 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb10(&self) -> &CnstatCmb10 { + &self.cnstat_cmb10 + } + #[doc = "0x144 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb10(&self) -> &TstpCmb10 { + &self.tstp_cmb10 + } + #[doc = "0x148 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb10(&self) -> &Data3Cmb10 { + &self.data3_cmb10 + } + #[doc = "0x14c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb10(&self) -> &Data2Cmb10 { + &self.data2_cmb10 + } + #[doc = "0x150 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb10(&self) -> &Data1Cmb10 { + &self.data1_cmb10 + } + #[doc = "0x154 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb10(&self) -> &Data0Cmb10 { + &self.data0_cmb10 + } + #[doc = "0x158 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb10(&self) -> &Id0Cmb10 { + &self.id0_cmb10 + } + #[doc = "0x15c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb10(&self) -> &Id1Cmb10 { + &self.id1_cmb10 + } + #[doc = "0x160 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb11(&self) -> &CnstatCmb11 { + &self.cnstat_cmb11 + } + #[doc = "0x164 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb11(&self) -> &TstpCmb11 { + &self.tstp_cmb11 + } + #[doc = "0x168 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb11(&self) -> &Data3Cmb11 { + &self.data3_cmb11 + } + #[doc = "0x16c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb11(&self) -> &Data2Cmb11 { + &self.data2_cmb11 + } + #[doc = "0x170 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb11(&self) -> &Data1Cmb11 { + &self.data1_cmb11 + } + #[doc = "0x174 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb11(&self) -> &Data0Cmb11 { + &self.data0_cmb11 + } + #[doc = "0x178 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb11(&self) -> &Id0Cmb11 { + &self.id0_cmb11 + } + #[doc = "0x17c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb11(&self) -> &Id1Cmb11 { + &self.id1_cmb11 + } + #[doc = "0x180 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb12(&self) -> &CnstatCmb12 { + &self.cnstat_cmb12 + } + #[doc = "0x184 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb12(&self) -> &TstpCmb12 { + &self.tstp_cmb12 + } + #[doc = "0x188 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb12(&self) -> &Data3Cmb12 { + &self.data3_cmb12 + } + #[doc = "0x18c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb12(&self) -> &Data2Cmb12 { + &self.data2_cmb12 + } + #[doc = "0x190 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb12(&self) -> &Data1Cmb12 { + &self.data1_cmb12 + } + #[doc = "0x194 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb12(&self) -> &Data0Cmb12 { + &self.data0_cmb12 + } + #[doc = "0x198 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb12(&self) -> &Id0Cmb12 { + &self.id0_cmb12 + } + #[doc = "0x19c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb12(&self) -> &Id1Cmb12 { + &self.id1_cmb12 + } + #[doc = "0x1a0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb13(&self) -> &CnstatCmb13 { + &self.cnstat_cmb13 + } + #[doc = "0x1a4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb13(&self) -> &TstpCmb13 { + &self.tstp_cmb13 + } + #[doc = "0x1a8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb13(&self) -> &Data3Cmb13 { + &self.data3_cmb13 + } + #[doc = "0x1ac - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb13(&self) -> &Data2Cmb13 { + &self.data2_cmb13 + } + #[doc = "0x1b0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb13(&self) -> &Data1Cmb13 { + &self.data1_cmb13 + } + #[doc = "0x1b4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb13(&self) -> &Data0Cmb13 { + &self.data0_cmb13 + } + #[doc = "0x1b8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb13(&self) -> &Id0Cmb13 { + &self.id0_cmb13 + } + #[doc = "0x1bc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb13(&self) -> &Id1Cmb13 { + &self.id1_cmb13 + } + #[doc = "0x1c0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb14(&self) -> &CnstatCmb14 { + &self.cnstat_cmb14 + } + #[doc = "0x1c4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb14(&self) -> &TstpCmb14 { + &self.tstp_cmb14 + } + #[doc = "0x1c8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb14(&self) -> &Data3Cmb14 { + &self.data3_cmb14 + } + #[doc = "0x1cc - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb14(&self) -> &Data2Cmb14 { + &self.data2_cmb14 + } + #[doc = "0x1d0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb14(&self) -> &Data1Cmb14 { + &self.data1_cmb14 + } + #[doc = "0x1d4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb14(&self) -> &Data0Cmb14 { + &self.data0_cmb14 + } + #[doc = "0x1d8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb14(&self) -> &Id0Cmb14 { + &self.id0_cmb14 + } + #[doc = "0x1dc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb14(&self) -> &Id1Cmb14 { + &self.id1_cmb14 + } + #[doc = "0x1e0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_hcmb(&self) -> &CnstatHcmb { + &self.cnstat_hcmb + } + #[doc = "0x1e4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_hcmb(&self) -> &TstpHcmb { + &self.tstp_hcmb + } + #[doc = "0x1e8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_hcmb(&self) -> &Data3Hcmb { + &self.data3_hcmb + } + #[doc = "0x1ec - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_hcmb(&self) -> &Data2Hcmb { + &self.data2_hcmb + } + #[doc = "0x1f0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_hcmb(&self) -> &Data1Hcmb { + &self.data1_hcmb + } + #[doc = "0x1f4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_hcmb(&self) -> &Data0Hcmb { + &self.data0_hcmb + } + #[doc = "0x1f8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_hcmb(&self) -> &Id0Hcmb { + &self.id0_hcmb + } + #[doc = "0x1fc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_hcmb(&self) -> &Id1Hcmb { + &self.id1_hcmb + } + #[doc = "0x200 - CAN Global Configuration Register"] + #[inline(always)] + pub const fn cgcr(&self) -> &Cgcr { + &self.cgcr + } + #[doc = "0x204 - CAN Timing Register"] + #[inline(always)] + pub const fn ctim(&self) -> &Ctim { + &self.ctim + } + #[doc = "0x208 - CAN Global Mask Extension"] + #[inline(always)] + pub const fn gmskx(&self) -> &Gmskx { + &self.gmskx + } + #[doc = "0x20c - CAN Global Mask Base"] + #[inline(always)] + pub const fn gmskb(&self) -> &Gmskb { + &self.gmskb + } + #[doc = "0x210 - CAN Basic Mask Extension"] + #[inline(always)] + pub const fn bmskx(&self) -> &Bmskx { + &self.bmskx + } + #[doc = "0x214 - CAN Basic Mask Base"] + #[inline(always)] + pub const fn bmskb(&self) -> &Bmskb { + &self.bmskb + } + #[doc = "0x218 - CAN Interrupt Enable Register"] + #[inline(always)] + pub const fn cien(&self) -> &Cien { + &self.cien + } + #[doc = "0x21c - CAN Interrupt Pending Register"] + #[inline(always)] + pub const fn cipnd(&self) -> &Cipnd { + &self.cipnd + } + #[doc = "0x220 - CAN Interrupt Clear Register"] + #[inline(always)] + pub const fn ciclr(&self) -> &Ciclr { + &self.ciclr + } + #[doc = "0x224 - CAN Interrupt Code Enable Register"] + #[inline(always)] + pub const fn cicen(&self) -> &Cicen { + &self.cicen + } + #[doc = "0x228 - CAN Status Pending Register"] + #[inline(always)] + pub const fn cstpnd(&self) -> &Cstpnd { + &self.cstpnd + } + #[doc = "0x22c - CAN Error Counter Register"] + #[inline(always)] + pub const fn canec(&self) -> &Canec { + &self.canec + } + #[doc = "0x230 - CAN Error Diagnostic Register"] + #[inline(always)] + pub const fn cediag(&self) -> &Cediag { + &self.cediag + } + #[doc = "0x234 - CAN Timer Register"] + #[inline(always)] + pub const fn ctmr(&self) -> &Ctmr { + &self.ctmr + } +} +#[doc = "CNSTAT_CMB0 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb0`] module"] +#[doc(alias = "CNSTAT_CMB0")] +pub type CnstatCmb0 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb0; +#[doc = "TSTP_CMB0 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb0`] module"] +#[doc(alias = "TSTP_CMB0")] +pub type TstpCmb0 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb0; +#[doc = "DATA3_CMB0 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb0`] module"] +#[doc(alias = "DATA3_CMB0")] +pub type Data3Cmb0 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb0; +#[doc = "DATA2_CMB0 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb0`] module"] +#[doc(alias = "DATA2_CMB0")] +pub type Data2Cmb0 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb0; +#[doc = "DATA1_CMB0 (rw) register accessor: CAN Frame Data Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb0`] module"] +#[doc(alias = "DATA1_CMB0")] +pub type Data1Cmb0 = crate::Reg; +#[doc = "CAN Frame Data Word 1"] +pub mod data1_cmb0; +#[doc = "DATA0_CMB0 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb0`] module"] +#[doc(alias = "DATA0_CMB0")] +pub type Data0Cmb0 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb0; +#[doc = "ID0_CMB0 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb0`] module"] +#[doc(alias = "ID0_CMB0")] +pub type Id0Cmb0 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb0; +#[doc = "ID1_CMB0 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb0`] module"] +#[doc(alias = "ID1_CMB0")] +pub type Id1Cmb0 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb0; +#[doc = "CNSTAT_CMB1 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb1`] module"] +#[doc(alias = "CNSTAT_CMB1")] +pub type CnstatCmb1 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb1; +#[doc = "TSTP_CMB1 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb1`] module"] +#[doc(alias = "TSTP_CMB1")] +pub type TstpCmb1 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb1; +#[doc = "DATA3_CMB1 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb1`] module"] +#[doc(alias = "DATA3_CMB1")] +pub type Data3Cmb1 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb1; +#[doc = "DATA2_CMB1 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb1`] module"] +#[doc(alias = "DATA2_CMB1")] +pub type Data2Cmb1 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb1; +#[doc = "DATA1_CMB1 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb1`] module"] +#[doc(alias = "DATA1_CMB1")] +pub type Data1Cmb1 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb1; +#[doc = "DATA0_CMB1 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb1`] module"] +#[doc(alias = "DATA0_CMB1")] +pub type Data0Cmb1 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb1; +#[doc = "ID0_CMB1 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb1`] module"] +#[doc(alias = "ID0_CMB1")] +pub type Id0Cmb1 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb1; +#[doc = "ID1_CMB1 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb1`] module"] +#[doc(alias = "ID1_CMB1")] +pub type Id1Cmb1 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb1; +#[doc = "CNSTAT_CMB2 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb2`] module"] +#[doc(alias = "CNSTAT_CMB2")] +pub type CnstatCmb2 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb2; +#[doc = "TSTP_CMB2 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb2`] module"] +#[doc(alias = "TSTP_CMB2")] +pub type TstpCmb2 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb2; +#[doc = "DATA3_CMB2 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb2`] module"] +#[doc(alias = "DATA3_CMB2")] +pub type Data3Cmb2 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb2; +#[doc = "DATA2_CMB2 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb2`] module"] +#[doc(alias = "DATA2_CMB2")] +pub type Data2Cmb2 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb2; +#[doc = "DATA1_CMB2 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb2`] module"] +#[doc(alias = "DATA1_CMB2")] +pub type Data1Cmb2 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb2; +#[doc = "DATA0_CMB2 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb2`] module"] +#[doc(alias = "DATA0_CMB2")] +pub type Data0Cmb2 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb2; +#[doc = "ID0_CMB2 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb2`] module"] +#[doc(alias = "ID0_CMB2")] +pub type Id0Cmb2 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb2; +#[doc = "ID1_CMB2 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb2`] module"] +#[doc(alias = "ID1_CMB2")] +pub type Id1Cmb2 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb2; +#[doc = "CNSTAT_CMB3 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb3`] module"] +#[doc(alias = "CNSTAT_CMB3")] +pub type CnstatCmb3 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb3; +#[doc = "TSTP_CMB3 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb3`] module"] +#[doc(alias = "TSTP_CMB3")] +pub type TstpCmb3 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb3; +#[doc = "DATA3_CMB3 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb3`] module"] +#[doc(alias = "DATA3_CMB3")] +pub type Data3Cmb3 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb3; +#[doc = "DATA2_CMB3 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb3`] module"] +#[doc(alias = "DATA2_CMB3")] +pub type Data2Cmb3 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb3; +#[doc = "DATA1_CMB3 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb3`] module"] +#[doc(alias = "DATA1_CMB3")] +pub type Data1Cmb3 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb3; +#[doc = "DATA0_CMB3 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb3`] module"] +#[doc(alias = "DATA0_CMB3")] +pub type Data0Cmb3 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb3; +#[doc = "ID0_CMB3 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb3`] module"] +#[doc(alias = "ID0_CMB3")] +pub type Id0Cmb3 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb3; +#[doc = "ID1_CMB3 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb3`] module"] +#[doc(alias = "ID1_CMB3")] +pub type Id1Cmb3 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb3; +#[doc = "CNSTAT_CMB4 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb4`] module"] +#[doc(alias = "CNSTAT_CMB4")] +pub type CnstatCmb4 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb4; +#[doc = "TSTP_CMB4 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb4`] module"] +#[doc(alias = "TSTP_CMB4")] +pub type TstpCmb4 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb4; +#[doc = "DATA3_CMB4 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb4`] module"] +#[doc(alias = "DATA3_CMB4")] +pub type Data3Cmb4 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb4; +#[doc = "DATA2_CMB4 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb4`] module"] +#[doc(alias = "DATA2_CMB4")] +pub type Data2Cmb4 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb4; +#[doc = "DATA1_CMB4 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb4`] module"] +#[doc(alias = "DATA1_CMB4")] +pub type Data1Cmb4 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb4; +#[doc = "DATA0_CMB4 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb4`] module"] +#[doc(alias = "DATA0_CMB4")] +pub type Data0Cmb4 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb4; +#[doc = "ID0_CMB4 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb4`] module"] +#[doc(alias = "ID0_CMB4")] +pub type Id0Cmb4 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb4; +#[doc = "ID1_CMB4 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb4`] module"] +#[doc(alias = "ID1_CMB4")] +pub type Id1Cmb4 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb4; +#[doc = "CNSTAT_CMB5 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb5`] module"] +#[doc(alias = "CNSTAT_CMB5")] +pub type CnstatCmb5 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb5; +#[doc = "TSTP_CMB5 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb5`] module"] +#[doc(alias = "TSTP_CMB5")] +pub type TstpCmb5 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb5; +#[doc = "DATA3_CMB5 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb5`] module"] +#[doc(alias = "DATA3_CMB5")] +pub type Data3Cmb5 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb5; +#[doc = "DATA2_CMB5 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb5`] module"] +#[doc(alias = "DATA2_CMB5")] +pub type Data2Cmb5 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb5; +#[doc = "DATA1_CMB5 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb5`] module"] +#[doc(alias = "DATA1_CMB5")] +pub type Data1Cmb5 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb5; +#[doc = "DATA0_CMB5 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb5`] module"] +#[doc(alias = "DATA0_CMB5")] +pub type Data0Cmb5 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb5; +#[doc = "ID0_CMB5 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb5`] module"] +#[doc(alias = "ID0_CMB5")] +pub type Id0Cmb5 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb5; +#[doc = "ID1_CMB5 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb5`] module"] +#[doc(alias = "ID1_CMB5")] +pub type Id1Cmb5 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb5; +#[doc = "CNSTAT_CMB6 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb6`] module"] +#[doc(alias = "CNSTAT_CMB6")] +pub type CnstatCmb6 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb6; +#[doc = "TSTP_CMB6 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb6`] module"] +#[doc(alias = "TSTP_CMB6")] +pub type TstpCmb6 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb6; +#[doc = "DATA3_CMB6 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb6`] module"] +#[doc(alias = "DATA3_CMB6")] +pub type Data3Cmb6 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb6; +#[doc = "DATA2_CMB6 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb6`] module"] +#[doc(alias = "DATA2_CMB6")] +pub type Data2Cmb6 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb6; +#[doc = "DATA1_CMB6 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb6`] module"] +#[doc(alias = "DATA1_CMB6")] +pub type Data1Cmb6 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb6; +#[doc = "DATA0_CMB6 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb6`] module"] +#[doc(alias = "DATA0_CMB6")] +pub type Data0Cmb6 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb6; +#[doc = "ID0_CMB6 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb6`] module"] +#[doc(alias = "ID0_CMB6")] +pub type Id0Cmb6 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb6; +#[doc = "ID1_CMB6 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb6`] module"] +#[doc(alias = "ID1_CMB6")] +pub type Id1Cmb6 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb6; +#[doc = "CNSTAT_CMB7 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb7`] module"] +#[doc(alias = "CNSTAT_CMB7")] +pub type CnstatCmb7 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb7; +#[doc = "TSTP_CMB7 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb7`] module"] +#[doc(alias = "TSTP_CMB7")] +pub type TstpCmb7 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb7; +#[doc = "DATA3_CMB7 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb7`] module"] +#[doc(alias = "DATA3_CMB7")] +pub type Data3Cmb7 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb7; +#[doc = "DATA2_CMB7 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb7`] module"] +#[doc(alias = "DATA2_CMB7")] +pub type Data2Cmb7 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb7; +#[doc = "DATA1_CMB7 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb7`] module"] +#[doc(alias = "DATA1_CMB7")] +pub type Data1Cmb7 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb7; +#[doc = "DATA0_CMB7 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb7`] module"] +#[doc(alias = "DATA0_CMB7")] +pub type Data0Cmb7 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb7; +#[doc = "ID0_CMB7 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb7`] module"] +#[doc(alias = "ID0_CMB7")] +pub type Id0Cmb7 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb7; +#[doc = "ID1_CMB7 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb7`] module"] +#[doc(alias = "ID1_CMB7")] +pub type Id1Cmb7 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb7; +#[doc = "CNSTAT_CMB8 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb8`] module"] +#[doc(alias = "CNSTAT_CMB8")] +pub type CnstatCmb8 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb8; +#[doc = "TSTP_CMB8 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb8`] module"] +#[doc(alias = "TSTP_CMB8")] +pub type TstpCmb8 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb8; +#[doc = "DATA3_CMB8 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb8`] module"] +#[doc(alias = "DATA3_CMB8")] +pub type Data3Cmb8 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb8; +#[doc = "DATA2_CMB8 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb8`] module"] +#[doc(alias = "DATA2_CMB8")] +pub type Data2Cmb8 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb8; +#[doc = "DATA1_CMB8 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb8`] module"] +#[doc(alias = "DATA1_CMB8")] +pub type Data1Cmb8 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb8; +#[doc = "DATA0_CMB8 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb8`] module"] +#[doc(alias = "DATA0_CMB8")] +pub type Data0Cmb8 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb8; +#[doc = "ID0_CMB8 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb8`] module"] +#[doc(alias = "ID0_CMB8")] +pub type Id0Cmb8 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb8; +#[doc = "ID1_CMB8 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb8`] module"] +#[doc(alias = "ID1_CMB8")] +pub type Id1Cmb8 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb8; +#[doc = "CNSTAT_CMB9 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb9`] module"] +#[doc(alias = "CNSTAT_CMB9")] +pub type CnstatCmb9 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb9; +#[doc = "TSTP_CMB9 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb9`] module"] +#[doc(alias = "TSTP_CMB9")] +pub type TstpCmb9 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb9; +#[doc = "DATA3_CMB9 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb9`] module"] +#[doc(alias = "DATA3_CMB9")] +pub type Data3Cmb9 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb9; +#[doc = "DATA2_CMB9 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb9`] module"] +#[doc(alias = "DATA2_CMB9")] +pub type Data2Cmb9 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb9; +#[doc = "DATA1_CMB9 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb9`] module"] +#[doc(alias = "DATA1_CMB9")] +pub type Data1Cmb9 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb9; +#[doc = "DATA0_CMB9 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb9`] module"] +#[doc(alias = "DATA0_CMB9")] +pub type Data0Cmb9 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb9; +#[doc = "ID0_CMB9 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb9`] module"] +#[doc(alias = "ID0_CMB9")] +pub type Id0Cmb9 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb9; +#[doc = "ID1_CMB9 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb9`] module"] +#[doc(alias = "ID1_CMB9")] +pub type Id1Cmb9 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb9; +#[doc = "CNSTAT_CMB10 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb10`] module"] +#[doc(alias = "CNSTAT_CMB10")] +pub type CnstatCmb10 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb10; +#[doc = "TSTP_CMB10 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb10`] module"] +#[doc(alias = "TSTP_CMB10")] +pub type TstpCmb10 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb10; +#[doc = "DATA3_CMB10 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb10`] module"] +#[doc(alias = "DATA3_CMB10")] +pub type Data3Cmb10 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb10; +#[doc = "DATA2_CMB10 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb10`] module"] +#[doc(alias = "DATA2_CMB10")] +pub type Data2Cmb10 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb10; +#[doc = "DATA1_CMB10 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb10`] module"] +#[doc(alias = "DATA1_CMB10")] +pub type Data1Cmb10 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb10; +#[doc = "DATA0_CMB10 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb10`] module"] +#[doc(alias = "DATA0_CMB10")] +pub type Data0Cmb10 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb10; +#[doc = "ID0_CMB10 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb10`] module"] +#[doc(alias = "ID0_CMB10")] +pub type Id0Cmb10 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb10; +#[doc = "ID1_CMB10 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb10`] module"] +#[doc(alias = "ID1_CMB10")] +pub type Id1Cmb10 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb10; +#[doc = "CNSTAT_CMB11 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb11`] module"] +#[doc(alias = "CNSTAT_CMB11")] +pub type CnstatCmb11 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb11; +#[doc = "TSTP_CMB11 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb11`] module"] +#[doc(alias = "TSTP_CMB11")] +pub type TstpCmb11 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb11; +#[doc = "DATA3_CMB11 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb11`] module"] +#[doc(alias = "DATA3_CMB11")] +pub type Data3Cmb11 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb11; +#[doc = "DATA2_CMB11 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb11`] module"] +#[doc(alias = "DATA2_CMB11")] +pub type Data2Cmb11 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb11; +#[doc = "DATA1_CMB11 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb11`] module"] +#[doc(alias = "DATA1_CMB11")] +pub type Data1Cmb11 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb11; +#[doc = "DATA0_CMB11 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb11`] module"] +#[doc(alias = "DATA0_CMB11")] +pub type Data0Cmb11 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb11; +#[doc = "ID0_CMB11 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb11`] module"] +#[doc(alias = "ID0_CMB11")] +pub type Id0Cmb11 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb11; +#[doc = "ID1_CMB11 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb11`] module"] +#[doc(alias = "ID1_CMB11")] +pub type Id1Cmb11 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb11; +#[doc = "CNSTAT_CMB12 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb12`] module"] +#[doc(alias = "CNSTAT_CMB12")] +pub type CnstatCmb12 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb12; +#[doc = "TSTP_CMB12 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb12`] module"] +#[doc(alias = "TSTP_CMB12")] +pub type TstpCmb12 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb12; +#[doc = "DATA3_CMB12 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb12`] module"] +#[doc(alias = "DATA3_CMB12")] +pub type Data3Cmb12 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb12; +#[doc = "DATA2_CMB12 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb12`] module"] +#[doc(alias = "DATA2_CMB12")] +pub type Data2Cmb12 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb12; +#[doc = "DATA1_CMB12 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb12`] module"] +#[doc(alias = "DATA1_CMB12")] +pub type Data1Cmb12 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb12; +#[doc = "DATA0_CMB12 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb12`] module"] +#[doc(alias = "DATA0_CMB12")] +pub type Data0Cmb12 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb12; +#[doc = "ID0_CMB12 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb12`] module"] +#[doc(alias = "ID0_CMB12")] +pub type Id0Cmb12 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb12; +#[doc = "ID1_CMB12 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb12`] module"] +#[doc(alias = "ID1_CMB12")] +pub type Id1Cmb12 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb12; +#[doc = "CNSTAT_CMB13 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb13`] module"] +#[doc(alias = "CNSTAT_CMB13")] +pub type CnstatCmb13 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb13; +#[doc = "TSTP_CMB13 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb13`] module"] +#[doc(alias = "TSTP_CMB13")] +pub type TstpCmb13 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb13; +#[doc = "DATA3_CMB13 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb13`] module"] +#[doc(alias = "DATA3_CMB13")] +pub type Data3Cmb13 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb13; +#[doc = "DATA2_CMB13 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb13`] module"] +#[doc(alias = "DATA2_CMB13")] +pub type Data2Cmb13 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb13; +#[doc = "DATA1_CMB13 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb13`] module"] +#[doc(alias = "DATA1_CMB13")] +pub type Data1Cmb13 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb13; +#[doc = "DATA0_CMB13 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb13`] module"] +#[doc(alias = "DATA0_CMB13")] +pub type Data0Cmb13 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb13; +#[doc = "ID0_CMB13 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb13`] module"] +#[doc(alias = "ID0_CMB13")] +pub type Id0Cmb13 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb13; +#[doc = "ID1_CMB13 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb13`] module"] +#[doc(alias = "ID1_CMB13")] +pub type Id1Cmb13 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb13; +#[doc = "CNSTAT_CMB14 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb14`] module"] +#[doc(alias = "CNSTAT_CMB14")] +pub type CnstatCmb14 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb14; +#[doc = "TSTP_CMB14 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb14`] module"] +#[doc(alias = "TSTP_CMB14")] +pub type TstpCmb14 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb14; +#[doc = "DATA3_CMB14 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb14`] module"] +#[doc(alias = "DATA3_CMB14")] +pub type Data3Cmb14 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb14; +#[doc = "DATA2_CMB14 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb14`] module"] +#[doc(alias = "DATA2_CMB14")] +pub type Data2Cmb14 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb14; +#[doc = "DATA1_CMB14 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb14`] module"] +#[doc(alias = "DATA1_CMB14")] +pub type Data1Cmb14 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb14; +#[doc = "DATA0_CMB14 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb14`] module"] +#[doc(alias = "DATA0_CMB14")] +pub type Data0Cmb14 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb14; +#[doc = "ID0_CMB14 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb14`] module"] +#[doc(alias = "ID0_CMB14")] +pub type Id0Cmb14 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb14; +#[doc = "ID1_CMB14 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb14`] module"] +#[doc(alias = "ID1_CMB14")] +pub type Id1Cmb14 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb14; +#[doc = "CNSTAT_HCMB (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_hcmb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_hcmb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_hcmb`] module"] +#[doc(alias = "CNSTAT_HCMB")] +pub type CnstatHcmb = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_hcmb; +#[doc = "TSTP_HCMB (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_hcmb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_hcmb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_hcmb`] module"] +#[doc(alias = "TSTP_HCMB")] +pub type TstpHcmb = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_hcmb; +#[doc = "DATA3_HCMB (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_hcmb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_hcmb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_hcmb`] module"] +#[doc(alias = "DATA3_HCMB")] +pub type Data3Hcmb = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_hcmb; +#[doc = "DATA2_HCMB (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_hcmb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_hcmb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_hcmb`] module"] +#[doc(alias = "DATA2_HCMB")] +pub type Data2Hcmb = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_hcmb; +#[doc = "DATA1_HCMB (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_hcmb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_hcmb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_hcmb`] module"] +#[doc(alias = "DATA1_HCMB")] +pub type Data1Hcmb = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_hcmb; +#[doc = "DATA0_HCMB (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_hcmb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_hcmb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_hcmb`] module"] +#[doc(alias = "DATA0_HCMB")] +pub type Data0Hcmb = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_hcmb; +#[doc = "ID0_HCMB (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_hcmb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_hcmb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_hcmb`] module"] +#[doc(alias = "ID0_HCMB")] +pub type Id0Hcmb = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_hcmb; +#[doc = "ID1_HCMB (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_hcmb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_hcmb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_hcmb`] module"] +#[doc(alias = "ID1_HCMB")] +pub type Id1Hcmb = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_hcmb; +#[doc = "CGCR (rw) register accessor: CAN Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cgcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cgcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgcr`] module"] +#[doc(alias = "CGCR")] +pub type Cgcr = crate::Reg; +#[doc = "CAN Global Configuration Register"] +pub mod cgcr; +#[doc = "CTIM (rw) register accessor: CAN Timing Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctim`] module"] +#[doc(alias = "CTIM")] +pub type Ctim = crate::Reg; +#[doc = "CAN Timing Register"] +pub mod ctim; +#[doc = "GMSKX (rw) register accessor: CAN Global Mask Extension\n\nYou can [`read`](crate::Reg::read) this register and get [`gmskx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gmskx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmskx`] module"] +#[doc(alias = "GMSKX")] +pub type Gmskx = crate::Reg; +#[doc = "CAN Global Mask Extension"] +pub mod gmskx; +#[doc = "GMSKB (rw) register accessor: CAN Global Mask Base\n\nYou can [`read`](crate::Reg::read) this register and get [`gmskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gmskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmskb`] module"] +#[doc(alias = "GMSKB")] +pub type Gmskb = crate::Reg; +#[doc = "CAN Global Mask Base"] +pub mod gmskb; +#[doc = "BMSKX (rw) register accessor: CAN Basic Mask Extension\n\nYou can [`read`](crate::Reg::read) this register and get [`bmskx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bmskx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmskx`] module"] +#[doc(alias = "BMSKX")] +pub type Bmskx = crate::Reg; +#[doc = "CAN Basic Mask Extension"] +pub mod bmskx; +#[doc = "BMSKB (rw) register accessor: CAN Basic Mask Base\n\nYou can [`read`](crate::Reg::read) this register and get [`bmskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bmskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmskb`] module"] +#[doc(alias = "BMSKB")] +pub type Bmskb = crate::Reg; +#[doc = "CAN Basic Mask Base"] +pub mod bmskb; +#[doc = "CIEN (rw) register accessor: CAN Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cien`] module"] +#[doc(alias = "CIEN")] +pub type Cien = crate::Reg; +#[doc = "CAN Interrupt Enable Register"] +pub mod cien; +#[doc = "CIPND (rw) register accessor: CAN Interrupt Pending Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cipnd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cipnd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cipnd`] module"] +#[doc(alias = "CIPND")] +pub type Cipnd = crate::Reg; +#[doc = "CAN Interrupt Pending Register"] +pub mod cipnd; +#[doc = "CICLR (rw) register accessor: CAN Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ciclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ciclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ciclr`] module"] +#[doc(alias = "CICLR")] +pub type Ciclr = crate::Reg; +#[doc = "CAN Interrupt Clear Register"] +pub mod ciclr; +#[doc = "CICEN (rw) register accessor: CAN Interrupt Code Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cicen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cicen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cicen`] module"] +#[doc(alias = "CICEN")] +pub type Cicen = crate::Reg; +#[doc = "CAN Interrupt Code Enable Register"] +pub mod cicen; +#[doc = "CSTPND (rw) register accessor: CAN Status Pending Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cstpnd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cstpnd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cstpnd`] module"] +#[doc(alias = "CSTPND")] +pub type Cstpnd = crate::Reg; +#[doc = "CAN Status Pending Register"] +pub mod cstpnd; +#[doc = "CANEC (rw) register accessor: CAN Error Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`canec::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`canec::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@canec`] module"] +#[doc(alias = "CANEC")] +pub type Canec = crate::Reg; +#[doc = "CAN Error Counter Register"] +pub mod canec; +#[doc = "CEDIAG (rw) register accessor: CAN Error Diagnostic Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cediag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cediag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cediag`] module"] +#[doc(alias = "CEDIAG")] +pub type Cediag = crate::Reg; +#[doc = "CAN Error Diagnostic Register"] +pub mod cediag; +#[doc = "CTMR (rw) register accessor: CAN Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctmr`] module"] +#[doc(alias = "CTMR")] +pub type Ctmr = crate::Reg; +#[doc = "CAN Timer Register"] +pub mod ctmr; diff --git a/va416xx/va416xx/src/can0/bmskb.rs b/va416xx/va416xx/src/can0/bmskb.rs new file mode 100644 index 0000000..8c5282b --- /dev/null +++ b/va416xx/va416xx/src/can0/bmskb.rs @@ -0,0 +1,77 @@ +#[doc = "Register `BMSKB` reader"] +pub type R = crate::R; +#[doc = "Register `BMSKB` writer"] +pub type W = crate::W; +#[doc = "Field `BM0` reader - BM\\[17:15\\] - Unused in standard, ID\\[17:15\\] in extended"] +pub type Bm0R = crate::FieldReader; +#[doc = "Field `BM0` writer - BM\\[17:15\\] - Unused in standard, ID\\[17:15\\] in extended"] +pub type Bm0W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IDE` reader - Identifier Extension Bit"] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - Identifier Extension Bit"] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTR` reader - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BM1` reader - BM\\[28:18\\] - ID\\[10:0\\] in standard, ID\\[28:18\\] in extended"] +pub type Bm1R = crate::FieldReader; +#[doc = "Field `BM1` writer - BM\\[28:18\\] - ID\\[10:0\\] in standard, ID\\[28:18\\] in extended"] +pub type Bm1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:2 - BM\\[17:15\\] - Unused in standard, ID\\[17:15\\] in extended"] + #[inline(always)] + pub fn bm0(&self) -> Bm0R { + Bm0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:15 - BM\\[28:18\\] - ID\\[10:0\\] in standard, ID\\[28:18\\] in extended"] + #[inline(always)] + pub fn bm1(&self) -> Bm1R { + Bm1R::new(((self.bits >> 5) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - BM\\[17:15\\] - Unused in standard, ID\\[17:15\\] in extended"] + #[inline(always)] + pub fn bm0(&mut self) -> Bm0W<'_, BmskbSpec> { + Bm0W::new(self, 0) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&mut self) -> IdeW<'_, BmskbSpec> { + IdeW::new(self, 3) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW<'_, BmskbSpec> { + RtrW::new(self, 4) + } + #[doc = "Bits 5:15 - BM\\[28:18\\] - ID\\[10:0\\] in standard, ID\\[28:18\\] in extended"] + #[inline(always)] + pub fn bm1(&mut self) -> Bm1W<'_, BmskbSpec> { + Bm1W::new(self, 5) + } +} +#[doc = "CAN Basic Mask Base\n\nYou can [`read`](crate::Reg::read) this register and get [`bmskb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bmskb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BmskbSpec; +impl crate::RegisterSpec for BmskbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bmskb::R`](R) reader structure"] +impl crate::Readable for BmskbSpec {} +#[doc = "`write(|w| ..)` method takes [`bmskb::W`](W) writer structure"] +impl crate::Writable for BmskbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BMSKB to value 0"] +impl crate::Resettable for BmskbSpec {} diff --git a/va416xx/va416xx/src/can0/bmskx.rs b/va416xx/va416xx/src/can0/bmskx.rs new file mode 100644 index 0000000..99bd604 --- /dev/null +++ b/va416xx/va416xx/src/can0/bmskx.rs @@ -0,0 +1,49 @@ +#[doc = "Register `BMSKX` reader"] +pub type R = crate::R; +#[doc = "Register `BMSKX` writer"] +pub type W = crate::W; +#[doc = "Field `XRTR` reader - Extended Remote transmission Request Bit"] +pub type XrtrR = crate::BitReader; +#[doc = "Field `XRTR` writer - Extended Remote transmission Request Bit"] +pub type XrtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BM` reader - BM\\[14:0\\] used when an extended frame is received. ID\\[14:0\\] in extended, unused standard"] +pub type BmR = crate::FieldReader; +#[doc = "Field `BM` writer - BM\\[14:0\\] used when an extended frame is received. ID\\[14:0\\] in extended, unused standard"] +pub type BmW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&self) -> XrtrR { + XrtrR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:15 - BM\\[14:0\\] used when an extended frame is received. ID\\[14:0\\] in extended, unused standard"] + #[inline(always)] + pub fn bm(&self) -> BmR { + BmR::new(((self.bits >> 1) & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&mut self) -> XrtrW<'_, BmskxSpec> { + XrtrW::new(self, 0) + } + #[doc = "Bits 1:15 - BM\\[14:0\\] used when an extended frame is received. ID\\[14:0\\] in extended, unused standard"] + #[inline(always)] + pub fn bm(&mut self) -> BmW<'_, BmskxSpec> { + BmW::new(self, 1) + } +} +#[doc = "CAN Basic Mask Extension\n\nYou can [`read`](crate::Reg::read) this register and get [`bmskx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bmskx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BmskxSpec; +impl crate::RegisterSpec for BmskxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bmskx::R`](R) reader structure"] +impl crate::Readable for BmskxSpec {} +#[doc = "`write(|w| ..)` method takes [`bmskx::W`](W) writer structure"] +impl crate::Writable for BmskxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets BMSKX to value 0"] +impl crate::Resettable for BmskxSpec {} diff --git a/va416xx/va416xx/src/can0/canec.rs b/va416xx/va416xx/src/can0/canec.rs new file mode 100644 index 0000000..18f9ac1 --- /dev/null +++ b/va416xx/va416xx/src/can0/canec.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CANEC` reader"] +pub type R = crate::R; +#[doc = "Register `CANEC` writer"] +pub type W = crate::W; +#[doc = "Field `TEC` reader - Transmit Error Counter"] +pub type TecR = crate::FieldReader; +#[doc = "Field `TEC` writer - Transmit Error Counter"] +pub type TecW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REC` reader - Receive Error Counter"] +pub type RecR = crate::FieldReader; +#[doc = "Field `REC` writer - Receive Error Counter"] +pub type RecW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn tec(&self) -> TecR { + TecR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Receive Error Counter"] + #[inline(always)] + pub fn rec(&self) -> RecR { + RecR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn tec(&mut self) -> TecW<'_, CanecSpec> { + TecW::new(self, 0) + } + #[doc = "Bits 8:15 - Receive Error Counter"] + #[inline(always)] + pub fn rec(&mut self) -> RecW<'_, CanecSpec> { + RecW::new(self, 8) + } +} +#[doc = "CAN Error Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`canec::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`canec::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CanecSpec; +impl crate::RegisterSpec for CanecSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`canec::R`](R) reader structure"] +impl crate::Readable for CanecSpec {} +#[doc = "`write(|w| ..)` method takes [`canec::W`](W) writer structure"] +impl crate::Writable for CanecSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CANEC to value 0"] +impl crate::Resettable for CanecSpec {} diff --git a/va416xx/va416xx/src/can0/cediag.rs b/va416xx/va416xx/src/can0/cediag.rs new file mode 100644 index 0000000..71e301d --- /dev/null +++ b/va416xx/va416xx/src/can0/cediag.rs @@ -0,0 +1,119 @@ +#[doc = "Register `CEDIAG` reader"] +pub type R = crate::R; +#[doc = "Register `CEDIAG` writer"] +pub type W = crate::W; +#[doc = "Field `EFID` reader - Error Field Identifier"] +pub type EfidR = crate::FieldReader; +#[doc = "Field `EFID` writer - Error Field Identifier"] +pub type EfidW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `EBID` reader - Error Bit Identifier"] +pub type EbidR = crate::FieldReader; +#[doc = "Field `EBID` writer - Error Bit Identifier"] +pub type EbidW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `TXE` reader - Transmit Error"] +pub type TxeR = crate::BitReader; +#[doc = "Field `TXE` writer - Transmit Error"] +pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STUFF` reader - Stuff Error"] +pub type StuffR = crate::BitReader; +#[doc = "Field `STUFF` writer - Stuff Error"] +pub type StuffW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRC` reader - CRC"] +pub type CrcR = crate::BitReader; +#[doc = "Field `CRC` writer - CRC"] +pub type CrcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MON` reader - Monitor"] +pub type MonR = crate::BitReader; +#[doc = "Field `MON` writer - Monitor"] +pub type MonW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DRIVE` reader - Drive"] +pub type DriveR = crate::BitReader; +#[doc = "Field `DRIVE` writer - Drive"] +pub type DriveW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Error Field Identifier"] + #[inline(always)] + pub fn efid(&self) -> EfidR { + EfidR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:9 - Error Bit Identifier"] + #[inline(always)] + pub fn ebid(&self) -> EbidR { + EbidR::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bit 10 - Transmit Error"] + #[inline(always)] + pub fn txe(&self) -> TxeR { + TxeR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Stuff Error"] + #[inline(always)] + pub fn stuff(&self) -> StuffR { + StuffR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - CRC"] + #[inline(always)] + pub fn crc(&self) -> CrcR { + CrcR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Monitor"] + #[inline(always)] + pub fn mon(&self) -> MonR { + MonR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Drive"] + #[inline(always)] + pub fn drive(&self) -> DriveR { + DriveR::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Error Field Identifier"] + #[inline(always)] + pub fn efid(&mut self) -> EfidW<'_, CediagSpec> { + EfidW::new(self, 0) + } + #[doc = "Bits 4:9 - Error Bit Identifier"] + #[inline(always)] + pub fn ebid(&mut self) -> EbidW<'_, CediagSpec> { + EbidW::new(self, 4) + } + #[doc = "Bit 10 - Transmit Error"] + #[inline(always)] + pub fn txe(&mut self) -> TxeW<'_, CediagSpec> { + TxeW::new(self, 10) + } + #[doc = "Bit 11 - Stuff Error"] + #[inline(always)] + pub fn stuff(&mut self) -> StuffW<'_, CediagSpec> { + StuffW::new(self, 11) + } + #[doc = "Bit 12 - CRC"] + #[inline(always)] + pub fn crc(&mut self) -> CrcW<'_, CediagSpec> { + CrcW::new(self, 12) + } + #[doc = "Bit 13 - Monitor"] + #[inline(always)] + pub fn mon(&mut self) -> MonW<'_, CediagSpec> { + MonW::new(self, 13) + } + #[doc = "Bit 14 - Drive"] + #[inline(always)] + pub fn drive(&mut self) -> DriveW<'_, CediagSpec> { + DriveW::new(self, 14) + } +} +#[doc = "CAN Error Diagnostic Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cediag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cediag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CediagSpec; +impl crate::RegisterSpec for CediagSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cediag::R`](R) reader structure"] +impl crate::Readable for CediagSpec {} +#[doc = "`write(|w| ..)` method takes [`cediag::W`](W) writer structure"] +impl crate::Writable for CediagSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CEDIAG to value 0"] +impl crate::Resettable for CediagSpec {} diff --git a/va416xx/va416xx/src/can0/cgcr.rs b/va416xx/va416xx/src/can0/cgcr.rs new file mode 100644 index 0000000..44604ff --- /dev/null +++ b/va416xx/va416xx/src/can0/cgcr.rs @@ -0,0 +1,189 @@ +#[doc = "Register `CGCR` reader"] +pub type R = crate::R; +#[doc = "Register `CGCR` writer"] +pub type W = crate::W; +#[doc = "Field `CANEN` reader - CAN Enable"] +pub type CanenR = crate::BitReader; +#[doc = "Field `CANEN` writer - CAN Enable"] +pub type CanenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRX` reader - RW,Control Receive"] +pub type CrxR = crate::BitReader; +#[doc = "Field `CRX` writer - RW,Control Receive"] +pub type CrxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTX` reader - RW,Control Transmit"] +pub type CtxR = crate::BitReader; +#[doc = "Field `CTX` writer - RW,Control Transmit"] +pub type CtxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUFFLOCK` reader - Buffer Lock"] +pub type BufflockR = crate::BitReader; +#[doc = "Field `BUFFLOCK` writer - Buffer Lock"] +pub type BufflockW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSTPEN` reader - Time Sync Enable"] +pub type TstpenR = crate::BitReader; +#[doc = "Field `TSTPEN` writer - Time Sync Enable"] +pub type TstpenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DDIR` reader - Data Direction"] +pub type DdirR = crate::BitReader; +#[doc = "Field `DDIR` writer - Data Direction"] +pub type DdirW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LO` reader - Listen Only"] +pub type LoR = crate::BitReader; +#[doc = "Field `LO` writer - Listen Only"] +pub type LoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IGNACK` reader - Ignore Acknowledge"] +pub type IgnackR = crate::BitReader; +#[doc = "Field `IGNACK` writer - Ignore Acknowledge"] +pub type IgnackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACK` reader - Loopback"] +pub type LoopbackR = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Loopback"] +pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTERNAL` reader - Internal"] +pub type InternalR = crate::BitReader; +#[doc = "Field `INTERNAL` writer - Internal"] +pub type InternalW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIAGEN` reader - Diagnostic Enable"] +pub type DiagenR = crate::BitReader; +#[doc = "Field `DIAGEN` writer - Diagnostic Enable"] +pub type DiagenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EIT` reader - Error Interrupt Type"] +pub type EitR = crate::BitReader; +#[doc = "Field `EIT` writer - Error Interrupt Type"] +pub type EitW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - CAN Enable"] + #[inline(always)] + pub fn canen(&self) -> CanenR { + CanenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RW,Control Receive"] + #[inline(always)] + pub fn crx(&self) -> CrxR { + CrxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RW,Control Transmit"] + #[inline(always)] + pub fn ctx(&self) -> CtxR { + CtxR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Buffer Lock"] + #[inline(always)] + pub fn bufflock(&self) -> BufflockR { + BufflockR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Time Sync Enable"] + #[inline(always)] + pub fn tstpen(&self) -> TstpenR { + TstpenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Data Direction"] + #[inline(always)] + pub fn ddir(&self) -> DdirR { + DdirR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Listen Only"] + #[inline(always)] + pub fn lo(&self) -> LoR { + LoR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Ignore Acknowledge"] + #[inline(always)] + pub fn ignack(&self) -> IgnackR { + IgnackR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Loopback"] + #[inline(always)] + pub fn loopback(&self) -> LoopbackR { + LoopbackR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Internal"] + #[inline(always)] + pub fn internal(&self) -> InternalR { + InternalR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Diagnostic Enable"] + #[inline(always)] + pub fn diagen(&self) -> DiagenR { + DiagenR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Error Interrupt Type"] + #[inline(always)] + pub fn eit(&self) -> EitR { + EitR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CAN Enable"] + #[inline(always)] + pub fn canen(&mut self) -> CanenW<'_, CgcrSpec> { + CanenW::new(self, 0) + } + #[doc = "Bit 1 - RW,Control Receive"] + #[inline(always)] + pub fn crx(&mut self) -> CrxW<'_, CgcrSpec> { + CrxW::new(self, 1) + } + #[doc = "Bit 2 - RW,Control Transmit"] + #[inline(always)] + pub fn ctx(&mut self) -> CtxW<'_, CgcrSpec> { + CtxW::new(self, 2) + } + #[doc = "Bit 3 - Buffer Lock"] + #[inline(always)] + pub fn bufflock(&mut self) -> BufflockW<'_, CgcrSpec> { + BufflockW::new(self, 3) + } + #[doc = "Bit 4 - Time Sync Enable"] + #[inline(always)] + pub fn tstpen(&mut self) -> TstpenW<'_, CgcrSpec> { + TstpenW::new(self, 4) + } + #[doc = "Bit 5 - Data Direction"] + #[inline(always)] + pub fn ddir(&mut self) -> DdirW<'_, CgcrSpec> { + DdirW::new(self, 5) + } + #[doc = "Bit 6 - Listen Only"] + #[inline(always)] + pub fn lo(&mut self) -> LoW<'_, CgcrSpec> { + LoW::new(self, 6) + } + #[doc = "Bit 7 - Ignore Acknowledge"] + #[inline(always)] + pub fn ignack(&mut self) -> IgnackW<'_, CgcrSpec> { + IgnackW::new(self, 7) + } + #[doc = "Bit 8 - Loopback"] + #[inline(always)] + pub fn loopback(&mut self) -> LoopbackW<'_, CgcrSpec> { + LoopbackW::new(self, 8) + } + #[doc = "Bit 9 - Internal"] + #[inline(always)] + pub fn internal(&mut self) -> InternalW<'_, CgcrSpec> { + InternalW::new(self, 9) + } + #[doc = "Bit 10 - Diagnostic Enable"] + #[inline(always)] + pub fn diagen(&mut self) -> DiagenW<'_, CgcrSpec> { + DiagenW::new(self, 10) + } + #[doc = "Bit 11 - Error Interrupt Type"] + #[inline(always)] + pub fn eit(&mut self) -> EitW<'_, CgcrSpec> { + EitW::new(self, 11) + } +} +#[doc = "CAN Global Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cgcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cgcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CgcrSpec; +impl crate::RegisterSpec for CgcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cgcr::R`](R) reader structure"] +impl crate::Readable for CgcrSpec {} +#[doc = "`write(|w| ..)` method takes [`cgcr::W`](W) writer structure"] +impl crate::Writable for CgcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CGCR to value 0"] +impl crate::Resettable for CgcrSpec {} diff --git a/va416xx/va416xx/src/can0/cicen.rs b/va416xx/va416xx/src/can0/cicen.rs new file mode 100644 index 0000000..9f623fa --- /dev/null +++ b/va416xx/va416xx/src/can0/cicen.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CICEN` reader"] +pub type R = crate::R; +#[doc = "Register `CICEN` writer"] +pub type W = crate::W; +#[doc = "Field `ICEN` reader - Buffer Interrupt Code Enable\\[14:0\\]"] +pub type IcenR = crate::FieldReader; +#[doc = "Field `ICEN` writer - Buffer Interrupt Code Enable\\[14:0\\]"] +pub type IcenW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `EICEN` reader - Error Interrupt Code Enable"] +pub type EicenR = crate::BitReader; +#[doc = "Field `EICEN` writer - Error Interrupt Code Enable"] +pub type EicenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"] + #[inline(always)] + pub fn icen(&self) -> IcenR { + IcenR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - Error Interrupt Code Enable"] + #[inline(always)] + pub fn eicen(&self) -> EicenR { + EicenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"] + #[inline(always)] + pub fn icen(&mut self) -> IcenW<'_, CicenSpec> { + IcenW::new(self, 0) + } + #[doc = "Bit 15 - Error Interrupt Code Enable"] + #[inline(always)] + pub fn eicen(&mut self) -> EicenW<'_, CicenSpec> { + EicenW::new(self, 15) + } +} +#[doc = "CAN Interrupt Code Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cicen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cicen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CicenSpec; +impl crate::RegisterSpec for CicenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cicen::R`](R) reader structure"] +impl crate::Readable for CicenSpec {} +#[doc = "`write(|w| ..)` method takes [`cicen::W`](W) writer structure"] +impl crate::Writable for CicenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CICEN to value 0"] +impl crate::Resettable for CicenSpec {} diff --git a/va416xx/va416xx/src/can0/ciclr.rs b/va416xx/va416xx/src/can0/ciclr.rs new file mode 100644 index 0000000..0ba3233 --- /dev/null +++ b/va416xx/va416xx/src/can0/ciclr.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CICLR` reader"] +pub type R = crate::R; +#[doc = "Register `CICLR` writer"] +pub type W = crate::W; +#[doc = "Field `ICLR` reader - Buffer Interrupt Clear\\[14:0\\]"] +pub type IclrR = crate::FieldReader; +#[doc = "Field `ICLR` writer - Buffer Interrupt Clear\\[14:0\\]"] +pub type IclrW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `EICLR` reader - Error Interrupt Clear"] +pub type EiclrR = crate::BitReader; +#[doc = "Field `EICLR` writer - Error Interrupt Clear"] +pub type EiclrW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - Buffer Interrupt Clear\\[14:0\\]"] + #[inline(always)] + pub fn iclr(&self) -> IclrR { + IclrR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - Error Interrupt Clear"] + #[inline(always)] + pub fn eiclr(&self) -> EiclrR { + EiclrR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Buffer Interrupt Clear\\[14:0\\]"] + #[inline(always)] + pub fn iclr(&mut self) -> IclrW<'_, CiclrSpec> { + IclrW::new(self, 0) + } + #[doc = "Bit 15 - Error Interrupt Clear"] + #[inline(always)] + pub fn eiclr(&mut self) -> EiclrW<'_, CiclrSpec> { + EiclrW::new(self, 15) + } +} +#[doc = "CAN Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ciclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ciclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CiclrSpec; +impl crate::RegisterSpec for CiclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ciclr::R`](R) reader structure"] +impl crate::Readable for CiclrSpec {} +#[doc = "`write(|w| ..)` method takes [`ciclr::W`](W) writer structure"] +impl crate::Writable for CiclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CICLR to value 0"] +impl crate::Resettable for CiclrSpec {} diff --git a/va416xx/va416xx/src/can0/cien.rs b/va416xx/va416xx/src/can0/cien.rs new file mode 100644 index 0000000..0cdb063 --- /dev/null +++ b/va416xx/va416xx/src/can0/cien.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CIEN` reader"] +pub type R = crate::R; +#[doc = "Register `CIEN` writer"] +pub type W = crate::W; +#[doc = "Field `IEN` reader - Buffer Interrupt Enable\\[14:0\\]"] +pub type IenR = crate::FieldReader; +#[doc = "Field `IEN` writer - Buffer Interrupt Enable\\[14:0\\]"] +pub type IenW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `EIEN` reader - Error Interrupt Enable"] +pub type EienR = crate::BitReader; +#[doc = "Field `EIEN` writer - Error Interrupt Enable"] +pub type EienW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - Buffer Interrupt Enable\\[14:0\\]"] + #[inline(always)] + pub fn ien(&self) -> IenR { + IenR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - Error Interrupt Enable"] + #[inline(always)] + pub fn eien(&self) -> EienR { + EienR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Buffer Interrupt Enable\\[14:0\\]"] + #[inline(always)] + pub fn ien(&mut self) -> IenW<'_, CienSpec> { + IenW::new(self, 0) + } + #[doc = "Bit 15 - Error Interrupt Enable"] + #[inline(always)] + pub fn eien(&mut self) -> EienW<'_, CienSpec> { + EienW::new(self, 15) + } +} +#[doc = "CAN Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CienSpec; +impl crate::RegisterSpec for CienSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cien::R`](R) reader structure"] +impl crate::Readable for CienSpec {} +#[doc = "`write(|w| ..)` method takes [`cien::W`](W) writer structure"] +impl crate::Writable for CienSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CIEN to value 0"] +impl crate::Resettable for CienSpec {} diff --git a/va416xx/va416xx/src/can0/cipnd.rs b/va416xx/va416xx/src/can0/cipnd.rs new file mode 100644 index 0000000..224864e --- /dev/null +++ b/va416xx/va416xx/src/can0/cipnd.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CIPND` reader"] +pub type R = crate::R; +#[doc = "Register `CIPND` writer"] +pub type W = crate::W; +#[doc = "Field `IPND` reader - Buffer Interrupt Pending\\[14:0\\]"] +pub type IpndR = crate::FieldReader; +#[doc = "Field `IPND` writer - Buffer Interrupt Pending\\[14:0\\]"] +pub type IpndW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `EIPND` reader - Error Interrupt Pending"] +pub type EipndR = crate::BitReader; +#[doc = "Field `EIPND` writer - Error Interrupt Pending"] +pub type EipndW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - Buffer Interrupt Pending\\[14:0\\]"] + #[inline(always)] + pub fn ipnd(&self) -> IpndR { + IpndR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - Error Interrupt Pending"] + #[inline(always)] + pub fn eipnd(&self) -> EipndR { + EipndR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Buffer Interrupt Pending\\[14:0\\]"] + #[inline(always)] + pub fn ipnd(&mut self) -> IpndW<'_, CipndSpec> { + IpndW::new(self, 0) + } + #[doc = "Bit 15 - Error Interrupt Pending"] + #[inline(always)] + pub fn eipnd(&mut self) -> EipndW<'_, CipndSpec> { + EipndW::new(self, 15) + } +} +#[doc = "CAN Interrupt Pending Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cipnd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cipnd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CipndSpec; +impl crate::RegisterSpec for CipndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cipnd::R`](R) reader structure"] +impl crate::Readable for CipndSpec {} +#[doc = "`write(|w| ..)` method takes [`cipnd::W`](W) writer structure"] +impl crate::Writable for CipndSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CIPND to value 0"] +impl crate::Resettable for CipndSpec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb0.rs b/va416xx/va416xx/src/can0/cnstat_cmb0.rs new file mode 100644 index 0000000..586e3d4 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb0Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb0Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb0Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb0Spec; +impl crate::RegisterSpec for CnstatCmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb0::R`](R) reader structure"] +impl crate::Readable for CnstatCmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb0::W`](W) writer structure"] +impl crate::Writable for CnstatCmb0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB0 to value 0"] +impl crate::Resettable for CnstatCmb0Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb1.rs b/va416xx/va416xx/src/can0/cnstat_cmb1.rs new file mode 100644 index 0000000..8885e06 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb1Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb1Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb1Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb1Spec; +impl crate::RegisterSpec for CnstatCmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb1::R`](R) reader structure"] +impl crate::Readable for CnstatCmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb1::W`](W) writer structure"] +impl crate::Writable for CnstatCmb1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB1 to value 0"] +impl crate::Resettable for CnstatCmb1Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb10.rs b/va416xx/va416xx/src/can0/cnstat_cmb10.rs new file mode 100644 index 0000000..95418ec --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb10.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb10Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb10Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb10Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb10Spec; +impl crate::RegisterSpec for CnstatCmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb10::R`](R) reader structure"] +impl crate::Readable for CnstatCmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb10::W`](W) writer structure"] +impl crate::Writable for CnstatCmb10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB10 to value 0"] +impl crate::Resettable for CnstatCmb10Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb11.rs b/va416xx/va416xx/src/can0/cnstat_cmb11.rs new file mode 100644 index 0000000..b7f689e --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb11.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb11Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb11Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb11Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb11Spec; +impl crate::RegisterSpec for CnstatCmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb11::R`](R) reader structure"] +impl crate::Readable for CnstatCmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb11::W`](W) writer structure"] +impl crate::Writable for CnstatCmb11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB11 to value 0"] +impl crate::Resettable for CnstatCmb11Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb12.rs b/va416xx/va416xx/src/can0/cnstat_cmb12.rs new file mode 100644 index 0000000..3fabc9f --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb12.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb12Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb12Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb12Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb12Spec; +impl crate::RegisterSpec for CnstatCmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb12::R`](R) reader structure"] +impl crate::Readable for CnstatCmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb12::W`](W) writer structure"] +impl crate::Writable for CnstatCmb12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB12 to value 0"] +impl crate::Resettable for CnstatCmb12Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb13.rs b/va416xx/va416xx/src/can0/cnstat_cmb13.rs new file mode 100644 index 0000000..88a8e63 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb13.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb13Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb13Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb13Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb13Spec; +impl crate::RegisterSpec for CnstatCmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb13::R`](R) reader structure"] +impl crate::Readable for CnstatCmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb13::W`](W) writer structure"] +impl crate::Writable for CnstatCmb13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB13 to value 0"] +impl crate::Resettable for CnstatCmb13Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb14.rs b/va416xx/va416xx/src/can0/cnstat_cmb14.rs new file mode 100644 index 0000000..4c68312 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb14.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb14Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb14Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb14Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb14Spec; +impl crate::RegisterSpec for CnstatCmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb14::R`](R) reader structure"] +impl crate::Readable for CnstatCmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb14::W`](W) writer structure"] +impl crate::Writable for CnstatCmb14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB14 to value 0"] +impl crate::Resettable for CnstatCmb14Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb2.rs b/va416xx/va416xx/src/can0/cnstat_cmb2.rs new file mode 100644 index 0000000..26eeb12 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb2Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb2Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb2Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb2Spec; +impl crate::RegisterSpec for CnstatCmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb2::R`](R) reader structure"] +impl crate::Readable for CnstatCmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb2::W`](W) writer structure"] +impl crate::Writable for CnstatCmb2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB2 to value 0"] +impl crate::Resettable for CnstatCmb2Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb3.rs b/va416xx/va416xx/src/can0/cnstat_cmb3.rs new file mode 100644 index 0000000..7bce684 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb3Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb3Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb3Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb3Spec; +impl crate::RegisterSpec for CnstatCmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb3::R`](R) reader structure"] +impl crate::Readable for CnstatCmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb3::W`](W) writer structure"] +impl crate::Writable for CnstatCmb3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB3 to value 0"] +impl crate::Resettable for CnstatCmb3Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb4.rs b/va416xx/va416xx/src/can0/cnstat_cmb4.rs new file mode 100644 index 0000000..f8f5811 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb4.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb4Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb4Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb4Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb4Spec; +impl crate::RegisterSpec for CnstatCmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb4::R`](R) reader structure"] +impl crate::Readable for CnstatCmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb4::W`](W) writer structure"] +impl crate::Writable for CnstatCmb4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB4 to value 0"] +impl crate::Resettable for CnstatCmb4Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb5.rs b/va416xx/va416xx/src/can0/cnstat_cmb5.rs new file mode 100644 index 0000000..ae92790 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb5.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb5Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb5Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb5Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb5Spec; +impl crate::RegisterSpec for CnstatCmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb5::R`](R) reader structure"] +impl crate::Readable for CnstatCmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb5::W`](W) writer structure"] +impl crate::Writable for CnstatCmb5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB5 to value 0"] +impl crate::Resettable for CnstatCmb5Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb6.rs b/va416xx/va416xx/src/can0/cnstat_cmb6.rs new file mode 100644 index 0000000..9dc607b --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb6.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb6Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb6Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb6Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb6Spec; +impl crate::RegisterSpec for CnstatCmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb6::R`](R) reader structure"] +impl crate::Readable for CnstatCmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb6::W`](W) writer structure"] +impl crate::Writable for CnstatCmb6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB6 to value 0"] +impl crate::Resettable for CnstatCmb6Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb7.rs b/va416xx/va416xx/src/can0/cnstat_cmb7.rs new file mode 100644 index 0000000..1f441a7 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb7.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb7Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb7Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb7Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb7Spec; +impl crate::RegisterSpec for CnstatCmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb7::R`](R) reader structure"] +impl crate::Readable for CnstatCmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb7::W`](W) writer structure"] +impl crate::Writable for CnstatCmb7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB7 to value 0"] +impl crate::Resettable for CnstatCmb7Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb8.rs b/va416xx/va416xx/src/can0/cnstat_cmb8.rs new file mode 100644 index 0000000..42f104d --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb8.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb8Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb8Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb8Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb8Spec; +impl crate::RegisterSpec for CnstatCmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb8::R`](R) reader structure"] +impl crate::Readable for CnstatCmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb8::W`](W) writer structure"] +impl crate::Writable for CnstatCmb8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB8 to value 0"] +impl crate::Resettable for CnstatCmb8Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_cmb9.rs b/va416xx/va416xx/src/can0/cnstat_cmb9.rs new file mode 100644 index 0000000..0bc36d6 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_cmb9.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatCmb9Spec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatCmb9Spec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatCmb9Spec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_cmb9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_cmb9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb9Spec; +impl crate::RegisterSpec for CnstatCmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb9::R`](R) reader structure"] +impl crate::Readable for CnstatCmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb9::W`](W) writer structure"] +impl crate::Writable for CnstatCmb9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_CMB9 to value 0"] +impl crate::Resettable for CnstatCmb9Spec {} diff --git a/va416xx/va416xx/src/can0/cnstat_hcmb.rs b/va416xx/va416xx/src/can0/cnstat_hcmb.rs new file mode 100644 index 0000000..8a73e64 --- /dev/null +++ b/va416xx/va416xx/src/can0/cnstat_hcmb.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CNSTAT_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, CnstatHcmbSpec> { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&mut self) -> PriW<'_, CnstatHcmbSpec> { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&mut self) -> DlcW<'_, CnstatHcmbSpec> { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cnstat_hcmb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnstat_hcmb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatHcmbSpec; +impl crate::RegisterSpec for CnstatHcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_hcmb::R`](R) reader structure"] +impl crate::Readable for CnstatHcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_hcmb::W`](W) writer structure"] +impl crate::Writable for CnstatHcmbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNSTAT_HCMB to value 0"] +impl crate::Resettable for CnstatHcmbSpec {} diff --git a/va416xx/va416xx/src/can0/cstpnd.rs b/va416xx/va416xx/src/can0/cstpnd.rs new file mode 100644 index 0000000..514d5b9 --- /dev/null +++ b/va416xx/va416xx/src/can0/cstpnd.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CSTPND` reader"] +pub type R = crate::R; +#[doc = "Register `CSTPND` writer"] +pub type W = crate::W; +#[doc = "Field `IST` reader - Interrupt Source portion of Interrupt Code"] +pub type IstR = crate::FieldReader; +#[doc = "Field `IST` writer - Interrupt Source portion of Interrupt Code"] +pub type IstW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `IRQ` reader - Interrupt Request portion of Interrupt Code"] +pub type IrqR = crate::BitReader; +#[doc = "Field `IRQ` writer - Interrupt Request portion of Interrupt Code"] +pub type IrqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NS` reader - CAN Node Status"] +pub type NsR = crate::FieldReader; +#[doc = "Field `NS` writer - CAN Node Status"] +pub type NsW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Interrupt Source portion of Interrupt Code"] + #[inline(always)] + pub fn ist(&self) -> IstR { + IstR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 4 - Interrupt Request portion of Interrupt Code"] + #[inline(always)] + pub fn irq(&self) -> IrqR { + IrqR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - CAN Node Status"] + #[inline(always)] + pub fn ns(&self) -> NsR { + NsR::new(((self.bits >> 5) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Interrupt Source portion of Interrupt Code"] + #[inline(always)] + pub fn ist(&mut self) -> IstW<'_, CstpndSpec> { + IstW::new(self, 0) + } + #[doc = "Bit 4 - Interrupt Request portion of Interrupt Code"] + #[inline(always)] + pub fn irq(&mut self) -> IrqW<'_, CstpndSpec> { + IrqW::new(self, 4) + } + #[doc = "Bits 5:7 - CAN Node Status"] + #[inline(always)] + pub fn ns(&mut self) -> NsW<'_, CstpndSpec> { + NsW::new(self, 5) + } +} +#[doc = "CAN Status Pending Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cstpnd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cstpnd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CstpndSpec; +impl crate::RegisterSpec for CstpndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cstpnd::R`](R) reader structure"] +impl crate::Readable for CstpndSpec {} +#[doc = "`write(|w| ..)` method takes [`cstpnd::W`](W) writer structure"] +impl crate::Writable for CstpndSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CSTPND to value 0"] +impl crate::Resettable for CstpndSpec {} diff --git a/va416xx/va416xx/src/can0/ctim.rs b/va416xx/va416xx/src/can0/ctim.rs new file mode 100644 index 0000000..b020461 --- /dev/null +++ b/va416xx/va416xx/src/can0/ctim.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CTIM` reader"] +pub type R = crate::R; +#[doc = "Register `CTIM` writer"] +pub type W = crate::W; +#[doc = "Field `TSEG2` reader - Time Segment 2"] +pub type Tseg2R = crate::FieldReader; +#[doc = "Field `TSEG2` writer - Time Segment 2"] +pub type Tseg2W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TSEG1` reader - Time Segment 1"] +pub type Tseg1R = crate::FieldReader; +#[doc = "Field `TSEG1` writer - Time Segment 1"] +pub type Tseg1W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SJW` reader - Synchronization Jump Width"] +pub type SjwR = crate::FieldReader; +#[doc = "Field `SJW` writer - Synchronization Jump Width"] +pub type SjwW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PSC` reader - Prescaler Configuration"] +pub type PscR = crate::FieldReader; +#[doc = "Field `PSC` writer - Prescaler Configuration"] +pub type PscW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:2 - Time Segment 2"] + #[inline(always)] + pub fn tseg2(&self) -> Tseg2R { + Tseg2R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:6 - Time Segment 1"] + #[inline(always)] + pub fn tseg1(&self) -> Tseg1R { + Tseg1R::new(((self.bits >> 3) & 0x0f) as u8) + } + #[doc = "Bits 7:8 - Synchronization Jump Width"] + #[inline(always)] + pub fn sjw(&self) -> SjwR { + SjwR::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 9:15 - Prescaler Configuration"] + #[inline(always)] + pub fn psc(&self) -> PscR { + PscR::new(((self.bits >> 9) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Time Segment 2"] + #[inline(always)] + pub fn tseg2(&mut self) -> Tseg2W<'_, CtimSpec> { + Tseg2W::new(self, 0) + } + #[doc = "Bits 3:6 - Time Segment 1"] + #[inline(always)] + pub fn tseg1(&mut self) -> Tseg1W<'_, CtimSpec> { + Tseg1W::new(self, 3) + } + #[doc = "Bits 7:8 - Synchronization Jump Width"] + #[inline(always)] + pub fn sjw(&mut self) -> SjwW<'_, CtimSpec> { + SjwW::new(self, 7) + } + #[doc = "Bits 9:15 - Prescaler Configuration"] + #[inline(always)] + pub fn psc(&mut self) -> PscW<'_, CtimSpec> { + PscW::new(self, 9) + } +} +#[doc = "CAN Timing Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtimSpec; +impl crate::RegisterSpec for CtimSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctim::R`](R) reader structure"] +impl crate::Readable for CtimSpec {} +#[doc = "`write(|w| ..)` method takes [`ctim::W`](W) writer structure"] +impl crate::Writable for CtimSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTIM to value 0"] +impl crate::Resettable for CtimSpec {} diff --git a/va416xx/va416xx/src/can0/ctmr.rs b/va416xx/va416xx/src/can0/ctmr.rs new file mode 100644 index 0000000..6439a30 --- /dev/null +++ b/va416xx/va416xx/src/can0/ctmr.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CTMR` reader"] +pub type R = crate::R; +#[doc = "Register `CTMR` writer"] +pub type W = crate::W; +#[doc = "Field `CTMR` reader - Time Stamp Counter"] +pub type CtmrR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Time Stamp Counter"] + #[inline(always)] + pub fn ctmr(&self) -> CtmrR { + CtmrR::new((self.bits & 0xffff) as u16) + } +} +impl W {} +#[doc = "CAN Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctmr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctmr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtmrSpec; +impl crate::RegisterSpec for CtmrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctmr::R`](R) reader structure"] +impl crate::Readable for CtmrSpec {} +#[doc = "`write(|w| ..)` method takes [`ctmr::W`](W) writer structure"] +impl crate::Writable for CtmrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTMR to value 0"] +impl crate::Resettable for CtmrSpec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb0.rs b/va416xx/va416xx/src/can0/data0_cmb0.rs new file mode 100644 index 0000000..7170a43 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb0Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb0Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb0Spec; +impl crate::RegisterSpec for Data0Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb0::R`](R) reader structure"] +impl crate::Readable for Data0Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb0::W`](W) writer structure"] +impl crate::Writable for Data0Cmb0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB0 to value 0"] +impl crate::Resettable for Data0Cmb0Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb1.rs b/va416xx/va416xx/src/can0/data0_cmb1.rs new file mode 100644 index 0000000..7daee0f --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb1Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb1Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb1Spec; +impl crate::RegisterSpec for Data0Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb1::R`](R) reader structure"] +impl crate::Readable for Data0Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb1::W`](W) writer structure"] +impl crate::Writable for Data0Cmb1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB1 to value 0"] +impl crate::Resettable for Data0Cmb1Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb10.rs b/va416xx/va416xx/src/can0/data0_cmb10.rs new file mode 100644 index 0000000..9347fcf --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb10.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb10Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb10Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb10Spec; +impl crate::RegisterSpec for Data0Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb10::R`](R) reader structure"] +impl crate::Readable for Data0Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb10::W`](W) writer structure"] +impl crate::Writable for Data0Cmb10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB10 to value 0"] +impl crate::Resettable for Data0Cmb10Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb11.rs b/va416xx/va416xx/src/can0/data0_cmb11.rs new file mode 100644 index 0000000..4c30924 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb11.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb11Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb11Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb11Spec; +impl crate::RegisterSpec for Data0Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb11::R`](R) reader structure"] +impl crate::Readable for Data0Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb11::W`](W) writer structure"] +impl crate::Writable for Data0Cmb11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB11 to value 0"] +impl crate::Resettable for Data0Cmb11Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb12.rs b/va416xx/va416xx/src/can0/data0_cmb12.rs new file mode 100644 index 0000000..a0db512 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb12.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb12Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb12Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb12Spec; +impl crate::RegisterSpec for Data0Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb12::R`](R) reader structure"] +impl crate::Readable for Data0Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb12::W`](W) writer structure"] +impl crate::Writable for Data0Cmb12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB12 to value 0"] +impl crate::Resettable for Data0Cmb12Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb13.rs b/va416xx/va416xx/src/can0/data0_cmb13.rs new file mode 100644 index 0000000..8637644 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb13.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb13Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb13Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb13Spec; +impl crate::RegisterSpec for Data0Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb13::R`](R) reader structure"] +impl crate::Readable for Data0Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb13::W`](W) writer structure"] +impl crate::Writable for Data0Cmb13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB13 to value 0"] +impl crate::Resettable for Data0Cmb13Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb14.rs b/va416xx/va416xx/src/can0/data0_cmb14.rs new file mode 100644 index 0000000..e62fb32 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb14.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb14Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb14Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb14Spec; +impl crate::RegisterSpec for Data0Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb14::R`](R) reader structure"] +impl crate::Readable for Data0Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb14::W`](W) writer structure"] +impl crate::Writable for Data0Cmb14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB14 to value 0"] +impl crate::Resettable for Data0Cmb14Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb2.rs b/va416xx/va416xx/src/can0/data0_cmb2.rs new file mode 100644 index 0000000..179ad4d --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb2Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb2Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb2Spec; +impl crate::RegisterSpec for Data0Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb2::R`](R) reader structure"] +impl crate::Readable for Data0Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb2::W`](W) writer structure"] +impl crate::Writable for Data0Cmb2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB2 to value 0"] +impl crate::Resettable for Data0Cmb2Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb3.rs b/va416xx/va416xx/src/can0/data0_cmb3.rs new file mode 100644 index 0000000..eb80122 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb3Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb3Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb3Spec; +impl crate::RegisterSpec for Data0Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb3::R`](R) reader structure"] +impl crate::Readable for Data0Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb3::W`](W) writer structure"] +impl crate::Writable for Data0Cmb3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB3 to value 0"] +impl crate::Resettable for Data0Cmb3Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb4.rs b/va416xx/va416xx/src/can0/data0_cmb4.rs new file mode 100644 index 0000000..6b79322 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb4.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb4Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb4Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb4Spec; +impl crate::RegisterSpec for Data0Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb4::R`](R) reader structure"] +impl crate::Readable for Data0Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb4::W`](W) writer structure"] +impl crate::Writable for Data0Cmb4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB4 to value 0"] +impl crate::Resettable for Data0Cmb4Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb5.rs b/va416xx/va416xx/src/can0/data0_cmb5.rs new file mode 100644 index 0000000..e3ea431 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb5.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb5Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb5Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb5Spec; +impl crate::RegisterSpec for Data0Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb5::R`](R) reader structure"] +impl crate::Readable for Data0Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb5::W`](W) writer structure"] +impl crate::Writable for Data0Cmb5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB5 to value 0"] +impl crate::Resettable for Data0Cmb5Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb6.rs b/va416xx/va416xx/src/can0/data0_cmb6.rs new file mode 100644 index 0000000..aa2a020 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb6.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb6Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb6Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb6Spec; +impl crate::RegisterSpec for Data0Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb6::R`](R) reader structure"] +impl crate::Readable for Data0Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb6::W`](W) writer structure"] +impl crate::Writable for Data0Cmb6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB6 to value 0"] +impl crate::Resettable for Data0Cmb6Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb7.rs b/va416xx/va416xx/src/can0/data0_cmb7.rs new file mode 100644 index 0000000..6fefb07 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb7.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb7Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb7Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb7Spec; +impl crate::RegisterSpec for Data0Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb7::R`](R) reader structure"] +impl crate::Readable for Data0Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb7::W`](W) writer structure"] +impl crate::Writable for Data0Cmb7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB7 to value 0"] +impl crate::Resettable for Data0Cmb7Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb8.rs b/va416xx/va416xx/src/can0/data0_cmb8.rs new file mode 100644 index 0000000..f2f6c92 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb8.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb8Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb8Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb8Spec; +impl crate::RegisterSpec for Data0Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb8::R`](R) reader structure"] +impl crate::Readable for Data0Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb8::W`](W) writer structure"] +impl crate::Writable for Data0Cmb8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB8 to value 0"] +impl crate::Resettable for Data0Cmb8Spec {} diff --git a/va416xx/va416xx/src/can0/data0_cmb9.rs b/va416xx/va416xx/src/can0/data0_cmb9.rs new file mode 100644 index 0000000..4daf7bc --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_cmb9.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0Cmb9Spec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0Cmb9Spec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_cmb9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_cmb9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb9Spec; +impl crate::RegisterSpec for Data0Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb9::R`](R) reader structure"] +impl crate::Readable for Data0Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb9::W`](W) writer structure"] +impl crate::Writable for Data0Cmb9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_CMB9 to value 0"] +impl crate::Resettable for Data0Cmb9Spec {} diff --git a/va416xx/va416xx/src/can0/data0_hcmb.rs b/va416xx/va416xx/src/can0/data0_hcmb.rs new file mode 100644 index 0000000..2780207 --- /dev/null +++ b/va416xx/va416xx/src/can0/data0_hcmb.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA0_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&mut self) -> Byte2W<'_, Data0HcmbSpec> { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&mut self) -> Byte1W<'_, Data0HcmbSpec> { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`data0_hcmb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0_hcmb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0HcmbSpec; +impl crate::RegisterSpec for Data0HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_hcmb::R`](R) reader structure"] +impl crate::Readable for Data0HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`data0_hcmb::W`](W) writer structure"] +impl crate::Writable for Data0HcmbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA0_HCMB to value 0"] +impl crate::Resettable for Data0HcmbSpec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb0.rs b/va416xx/va416xx/src/can0/data1_cmb0.rs new file mode 100644 index 0000000..32398e8 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb0Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb0Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb0Spec; +impl crate::RegisterSpec for Data1Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb0::R`](R) reader structure"] +impl crate::Readable for Data1Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb0::W`](W) writer structure"] +impl crate::Writable for Data1Cmb0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB0 to value 0"] +impl crate::Resettable for Data1Cmb0Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb1.rs b/va416xx/va416xx/src/can0/data1_cmb1.rs new file mode 100644 index 0000000..dbd5323 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb1Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb1Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb1Spec; +impl crate::RegisterSpec for Data1Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb1::R`](R) reader structure"] +impl crate::Readable for Data1Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb1::W`](W) writer structure"] +impl crate::Writable for Data1Cmb1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB1 to value 0"] +impl crate::Resettable for Data1Cmb1Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb10.rs b/va416xx/va416xx/src/can0/data1_cmb10.rs new file mode 100644 index 0000000..7546cf7 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb10.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb10Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb10Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb10Spec; +impl crate::RegisterSpec for Data1Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb10::R`](R) reader structure"] +impl crate::Readable for Data1Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb10::W`](W) writer structure"] +impl crate::Writable for Data1Cmb10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB10 to value 0"] +impl crate::Resettable for Data1Cmb10Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb11.rs b/va416xx/va416xx/src/can0/data1_cmb11.rs new file mode 100644 index 0000000..6451a91 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb11.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb11Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb11Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb11Spec; +impl crate::RegisterSpec for Data1Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb11::R`](R) reader structure"] +impl crate::Readable for Data1Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb11::W`](W) writer structure"] +impl crate::Writable for Data1Cmb11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB11 to value 0"] +impl crate::Resettable for Data1Cmb11Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb12.rs b/va416xx/va416xx/src/can0/data1_cmb12.rs new file mode 100644 index 0000000..c0983df --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb12.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb12Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb12Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb12Spec; +impl crate::RegisterSpec for Data1Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb12::R`](R) reader structure"] +impl crate::Readable for Data1Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb12::W`](W) writer structure"] +impl crate::Writable for Data1Cmb12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB12 to value 0"] +impl crate::Resettable for Data1Cmb12Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb13.rs b/va416xx/va416xx/src/can0/data1_cmb13.rs new file mode 100644 index 0000000..630de3a --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb13.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb13Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb13Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb13Spec; +impl crate::RegisterSpec for Data1Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb13::R`](R) reader structure"] +impl crate::Readable for Data1Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb13::W`](W) writer structure"] +impl crate::Writable for Data1Cmb13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB13 to value 0"] +impl crate::Resettable for Data1Cmb13Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb14.rs b/va416xx/va416xx/src/can0/data1_cmb14.rs new file mode 100644 index 0000000..c83b667 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb14.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb14Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb14Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb14Spec; +impl crate::RegisterSpec for Data1Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb14::R`](R) reader structure"] +impl crate::Readable for Data1Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb14::W`](W) writer structure"] +impl crate::Writable for Data1Cmb14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB14 to value 0"] +impl crate::Resettable for Data1Cmb14Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb2.rs b/va416xx/va416xx/src/can0/data1_cmb2.rs new file mode 100644 index 0000000..ac157c4 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb2Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb2Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb2Spec; +impl crate::RegisterSpec for Data1Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb2::R`](R) reader structure"] +impl crate::Readable for Data1Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb2::W`](W) writer structure"] +impl crate::Writable for Data1Cmb2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB2 to value 0"] +impl crate::Resettable for Data1Cmb2Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb3.rs b/va416xx/va416xx/src/can0/data1_cmb3.rs new file mode 100644 index 0000000..81d279e --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb3Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb3Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb3Spec; +impl crate::RegisterSpec for Data1Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb3::R`](R) reader structure"] +impl crate::Readable for Data1Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb3::W`](W) writer structure"] +impl crate::Writable for Data1Cmb3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB3 to value 0"] +impl crate::Resettable for Data1Cmb3Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb4.rs b/va416xx/va416xx/src/can0/data1_cmb4.rs new file mode 100644 index 0000000..cdd9dc1 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb4.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb4Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb4Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb4Spec; +impl crate::RegisterSpec for Data1Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb4::R`](R) reader structure"] +impl crate::Readable for Data1Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb4::W`](W) writer structure"] +impl crate::Writable for Data1Cmb4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB4 to value 0"] +impl crate::Resettable for Data1Cmb4Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb5.rs b/va416xx/va416xx/src/can0/data1_cmb5.rs new file mode 100644 index 0000000..71e5f30 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb5.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb5Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb5Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb5Spec; +impl crate::RegisterSpec for Data1Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb5::R`](R) reader structure"] +impl crate::Readable for Data1Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb5::W`](W) writer structure"] +impl crate::Writable for Data1Cmb5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB5 to value 0"] +impl crate::Resettable for Data1Cmb5Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb6.rs b/va416xx/va416xx/src/can0/data1_cmb6.rs new file mode 100644 index 0000000..f6070fa --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb6.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb6Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb6Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb6Spec; +impl crate::RegisterSpec for Data1Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb6::R`](R) reader structure"] +impl crate::Readable for Data1Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb6::W`](W) writer structure"] +impl crate::Writable for Data1Cmb6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB6 to value 0"] +impl crate::Resettable for Data1Cmb6Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb7.rs b/va416xx/va416xx/src/can0/data1_cmb7.rs new file mode 100644 index 0000000..33dfc5e --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb7.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb7Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb7Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb7Spec; +impl crate::RegisterSpec for Data1Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb7::R`](R) reader structure"] +impl crate::Readable for Data1Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb7::W`](W) writer structure"] +impl crate::Writable for Data1Cmb7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB7 to value 0"] +impl crate::Resettable for Data1Cmb7Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb8.rs b/va416xx/va416xx/src/can0/data1_cmb8.rs new file mode 100644 index 0000000..70e1a12 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb8.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb8Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb8Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb8Spec; +impl crate::RegisterSpec for Data1Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb8::R`](R) reader structure"] +impl crate::Readable for Data1Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb8::W`](W) writer structure"] +impl crate::Writable for Data1Cmb8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB8 to value 0"] +impl crate::Resettable for Data1Cmb8Spec {} diff --git a/va416xx/va416xx/src/can0/data1_cmb9.rs b/va416xx/va416xx/src/can0/data1_cmb9.rs new file mode 100644 index 0000000..ef7c32e --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_cmb9.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1Cmb9Spec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1Cmb9Spec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_cmb9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_cmb9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb9Spec; +impl crate::RegisterSpec for Data1Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb9::R`](R) reader structure"] +impl crate::Readable for Data1Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb9::W`](W) writer structure"] +impl crate::Writable for Data1Cmb9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_CMB9 to value 0"] +impl crate::Resettable for Data1Cmb9Spec {} diff --git a/va416xx/va416xx/src/can0/data1_hcmb.rs b/va416xx/va416xx/src/can0/data1_hcmb.rs new file mode 100644 index 0000000..7d1b9e6 --- /dev/null +++ b/va416xx/va416xx/src/can0/data1_hcmb.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA1_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&mut self) -> Byte4W<'_, Data1HcmbSpec> { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&mut self) -> Byte3W<'_, Data1HcmbSpec> { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data1_hcmb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1_hcmb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1HcmbSpec; +impl crate::RegisterSpec for Data1HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_hcmb::R`](R) reader structure"] +impl crate::Readable for Data1HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`data1_hcmb::W`](W) writer structure"] +impl crate::Writable for Data1HcmbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA1_HCMB to value 0"] +impl crate::Resettable for Data1HcmbSpec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb0.rs b/va416xx/va416xx/src/can0/data2_cmb0.rs new file mode 100644 index 0000000..a991989 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb0Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb0Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb0Spec; +impl crate::RegisterSpec for Data2Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb0::R`](R) reader structure"] +impl crate::Readable for Data2Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb0::W`](W) writer structure"] +impl crate::Writable for Data2Cmb0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB0 to value 0"] +impl crate::Resettable for Data2Cmb0Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb1.rs b/va416xx/va416xx/src/can0/data2_cmb1.rs new file mode 100644 index 0000000..b6fd1b2 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb1Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb1Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb1Spec; +impl crate::RegisterSpec for Data2Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb1::R`](R) reader structure"] +impl crate::Readable for Data2Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb1::W`](W) writer structure"] +impl crate::Writable for Data2Cmb1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB1 to value 0"] +impl crate::Resettable for Data2Cmb1Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb10.rs b/va416xx/va416xx/src/can0/data2_cmb10.rs new file mode 100644 index 0000000..b12549c --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb10.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb10Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb10Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb10Spec; +impl crate::RegisterSpec for Data2Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb10::R`](R) reader structure"] +impl crate::Readable for Data2Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb10::W`](W) writer structure"] +impl crate::Writable for Data2Cmb10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB10 to value 0"] +impl crate::Resettable for Data2Cmb10Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb11.rs b/va416xx/va416xx/src/can0/data2_cmb11.rs new file mode 100644 index 0000000..505151e --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb11.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb11Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb11Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb11Spec; +impl crate::RegisterSpec for Data2Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb11::R`](R) reader structure"] +impl crate::Readable for Data2Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb11::W`](W) writer structure"] +impl crate::Writable for Data2Cmb11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB11 to value 0"] +impl crate::Resettable for Data2Cmb11Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb12.rs b/va416xx/va416xx/src/can0/data2_cmb12.rs new file mode 100644 index 0000000..147ddf8 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb12.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb12Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb12Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb12Spec; +impl crate::RegisterSpec for Data2Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb12::R`](R) reader structure"] +impl crate::Readable for Data2Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb12::W`](W) writer structure"] +impl crate::Writable for Data2Cmb12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB12 to value 0"] +impl crate::Resettable for Data2Cmb12Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb13.rs b/va416xx/va416xx/src/can0/data2_cmb13.rs new file mode 100644 index 0000000..c9d6096 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb13.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb13Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb13Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb13Spec; +impl crate::RegisterSpec for Data2Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb13::R`](R) reader structure"] +impl crate::Readable for Data2Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb13::W`](W) writer structure"] +impl crate::Writable for Data2Cmb13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB13 to value 0"] +impl crate::Resettable for Data2Cmb13Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb14.rs b/va416xx/va416xx/src/can0/data2_cmb14.rs new file mode 100644 index 0000000..e3a212f --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb14.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb14Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb14Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb14Spec; +impl crate::RegisterSpec for Data2Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb14::R`](R) reader structure"] +impl crate::Readable for Data2Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb14::W`](W) writer structure"] +impl crate::Writable for Data2Cmb14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB14 to value 0"] +impl crate::Resettable for Data2Cmb14Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb2.rs b/va416xx/va416xx/src/can0/data2_cmb2.rs new file mode 100644 index 0000000..a9ff4fe --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb2Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb2Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb2Spec; +impl crate::RegisterSpec for Data2Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb2::R`](R) reader structure"] +impl crate::Readable for Data2Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb2::W`](W) writer structure"] +impl crate::Writable for Data2Cmb2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB2 to value 0"] +impl crate::Resettable for Data2Cmb2Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb3.rs b/va416xx/va416xx/src/can0/data2_cmb3.rs new file mode 100644 index 0000000..4358008 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb3Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb3Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb3Spec; +impl crate::RegisterSpec for Data2Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb3::R`](R) reader structure"] +impl crate::Readable for Data2Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb3::W`](W) writer structure"] +impl crate::Writable for Data2Cmb3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB3 to value 0"] +impl crate::Resettable for Data2Cmb3Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb4.rs b/va416xx/va416xx/src/can0/data2_cmb4.rs new file mode 100644 index 0000000..799bb76 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb4.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb4Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb4Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb4Spec; +impl crate::RegisterSpec for Data2Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb4::R`](R) reader structure"] +impl crate::Readable for Data2Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb4::W`](W) writer structure"] +impl crate::Writable for Data2Cmb4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB4 to value 0"] +impl crate::Resettable for Data2Cmb4Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb5.rs b/va416xx/va416xx/src/can0/data2_cmb5.rs new file mode 100644 index 0000000..2d39f51 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb5.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb5Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb5Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb5Spec; +impl crate::RegisterSpec for Data2Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb5::R`](R) reader structure"] +impl crate::Readable for Data2Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb5::W`](W) writer structure"] +impl crate::Writable for Data2Cmb5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB5 to value 0"] +impl crate::Resettable for Data2Cmb5Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb6.rs b/va416xx/va416xx/src/can0/data2_cmb6.rs new file mode 100644 index 0000000..f86ef5d --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb6.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb6Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb6Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb6Spec; +impl crate::RegisterSpec for Data2Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb6::R`](R) reader structure"] +impl crate::Readable for Data2Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb6::W`](W) writer structure"] +impl crate::Writable for Data2Cmb6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB6 to value 0"] +impl crate::Resettable for Data2Cmb6Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb7.rs b/va416xx/va416xx/src/can0/data2_cmb7.rs new file mode 100644 index 0000000..42efa19 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb7.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb7Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb7Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb7Spec; +impl crate::RegisterSpec for Data2Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb7::R`](R) reader structure"] +impl crate::Readable for Data2Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb7::W`](W) writer structure"] +impl crate::Writable for Data2Cmb7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB7 to value 0"] +impl crate::Resettable for Data2Cmb7Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb8.rs b/va416xx/va416xx/src/can0/data2_cmb8.rs new file mode 100644 index 0000000..07fe7c9 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb8.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb8Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb8Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb8Spec; +impl crate::RegisterSpec for Data2Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb8::R`](R) reader structure"] +impl crate::Readable for Data2Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb8::W`](W) writer structure"] +impl crate::Writable for Data2Cmb8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB8 to value 0"] +impl crate::Resettable for Data2Cmb8Spec {} diff --git a/va416xx/va416xx/src/can0/data2_cmb9.rs b/va416xx/va416xx/src/can0/data2_cmb9.rs new file mode 100644 index 0000000..657f087 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_cmb9.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2Cmb9Spec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2Cmb9Spec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_cmb9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_cmb9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb9Spec; +impl crate::RegisterSpec for Data2Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb9::R`](R) reader structure"] +impl crate::Readable for Data2Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb9::W`](W) writer structure"] +impl crate::Writable for Data2Cmb9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_CMB9 to value 0"] +impl crate::Resettable for Data2Cmb9Spec {} diff --git a/va416xx/va416xx/src/can0/data2_hcmb.rs b/va416xx/va416xx/src/can0/data2_hcmb.rs new file mode 100644 index 0000000..d4178b8 --- /dev/null +++ b/va416xx/va416xx/src/can0/data2_hcmb.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA2_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&mut self) -> Byte6W<'_, Data2HcmbSpec> { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&mut self) -> Byte5W<'_, Data2HcmbSpec> { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::Reg::read) this register and get [`data2_hcmb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2_hcmb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2HcmbSpec; +impl crate::RegisterSpec for Data2HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_hcmb::R`](R) reader structure"] +impl crate::Readable for Data2HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`data2_hcmb::W`](W) writer structure"] +impl crate::Writable for Data2HcmbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA2_HCMB to value 0"] +impl crate::Resettable for Data2HcmbSpec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb0.rs b/va416xx/va416xx/src/can0/data3_cmb0.rs new file mode 100644 index 0000000..b29a99d --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb0Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb0Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb0Spec; +impl crate::RegisterSpec for Data3Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb0::R`](R) reader structure"] +impl crate::Readable for Data3Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb0::W`](W) writer structure"] +impl crate::Writable for Data3Cmb0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB0 to value 0"] +impl crate::Resettable for Data3Cmb0Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb1.rs b/va416xx/va416xx/src/can0/data3_cmb1.rs new file mode 100644 index 0000000..252f0de --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb1Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb1Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb1Spec; +impl crate::RegisterSpec for Data3Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb1::R`](R) reader structure"] +impl crate::Readable for Data3Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb1::W`](W) writer structure"] +impl crate::Writable for Data3Cmb1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB1 to value 0"] +impl crate::Resettable for Data3Cmb1Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb10.rs b/va416xx/va416xx/src/can0/data3_cmb10.rs new file mode 100644 index 0000000..6893044 --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb10.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb10Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb10Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb10Spec; +impl crate::RegisterSpec for Data3Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb10::R`](R) reader structure"] +impl crate::Readable for Data3Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb10::W`](W) writer structure"] +impl crate::Writable for Data3Cmb10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB10 to value 0"] +impl crate::Resettable for Data3Cmb10Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb11.rs b/va416xx/va416xx/src/can0/data3_cmb11.rs new file mode 100644 index 0000000..2779cd8 --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb11.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb11Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb11Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb11Spec; +impl crate::RegisterSpec for Data3Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb11::R`](R) reader structure"] +impl crate::Readable for Data3Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb11::W`](W) writer structure"] +impl crate::Writable for Data3Cmb11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB11 to value 0"] +impl crate::Resettable for Data3Cmb11Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb12.rs b/va416xx/va416xx/src/can0/data3_cmb12.rs new file mode 100644 index 0000000..4a6dc45 --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb12.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb12Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb12Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb12Spec; +impl crate::RegisterSpec for Data3Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb12::R`](R) reader structure"] +impl crate::Readable for Data3Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb12::W`](W) writer structure"] +impl crate::Writable for Data3Cmb12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB12 to value 0"] +impl crate::Resettable for Data3Cmb12Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb13.rs b/va416xx/va416xx/src/can0/data3_cmb13.rs new file mode 100644 index 0000000..4c994c5 --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb13.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb13Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb13Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb13Spec; +impl crate::RegisterSpec for Data3Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb13::R`](R) reader structure"] +impl crate::Readable for Data3Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb13::W`](W) writer structure"] +impl crate::Writable for Data3Cmb13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB13 to value 0"] +impl crate::Resettable for Data3Cmb13Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb14.rs b/va416xx/va416xx/src/can0/data3_cmb14.rs new file mode 100644 index 0000000..b340e4e --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb14.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb14Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb14Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb14Spec; +impl crate::RegisterSpec for Data3Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb14::R`](R) reader structure"] +impl crate::Readable for Data3Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb14::W`](W) writer structure"] +impl crate::Writable for Data3Cmb14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB14 to value 0"] +impl crate::Resettable for Data3Cmb14Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb2.rs b/va416xx/va416xx/src/can0/data3_cmb2.rs new file mode 100644 index 0000000..ee87b2d --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb2.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb2Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb2Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb2Spec; +impl crate::RegisterSpec for Data3Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb2::R`](R) reader structure"] +impl crate::Readable for Data3Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb2::W`](W) writer structure"] +impl crate::Writable for Data3Cmb2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB2 to value 0"] +impl crate::Resettable for Data3Cmb2Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb3.rs b/va416xx/va416xx/src/can0/data3_cmb3.rs new file mode 100644 index 0000000..18009cc --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb3.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb3Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb3Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb3Spec; +impl crate::RegisterSpec for Data3Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb3::R`](R) reader structure"] +impl crate::Readable for Data3Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb3::W`](W) writer structure"] +impl crate::Writable for Data3Cmb3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB3 to value 0"] +impl crate::Resettable for Data3Cmb3Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb4.rs b/va416xx/va416xx/src/can0/data3_cmb4.rs new file mode 100644 index 0000000..2c01cbb --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb4.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb4Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb4Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb4Spec; +impl crate::RegisterSpec for Data3Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb4::R`](R) reader structure"] +impl crate::Readable for Data3Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb4::W`](W) writer structure"] +impl crate::Writable for Data3Cmb4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB4 to value 0"] +impl crate::Resettable for Data3Cmb4Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb5.rs b/va416xx/va416xx/src/can0/data3_cmb5.rs new file mode 100644 index 0000000..65f043e --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb5.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb5Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb5Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb5Spec; +impl crate::RegisterSpec for Data3Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb5::R`](R) reader structure"] +impl crate::Readable for Data3Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb5::W`](W) writer structure"] +impl crate::Writable for Data3Cmb5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB5 to value 0"] +impl crate::Resettable for Data3Cmb5Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb6.rs b/va416xx/va416xx/src/can0/data3_cmb6.rs new file mode 100644 index 0000000..5839749 --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb6.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb6Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb6Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb6Spec; +impl crate::RegisterSpec for Data3Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb6::R`](R) reader structure"] +impl crate::Readable for Data3Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb6::W`](W) writer structure"] +impl crate::Writable for Data3Cmb6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB6 to value 0"] +impl crate::Resettable for Data3Cmb6Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb7.rs b/va416xx/va416xx/src/can0/data3_cmb7.rs new file mode 100644 index 0000000..c92ef72 --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb7.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb7Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb7Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb7Spec; +impl crate::RegisterSpec for Data3Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb7::R`](R) reader structure"] +impl crate::Readable for Data3Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb7::W`](W) writer structure"] +impl crate::Writable for Data3Cmb7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB7 to value 0"] +impl crate::Resettable for Data3Cmb7Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb8.rs b/va416xx/va416xx/src/can0/data3_cmb8.rs new file mode 100644 index 0000000..72c20ac --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb8.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb8Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb8Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb8Spec; +impl crate::RegisterSpec for Data3Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb8::R`](R) reader structure"] +impl crate::Readable for Data3Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb8::W`](W) writer structure"] +impl crate::Writable for Data3Cmb8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB8 to value 0"] +impl crate::Resettable for Data3Cmb8Spec {} diff --git a/va416xx/va416xx/src/can0/data3_cmb9.rs b/va416xx/va416xx/src/can0/data3_cmb9.rs new file mode 100644 index 0000000..3aeef82 --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_cmb9.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3Cmb9Spec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3Cmb9Spec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_cmb9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_cmb9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb9Spec; +impl crate::RegisterSpec for Data3Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb9::R`](R) reader structure"] +impl crate::Readable for Data3Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb9::W`](W) writer structure"] +impl crate::Writable for Data3Cmb9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_CMB9 to value 0"] +impl crate::Resettable for Data3Cmb9Spec {} diff --git a/va416xx/va416xx/src/can0/data3_hcmb.rs b/va416xx/va416xx/src/can0/data3_hcmb.rs new file mode 100644 index 0000000..b10ad27 --- /dev/null +++ b/va416xx/va416xx/src/can0/data3_hcmb.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DATA3_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&mut self) -> Byte8W<'_, Data3HcmbSpec> { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&mut self) -> Byte7W<'_, Data3HcmbSpec> { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::Reg::read) this register and get [`data3_hcmb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3_hcmb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3HcmbSpec; +impl crate::RegisterSpec for Data3HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_hcmb::R`](R) reader structure"] +impl crate::Readable for Data3HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`data3_hcmb::W`](W) writer structure"] +impl crate::Writable for Data3HcmbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA3_HCMB to value 0"] +impl crate::Resettable for Data3HcmbSpec {} diff --git a/va416xx/va416xx/src/can0/gmskb.rs b/va416xx/va416xx/src/can0/gmskb.rs new file mode 100644 index 0000000..db833c0 --- /dev/null +++ b/va416xx/va416xx/src/can0/gmskb.rs @@ -0,0 +1,77 @@ +#[doc = "Register `GMSKB` reader"] +pub type R = crate::R; +#[doc = "Register `GMSKB` writer"] +pub type W = crate::W; +#[doc = "Field `GM0` reader - GM\\[17:15\\] - Unused in standard, ID\\[17:15\\] in extended"] +pub type Gm0R = crate::FieldReader; +#[doc = "Field `GM0` writer - GM\\[17:15\\] - Unused in standard, ID\\[17:15\\] in extended"] +pub type Gm0W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IDE` reader - Identifier Extension Bit"] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - Identifier Extension Bit"] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTR` reader - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GM1` reader - GM\\[28:18\\] - ID\\[10:0\\] in standard, ID\\[28:18\\] in extended"] +pub type Gm1R = crate::FieldReader; +#[doc = "Field `GM1` writer - GM\\[28:18\\] - ID\\[10:0\\] in standard, ID\\[28:18\\] in extended"] +pub type Gm1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:2 - GM\\[17:15\\] - Unused in standard, ID\\[17:15\\] in extended"] + #[inline(always)] + pub fn gm0(&self) -> Gm0R { + Gm0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:15 - GM\\[28:18\\] - ID\\[10:0\\] in standard, ID\\[28:18\\] in extended"] + #[inline(always)] + pub fn gm1(&self) -> Gm1R { + Gm1R::new(((self.bits >> 5) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - GM\\[17:15\\] - Unused in standard, ID\\[17:15\\] in extended"] + #[inline(always)] + pub fn gm0(&mut self) -> Gm0W<'_, GmskbSpec> { + Gm0W::new(self, 0) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&mut self) -> IdeW<'_, GmskbSpec> { + IdeW::new(self, 3) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&mut self) -> RtrW<'_, GmskbSpec> { + RtrW::new(self, 4) + } + #[doc = "Bits 5:15 - GM\\[28:18\\] - ID\\[10:0\\] in standard, ID\\[28:18\\] in extended"] + #[inline(always)] + pub fn gm1(&mut self) -> Gm1W<'_, GmskbSpec> { + Gm1W::new(self, 5) + } +} +#[doc = "CAN Global Mask Base\n\nYou can [`read`](crate::Reg::read) this register and get [`gmskb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gmskb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GmskbSpec; +impl crate::RegisterSpec for GmskbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmskb::R`](R) reader structure"] +impl crate::Readable for GmskbSpec {} +#[doc = "`write(|w| ..)` method takes [`gmskb::W`](W) writer structure"] +impl crate::Writable for GmskbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GMSKB to value 0"] +impl crate::Resettable for GmskbSpec {} diff --git a/va416xx/va416xx/src/can0/gmskx.rs b/va416xx/va416xx/src/can0/gmskx.rs new file mode 100644 index 0000000..5897eed --- /dev/null +++ b/va416xx/va416xx/src/can0/gmskx.rs @@ -0,0 +1,49 @@ +#[doc = "Register `GMSKX` reader"] +pub type R = crate::R; +#[doc = "Register `GMSKX` writer"] +pub type W = crate::W; +#[doc = "Field `XRTR` reader - Extended Remote transmission Request Bit"] +pub type XrtrR = crate::BitReader; +#[doc = "Field `XRTR` writer - Extended Remote transmission Request Bit"] +pub type XrtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GM` reader - GM\\[14:0\\] used when an extended frame is received. ID\\[14:0\\] in extended, unused standard"] +pub type GmR = crate::FieldReader; +#[doc = "Field `GM` writer - GM\\[14:0\\] used when an extended frame is received. ID\\[14:0\\] in extended, unused standard"] +pub type GmW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&self) -> XrtrR { + XrtrR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:15 - GM\\[14:0\\] used when an extended frame is received. ID\\[14:0\\] in extended, unused standard"] + #[inline(always)] + pub fn gm(&self) -> GmR { + GmR::new(((self.bits >> 1) & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&mut self) -> XrtrW<'_, GmskxSpec> { + XrtrW::new(self, 0) + } + #[doc = "Bits 1:15 - GM\\[14:0\\] used when an extended frame is received. ID\\[14:0\\] in extended, unused standard"] + #[inline(always)] + pub fn gm(&mut self) -> GmW<'_, GmskxSpec> { + GmW::new(self, 1) + } +} +#[doc = "CAN Global Mask Extension\n\nYou can [`read`](crate::Reg::read) this register and get [`gmskx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gmskx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GmskxSpec; +impl crate::RegisterSpec for GmskxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmskx::R`](R) reader structure"] +impl crate::Readable for GmskxSpec {} +#[doc = "`write(|w| ..)` method takes [`gmskx::W`](W) writer structure"] +impl crate::Writable for GmskxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets GMSKX to value 0"] +impl crate::Resettable for GmskxSpec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb0.rs b/va416xx/va416xx/src/can0/id0_cmb0.rs new file mode 100644 index 0000000..0d0e2c2 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb0Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb0Spec; +impl crate::RegisterSpec for Id0Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb0::R`](R) reader structure"] +impl crate::Readable for Id0Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb0::W`](W) writer structure"] +impl crate::Writable for Id0Cmb0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB0 to value 0"] +impl crate::Resettable for Id0Cmb0Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb1.rs b/va416xx/va416xx/src/can0/id0_cmb1.rs new file mode 100644 index 0000000..c37bf13 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb1Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb1Spec; +impl crate::RegisterSpec for Id0Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb1::R`](R) reader structure"] +impl crate::Readable for Id0Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb1::W`](W) writer structure"] +impl crate::Writable for Id0Cmb1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB1 to value 0"] +impl crate::Resettable for Id0Cmb1Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb10.rs b/va416xx/va416xx/src/can0/id0_cmb10.rs new file mode 100644 index 0000000..c12da5e --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb10.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb10Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb10Spec; +impl crate::RegisterSpec for Id0Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb10::R`](R) reader structure"] +impl crate::Readable for Id0Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb10::W`](W) writer structure"] +impl crate::Writable for Id0Cmb10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB10 to value 0"] +impl crate::Resettable for Id0Cmb10Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb11.rs b/va416xx/va416xx/src/can0/id0_cmb11.rs new file mode 100644 index 0000000..f6a6279 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb11.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb11Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb11Spec; +impl crate::RegisterSpec for Id0Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb11::R`](R) reader structure"] +impl crate::Readable for Id0Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb11::W`](W) writer structure"] +impl crate::Writable for Id0Cmb11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB11 to value 0"] +impl crate::Resettable for Id0Cmb11Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb12.rs b/va416xx/va416xx/src/can0/id0_cmb12.rs new file mode 100644 index 0000000..8f9cbe0 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb12.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb12Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb12Spec; +impl crate::RegisterSpec for Id0Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb12::R`](R) reader structure"] +impl crate::Readable for Id0Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb12::W`](W) writer structure"] +impl crate::Writable for Id0Cmb12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB12 to value 0"] +impl crate::Resettable for Id0Cmb12Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb13.rs b/va416xx/va416xx/src/can0/id0_cmb13.rs new file mode 100644 index 0000000..7f7d93a --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb13.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb13Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb13Spec; +impl crate::RegisterSpec for Id0Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb13::R`](R) reader structure"] +impl crate::Readable for Id0Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb13::W`](W) writer structure"] +impl crate::Writable for Id0Cmb13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB13 to value 0"] +impl crate::Resettable for Id0Cmb13Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb14.rs b/va416xx/va416xx/src/can0/id0_cmb14.rs new file mode 100644 index 0000000..b678630 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb14.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb14Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb14Spec; +impl crate::RegisterSpec for Id0Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb14::R`](R) reader structure"] +impl crate::Readable for Id0Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb14::W`](W) writer structure"] +impl crate::Writable for Id0Cmb14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB14 to value 0"] +impl crate::Resettable for Id0Cmb14Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb2.rs b/va416xx/va416xx/src/can0/id0_cmb2.rs new file mode 100644 index 0000000..99dde1b --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb2Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb2Spec; +impl crate::RegisterSpec for Id0Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb2::R`](R) reader structure"] +impl crate::Readable for Id0Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb2::W`](W) writer structure"] +impl crate::Writable for Id0Cmb2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB2 to value 0"] +impl crate::Resettable for Id0Cmb2Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb3.rs b/va416xx/va416xx/src/can0/id0_cmb3.rs new file mode 100644 index 0000000..5b4cf64 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb3Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb3Spec; +impl crate::RegisterSpec for Id0Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb3::R`](R) reader structure"] +impl crate::Readable for Id0Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb3::W`](W) writer structure"] +impl crate::Writable for Id0Cmb3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB3 to value 0"] +impl crate::Resettable for Id0Cmb3Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb4.rs b/va416xx/va416xx/src/can0/id0_cmb4.rs new file mode 100644 index 0000000..0e7cdd0 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb4.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb4Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb4Spec; +impl crate::RegisterSpec for Id0Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb4::R`](R) reader structure"] +impl crate::Readable for Id0Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb4::W`](W) writer structure"] +impl crate::Writable for Id0Cmb4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB4 to value 0"] +impl crate::Resettable for Id0Cmb4Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb5.rs b/va416xx/va416xx/src/can0/id0_cmb5.rs new file mode 100644 index 0000000..e1539c2 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb5.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb5Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb5Spec; +impl crate::RegisterSpec for Id0Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb5::R`](R) reader structure"] +impl crate::Readable for Id0Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb5::W`](W) writer structure"] +impl crate::Writable for Id0Cmb5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB5 to value 0"] +impl crate::Resettable for Id0Cmb5Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb6.rs b/va416xx/va416xx/src/can0/id0_cmb6.rs new file mode 100644 index 0000000..97adb78 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb6.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb6Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb6Spec; +impl crate::RegisterSpec for Id0Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb6::R`](R) reader structure"] +impl crate::Readable for Id0Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb6::W`](W) writer structure"] +impl crate::Writable for Id0Cmb6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB6 to value 0"] +impl crate::Resettable for Id0Cmb6Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb7.rs b/va416xx/va416xx/src/can0/id0_cmb7.rs new file mode 100644 index 0000000..e03298a --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb7.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb7Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb7Spec; +impl crate::RegisterSpec for Id0Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb7::R`](R) reader structure"] +impl crate::Readable for Id0Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb7::W`](W) writer structure"] +impl crate::Writable for Id0Cmb7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB7 to value 0"] +impl crate::Resettable for Id0Cmb7Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb8.rs b/va416xx/va416xx/src/can0/id0_cmb8.rs new file mode 100644 index 0000000..18799c1 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb8.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb8Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb8Spec; +impl crate::RegisterSpec for Id0Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb8::R`](R) reader structure"] +impl crate::Readable for Id0Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb8::W`](W) writer structure"] +impl crate::Writable for Id0Cmb8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB8 to value 0"] +impl crate::Resettable for Id0Cmb8Spec {} diff --git a/va416xx/va416xx/src/can0/id0_cmb9.rs b/va416xx/va416xx/src/can0/id0_cmb9.rs new file mode 100644 index 0000000..9b2471a --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_cmb9.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0Cmb9Spec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_cmb9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_cmb9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb9Spec; +impl crate::RegisterSpec for Id0Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb9::R`](R) reader structure"] +impl crate::Readable for Id0Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb9::W`](W) writer structure"] +impl crate::Writable for Id0Cmb9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_CMB9 to value 0"] +impl crate::Resettable for Id0Cmb9Spec {} diff --git a/va416xx/va416xx/src/can0/id0_hcmb.rs b/va416xx/va416xx/src/can0/id0_hcmb.rs new file mode 100644 index 0000000..ecb3cd9 --- /dev/null +++ b/va416xx/va416xx/src/can0/id0_hcmb.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID0_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&mut self) -> Id0W<'_, Id0HcmbSpec> { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::Reg::read) this register and get [`id0_hcmb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id0_hcmb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0HcmbSpec; +impl crate::RegisterSpec for Id0HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_hcmb::R`](R) reader structure"] +impl crate::Readable for Id0HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`id0_hcmb::W`](W) writer structure"] +impl crate::Writable for Id0HcmbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID0_HCMB to value 0"] +impl crate::Resettable for Id0HcmbSpec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb0.rs b/va416xx/va416xx/src/can0/id1_cmb0.rs new file mode 100644 index 0000000..ca211c4 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb0Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb0Spec; +impl crate::RegisterSpec for Id1Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb0::R`](R) reader structure"] +impl crate::Readable for Id1Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb0::W`](W) writer structure"] +impl crate::Writable for Id1Cmb0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB0 to value 0"] +impl crate::Resettable for Id1Cmb0Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb1.rs b/va416xx/va416xx/src/can0/id1_cmb1.rs new file mode 100644 index 0000000..9ccc3a0 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb1Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb1Spec; +impl crate::RegisterSpec for Id1Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb1::R`](R) reader structure"] +impl crate::Readable for Id1Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb1::W`](W) writer structure"] +impl crate::Writable for Id1Cmb1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB1 to value 0"] +impl crate::Resettable for Id1Cmb1Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb10.rs b/va416xx/va416xx/src/can0/id1_cmb10.rs new file mode 100644 index 0000000..c9acf7d --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb10.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb10Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb10Spec; +impl crate::RegisterSpec for Id1Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb10::R`](R) reader structure"] +impl crate::Readable for Id1Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb10::W`](W) writer structure"] +impl crate::Writable for Id1Cmb10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB10 to value 0"] +impl crate::Resettable for Id1Cmb10Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb11.rs b/va416xx/va416xx/src/can0/id1_cmb11.rs new file mode 100644 index 0000000..2c44b9b --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb11.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb11Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb11Spec; +impl crate::RegisterSpec for Id1Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb11::R`](R) reader structure"] +impl crate::Readable for Id1Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb11::W`](W) writer structure"] +impl crate::Writable for Id1Cmb11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB11 to value 0"] +impl crate::Resettable for Id1Cmb11Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb12.rs b/va416xx/va416xx/src/can0/id1_cmb12.rs new file mode 100644 index 0000000..74cc7ee --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb12.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb12Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb12Spec; +impl crate::RegisterSpec for Id1Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb12::R`](R) reader structure"] +impl crate::Readable for Id1Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb12::W`](W) writer structure"] +impl crate::Writable for Id1Cmb12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB12 to value 0"] +impl crate::Resettable for Id1Cmb12Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb13.rs b/va416xx/va416xx/src/can0/id1_cmb13.rs new file mode 100644 index 0000000..8cb14e6 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb13.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb13Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb13Spec; +impl crate::RegisterSpec for Id1Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb13::R`](R) reader structure"] +impl crate::Readable for Id1Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb13::W`](W) writer structure"] +impl crate::Writable for Id1Cmb13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB13 to value 0"] +impl crate::Resettable for Id1Cmb13Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb14.rs b/va416xx/va416xx/src/can0/id1_cmb14.rs new file mode 100644 index 0000000..dda21ed --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb14.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb14Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb14Spec; +impl crate::RegisterSpec for Id1Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb14::R`](R) reader structure"] +impl crate::Readable for Id1Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb14::W`](W) writer structure"] +impl crate::Writable for Id1Cmb14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB14 to value 0"] +impl crate::Resettable for Id1Cmb14Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb2.rs b/va416xx/va416xx/src/can0/id1_cmb2.rs new file mode 100644 index 0000000..ab36ef7 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb2Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb2Spec; +impl crate::RegisterSpec for Id1Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb2::R`](R) reader structure"] +impl crate::Readable for Id1Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb2::W`](W) writer structure"] +impl crate::Writable for Id1Cmb2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB2 to value 0"] +impl crate::Resettable for Id1Cmb2Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb3.rs b/va416xx/va416xx/src/can0/id1_cmb3.rs new file mode 100644 index 0000000..2174457 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb3Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb3Spec; +impl crate::RegisterSpec for Id1Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb3::R`](R) reader structure"] +impl crate::Readable for Id1Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb3::W`](W) writer structure"] +impl crate::Writable for Id1Cmb3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB3 to value 0"] +impl crate::Resettable for Id1Cmb3Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb4.rs b/va416xx/va416xx/src/can0/id1_cmb4.rs new file mode 100644 index 0000000..e46b000 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb4.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb4Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb4Spec; +impl crate::RegisterSpec for Id1Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb4::R`](R) reader structure"] +impl crate::Readable for Id1Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb4::W`](W) writer structure"] +impl crate::Writable for Id1Cmb4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB4 to value 0"] +impl crate::Resettable for Id1Cmb4Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb5.rs b/va416xx/va416xx/src/can0/id1_cmb5.rs new file mode 100644 index 0000000..d17f343 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb5.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb5Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb5Spec; +impl crate::RegisterSpec for Id1Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb5::R`](R) reader structure"] +impl crate::Readable for Id1Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb5::W`](W) writer structure"] +impl crate::Writable for Id1Cmb5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB5 to value 0"] +impl crate::Resettable for Id1Cmb5Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb6.rs b/va416xx/va416xx/src/can0/id1_cmb6.rs new file mode 100644 index 0000000..3374a90 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb6.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb6Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb6Spec; +impl crate::RegisterSpec for Id1Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb6::R`](R) reader structure"] +impl crate::Readable for Id1Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb6::W`](W) writer structure"] +impl crate::Writable for Id1Cmb6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB6 to value 0"] +impl crate::Resettable for Id1Cmb6Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb7.rs b/va416xx/va416xx/src/can0/id1_cmb7.rs new file mode 100644 index 0000000..a2a8620 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb7.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb7Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb7Spec; +impl crate::RegisterSpec for Id1Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb7::R`](R) reader structure"] +impl crate::Readable for Id1Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb7::W`](W) writer structure"] +impl crate::Writable for Id1Cmb7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB7 to value 0"] +impl crate::Resettable for Id1Cmb7Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb8.rs b/va416xx/va416xx/src/can0/id1_cmb8.rs new file mode 100644 index 0000000..51f98cb --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb8.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb8Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb8Spec; +impl crate::RegisterSpec for Id1Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb8::R`](R) reader structure"] +impl crate::Readable for Id1Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb8::W`](W) writer structure"] +impl crate::Writable for Id1Cmb8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB8 to value 0"] +impl crate::Resettable for Id1Cmb8Spec {} diff --git a/va416xx/va416xx/src/can0/id1_cmb9.rs b/va416xx/va416xx/src/can0/id1_cmb9.rs new file mode 100644 index 0000000..777ec4f --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_cmb9.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1Cmb9Spec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_cmb9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_cmb9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb9Spec; +impl crate::RegisterSpec for Id1Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb9::R`](R) reader structure"] +impl crate::Readable for Id1Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb9::W`](W) writer structure"] +impl crate::Writable for Id1Cmb9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_CMB9 to value 0"] +impl crate::Resettable for Id1Cmb9Spec {} diff --git a/va416xx/va416xx/src/can0/id1_hcmb.rs b/va416xx/va416xx/src/can0/id1_hcmb.rs new file mode 100644 index 0000000..a6d1146 --- /dev/null +++ b/va416xx/va416xx/src/can0/id1_hcmb.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ID1_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&mut self) -> Id1W<'_, Id1HcmbSpec> { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::Reg::read) this register and get [`id1_hcmb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id1_hcmb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1HcmbSpec; +impl crate::RegisterSpec for Id1HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_hcmb::R`](R) reader structure"] +impl crate::Readable for Id1HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`id1_hcmb::W`](W) writer structure"] +impl crate::Writable for Id1HcmbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ID1_HCMB to value 0"] +impl crate::Resettable for Id1HcmbSpec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb0.rs b/va416xx/va416xx/src/can0/tstp_cmb0.rs new file mode 100644 index 0000000..c9b1c10 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb0Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb0Spec; +impl crate::RegisterSpec for TstpCmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb0::R`](R) reader structure"] +impl crate::Readable for TstpCmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb0::W`](W) writer structure"] +impl crate::Writable for TstpCmb0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB0 to value 0"] +impl crate::Resettable for TstpCmb0Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb1.rs b/va416xx/va416xx/src/can0/tstp_cmb1.rs new file mode 100644 index 0000000..8422f84 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb1Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb1Spec; +impl crate::RegisterSpec for TstpCmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb1::R`](R) reader structure"] +impl crate::Readable for TstpCmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb1::W`](W) writer structure"] +impl crate::Writable for TstpCmb1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB1 to value 0"] +impl crate::Resettable for TstpCmb1Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb10.rs b/va416xx/va416xx/src/can0/tstp_cmb10.rs new file mode 100644 index 0000000..e0f2ead --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb10.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb10Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb10Spec; +impl crate::RegisterSpec for TstpCmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb10::R`](R) reader structure"] +impl crate::Readable for TstpCmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb10::W`](W) writer structure"] +impl crate::Writable for TstpCmb10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB10 to value 0"] +impl crate::Resettable for TstpCmb10Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb11.rs b/va416xx/va416xx/src/can0/tstp_cmb11.rs new file mode 100644 index 0000000..f2f8a32 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb11.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb11Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb11Spec; +impl crate::RegisterSpec for TstpCmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb11::R`](R) reader structure"] +impl crate::Readable for TstpCmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb11::W`](W) writer structure"] +impl crate::Writable for TstpCmb11Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB11 to value 0"] +impl crate::Resettable for TstpCmb11Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb12.rs b/va416xx/va416xx/src/can0/tstp_cmb12.rs new file mode 100644 index 0000000..0420080 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb12.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb12Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb12Spec; +impl crate::RegisterSpec for TstpCmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb12::R`](R) reader structure"] +impl crate::Readable for TstpCmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb12::W`](W) writer structure"] +impl crate::Writable for TstpCmb12Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB12 to value 0"] +impl crate::Resettable for TstpCmb12Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb13.rs b/va416xx/va416xx/src/can0/tstp_cmb13.rs new file mode 100644 index 0000000..1645968 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb13.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb13Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb13Spec; +impl crate::RegisterSpec for TstpCmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb13::R`](R) reader structure"] +impl crate::Readable for TstpCmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb13::W`](W) writer structure"] +impl crate::Writable for TstpCmb13Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB13 to value 0"] +impl crate::Resettable for TstpCmb13Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb14.rs b/va416xx/va416xx/src/can0/tstp_cmb14.rs new file mode 100644 index 0000000..cba06c3 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb14.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb14Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb14Spec; +impl crate::RegisterSpec for TstpCmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb14::R`](R) reader structure"] +impl crate::Readable for TstpCmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb14::W`](W) writer structure"] +impl crate::Writable for TstpCmb14Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB14 to value 0"] +impl crate::Resettable for TstpCmb14Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb2.rs b/va416xx/va416xx/src/can0/tstp_cmb2.rs new file mode 100644 index 0000000..9d92124 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb2Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb2Spec; +impl crate::RegisterSpec for TstpCmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb2::R`](R) reader structure"] +impl crate::Readable for TstpCmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb2::W`](W) writer structure"] +impl crate::Writable for TstpCmb2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB2 to value 0"] +impl crate::Resettable for TstpCmb2Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb3.rs b/va416xx/va416xx/src/can0/tstp_cmb3.rs new file mode 100644 index 0000000..1f8c9c1 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb3Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb3Spec; +impl crate::RegisterSpec for TstpCmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb3::R`](R) reader structure"] +impl crate::Readable for TstpCmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb3::W`](W) writer structure"] +impl crate::Writable for TstpCmb3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB3 to value 0"] +impl crate::Resettable for TstpCmb3Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb4.rs b/va416xx/va416xx/src/can0/tstp_cmb4.rs new file mode 100644 index 0000000..a20dfea --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb4.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb4Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb4Spec; +impl crate::RegisterSpec for TstpCmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb4::R`](R) reader structure"] +impl crate::Readable for TstpCmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb4::W`](W) writer structure"] +impl crate::Writable for TstpCmb4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB4 to value 0"] +impl crate::Resettable for TstpCmb4Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb5.rs b/va416xx/va416xx/src/can0/tstp_cmb5.rs new file mode 100644 index 0000000..ca6f5b1 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb5.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb5Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb5Spec; +impl crate::RegisterSpec for TstpCmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb5::R`](R) reader structure"] +impl crate::Readable for TstpCmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb5::W`](W) writer structure"] +impl crate::Writable for TstpCmb5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB5 to value 0"] +impl crate::Resettable for TstpCmb5Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb6.rs b/va416xx/va416xx/src/can0/tstp_cmb6.rs new file mode 100644 index 0000000..e2ddb52 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb6.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb6Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb6Spec; +impl crate::RegisterSpec for TstpCmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb6::R`](R) reader structure"] +impl crate::Readable for TstpCmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb6::W`](W) writer structure"] +impl crate::Writable for TstpCmb6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB6 to value 0"] +impl crate::Resettable for TstpCmb6Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb7.rs b/va416xx/va416xx/src/can0/tstp_cmb7.rs new file mode 100644 index 0000000..77f5333 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb7.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb7Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb7Spec; +impl crate::RegisterSpec for TstpCmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb7::R`](R) reader structure"] +impl crate::Readable for TstpCmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb7::W`](W) writer structure"] +impl crate::Writable for TstpCmb7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB7 to value 0"] +impl crate::Resettable for TstpCmb7Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb8.rs b/va416xx/va416xx/src/can0/tstp_cmb8.rs new file mode 100644 index 0000000..2077474 --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb8.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb8Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb8Spec; +impl crate::RegisterSpec for TstpCmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb8::R`](R) reader structure"] +impl crate::Readable for TstpCmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb8::W`](W) writer structure"] +impl crate::Writable for TstpCmb8Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB8 to value 0"] +impl crate::Resettable for TstpCmb8Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_cmb9.rs b/va416xx/va416xx/src/can0/tstp_cmb9.rs new file mode 100644 index 0000000..a2edc6b --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_cmb9.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpCmb9Spec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_cmb9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_cmb9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb9Spec; +impl crate::RegisterSpec for TstpCmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb9::R`](R) reader structure"] +impl crate::Readable for TstpCmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb9::W`](W) writer structure"] +impl crate::Writable for TstpCmb9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_CMB9 to value 0"] +impl crate::Resettable for TstpCmb9Spec {} diff --git a/va416xx/va416xx/src/can0/tstp_hcmb.rs b/va416xx/va416xx/src/can0/tstp_hcmb.rs new file mode 100644 index 0000000..89c980b --- /dev/null +++ b/va416xx/va416xx/src/can0/tstp_hcmb.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TSTP_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&mut self) -> TimestampW<'_, TstpHcmbSpec> { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::Reg::read) this register and get [`tstp_hcmb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tstp_hcmb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpHcmbSpec; +impl crate::RegisterSpec for TstpHcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_hcmb::R`](R) reader structure"] +impl crate::Readable for TstpHcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`tstp_hcmb::W`](W) writer structure"] +impl crate::Writable for TstpHcmbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TSTP_HCMB to value 0"] +impl crate::Resettable for TstpHcmbSpec {} diff --git a/va416xx/va416xx/src/clkgen.rs b/va416xx/va416xx/src/clkgen.rs new file mode 100644 index 0000000..2b9a43a --- /dev/null +++ b/va416xx/va416xx/src/clkgen.rs @@ -0,0 +1,39 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl0: Ctrl0, + stat: Stat, + ctrl1: Ctrl1, +} +impl RegisterBlock { + #[doc = "0x00 - Clock Generation Module Control Register 0"] + #[inline(always)] + pub const fn ctrl0(&self) -> &Ctrl0 { + &self.ctrl0 + } + #[doc = "0x04 - Clock Generation Module Status Register"] + #[inline(always)] + pub const fn stat(&self) -> &Stat { + &self.stat + } + #[doc = "0x08 - Clock Generation Module Control Register 1"] + #[inline(always)] + pub const fn ctrl1(&self) -> &Ctrl1 { + &self.ctrl1 + } +} +#[doc = "CTRL0 (rw) register accessor: Clock Generation Module Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] module"] +#[doc(alias = "CTRL0")] +pub type Ctrl0 = crate::Reg; +#[doc = "Clock Generation Module Control Register 0"] +pub mod ctrl0; +#[doc = "STAT (r) register accessor: Clock Generation Module Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"] +#[doc(alias = "STAT")] +pub type Stat = crate::Reg; +#[doc = "Clock Generation Module Status Register"] +pub mod stat; +#[doc = "CTRL1 (rw) register accessor: Clock Generation Module Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"] +#[doc(alias = "CTRL1")] +pub type Ctrl1 = crate::Reg; +#[doc = "Clock Generation Module Control Register 1"] +pub mod ctrl1; diff --git a/va416xx/va416xx/src/clkgen/ctrl0.rs b/va416xx/va416xx/src/clkgen/ctrl0.rs new file mode 100644 index 0000000..fe55d26 --- /dev/null +++ b/va416xx/va416xx/src/clkgen/ctrl0.rs @@ -0,0 +1,205 @@ +#[doc = "Register `CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REF_CLK_SEL` reader - PLL Reference Clock Select"] +pub type RefClkSelR = crate::FieldReader; +#[doc = "Field `REF_CLK_SEL` writer - PLL Reference Clock Select"] +pub type RefClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CLKSEL_SYS` reader - Input clock select to PLL"] +pub type ClkselSysR = crate::FieldReader; +#[doc = "Field `CLKSEL_SYS` writer - Input clock select to PLL"] +pub type ClkselSysW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PLL_INTFB` reader - PLL Symbol; select internal feedback path when high rather than FCLK"] +pub type PllIntfbR = crate::BitReader; +#[doc = "Field `PLL_INTFB` writer - PLL Symbol; select internal feedback path when high rather than FCLK"] +pub type PllIntfbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_PWDN` reader - PLL Symbol; power down when high"] +pub type PllPwdnR = crate::BitReader; +#[doc = "Field `PLL_PWDN` writer - PLL Symbol; power down when high"] +pub type PllPwdnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_BYPASS` reader - PLL Symbol; reference-to-output bypass when high"] +pub type PllBypassR = crate::BitReader; +#[doc = "Field `PLL_BYPASS` writer - PLL Symbol; reference-to-output bypass when high"] +pub type PllBypassW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_TEST` reader - PLL Symbol; Reference-to-counters-to-output bypass when high"] +pub type PllTestR = crate::BitReader; +#[doc = "Field `PLL_TEST` writer - PLL Symbol; Reference-to-counters-to-output bypass when high"] +pub type PllTestW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_BWADJ` reader - PLL Symbol; selects the values 1-64 for the bandwidth divider"] +pub type PllBwadjR = crate::FieldReader; +#[doc = "Field `PLL_BWADJ` writer - PLL Symbol; selects the values 1-64 for the bandwidth divider"] +pub type PllBwadjW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PLL_CLKOD` reader - PLL Symbol; selects the values 1-16 for the post VCO divider"] +pub type PllClkodR = crate::FieldReader; +#[doc = "Field `PLL_CLKOD` writer - PLL Symbol; selects the values 1-16 for the post VCO divider"] +pub type PllClkodW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PLL_CLKF` reader - PLL Symbol; selects the values 1-64 for the multiplication factor"] +pub type PllClkfR = crate::FieldReader; +#[doc = "Field `PLL_CLKF` writer - PLL Symbol; selects the values 1-64 for the multiplication factor"] +pub type PllClkfW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PLL_CLKR` reader - PLL Symbol; selects the values 1-16 for the reference divider"] +pub type PllClkrR = crate::FieldReader; +#[doc = "Field `PLL_CLKR` writer - PLL Symbol; selects the values 1-16 for the reference divider"] +pub type PllClkrW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CLK_DIV_SEL` reader - Selects the PLL out divider to divide by 1/2/4/8"] +pub type ClkDivSelR = crate::FieldReader; +#[doc = "Field `CLK_DIV_SEL` writer - Selects the PLL out divider to divide by 1/2/4/8"] +pub type ClkDivSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PLL_RESET` reader - Writing this bit to 1 puts the PLL into reset"] +pub type PllResetR = crate::BitReader; +#[doc = "Field `PLL_RESET` writer - Writing this bit to 1 puts the PLL into reset"] +pub type PllResetW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYS_CLK_LOST_DET_EN` reader - Enable the circuit that detects loss of SYS_CLK"] +pub type SysClkLostDetEnR = crate::BitReader; +#[doc = "Field `SYS_CLK_LOST_DET_EN` writer - Enable the circuit that detects loss of SYS_CLK"] +pub type SysClkLostDetEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - PLL Reference Clock Select"] + #[inline(always)] + pub fn ref_clk_sel(&self) -> RefClkSelR { + RefClkSelR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Input clock select to PLL"] + #[inline(always)] + pub fn clksel_sys(&self) -> ClkselSysR { + ClkselSysR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - PLL Symbol; select internal feedback path when high rather than FCLK"] + #[inline(always)] + pub fn pll_intfb(&self) -> PllIntfbR { + PllIntfbR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - PLL Symbol; power down when high"] + #[inline(always)] + pub fn pll_pwdn(&self) -> PllPwdnR { + PllPwdnR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - PLL Symbol; reference-to-output bypass when high"] + #[inline(always)] + pub fn pll_bypass(&self) -> PllBypassR { + PllBypassR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - PLL Symbol; Reference-to-counters-to-output bypass when high"] + #[inline(always)] + pub fn pll_test(&self) -> PllTestR { + PllTestR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:13 - PLL Symbol; selects the values 1-64 for the bandwidth divider"] + #[inline(always)] + pub fn pll_bwadj(&self) -> PllBwadjR { + PllBwadjR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 14:17 - PLL Symbol; selects the values 1-16 for the post VCO divider"] + #[inline(always)] + pub fn pll_clkod(&self) -> PllClkodR { + PllClkodR::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:23 - PLL Symbol; selects the values 1-64 for the multiplication factor"] + #[inline(always)] + pub fn pll_clkf(&self) -> PllClkfR { + PllClkfR::new(((self.bits >> 18) & 0x3f) as u8) + } + #[doc = "Bits 24:27 - PLL Symbol; selects the values 1-16 for the reference divider"] + #[inline(always)] + pub fn pll_clkr(&self) -> PllClkrR { + PllClkrR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:29 - Selects the PLL out divider to divide by 1/2/4/8"] + #[inline(always)] + pub fn clk_div_sel(&self) -> ClkDivSelR { + ClkDivSelR::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 30 - Writing this bit to 1 puts the PLL into reset"] + #[inline(always)] + pub fn pll_reset(&self) -> PllResetR { + PllResetR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Enable the circuit that detects loss of SYS_CLK"] + #[inline(always)] + pub fn sys_clk_lost_det_en(&self) -> SysClkLostDetEnR { + SysClkLostDetEnR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - PLL Reference Clock Select"] + #[inline(always)] + pub fn ref_clk_sel(&mut self) -> RefClkSelW<'_, Ctrl0Spec> { + RefClkSelW::new(self, 0) + } + #[doc = "Bits 2:3 - Input clock select to PLL"] + #[inline(always)] + pub fn clksel_sys(&mut self) -> ClkselSysW<'_, Ctrl0Spec> { + ClkselSysW::new(self, 2) + } + #[doc = "Bit 4 - PLL Symbol; select internal feedback path when high rather than FCLK"] + #[inline(always)] + pub fn pll_intfb(&mut self) -> PllIntfbW<'_, Ctrl0Spec> { + PllIntfbW::new(self, 4) + } + #[doc = "Bit 5 - PLL Symbol; power down when high"] + #[inline(always)] + pub fn pll_pwdn(&mut self) -> PllPwdnW<'_, Ctrl0Spec> { + PllPwdnW::new(self, 5) + } + #[doc = "Bit 6 - PLL Symbol; reference-to-output bypass when high"] + #[inline(always)] + pub fn pll_bypass(&mut self) -> PllBypassW<'_, Ctrl0Spec> { + PllBypassW::new(self, 6) + } + #[doc = "Bit 7 - PLL Symbol; Reference-to-counters-to-output bypass when high"] + #[inline(always)] + pub fn pll_test(&mut self) -> PllTestW<'_, Ctrl0Spec> { + PllTestW::new(self, 7) + } + #[doc = "Bits 8:13 - PLL Symbol; selects the values 1-64 for the bandwidth divider"] + #[inline(always)] + pub fn pll_bwadj(&mut self) -> PllBwadjW<'_, Ctrl0Spec> { + PllBwadjW::new(self, 8) + } + #[doc = "Bits 14:17 - PLL Symbol; selects the values 1-16 for the post VCO divider"] + #[inline(always)] + pub fn pll_clkod(&mut self) -> PllClkodW<'_, Ctrl0Spec> { + PllClkodW::new(self, 14) + } + #[doc = "Bits 18:23 - PLL Symbol; selects the values 1-64 for the multiplication factor"] + #[inline(always)] + pub fn pll_clkf(&mut self) -> PllClkfW<'_, Ctrl0Spec> { + PllClkfW::new(self, 18) + } + #[doc = "Bits 24:27 - PLL Symbol; selects the values 1-16 for the reference divider"] + #[inline(always)] + pub fn pll_clkr(&mut self) -> PllClkrW<'_, Ctrl0Spec> { + PllClkrW::new(self, 24) + } + #[doc = "Bits 28:29 - Selects the PLL out divider to divide by 1/2/4/8"] + #[inline(always)] + pub fn clk_div_sel(&mut self) -> ClkDivSelW<'_, Ctrl0Spec> { + ClkDivSelW::new(self, 28) + } + #[doc = "Bit 30 - Writing this bit to 1 puts the PLL into reset"] + #[inline(always)] + pub fn pll_reset(&mut self) -> PllResetW<'_, Ctrl0Spec> { + PllResetW::new(self, 30) + } + #[doc = "Bit 31 - Enable the circuit that detects loss of SYS_CLK"] + #[inline(always)] + pub fn sys_clk_lost_det_en(&mut self) -> SysClkLostDetEnW<'_, Ctrl0Spec> { + SysClkLostDetEnW::new(self, 31) + } +} +#[doc = "Clock Generation Module Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl0Spec; +impl crate::RegisterSpec for Ctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"] +impl crate::Readable for Ctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"] +impl crate::Writable for Ctrl0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL0 to value 0x30"] +impl crate::Resettable for Ctrl0Spec { + const RESET_VALUE: u32 = 0x30; +} diff --git a/va416xx/va416xx/src/clkgen/ctrl1.rs b/va416xx/va416xx/src/clkgen/ctrl1.rs new file mode 100644 index 0000000..889cde8 --- /dev/null +++ b/va416xx/va416xx/src/clkgen/ctrl1.rs @@ -0,0 +1,105 @@ +#[doc = "Register `CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `SYS_CLK_LOST_DET_REARM` reader - Resets/Rearms the SYS_CLK lost detection feature"] +pub type SysClkLostDetRearmR = crate::BitReader; +#[doc = "Field `SYS_CLK_LOST_DET_REARM` writer - Resets/Rearms the SYS_CLK lost detection feature"] +pub type SysClkLostDetRearmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_LCK_DET_REARM` reader - Resets/Rearms the PLL lock detect circuit"] +pub type PllLckDetRearmR = crate::BitReader; +#[doc = "Field `PLL_LCK_DET_REARM` writer - Resets/Rearms the PLL lock detect circuit"] +pub type PllLckDetRearmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_LOST_LOCK_DET_EN` reader - Enables the PLL lock lost detection circuit"] +pub type PllLostLockDetEnR = crate::BitReader; +#[doc = "Field `PLL_LOST_LOCK_DET_EN` writer - Enables the PLL lock lost detection circuit"] +pub type PllLostLockDetEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XTAL_EN` reader - Enables the crystal oscillator"] +pub type XtalEnR = crate::BitReader; +#[doc = "Field `XTAL_EN` writer - Enables the crystal oscillator"] +pub type XtalEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XTAL_N_EN` reader - Enables XTAL_N output"] +pub type XtalNEnR = crate::BitReader; +#[doc = "Field `XTAL_N_EN` writer - Enables XTAL_N output"] +pub type XtalNEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_CLK_DIV_SEL` reader - Clock divider select for ADC"] +pub type AdcClkDivSelR = crate::FieldReader; +#[doc = "Field `ADC_CLK_DIV_SEL` writer - Clock divider select for ADC"] +pub type AdcClkDivSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Resets/Rearms the SYS_CLK lost detection feature"] + #[inline(always)] + pub fn sys_clk_lost_det_rearm(&self) -> SysClkLostDetRearmR { + SysClkLostDetRearmR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Resets/Rearms the PLL lock detect circuit"] + #[inline(always)] + pub fn pll_lck_det_rearm(&self) -> PllLckDetRearmR { + PllLckDetRearmR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables the PLL lock lost detection circuit"] + #[inline(always)] + pub fn pll_lost_lock_det_en(&self) -> PllLostLockDetEnR { + PllLostLockDetEnR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables the crystal oscillator"] + #[inline(always)] + pub fn xtal_en(&self) -> XtalEnR { + XtalEnR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables XTAL_N output"] + #[inline(always)] + pub fn xtal_n_en(&self) -> XtalNEnR { + XtalNEnR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Clock divider select for ADC"] + #[inline(always)] + pub fn adc_clk_div_sel(&self) -> AdcClkDivSelR { + AdcClkDivSelR::new(((self.bits >> 5) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Resets/Rearms the SYS_CLK lost detection feature"] + #[inline(always)] + pub fn sys_clk_lost_det_rearm(&mut self) -> SysClkLostDetRearmW<'_, Ctrl1Spec> { + SysClkLostDetRearmW::new(self, 0) + } + #[doc = "Bit 1 - Resets/Rearms the PLL lock detect circuit"] + #[inline(always)] + pub fn pll_lck_det_rearm(&mut self) -> PllLckDetRearmW<'_, Ctrl1Spec> { + PllLckDetRearmW::new(self, 1) + } + #[doc = "Bit 2 - Enables the PLL lock lost detection circuit"] + #[inline(always)] + pub fn pll_lost_lock_det_en(&mut self) -> PllLostLockDetEnW<'_, Ctrl1Spec> { + PllLostLockDetEnW::new(self, 2) + } + #[doc = "Bit 3 - Enables the crystal oscillator"] + #[inline(always)] + pub fn xtal_en(&mut self) -> XtalEnW<'_, Ctrl1Spec> { + XtalEnW::new(self, 3) + } + #[doc = "Bit 4 - Enables XTAL_N output"] + #[inline(always)] + pub fn xtal_n_en(&mut self) -> XtalNEnW<'_, Ctrl1Spec> { + XtalNEnW::new(self, 4) + } + #[doc = "Bits 5:6 - Clock divider select for ADC"] + #[inline(always)] + pub fn adc_clk_div_sel(&mut self) -> AdcClkDivSelW<'_, Ctrl1Spec> { + AdcClkDivSelW::new(self, 5) + } +} +#[doc = "Clock Generation Module Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1Spec; +impl crate::RegisterSpec for Ctrl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"] +impl crate::Readable for Ctrl1Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] +impl crate::Writable for Ctrl1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for Ctrl1Spec {} diff --git a/va416xx/va416xx/src/clkgen/stat.rs b/va416xx/va416xx/src/clkgen/stat.rs new file mode 100644 index 0000000..f13249a --- /dev/null +++ b/va416xx/va416xx/src/clkgen/stat.rs @@ -0,0 +1,41 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Field `FBSLIP` reader - Feedback cycle slip output (CLKOUT frequency low)"] +pub type FbslipR = crate::BitReader; +#[doc = "Field `RFSLIP` reader - Reference cycle slip output (CLKOUT frequency high)"] +pub type RfslipR = crate::BitReader; +#[doc = "Field `LOCKLOST` reader - LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles"] +pub type LocklostR = crate::BitReader; +#[doc = "Field `SYSCLKLOST` reader - Set when SYS_CLK has dropped to less than 1MHz"] +pub type SysclklostR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Feedback cycle slip output (CLKOUT frequency low)"] + #[inline(always)] + pub fn fbslip(&self) -> FbslipR { + FbslipR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reference cycle slip output (CLKOUT frequency high)"] + #[inline(always)] + pub fn rfslip(&self) -> RfslipR { + RfslipR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles"] + #[inline(always)] + pub fn locklost(&self) -> LocklostR { + LocklostR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set when SYS_CLK has dropped to less than 1MHz"] + #[inline(always)] + pub fn sysclklost(&self) -> SysclklostR { + SysclklostR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Clock Generation Module Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatSpec; +impl crate::RegisterSpec for StatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for StatSpec {} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for StatSpec {} diff --git a/va416xx/va416xx/src/dac0.rs b/va416xx/va416xx/src/dac0.rs new file mode 100644 index 0000000..d7b8e1b --- /dev/null +++ b/va416xx/va416xx/src/dac0.rs @@ -0,0 +1,128 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl0: Ctrl0, + ctrl1: Ctrl1, + fifo_data: FifoData, + status: Status, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + txfifoirqtrg: Txfifoirqtrg, + fifo_clr: FifoClr, + _reserved10: [u8; 0x07d4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register 0"] + #[inline(always)] + pub const fn ctrl0(&self) -> &Ctrl0 { + &self.ctrl0 + } + #[doc = "0x04 - Control Register 1"] + #[inline(always)] + pub const fn ctrl1(&self) -> &Ctrl1 { + &self.ctrl1 + } + #[doc = "0x08 - FIFO data"] + #[inline(always)] + pub const fn fifo_data(&self) -> &FifoData { + &self.fifo_data + } + #[doc = "0x0c - Status"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x10 - Interrupt Enable"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x14 - Raw Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x18 - Enabled Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x1c - Clear Interrupt"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x20 - Receive FIFO Interrupt Trigger Value"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x24 - FIFO Clear"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x7fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] module"] +#[doc(alias = "CTRL0")] +pub type Ctrl0 = crate::Reg; +#[doc = "Control Register 0"] +pub mod ctrl0; +#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"] +#[doc(alias = "CTRL1")] +pub type Ctrl1 = crate::Reg; +#[doc = "Control Register 1"] +pub mod ctrl1; +#[doc = "FIFO_DATA (rw) register accessor: FIFO data\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_data`] module"] +#[doc(alias = "FIFO_DATA")] +pub type FifoData = crate::Reg; +#[doc = "FIFO data"] +pub mod fifo_data; +#[doc = "STATUS (r) register accessor: Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod irq_enb; +#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] module"] +#[doc(alias = "IRQ_RAW")] +pub type IrqRaw = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END (r) register accessor: Enabled Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] module"] +#[doc(alias = "IRQ_END")] +pub type IrqEnd = crate::Reg; +#[doc = "Enabled Interrupt Status"] +pub mod irq_end; +#[doc = "IRQ_CLR (w) register accessor: Clear Interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_clr`] module"] +#[doc(alias = "IRQ_CLR")] +pub type IrqClr = crate::Reg; +#[doc = "Clear Interrupt"] +pub mod irq_clr; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Receive FIFO Interrupt Trigger Value"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR (rw) register accessor: FIFO Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "FIFO Clear"] +pub mod fifo_clr; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/dac0/ctrl0.rs b/va416xx/va416xx/src/dac0/ctrl0.rs new file mode 100644 index 0000000..6c1b290 --- /dev/null +++ b/va416xx/va416xx/src/dac0/ctrl0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `EXT_TRIG_EN` reader - Enables external trigger"] +pub type ExtTrigEnR = crate::BitReader; +#[doc = "Field `EXT_TRIG_EN` writer - Enables external trigger"] +pub type ExtTrigEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAN_TRIG_EN` reader - Enables manual trigger"] +pub type ManTrigEnR = crate::BitReader; +#[doc = "Field `MAN_TRIG_EN` writer - Enables manual trigger"] +pub type ManTrigEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 10 - Enables external trigger"] + #[inline(always)] + pub fn ext_trig_en(&self) -> ExtTrigEnR { + ExtTrigEnR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enables manual trigger"] + #[inline(always)] + pub fn man_trig_en(&self) -> ManTrigEnR { + ManTrigEnR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 10 - Enables external trigger"] + #[inline(always)] + pub fn ext_trig_en(&mut self) -> ExtTrigEnW<'_, Ctrl0Spec> { + ExtTrigEnW::new(self, 10) + } + #[doc = "Bit 11 - Enables manual trigger"] + #[inline(always)] + pub fn man_trig_en(&mut self) -> ManTrigEnW<'_, Ctrl0Spec> { + ManTrigEnW::new(self, 11) + } +} +#[doc = "Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl0Spec; +impl crate::RegisterSpec for Ctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"] +impl crate::Readable for Ctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"] +impl crate::Writable for Ctrl0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL0 to value 0"] +impl crate::Resettable for Ctrl0Spec {} diff --git a/va416xx/va416xx/src/dac0/ctrl1.rs b/va416xx/va416xx/src/dac0/ctrl1.rs new file mode 100644 index 0000000..e36b49c --- /dev/null +++ b/va416xx/va416xx/src/dac0/ctrl1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `DAC_SETTLING` reader - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] +pub type DacSettlingR = crate::FieldReader; +#[doc = "Field `DAC_SETTLING` writer - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] +pub type DacSettlingW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DAC_EN` reader - Enables the DAC analog block"] +pub type DacEnR = crate::BitReader; +#[doc = "Field `DAC_EN` writer - Enables the DAC analog block"] +pub type DacEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 5:7 - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] + #[inline(always)] + pub fn dac_settling(&self) -> DacSettlingR { + DacSettlingR::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 8 - Enables the DAC analog block"] + #[inline(always)] + pub fn dac_en(&self) -> DacEnR { + DacEnR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:7 - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] + #[inline(always)] + pub fn dac_settling(&mut self) -> DacSettlingW<'_, Ctrl1Spec> { + DacSettlingW::new(self, 5) + } + #[doc = "Bit 8 - Enables the DAC analog block"] + #[inline(always)] + pub fn dac_en(&mut self) -> DacEnW<'_, Ctrl1Spec> { + DacEnW::new(self, 8) + } +} +#[doc = "Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1Spec; +impl crate::RegisterSpec for Ctrl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"] +impl crate::Readable for Ctrl1Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] +impl crate::Writable for Ctrl1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for Ctrl1Spec {} diff --git a/va416xx/va416xx/src/dac0/fifo_clr.rs b/va416xx/va416xx/src/dac0/fifo_clr.rs new file mode 100644 index 0000000..58d31ae --- /dev/null +++ b/va416xx/va416xx/src/dac0/fifo_clr.rs @@ -0,0 +1,26 @@ +#[doc = "Register `FIFO_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_CLR` writer - Clears the DAC FIFO. Always reads 0"] +pub type FifoClrW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clears the DAC FIFO. Always reads 0"] + #[inline(always)] + pub fn fifo_clr(&mut self) -> FifoClrW<'_, FifoClrSpec> { + FifoClrW::new(self, 0) + } +} +#[doc = "FIFO Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_clr::R`](R) reader structure"] +impl crate::Readable for FifoClrSpec {} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec {} diff --git a/va416xx/va416xx/src/dac0/fifo_data.rs b/va416xx/va416xx/src/dac0/fifo_data.rs new file mode 100644 index 0000000..3eed88f --- /dev/null +++ b/va416xx/va416xx/src/dac0/fifo_data.rs @@ -0,0 +1,26 @@ +#[doc = "Register `FIFO_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data for FIFO write"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl W { + #[doc = "Bits 0:11 - Data for FIFO write"] + #[inline(always)] + pub fn data(&mut self) -> DataW<'_, FifoDataSpec> { + DataW::new(self, 0) + } +} +#[doc = "FIFO data\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoDataSpec; +impl crate::RegisterSpec for FifoDataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_data::R`](R) reader structure"] +impl crate::Readable for FifoDataSpec {} +#[doc = "`write(|w| ..)` method takes [`fifo_data::W`](W) writer structure"] +impl crate::Writable for FifoDataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIFO_DATA to value 0"] +impl crate::Resettable for FifoDataSpec {} diff --git a/va416xx/va416xx/src/dac0/irq_clr.rs b/va416xx/va416xx/src/dac0/irq_clr.rs new file mode 100644 index 0000000..5902dc0 --- /dev/null +++ b/va416xx/va416xx/src/dac0/irq_clr.rs @@ -0,0 +1,43 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_OFLOW` writer - Clears the FIFO overflow interrupt status. Always reads 0"] +pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_UFLOW` writer - Clears the FIFO underflow interrupt status. Always reads 0"] +pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DAC_DONE` writer - Clears the DAC done interrupt status. Always reads 0"] +pub type DacDoneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRIG_ERROR` writer - Clears the trigger error interrupt status. Always reads 0"] +pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"] + #[inline(always)] + pub fn fifo_oflow(&mut self) -> FifoOflowW<'_, IrqClrSpec> { + FifoOflowW::new(self, 0) + } + #[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"] + #[inline(always)] + pub fn fifo_uflow(&mut self) -> FifoUflowW<'_, IrqClrSpec> { + FifoUflowW::new(self, 1) + } + #[doc = "Bit 2 - Clears the DAC done interrupt status. Always reads 0"] + #[inline(always)] + pub fn dac_done(&mut self) -> DacDoneW<'_, IrqClrSpec> { + DacDoneW::new(self, 2) + } + #[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"] + #[inline(always)] + pub fn trig_error(&mut self) -> TrigErrorW<'_, IrqClrSpec> { + TrigErrorW::new(self, 3) + } +} +#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqClrSpec; +impl crate::RegisterSpec for IrqClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`irq_clr::W`](W) writer structure"] +impl crate::Writable for IrqClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IrqClrSpec {} diff --git a/va416xx/va416xx/src/dac0/irq_enb.rs b/va416xx/va416xx/src/dac0/irq_enb.rs new file mode 100644 index 0000000..4eb2e59 --- /dev/null +++ b/va416xx/va416xx/src/dac0/irq_enb.rs @@ -0,0 +1,119 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"] +pub type FifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"] +pub type FifoFullW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"] +pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"] +pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DAC_DONE` reader - Enables the interrupt for a DAC data acquisition completion"] +pub type DacDoneR = crate::BitReader; +#[doc = "Field `DAC_DONE` writer - Enables the interrupt for a DAC data acquisition completion"] +pub type DacDoneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"] +pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] +pub type FifoDepthTrigW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables the interrupt for a DAC data acquisition completion"] + #[inline(always)] + pub fn dac_done(&self) -> DacDoneR { + DacDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&mut self) -> FifoEmptyW<'_, IrqEnbSpec> { + FifoEmptyW::new(self, 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&mut self) -> FifoFullW<'_, IrqEnbSpec> { + FifoFullW::new(self, 1) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&mut self) -> FifoOflowW<'_, IrqEnbSpec> { + FifoOflowW::new(self, 2) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&mut self) -> FifoUflowW<'_, IrqEnbSpec> { + FifoUflowW::new(self, 3) + } + #[doc = "Bit 4 - Enables the interrupt for a DAC data acquisition completion"] + #[inline(always)] + pub fn dac_done(&mut self) -> DacDoneW<'_, IrqEnbSpec> { + DacDoneW::new(self, 4) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&mut self) -> TrigErrorW<'_, IrqEnbSpec> { + TrigErrorW::new(self, 5) + } + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&mut self) -> FifoDepthTrigW<'_, IrqEnbSpec> { + FifoDepthTrigW::new(self, 6) + } +} +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va416xx/va416xx/src/dac0/irq_end.rs b/va416xx/va416xx/src/dac0/irq_end.rs new file mode 100644 index 0000000..42b69d7 --- /dev/null +++ b/va416xx/va416xx/src/dac0/irq_end.rs @@ -0,0 +1,62 @@ +#[doc = "Register `IRQ_END` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty and the interrupt is enabled"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full and the interrupt is enabled"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred and the interrupt is enabled"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` reader - Indicates a FIFO underflow occurred and the interrupt is enabled"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `DAC_DONE` reader - Indicates that a DAC conversion is done and the interrupt is enabled"] +pub type DacDoneR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled"] +pub type FifoDepthTrigR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the FIFO is empty and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates a FIFO underflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates that a DAC conversion is done and the interrupt is enabled"] + #[inline(always)] + pub fn dac_done(&self) -> DacDoneR { + DacDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Enabled Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEndSpec; +impl crate::RegisterSpec for IrqEndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"] +impl crate::Readable for IrqEndSpec {} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IrqEndSpec {} diff --git a/va416xx/va416xx/src/dac0/irq_raw.rs b/va416xx/va416xx/src/dac0/irq_raw.rs new file mode 100644 index 0000000..2fd40ef --- /dev/null +++ b/va416xx/va416xx/src/dac0/irq_raw.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` reader - Indicates data was unavailable when a new trigger for DAC update is received"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `DAC_DONE` reader - Indicates that a DAC conversion is done"] +pub type DacDoneR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the FIFO entry count is less than or equal to the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the FIFO is empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates data was unavailable when a new trigger for DAC update is received"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates that a DAC conversion is done"] + #[inline(always)] + pub fn dac_done(&self) -> DacDoneR { + DacDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the FIFO entry count is less than or equal to the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqRawSpec; +impl crate::RegisterSpec for IrqRawSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"] +impl crate::Readable for IrqRawSpec {} +#[doc = "`reset()` method sets IRQ_RAW to value 0x41"] +impl crate::Resettable for IrqRawSpec { + const RESET_VALUE: u32 = 0x41; +} diff --git a/va416xx/va416xx/src/dac0/perid.rs b/va416xx/va416xx/src/dac0/perid.rs new file mode 100644 index 0000000..6eb9587 --- /dev/null +++ b/va416xx/va416xx/src/dac0/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0020_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0020_07e9; +} diff --git a/va416xx/va416xx/src/dac0/status.rs b/va416xx/va416xx/src/dac0/status.rs new file mode 100644 index 0000000..e5696cd --- /dev/null +++ b/va416xx/va416xx/src/dac0/status.rs @@ -0,0 +1,27 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_ENTRY_CNT` reader - Indicates the number of entries in the FIFO"] +pub type FifoEntryCntR = crate::FieldReader; +#[doc = "Field `DAC_BUSY` reader - Indicates a DAC data acquisition is in process"] +pub type DacBusyR = crate::BitReader; +impl R { + #[doc = "Bits 0:5 - Indicates the number of entries in the FIFO"] + #[inline(always)] + pub fn fifo_entry_cnt(&self) -> FifoEntryCntR { + FifoEntryCntR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Indicates a DAC data acquisition is in process"] + #[inline(always)] + pub fn dac_busy(&self) -> DacBusyR { + DacBusyR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec {} diff --git a/va416xx/va416xx/src/dac0/txfifoirqtrg.rs b/va416xx/va416xx/src/dac0/txfifoirqtrg.rs new file mode 100644 index 0000000..b0c8a4f --- /dev/null +++ b/va416xx/va416xx/src/dac0/txfifoirqtrg.rs @@ -0,0 +1,37 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub type LevelR = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&self) -> LevelR { + LevelR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&mut self) -> LevelW<'_, TxfifoirqtrgSpec> { + LevelW::new(self, 0) + } +} +#[doc = "Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0x10"] +impl crate::Resettable for TxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0x10; +} diff --git a/va416xx/va416xx/src/dma.rs b/va416xx/va416xx/src/dma.rs new file mode 100644 index 0000000..921287a --- /dev/null +++ b/va416xx/va416xx/src/dma.rs @@ -0,0 +1,400 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + status: Status, + cfg: Cfg, + ctrl_base_ptr: CtrlBasePtr, + alt_ctrl_base_ptr: AltCtrlBasePtr, + waitonreq_status: WaitonreqStatus, + chnl_sw_request: ChnlSwRequest, + chnl_useburst_set: ChnlUseburstSet, + chnl_useburst_clr: ChnlUseburstClr, + chnl_req_mask_set: ChnlReqMaskSet, + chnl_req_mask_clr: ChnlReqMaskClr, + chnl_enable_set: ChnlEnableSet, + chnl_enable_clr: ChnlEnableClr, + chnl_pri_alt_set: ChnlPriAltSet, + chnl_pri_alt_clr: ChnlPriAltClr, + chnl_priority_set: ChnlPrioritySet, + chnl_priority_clr: ChnlPriorityClr, + _reserved16: [u8; 0x0c], + err_clr: ErrClr, + _reserved17: [u8; 0x0db0], + integration_cfg: IntegrationCfg, + _reserved18: [u8; 0x04], + stall_status: StallStatus, + _reserved19: [u8; 0x04], + dma_req_status: DmaReqStatus, + _reserved20: [u8; 0x04], + dma_sreq_status: DmaSreqStatus, + _reserved21: [u8; 0x04], + dma_done_set: DmaDoneSet, + dma_done_clr: DmaDoneClr, + dma_active_set: DmaActiveSet, + dma_active_clr: DmaActiveClr, + _reserved25: [u8; 0x18], + err_set: ErrSet, + _reserved26: [u8; 0x0184], + periph_id_4: PeriphId4, + _reserved27: [u8; 0x0c], + periph_id_0: PeriphId0, + periph_id_1: PeriphId1, + periph_id_2: PeriphId2, + periph_id_3: PeriphId3, + primecell_id_0: PrimecellId0, + primecell_id_1: PrimecellId1, + primecell_id_2: PrimecellId2, + primecell_id_3: PrimecellId3, +} +impl RegisterBlock { + #[doc = "0x00 - DMA Status"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x04 - DMA Configuration"] + #[inline(always)] + pub const fn cfg(&self) -> &Cfg { + &self.cfg + } + #[doc = "0x08 - Base Pointer for DMA Control Registers"] + #[inline(always)] + pub const fn ctrl_base_ptr(&self) -> &CtrlBasePtr { + &self.ctrl_base_ptr + } + #[doc = "0x0c - DMA Channel alternate control data base pointer"] + #[inline(always)] + pub const fn alt_ctrl_base_ptr(&self) -> &AltCtrlBasePtr { + &self.alt_ctrl_base_ptr + } + #[doc = "0x10 - DMA channel wait on request status"] + #[inline(always)] + pub const fn waitonreq_status(&self) -> &WaitonreqStatus { + &self.waitonreq_status + } + #[doc = "0x14 - DMA channel software request"] + #[inline(always)] + pub const fn chnl_sw_request(&self) -> &ChnlSwRequest { + &self.chnl_sw_request + } + #[doc = "0x18 - DMA channel useburst set"] + #[inline(always)] + pub const fn chnl_useburst_set(&self) -> &ChnlUseburstSet { + &self.chnl_useburst_set + } + #[doc = "0x1c - DMA channel useburst clear"] + #[inline(always)] + pub const fn chnl_useburst_clr(&self) -> &ChnlUseburstClr { + &self.chnl_useburst_clr + } + #[doc = "0x20 - DMA channel request mask set"] + #[inline(always)] + pub const fn chnl_req_mask_set(&self) -> &ChnlReqMaskSet { + &self.chnl_req_mask_set + } + #[doc = "0x24 - DMA channel request mask clear"] + #[inline(always)] + pub const fn chnl_req_mask_clr(&self) -> &ChnlReqMaskClr { + &self.chnl_req_mask_clr + } + #[doc = "0x28 - DMA channel enable set"] + #[inline(always)] + pub const fn chnl_enable_set(&self) -> &ChnlEnableSet { + &self.chnl_enable_set + } + #[doc = "0x2c - DMA channel enable clear"] + #[inline(always)] + pub const fn chnl_enable_clr(&self) -> &ChnlEnableClr { + &self.chnl_enable_clr + } + #[doc = "0x30 - DMA channel primary alternate set"] + #[inline(always)] + pub const fn chnl_pri_alt_set(&self) -> &ChnlPriAltSet { + &self.chnl_pri_alt_set + } + #[doc = "0x34 - DMA channel primary alternate clear"] + #[inline(always)] + pub const fn chnl_pri_alt_clr(&self) -> &ChnlPriAltClr { + &self.chnl_pri_alt_clr + } + #[doc = "0x38 - DMA channel priority set"] + #[inline(always)] + pub const fn chnl_priority_set(&self) -> &ChnlPrioritySet { + &self.chnl_priority_set + } + #[doc = "0x3c - DMA channel priority clear"] + #[inline(always)] + pub const fn chnl_priority_clr(&self) -> &ChnlPriorityClr { + &self.chnl_priority_clr + } + #[doc = "0x4c - DMA bus error clear"] + #[inline(always)] + pub const fn err_clr(&self) -> &ErrClr { + &self.err_clr + } + #[doc = "0xe00 - DMA integration configuration"] + #[inline(always)] + pub const fn integration_cfg(&self) -> &IntegrationCfg { + &self.integration_cfg + } + #[doc = "0xe08 - DMA stall status"] + #[inline(always)] + pub const fn stall_status(&self) -> &StallStatus { + &self.stall_status + } + #[doc = "0xe10 - DMA Configuration"] + #[inline(always)] + pub const fn dma_req_status(&self) -> &DmaReqStatus { + &self.dma_req_status + } + #[doc = "0xe18 - DMA single request status"] + #[inline(always)] + pub const fn dma_sreq_status(&self) -> &DmaSreqStatus { + &self.dma_sreq_status + } + #[doc = "0xe20 - DMA done set"] + #[inline(always)] + pub const fn dma_done_set(&self) -> &DmaDoneSet { + &self.dma_done_set + } + #[doc = "0xe24 - DMA done clear"] + #[inline(always)] + pub const fn dma_done_clr(&self) -> &DmaDoneClr { + &self.dma_done_clr + } + #[doc = "0xe28 - DMA active set"] + #[inline(always)] + pub const fn dma_active_set(&self) -> &DmaActiveSet { + &self.dma_active_set + } + #[doc = "0xe2c - DMA active clear"] + #[inline(always)] + pub const fn dma_active_clr(&self) -> &DmaActiveClr { + &self.dma_active_clr + } + #[doc = "0xe48 - DMA bus error set"] + #[inline(always)] + pub const fn err_set(&self) -> &ErrSet { + &self.err_set + } + #[doc = "0xfd0 - DMA Peripheral ID 4"] + #[inline(always)] + pub const fn periph_id_4(&self) -> &PeriphId4 { + &self.periph_id_4 + } + #[doc = "0xfe0 - DMA Peripheral ID 0"] + #[inline(always)] + pub const fn periph_id_0(&self) -> &PeriphId0 { + &self.periph_id_0 + } + #[doc = "0xfe4 - DMA Peripheral ID 1"] + #[inline(always)] + pub const fn periph_id_1(&self) -> &PeriphId1 { + &self.periph_id_1 + } + #[doc = "0xfe8 - DMA Peripheral ID 2"] + #[inline(always)] + pub const fn periph_id_2(&self) -> &PeriphId2 { + &self.periph_id_2 + } + #[doc = "0xfec - DMA Peripheral ID 3"] + #[inline(always)] + pub const fn periph_id_3(&self) -> &PeriphId3 { + &self.periph_id_3 + } + #[doc = "0xff0 - DMA PrimeCell ID 0"] + #[inline(always)] + pub const fn primecell_id_0(&self) -> &PrimecellId0 { + &self.primecell_id_0 + } + #[doc = "0xff4 - DMA PrimeCell ID 1"] + #[inline(always)] + pub const fn primecell_id_1(&self) -> &PrimecellId1 { + &self.primecell_id_1 + } + #[doc = "0xff8 - DMA PrimeCell ID 2"] + #[inline(always)] + pub const fn primecell_id_2(&self) -> &PrimecellId2 { + &self.primecell_id_2 + } + #[doc = "0xffc - DMA PrimeCell ID 3"] + #[inline(always)] + pub const fn primecell_id_3(&self) -> &PrimecellId3 { + &self.primecell_id_3 + } +} +#[doc = "STATUS (r) register accessor: DMA Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "DMA Status"] +pub mod status; +#[doc = "CFG (w) register accessor: DMA Configuration\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg`] module"] +#[doc(alias = "CFG")] +pub type Cfg = crate::Reg; +#[doc = "DMA Configuration"] +pub mod cfg; +#[doc = "CTRL_BASE_PTR (rw) register accessor: Base Pointer for DMA Control Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_base_ptr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_base_ptr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl_base_ptr`] module"] +#[doc(alias = "CTRL_BASE_PTR")] +pub type CtrlBasePtr = crate::Reg; +#[doc = "Base Pointer for DMA Control Registers"] +pub mod ctrl_base_ptr; +#[doc = "ALT_CTRL_BASE_PTR (rw) register accessor: DMA Channel alternate control data base pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`alt_ctrl_base_ptr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alt_ctrl_base_ptr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@alt_ctrl_base_ptr`] module"] +#[doc(alias = "ALT_CTRL_BASE_PTR")] +pub type AltCtrlBasePtr = crate::Reg; +#[doc = "DMA Channel alternate control data base pointer"] +pub mod alt_ctrl_base_ptr; +#[doc = "WAITONREQ_STATUS (r) register accessor: DMA channel wait on request status\n\nYou can [`read`](crate::Reg::read) this register and get [`waitonreq_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@waitonreq_status`] module"] +#[doc(alias = "WAITONREQ_STATUS")] +pub type WaitonreqStatus = crate::Reg; +#[doc = "DMA channel wait on request status"] +pub mod waitonreq_status; +#[doc = "CHNL_SW_REQUEST (w) register accessor: DMA channel software request\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_sw_request::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_sw_request`] module"] +#[doc(alias = "CHNL_SW_REQUEST")] +pub type ChnlSwRequest = crate::Reg; +#[doc = "DMA channel software request"] +pub mod chnl_sw_request; +#[doc = "CHNL_USEBURST_SET (rw) register accessor: DMA channel useburst set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_useburst_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_useburst_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_useburst_set`] module"] +#[doc(alias = "CHNL_USEBURST_SET")] +pub type ChnlUseburstSet = crate::Reg; +#[doc = "DMA channel useburst set"] +pub mod chnl_useburst_set; +#[doc = "CHNL_USEBURST_CLR (rw) register accessor: DMA channel useburst clear\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_useburst_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_useburst_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_useburst_clr`] module"] +#[doc(alias = "CHNL_USEBURST_CLR")] +pub type ChnlUseburstClr = crate::Reg; +#[doc = "DMA channel useburst clear"] +pub mod chnl_useburst_clr; +#[doc = "CHNL_REQ_MASK_SET (rw) register accessor: DMA channel request mask set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_req_mask_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_req_mask_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_req_mask_set`] module"] +#[doc(alias = "CHNL_REQ_MASK_SET")] +pub type ChnlReqMaskSet = crate::Reg; +#[doc = "DMA channel request mask set"] +pub mod chnl_req_mask_set; +#[doc = "CHNL_REQ_MASK_CLR (rw) register accessor: DMA channel request mask clear\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_req_mask_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_req_mask_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_req_mask_clr`] module"] +#[doc(alias = "CHNL_REQ_MASK_CLR")] +pub type ChnlReqMaskClr = crate::Reg; +#[doc = "DMA channel request mask clear"] +pub mod chnl_req_mask_clr; +#[doc = "CHNL_ENABLE_SET (rw) register accessor: DMA channel enable set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_enable_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_enable_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_enable_set`] module"] +#[doc(alias = "CHNL_ENABLE_SET")] +pub type ChnlEnableSet = crate::Reg; +#[doc = "DMA channel enable set"] +pub mod chnl_enable_set; +#[doc = "CHNL_ENABLE_CLR (rw) register accessor: DMA channel enable clear\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_enable_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_enable_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_enable_clr`] module"] +#[doc(alias = "CHNL_ENABLE_CLR")] +pub type ChnlEnableClr = crate::Reg; +#[doc = "DMA channel enable clear"] +pub mod chnl_enable_clr; +#[doc = "CHNL_PRI_ALT_SET (rw) register accessor: DMA channel primary alternate set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_pri_alt_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_pri_alt_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_pri_alt_set`] module"] +#[doc(alias = "CHNL_PRI_ALT_SET")] +pub type ChnlPriAltSet = crate::Reg; +#[doc = "DMA channel primary alternate set"] +pub mod chnl_pri_alt_set; +#[doc = "CHNL_PRI_ALT_CLR (rw) register accessor: DMA channel primary alternate clear\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_pri_alt_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_pri_alt_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_pri_alt_clr`] module"] +#[doc(alias = "CHNL_PRI_ALT_CLR")] +pub type ChnlPriAltClr = crate::Reg; +#[doc = "DMA channel primary alternate clear"] +pub mod chnl_pri_alt_clr; +#[doc = "CHNL_PRIORITY_SET (rw) register accessor: DMA channel priority set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_priority_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_priority_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_priority_set`] module"] +#[doc(alias = "CHNL_PRIORITY_SET")] +pub type ChnlPrioritySet = crate::Reg; +#[doc = "DMA channel priority set"] +pub mod chnl_priority_set; +#[doc = "CHNL_PRIORITY_CLR (w) register accessor: DMA channel priority clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_priority_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_priority_clr`] module"] +#[doc(alias = "CHNL_PRIORITY_CLR")] +pub type ChnlPriorityClr = crate::Reg; +#[doc = "DMA channel priority clear"] +pub mod chnl_priority_clr; +#[doc = "ERR_CLR (rw) register accessor: DMA bus error clear\n\nYou can [`read`](crate::Reg::read) this register and get [`err_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_clr`] module"] +#[doc(alias = "ERR_CLR")] +pub type ErrClr = crate::Reg; +#[doc = "DMA bus error clear"] +pub mod err_clr; +#[doc = "INTEGRATION_CFG (rw) register accessor: DMA integration configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`integration_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`integration_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@integration_cfg`] module"] +#[doc(alias = "INTEGRATION_CFG")] +pub type IntegrationCfg = crate::Reg; +#[doc = "DMA integration configuration"] +pub mod integration_cfg; +#[doc = "STALL_STATUS (rw) register accessor: DMA stall status\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_status`] module"] +#[doc(alias = "STALL_STATUS")] +pub type StallStatus = crate::Reg; +#[doc = "DMA stall status"] +pub mod stall_status; +#[doc = "DMA_REQ_STATUS (rw) register accessor: DMA Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_req_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_req_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_req_status`] module"] +#[doc(alias = "DMA_REQ_STATUS")] +pub type DmaReqStatus = crate::Reg; +#[doc = "DMA Configuration"] +pub mod dma_req_status; +#[doc = "DMA_SREQ_STATUS (rw) register accessor: DMA single request status\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sreq_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sreq_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_sreq_status`] module"] +#[doc(alias = "DMA_SREQ_STATUS")] +pub type DmaSreqStatus = crate::Reg; +#[doc = "DMA single request status"] +pub mod dma_sreq_status; +#[doc = "DMA_DONE_SET (rw) register accessor: DMA done set\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_done_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_done_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_done_set`] module"] +#[doc(alias = "DMA_DONE_SET")] +pub type DmaDoneSet = crate::Reg; +#[doc = "DMA done set"] +pub mod dma_done_set; +#[doc = "DMA_DONE_CLR (rw) register accessor: DMA done clear\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_done_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_done_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_done_clr`] module"] +#[doc(alias = "DMA_DONE_CLR")] +pub type DmaDoneClr = crate::Reg; +#[doc = "DMA done clear"] +pub mod dma_done_clr; +#[doc = "DMA_ACTIVE_SET (rw) register accessor: DMA active set\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_active_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_active_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_active_set`] module"] +#[doc(alias = "DMA_ACTIVE_SET")] +pub type DmaActiveSet = crate::Reg; +#[doc = "DMA active set"] +pub mod dma_active_set; +#[doc = "DMA_ACTIVE_CLR (rw) register accessor: DMA active clear\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_active_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_active_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_active_clr`] module"] +#[doc(alias = "DMA_ACTIVE_CLR")] +pub type DmaActiveClr = crate::Reg; +#[doc = "DMA active clear"] +pub mod dma_active_clr; +#[doc = "ERR_SET (rw) register accessor: DMA bus error set\n\nYou can [`read`](crate::Reg::read) this register and get [`err_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_set`] module"] +#[doc(alias = "ERR_SET")] +pub type ErrSet = crate::Reg; +#[doc = "DMA bus error set"] +pub mod err_set; +#[doc = "PERIPH_ID_4 (rw) register accessor: DMA Peripheral ID 4\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periph_id_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_4`] module"] +#[doc(alias = "PERIPH_ID_4")] +pub type PeriphId4 = crate::Reg; +#[doc = "DMA Peripheral ID 4"] +pub mod periph_id_4; +#[doc = "PERIPH_ID_0 (rw) register accessor: DMA Peripheral ID 0\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periph_id_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_0`] module"] +#[doc(alias = "PERIPH_ID_0")] +pub type PeriphId0 = crate::Reg; +#[doc = "DMA Peripheral ID 0"] +pub mod periph_id_0; +#[doc = "PERIPH_ID_1 (r) register accessor: DMA Peripheral ID 1\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_1`] module"] +#[doc(alias = "PERIPH_ID_1")] +pub type PeriphId1 = crate::Reg; +#[doc = "DMA Peripheral ID 1"] +pub mod periph_id_1; +#[doc = "PERIPH_ID_2 (rw) register accessor: DMA Peripheral ID 2\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periph_id_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_2`] module"] +#[doc(alias = "PERIPH_ID_2")] +pub type PeriphId2 = crate::Reg; +#[doc = "DMA Peripheral ID 2"] +pub mod periph_id_2; +#[doc = "PERIPH_ID_3 (rw) register accessor: DMA Peripheral ID 3\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periph_id_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_3`] module"] +#[doc(alias = "PERIPH_ID_3")] +pub type PeriphId3 = crate::Reg; +#[doc = "DMA Peripheral ID 3"] +pub mod periph_id_3; +#[doc = "PRIMECELL_ID_0 (rw) register accessor: DMA PrimeCell ID 0\n\nYou can [`read`](crate::Reg::read) this register and get [`primecell_id_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`primecell_id_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@primecell_id_0`] module"] +#[doc(alias = "PRIMECELL_ID_0")] +pub type PrimecellId0 = crate::Reg; +#[doc = "DMA PrimeCell ID 0"] +pub mod primecell_id_0; +#[doc = "PRIMECELL_ID_1 (rw) register accessor: DMA PrimeCell ID 1\n\nYou can [`read`](crate::Reg::read) this register and get [`primecell_id_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`primecell_id_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@primecell_id_1`] module"] +#[doc(alias = "PRIMECELL_ID_1")] +pub type PrimecellId1 = crate::Reg; +#[doc = "DMA PrimeCell ID 1"] +pub mod primecell_id_1; +#[doc = "PRIMECELL_ID_2 (rw) register accessor: DMA PrimeCell ID 2\n\nYou can [`read`](crate::Reg::read) this register and get [`primecell_id_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`primecell_id_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@primecell_id_2`] module"] +#[doc(alias = "PRIMECELL_ID_2")] +pub type PrimecellId2 = crate::Reg; +#[doc = "DMA PrimeCell ID 2"] +pub mod primecell_id_2; +#[doc = "PRIMECELL_ID_3 (rw) register accessor: DMA PrimeCell ID 3\n\nYou can [`read`](crate::Reg::read) this register and get [`primecell_id_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`primecell_id_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@primecell_id_3`] module"] +#[doc(alias = "PRIMECELL_ID_3")] +pub type PrimecellId3 = crate::Reg; +#[doc = "DMA PrimeCell ID 3"] +pub mod primecell_id_3; diff --git a/va416xx/va416xx/src/dma/alt_ctrl_base_ptr.rs b/va416xx/va416xx/src/dma/alt_ctrl_base_ptr.rs new file mode 100644 index 0000000..f69d181 --- /dev/null +++ b/va416xx/va416xx/src/dma/alt_ctrl_base_ptr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ALT_CTRL_BASE_PTR` reader"] +pub type R = crate::R; +#[doc = "Register `ALT_CTRL_BASE_PTR` writer"] +pub type W = crate::W; +#[doc = "Field `ALT_CTRL_BASE_PTR` reader - Base Pointer for Alternate DMA Control Register"] +pub type AltCtrlBasePtrR = crate::FieldReader; +#[doc = "Field `ALT_CTRL_BASE_PTR` writer - Base Pointer for Alternate DMA Control Register"] +pub type AltCtrlBasePtrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Base Pointer for Alternate DMA Control Register"] + #[inline(always)] + pub fn alt_ctrl_base_ptr(&self) -> AltCtrlBasePtrR { + AltCtrlBasePtrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Base Pointer for Alternate DMA Control Register"] + #[inline(always)] + pub fn alt_ctrl_base_ptr(&mut self) -> AltCtrlBasePtrW<'_, AltCtrlBasePtrSpec> { + AltCtrlBasePtrW::new(self, 0) + } +} +#[doc = "DMA Channel alternate control data base pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`alt_ctrl_base_ptr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alt_ctrl_base_ptr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AltCtrlBasePtrSpec; +impl crate::RegisterSpec for AltCtrlBasePtrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`alt_ctrl_base_ptr::R`](R) reader structure"] +impl crate::Readable for AltCtrlBasePtrSpec {} +#[doc = "`write(|w| ..)` method takes [`alt_ctrl_base_ptr::W`](W) writer structure"] +impl crate::Writable for AltCtrlBasePtrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ALT_CTRL_BASE_PTR to value 0"] +impl crate::Resettable for AltCtrlBasePtrSpec {} diff --git a/va416xx/va416xx/src/dma/cfg.rs b/va416xx/va416xx/src/dma/cfg.rs new file mode 100644 index 0000000..df9c3f8 --- /dev/null +++ b/va416xx/va416xx/src/dma/cfg.rs @@ -0,0 +1,29 @@ +#[doc = "Register `CFG` writer"] +pub type W = crate::W; +#[doc = "Field `MASTER_ENABLE` writer - PLL Symbol; Feedback cycle slip output (CLKOUT frequency low)"] +pub type MasterEnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHNL_PROT_CTRL` writer - HPROT\\[3:0\\]"] +pub type ChnlProtCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl W { + #[doc = "Bit 0 - PLL Symbol; Feedback cycle slip output (CLKOUT frequency low)"] + #[inline(always)] + pub fn master_enable(&mut self) -> MasterEnableW<'_, CfgSpec> { + MasterEnableW::new(self, 0) + } + #[doc = "Bits 5:7 - HPROT\\[3:0\\]"] + #[inline(always)] + pub fn chnl_prot_ctrl(&mut self) -> ChnlProtCtrlW<'_, CfgSpec> { + ChnlProtCtrlW::new(self, 5) + } +} +#[doc = "DMA Configuration\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CfgSpec; +impl crate::RegisterSpec for CfgSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] +impl crate::Writable for CfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CFG to value 0"] +impl crate::Resettable for CfgSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_enable_clr.rs b/va416xx/va416xx/src/dma/chnl_enable_clr.rs new file mode 100644 index 0000000..649e884 --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_enable_clr.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CHNL_ENABLE_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_ENABLE_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel Enable clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel Enable clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel Enable clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel Enable clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel Enable clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel Enable clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel Enable clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel Enable clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel Enable clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Enable clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Enable clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel Enable clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Enable clear"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlEnableClrSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel Enable clear"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlEnableClrSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel Enable clear"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlEnableClrSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel Enable clear"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlEnableClrSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel enable clear\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_enable_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_enable_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlEnableClrSpec; +impl crate::RegisterSpec for ChnlEnableClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_enable_clr::R`](R) reader structure"] +impl crate::Readable for ChnlEnableClrSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_enable_clr::W`](W) writer structure"] +impl crate::Writable for ChnlEnableClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_ENABLE_CLR to value 0"] +impl crate::Resettable for ChnlEnableClrSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_enable_set.rs b/va416xx/va416xx/src/dma/chnl_enable_set.rs new file mode 100644 index 0000000..b3f2038 --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_enable_set.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CHNL_ENABLE_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_ENABLE_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel Enable set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel Enable set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel Enable set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel Enable set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel Enable set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel Enable set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel Enable set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel Enable set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel Enable set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Enable set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Enable set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel Enable set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Enable set"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlEnableSetSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel Enable set"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlEnableSetSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel Enable set"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlEnableSetSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel Enable set"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlEnableSetSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel enable set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_enable_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_enable_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlEnableSetSpec; +impl crate::RegisterSpec for ChnlEnableSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_enable_set::R`](R) reader structure"] +impl crate::Readable for ChnlEnableSetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_enable_set::W`](W) writer structure"] +impl crate::Writable for ChnlEnableSetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_ENABLE_SET to value 0"] +impl crate::Resettable for ChnlEnableSetSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_pri_alt_clr.rs b/va416xx/va416xx/src/dma/chnl_pri_alt_clr.rs new file mode 100644 index 0000000..0926fd6 --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_pri_alt_clr.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CHNL_PRI_ALT_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_PRI_ALT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel PRI_ALT clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel PRI_ALT clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel PRI_ALT clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel PRI_ALT clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel PRI_ALT clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel PRI_ALT clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel PRI_ALT clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel PRI_ALT clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlPriAltClrSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlPriAltClrSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlPriAltClrSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlPriAltClrSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel primary alternate clear\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_pri_alt_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_pri_alt_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlPriAltClrSpec; +impl crate::RegisterSpec for ChnlPriAltClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_pri_alt_clr::R`](R) reader structure"] +impl crate::Readable for ChnlPriAltClrSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_pri_alt_clr::W`](W) writer structure"] +impl crate::Writable for ChnlPriAltClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_PRI_ALT_CLR to value 0"] +impl crate::Resettable for ChnlPriAltClrSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_pri_alt_set.rs b/va416xx/va416xx/src/dma/chnl_pri_alt_set.rs new file mode 100644 index 0000000..fa9592c --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_pri_alt_set.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CHNL_PRI_ALT_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_PRI_ALT_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel PRI_ALT set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel PRI_ALT set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel PRI_ALT set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel PRI_ALT set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel PRI_ALT set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel PRI_ALT set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel PRI_ALT set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel PRI_ALT set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlPriAltSetSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlPriAltSetSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlPriAltSetSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlPriAltSetSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel primary alternate set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_pri_alt_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_pri_alt_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlPriAltSetSpec; +impl crate::RegisterSpec for ChnlPriAltSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_pri_alt_set::R`](R) reader structure"] +impl crate::Readable for ChnlPriAltSetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_pri_alt_set::W`](W) writer structure"] +impl crate::Writable for ChnlPriAltSetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_PRI_ALT_SET to value 0"] +impl crate::Resettable for ChnlPriAltSetSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_priority_clr.rs b/va416xx/va416xx/src/dma/chnl_priority_clr.rs new file mode 100644 index 0000000..3e38c4f --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_priority_clr.rs @@ -0,0 +1,43 @@ +#[doc = "Register `CHNL_PRIORITY_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` writer - Channel PRIORITY clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` writer - Channel PRIORITY clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` writer - Channel PRIORITY clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` writer - Channel PRIORITY clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Channel PRIORITY clear"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlPriorityClrSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel PRIORITY clear"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlPriorityClrSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel PRIORITY clear"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlPriorityClrSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel PRIORITY clear"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlPriorityClrSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel priority clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_priority_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlPriorityClrSpec; +impl crate::RegisterSpec for ChnlPriorityClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`chnl_priority_clr::W`](W) writer structure"] +impl crate::Writable for ChnlPriorityClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_PRIORITY_CLR to value 0"] +impl crate::Resettable for ChnlPriorityClrSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_priority_set.rs b/va416xx/va416xx/src/dma/chnl_priority_set.rs new file mode 100644 index 0000000..a21f390 --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_priority_set.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CHNL_PRIORITY_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_PRIORITY_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel PRIORITY set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel PRIORITY set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel PRIORITY set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel PRIORITY set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel PRIORITY set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel PRIORITY set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel PRIORITY set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel PRIORITY set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlPrioritySetSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlPrioritySetSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlPrioritySetSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlPrioritySetSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel priority set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_priority_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_priority_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlPrioritySetSpec; +impl crate::RegisterSpec for ChnlPrioritySetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_priority_set::R`](R) reader structure"] +impl crate::Readable for ChnlPrioritySetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_priority_set::W`](W) writer structure"] +impl crate::Writable for ChnlPrioritySetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_PRIORITY_SET to value 0"] +impl crate::Resettable for ChnlPrioritySetSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_req_mask_clr.rs b/va416xx/va416xx/src/dma/chnl_req_mask_clr.rs new file mode 100644 index 0000000..95e5b9d --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_req_mask_clr.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CHNL_REQ_MASK_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_REQ_MASK_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel Request Mask clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel Request Mask clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel Request Mask clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel Request Mask clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel Request Mask clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel Request Mask clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel Request Mask clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel Request Mask clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlReqMaskClrSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlReqMaskClrSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlReqMaskClrSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlReqMaskClrSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel request mask clear\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_req_mask_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_req_mask_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlReqMaskClrSpec; +impl crate::RegisterSpec for ChnlReqMaskClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_req_mask_clr::R`](R) reader structure"] +impl crate::Readable for ChnlReqMaskClrSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_req_mask_clr::W`](W) writer structure"] +impl crate::Writable for ChnlReqMaskClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_REQ_MASK_CLR to value 0"] +impl crate::Resettable for ChnlReqMaskClrSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_req_mask_set.rs b/va416xx/va416xx/src/dma/chnl_req_mask_set.rs new file mode 100644 index 0000000..652486b --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_req_mask_set.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CHNL_REQ_MASK_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_REQ_MASK_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel Request Mask set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel Request Mask set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel Request Mask set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel Request Mask set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel Request Mask set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel Request Mask set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel Request Mask set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel Request Mask set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel Request Mask set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Request Mask set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Request Mask set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel Request Mask set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Request Mask set"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlReqMaskSetSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel Request Mask set"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlReqMaskSetSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel Request Mask set"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlReqMaskSetSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel Request Mask set"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlReqMaskSetSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel request mask set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_req_mask_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_req_mask_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlReqMaskSetSpec; +impl crate::RegisterSpec for ChnlReqMaskSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_req_mask_set::R`](R) reader structure"] +impl crate::Readable for ChnlReqMaskSetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_req_mask_set::W`](W) writer structure"] +impl crate::Writable for ChnlReqMaskSetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_REQ_MASK_SET to value 0"] +impl crate::Resettable for ChnlReqMaskSetSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_sw_request.rs b/va416xx/va416xx/src/dma/chnl_sw_request.rs new file mode 100644 index 0000000..f51eed3 --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_sw_request.rs @@ -0,0 +1,43 @@ +#[doc = "Register `CHNL_SW_REQUEST` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` writer - Channel SW request"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` writer - Channel SW request"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` writer - Channel SW request"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` writer - Channel SW request"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Channel SW request"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlSwRequestSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel SW request"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlSwRequestSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel SW request"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlSwRequestSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel SW request"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlSwRequestSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel software request\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_sw_request::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlSwRequestSpec; +impl crate::RegisterSpec for ChnlSwRequestSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`chnl_sw_request::W`](W) writer structure"] +impl crate::Writable for ChnlSwRequestSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_SW_REQUEST to value 0"] +impl crate::Resettable for ChnlSwRequestSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_useburst_clr.rs b/va416xx/va416xx/src/dma/chnl_useburst_clr.rs new file mode 100644 index 0000000..a8bbd20 --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_useburst_clr.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CHNL_USEBURST_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_USEBURST_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel use burst clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel use burst clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel use burst clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel use burst clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel use burst clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel use burst clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel use burst clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel use burst clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel use burst clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel use burst clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel use burst clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel use burst clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel use burst clear"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlUseburstClrSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel use burst clear"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlUseburstClrSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel use burst clear"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlUseburstClrSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel use burst clear"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlUseburstClrSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel useburst clear\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_useburst_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_useburst_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlUseburstClrSpec; +impl crate::RegisterSpec for ChnlUseburstClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_useburst_clr::R`](R) reader structure"] +impl crate::Readable for ChnlUseburstClrSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_useburst_clr::W`](W) writer structure"] +impl crate::Writable for ChnlUseburstClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_USEBURST_CLR to value 0"] +impl crate::Resettable for ChnlUseburstClrSpec {} diff --git a/va416xx/va416xx/src/dma/chnl_useburst_set.rs b/va416xx/va416xx/src/dma/chnl_useburst_set.rs new file mode 100644 index 0000000..e4cc8d7 --- /dev/null +++ b/va416xx/va416xx/src/dma/chnl_useburst_set.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CHNL_USEBURST_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_USEBURST_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel use burst set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel use burst set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel use burst set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel use burst set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel use burst set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel use burst set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel use burst set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel use burst set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel use burst set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel use burst set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel use burst set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel use burst set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel use burst set"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, ChnlUseburstSetSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel use burst set"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, ChnlUseburstSetSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel use burst set"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, ChnlUseburstSetSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel use burst set"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, ChnlUseburstSetSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel useburst set\n\nYou can [`read`](crate::Reg::read) this register and get [`chnl_useburst_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chnl_useburst_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlUseburstSetSpec; +impl crate::RegisterSpec for ChnlUseburstSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_useburst_set::R`](R) reader structure"] +impl crate::Readable for ChnlUseburstSetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_useburst_set::W`](W) writer structure"] +impl crate::Writable for ChnlUseburstSetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CHNL_USEBURST_SET to value 0"] +impl crate::Resettable for ChnlUseburstSetSpec {} diff --git a/va416xx/va416xx/src/dma/ctrl_base_ptr.rs b/va416xx/va416xx/src/dma/ctrl_base_ptr.rs new file mode 100644 index 0000000..11fa9bf --- /dev/null +++ b/va416xx/va416xx/src/dma/ctrl_base_ptr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CTRL_BASE_PTR` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL_BASE_PTR` writer"] +pub type W = crate::W; +#[doc = "Field `CTRL_BASE_PTR` reader - Base Pointer for DMA Control Registers"] +pub type CtrlBasePtrR = crate::FieldReader; +#[doc = "Field `CTRL_BASE_PTR` writer - Base Pointer for DMA Control Registers"] +pub type CtrlBasePtrW<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bits 7:31 - Base Pointer for DMA Control Registers"] + #[inline(always)] + pub fn ctrl_base_ptr(&self) -> CtrlBasePtrR { + CtrlBasePtrR::new((self.bits >> 7) & 0x01ff_ffff) + } +} +impl W { + #[doc = "Bits 7:31 - Base Pointer for DMA Control Registers"] + #[inline(always)] + pub fn ctrl_base_ptr(&mut self) -> CtrlBasePtrW<'_, CtrlBasePtrSpec> { + CtrlBasePtrW::new(self, 7) + } +} +#[doc = "Base Pointer for DMA Control Registers\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_base_ptr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_base_ptr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlBasePtrSpec; +impl crate::RegisterSpec for CtrlBasePtrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl_base_ptr::R`](R) reader structure"] +impl crate::Readable for CtrlBasePtrSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl_base_ptr::W`](W) writer structure"] +impl crate::Writable for CtrlBasePtrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL_BASE_PTR to value 0"] +impl crate::Resettable for CtrlBasePtrSpec {} diff --git a/va416xx/va416xx/src/dma/dma_active_clr.rs b/va416xx/va416xx/src/dma/dma_active_clr.rs new file mode 100644 index 0000000..e146eb5 --- /dev/null +++ b/va416xx/va416xx/src/dma/dma_active_clr.rs @@ -0,0 +1,77 @@ +#[doc = "Register `DMA_ACTIVE_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_ACTIVE_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Active clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Active clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Active clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Active clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Active clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Active clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Active clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Active clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Active clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Active clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Active clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Active clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Active clear"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, DmaActiveClrSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Active clear"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, DmaActiveClrSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Active clear"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, DmaActiveClrSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Active clear"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, DmaActiveClrSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA active clear\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_active_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_active_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaActiveClrSpec; +impl crate::RegisterSpec for DmaActiveClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_active_clr::R`](R) reader structure"] +impl crate::Readable for DmaActiveClrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_active_clr::W`](W) writer structure"] +impl crate::Writable for DmaActiveClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_ACTIVE_CLR to value 0"] +impl crate::Resettable for DmaActiveClrSpec {} diff --git a/va416xx/va416xx/src/dma/dma_active_set.rs b/va416xx/va416xx/src/dma/dma_active_set.rs new file mode 100644 index 0000000..457a201 --- /dev/null +++ b/va416xx/va416xx/src/dma/dma_active_set.rs @@ -0,0 +1,77 @@ +#[doc = "Register `DMA_ACTIVE_SET` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_ACTIVE_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Active Set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Active Set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Active Set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Active Set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Active Set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Active Set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Active Set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Active Set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Active Set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Active Set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Active Set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Active Set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Active Set"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, DmaActiveSetSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Active Set"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, DmaActiveSetSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Active Set"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, DmaActiveSetSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Active Set"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, DmaActiveSetSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA active set\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_active_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_active_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaActiveSetSpec; +impl crate::RegisterSpec for DmaActiveSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_active_set::R`](R) reader structure"] +impl crate::Readable for DmaActiveSetSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_active_set::W`](W) writer structure"] +impl crate::Writable for DmaActiveSetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_ACTIVE_SET to value 0"] +impl crate::Resettable for DmaActiveSetSpec {} diff --git a/va416xx/va416xx/src/dma/dma_done_clr.rs b/va416xx/va416xx/src/dma/dma_done_clr.rs new file mode 100644 index 0000000..b6ed4e6 --- /dev/null +++ b/va416xx/va416xx/src/dma/dma_done_clr.rs @@ -0,0 +1,77 @@ +#[doc = "Register `DMA_DONE_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_DONE_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Done clear for this CH"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Done clear for this CH"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Done clear for this CH"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Done clear for this CH"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Done clear for this CH"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Done clear for this CH"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Done clear for this CH"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Done clear for this CH"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, DmaDoneClrSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, DmaDoneClrSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, DmaDoneClrSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, DmaDoneClrSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA done clear\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_done_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_done_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaDoneClrSpec; +impl crate::RegisterSpec for DmaDoneClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_done_clr::R`](R) reader structure"] +impl crate::Readable for DmaDoneClrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_done_clr::W`](W) writer structure"] +impl crate::Writable for DmaDoneClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_DONE_CLR to value 0"] +impl crate::Resettable for DmaDoneClrSpec {} diff --git a/va416xx/va416xx/src/dma/dma_done_set.rs b/va416xx/va416xx/src/dma/dma_done_set.rs new file mode 100644 index 0000000..0f6b441 --- /dev/null +++ b/va416xx/va416xx/src/dma/dma_done_set.rs @@ -0,0 +1,77 @@ +#[doc = "Register `DMA_DONE_SET` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_DONE_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Done Set for this CH"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Done Set for this CH"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Done Set for this CH"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Done Set for this CH"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Done Set for this CH"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Done Set for this CH"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Done Set for this CH"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Done Set for this CH"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, DmaDoneSetSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, DmaDoneSetSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, DmaDoneSetSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, DmaDoneSetSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA done set\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_done_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_done_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaDoneSetSpec; +impl crate::RegisterSpec for DmaDoneSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_done_set::R`](R) reader structure"] +impl crate::Readable for DmaDoneSetSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_done_set::W`](W) writer structure"] +impl crate::Writable for DmaDoneSetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_DONE_SET to value 0"] +impl crate::Resettable for DmaDoneSetSpec {} diff --git a/va416xx/va416xx/src/dma/dma_req_status.rs b/va416xx/va416xx/src/dma/dma_req_status.rs new file mode 100644 index 0000000..d545196 --- /dev/null +++ b/va416xx/va416xx/src/dma/dma_req_status.rs @@ -0,0 +1,77 @@ +#[doc = "Register `DMA_REQ_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_REQ_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Request Status for this CH"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Request Status for this CH"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Request Status for this CH"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Request Status for this CH"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Request Status for this CH"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Request Status for this CH"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Request Status for this CH"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Request Status for this CH"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, DmaReqStatusSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, DmaReqStatusSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, DmaReqStatusSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, DmaReqStatusSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_req_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_req_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaReqStatusSpec; +impl crate::RegisterSpec for DmaReqStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_req_status::R`](R) reader structure"] +impl crate::Readable for DmaReqStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_req_status::W`](W) writer structure"] +impl crate::Writable for DmaReqStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_REQ_STATUS to value 0"] +impl crate::Resettable for DmaReqStatusSpec {} diff --git a/va416xx/va416xx/src/dma/dma_sreq_status.rs b/va416xx/va416xx/src/dma/dma_sreq_status.rs new file mode 100644 index 0000000..b09c9a5 --- /dev/null +++ b/va416xx/va416xx/src/dma/dma_sreq_status.rs @@ -0,0 +1,77 @@ +#[doc = "Register `DMA_SREQ_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_SREQ_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA SRequest Status for this CH"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA SRequest Status for this CH"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA SRequest Status for this CH"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA SRequest Status for this CH"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA SRequest Status for this CH"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA SRequest Status for this CH"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA SRequest Status for this CH"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA SRequest Status for this CH"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch0(&mut self) -> Ch0W<'_, DmaSreqStatusSpec> { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch1(&mut self) -> Ch1W<'_, DmaSreqStatusSpec> { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch2(&mut self) -> Ch2W<'_, DmaSreqStatusSpec> { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch3(&mut self) -> Ch3W<'_, DmaSreqStatusSpec> { + Ch3W::new(self, 3) + } +} +#[doc = "DMA single request status\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_sreq_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_sreq_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaSreqStatusSpec; +impl crate::RegisterSpec for DmaSreqStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_sreq_status::R`](R) reader structure"] +impl crate::Readable for DmaSreqStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_sreq_status::W`](W) writer structure"] +impl crate::Writable for DmaSreqStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_SREQ_STATUS to value 0"] +impl crate::Resettable for DmaSreqStatusSpec {} diff --git a/va416xx/va416xx/src/dma/err_clr.rs b/va416xx/va416xx/src/dma/err_clr.rs new file mode 100644 index 0000000..f715363 --- /dev/null +++ b/va416xx/va416xx/src/dma/err_clr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ERR_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `ERR_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `ERR_CLR` reader - Error Clear"] +pub type ErrClrR = crate::BitReader; +#[doc = "Field `ERR_CLR` writer - Error Clear"] +pub type ErrClrW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn err_clr(&self) -> ErrClrR { + ErrClrR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn err_clr(&mut self) -> ErrClrW<'_, ErrClrSpec> { + ErrClrW::new(self, 0) + } +} +#[doc = "DMA bus error clear\n\nYou can [`read`](crate::Reg::read) this register and get [`err_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErrClrSpec; +impl crate::RegisterSpec for ErrClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`err_clr::R`](R) reader structure"] +impl crate::Readable for ErrClrSpec {} +#[doc = "`write(|w| ..)` method takes [`err_clr::W`](W) writer structure"] +impl crate::Writable for ErrClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ERR_CLR to value 0"] +impl crate::Resettable for ErrClrSpec {} diff --git a/va416xx/va416xx/src/dma/err_set.rs b/va416xx/va416xx/src/dma/err_set.rs new file mode 100644 index 0000000..e8cd604 --- /dev/null +++ b/va416xx/va416xx/src/dma/err_set.rs @@ -0,0 +1,27 @@ +#[doc = "Register `ERR_SET` reader"] +pub type R = crate::R; +#[doc = "Register `ERR_SET` writer"] +pub type W = crate::W; +#[doc = "Field `ERR_SET` reader - Set Error"] +pub type ErrSetR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Set Error"] + #[inline(always)] + pub fn err_set(&self) -> ErrSetR { + ErrSetR::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "DMA bus error set\n\nYou can [`read`](crate::Reg::read) this register and get [`err_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`err_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErrSetSpec; +impl crate::RegisterSpec for ErrSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`err_set::R`](R) reader structure"] +impl crate::Readable for ErrSetSpec {} +#[doc = "`write(|w| ..)` method takes [`err_set::W`](W) writer structure"] +impl crate::Writable for ErrSetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ERR_SET to value 0"] +impl crate::Resettable for ErrSetSpec {} diff --git a/va416xx/va416xx/src/dma/integration_cfg.rs b/va416xx/va416xx/src/dma/integration_cfg.rs new file mode 100644 index 0000000..93b1c1d --- /dev/null +++ b/va416xx/va416xx/src/dma/integration_cfg.rs @@ -0,0 +1,35 @@ +#[doc = "Register `INTEGRATION_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `INTEGRATION_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `INT_TEST_EN` reader - Error Clear"] +pub type IntTestEnR = crate::BitReader; +#[doc = "Field `INT_TEST_EN` writer - Error Clear"] +pub type IntTestEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn int_test_en(&self) -> IntTestEnR { + IntTestEnR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn int_test_en(&mut self) -> IntTestEnW<'_, IntegrationCfgSpec> { + IntTestEnW::new(self, 0) + } +} +#[doc = "DMA integration configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`integration_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`integration_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntegrationCfgSpec; +impl crate::RegisterSpec for IntegrationCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`integration_cfg::R`](R) reader structure"] +impl crate::Readable for IntegrationCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`integration_cfg::W`](W) writer structure"] +impl crate::Writable for IntegrationCfgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets INTEGRATION_CFG to value 0"] +impl crate::Resettable for IntegrationCfgSpec {} diff --git a/va416xx/va416xx/src/dma/periph_id_0.rs b/va416xx/va416xx/src/dma/periph_id_0.rs new file mode 100644 index 0000000..b1cbcd5 --- /dev/null +++ b/va416xx/va416xx/src/dma/periph_id_0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PERIPH_ID_0` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPH_ID_0` writer"] +pub type W = crate::W; +#[doc = "Field `PART_NUMBER_0` reader - Part Number"] +pub type PartNumber0R = crate::FieldReader; +#[doc = "Field `PART_NUMBER_0` writer - Part Number"] +pub type PartNumber0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Part Number"] + #[inline(always)] + pub fn part_number_0(&self) -> PartNumber0R { + PartNumber0R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Part Number"] + #[inline(always)] + pub fn part_number_0(&mut self) -> PartNumber0W<'_, PeriphId0Spec> { + PartNumber0W::new(self, 0) + } +} +#[doc = "DMA Peripheral ID 0\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periph_id_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId0Spec; +impl crate::RegisterSpec for PeriphId0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_0::R`](R) reader structure"] +impl crate::Readable for PeriphId0Spec {} +#[doc = "`write(|w| ..)` method takes [`periph_id_0::W`](W) writer structure"] +impl crate::Writable for PeriphId0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PERIPH_ID_0 to value 0x30"] +impl crate::Resettable for PeriphId0Spec { + const RESET_VALUE: u32 = 0x30; +} diff --git a/va416xx/va416xx/src/dma/periph_id_1.rs b/va416xx/va416xx/src/dma/periph_id_1.rs new file mode 100644 index 0000000..b033fdc --- /dev/null +++ b/va416xx/va416xx/src/dma/periph_id_1.rs @@ -0,0 +1,29 @@ +#[doc = "Register `PERIPH_ID_1` reader"] +pub type R = crate::R; +#[doc = "Field `PART_NUMBER_1` reader - Part Number 1"] +pub type PartNumber1R = crate::FieldReader; +#[doc = "Field `JEP106_ID_3_0` reader - Indentity Code"] +pub type Jep106Id3_0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Part Number 1"] + #[inline(always)] + pub fn part_number_1(&self) -> PartNumber1R { + PartNumber1R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indentity Code"] + #[inline(always)] + pub fn jep106_id_3_0(&self) -> Jep106Id3_0R { + Jep106Id3_0R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "DMA Peripheral ID 1\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId1Spec; +impl crate::RegisterSpec for PeriphId1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_1::R`](R) reader structure"] +impl crate::Readable for PeriphId1Spec {} +#[doc = "`reset()` method sets PERIPH_ID_1 to value 0xb2"] +impl crate::Resettable for PeriphId1Spec { + const RESET_VALUE: u32 = 0xb2; +} diff --git a/va416xx/va416xx/src/dma/periph_id_2.rs b/va416xx/va416xx/src/dma/periph_id_2.rs new file mode 100644 index 0000000..19692d1 --- /dev/null +++ b/va416xx/va416xx/src/dma/periph_id_2.rs @@ -0,0 +1,65 @@ +#[doc = "Register `PERIPH_ID_2` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPH_ID_2` writer"] +pub type W = crate::W; +#[doc = "Field `JEP106_ID_6_4` reader - JEP106"] +pub type Jep106Id6_4R = crate::FieldReader; +#[doc = "Field `JEP106_ID_6_4` writer - JEP106"] +pub type Jep106Id6_4W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `JEDEC_USED` reader - JEDEC"] +pub type JedecUsedR = crate::BitReader; +#[doc = "Field `JEDEC_USED` writer - JEDEC"] +pub type JedecUsedW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REVISION` reader - Revision"] +pub type RevisionR = crate::FieldReader; +#[doc = "Field `REVISION` writer - Revision"] +pub type RevisionW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:2 - JEP106"] + #[inline(always)] + pub fn jep106_id_6_4(&self) -> Jep106Id6_4R { + Jep106Id6_4R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - JEDEC"] + #[inline(always)] + pub fn jedec_used(&self) -> JedecUsedR { + JedecUsedR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - Revision"] + #[inline(always)] + pub fn revision(&self) -> RevisionR { + RevisionR::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - JEP106"] + #[inline(always)] + pub fn jep106_id_6_4(&mut self) -> Jep106Id6_4W<'_, PeriphId2Spec> { + Jep106Id6_4W::new(self, 0) + } + #[doc = "Bit 3 - JEDEC"] + #[inline(always)] + pub fn jedec_used(&mut self) -> JedecUsedW<'_, PeriphId2Spec> { + JedecUsedW::new(self, 3) + } + #[doc = "Bits 4:7 - Revision"] + #[inline(always)] + pub fn revision(&mut self) -> RevisionW<'_, PeriphId2Spec> { + RevisionW::new(self, 4) + } +} +#[doc = "DMA Peripheral ID 2\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periph_id_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId2Spec; +impl crate::RegisterSpec for PeriphId2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_2::R`](R) reader structure"] +impl crate::Readable for PeriphId2Spec {} +#[doc = "`write(|w| ..)` method takes [`periph_id_2::W`](W) writer structure"] +impl crate::Writable for PeriphId2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PERIPH_ID_2 to value 0xbc"] +impl crate::Resettable for PeriphId2Spec { + const RESET_VALUE: u32 = 0xbc; +} diff --git a/va416xx/va416xx/src/dma/periph_id_3.rs b/va416xx/va416xx/src/dma/periph_id_3.rs new file mode 100644 index 0000000..b458ec5 --- /dev/null +++ b/va416xx/va416xx/src/dma/periph_id_3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PERIPH_ID_3` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPH_ID_3` writer"] +pub type W = crate::W; +#[doc = "Field `MOD_NUMBER` reader - Controller Modifications"] +pub type ModNumberR = crate::FieldReader; +#[doc = "Field `MOD_NUMBER` writer - Controller Modifications"] +pub type ModNumberW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Controller Modifications"] + #[inline(always)] + pub fn mod_number(&self) -> ModNumberR { + ModNumberR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Controller Modifications"] + #[inline(always)] + pub fn mod_number(&mut self) -> ModNumberW<'_, PeriphId3Spec> { + ModNumberW::new(self, 0) + } +} +#[doc = "DMA Peripheral ID 3\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periph_id_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId3Spec; +impl crate::RegisterSpec for PeriphId3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_3::R`](R) reader structure"] +impl crate::Readable for PeriphId3Spec {} +#[doc = "`write(|w| ..)` method takes [`periph_id_3::W`](W) writer structure"] +impl crate::Writable for PeriphId3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PERIPH_ID_3 to value 0"] +impl crate::Resettable for PeriphId3Spec {} diff --git a/va416xx/va416xx/src/dma/periph_id_4.rs b/va416xx/va416xx/src/dma/periph_id_4.rs new file mode 100644 index 0000000..88e4810 --- /dev/null +++ b/va416xx/va416xx/src/dma/periph_id_4.rs @@ -0,0 +1,51 @@ +#[doc = "Register `PERIPH_ID_4` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPH_ID_4` writer"] +pub type W = crate::W; +#[doc = "Field `JEP106_C_CODE` reader - JEP106"] +pub type Jep106CCodeR = crate::FieldReader; +#[doc = "Field `JEP106_C_CODE` writer - JEP106"] +pub type Jep106CCodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `BLOCK_COUNT` reader - The Number of 4k Address Blocks Required"] +pub type BlockCountR = crate::FieldReader; +#[doc = "Field `BLOCK_COUNT` writer - The Number of 4k Address Blocks Required"] +pub type BlockCountW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - JEP106"] + #[inline(always)] + pub fn jep106_c_code(&self) -> Jep106CCodeR { + Jep106CCodeR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - The Number of 4k Address Blocks Required"] + #[inline(always)] + pub fn block_count(&self) -> BlockCountR { + BlockCountR::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - JEP106"] + #[inline(always)] + pub fn jep106_c_code(&mut self) -> Jep106CCodeW<'_, PeriphId4Spec> { + Jep106CCodeW::new(self, 0) + } + #[doc = "Bits 4:7 - The Number of 4k Address Blocks Required"] + #[inline(always)] + pub fn block_count(&mut self) -> BlockCountW<'_, PeriphId4Spec> { + BlockCountW::new(self, 4) + } +} +#[doc = "DMA Peripheral ID 4\n\nYou can [`read`](crate::Reg::read) this register and get [`periph_id_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periph_id_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId4Spec; +impl crate::RegisterSpec for PeriphId4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_4::R`](R) reader structure"] +impl crate::Readable for PeriphId4Spec {} +#[doc = "`write(|w| ..)` method takes [`periph_id_4::W`](W) writer structure"] +impl crate::Writable for PeriphId4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PERIPH_ID_4 to value 0x04"] +impl crate::Resettable for PeriphId4Spec { + const RESET_VALUE: u32 = 0x04; +} diff --git a/va416xx/va416xx/src/dma/primecell_id_0.rs b/va416xx/va416xx/src/dma/primecell_id_0.rs new file mode 100644 index 0000000..31a57d4 --- /dev/null +++ b/va416xx/va416xx/src/dma/primecell_id_0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PRIMECELL_ID_0` reader"] +pub type R = crate::R; +#[doc = "Register `PRIMECELL_ID_0` writer"] +pub type W = crate::W; +#[doc = "Field `PRIMECELL_ID_0` reader - PrimeCell Identification"] +pub type PrimecellId0R = crate::FieldReader; +#[doc = "Field `PRIMECELL_ID_0` writer - PrimeCell Identification"] +pub type PrimecellId0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_0(&self) -> PrimecellId0R { + PrimecellId0R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_0(&mut self) -> PrimecellId0W<'_, PrimecellId0Spec> { + PrimecellId0W::new(self, 0) + } +} +#[doc = "DMA PrimeCell ID 0\n\nYou can [`read`](crate::Reg::read) this register and get [`primecell_id_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`primecell_id_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrimecellId0Spec; +impl crate::RegisterSpec for PrimecellId0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`primecell_id_0::R`](R) reader structure"] +impl crate::Readable for PrimecellId0Spec {} +#[doc = "`write(|w| ..)` method takes [`primecell_id_0::W`](W) writer structure"] +impl crate::Writable for PrimecellId0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PRIMECELL_ID_0 to value 0x0d"] +impl crate::Resettable for PrimecellId0Spec { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/va416xx/va416xx/src/dma/primecell_id_1.rs b/va416xx/va416xx/src/dma/primecell_id_1.rs new file mode 100644 index 0000000..87dc891 --- /dev/null +++ b/va416xx/va416xx/src/dma/primecell_id_1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PRIMECELL_ID_1` reader"] +pub type R = crate::R; +#[doc = "Register `PRIMECELL_ID_1` writer"] +pub type W = crate::W; +#[doc = "Field `PRIMECELL_ID_1` reader - PrimeCell Identification"] +pub type PrimecellId1R = crate::FieldReader; +#[doc = "Field `PRIMECELL_ID_1` writer - PrimeCell Identification"] +pub type PrimecellId1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_1(&self) -> PrimecellId1R { + PrimecellId1R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_1(&mut self) -> PrimecellId1W<'_, PrimecellId1Spec> { + PrimecellId1W::new(self, 0) + } +} +#[doc = "DMA PrimeCell ID 1\n\nYou can [`read`](crate::Reg::read) this register and get [`primecell_id_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`primecell_id_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrimecellId1Spec; +impl crate::RegisterSpec for PrimecellId1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`primecell_id_1::R`](R) reader structure"] +impl crate::Readable for PrimecellId1Spec {} +#[doc = "`write(|w| ..)` method takes [`primecell_id_1::W`](W) writer structure"] +impl crate::Writable for PrimecellId1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PRIMECELL_ID_1 to value 0xf0"] +impl crate::Resettable for PrimecellId1Spec { + const RESET_VALUE: u32 = 0xf0; +} diff --git a/va416xx/va416xx/src/dma/primecell_id_2.rs b/va416xx/va416xx/src/dma/primecell_id_2.rs new file mode 100644 index 0000000..ae0e9b6 --- /dev/null +++ b/va416xx/va416xx/src/dma/primecell_id_2.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PRIMECELL_ID_2` reader"] +pub type R = crate::R; +#[doc = "Register `PRIMECELL_ID_2` writer"] +pub type W = crate::W; +#[doc = "Field `PRIMECELL_ID_2` reader - PrimeCell Identification"] +pub type PrimecellId2R = crate::FieldReader; +#[doc = "Field `PRIMECELL_ID_2` writer - PrimeCell Identification"] +pub type PrimecellId2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_2(&self) -> PrimecellId2R { + PrimecellId2R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_2(&mut self) -> PrimecellId2W<'_, PrimecellId2Spec> { + PrimecellId2W::new(self, 0) + } +} +#[doc = "DMA PrimeCell ID 2\n\nYou can [`read`](crate::Reg::read) this register and get [`primecell_id_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`primecell_id_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrimecellId2Spec; +impl crate::RegisterSpec for PrimecellId2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`primecell_id_2::R`](R) reader structure"] +impl crate::Readable for PrimecellId2Spec {} +#[doc = "`write(|w| ..)` method takes [`primecell_id_2::W`](W) writer structure"] +impl crate::Writable for PrimecellId2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PRIMECELL_ID_2 to value 0x05"] +impl crate::Resettable for PrimecellId2Spec { + const RESET_VALUE: u32 = 0x05; +} diff --git a/va416xx/va416xx/src/dma/primecell_id_3.rs b/va416xx/va416xx/src/dma/primecell_id_3.rs new file mode 100644 index 0000000..4635cc7 --- /dev/null +++ b/va416xx/va416xx/src/dma/primecell_id_3.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PRIMECELL_ID_3` reader"] +pub type R = crate::R; +#[doc = "Register `PRIMECELL_ID_3` writer"] +pub type W = crate::W; +#[doc = "Field `PRIMECELL_ID_3` reader - PrimeCell Identification"] +pub type PrimecellId3R = crate::FieldReader; +#[doc = "Field `PRIMECELL_ID_3` writer - PrimeCell Identification"] +pub type PrimecellId3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_3(&self) -> PrimecellId3R { + PrimecellId3R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_3(&mut self) -> PrimecellId3W<'_, PrimecellId3Spec> { + PrimecellId3W::new(self, 0) + } +} +#[doc = "DMA PrimeCell ID 3\n\nYou can [`read`](crate::Reg::read) this register and get [`primecell_id_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`primecell_id_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrimecellId3Spec; +impl crate::RegisterSpec for PrimecellId3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`primecell_id_3::R`](R) reader structure"] +impl crate::Readable for PrimecellId3Spec {} +#[doc = "`write(|w| ..)` method takes [`primecell_id_3::W`](W) writer structure"] +impl crate::Writable for PrimecellId3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PRIMECELL_ID_3 to value 0xb1"] +impl crate::Resettable for PrimecellId3Spec { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/va416xx/va416xx/src/dma/stall_status.rs b/va416xx/va416xx/src/dma/stall_status.rs new file mode 100644 index 0000000..535f7ed --- /dev/null +++ b/va416xx/va416xx/src/dma/stall_status.rs @@ -0,0 +1,27 @@ +#[doc = "Register `STALL_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `STALL_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `STALL_STATUS` reader - DMA is stalled"] +pub type StallStatusR = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA is stalled"] + #[inline(always)] + pub fn stall_status(&self) -> StallStatusR { + StallStatusR::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "DMA stall status\n\nYou can [`read`](crate::Reg::read) this register and get [`stall_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stall_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StallStatusSpec; +impl crate::RegisterSpec for StallStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stall_status::R`](R) reader structure"] +impl crate::Readable for StallStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`stall_status::W`](W) writer structure"] +impl crate::Writable for StallStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STALL_STATUS to value 0"] +impl crate::Resettable for StallStatusSpec {} diff --git a/va416xx/va416xx/src/dma/status.rs b/va416xx/va416xx/src/dma/status.rs new file mode 100644 index 0000000..3c98c4f --- /dev/null +++ b/va416xx/va416xx/src/dma/status.rs @@ -0,0 +1,41 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `MASTER_ENABLE` reader - Enable status of the controller"] +pub type MasterEnableR = crate::BitReader; +#[doc = "Field `STATE` reader - Current State of the control state machine"] +pub type StateR = crate::FieldReader; +#[doc = "Field `CHNLS_MINUS1` reader - Number of Available Channels Minus 1"] +pub type ChnlsMinus1R = crate::FieldReader; +#[doc = "Field `TEST_STATUS` reader - Test Status Logic Included"] +pub type TestStatusR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Enable status of the controller"] + #[inline(always)] + pub fn master_enable(&self) -> MasterEnableR { + MasterEnableR::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:7 - Current State of the control state machine"] + #[inline(always)] + pub fn state(&self) -> StateR { + StateR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 16:20 - Number of Available Channels Minus 1"] + #[inline(always)] + pub fn chnls_minus1(&self) -> ChnlsMinus1R { + ChnlsMinus1R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Test Status Logic Included"] + #[inline(always)] + pub fn test_status(&self) -> TestStatusR { + TestStatusR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "DMA Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec {} diff --git a/va416xx/va416xx/src/dma/waitonreq_status.rs b/va416xx/va416xx/src/dma/waitonreq_status.rs new file mode 100644 index 0000000..e6aa791 --- /dev/null +++ b/va416xx/va416xx/src/dma/waitonreq_status.rs @@ -0,0 +1,41 @@ +#[doc = "Register `WAITONREQ_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `CH0` reader - DMA wait on request"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH1` reader - DMA wait on request"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH2` reader - DMA wait on request"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH3` reader - DMA wait on request"] +pub type Ch3R = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA wait on request"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA wait on request"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA wait on request"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA wait on request"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "DMA channel wait on request status\n\nYou can [`read`](crate::Reg::read) this register and get [`waitonreq_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WaitonreqStatusSpec; +impl crate::RegisterSpec for WaitonreqStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`waitonreq_status::R`](R) reader structure"] +impl crate::Readable for WaitonreqStatusSpec {} +#[doc = "`reset()` method sets WAITONREQ_STATUS to value 0"] +impl crate::Resettable for WaitonreqStatusSpec {} diff --git a/va416xx/va416xx/src/eth.rs b/va416xx/va416xx/src/eth.rs new file mode 100644 index 0000000..abaeed2 --- /dev/null +++ b/va416xx/va416xx/src/eth.rs @@ -0,0 +1,1062 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + mac_config: MacConfig, + mac_frame_fltr: MacFrameFltr, + _reserved2: [u8; 0x08], + mac_gmii_addr: MacGmiiAddr, + mac_gmii_data: MacGmiiData, + mac_flow_ctrl: MacFlowCtrl, + mac_vlan_tag: MacVlanTag, + _reserved6: [u8; 0x04], + mac_debug: MacDebug, + _reserved7: [u8; 0x10], + mac_intr_stat: MacIntrStat, + mac_intr_mask: MacIntrMask, + mac_addr_h: MacAddrH, + mac_addr_l: MacAddrL, + _reserved11: [u8; 0x94], + mac_wdog_to: MacWdogTo, + _reserved12: [u8; 0x20], + mmc_cntrl: MmcCntrl, + mmc_intr_rx: MmcIntrRx, + mmc_intr_tx: MmcIntrTx, + mmc_intr_mask_rx: MmcIntrMaskRx, + mmc_intr_mask_tx: MmcIntrMaskTx, + txoctetcount_gb: TxoctetcountGb, + txframecount_gb: TxframecountGb, + txbcastframes_g: TxbcastframesG, + txmcastframes_g: TxmcastframesG, + tx64oct_gb: Tx64octGb, + tx65to127oct_gb: Tx65to127octGb, + tx128to255oct_gb: Tx128to255octGb, + tx256to511oct_gb: Tx256to511octGb, + tx512to1023oct_gb: Tx512to1023octGb, + tx1024maxoct_gb: Tx1024maxoctGb, + txucastframe_gb: TxucastframeGb, + txmcastframe_gb: TxmcastframeGb, + txbcastframe_gb: TxbcastframeGb, + txundererr: Txundererr, + txsinglecol_g: TxsinglecolG, + txmulticol_g: TxmulticolG, + txdeferred: Txdeferred, + txlatecol: Txlatecol, + txexesscol: Txexesscol, + txcarriererror: Txcarriererror, + txoctetcount_g: TxoctetcountG, + txframecount_g: TxframecountG, + txexcessdef: Txexcessdef, + txpauseframes: Txpauseframes, + txlanframes_g: TxlanframesG, + txoversize_g: TxoversizeG, + _reserved43: [u8; 0x04], + rxframecount_gb: RxframecountGb, + rxoctetcount_gb: RxoctetcountGb, + rxoctetcount_g: RxoctetcountG, + rxbcastframes_g: RxbcastframesG, + rxmcastframes_g: RxmcastframesG, + rxcrcerror: Rxcrcerror, + rxalignerror: Rxalignerror, + rxrunterror: Rxrunterror, + rxjabbererror: Rxjabbererror, + rxundersize_g: RxundersizeG, + rxoversize_g: RxoversizeG, + rx64octets_gb: Rx64octetsGb, + rx65to127oct_gb: Rx65to127octGb, + rx128to255oct_gb: Rx128to255octGb, + rx256to511oct_gb: Rx256to511octGb, + rx512to1023oct_gb: Rx512to1023octGb, + rx1024maxoct_gb: Rx1024maxoctGb, + rxucastframes_g: RxucastframesG, + rxlengtherror: Rxlengtherror, + rxoutrangetype: Rxoutrangetype, + rxpauseframes: Rxpauseframes, + rxfifooverflow: Rxfifooverflow, + rxvlanframes_gb: RxvlanframesGb, + rxwdogerror: Rxwdogerror, + rxrcverror: Rxrcverror, + rxctrlframes_g: RxctrlframesG, + _reserved69: [u8; 0x039c], + vlan_increplace: VlanIncreplace, + vlan_hashtable: VlanHashtable, + _reserved71: [u8; 0x0174], + timestamp_ctrl: TimestampCtrl, + subsec_inc: SubsecInc, + systime_seconds: SystimeSeconds, + systime_nanosec: SystimeNanosec, + systime_secsupdat: SystimeSecsupdat, + systime_nsecup: SystimeNsecup, + timestampaddend: Timestampaddend, + target_time_secs: TargetTimeSecs, + target_time_nsec: TargetTimeNsec, + _reserved80: [u8; 0x08dc], + dma_bus_mode: DmaBusMode, + dma_tx_poll_demand: DmaTxPollDemand, + dma_rx_poll_demand: DmaRxPollDemand, + dma_rx_desc_list_addr: DmaRxDescListAddr, + dma_tx_desc_list_addr: DmaTxDescListAddr, + dma_status: DmaStatus, + dma_oper_mode: DmaOperMode, + dma_intr_en: DmaIntrEn, + dma_miss_over_counter: DmaMissOverCounter, + dma_rx_intr_wdog_timer: DmaRxIntrWdogTimer, + _reserved90: [u8; 0x04], + dma_ahb_status: DmaAhbStatus, + _reserved91: [u8; 0x18], + dma_curr_tx_desc: DmaCurrTxDesc, + dma_curr_rx_desc: DmaCurrRxDesc, + dma_curr_tx_bufr_addr: DmaCurrTxBufrAddr, + dma_curr_rx_bufr_addr: DmaCurrRxBufrAddr, +} +impl RegisterBlock { + #[doc = "0x00 - Operation mode register for the MAC"] + #[inline(always)] + pub const fn mac_config(&self) -> &MacConfig { + &self.mac_config + } + #[doc = "0x04 - Contains the frame filtering controls"] + #[inline(always)] + pub const fn mac_frame_fltr(&self) -> &MacFrameFltr { + &self.mac_frame_fltr + } + #[doc = "0x10 - Controls the management cycles to an external PHY"] + #[inline(always)] + pub const fn mac_gmii_addr(&self) -> &MacGmiiAddr { + &self.mac_gmii_addr + } + #[doc = "0x14 - Contains the data to be written to or read from the PHY register"] + #[inline(always)] + pub const fn mac_gmii_data(&self) -> &MacGmiiData { + &self.mac_gmii_data + } + #[doc = "0x18 - Controls the generation of control frames"] + #[inline(always)] + pub const fn mac_flow_ctrl(&self) -> &MacFlowCtrl { + &self.mac_flow_ctrl + } + #[doc = "0x1c - Identifies IEEE 802.1Q VLAN type frames"] + #[inline(always)] + pub const fn mac_vlan_tag(&self) -> &MacVlanTag { + &self.mac_vlan_tag + } + #[doc = "0x24 - Gives the status of the various internal blocks for debugging"] + #[inline(always)] + pub const fn mac_debug(&self) -> &MacDebug { + &self.mac_debug + } + #[doc = "0x38 - Contains the interrupt status"] + #[inline(always)] + pub const fn mac_intr_stat(&self) -> &MacIntrStat { + &self.mac_intr_stat + } + #[doc = "0x3c - Contains the masks for generating interrupt"] + #[inline(always)] + pub const fn mac_intr_mask(&self) -> &MacIntrMask { + &self.mac_intr_mask + } + #[doc = "0x40 - Contains the high 16-bits of the first MAC Address"] + #[inline(always)] + pub const fn mac_addr_h(&self) -> &MacAddrH { + &self.mac_addr_h + } + #[doc = "0x44 - Contains the Low 32-bits of the first MAC Address"] + #[inline(always)] + pub const fn mac_addr_l(&self) -> &MacAddrL { + &self.mac_addr_l + } + #[doc = "0xdc - Controls the watchdog time-out for received frames"] + #[inline(always)] + pub const fn mac_wdog_to(&self) -> &MacWdogTo { + &self.mac_wdog_to + } + #[doc = "0x100 - MMC Control Register"] + #[inline(always)] + pub const fn mmc_cntrl(&self) -> &MmcCntrl { + &self.mmc_cntrl + } + #[doc = "0x104 - MMC Receive Interrupt Register"] + #[inline(always)] + pub const fn mmc_intr_rx(&self) -> &MmcIntrRx { + &self.mmc_intr_rx + } + #[doc = "0x108 - MMC Transmit Interrupt Register"] + #[inline(always)] + pub const fn mmc_intr_tx(&self) -> &MmcIntrTx { + &self.mmc_intr_tx + } + #[doc = "0x10c - MMC Receive Interrupt Mask Register"] + #[inline(always)] + pub const fn mmc_intr_mask_rx(&self) -> &MmcIntrMaskRx { + &self.mmc_intr_mask_rx + } + #[doc = "0x110 - MMC Transmit Interrupt Mask Register"] + #[inline(always)] + pub const fn mmc_intr_mask_tx(&self) -> &MmcIntrMaskTx { + &self.mmc_intr_mask_tx + } + #[doc = "0x114 - MMC Transmit Count"] + #[inline(always)] + pub const fn txoctetcount_gb(&self) -> &TxoctetcountGb { + &self.txoctetcount_gb + } + #[doc = "0x118 - MMC Frame Count Register"] + #[inline(always)] + pub const fn txframecount_gb(&self) -> &TxframecountGb { + &self.txframecount_gb + } + #[doc = "0x11c - MMC Good Broadcast Frames Register"] + #[inline(always)] + pub const fn txbcastframes_g(&self) -> &TxbcastframesG { + &self.txbcastframes_g + } + #[doc = "0x120 - MMC Good Multicast Frames Register"] + #[inline(always)] + pub const fn txmcastframes_g(&self) -> &TxmcastframesG { + &self.txmcastframes_g + } + #[doc = "0x124 - MMC Good and bad Frames transmitted with length 64"] + #[inline(always)] + pub const fn tx64oct_gb(&self) -> &Tx64octGb { + &self.tx64oct_gb + } + #[doc = "0x128 - MMC Good and bad Frames transmitted with length 65 to 127"] + #[inline(always)] + pub const fn tx65to127oct_gb(&self) -> &Tx65to127octGb { + &self.tx65to127oct_gb + } + #[doc = "0x12c - MMC Good and bad Frames transmitted with length 128 to 255"] + #[inline(always)] + pub const fn tx128to255oct_gb(&self) -> &Tx128to255octGb { + &self.tx128to255oct_gb + } + #[doc = "0x130 - MMC Good and bad Frames transmitted with length 256 to 511"] + #[inline(always)] + pub const fn tx256to511oct_gb(&self) -> &Tx256to511octGb { + &self.tx256to511oct_gb + } + #[doc = "0x134 - MMC Good and bad Frames transmitted with length 512 to 1023"] + #[inline(always)] + pub const fn tx512to1023oct_gb(&self) -> &Tx512to1023octGb { + &self.tx512to1023oct_gb + } + #[doc = "0x138 - MMC Good and bad Frames transmitted with length 1024 to max bytes"] + #[inline(always)] + pub const fn tx1024maxoct_gb(&self) -> &Tx1024maxoctGb { + &self.tx1024maxoct_gb + } + #[doc = "0x13c - MMC number of good and bad unicast frames transmitted"] + #[inline(always)] + pub const fn txucastframe_gb(&self) -> &TxucastframeGb { + &self.txucastframe_gb + } + #[doc = "0x140 - MMC number of good and bad MULTIcast frames transmitted"] + #[inline(always)] + pub const fn txmcastframe_gb(&self) -> &TxmcastframeGb { + &self.txmcastframe_gb + } + #[doc = "0x144 - MMC number of good and bad broadcast frames transmitted"] + #[inline(always)] + pub const fn txbcastframe_gb(&self) -> &TxbcastframeGb { + &self.txbcastframe_gb + } + #[doc = "0x148 - MMC number of frames aborted because of frame underflow error"] + #[inline(always)] + pub const fn txundererr(&self) -> &Txundererr { + &self.txundererr + } + #[doc = "0x14c - MMC Number of successfully transmitted frames after a single collision"] + #[inline(always)] + pub const fn txsinglecol_g(&self) -> &TxsinglecolG { + &self.txsinglecol_g + } + #[doc = "0x150 - MMC Number of successfully transmitted frames after multiple collisions"] + #[inline(always)] + pub const fn txmulticol_g(&self) -> &TxmulticolG { + &self.txmulticol_g + } + #[doc = "0x154 - MMC Number of successfully transmitted frames after a deferral"] + #[inline(always)] + pub const fn txdeferred(&self) -> &Txdeferred { + &self.txdeferred + } + #[doc = "0x158 - MMC Number of aborted frames because of late collision error"] + #[inline(always)] + pub const fn txlatecol(&self) -> &Txlatecol { + &self.txlatecol + } + #[doc = "0x15c - MMC Number of aborted frames because of excessive collision errors"] + #[inline(always)] + pub const fn txexesscol(&self) -> &Txexesscol { + &self.txexesscol + } + #[doc = "0x160 - MMC Number of aborted frames because of carrier sense error"] + #[inline(always)] + pub const fn txcarriererror(&self) -> &Txcarriererror { + &self.txcarriererror + } + #[doc = "0x164 - MMC Number of bytes transmitted frames only in good frames"] + #[inline(always)] + pub const fn txoctetcount_g(&self) -> &TxoctetcountG { + &self.txoctetcount_g + } + #[doc = "0x168 - MMC Number of good frames transmitted"] + #[inline(always)] + pub const fn txframecount_g(&self) -> &TxframecountG { + &self.txframecount_g + } + #[doc = "0x16c - MMC Number of frames aborted because of excessive deferral error"] + #[inline(always)] + pub const fn txexcessdef(&self) -> &Txexcessdef { + &self.txexcessdef + } + #[doc = "0x170 - MMC Number of good pause frames transmitted"] + #[inline(always)] + pub const fn txpauseframes(&self) -> &Txpauseframes { + &self.txpauseframes + } + #[doc = "0x174 - MMC Number of good VLAN frames transmitted"] + #[inline(always)] + pub const fn txlanframes_g(&self) -> &TxlanframesG { + &self.txlanframes_g + } + #[doc = "0x178 - MMC Number of frames transmitted without errors"] + #[inline(always)] + pub const fn txoversize_g(&self) -> &TxoversizeG { + &self.txoversize_g + } + #[doc = "0x180 - MMC Number of good and bad frames received"] + #[inline(always)] + pub const fn rxframecount_gb(&self) -> &RxframecountGb { + &self.rxframecount_gb + } + #[doc = "0x184 - MMC Number of bytes received in good and bad frames"] + #[inline(always)] + pub const fn rxoctetcount_gb(&self) -> &RxoctetcountGb { + &self.rxoctetcount_gb + } + #[doc = "0x188 - MMC Number of bytes received in good frames only"] + #[inline(always)] + pub const fn rxoctetcount_g(&self) -> &RxoctetcountG { + &self.rxoctetcount_g + } + #[doc = "0x18c - MMC Number of good broadcast frames received"] + #[inline(always)] + pub const fn rxbcastframes_g(&self) -> &RxbcastframesG { + &self.rxbcastframes_g + } + #[doc = "0x190 - MMC Number of good multicast frames received"] + #[inline(always)] + pub const fn rxmcastframes_g(&self) -> &RxmcastframesG { + &self.rxmcastframes_g + } + #[doc = "0x194 - MMC Number of frames received with CRC error"] + #[inline(always)] + pub const fn rxcrcerror(&self) -> &Rxcrcerror { + &self.rxcrcerror + } + #[doc = "0x198 - MMC Number of frames received with alignment error"] + #[inline(always)] + pub const fn rxalignerror(&self) -> &Rxalignerror { + &self.rxalignerror + } + #[doc = "0x19c - MMC Number of frames received with runt error"] + #[inline(always)] + pub const fn rxrunterror(&self) -> &Rxrunterror { + &self.rxrunterror + } + #[doc = "0x1a0 - MMC Number of giant frames received with length greater than 1518 bytes and with CRC error"] + #[inline(always)] + pub const fn rxjabbererror(&self) -> &Rxjabbererror { + &self.rxjabbererror + } + #[doc = "0x1a4 - MMC Number of frames received with length less than 64 bytes"] + #[inline(always)] + pub const fn rxundersize_g(&self) -> &RxundersizeG { + &self.rxundersize_g + } + #[doc = "0x1a8 - MMC Number of frames received without errors with length greater than the max size"] + #[inline(always)] + pub const fn rxoversize_g(&self) -> &RxoversizeG { + &self.rxoversize_g + } + #[doc = "0x1ac - MMC Number of good and bad frames received with length 64 bytes"] + #[inline(always)] + pub const fn rx64octets_gb(&self) -> &Rx64octetsGb { + &self.rx64octets_gb + } + #[doc = "0x1b0 - MMC Number of good and bad frames received with length between 65 and 127 bytes"] + #[inline(always)] + pub const fn rx65to127oct_gb(&self) -> &Rx65to127octGb { + &self.rx65to127oct_gb + } + #[doc = "0x1b4 - MMC Number of good and bad frames received with length between 128 and 255 bytes"] + #[inline(always)] + pub const fn rx128to255oct_gb(&self) -> &Rx128to255octGb { + &self.rx128to255oct_gb + } + #[doc = "0x1b8 - MMC Number of good and bad frames received with length between 256 and 511 bytes"] + #[inline(always)] + pub const fn rx256to511oct_gb(&self) -> &Rx256to511octGb { + &self.rx256to511oct_gb + } + #[doc = "0x1bc - MMC Number of good and bad frames received with length between 512 and 1023 bytes"] + #[inline(always)] + pub const fn rx512to1023oct_gb(&self) -> &Rx512to1023octGb { + &self.rx512to1023oct_gb + } + #[doc = "0x1c0 - MMC Number of good and bad frames received with length between 1024 and max size bytes"] + #[inline(always)] + pub const fn rx1024maxoct_gb(&self) -> &Rx1024maxoctGb { + &self.rx1024maxoct_gb + } + #[doc = "0x1c4 - MMC Number of received good unicast frames"] + #[inline(always)] + pub const fn rxucastframes_g(&self) -> &RxucastframesG { + &self.rxucastframes_g + } + #[doc = "0x1c8 - MMC Number of frames received with length error"] + #[inline(always)] + pub const fn rxlengtherror(&self) -> &Rxlengtherror { + &self.rxlengtherror + } + #[doc = "0x1cc - MMC Number of frames received with length field not equal to the valid frame size"] + #[inline(always)] + pub const fn rxoutrangetype(&self) -> &Rxoutrangetype { + &self.rxoutrangetype + } + #[doc = "0x1d0 - MMC Number of good and valid Pause frames received"] + #[inline(always)] + pub const fn rxpauseframes(&self) -> &Rxpauseframes { + &self.rxpauseframes + } + #[doc = "0x1d4 - MMC Number of missed received frames because of FIFO overflow"] + #[inline(always)] + pub const fn rxfifooverflow(&self) -> &Rxfifooverflow { + &self.rxfifooverflow + } + #[doc = "0x1d8 - MMC Number of good and bad VLAN frames received"] + #[inline(always)] + pub const fn rxvlanframes_gb(&self) -> &RxvlanframesGb { + &self.rxvlanframes_gb + } + #[doc = "0x1dc - MMC Number of frames received with error because of watchdog timeout error"] + #[inline(always)] + pub const fn rxwdogerror(&self) -> &Rxwdogerror { + &self.rxwdogerror + } + #[doc = "0x1e0 - MMC Number of frames received with Receive error or Frame Extension error"] + #[inline(always)] + pub const fn rxrcverror(&self) -> &Rxrcverror { + &self.rxrcverror + } + #[doc = "0x1e4 - MMC Number of received good control frames"] + #[inline(always)] + pub const fn rxctrlframes_g(&self) -> &RxctrlframesG { + &self.rxctrlframes_g + } + #[doc = "0x584 - Holds the VLAN Tag for insertion into or replacement in the transmit frames"] + #[inline(always)] + pub const fn vlan_increplace(&self) -> &VlanIncreplace { + &self.vlan_increplace + } + #[doc = "0x588 - Holds the VLAN Hash Table"] + #[inline(always)] + pub const fn vlan_hashtable(&self) -> &VlanHashtable { + &self.vlan_hashtable + } + #[doc = "0x700 - Controls the IEEE 1588 timestamp generation and update logic"] + #[inline(always)] + pub const fn timestamp_ctrl(&self) -> &TimestampCtrl { + &self.timestamp_ctrl + } + #[doc = "0x704 - Holds the 8-bit value by which the Sub-Second register is incremented"] + #[inline(always)] + pub const fn subsec_inc(&self) -> &SubsecInc { + &self.subsec_inc + } + #[doc = "0x708 - Holds the lower 32 bits of the second field of the system time"] + #[inline(always)] + pub const fn systime_seconds(&self) -> &SystimeSeconds { + &self.systime_seconds + } + #[doc = "0x70c - Holds 32 bits of the nano-second field of the system time"] + #[inline(always)] + pub const fn systime_nanosec(&self) -> &SystimeNanosec { + &self.systime_nanosec + } + #[doc = "0x710 - Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value"] + #[inline(always)] + pub const fn systime_secsupdat(&self) -> &SystimeSecsupdat { + &self.systime_secsupdat + } + #[doc = "0x714 - Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value"] + #[inline(always)] + pub const fn systime_nsecup(&self) -> &SystimeNsecup { + &self.systime_nsecup + } + #[doc = "0x718 - This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency"] + #[inline(always)] + pub const fn timestampaddend(&self) -> &Timestampaddend { + &self.timestampaddend + } + #[doc = "0x71c - Holds the high 32-bits of time to be compared with the system time"] + #[inline(always)] + pub const fn target_time_secs(&self) -> &TargetTimeSecs { + &self.target_time_secs + } + #[doc = "0x720 - Holds the lower 32-bits of time to be compared with the system time"] + #[inline(always)] + pub const fn target_time_nsec(&self) -> &TargetTimeNsec { + &self.target_time_nsec + } + #[doc = "0x1000 - Controls the DMA Host Interface Mode"] + #[inline(always)] + pub const fn dma_bus_mode(&self) -> &DmaBusMode { + &self.dma_bus_mode + } + #[doc = "0x1004 - Used by the host to instruct the DMA to poll the transmit Descriptor list"] + #[inline(always)] + pub const fn dma_tx_poll_demand(&self) -> &DmaTxPollDemand { + &self.dma_tx_poll_demand + } + #[doc = "0x1008 - Used by the host to instruct the DMA to poll the Receive Descriptor list"] + #[inline(always)] + pub const fn dma_rx_poll_demand(&self) -> &DmaRxPollDemand { + &self.dma_rx_poll_demand + } + #[doc = "0x100c - Points the DMA to the start of the Receive Descriptor list"] + #[inline(always)] + pub const fn dma_rx_desc_list_addr(&self) -> &DmaRxDescListAddr { + &self.dma_rx_desc_list_addr + } + #[doc = "0x1010 - Points the DMA to the start of the Transmit Descriptor list"] + #[inline(always)] + pub const fn dma_tx_desc_list_addr(&self) -> &DmaTxDescListAddr { + &self.dma_tx_desc_list_addr + } + #[doc = "0x1014 - Used to determine the status of the DMA"] + #[inline(always)] + pub const fn dma_status(&self) -> &DmaStatus { + &self.dma_status + } + #[doc = "0x1018 - Sets the Receive and Transmit operation mode and command"] + #[inline(always)] + pub const fn dma_oper_mode(&self) -> &DmaOperMode { + &self.dma_oper_mode + } + #[doc = "0x101c - Enables the interrupts reported in the status register"] + #[inline(always)] + pub const fn dma_intr_en(&self) -> &DmaIntrEn { + &self.dma_intr_en + } + #[doc = "0x1020 - Contains the counters for discarded frames because no Receive Descriptor is available"] + #[inline(always)] + pub const fn dma_miss_over_counter(&self) -> &DmaMissOverCounter { + &self.dma_miss_over_counter + } + #[doc = "0x1024 - Watchdog timeout for Receive Interrupt from DMA"] + #[inline(always)] + pub const fn dma_rx_intr_wdog_timer(&self) -> &DmaRxIntrWdogTimer { + &self.dma_rx_intr_wdog_timer + } + #[doc = "0x102c - Provides the active status of the read and write channels of the AHB master interface"] + #[inline(always)] + pub const fn dma_ahb_status(&self) -> &DmaAhbStatus { + &self.dma_ahb_status + } + #[doc = "0x1048 - Contains the start address of the current Transmit Descriptor read by the DMA"] + #[inline(always)] + pub const fn dma_curr_tx_desc(&self) -> &DmaCurrTxDesc { + &self.dma_curr_tx_desc + } + #[doc = "0x104c - Contains the start address of the current Receive Descriptor read by the DMA"] + #[inline(always)] + pub const fn dma_curr_rx_desc(&self) -> &DmaCurrRxDesc { + &self.dma_curr_rx_desc + } + #[doc = "0x1050 - Contains the start address of the current Receive Descriptor read by the DMA"] + #[inline(always)] + pub const fn dma_curr_tx_bufr_addr(&self) -> &DmaCurrTxBufrAddr { + &self.dma_curr_tx_bufr_addr + } + #[doc = "0x1054 - Contains the current Receive Buffer address read by the DMA"] + #[inline(always)] + pub const fn dma_curr_rx_bufr_addr(&self) -> &DmaCurrRxBufrAddr { + &self.dma_curr_rx_bufr_addr + } +} +#[doc = "MAC_CONFIG (rw) register accessor: Operation mode register for the MAC\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_config`] module"] +#[doc(alias = "MAC_CONFIG")] +pub type MacConfig = crate::Reg; +#[doc = "Operation mode register for the MAC"] +pub mod mac_config; +#[doc = "MAC_FRAME_FLTR (rw) register accessor: Contains the frame filtering controls\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_frame_fltr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_frame_fltr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_frame_fltr`] module"] +#[doc(alias = "MAC_FRAME_FLTR")] +pub type MacFrameFltr = crate::Reg; +#[doc = "Contains the frame filtering controls"] +pub mod mac_frame_fltr; +#[doc = "MAC_GMII_ADDR (rw) register accessor: Controls the management cycles to an external PHY\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_gmii_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_gmii_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_gmii_addr`] module"] +#[doc(alias = "MAC_GMII_ADDR")] +pub type MacGmiiAddr = crate::Reg; +#[doc = "Controls the management cycles to an external PHY"] +pub mod mac_gmii_addr; +#[doc = "MAC_GMII_DATA (rw) register accessor: Contains the data to be written to or read from the PHY register\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_gmii_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_gmii_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_gmii_data`] module"] +#[doc(alias = "MAC_GMII_DATA")] +pub type MacGmiiData = crate::Reg; +#[doc = "Contains the data to be written to or read from the PHY register"] +pub mod mac_gmii_data; +#[doc = "MAC_FLOW_CTRL (rw) register accessor: Controls the generation of control frames\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_flow_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_flow_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_flow_ctrl`] module"] +#[doc(alias = "MAC_FLOW_CTRL")] +pub type MacFlowCtrl = crate::Reg; +#[doc = "Controls the generation of control frames"] +pub mod mac_flow_ctrl; +#[doc = "MAC_VLAN_TAG (rw) register accessor: Identifies IEEE 802.1Q VLAN type frames\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_vlan_tag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_vlan_tag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_vlan_tag`] module"] +#[doc(alias = "MAC_VLAN_TAG")] +pub type MacVlanTag = crate::Reg; +#[doc = "Identifies IEEE 802.1Q VLAN type frames"] +pub mod mac_vlan_tag; +#[doc = "MAC_DEBUG (r) register accessor: Gives the status of the various internal blocks for debugging\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_debug::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_debug`] module"] +#[doc(alias = "MAC_DEBUG")] +pub type MacDebug = crate::Reg; +#[doc = "Gives the status of the various internal blocks for debugging"] +pub mod mac_debug; +#[doc = "MAC_INTR_STAT (r) register accessor: Contains the interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_intr_stat`] module"] +#[doc(alias = "MAC_INTR_STAT")] +pub type MacIntrStat = crate::Reg; +#[doc = "Contains the interrupt status"] +pub mod mac_intr_stat; +#[doc = "MAC_INTR_MASK (rw) register accessor: Contains the masks for generating interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_intr_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_intr_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_intr_mask`] module"] +#[doc(alias = "MAC_INTR_MASK")] +pub type MacIntrMask = crate::Reg; +#[doc = "Contains the masks for generating interrupt"] +pub mod mac_intr_mask; +#[doc = "MAC_ADDR_H (rw) register accessor: Contains the high 16-bits of the first MAC Address\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_addr_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_addr_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_addr_h`] module"] +#[doc(alias = "MAC_ADDR_H")] +pub type MacAddrH = crate::Reg; +#[doc = "Contains the high 16-bits of the first MAC Address"] +pub mod mac_addr_h; +#[doc = "MAC_ADDR_L (rw) register accessor: Contains the Low 32-bits of the first MAC Address\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_addr_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_addr_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_addr_l`] module"] +#[doc(alias = "MAC_ADDR_L")] +pub type MacAddrL = crate::Reg; +#[doc = "Contains the Low 32-bits of the first MAC Address"] +pub mod mac_addr_l; +#[doc = "MAC_WDOG_TO (rw) register accessor: Controls the watchdog time-out for received frames\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_wdog_to::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_wdog_to::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_wdog_to`] module"] +#[doc(alias = "MAC_WDOG_TO")] +pub type MacWdogTo = crate::Reg; +#[doc = "Controls the watchdog time-out for received frames"] +pub mod mac_wdog_to; +#[doc = "MMC_CNTRL (rw) register accessor: MMC Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_cntrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_cntrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_cntrl`] module"] +#[doc(alias = "MMC_CNTRL")] +pub type MmcCntrl = crate::Reg; +#[doc = "MMC Control Register"] +pub mod mmc_cntrl; +#[doc = "MMC_INTR_RX (rw) register accessor: MMC Receive Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_intr_rx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_intr_rx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_intr_rx`] module"] +#[doc(alias = "MMC_INTR_RX")] +pub type MmcIntrRx = crate::Reg; +#[doc = "MMC Receive Interrupt Register"] +pub mod mmc_intr_rx; +#[doc = "MMC_INTR_TX (rw) register accessor: MMC Transmit Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_intr_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_intr_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_intr_tx`] module"] +#[doc(alias = "MMC_INTR_TX")] +pub type MmcIntrTx = crate::Reg; +#[doc = "MMC Transmit Interrupt Register"] +pub mod mmc_intr_tx; +#[doc = "MMC_INTR_MASK_RX (rw) register accessor: MMC Receive Interrupt Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_intr_mask_rx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_intr_mask_rx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_intr_mask_rx`] module"] +#[doc(alias = "MMC_INTR_MASK_RX")] +pub type MmcIntrMaskRx = crate::Reg; +#[doc = "MMC Receive Interrupt Mask Register"] +pub mod mmc_intr_mask_rx; +#[doc = "MMC_INTR_MASK_TX (rw) register accessor: MMC Transmit Interrupt Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_intr_mask_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_intr_mask_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_intr_mask_tx`] module"] +#[doc(alias = "MMC_INTR_MASK_TX")] +pub type MmcIntrMaskTx = crate::Reg; +#[doc = "MMC Transmit Interrupt Mask Register"] +pub mod mmc_intr_mask_tx; +#[doc = "TXOCTETCOUNT_GB (r) register accessor: MMC Transmit Count\n\nYou can [`read`](crate::Reg::read) this register and get [`txoctetcount_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txoctetcount_gb`] module"] +#[doc(alias = "TXOCTETCOUNT_GB")] +pub type TxoctetcountGb = crate::Reg; +#[doc = "MMC Transmit Count"] +pub mod txoctetcount_gb; +#[doc = "TXFRAMECOUNT_GB (r) register accessor: MMC Frame Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txframecount_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txframecount_gb`] module"] +#[doc(alias = "TXFRAMECOUNT_GB")] +pub type TxframecountGb = crate::Reg; +#[doc = "MMC Frame Count Register"] +pub mod txframecount_gb; +#[doc = "TXBCASTFRAMES_G (r) register accessor: MMC Good Broadcast Frames Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcastframes_g`] module"] +#[doc(alias = "TXBCASTFRAMES_G")] +pub type TxbcastframesG = crate::Reg; +#[doc = "MMC Good Broadcast Frames Register"] +pub mod txbcastframes_g; +#[doc = "TXMCASTFRAMES_G (r) register accessor: MMC Good Multicast Frames Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txmcastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txmcastframes_g`] module"] +#[doc(alias = "TXMCASTFRAMES_G")] +pub type TxmcastframesG = crate::Reg; +#[doc = "MMC Good Multicast Frames Register"] +pub mod txmcastframes_g; +#[doc = "TX64OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 64\n\nYou can [`read`](crate::Reg::read) this register and get [`tx64oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx64oct_gb`] module"] +#[doc(alias = "TX64OCT_GB")] +pub type Tx64octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 64"] +pub mod tx64oct_gb; +#[doc = "TX65TO127OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 65 to 127\n\nYou can [`read`](crate::Reg::read) this register and get [`tx65to127oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx65to127oct_gb`] module"] +#[doc(alias = "TX65TO127OCT_GB")] +pub type Tx65to127octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 65 to 127"] +pub mod tx65to127oct_gb; +#[doc = "TX128TO255OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 128 to 255\n\nYou can [`read`](crate::Reg::read) this register and get [`tx128to255oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx128to255oct_gb`] module"] +#[doc(alias = "TX128TO255OCT_GB")] +pub type Tx128to255octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 128 to 255"] +pub mod tx128to255oct_gb; +#[doc = "TX256TO511OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 256 to 511\n\nYou can [`read`](crate::Reg::read) this register and get [`tx256to511oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx256to511oct_gb`] module"] +#[doc(alias = "TX256TO511OCT_GB")] +pub type Tx256to511octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 256 to 511"] +pub mod tx256to511oct_gb; +#[doc = "TX512TO1023OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 512 to 1023\n\nYou can [`read`](crate::Reg::read) this register and get [`tx512to1023oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx512to1023oct_gb`] module"] +#[doc(alias = "TX512TO1023OCT_GB")] +pub type Tx512to1023octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 512 to 1023"] +pub mod tx512to1023oct_gb; +#[doc = "TX1024MAXOCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 1024 to max bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`tx1024maxoct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx1024maxoct_gb`] module"] +#[doc(alias = "TX1024MAXOCT_GB")] +pub type Tx1024maxoctGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 1024 to max bytes"] +pub mod tx1024maxoct_gb; +#[doc = "TXUCASTFRAME_GB (r) register accessor: MMC number of good and bad unicast frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txucastframe_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txucastframe_gb`] module"] +#[doc(alias = "TXUCASTFRAME_GB")] +pub type TxucastframeGb = crate::Reg; +#[doc = "MMC number of good and bad unicast frames transmitted"] +pub mod txucastframe_gb; +#[doc = "TXMCASTFRAME_GB (r) register accessor: MMC number of good and bad MULTIcast frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txmcastframe_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txmcastframe_gb`] module"] +#[doc(alias = "TXMCASTFRAME_GB")] +pub type TxmcastframeGb = crate::Reg; +#[doc = "MMC number of good and bad MULTIcast frames transmitted"] +pub mod txmcastframe_gb; +#[doc = "TXBCASTFRAME_GB (r) register accessor: MMC number of good and bad broadcast frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcastframe_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcastframe_gb`] module"] +#[doc(alias = "TXBCASTFRAME_GB")] +pub type TxbcastframeGb = crate::Reg; +#[doc = "MMC number of good and bad broadcast frames transmitted"] +pub mod txbcastframe_gb; +#[doc = "TXUNDERERR (r) register accessor: MMC number of frames aborted because of frame underflow error\n\nYou can [`read`](crate::Reg::read) this register and get [`txundererr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txundererr`] module"] +#[doc(alias = "TXUNDERERR")] +pub type Txundererr = crate::Reg; +#[doc = "MMC number of frames aborted because of frame underflow error"] +pub mod txundererr; +#[doc = "TXSINGLECOL_G (r) register accessor: MMC Number of successfully transmitted frames after a single collision\n\nYou can [`read`](crate::Reg::read) this register and get [`txsinglecol_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txsinglecol_g`] module"] +#[doc(alias = "TXSINGLECOL_G")] +pub type TxsinglecolG = crate::Reg; +#[doc = "MMC Number of successfully transmitted frames after a single collision"] +pub mod txsinglecol_g; +#[doc = "TXMULTICOL_G (r) register accessor: MMC Number of successfully transmitted frames after multiple collisions\n\nYou can [`read`](crate::Reg::read) this register and get [`txmulticol_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txmulticol_g`] module"] +#[doc(alias = "TXMULTICOL_G")] +pub type TxmulticolG = crate::Reg; +#[doc = "MMC Number of successfully transmitted frames after multiple collisions"] +pub mod txmulticol_g; +#[doc = "TXDEFERRED (r) register accessor: MMC Number of successfully transmitted frames after a deferral\n\nYou can [`read`](crate::Reg::read) this register and get [`txdeferred::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txdeferred`] module"] +#[doc(alias = "TXDEFERRED")] +pub type Txdeferred = crate::Reg; +#[doc = "MMC Number of successfully transmitted frames after a deferral"] +pub mod txdeferred; +#[doc = "TXLATECOL (r) register accessor: MMC Number of aborted frames because of late collision error\n\nYou can [`read`](crate::Reg::read) this register and get [`txlatecol::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txlatecol`] module"] +#[doc(alias = "TXLATECOL")] +pub type Txlatecol = crate::Reg; +#[doc = "MMC Number of aborted frames because of late collision error"] +pub mod txlatecol; +#[doc = "TXEXESSCOL (r) register accessor: MMC Number of aborted frames because of excessive collision errors\n\nYou can [`read`](crate::Reg::read) this register and get [`txexesscol::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txexesscol`] module"] +#[doc(alias = "TXEXESSCOL")] +pub type Txexesscol = crate::Reg; +#[doc = "MMC Number of aborted frames because of excessive collision errors"] +pub mod txexesscol; +#[doc = "TXCARRIERERROR (r) register accessor: MMC Number of aborted frames because of carrier sense error\n\nYou can [`read`](crate::Reg::read) this register and get [`txcarriererror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcarriererror`] module"] +#[doc(alias = "TXCARRIERERROR")] +pub type Txcarriererror = crate::Reg; +#[doc = "MMC Number of aborted frames because of carrier sense error"] +pub mod txcarriererror; +#[doc = "TXOCTETCOUNT_G (r) register accessor: MMC Number of bytes transmitted frames only in good frames\n\nYou can [`read`](crate::Reg::read) this register and get [`txoctetcount_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txoctetcount_g`] module"] +#[doc(alias = "TXOCTETCOUNT_G")] +pub type TxoctetcountG = crate::Reg; +#[doc = "MMC Number of bytes transmitted frames only in good frames"] +pub mod txoctetcount_g; +#[doc = "TXFRAMECOUNT_G (r) register accessor: MMC Number of good frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txframecount_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txframecount_g`] module"] +#[doc(alias = "TXFRAMECOUNT_G")] +pub type TxframecountG = crate::Reg; +#[doc = "MMC Number of good frames transmitted"] +pub mod txframecount_g; +#[doc = "TXEXCESSDEF (r) register accessor: MMC Number of frames aborted because of excessive deferral error\n\nYou can [`read`](crate::Reg::read) this register and get [`txexcessdef::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txexcessdef`] module"] +#[doc(alias = "TXEXCESSDEF")] +pub type Txexcessdef = crate::Reg; +#[doc = "MMC Number of frames aborted because of excessive deferral error"] +pub mod txexcessdef; +#[doc = "TXPAUSEFRAMES (r) register accessor: MMC Number of good pause frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txpauseframes::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txpauseframes`] module"] +#[doc(alias = "TXPAUSEFRAMES")] +pub type Txpauseframes = crate::Reg; +#[doc = "MMC Number of good pause frames transmitted"] +pub mod txpauseframes; +#[doc = "TXLANFRAMES_G (r) register accessor: MMC Number of good VLAN frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txlanframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txlanframes_g`] module"] +#[doc(alias = "TXLANFRAMES_G")] +pub type TxlanframesG = crate::Reg; +#[doc = "MMC Number of good VLAN frames transmitted"] +pub mod txlanframes_g; +#[doc = "TXOVERSIZE_G (r) register accessor: MMC Number of frames transmitted without errors\n\nYou can [`read`](crate::Reg::read) this register and get [`txoversize_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txoversize_g`] module"] +#[doc(alias = "TXOVERSIZE_G")] +pub type TxoversizeG = crate::Reg; +#[doc = "MMC Number of frames transmitted without errors"] +pub mod txoversize_g; +#[doc = "RXFRAMECOUNT_GB (r) register accessor: MMC Number of good and bad frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxframecount_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxframecount_gb`] module"] +#[doc(alias = "RXFRAMECOUNT_GB")] +pub type RxframecountGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received"] +pub mod rxframecount_gb; +#[doc = "RXOCTETCOUNT_GB (r) register accessor: MMC Number of bytes received in good and bad frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rxoctetcount_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxoctetcount_gb`] module"] +#[doc(alias = "RXOCTETCOUNT_GB")] +pub type RxoctetcountGb = crate::Reg; +#[doc = "MMC Number of bytes received in good and bad frames"] +pub mod rxoctetcount_gb; +#[doc = "RXOCTETCOUNT_G (r) register accessor: MMC Number of bytes received in good frames only\n\nYou can [`read`](crate::Reg::read) this register and get [`rxoctetcount_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxoctetcount_g`] module"] +#[doc(alias = "RXOCTETCOUNT_G")] +pub type RxoctetcountG = crate::Reg; +#[doc = "MMC Number of bytes received in good frames only"] +pub mod rxoctetcount_g; +#[doc = "RXBCASTFRAMES_G (r) register accessor: MMC Number of good broadcast frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxbcastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxbcastframes_g`] module"] +#[doc(alias = "RXBCASTFRAMES_G")] +pub type RxbcastframesG = crate::Reg; +#[doc = "MMC Number of good broadcast frames received"] +pub mod rxbcastframes_g; +#[doc = "RXMCASTFRAMES_G (r) register accessor: MMC Number of good multicast frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxmcastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxmcastframes_g`] module"] +#[doc(alias = "RXMCASTFRAMES_G")] +pub type RxmcastframesG = crate::Reg; +#[doc = "MMC Number of good multicast frames received"] +pub mod rxmcastframes_g; +#[doc = "RXCRCERROR (r) register accessor: MMC Number of frames received with CRC error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcrcerror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcrcerror`] module"] +#[doc(alias = "RXCRCERROR")] +pub type Rxcrcerror = crate::Reg; +#[doc = "MMC Number of frames received with CRC error"] +pub mod rxcrcerror; +#[doc = "RXALIGNERROR (r) register accessor: MMC Number of frames received with alignment error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxalignerror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxalignerror`] module"] +#[doc(alias = "RXALIGNERROR")] +pub type Rxalignerror = crate::Reg; +#[doc = "MMC Number of frames received with alignment error"] +pub mod rxalignerror; +#[doc = "RXRUNTERROR (r) register accessor: MMC Number of frames received with runt error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxrunterror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxrunterror`] module"] +#[doc(alias = "RXRUNTERROR")] +pub type Rxrunterror = crate::Reg; +#[doc = "MMC Number of frames received with runt error"] +pub mod rxrunterror; +#[doc = "RXJABBERERROR (r) register accessor: MMC Number of giant frames received with length greater than 1518 bytes and with CRC error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxjabbererror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxjabbererror`] module"] +#[doc(alias = "RXJABBERERROR")] +pub type Rxjabbererror = crate::Reg; +#[doc = "MMC Number of giant frames received with length greater than 1518 bytes and with CRC error"] +pub mod rxjabbererror; +#[doc = "RXUNDERSIZE_G (r) register accessor: MMC Number of frames received with length less than 64 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rxundersize_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxundersize_g`] module"] +#[doc(alias = "RXUNDERSIZE_G")] +pub type RxundersizeG = crate::Reg; +#[doc = "MMC Number of frames received with length less than 64 bytes"] +pub mod rxundersize_g; +#[doc = "RXOVERSIZE_G (r) register accessor: MMC Number of frames received without errors with length greater than the max size\n\nYou can [`read`](crate::Reg::read) this register and get [`rxoversize_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxoversize_g`] module"] +#[doc(alias = "RXOVERSIZE_G")] +pub type RxoversizeG = crate::Reg; +#[doc = "MMC Number of frames received without errors with length greater than the max size"] +pub mod rxoversize_g; +#[doc = "RX64OCTETS_GB (r) register accessor: MMC Number of good and bad frames received with length 64 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx64octets_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx64octets_gb`] module"] +#[doc(alias = "RX64OCTETS_GB")] +pub type Rx64octetsGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length 64 bytes"] +pub mod rx64octets_gb; +#[doc = "RX65TO127OCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 65 and 127 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx65to127oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx65to127oct_gb`] module"] +#[doc(alias = "RX65TO127OCT_GB")] +pub type Rx65to127octGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 65 and 127 bytes"] +pub mod rx65to127oct_gb; +#[doc = "RX128TO255OCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 128 and 255 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx128to255oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx128to255oct_gb`] module"] +#[doc(alias = "RX128TO255OCT_GB")] +pub type Rx128to255octGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 128 and 255 bytes"] +pub mod rx128to255oct_gb; +#[doc = "RX256TO511OCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 256 and 511 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx256to511oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx256to511oct_gb`] module"] +#[doc(alias = "RX256TO511OCT_GB")] +pub type Rx256to511octGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 256 and 511 bytes"] +pub mod rx256to511oct_gb; +#[doc = "RX512TO1023OCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 512 and 1023 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx512to1023oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx512to1023oct_gb`] module"] +#[doc(alias = "RX512TO1023OCT_GB")] +pub type Rx512to1023octGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 512 and 1023 bytes"] +pub mod rx512to1023oct_gb; +#[doc = "RX1024MAXOCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 1024 and max size bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx1024maxoct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx1024maxoct_gb`] module"] +#[doc(alias = "RX1024MAXOCT_GB")] +pub type Rx1024maxoctGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 1024 and max size bytes"] +pub mod rx1024maxoct_gb; +#[doc = "RXUCASTFRAMES_G (r) register accessor: MMC Number of received good unicast frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rxucastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxucastframes_g`] module"] +#[doc(alias = "RXUCASTFRAMES_G")] +pub type RxucastframesG = crate::Reg; +#[doc = "MMC Number of received good unicast frames"] +pub mod rxucastframes_g; +#[doc = "RXLENGTHERROR (r) register accessor: MMC Number of frames received with length error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxlengtherror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxlengtherror`] module"] +#[doc(alias = "RXLENGTHERROR")] +pub type Rxlengtherror = crate::Reg; +#[doc = "MMC Number of frames received with length error"] +pub mod rxlengtherror; +#[doc = "RXOUTRANGETYPE (r) register accessor: MMC Number of frames received with length field not equal to the valid frame size\n\nYou can [`read`](crate::Reg::read) this register and get [`rxoutrangetype::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxoutrangetype`] module"] +#[doc(alias = "RXOUTRANGETYPE")] +pub type Rxoutrangetype = crate::Reg; +#[doc = "MMC Number of frames received with length field not equal to the valid frame size"] +pub mod rxoutrangetype; +#[doc = "RXPAUSEFRAMES (r) register accessor: MMC Number of good and valid Pause frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxpauseframes::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxpauseframes`] module"] +#[doc(alias = "RXPAUSEFRAMES")] +pub type Rxpauseframes = crate::Reg; +#[doc = "MMC Number of good and valid Pause frames received"] +pub mod rxpauseframes; +#[doc = "RXFIFOOVERFLOW (r) register accessor: MMC Number of missed received frames because of FIFO overflow\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifooverflow::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifooverflow`] module"] +#[doc(alias = "RXFIFOOVERFLOW")] +pub type Rxfifooverflow = crate::Reg; +#[doc = "MMC Number of missed received frames because of FIFO overflow"] +pub mod rxfifooverflow; +#[doc = "RXVLANFRAMES_GB (r) register accessor: MMC Number of good and bad VLAN frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxvlanframes_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxvlanframes_gb`] module"] +#[doc(alias = "RXVLANFRAMES_GB")] +pub type RxvlanframesGb = crate::Reg; +#[doc = "MMC Number of good and bad VLAN frames received"] +pub mod rxvlanframes_gb; +#[doc = "RXWDOGERROR (r) register accessor: MMC Number of frames received with error because of watchdog timeout error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxwdogerror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxwdogerror`] module"] +#[doc(alias = "RXWDOGERROR")] +pub type Rxwdogerror = crate::Reg; +#[doc = "MMC Number of frames received with error because of watchdog timeout error"] +pub mod rxwdogerror; +#[doc = "RXRCVERROR (r) register accessor: MMC Number of frames received with Receive error or Frame Extension error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxrcverror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxrcverror`] module"] +#[doc(alias = "RXRCVERROR")] +pub type Rxrcverror = crate::Reg; +#[doc = "MMC Number of frames received with Receive error or Frame Extension error"] +pub mod rxrcverror; +#[doc = "RXCTRLFRAMES_G (r) register accessor: MMC Number of received good control frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rxctrlframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxctrlframes_g`] module"] +#[doc(alias = "RXCTRLFRAMES_G")] +pub type RxctrlframesG = crate::Reg; +#[doc = "MMC Number of received good control frames"] +pub mod rxctrlframes_g; +#[doc = "VLAN_INCREPLACE (rw) register accessor: Holds the VLAN Tag for insertion into or replacement in the transmit frames\n\nYou can [`read`](crate::Reg::read) this register and get [`vlan_increplace::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vlan_increplace::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vlan_increplace`] module"] +#[doc(alias = "VLAN_INCREPLACE")] +pub type VlanIncreplace = crate::Reg; +#[doc = "Holds the VLAN Tag for insertion into or replacement in the transmit frames"] +pub mod vlan_increplace; +#[doc = "VLAN_HASHTABLE (rw) register accessor: Holds the VLAN Hash Table\n\nYou can [`read`](crate::Reg::read) this register and get [`vlan_hashtable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vlan_hashtable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vlan_hashtable`] module"] +#[doc(alias = "VLAN_HASHTABLE")] +pub type VlanHashtable = crate::Reg; +#[doc = "Holds the VLAN Hash Table"] +pub mod vlan_hashtable; +#[doc = "TIMESTAMP_CTRL (rw) register accessor: Controls the IEEE 1588 timestamp generation and update logic\n\nYou can [`read`](crate::Reg::read) this register and get [`timestamp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timestamp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestamp_ctrl`] module"] +#[doc(alias = "TIMESTAMP_CTRL")] +pub type TimestampCtrl = crate::Reg; +#[doc = "Controls the IEEE 1588 timestamp generation and update logic"] +pub mod timestamp_ctrl; +#[doc = "SUBSEC_INC (rw) register accessor: Holds the 8-bit value by which the Sub-Second register is incremented\n\nYou can [`read`](crate::Reg::read) this register and get [`subsec_inc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`subsec_inc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@subsec_inc`] module"] +#[doc(alias = "SUBSEC_INC")] +pub type SubsecInc = crate::Reg; +#[doc = "Holds the 8-bit value by which the Sub-Second register is incremented"] +pub mod subsec_inc; +#[doc = "SYSTIME_SECONDS (r) register accessor: Holds the lower 32 bits of the second field of the system time\n\nYou can [`read`](crate::Reg::read) this register and get [`systime_seconds::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systime_seconds`] module"] +#[doc(alias = "SYSTIME_SECONDS")] +pub type SystimeSeconds = crate::Reg; +#[doc = "Holds the lower 32 bits of the second field of the system time"] +pub mod systime_seconds; +#[doc = "SYSTIME_NANOSEC (r) register accessor: Holds 32 bits of the nano-second field of the system time\n\nYou can [`read`](crate::Reg::read) this register and get [`systime_nanosec::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systime_nanosec`] module"] +#[doc(alias = "SYSTIME_NANOSEC")] +pub type SystimeNanosec = crate::Reg; +#[doc = "Holds 32 bits of the nano-second field of the system time"] +pub mod systime_nanosec; +#[doc = "SYSTIME_SECSUPDAT (rw) register accessor: Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value\n\nYou can [`read`](crate::Reg::read) this register and get [`systime_secsupdat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`systime_secsupdat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systime_secsupdat`] module"] +#[doc(alias = "SYSTIME_SECSUPDAT")] +pub type SystimeSecsupdat = crate::Reg; +#[doc = "Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value"] +pub mod systime_secsupdat; +#[doc = "SYSTIME_NSECUP (rw) register accessor: Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value\n\nYou can [`read`](crate::Reg::read) this register and get [`systime_nsecup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`systime_nsecup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systime_nsecup`] module"] +#[doc(alias = "SYSTIME_NSECUP")] +pub type SystimeNsecup = crate::Reg; +#[doc = "Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value"] +pub mod systime_nsecup; +#[doc = "TIMESTAMPADDEND (rw) register accessor: This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency\n\nYou can [`read`](crate::Reg::read) this register and get [`timestampaddend::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timestampaddend::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestampaddend`] module"] +#[doc(alias = "TIMESTAMPADDEND")] +pub type Timestampaddend = crate::Reg; +#[doc = "This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency"] +pub mod timestampaddend; +#[doc = "TARGET_TIME_SECS (rw) register accessor: Holds the high 32-bits of time to be compared with the system time\n\nYou can [`read`](crate::Reg::read) this register and get [`target_time_secs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`target_time_secs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target_time_secs`] module"] +#[doc(alias = "TARGET_TIME_SECS")] +pub type TargetTimeSecs = crate::Reg; +#[doc = "Holds the high 32-bits of time to be compared with the system time"] +pub mod target_time_secs; +#[doc = "TARGET_TIME_NSEC (rw) register accessor: Holds the lower 32-bits of time to be compared with the system time\n\nYou can [`read`](crate::Reg::read) this register and get [`target_time_nsec::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`target_time_nsec::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target_time_nsec`] module"] +#[doc(alias = "TARGET_TIME_NSEC")] +pub type TargetTimeNsec = crate::Reg; +#[doc = "Holds the lower 32-bits of time to be compared with the system time"] +pub mod target_time_nsec; +#[doc = "DMA_BUS_MODE (rw) register accessor: Controls the DMA Host Interface Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_bus_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_bus_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_bus_mode`] module"] +#[doc(alias = "DMA_BUS_MODE")] +pub type DmaBusMode = crate::Reg; +#[doc = "Controls the DMA Host Interface Mode"] +pub mod dma_bus_mode; +#[doc = "DMA_TX_POLL_DEMAND (rw) register accessor: Used by the host to instruct the DMA to poll the transmit Descriptor list\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_tx_poll_demand::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_tx_poll_demand::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_tx_poll_demand`] module"] +#[doc(alias = "DMA_TX_POLL_DEMAND")] +pub type DmaTxPollDemand = crate::Reg; +#[doc = "Used by the host to instruct the DMA to poll the transmit Descriptor list"] +pub mod dma_tx_poll_demand; +#[doc = "DMA_RX_POLL_DEMAND (rw) register accessor: Used by the host to instruct the DMA to poll the Receive Descriptor list\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_rx_poll_demand::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_rx_poll_demand::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_rx_poll_demand`] module"] +#[doc(alias = "DMA_RX_POLL_DEMAND")] +pub type DmaRxPollDemand = crate::Reg; +#[doc = "Used by the host to instruct the DMA to poll the Receive Descriptor list"] +pub mod dma_rx_poll_demand; +#[doc = "DMA_RX_DESC_LIST_ADDR (rw) register accessor: Points the DMA to the start of the Receive Descriptor list\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_rx_desc_list_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_rx_desc_list_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_rx_desc_list_addr`] module"] +#[doc(alias = "DMA_RX_DESC_LIST_ADDR")] +pub type DmaRxDescListAddr = crate::Reg; +#[doc = "Points the DMA to the start of the Receive Descriptor list"] +pub mod dma_rx_desc_list_addr; +#[doc = "DMA_TX_DESC_LIST_ADDR (rw) register accessor: Points the DMA to the start of the Transmit Descriptor list\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_tx_desc_list_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_tx_desc_list_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_tx_desc_list_addr`] module"] +#[doc(alias = "DMA_TX_DESC_LIST_ADDR")] +pub type DmaTxDescListAddr = crate::Reg; +#[doc = "Points the DMA to the start of the Transmit Descriptor list"] +pub mod dma_tx_desc_list_addr; +#[doc = "DMA_STATUS (r) register accessor: Used to determine the status of the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_status`] module"] +#[doc(alias = "DMA_STATUS")] +pub type DmaStatus = crate::Reg; +#[doc = "Used to determine the status of the DMA"] +pub mod dma_status; +#[doc = "DMA_OPER_MODE (rw) register accessor: Sets the Receive and Transmit operation mode and command\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_oper_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_oper_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_oper_mode`] module"] +#[doc(alias = "DMA_OPER_MODE")] +pub type DmaOperMode = crate::Reg; +#[doc = "Sets the Receive and Transmit operation mode and command"] +pub mod dma_oper_mode; +#[doc = "DMA_INTR_EN (rw) register accessor: Enables the interrupts reported in the status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_intr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_intr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_intr_en`] module"] +#[doc(alias = "DMA_INTR_EN")] +pub type DmaIntrEn = crate::Reg; +#[doc = "Enables the interrupts reported in the status register"] +pub mod dma_intr_en; +#[doc = "DMA_MISS_OVER_COUNTER (rw) register accessor: Contains the counters for discarded frames because no Receive Descriptor is available\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_miss_over_counter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_miss_over_counter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_miss_over_counter`] module"] +#[doc(alias = "DMA_MISS_OVER_COUNTER")] +pub type DmaMissOverCounter = crate::Reg; +#[doc = "Contains the counters for discarded frames because no Receive Descriptor is available"] +pub mod dma_miss_over_counter; +#[doc = "DMA_RX_INTR_WDOG_TIMER (rw) register accessor: Watchdog timeout for Receive Interrupt from DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_rx_intr_wdog_timer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_rx_intr_wdog_timer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_rx_intr_wdog_timer`] module"] +#[doc(alias = "DMA_RX_INTR_WDOG_TIMER")] +pub type DmaRxIntrWdogTimer = crate::Reg; +#[doc = "Watchdog timeout for Receive Interrupt from DMA"] +pub mod dma_rx_intr_wdog_timer; +#[doc = "DMA_AHB_STATUS (rw) register accessor: Provides the active status of the read and write channels of the AHB master interface\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_ahb_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_ahb_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_ahb_status`] module"] +#[doc(alias = "DMA_AHB_STATUS")] +pub type DmaAhbStatus = crate::Reg; +#[doc = "Provides the active status of the read and write channels of the AHB master interface"] +pub mod dma_ahb_status; +#[doc = "DMA_CURR_TX_DESC (rw) register accessor: Contains the start address of the current Transmit Descriptor read by the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_curr_tx_desc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_curr_tx_desc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_curr_tx_desc`] module"] +#[doc(alias = "DMA_CURR_TX_DESC")] +pub type DmaCurrTxDesc = crate::Reg; +#[doc = "Contains the start address of the current Transmit Descriptor read by the DMA"] +pub mod dma_curr_tx_desc; +#[doc = "DMA_CURR_RX_DESC (rw) register accessor: Contains the start address of the current Receive Descriptor read by the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_curr_rx_desc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_curr_rx_desc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_curr_rx_desc`] module"] +#[doc(alias = "DMA_CURR_RX_DESC")] +pub type DmaCurrRxDesc = crate::Reg; +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA"] +pub mod dma_curr_rx_desc; +#[doc = "DMA_CURR_TX_BUFR_ADDR (rw) register accessor: Contains the start address of the current Receive Descriptor read by the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_curr_tx_bufr_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_curr_tx_bufr_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_curr_tx_bufr_addr`] module"] +#[doc(alias = "DMA_CURR_TX_BUFR_ADDR")] +pub type DmaCurrTxBufrAddr = crate::Reg; +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA"] +pub mod dma_curr_tx_bufr_addr; +#[doc = "DMA_CURR_RX_BUFR_ADDR (rw) register accessor: Contains the current Receive Buffer address read by the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_curr_rx_bufr_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_curr_rx_bufr_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_curr_rx_bufr_addr`] module"] +#[doc(alias = "DMA_CURR_RX_BUFR_ADDR")] +pub type DmaCurrRxBufrAddr = crate::Reg; +#[doc = "Contains the current Receive Buffer address read by the DMA"] +pub mod dma_curr_rx_bufr_addr; diff --git a/va416xx/va416xx/src/eth/dma_ahb_status.rs b/va416xx/va416xx/src/eth/dma_ahb_status.rs new file mode 100644 index 0000000..bfd68b8 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_ahb_status.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_AHB_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_AHB_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `AHBMASTRSTS` reader - When high, indicates that the AHB master interface FSMs are in the non-idle state"] +pub type AhbmastrstsR = crate::BitReader; +#[doc = "Field `AHBMASTRSTS` writer - When high, indicates that the AHB master interface FSMs are in the non-idle state"] +pub type AhbmastrstsW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When high, indicates that the AHB master interface FSMs are in the non-idle state"] + #[inline(always)] + pub fn ahbmastrsts(&self) -> AhbmastrstsR { + AhbmastrstsR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - When high, indicates that the AHB master interface FSMs are in the non-idle state"] + #[inline(always)] + pub fn ahbmastrsts(&mut self) -> AhbmastrstsW<'_, DmaAhbStatusSpec> { + AhbmastrstsW::new(self, 0) + } +} +#[doc = "Provides the active status of the read and write channels of the AHB master interface\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_ahb_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_ahb_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaAhbStatusSpec; +impl crate::RegisterSpec for DmaAhbStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_ahb_status::R`](R) reader structure"] +impl crate::Readable for DmaAhbStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_ahb_status::W`](W) writer structure"] +impl crate::Writable for DmaAhbStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_AHB_STATUS to value 0"] +impl crate::Resettable for DmaAhbStatusSpec {} diff --git a/va416xx/va416xx/src/eth/dma_bus_mode.rs b/va416xx/va416xx/src/eth/dma_bus_mode.rs new file mode 100644 index 0000000..9442255 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_bus_mode.rs @@ -0,0 +1,219 @@ +#[doc = "Register `DMA_BUS_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_BUS_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SWR` reader - Software Reset (Read, Write Set, and Self Clear)"] +pub type SwrR = crate::BitReader; +#[doc = "Field `SWR` writer - Software Reset (Read, Write Set, and Self Clear)"] +pub type SwrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DA` reader - DMA Arbitration Scheme"] +pub type DaR = crate::BitReader; +#[doc = "Field `DA` writer - DMA Arbitration Scheme"] +pub type DaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSL` reader - Descriptor Skip Length"] +pub type DslR = crate::FieldReader; +#[doc = "Field `DSL` writer - Descriptor Skip Length"] +pub type DslW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PBL` reader - Programmable Burst Lengthe"] +pub type PblR = crate::FieldReader; +#[doc = "Field `PBL` writer - Programmable Burst Lengthe"] +pub type PblW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PR` reader - Priority Ratio"] +pub type PrR = crate::FieldReader; +#[doc = "Field `PR` writer - Priority Ratio"] +pub type PrW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `FB` reader - Fixed Burste"] +pub type FbR = crate::BitReader; +#[doc = "Field `FB` writer - Fixed Burste"] +pub type FbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RPBL` reader - Rx DMA PBL"] +pub type RpblR = crate::FieldReader; +#[doc = "Field `RPBL` writer - Rx DMA PBL"] +pub type RpblW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `USP` reader - Use Separate PBL"] +pub type UspR = crate::BitReader; +#[doc = "Field `USP` writer - Use Separate PBL"] +pub type UspW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PBLx8` reader - PBLx8 Mode"] +pub type Pblx8R = crate::BitReader; +#[doc = "Field `PBLx8` writer - PBLx8 Mode"] +pub type Pblx8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AAL` reader - Address-Aligned Beats"] +pub type AalR = crate::BitReader; +#[doc = "Field `AAL` writer - Address-Aligned Beats"] +pub type AalW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MB` reader - Mixed Burst"] +pub type MbR = crate::BitReader; +#[doc = "Field `MB` writer - Mixed Burst"] +pub type MbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXPR` reader - Transmit Priority"] +pub type TxprR = crate::BitReader; +#[doc = "Field `TXPR` writer - Transmit Priority"] +pub type TxprW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PRWG` reader - Channel Priority Weights"] +pub type PrwgR = crate::FieldReader; +#[doc = "Field `PRWG` writer - Channel Priority Weights"] +pub type PrwgW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RIB` reader - Rebuild INCRx Burst"] +pub type RibR = crate::BitReader; +#[doc = "Field `RIB` writer - Rebuild INCRx Burst"] +pub type RibW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Software Reset (Read, Write Set, and Self Clear)"] + #[inline(always)] + pub fn swr(&self) -> SwrR { + SwrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Arbitration Scheme"] + #[inline(always)] + pub fn da(&self) -> DaR { + DaR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:6 - Descriptor Skip Length"] + #[inline(always)] + pub fn dsl(&self) -> DslR { + DslR::new(((self.bits >> 2) & 0x1f) as u8) + } + #[doc = "Bits 8:13 - Programmable Burst Lengthe"] + #[inline(always)] + pub fn pbl(&self) -> PblR { + PblR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 14:15 - Priority Ratio"] + #[inline(always)] + pub fn pr(&self) -> PrR { + PrR::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 16 - Fixed Burste"] + #[inline(always)] + pub fn fb(&self) -> FbR { + FbR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:22 - Rx DMA PBL"] + #[inline(always)] + pub fn rpbl(&self) -> RpblR { + RpblR::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bit 23 - Use Separate PBL"] + #[inline(always)] + pub fn usp(&self) -> UspR { + UspR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - PBLx8 Mode"] + #[inline(always)] + pub fn pblx8(&self) -> Pblx8R { + Pblx8R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Address-Aligned Beats"] + #[inline(always)] + pub fn aal(&self) -> AalR { + AalR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Mixed Burst"] + #[inline(always)] + pub fn mb(&self) -> MbR { + MbR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Transmit Priority"] + #[inline(always)] + pub fn txpr(&self) -> TxprR { + TxprR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:29 - Channel Priority Weights"] + #[inline(always)] + pub fn prwg(&self) -> PrwgR { + PrwgR::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 31 - Rebuild INCRx Burst"] + #[inline(always)] + pub fn rib(&self) -> RibR { + RibR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset (Read, Write Set, and Self Clear)"] + #[inline(always)] + pub fn swr(&mut self) -> SwrW<'_, DmaBusModeSpec> { + SwrW::new(self, 0) + } + #[doc = "Bit 1 - DMA Arbitration Scheme"] + #[inline(always)] + pub fn da(&mut self) -> DaW<'_, DmaBusModeSpec> { + DaW::new(self, 1) + } + #[doc = "Bits 2:6 - Descriptor Skip Length"] + #[inline(always)] + pub fn dsl(&mut self) -> DslW<'_, DmaBusModeSpec> { + DslW::new(self, 2) + } + #[doc = "Bits 8:13 - Programmable Burst Lengthe"] + #[inline(always)] + pub fn pbl(&mut self) -> PblW<'_, DmaBusModeSpec> { + PblW::new(self, 8) + } + #[doc = "Bits 14:15 - Priority Ratio"] + #[inline(always)] + pub fn pr(&mut self) -> PrW<'_, DmaBusModeSpec> { + PrW::new(self, 14) + } + #[doc = "Bit 16 - Fixed Burste"] + #[inline(always)] + pub fn fb(&mut self) -> FbW<'_, DmaBusModeSpec> { + FbW::new(self, 16) + } + #[doc = "Bits 17:22 - Rx DMA PBL"] + #[inline(always)] + pub fn rpbl(&mut self) -> RpblW<'_, DmaBusModeSpec> { + RpblW::new(self, 17) + } + #[doc = "Bit 23 - Use Separate PBL"] + #[inline(always)] + pub fn usp(&mut self) -> UspW<'_, DmaBusModeSpec> { + UspW::new(self, 23) + } + #[doc = "Bit 24 - PBLx8 Mode"] + #[inline(always)] + pub fn pblx8(&mut self) -> Pblx8W<'_, DmaBusModeSpec> { + Pblx8W::new(self, 24) + } + #[doc = "Bit 25 - Address-Aligned Beats"] + #[inline(always)] + pub fn aal(&mut self) -> AalW<'_, DmaBusModeSpec> { + AalW::new(self, 25) + } + #[doc = "Bit 26 - Mixed Burst"] + #[inline(always)] + pub fn mb(&mut self) -> MbW<'_, DmaBusModeSpec> { + MbW::new(self, 26) + } + #[doc = "Bit 27 - Transmit Priority"] + #[inline(always)] + pub fn txpr(&mut self) -> TxprW<'_, DmaBusModeSpec> { + TxprW::new(self, 27) + } + #[doc = "Bits 28:29 - Channel Priority Weights"] + #[inline(always)] + pub fn prwg(&mut self) -> PrwgW<'_, DmaBusModeSpec> { + PrwgW::new(self, 28) + } + #[doc = "Bit 31 - Rebuild INCRx Burst"] + #[inline(always)] + pub fn rib(&mut self) -> RibW<'_, DmaBusModeSpec> { + RibW::new(self, 31) + } +} +#[doc = "Controls the DMA Host Interface Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_bus_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_bus_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaBusModeSpec; +impl crate::RegisterSpec for DmaBusModeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_bus_mode::R`](R) reader structure"] +impl crate::Readable for DmaBusModeSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_bus_mode::W`](W) writer structure"] +impl crate::Writable for DmaBusModeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_BUS_MODE to value 0x0002_0101"] +impl crate::Resettable for DmaBusModeSpec { + const RESET_VALUE: u32 = 0x0002_0101; +} diff --git a/va416xx/va416xx/src/eth/dma_curr_rx_bufr_addr.rs b/va416xx/va416xx/src/eth/dma_curr_rx_bufr_addr.rs new file mode 100644 index 0000000..4407c02 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_curr_rx_bufr_addr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_CURR_RX_BUFR_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CURR_RX_BUFR_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CURTBUFAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtbufaptrR = crate::FieldReader; +#[doc = "Field `CURTBUFAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtbufaptrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&self) -> CurtbufaptrR { + CurtbufaptrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&mut self) -> CurtbufaptrW<'_, DmaCurrRxBufrAddrSpec> { + CurtbufaptrW::new(self, 0) + } +} +#[doc = "Contains the current Receive Buffer address read by the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_curr_rx_bufr_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_curr_rx_bufr_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaCurrRxBufrAddrSpec; +impl crate::RegisterSpec for DmaCurrRxBufrAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_curr_rx_bufr_addr::R`](R) reader structure"] +impl crate::Readable for DmaCurrRxBufrAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_curr_rx_bufr_addr::W`](W) writer structure"] +impl crate::Writable for DmaCurrRxBufrAddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_CURR_RX_BUFR_ADDR to value 0"] +impl crate::Resettable for DmaCurrRxBufrAddrSpec {} diff --git a/va416xx/va416xx/src/eth/dma_curr_rx_desc.rs b/va416xx/va416xx/src/eth/dma_curr_rx_desc.rs new file mode 100644 index 0000000..07e63a9 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_curr_rx_desc.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_CURR_RX_DESC` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CURR_RX_DESC` writer"] +pub type W = crate::W; +#[doc = "Field `CURRDESAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurrdesaptrR = crate::FieldReader; +#[doc = "Field `CURRDESAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurrdesaptrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn currdesaptr(&self) -> CurrdesaptrR { + CurrdesaptrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn currdesaptr(&mut self) -> CurrdesaptrW<'_, DmaCurrRxDescSpec> { + CurrdesaptrW::new(self, 0) + } +} +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_curr_rx_desc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_curr_rx_desc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaCurrRxDescSpec; +impl crate::RegisterSpec for DmaCurrRxDescSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_curr_rx_desc::R`](R) reader structure"] +impl crate::Readable for DmaCurrRxDescSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_curr_rx_desc::W`](W) writer structure"] +impl crate::Writable for DmaCurrRxDescSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_CURR_RX_DESC to value 0"] +impl crate::Resettable for DmaCurrRxDescSpec {} diff --git a/va416xx/va416xx/src/eth/dma_curr_tx_bufr_addr.rs b/va416xx/va416xx/src/eth/dma_curr_tx_bufr_addr.rs new file mode 100644 index 0000000..3ca5bdf --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_curr_tx_bufr_addr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_CURR_TX_BUFR_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CURR_TX_BUFR_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CURTBUFAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtbufaptrR = crate::FieldReader; +#[doc = "Field `CURTBUFAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtbufaptrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&self) -> CurtbufaptrR { + CurtbufaptrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&mut self) -> CurtbufaptrW<'_, DmaCurrTxBufrAddrSpec> { + CurtbufaptrW::new(self, 0) + } +} +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_curr_tx_bufr_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_curr_tx_bufr_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaCurrTxBufrAddrSpec; +impl crate::RegisterSpec for DmaCurrTxBufrAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_curr_tx_bufr_addr::R`](R) reader structure"] +impl crate::Readable for DmaCurrTxBufrAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_curr_tx_bufr_addr::W`](W) writer structure"] +impl crate::Writable for DmaCurrTxBufrAddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_CURR_TX_BUFR_ADDR to value 0"] +impl crate::Resettable for DmaCurrTxBufrAddrSpec {} diff --git a/va416xx/va416xx/src/eth/dma_curr_tx_desc.rs b/va416xx/va416xx/src/eth/dma_curr_tx_desc.rs new file mode 100644 index 0000000..2f24a16 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_curr_tx_desc.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_CURR_TX_DESC` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CURR_TX_DESC` writer"] +pub type W = crate::W; +#[doc = "Field `CURTDESAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtdesaptrR = crate::FieldReader; +#[doc = "Field `CURTDESAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtdesaptrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtdesaptr(&self) -> CurtdesaptrR { + CurtdesaptrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtdesaptr(&mut self) -> CurtdesaptrW<'_, DmaCurrTxDescSpec> { + CurtdesaptrW::new(self, 0) + } +} +#[doc = "Contains the start address of the current Transmit Descriptor read by the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_curr_tx_desc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_curr_tx_desc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaCurrTxDescSpec; +impl crate::RegisterSpec for DmaCurrTxDescSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_curr_tx_desc::R`](R) reader structure"] +impl crate::Readable for DmaCurrTxDescSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_curr_tx_desc::W`](W) writer structure"] +impl crate::Writable for DmaCurrTxDescSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_CURR_TX_DESC to value 0"] +impl crate::Resettable for DmaCurrTxDescSpec {} diff --git a/va416xx/va416xx/src/eth/dma_intr_en.rs b/va416xx/va416xx/src/eth/dma_intr_en.rs new file mode 100644 index 0000000..186c379 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_intr_en.rs @@ -0,0 +1,231 @@ +#[doc = "Register `DMA_INTR_EN` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_INTR_EN` writer"] +pub type W = crate::W; +#[doc = "Field `TIE` reader - Transmit Interrupt Enable"] +pub type TieR = crate::BitReader; +#[doc = "Field `TIE` writer - Transmit Interrupt Enable"] +pub type TieW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSE` reader - Transmit Stopped Enable"] +pub type TseR = crate::BitReader; +#[doc = "Field `TSE` writer - Transmit Stopped Enable"] +pub type TseW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TUE` reader - Transmit Buffer Unavailable Enable"] +pub type TueR = crate::BitReader; +#[doc = "Field `TUE` writer - Transmit Buffer Unavailable Enable"] +pub type TueW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THE` reader - Transmit Jabber Timeout Enable"] +pub type TheR = crate::BitReader; +#[doc = "Field `THE` writer - Transmit Jabber Timeout Enable"] +pub type TheW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVE` reader - Overflow Interrupt Enable"] +pub type OveR = crate::BitReader; +#[doc = "Field `OVE` writer - Overflow Interrupt Enable"] +pub type OveW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNE` reader - Underflow Interrupt Enable"] +pub type UneR = crate::BitReader; +#[doc = "Field `UNE` writer - Underflow Interrupt Enable"] +pub type UneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RIE` reader - Receive Interrupt Enable"] +pub type RieR = crate::BitReader; +#[doc = "Field `RIE` writer - Receive Interrupt Enable"] +pub type RieW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RUE` reader - Receive Buffer Unavailable Enable"] +pub type RueR = crate::BitReader; +#[doc = "Field `RUE` writer - Receive Buffer Unavailable Enable"] +pub type RueW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSE` reader - Receive Stopped Enable"] +pub type RseR = crate::BitReader; +#[doc = "Field `RSE` writer - Receive Stopped Enable"] +pub type RseW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RWE` reader - Receive Watchdog Timeout Enable"] +pub type RweR = crate::BitReader; +#[doc = "Field `RWE` writer - Receive Watchdog Timeout Enable"] +pub type RweW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETE` reader - Early Transmit Interrupt Enable"] +pub type EteR = crate::BitReader; +#[doc = "Field `ETE` writer - Early Transmit Interrupt Enable"] +pub type EteW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FBE` reader - Fatal Bus Error Enable"] +pub type FbeR = crate::BitReader; +#[doc = "Field `FBE` writer - Fatal Bus Error Enable"] +pub type FbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERE` reader - Early Receive Interrupt Enable"] +pub type EreR = crate::BitReader; +#[doc = "Field `ERE` writer - Early Receive Interrupt Enable"] +pub type EreW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AIE` reader - Abnormal Interrupt Summary Enable"] +pub type AieR = crate::BitReader; +#[doc = "Field `AIE` writer - Abnormal Interrupt Summary Enable"] +pub type AieW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NIE` reader - Normal Interrupt Summary Enable"] +pub type NieR = crate::BitReader; +#[doc = "Field `NIE` writer - Normal Interrupt Summary Enable"] +pub type NieW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Transmit Interrupt Enable"] + #[inline(always)] + pub fn tie(&self) -> TieR { + TieR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Stopped Enable"] + #[inline(always)] + pub fn tse(&self) -> TseR { + TseR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmit Buffer Unavailable Enable"] + #[inline(always)] + pub fn tue(&self) -> TueR { + TueR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmit Jabber Timeout Enable"] + #[inline(always)] + pub fn the(&self) -> TheR { + TheR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ove(&self) -> OveR { + OveR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Underflow Interrupt Enable"] + #[inline(always)] + pub fn une(&self) -> UneR { + UneR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Receive Interrupt Enable"] + #[inline(always)] + pub fn rie(&self) -> RieR { + RieR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Receive Buffer Unavailable Enable"] + #[inline(always)] + pub fn rue(&self) -> RueR { + RueR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Receive Stopped Enable"] + #[inline(always)] + pub fn rse(&self) -> RseR { + RseR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Receive Watchdog Timeout Enable"] + #[inline(always)] + pub fn rwe(&self) -> RweR { + RweR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Early Transmit Interrupt Enable"] + #[inline(always)] + pub fn ete(&self) -> EteR { + EteR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - Fatal Bus Error Enable"] + #[inline(always)] + pub fn fbe(&self) -> FbeR { + FbeR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Early Receive Interrupt Enable"] + #[inline(always)] + pub fn ere(&self) -> EreR { + EreR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Abnormal Interrupt Summary Enable"] + #[inline(always)] + pub fn aie(&self) -> AieR { + AieR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Normal Interrupt Summary Enable"] + #[inline(always)] + pub fn nie(&self) -> NieR { + NieR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit Interrupt Enable"] + #[inline(always)] + pub fn tie(&mut self) -> TieW<'_, DmaIntrEnSpec> { + TieW::new(self, 0) + } + #[doc = "Bit 1 - Transmit Stopped Enable"] + #[inline(always)] + pub fn tse(&mut self) -> TseW<'_, DmaIntrEnSpec> { + TseW::new(self, 1) + } + #[doc = "Bit 2 - Transmit Buffer Unavailable Enable"] + #[inline(always)] + pub fn tue(&mut self) -> TueW<'_, DmaIntrEnSpec> { + TueW::new(self, 2) + } + #[doc = "Bit 3 - Transmit Jabber Timeout Enable"] + #[inline(always)] + pub fn the(&mut self) -> TheW<'_, DmaIntrEnSpec> { + TheW::new(self, 3) + } + #[doc = "Bit 4 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ove(&mut self) -> OveW<'_, DmaIntrEnSpec> { + OveW::new(self, 4) + } + #[doc = "Bit 5 - Underflow Interrupt Enable"] + #[inline(always)] + pub fn une(&mut self) -> UneW<'_, DmaIntrEnSpec> { + UneW::new(self, 5) + } + #[doc = "Bit 6 - Receive Interrupt Enable"] + #[inline(always)] + pub fn rie(&mut self) -> RieW<'_, DmaIntrEnSpec> { + RieW::new(self, 6) + } + #[doc = "Bit 7 - Receive Buffer Unavailable Enable"] + #[inline(always)] + pub fn rue(&mut self) -> RueW<'_, DmaIntrEnSpec> { + RueW::new(self, 7) + } + #[doc = "Bit 8 - Receive Stopped Enable"] + #[inline(always)] + pub fn rse(&mut self) -> RseW<'_, DmaIntrEnSpec> { + RseW::new(self, 8) + } + #[doc = "Bit 9 - Receive Watchdog Timeout Enable"] + #[inline(always)] + pub fn rwe(&mut self) -> RweW<'_, DmaIntrEnSpec> { + RweW::new(self, 9) + } + #[doc = "Bit 10 - Early Transmit Interrupt Enable"] + #[inline(always)] + pub fn ete(&mut self) -> EteW<'_, DmaIntrEnSpec> { + EteW::new(self, 10) + } + #[doc = "Bit 13 - Fatal Bus Error Enable"] + #[inline(always)] + pub fn fbe(&mut self) -> FbeW<'_, DmaIntrEnSpec> { + FbeW::new(self, 13) + } + #[doc = "Bit 14 - Early Receive Interrupt Enable"] + #[inline(always)] + pub fn ere(&mut self) -> EreW<'_, DmaIntrEnSpec> { + EreW::new(self, 14) + } + #[doc = "Bit 15 - Abnormal Interrupt Summary Enable"] + #[inline(always)] + pub fn aie(&mut self) -> AieW<'_, DmaIntrEnSpec> { + AieW::new(self, 15) + } + #[doc = "Bit 16 - Normal Interrupt Summary Enable"] + #[inline(always)] + pub fn nie(&mut self) -> NieW<'_, DmaIntrEnSpec> { + NieW::new(self, 16) + } +} +#[doc = "Enables the interrupts reported in the status register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_intr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_intr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaIntrEnSpec; +impl crate::RegisterSpec for DmaIntrEnSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_intr_en::R`](R) reader structure"] +impl crate::Readable for DmaIntrEnSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_intr_en::W`](W) writer structure"] +impl crate::Writable for DmaIntrEnSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_INTR_EN to value 0"] +impl crate::Resettable for DmaIntrEnSpec {} diff --git a/va416xx/va416xx/src/eth/dma_miss_over_counter.rs b/va416xx/va416xx/src/eth/dma_miss_over_counter.rs new file mode 100644 index 0000000..6a46a37 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_miss_over_counter.rs @@ -0,0 +1,77 @@ +#[doc = "Register `DMA_MISS_OVER_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_MISS_OVER_COUNTER` writer"] +pub type W = crate::W; +#[doc = "Field `MISFRMCNT` reader - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] +pub type MisfrmcntR = crate::FieldReader; +#[doc = "Field `MISFRMCNT` writer - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] +pub type MisfrmcntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `MISCNTOVF` reader - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] +pub type MiscntovfR = crate::BitReader; +#[doc = "Field `MISCNTOVF` writer - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] +pub type MiscntovfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVFFRMCNT` reader - This field indicates the number of frames missed by the application"] +pub type OvffrmcntR = crate::FieldReader; +#[doc = "Field `OVFFRMCNT` writer - This field indicates the number of frames missed by the application"] +pub type OvffrmcntW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `OVFCNTOVF` reader - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] +pub type OvfcntovfR = crate::BitReader; +#[doc = "Field `OVFCNTOVF` writer - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] +pub type OvfcntovfW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] + #[inline(always)] + pub fn misfrmcnt(&self) -> MisfrmcntR { + MisfrmcntR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] + #[inline(always)] + pub fn miscntovf(&self) -> MiscntovfR { + MiscntovfR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:27 - This field indicates the number of frames missed by the application"] + #[inline(always)] + pub fn ovffrmcnt(&self) -> OvffrmcntR { + OvffrmcntR::new(((self.bits >> 17) & 0x07ff) as u16) + } + #[doc = "Bit 28 - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] + #[inline(always)] + pub fn ovfcntovf(&self) -> OvfcntovfR { + OvfcntovfR::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] + #[inline(always)] + pub fn misfrmcnt(&mut self) -> MisfrmcntW<'_, DmaMissOverCounterSpec> { + MisfrmcntW::new(self, 0) + } + #[doc = "Bit 16 - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] + #[inline(always)] + pub fn miscntovf(&mut self) -> MiscntovfW<'_, DmaMissOverCounterSpec> { + MiscntovfW::new(self, 16) + } + #[doc = "Bits 17:27 - This field indicates the number of frames missed by the application"] + #[inline(always)] + pub fn ovffrmcnt(&mut self) -> OvffrmcntW<'_, DmaMissOverCounterSpec> { + OvffrmcntW::new(self, 17) + } + #[doc = "Bit 28 - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] + #[inline(always)] + pub fn ovfcntovf(&mut self) -> OvfcntovfW<'_, DmaMissOverCounterSpec> { + OvfcntovfW::new(self, 28) + } +} +#[doc = "Contains the counters for discarded frames because no Receive Descriptor is available\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_miss_over_counter::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_miss_over_counter::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaMissOverCounterSpec; +impl crate::RegisterSpec for DmaMissOverCounterSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_miss_over_counter::R`](R) reader structure"] +impl crate::Readable for DmaMissOverCounterSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_miss_over_counter::W`](W) writer structure"] +impl crate::Writable for DmaMissOverCounterSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_MISS_OVER_COUNTER to value 0"] +impl crate::Resettable for DmaMissOverCounterSpec {} diff --git a/va416xx/va416xx/src/eth/dma_oper_mode.rs b/va416xx/va416xx/src/eth/dma_oper_mode.rs new file mode 100644 index 0000000..a712586 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_oper_mode.rs @@ -0,0 +1,231 @@ +#[doc = "Register `DMA_OPER_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_OPER_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SR` reader - Start or Stop Receive"] +pub type SrR = crate::BitReader; +#[doc = "Field `SR` writer - Start or Stop Receive"] +pub type SrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OSF` reader - Operate on Second Frame"] +pub type OsfR = crate::BitReader; +#[doc = "Field `OSF` writer - Operate on Second Frame"] +pub type OsfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC` reader - Receive Threshold Control"] +pub type RtcR = crate::FieldReader; +#[doc = "Field `RTC` writer - Receive Threshold Control"] +pub type RtcW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DGF` reader - Drop Giant Frames"] +pub type DgfR = crate::BitReader; +#[doc = "Field `DGF` writer - Drop Giant Frames"] +pub type DgfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FUF` reader - Forward Undersized Good Frames"] +pub type FufR = crate::BitReader; +#[doc = "Field `FUF` writer - Forward Undersized Good Frames"] +pub type FufW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FEF` reader - Forward Error Frames"] +pub type FefR = crate::BitReader; +#[doc = "Field `FEF` writer - Forward Error Frames"] +pub type FefW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RFA` reader - Threshold for Activating Flow Control"] +pub type RfaR = crate::FieldReader; +#[doc = "Field `RFA` writer - Threshold for Activating Flow Control"] +pub type RfaW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RFD` reader - Threshold for Deactivating Flow Control"] +pub type RfdR = crate::FieldReader; +#[doc = "Field `RFD` writer - Threshold for Deactivating Flow Control"] +pub type RfdW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ST` reader - Start or Stop Transmission Command"] +pub type StR = crate::BitReader; +#[doc = "Field `ST` writer - Start or Stop Transmission Command"] +pub type StW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TTC` reader - Transmit Threshold Control"] +pub type TtcR = crate::FieldReader; +#[doc = "Field `TTC` writer - Transmit Threshold Control"] +pub type TtcW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `FTF` reader - Flush Transmit FIFO"] +pub type FtfR = crate::BitReader; +#[doc = "Field `FTF` writer - Flush Transmit FIFO"] +pub type FtfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSF` reader - Transmit Store and Forward"] +pub type TsfR = crate::BitReader; +#[doc = "Field `TSF` writer - Transmit Store and Forward"] +pub type TsfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DFF` reader - Disable Flushing of Received Frames"] +pub type DffR = crate::BitReader; +#[doc = "Field `DFF` writer - Disable Flushing of Received Frames"] +pub type DffW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSF` reader - Receive Store and Forward"] +pub type RsfR = crate::BitReader; +#[doc = "Field `RSF` writer - Receive Store and Forward"] +pub type RsfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DT` reader - Disable Dropping of TCP/IP Checksum Error Frames"] +pub type DtR = crate::BitReader; +#[doc = "Field `DT` writer - Disable Dropping of TCP/IP Checksum Error Frames"] +pub type DtW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Start or Stop Receive"] + #[inline(always)] + pub fn sr(&self) -> SrR { + SrR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Operate on Second Frame"] + #[inline(always)] + pub fn osf(&self) -> OsfR { + OsfR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - Receive Threshold Control"] + #[inline(always)] + pub fn rtc(&self) -> RtcR { + RtcR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Drop Giant Frames"] + #[inline(always)] + pub fn dgf(&self) -> DgfR { + DgfR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Forward Undersized Good Frames"] + #[inline(always)] + pub fn fuf(&self) -> FufR { + FufR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Forward Error Frames"] + #[inline(always)] + pub fn fef(&self) -> FefR { + FefR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 9:10 - Threshold for Activating Flow Control"] + #[inline(always)] + pub fn rfa(&self) -> RfaR { + RfaR::new(((self.bits >> 9) & 3) as u8) + } + #[doc = "Bits 11:12 - Threshold for Deactivating Flow Control"] + #[inline(always)] + pub fn rfd(&self) -> RfdR { + RfdR::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bit 13 - Start or Stop Transmission Command"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:16 - Transmit Threshold Control"] + #[inline(always)] + pub fn ttc(&self) -> TtcR { + TtcR::new(((self.bits >> 14) & 7) as u8) + } + #[doc = "Bit 20 - Flush Transmit FIFO"] + #[inline(always)] + pub fn ftf(&self) -> FtfR { + FtfR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Transmit Store and Forward"] + #[inline(always)] + pub fn tsf(&self) -> TsfR { + TsfR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 24 - Disable Flushing of Received Frames"] + #[inline(always)] + pub fn dff(&self) -> DffR { + DffR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Receive Store and Forward"] + #[inline(always)] + pub fn rsf(&self) -> RsfR { + RsfR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Disable Dropping of TCP/IP Checksum Error Frames"] + #[inline(always)] + pub fn dt(&self) -> DtR { + DtR::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Start or Stop Receive"] + #[inline(always)] + pub fn sr(&mut self) -> SrW<'_, DmaOperModeSpec> { + SrW::new(self, 1) + } + #[doc = "Bit 2 - Operate on Second Frame"] + #[inline(always)] + pub fn osf(&mut self) -> OsfW<'_, DmaOperModeSpec> { + OsfW::new(self, 2) + } + #[doc = "Bits 3:4 - Receive Threshold Control"] + #[inline(always)] + pub fn rtc(&mut self) -> RtcW<'_, DmaOperModeSpec> { + RtcW::new(self, 3) + } + #[doc = "Bit 5 - Drop Giant Frames"] + #[inline(always)] + pub fn dgf(&mut self) -> DgfW<'_, DmaOperModeSpec> { + DgfW::new(self, 5) + } + #[doc = "Bit 6 - Forward Undersized Good Frames"] + #[inline(always)] + pub fn fuf(&mut self) -> FufW<'_, DmaOperModeSpec> { + FufW::new(self, 6) + } + #[doc = "Bit 7 - Forward Error Frames"] + #[inline(always)] + pub fn fef(&mut self) -> FefW<'_, DmaOperModeSpec> { + FefW::new(self, 7) + } + #[doc = "Bits 9:10 - Threshold for Activating Flow Control"] + #[inline(always)] + pub fn rfa(&mut self) -> RfaW<'_, DmaOperModeSpec> { + RfaW::new(self, 9) + } + #[doc = "Bits 11:12 - Threshold for Deactivating Flow Control"] + #[inline(always)] + pub fn rfd(&mut self) -> RfdW<'_, DmaOperModeSpec> { + RfdW::new(self, 11) + } + #[doc = "Bit 13 - Start or Stop Transmission Command"] + #[inline(always)] + pub fn st(&mut self) -> StW<'_, DmaOperModeSpec> { + StW::new(self, 13) + } + #[doc = "Bits 14:16 - Transmit Threshold Control"] + #[inline(always)] + pub fn ttc(&mut self) -> TtcW<'_, DmaOperModeSpec> { + TtcW::new(self, 14) + } + #[doc = "Bit 20 - Flush Transmit FIFO"] + #[inline(always)] + pub fn ftf(&mut self) -> FtfW<'_, DmaOperModeSpec> { + FtfW::new(self, 20) + } + #[doc = "Bit 21 - Transmit Store and Forward"] + #[inline(always)] + pub fn tsf(&mut self) -> TsfW<'_, DmaOperModeSpec> { + TsfW::new(self, 21) + } + #[doc = "Bit 24 - Disable Flushing of Received Frames"] + #[inline(always)] + pub fn dff(&mut self) -> DffW<'_, DmaOperModeSpec> { + DffW::new(self, 24) + } + #[doc = "Bit 25 - Receive Store and Forward"] + #[inline(always)] + pub fn rsf(&mut self) -> RsfW<'_, DmaOperModeSpec> { + RsfW::new(self, 25) + } + #[doc = "Bit 26 - Disable Dropping of TCP/IP Checksum Error Frames"] + #[inline(always)] + pub fn dt(&mut self) -> DtW<'_, DmaOperModeSpec> { + DtW::new(self, 26) + } +} +#[doc = "Sets the Receive and Transmit operation mode and command\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_oper_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_oper_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaOperModeSpec; +impl crate::RegisterSpec for DmaOperModeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_oper_mode::R`](R) reader structure"] +impl crate::Readable for DmaOperModeSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_oper_mode::W`](W) writer structure"] +impl crate::Writable for DmaOperModeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_OPER_MODE to value 0"] +impl crate::Resettable for DmaOperModeSpec {} diff --git a/va416xx/va416xx/src/eth/dma_rx_desc_list_addr.rs b/va416xx/va416xx/src/eth/dma_rx_desc_list_addr.rs new file mode 100644 index 0000000..2864a03 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_rx_desc_list_addr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_RX_DESC_LIST_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_RX_DESC_LIST_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `RDESLA` reader - Start of Receive List"] +pub type RdeslaR = crate::FieldReader; +#[doc = "Field `RDESLA` writer - Start of Receive List"] +pub type RdeslaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Start of Receive List"] + #[inline(always)] + pub fn rdesla(&self) -> RdeslaR { + RdeslaR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Start of Receive List"] + #[inline(always)] + pub fn rdesla(&mut self) -> RdeslaW<'_, DmaRxDescListAddrSpec> { + RdeslaW::new(self, 0) + } +} +#[doc = "Points the DMA to the start of the Receive Descriptor list\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_rx_desc_list_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_rx_desc_list_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaRxDescListAddrSpec; +impl crate::RegisterSpec for DmaRxDescListAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_rx_desc_list_addr::R`](R) reader structure"] +impl crate::Readable for DmaRxDescListAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_rx_desc_list_addr::W`](W) writer structure"] +impl crate::Writable for DmaRxDescListAddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_RX_DESC_LIST_ADDR to value 0"] +impl crate::Resettable for DmaRxDescListAddrSpec {} diff --git a/va416xx/va416xx/src/eth/dma_rx_intr_wdog_timer.rs b/va416xx/va416xx/src/eth/dma_rx_intr_wdog_timer.rs new file mode 100644 index 0000000..5a12981 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_rx_intr_wdog_timer.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_RX_INTR_WDOG_TIMER` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_RX_INTR_WDOG_TIMER` writer"] +pub type W = crate::W; +#[doc = "Field `RIWT` reader - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] +pub type RiwtR = crate::FieldReader; +#[doc = "Field `RIWT` writer - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] +pub type RiwtW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] + #[inline(always)] + pub fn riwt(&self) -> RiwtR { + RiwtR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] + #[inline(always)] + pub fn riwt(&mut self) -> RiwtW<'_, DmaRxIntrWdogTimerSpec> { + RiwtW::new(self, 0) + } +} +#[doc = "Watchdog timeout for Receive Interrupt from DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_rx_intr_wdog_timer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_rx_intr_wdog_timer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaRxIntrWdogTimerSpec; +impl crate::RegisterSpec for DmaRxIntrWdogTimerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_rx_intr_wdog_timer::R`](R) reader structure"] +impl crate::Readable for DmaRxIntrWdogTimerSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_rx_intr_wdog_timer::W`](W) writer structure"] +impl crate::Writable for DmaRxIntrWdogTimerSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_RX_INTR_WDOG_TIMER to value 0"] +impl crate::Resettable for DmaRxIntrWdogTimerSpec {} diff --git a/va416xx/va416xx/src/eth/dma_rx_poll_demand.rs b/va416xx/va416xx/src/eth/dma_rx_poll_demand.rs new file mode 100644 index 0000000..1f30770 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_rx_poll_demand.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_RX_POLL_DEMAND` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_RX_POLL_DEMAND` writer"] +pub type W = crate::W; +#[doc = "Field `RPD` reader - Receive Poll Demand (Read Only and Write Trigger)"] +pub type RpdR = crate::FieldReader; +#[doc = "Field `RPD` writer - Receive Poll Demand (Read Only and Write Trigger)"] +pub type RpdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Receive Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn rpd(&self) -> RpdR { + RpdR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Receive Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn rpd(&mut self) -> RpdW<'_, DmaRxPollDemandSpec> { + RpdW::new(self, 0) + } +} +#[doc = "Used by the host to instruct the DMA to poll the Receive Descriptor list\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_rx_poll_demand::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_rx_poll_demand::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaRxPollDemandSpec; +impl crate::RegisterSpec for DmaRxPollDemandSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_rx_poll_demand::R`](R) reader structure"] +impl crate::Readable for DmaRxPollDemandSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_rx_poll_demand::W`](W) writer structure"] +impl crate::Writable for DmaRxPollDemandSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_RX_POLL_DEMAND to value 0"] +impl crate::Resettable for DmaRxPollDemandSpec {} diff --git a/va416xx/va416xx/src/eth/dma_status.rs b/va416xx/va416xx/src/eth/dma_status.rs new file mode 100644 index 0000000..4d8347c --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_status.rs @@ -0,0 +1,153 @@ +#[doc = "Register `DMA_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TI` reader - Transmit Interrupt"] +pub type TiR = crate::BitReader; +#[doc = "Field `TPS` reader - Transmit Process Stopped"] +pub type TpsR = crate::BitReader; +#[doc = "Field `TU` reader - Transmit Buffer Unavailable"] +pub type TuR = crate::BitReader; +#[doc = "Field `TJT` reader - Transmit Jabber Timeout"] +pub type TjtR = crate::BitReader; +#[doc = "Field `OVF` reader - Receive Underflow"] +pub type OvfR = crate::BitReader; +#[doc = "Field `UNF` reader - Transmit Underflow"] +pub type UnfR = crate::BitReader; +#[doc = "Field `RI` reader - Receive Interrupt"] +pub type RiR = crate::BitReader; +#[doc = "Field `RU` reader - Receive Buffer Unavailable"] +pub type RuR = crate::BitReader; +#[doc = "Field `RPS` reader - Receive Process Stopped"] +pub type RpsR = crate::BitReader; +#[doc = "Field `RWT` reader - Receive Watchdog Timeout"] +pub type RwtR = crate::BitReader; +#[doc = "Field `ETI` reader - Early Transmit Interrupt"] +pub type EtiR = crate::BitReader; +#[doc = "Field `FBI` reader - Fatal Bus Error Interruptble"] +pub type FbiR = crate::BitReader; +#[doc = "Field `ERI` reader - Early Receive Interrupt"] +pub type EriR = crate::BitReader; +#[doc = "Field `AIS` reader - Abnormal Interrupt Summary"] +pub type AisR = crate::BitReader; +#[doc = "Field `NIS` reader - Normal Interrupt Summary"] +pub type NisR = crate::BitReader; +#[doc = "Field `RS` reader - Receive Process State"] +pub type RsR = crate::FieldReader; +#[doc = "Field `TS` reader - Transmit Process State"] +pub type TsR = crate::FieldReader; +#[doc = "Field `EB` reader - Error Bits"] +pub type EbR = crate::FieldReader; +#[doc = "Field `GMI` reader - GMAC MMC Interrupt"] +pub type GmiR = crate::BitReader; +#[doc = "Field `TTI` reader - Timestamp Trigger Interrupt"] +pub type TtiR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit Interrupt"] + #[inline(always)] + pub fn ti(&self) -> TiR { + TiR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Process Stopped"] + #[inline(always)] + pub fn tps(&self) -> TpsR { + TpsR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmit Buffer Unavailable"] + #[inline(always)] + pub fn tu(&self) -> TuR { + TuR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmit Jabber Timeout"] + #[inline(always)] + pub fn tjt(&self) -> TjtR { + TjtR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive Underflow"] + #[inline(always)] + pub fn ovf(&self) -> OvfR { + OvfR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit Underflow"] + #[inline(always)] + pub fn unf(&self) -> UnfR { + UnfR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Receive Interrupt"] + #[inline(always)] + pub fn ri(&self) -> RiR { + RiR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Receive Buffer Unavailable"] + #[inline(always)] + pub fn ru(&self) -> RuR { + RuR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Receive Process Stopped"] + #[inline(always)] + pub fn rps(&self) -> RpsR { + RpsR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Receive Watchdog Timeout"] + #[inline(always)] + pub fn rwt(&self) -> RwtR { + RwtR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Early Transmit Interrupt"] + #[inline(always)] + pub fn eti(&self) -> EtiR { + EtiR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - Fatal Bus Error Interruptble"] + #[inline(always)] + pub fn fbi(&self) -> FbiR { + FbiR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Early Receive Interrupt"] + #[inline(always)] + pub fn eri(&self) -> EriR { + EriR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Abnormal Interrupt Summary"] + #[inline(always)] + pub fn ais(&self) -> AisR { + AisR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Normal Interrupt Summary"] + #[inline(always)] + pub fn nis(&self) -> NisR { + NisR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - Receive Process State"] + #[inline(always)] + pub fn rs(&self) -> RsR { + RsR::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bits 20:22 - Transmit Process State"] + #[inline(always)] + pub fn ts(&self) -> TsR { + TsR::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bits 23:25 - Error Bits"] + #[inline(always)] + pub fn eb(&self) -> EbR { + EbR::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bit 27 - GMAC MMC Interrupt"] + #[inline(always)] + pub fn gmi(&self) -> GmiR { + GmiR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Timestamp Trigger Interrupt"] + #[inline(always)] + pub fn tti(&self) -> TtiR { + TtiR::new(((self.bits >> 29) & 1) != 0) + } +} +#[doc = "Used to determine the status of the DMA\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaStatusSpec; +impl crate::RegisterSpec for DmaStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_status::R`](R) reader structure"] +impl crate::Readable for DmaStatusSpec {} +#[doc = "`reset()` method sets DMA_STATUS to value 0"] +impl crate::Resettable for DmaStatusSpec {} diff --git a/va416xx/va416xx/src/eth/dma_tx_desc_list_addr.rs b/va416xx/va416xx/src/eth/dma_tx_desc_list_addr.rs new file mode 100644 index 0000000..6b84c66 --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_tx_desc_list_addr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_TX_DESC_LIST_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_TX_DESC_LIST_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `TDESLA` reader - Start of Transmit List"] +pub type TdeslaR = crate::FieldReader; +#[doc = "Field `TDESLA` writer - Start of Transmit List"] +pub type TdeslaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Start of Transmit List"] + #[inline(always)] + pub fn tdesla(&self) -> TdeslaR { + TdeslaR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Start of Transmit List"] + #[inline(always)] + pub fn tdesla(&mut self) -> TdeslaW<'_, DmaTxDescListAddrSpec> { + TdeslaW::new(self, 0) + } +} +#[doc = "Points the DMA to the start of the Transmit Descriptor list\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_tx_desc_list_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_tx_desc_list_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaTxDescListAddrSpec; +impl crate::RegisterSpec for DmaTxDescListAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_tx_desc_list_addr::R`](R) reader structure"] +impl crate::Readable for DmaTxDescListAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_tx_desc_list_addr::W`](W) writer structure"] +impl crate::Writable for DmaTxDescListAddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_TX_DESC_LIST_ADDR to value 0"] +impl crate::Resettable for DmaTxDescListAddrSpec {} diff --git a/va416xx/va416xx/src/eth/dma_tx_poll_demand.rs b/va416xx/va416xx/src/eth/dma_tx_poll_demand.rs new file mode 100644 index 0000000..c92083c --- /dev/null +++ b/va416xx/va416xx/src/eth/dma_tx_poll_demand.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMA_TX_POLL_DEMAND` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_TX_POLL_DEMAND` writer"] +pub type W = crate::W; +#[doc = "Field `TPD` reader - Transmit Poll Demand (Read Only and Write Trigger)"] +pub type TpdR = crate::FieldReader; +#[doc = "Field `TPD` writer - Transmit Poll Demand (Read Only and Write Trigger)"] +pub type TpdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Transmit Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn tpd(&self) -> TpdR { + TpdR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Transmit Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn tpd(&mut self) -> TpdW<'_, DmaTxPollDemandSpec> { + TpdW::new(self, 0) + } +} +#[doc = "Used by the host to instruct the DMA to poll the transmit Descriptor list\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_tx_poll_demand::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_tx_poll_demand::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaTxPollDemandSpec; +impl crate::RegisterSpec for DmaTxPollDemandSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_tx_poll_demand::R`](R) reader structure"] +impl crate::Readable for DmaTxPollDemandSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_tx_poll_demand::W`](W) writer structure"] +impl crate::Writable for DmaTxPollDemandSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMA_TX_POLL_DEMAND to value 0"] +impl crate::Resettable for DmaTxPollDemandSpec {} diff --git a/va416xx/va416xx/src/eth/mac_addr_h.rs b/va416xx/va416xx/src/eth/mac_addr_h.rs new file mode 100644 index 0000000..5361c93 --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_addr_h.rs @@ -0,0 +1,36 @@ +#[doc = "Register `MAC_ADDR_H` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_ADDR_H` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRHI` reader - MAC Address0\\[47:32\\]"] +pub type AddrhiR = crate::FieldReader; +#[doc = "Field `AE` reader - Address Enable, This bit is always set to 1"] +pub type AeR = crate::BitReader; +impl R { + #[doc = "Bits 0:15 - MAC Address0\\[47:32\\]"] + #[inline(always)] + pub fn addrhi(&self) -> AddrhiR { + AddrhiR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 31 - Address Enable, This bit is always set to 1"] + #[inline(always)] + pub fn ae(&self) -> AeR { + AeR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Contains the high 16-bits of the first MAC Address\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_addr_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_addr_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacAddrHSpec; +impl crate::RegisterSpec for MacAddrHSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_addr_h::R`](R) reader structure"] +impl crate::Readable for MacAddrHSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_addr_h::W`](W) writer structure"] +impl crate::Writable for MacAddrHSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_ADDR_H to value 0x8000_ffff"] +impl crate::Resettable for MacAddrHSpec { + const RESET_VALUE: u32 = 0x8000_ffff; +} diff --git a/va416xx/va416xx/src/eth/mac_addr_l.rs b/va416xx/va416xx/src/eth/mac_addr_l.rs new file mode 100644 index 0000000..d61cf88 --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_addr_l.rs @@ -0,0 +1,29 @@ +#[doc = "Register `MAC_ADDR_L` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_ADDR_L` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRLO` reader - MAC Address0\\[31:0\\]"] +pub type AddrloR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - MAC Address0\\[31:0\\]"] + #[inline(always)] + pub fn addrlo(&self) -> AddrloR { + AddrloR::new(self.bits) + } +} +impl W {} +#[doc = "Contains the Low 32-bits of the first MAC Address\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_addr_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_addr_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacAddrLSpec; +impl crate::RegisterSpec for MacAddrLSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_addr_l::R`](R) reader structure"] +impl crate::Readable for MacAddrLSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_addr_l::W`](W) writer structure"] +impl crate::Writable for MacAddrLSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_ADDR_L to value 0xffff_ffff"] +impl crate::Resettable for MacAddrLSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va416xx/va416xx/src/eth/mac_config.rs b/va416xx/va416xx/src/eth/mac_config.rs new file mode 100644 index 0000000..b22f1e3 --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_config.rs @@ -0,0 +1,287 @@ +#[doc = "Register `MAC_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `PRELEN` reader - Preamble Length for Transmit frames"] +pub type PrelenR = crate::FieldReader; +#[doc = "Field `PRELEN` writer - Preamble Length for Transmit frames"] +pub type PrelenW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RE` reader - Receiver Enable"] +pub type ReR = crate::BitReader; +#[doc = "Field `RE` writer - Receiver Enable"] +pub type ReW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TE` reader - Transmitter Enable"] +pub type TeR = crate::BitReader; +#[doc = "Field `TE` writer - Transmitter Enable"] +pub type TeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DC` reader - Deferral Check"] +pub type DcR = crate::BitReader; +#[doc = "Field `DC` writer - Deferral Check"] +pub type DcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BL` reader - Back-Off-Limit"] +pub type BlR = crate::FieldReader; +#[doc = "Field `BL` writer - Back-Off-Limit"] +pub type BlW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ACS` reader - Automatic Pad, or CRC Stripping"] +pub type AcsR = crate::BitReader; +#[doc = "Field `ACS` writer - Automatic Pad, or CRC Stripping"] +pub type AcsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DR` reader - Disable Retry"] +pub type DrR = crate::BitReader; +#[doc = "Field `DR` writer - Disable Retry"] +pub type DrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IPC` reader - Checksum Offload"] +pub type IpcR = crate::BitReader; +#[doc = "Field `IPC` writer - Checksum Offload"] +pub type IpcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM` reader - Duplex Mode"] +pub type DmR = crate::BitReader; +#[doc = "Field `DM` writer - Duplex Mode"] +pub type DmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LM` reader - Loopback Mode"] +pub type LmR = crate::BitReader; +#[doc = "Field `LM` writer - Loopback Mode"] +pub type LmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DRO` reader - Disable Receive Own"] +pub type DroR = crate::BitReader; +#[doc = "Field `DRO` writer - Disable Receive Own"] +pub type DroW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FES` reader - Speed"] +pub type FesR = crate::BitReader; +#[doc = "Field `FES` writer - Speed"] +pub type FesW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PS` reader - Port Select"] +pub type PsR = crate::BitReader; +#[doc = "Field `PS` writer - Port Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCRS` reader - Disable Carrier Sense During Transmission"] +pub type DcrsR = crate::BitReader; +#[doc = "Field `DCRS` writer - Disable Carrier Sense During Transmission"] +pub type DcrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IFG` reader - Inter-Frame Gap"] +pub type IfgR = crate::FieldReader; +#[doc = "Field `IFG` writer - Inter-Frame Gap"] +pub type IfgW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `JE` reader - Jumbo Frame Enable"] +pub type JeR = crate::BitReader; +#[doc = "Field `JE` writer - Jumbo Frame Enable"] +pub type JeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BE` reader - Frame Burst Enable"] +pub type BeR = crate::BitReader; +#[doc = "Field `BE` writer - Frame Burst Enable"] +pub type BeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JD` reader - Jabber Disable"] +pub type JdR = crate::BitReader; +#[doc = "Field `JD` writer - Jabber Disable"] +pub type JdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WD` reader - Watchdog disable"] +pub type WdR = crate::BitReader; +#[doc = "Field `WD` writer - Watchdog disable"] +pub type WdW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Preamble Length for Transmit frames"] + #[inline(always)] + pub fn prelen(&self) -> PrelenR { + PrelenR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Receiver Enable"] + #[inline(always)] + pub fn re(&self) -> ReR { + ReR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmitter Enable"] + #[inline(always)] + pub fn te(&self) -> TeR { + TeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Deferral Check"] + #[inline(always)] + pub fn dc(&self) -> DcR { + DcR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Back-Off-Limit"] + #[inline(always)] + pub fn bl(&self) -> BlR { + BlR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Automatic Pad, or CRC Stripping"] + #[inline(always)] + pub fn acs(&self) -> AcsR { + AcsR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Disable Retry"] + #[inline(always)] + pub fn dr(&self) -> DrR { + DrR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Checksum Offload"] + #[inline(always)] + pub fn ipc(&self) -> IpcR { + IpcR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Duplex Mode"] + #[inline(always)] + pub fn dm(&self) -> DmR { + DmR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Loopback Mode"] + #[inline(always)] + pub fn lm(&self) -> LmR { + LmR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Disable Receive Own"] + #[inline(always)] + pub fn dro(&self) -> DroR { + DroR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Speed"] + #[inline(always)] + pub fn fes(&self) -> FesR { + FesR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Port Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Disable Carrier Sense During Transmission"] + #[inline(always)] + pub fn dcrs(&self) -> DcrsR { + DcrsR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - Inter-Frame Gap"] + #[inline(always)] + pub fn ifg(&self) -> IfgR { + IfgR::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 20 - Jumbo Frame Enable"] + #[inline(always)] + pub fn je(&self) -> JeR { + JeR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Frame Burst Enable"] + #[inline(always)] + pub fn be(&self) -> BeR { + BeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Jabber Disable"] + #[inline(always)] + pub fn jd(&self) -> JdR { + JdR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Watchdog disable"] + #[inline(always)] + pub fn wd(&self) -> WdR { + WdR::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Preamble Length for Transmit frames"] + #[inline(always)] + pub fn prelen(&mut self) -> PrelenW<'_, MacConfigSpec> { + PrelenW::new(self, 0) + } + #[doc = "Bit 2 - Receiver Enable"] + #[inline(always)] + pub fn re(&mut self) -> ReW<'_, MacConfigSpec> { + ReW::new(self, 2) + } + #[doc = "Bit 3 - Transmitter Enable"] + #[inline(always)] + pub fn te(&mut self) -> TeW<'_, MacConfigSpec> { + TeW::new(self, 3) + } + #[doc = "Bit 4 - Deferral Check"] + #[inline(always)] + pub fn dc(&mut self) -> DcW<'_, MacConfigSpec> { + DcW::new(self, 4) + } + #[doc = "Bits 5:6 - Back-Off-Limit"] + #[inline(always)] + pub fn bl(&mut self) -> BlW<'_, MacConfigSpec> { + BlW::new(self, 5) + } + #[doc = "Bit 7 - Automatic Pad, or CRC Stripping"] + #[inline(always)] + pub fn acs(&mut self) -> AcsW<'_, MacConfigSpec> { + AcsW::new(self, 7) + } + #[doc = "Bit 9 - Disable Retry"] + #[inline(always)] + pub fn dr(&mut self) -> DrW<'_, MacConfigSpec> { + DrW::new(self, 9) + } + #[doc = "Bit 10 - Checksum Offload"] + #[inline(always)] + pub fn ipc(&mut self) -> IpcW<'_, MacConfigSpec> { + IpcW::new(self, 10) + } + #[doc = "Bit 11 - Duplex Mode"] + #[inline(always)] + pub fn dm(&mut self) -> DmW<'_, MacConfigSpec> { + DmW::new(self, 11) + } + #[doc = "Bit 12 - Loopback Mode"] + #[inline(always)] + pub fn lm(&mut self) -> LmW<'_, MacConfigSpec> { + LmW::new(self, 12) + } + #[doc = "Bit 13 - Disable Receive Own"] + #[inline(always)] + pub fn dro(&mut self) -> DroW<'_, MacConfigSpec> { + DroW::new(self, 13) + } + #[doc = "Bit 14 - Speed"] + #[inline(always)] + pub fn fes(&mut self) -> FesW<'_, MacConfigSpec> { + FesW::new(self, 14) + } + #[doc = "Bit 15 - Port Select"] + #[inline(always)] + pub fn ps(&mut self) -> PsW<'_, MacConfigSpec> { + PsW::new(self, 15) + } + #[doc = "Bit 16 - Disable Carrier Sense During Transmission"] + #[inline(always)] + pub fn dcrs(&mut self) -> DcrsW<'_, MacConfigSpec> { + DcrsW::new(self, 16) + } + #[doc = "Bits 17:19 - Inter-Frame Gap"] + #[inline(always)] + pub fn ifg(&mut self) -> IfgW<'_, MacConfigSpec> { + IfgW::new(self, 17) + } + #[doc = "Bit 20 - Jumbo Frame Enable"] + #[inline(always)] + pub fn je(&mut self) -> JeW<'_, MacConfigSpec> { + JeW::new(self, 20) + } + #[doc = "Bit 21 - Frame Burst Enable"] + #[inline(always)] + pub fn be(&mut self) -> BeW<'_, MacConfigSpec> { + BeW::new(self, 21) + } + #[doc = "Bit 22 - Jabber Disable"] + #[inline(always)] + pub fn jd(&mut self) -> JdW<'_, MacConfigSpec> { + JdW::new(self, 22) + } + #[doc = "Bit 23 - Watchdog disable"] + #[inline(always)] + pub fn wd(&mut self) -> WdW<'_, MacConfigSpec> { + WdW::new(self, 23) + } +} +#[doc = "Operation mode register for the MAC\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacConfigSpec; +impl crate::RegisterSpec for MacConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_config::R`](R) reader structure"] +impl crate::Readable for MacConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_config::W`](W) writer structure"] +impl crate::Writable for MacConfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_CONFIG to value 0"] +impl crate::Resettable for MacConfigSpec {} diff --git a/va416xx/va416xx/src/eth/mac_debug.rs b/va416xx/va416xx/src/eth/mac_debug.rs new file mode 100644 index 0000000..a05adcd --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_debug.rs @@ -0,0 +1,97 @@ +#[doc = "Register `MAC_DEBUG` reader"] +pub type R = crate::R; +#[doc = "Field `RPESTS` reader - MAC GMII or MII Receive Protocol Engine Status"] +pub type RpestsR = crate::BitReader; +#[doc = "Field `RFCFCSTS` reader - MAC Receive Frame FIFO Controller Status"] +pub type RfcfcstsR = crate::FieldReader; +#[doc = "Field `RWCSTS` reader - MTL Rx FIFO Write Controller Active Status"] +pub type RwcstsR = crate::BitReader; +#[doc = "Field `RRCSTS` reader - MTL RxFIFO Read Controller State"] +pub type RrcstsR = crate::FieldReader; +#[doc = "Field `RXFSTS` reader - MTL RxFIFO Fill-Level Status"] +pub type RxfstsR = crate::FieldReader; +#[doc = "Field `TPESTS` reader - MAC GMII or MII Transmit Protocol Engine Status"] +pub type TpestsR = crate::BitReader; +#[doc = "Field `TFCSTS` reader - PAC Transmit Frame Controller Status"] +pub type TfcstsR = crate::FieldReader; +#[doc = "Field `TXPAUSED` reader - MAC Transmitter in Pause"] +pub type TxpausedR = crate::BitReader; +#[doc = "Field `TRCSTS` reader - MTL Tx FIFO Read Controller Status"] +pub type TrcstsR = crate::FieldReader; +#[doc = "Field `TWCSTS` reader - MTL Tx FIFO Write Controller Status"] +pub type TwcstsR = crate::BitReader; +#[doc = "Field `TXFSTS` reader - MTL Tx FIFO Not Empty Status"] +pub type TxfstsR = crate::BitReader; +#[doc = "Field `TXSTSFSTS` reader - MTL TxStatus FIFO Full Status"] +pub type TxstsfstsR = crate::BitReader; +impl R { + #[doc = "Bit 0 - MAC GMII or MII Receive Protocol Engine Status"] + #[inline(always)] + pub fn rpests(&self) -> RpestsR { + RpestsR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - MAC Receive Frame FIFO Controller Status"] + #[inline(always)] + pub fn rfcfcsts(&self) -> RfcfcstsR { + RfcfcstsR::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 4 - MTL Rx FIFO Write Controller Active Status"] + #[inline(always)] + pub fn rwcsts(&self) -> RwcstsR { + RwcstsR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - MTL RxFIFO Read Controller State"] + #[inline(always)] + pub fn rrcsts(&self) -> RrcstsR { + RrcstsR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bits 8:9 - MTL RxFIFO Fill-Level Status"] + #[inline(always)] + pub fn rxfsts(&self) -> RxfstsR { + RxfstsR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 16 - MAC GMII or MII Transmit Protocol Engine Status"] + #[inline(always)] + pub fn tpests(&self) -> TpestsR { + TpestsR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:18 - PAC Transmit Frame Controller Status"] + #[inline(always)] + pub fn tfcsts(&self) -> TfcstsR { + TfcstsR::new(((self.bits >> 17) & 3) as u8) + } + #[doc = "Bit 19 - MAC Transmitter in Pause"] + #[inline(always)] + pub fn txpaused(&self) -> TxpausedR { + TxpausedR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:21 - MTL Tx FIFO Read Controller Status"] + #[inline(always)] + pub fn trcsts(&self) -> TrcstsR { + TrcstsR::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 22 - MTL Tx FIFO Write Controller Status"] + #[inline(always)] + pub fn twcsts(&self) -> TwcstsR { + TwcstsR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - MTL Tx FIFO Not Empty Status"] + #[inline(always)] + pub fn txfsts(&self) -> TxfstsR { + TxfstsR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MTL TxStatus FIFO Full Status"] + #[inline(always)] + pub fn txstsfsts(&self) -> TxstsfstsR { + TxstsfstsR::new(((self.bits >> 25) & 1) != 0) + } +} +#[doc = "Gives the status of the various internal blocks for debugging\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_debug::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacDebugSpec; +impl crate::RegisterSpec for MacDebugSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_debug::R`](R) reader structure"] +impl crate::Readable for MacDebugSpec {} +#[doc = "`reset()` method sets MAC_DEBUG to value 0"] +impl crate::Resettable for MacDebugSpec {} diff --git a/va416xx/va416xx/src/eth/mac_flow_ctrl.rs b/va416xx/va416xx/src/eth/mac_flow_ctrl.rs new file mode 100644 index 0000000..936830d --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_flow_ctrl.rs @@ -0,0 +1,119 @@ +#[doc = "Register `MAC_FLOW_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_FLOW_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `FCB_BPA` reader - Flow Control Busy or Backpressure Activate"] +pub type FcbBpaR = crate::BitReader; +#[doc = "Field `FCB_BPA` writer - Flow Control Busy or Backpressure Activate"] +pub type FcbBpaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TFE` reader - Transmit Flow Control Enable"] +pub type TfeR = crate::BitReader; +#[doc = "Field `TFE` writer - Transmit Flow Control Enable"] +pub type TfeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RFE` reader - Receive Flow Control Enable"] +pub type RfeR = crate::BitReader; +#[doc = "Field `RFE` writer - Receive Flow Control Enable"] +pub type RfeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UP` reader - Unicast Pause Frame Detect"] +pub type UpR = crate::BitReader; +#[doc = "Field `UP` writer - Unicast Pause Frame Detect"] +pub type UpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLT` reader - Pause Low Threshold"] +pub type PltR = crate::FieldReader; +#[doc = "Field `PLT` writer - Pause Low Threshold"] +pub type PltW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DZPQ` reader - Disable Zero-Quanta Pause"] +pub type DzpqR = crate::BitReader; +#[doc = "Field `DZPQ` writer - Disable Zero-Quanta Pause"] +pub type DzpqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PT` reader - Pause time"] +pub type PtR = crate::FieldReader; +#[doc = "Field `PT` writer - Pause time"] +pub type PtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - Flow Control Busy or Backpressure Activate"] + #[inline(always)] + pub fn fcb_bpa(&self) -> FcbBpaR { + FcbBpaR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Flow Control Enable"] + #[inline(always)] + pub fn tfe(&self) -> TfeR { + TfeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive Flow Control Enable"] + #[inline(always)] + pub fn rfe(&self) -> RfeR { + RfeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Unicast Pause Frame Detect"] + #[inline(always)] + pub fn up(&self) -> UpR { + UpR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Pause Low Threshold"] + #[inline(always)] + pub fn plt(&self) -> PltR { + PltR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 7 - Disable Zero-Quanta Pause"] + #[inline(always)] + pub fn dzpq(&self) -> DzpqR { + DzpqR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 16:31 - Pause time"] + #[inline(always)] + pub fn pt(&self) -> PtR { + PtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Flow Control Busy or Backpressure Activate"] + #[inline(always)] + pub fn fcb_bpa(&mut self) -> FcbBpaW<'_, MacFlowCtrlSpec> { + FcbBpaW::new(self, 0) + } + #[doc = "Bit 1 - Transmit Flow Control Enable"] + #[inline(always)] + pub fn tfe(&mut self) -> TfeW<'_, MacFlowCtrlSpec> { + TfeW::new(self, 1) + } + #[doc = "Bit 2 - Receive Flow Control Enable"] + #[inline(always)] + pub fn rfe(&mut self) -> RfeW<'_, MacFlowCtrlSpec> { + RfeW::new(self, 2) + } + #[doc = "Bit 3 - Unicast Pause Frame Detect"] + #[inline(always)] + pub fn up(&mut self) -> UpW<'_, MacFlowCtrlSpec> { + UpW::new(self, 3) + } + #[doc = "Bits 4:5 - Pause Low Threshold"] + #[inline(always)] + pub fn plt(&mut self) -> PltW<'_, MacFlowCtrlSpec> { + PltW::new(self, 4) + } + #[doc = "Bit 7 - Disable Zero-Quanta Pause"] + #[inline(always)] + pub fn dzpq(&mut self) -> DzpqW<'_, MacFlowCtrlSpec> { + DzpqW::new(self, 7) + } + #[doc = "Bits 16:31 - Pause time"] + #[inline(always)] + pub fn pt(&mut self) -> PtW<'_, MacFlowCtrlSpec> { + PtW::new(self, 16) + } +} +#[doc = "Controls the generation of control frames\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_flow_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_flow_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacFlowCtrlSpec; +impl crate::RegisterSpec for MacFlowCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_flow_ctrl::R`](R) reader structure"] +impl crate::Readable for MacFlowCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_flow_ctrl::W`](W) writer structure"] +impl crate::Writable for MacFlowCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_FLOW_CTRL to value 0"] +impl crate::Resettable for MacFlowCtrlSpec {} diff --git a/va416xx/va416xx/src/eth/mac_frame_fltr.rs b/va416xx/va416xx/src/eth/mac_frame_fltr.rs new file mode 100644 index 0000000..129d8f8 --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_frame_fltr.rs @@ -0,0 +1,203 @@ +#[doc = "Register `MAC_FRAME_FLTR` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_FRAME_FLTR` writer"] +pub type W = crate::W; +#[doc = "Field `PR` reader - Promiscuous Mode"] +pub type PrR = crate::BitReader; +#[doc = "Field `PR` writer - Promiscuous Mode"] +pub type PrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HUC` reader - Hash Unicast"] +pub type HucR = crate::BitReader; +#[doc = "Field `HUC` writer - Hash Unicast"] +pub type HucW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HMC` reader - Hash Multicast"] +pub type HmcR = crate::BitReader; +#[doc = "Field `HMC` writer - Hash Multicast"] +pub type HmcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DAIF` reader - DA Inverse Filtering"] +pub type DaifR = crate::BitReader; +#[doc = "Field `DAIF` writer - DA Inverse Filtering"] +pub type DaifW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PM` reader - Pass All Multicast"] +pub type PmR = crate::BitReader; +#[doc = "Field `PM` writer - Pass All Multicast"] +pub type PmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBF` reader - Disable Broadcast Frames"] +pub type DbfR = crate::BitReader; +#[doc = "Field `DBF` writer - Disable Broadcast Frames"] +pub type DbfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PCF` reader - Pass Control Frames"] +pub type PcfR = crate::FieldReader; +#[doc = "Field `PCF` writer - Pass Control Frames"] +pub type PcfW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SAIF` reader - SA Inverse Filtering"] +pub type SaifR = crate::BitReader; +#[doc = "Field `SAIF` writer - SA Inverse Filtering"] +pub type SaifW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAF` reader - Source Address Filter Enable"] +pub type SafR = crate::BitReader; +#[doc = "Field `SAF` writer - Source Address Filter Enable"] +pub type SafW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HDF` reader - Hash or Perfect Filter"] +pub type HdfR = crate::BitReader; +#[doc = "Field `HDF` writer - Hash or Perfect Filter"] +pub type HdfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VFTE` reader - VLAN Tag Filter Enable"] +pub type VfteR = crate::BitReader; +#[doc = "Field `VFTE` writer - VLAN Tag Filter Enable"] +pub type VfteW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DNTU` reader - Drop non TCP/UDP over IP Frames"] +pub type DntuR = crate::BitReader; +#[doc = "Field `DNTU` writer - Drop non TCP/UDP over IP Frames"] +pub type DntuW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RA` reader - Receive All"] +pub type RaR = crate::BitReader; +#[doc = "Field `RA` writer - Receive All"] +pub type RaW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Promiscuous Mode"] + #[inline(always)] + pub fn pr(&self) -> PrR { + PrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Hash Unicast"] + #[inline(always)] + pub fn huc(&self) -> HucR { + HucR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Hash Multicast"] + #[inline(always)] + pub fn hmc(&self) -> HmcR { + HmcR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DA Inverse Filtering"] + #[inline(always)] + pub fn daif(&self) -> DaifR { + DaifR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pass All Multicast"] + #[inline(always)] + pub fn pm(&self) -> PmR { + PmR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Disable Broadcast Frames"] + #[inline(always)] + pub fn dbf(&self) -> DbfR { + DbfR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Pass Control Frames"] + #[inline(always)] + pub fn pcf(&self) -> PcfR { + PcfR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - SA Inverse Filtering"] + #[inline(always)] + pub fn saif(&self) -> SaifR { + SaifR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Source Address Filter Enable"] + #[inline(always)] + pub fn saf(&self) -> SafR { + SafR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Hash or Perfect Filter"] + #[inline(always)] + pub fn hdf(&self) -> HdfR { + HdfR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 16 - VLAN Tag Filter Enable"] + #[inline(always)] + pub fn vfte(&self) -> VfteR { + VfteR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 21 - Drop non TCP/UDP over IP Frames"] + #[inline(always)] + pub fn dntu(&self) -> DntuR { + DntuR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 31 - Receive All"] + #[inline(always)] + pub fn ra(&self) -> RaR { + RaR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Promiscuous Mode"] + #[inline(always)] + pub fn pr(&mut self) -> PrW<'_, MacFrameFltrSpec> { + PrW::new(self, 0) + } + #[doc = "Bit 1 - Hash Unicast"] + #[inline(always)] + pub fn huc(&mut self) -> HucW<'_, MacFrameFltrSpec> { + HucW::new(self, 1) + } + #[doc = "Bit 2 - Hash Multicast"] + #[inline(always)] + pub fn hmc(&mut self) -> HmcW<'_, MacFrameFltrSpec> { + HmcW::new(self, 2) + } + #[doc = "Bit 3 - DA Inverse Filtering"] + #[inline(always)] + pub fn daif(&mut self) -> DaifW<'_, MacFrameFltrSpec> { + DaifW::new(self, 3) + } + #[doc = "Bit 4 - Pass All Multicast"] + #[inline(always)] + pub fn pm(&mut self) -> PmW<'_, MacFrameFltrSpec> { + PmW::new(self, 4) + } + #[doc = "Bit 5 - Disable Broadcast Frames"] + #[inline(always)] + pub fn dbf(&mut self) -> DbfW<'_, MacFrameFltrSpec> { + DbfW::new(self, 5) + } + #[doc = "Bits 6:7 - Pass Control Frames"] + #[inline(always)] + pub fn pcf(&mut self) -> PcfW<'_, MacFrameFltrSpec> { + PcfW::new(self, 6) + } + #[doc = "Bit 8 - SA Inverse Filtering"] + #[inline(always)] + pub fn saif(&mut self) -> SaifW<'_, MacFrameFltrSpec> { + SaifW::new(self, 8) + } + #[doc = "Bit 9 - Source Address Filter Enable"] + #[inline(always)] + pub fn saf(&mut self) -> SafW<'_, MacFrameFltrSpec> { + SafW::new(self, 9) + } + #[doc = "Bit 10 - Hash or Perfect Filter"] + #[inline(always)] + pub fn hdf(&mut self) -> HdfW<'_, MacFrameFltrSpec> { + HdfW::new(self, 10) + } + #[doc = "Bit 16 - VLAN Tag Filter Enable"] + #[inline(always)] + pub fn vfte(&mut self) -> VfteW<'_, MacFrameFltrSpec> { + VfteW::new(self, 16) + } + #[doc = "Bit 21 - Drop non TCP/UDP over IP Frames"] + #[inline(always)] + pub fn dntu(&mut self) -> DntuW<'_, MacFrameFltrSpec> { + DntuW::new(self, 21) + } + #[doc = "Bit 31 - Receive All"] + #[inline(always)] + pub fn ra(&mut self) -> RaW<'_, MacFrameFltrSpec> { + RaW::new(self, 31) + } +} +#[doc = "Contains the frame filtering controls\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_frame_fltr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_frame_fltr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacFrameFltrSpec; +impl crate::RegisterSpec for MacFrameFltrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_frame_fltr::R`](R) reader structure"] +impl crate::Readable for MacFrameFltrSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_frame_fltr::W`](W) writer structure"] +impl crate::Writable for MacFrameFltrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_FRAME_FLTR to value 0"] +impl crate::Resettable for MacFrameFltrSpec {} diff --git a/va416xx/va416xx/src/eth/mac_gmii_addr.rs b/va416xx/va416xx/src/eth/mac_gmii_addr.rs new file mode 100644 index 0000000..afae52c --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_gmii_addr.rs @@ -0,0 +1,91 @@ +#[doc = "Register `MAC_GMII_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_GMII_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `GB` reader - GMII Busy"] +pub type GbR = crate::BitReader; +#[doc = "Field `GB` writer - GMII Busy"] +pub type GbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GW` reader - GMII Write/Read"] +pub type GwR = crate::BitReader; +#[doc = "Field `GW` writer - GMII Write/Read"] +pub type GwW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR` reader - CSR Clock Range"] +pub type CrR = crate::FieldReader; +#[doc = "Field `CR` writer - CSR Clock Range"] +pub type CrW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GR` reader - GMII Register"] +pub type GrR = crate::FieldReader; +#[doc = "Field `GR` writer - GMII Register"] +pub type GrW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PA` reader - Physical Layer Address"] +pub type PaR = crate::FieldReader; +#[doc = "Field `PA` writer - Physical Layer Address"] +pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 0 - GMII Busy"] + #[inline(always)] + pub fn gb(&self) -> GbR { + GbR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - GMII Write/Read"] + #[inline(always)] + pub fn gw(&self) -> GwR { + GwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - CSR Clock Range"] + #[inline(always)] + pub fn cr(&self) -> CrR { + CrR::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bits 6:10 - GMII Register"] + #[inline(always)] + pub fn gr(&self) -> GrR { + GrR::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 11:15 - Physical Layer Address"] + #[inline(always)] + pub fn pa(&self) -> PaR { + PaR::new(((self.bits >> 11) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bit 0 - GMII Busy"] + #[inline(always)] + pub fn gb(&mut self) -> GbW<'_, MacGmiiAddrSpec> { + GbW::new(self, 0) + } + #[doc = "Bit 1 - GMII Write/Read"] + #[inline(always)] + pub fn gw(&mut self) -> GwW<'_, MacGmiiAddrSpec> { + GwW::new(self, 1) + } + #[doc = "Bits 2:5 - CSR Clock Range"] + #[inline(always)] + pub fn cr(&mut self) -> CrW<'_, MacGmiiAddrSpec> { + CrW::new(self, 2) + } + #[doc = "Bits 6:10 - GMII Register"] + #[inline(always)] + pub fn gr(&mut self) -> GrW<'_, MacGmiiAddrSpec> { + GrW::new(self, 6) + } + #[doc = "Bits 11:15 - Physical Layer Address"] + #[inline(always)] + pub fn pa(&mut self) -> PaW<'_, MacGmiiAddrSpec> { + PaW::new(self, 11) + } +} +#[doc = "Controls the management cycles to an external PHY\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_gmii_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_gmii_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacGmiiAddrSpec; +impl crate::RegisterSpec for MacGmiiAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_gmii_addr::R`](R) reader structure"] +impl crate::Readable for MacGmiiAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_gmii_addr::W`](W) writer structure"] +impl crate::Writable for MacGmiiAddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_GMII_ADDR to value 0"] +impl crate::Resettable for MacGmiiAddrSpec {} diff --git a/va416xx/va416xx/src/eth/mac_gmii_data.rs b/va416xx/va416xx/src/eth/mac_gmii_data.rs new file mode 100644 index 0000000..2eaa09a --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_gmii_data.rs @@ -0,0 +1,35 @@ +#[doc = "Register `MAC_GMII_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_GMII_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `GD` reader - GMII Data"] +pub type GdR = crate::FieldReader; +#[doc = "Field `GD` writer - GMII Data"] +pub type GdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - GMII Data"] + #[inline(always)] + pub fn gd(&self) -> GdR { + GdR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - GMII Data"] + #[inline(always)] + pub fn gd(&mut self) -> GdW<'_, MacGmiiDataSpec> { + GdW::new(self, 0) + } +} +#[doc = "Contains the data to be written to or read from the PHY register\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_gmii_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_gmii_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacGmiiDataSpec; +impl crate::RegisterSpec for MacGmiiDataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_gmii_data::R`](R) reader structure"] +impl crate::Readable for MacGmiiDataSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_gmii_data::W`](W) writer structure"] +impl crate::Writable for MacGmiiDataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_GMII_DATA to value 0"] +impl crate::Resettable for MacGmiiDataSpec {} diff --git a/va416xx/va416xx/src/eth/mac_intr_mask.rs b/va416xx/va416xx/src/eth/mac_intr_mask.rs new file mode 100644 index 0000000..6518846 --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_intr_mask.rs @@ -0,0 +1,35 @@ +#[doc = "Register `MAC_INTR_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_INTR_MASK` writer"] +pub type W = crate::W; +#[doc = "Field `TSIM` reader - Timestamp Interrupt Mask"] +pub type TsimR = crate::BitReader; +#[doc = "Field `TSIM` writer - Timestamp Interrupt Mask"] +pub type TsimW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 9 - Timestamp Interrupt Mask"] + #[inline(always)] + pub fn tsim(&self) -> TsimR { + TsimR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 9 - Timestamp Interrupt Mask"] + #[inline(always)] + pub fn tsim(&mut self) -> TsimW<'_, MacIntrMaskSpec> { + TsimW::new(self, 9) + } +} +#[doc = "Contains the masks for generating interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_intr_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_intr_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacIntrMaskSpec; +impl crate::RegisterSpec for MacIntrMaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_intr_mask::R`](R) reader structure"] +impl crate::Readable for MacIntrMaskSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_intr_mask::W`](W) writer structure"] +impl crate::Writable for MacIntrMaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_INTR_MASK to value 0"] +impl crate::Resettable for MacIntrMaskSpec {} diff --git a/va416xx/va416xx/src/eth/mac_intr_stat.rs b/va416xx/va416xx/src/eth/mac_intr_stat.rs new file mode 100644 index 0000000..cdbab41 --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_intr_stat.rs @@ -0,0 +1,48 @@ +#[doc = "Register `MAC_INTR_STAT` reader"] +pub type R = crate::R; +#[doc = "Field `MMCIS` reader - MMC Interrupt Status"] +pub type MmcisR = crate::BitReader; +#[doc = "Field `MMCRXIS` reader - MMC Receive Interrupt Status"] +pub type MmcrxisR = crate::BitReader; +#[doc = "Field `MMCTXIS` reader - MMC Transmit Interrupt Status"] +pub type MmctxisR = crate::BitReader; +#[doc = "Field `MMCRXIPIS` reader - MMC Receive Checksum Offload Interrupt Status"] +pub type MmcrxipisR = crate::BitReader; +#[doc = "Field `TSIS` reader - Timestamp Interrupt Status"] +pub type TsisR = crate::BitReader; +impl R { + #[doc = "Bit 4 - MMC Interrupt Status"] + #[inline(always)] + pub fn mmcis(&self) -> MmcisR { + MmcisR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Receive Interrupt Status"] + #[inline(always)] + pub fn mmcrxis(&self) -> MmcrxisR { + MmcrxisR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Transmit Interrupt Status"] + #[inline(always)] + pub fn mmctxis(&self) -> MmctxisR { + MmctxisR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MMC Receive Checksum Offload Interrupt Status"] + #[inline(always)] + pub fn mmcrxipis(&self) -> MmcrxipisR { + MmcrxipisR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Timestamp Interrupt Status"] + #[inline(always)] + pub fn tsis(&self) -> TsisR { + TsisR::new(((self.bits >> 9) & 1) != 0) + } +} +#[doc = "Contains the interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacIntrStatSpec; +impl crate::RegisterSpec for MacIntrStatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_intr_stat::R`](R) reader structure"] +impl crate::Readable for MacIntrStatSpec {} +#[doc = "`reset()` method sets MAC_INTR_STAT to value 0"] +impl crate::Resettable for MacIntrStatSpec {} diff --git a/va416xx/va416xx/src/eth/mac_vlan_tag.rs b/va416xx/va416xx/src/eth/mac_vlan_tag.rs new file mode 100644 index 0000000..c9fe835 --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_vlan_tag.rs @@ -0,0 +1,77 @@ +#[doc = "Register `MAC_VLAN_TAG` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_VLAN_TAG` writer"] +pub type W = crate::W; +#[doc = "Field `VL` reader - VLAN Tag identifier for Receive Frames"] +pub type VlR = crate::FieldReader; +#[doc = "Field `VL` writer - VLAN Tag identifier for Receive Frames"] +pub type VlW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `ETV` reader - Enable 12-Bit VLAN Tag Comparison"] +pub type EtvR = crate::BitReader; +#[doc = "Field `ETV` writer - Enable 12-Bit VLAN Tag Comparison"] +pub type EtvW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VTIM` reader - VLAN Tag Inverse Match Enable"] +pub type VtimR = crate::BitReader; +#[doc = "Field `VTIM` writer - VLAN Tag Inverse Match Enable"] +pub type VtimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ESVL` reader - Enable S-VLAN"] +pub type EsvlR = crate::BitReader; +#[doc = "Field `ESVL` writer - Enable S-VLAN"] +pub type EsvlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - VLAN Tag identifier for Receive Frames"] + #[inline(always)] + pub fn vl(&self) -> VlR { + VlR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison"] + #[inline(always)] + pub fn etv(&self) -> EtvR { + EtvR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - VLAN Tag Inverse Match Enable"] + #[inline(always)] + pub fn vtim(&self) -> VtimR { + VtimR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable S-VLAN"] + #[inline(always)] + pub fn esvl(&self) -> EsvlR { + EsvlR::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - VLAN Tag identifier for Receive Frames"] + #[inline(always)] + pub fn vl(&mut self) -> VlW<'_, MacVlanTagSpec> { + VlW::new(self, 0) + } + #[doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison"] + #[inline(always)] + pub fn etv(&mut self) -> EtvW<'_, MacVlanTagSpec> { + EtvW::new(self, 16) + } + #[doc = "Bit 17 - VLAN Tag Inverse Match Enable"] + #[inline(always)] + pub fn vtim(&mut self) -> VtimW<'_, MacVlanTagSpec> { + VtimW::new(self, 17) + } + #[doc = "Bit 18 - Enable S-VLAN"] + #[inline(always)] + pub fn esvl(&mut self) -> EsvlW<'_, MacVlanTagSpec> { + EsvlW::new(self, 18) + } +} +#[doc = "Identifies IEEE 802.1Q VLAN type frames\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_vlan_tag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_vlan_tag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacVlanTagSpec; +impl crate::RegisterSpec for MacVlanTagSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_vlan_tag::R`](R) reader structure"] +impl crate::Readable for MacVlanTagSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_vlan_tag::W`](W) writer structure"] +impl crate::Writable for MacVlanTagSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_VLAN_TAG to value 0"] +impl crate::Resettable for MacVlanTagSpec {} diff --git a/va416xx/va416xx/src/eth/mac_wdog_to.rs b/va416xx/va416xx/src/eth/mac_wdog_to.rs new file mode 100644 index 0000000..d2fa569 --- /dev/null +++ b/va416xx/va416xx/src/eth/mac_wdog_to.rs @@ -0,0 +1,49 @@ +#[doc = "Register `MAC_WDOG_TO` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_WDOG_TO` writer"] +pub type W = crate::W; +#[doc = "Field `WTO` reader - Watchdog Timeout"] +pub type WtoR = crate::FieldReader; +#[doc = "Field `WTO` writer - Watchdog Timeout"] +pub type WtoW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `PWE` reader - Programmable Watchdog Enable"] +pub type PweR = crate::BitReader; +#[doc = "Field `PWE` writer - Programmable Watchdog Enable"] +pub type PweW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Watchdog Timeout"] + #[inline(always)] + pub fn wto(&self) -> WtoR { + WtoR::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 16 - Programmable Watchdog Enable"] + #[inline(always)] + pub fn pwe(&self) -> PweR { + PweR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:13 - Watchdog Timeout"] + #[inline(always)] + pub fn wto(&mut self) -> WtoW<'_, MacWdogToSpec> { + WtoW::new(self, 0) + } + #[doc = "Bit 16 - Programmable Watchdog Enable"] + #[inline(always)] + pub fn pwe(&mut self) -> PweW<'_, MacWdogToSpec> { + PweW::new(self, 16) + } +} +#[doc = "Controls the watchdog time-out for received frames\n\nYou can [`read`](crate::Reg::read) this register and get [`mac_wdog_to::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac_wdog_to::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacWdogToSpec; +impl crate::RegisterSpec for MacWdogToSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_wdog_to::R`](R) reader structure"] +impl crate::Readable for MacWdogToSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_wdog_to::W`](W) writer structure"] +impl crate::Writable for MacWdogToSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MAC_WDOG_TO to value 0"] +impl crate::Resettable for MacWdogToSpec {} diff --git a/va416xx/va416xx/src/eth/mmc_cntrl.rs b/va416xx/va416xx/src/eth/mmc_cntrl.rs new file mode 100644 index 0000000..6238948 --- /dev/null +++ b/va416xx/va416xx/src/eth/mmc_cntrl.rs @@ -0,0 +1,119 @@ +#[doc = "Register `MMC_CNTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_CNTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CNTRST` reader - Counters Reset"] +pub type CntrstR = crate::BitReader; +#[doc = "Field `CNTRST` writer - Counters Reset"] +pub type CntrstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNTSTOPRO` reader - Counter Stop Rollover"] +pub type CntstoproR = crate::BitReader; +#[doc = "Field `CNTSTOPRO` writer - Counter Stop Rollover"] +pub type CntstoproW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSTONRD` reader - Reset on Read"] +pub type RstonrdR = crate::BitReader; +#[doc = "Field `RSTONRD` writer - Reset on Read"] +pub type RstonrdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNTFREEZ` reader - MMC Counter Freeze"] +pub type CntfreezR = crate::BitReader; +#[doc = "Field `CNTFREEZ` writer - MMC Counter Freeze"] +pub type CntfreezW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNTPRST` reader - Counters Preset"] +pub type CntprstR = crate::BitReader; +#[doc = "Field `CNTPRST` writer - Counters Preset"] +pub type CntprstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNTPRSTLVL` reader - Full-Half Preset"] +pub type CntprstlvlR = crate::BitReader; +#[doc = "Field `CNTPRSTLVL` writer - Full-Half Preset"] +pub type CntprstlvlW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UCDBC` reader - Update MMC Counters for Dropped Broadcast Frames"] +pub type UcdbcR = crate::BitReader; +#[doc = "Field `UCDBC` writer - Update MMC Counters for Dropped Broadcast Frames"] +pub type UcdbcW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Counters Reset"] + #[inline(always)] + pub fn cntrst(&self) -> CntrstR { + CntrstR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Counter Stop Rollover"] + #[inline(always)] + pub fn cntstopro(&self) -> CntstoproR { + CntstoproR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reset on Read"] + #[inline(always)] + pub fn rstonrd(&self) -> RstonrdR { + RstonrdR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Counter Freeze"] + #[inline(always)] + pub fn cntfreez(&self) -> CntfreezR { + CntfreezR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Counters Preset"] + #[inline(always)] + pub fn cntprst(&self) -> CntprstR { + CntprstR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Full-Half Preset"] + #[inline(always)] + pub fn cntprstlvl(&self) -> CntprstlvlR { + CntprstlvlR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Update MMC Counters for Dropped Broadcast Frames"] + #[inline(always)] + pub fn ucdbc(&self) -> UcdbcR { + UcdbcR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counters Reset"] + #[inline(always)] + pub fn cntrst(&mut self) -> CntrstW<'_, MmcCntrlSpec> { + CntrstW::new(self, 0) + } + #[doc = "Bit 1 - Counter Stop Rollover"] + #[inline(always)] + pub fn cntstopro(&mut self) -> CntstoproW<'_, MmcCntrlSpec> { + CntstoproW::new(self, 1) + } + #[doc = "Bit 2 - Reset on Read"] + #[inline(always)] + pub fn rstonrd(&mut self) -> RstonrdW<'_, MmcCntrlSpec> { + RstonrdW::new(self, 2) + } + #[doc = "Bit 3 - MMC Counter Freeze"] + #[inline(always)] + pub fn cntfreez(&mut self) -> CntfreezW<'_, MmcCntrlSpec> { + CntfreezW::new(self, 3) + } + #[doc = "Bit 4 - Counters Preset"] + #[inline(always)] + pub fn cntprst(&mut self) -> CntprstW<'_, MmcCntrlSpec> { + CntprstW::new(self, 4) + } + #[doc = "Bit 5 - Full-Half Preset"] + #[inline(always)] + pub fn cntprstlvl(&mut self) -> CntprstlvlW<'_, MmcCntrlSpec> { + CntprstlvlW::new(self, 5) + } + #[doc = "Bit 8 - Update MMC Counters for Dropped Broadcast Frames"] + #[inline(always)] + pub fn ucdbc(&mut self) -> UcdbcW<'_, MmcCntrlSpec> { + UcdbcW::new(self, 8) + } +} +#[doc = "MMC Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_cntrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_cntrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcCntrlSpec; +impl crate::RegisterSpec for MmcCntrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_cntrl::R`](R) reader structure"] +impl crate::Readable for MmcCntrlSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_cntrl::W`](W) writer structure"] +impl crate::Writable for MmcCntrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MMC_CNTRL to value 0"] +impl crate::Resettable for MmcCntrlSpec {} diff --git a/va416xx/va416xx/src/eth/mmc_intr_mask_rx.rs b/va416xx/va416xx/src/eth/mmc_intr_mask_rx.rs new file mode 100644 index 0000000..8a4418f --- /dev/null +++ b/va416xx/va416xx/src/eth/mmc_intr_mask_rx.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MMC_INTR_MASK_RX` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_INTR_MASK_RX` writer"] +pub type W = crate::W; +#[doc = "Field `RXGBFRMIM` reader - MMC Receive Good Bad Frame Counter Interrupt Mask"] +pub type RxgbfrmimR = crate::BitReader; +#[doc = "Field `RXGBFRMIM` writer - MMC Receive Good Bad Frame Counter Interrupt Mask"] +pub type RxgbfrmimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXGBOCTIM` reader - MMC Receive Good Bad Octet Counter Interrupt Mask."] +pub type RxgboctimR = crate::BitReader; +#[doc = "Field `RXGBOCTIM` writer - MMC Receive Good Bad Octet Counter Interrupt Mask."] +pub type RxgboctimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXGOCTIM` reader - MMC Receive Good Octet Counter Interrupt Mask"] +pub type RxgoctimR = crate::BitReader; +#[doc = "Field `RXGOCTIM` writer - MMC Receive Good Octet Counter Interrupt Mask"] +pub type RxgoctimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXBCGFIM` reader - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] +pub type RxbcgfimR = crate::BitReader; +#[doc = "Field `RXBCGFIM` writer - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] +pub type RxbcgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXMCGFIM` reader - MMC Receive Multicast Good Frame Counter Interrupt Mask"] +pub type RxmcgfimR = crate::BitReader; +#[doc = "Field `RXMCGFIM` writer - MMC Receive Multicast Good Frame Counter Interrupt Mask"] +pub type RxmcgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXCRCERFIM` reader - MMC Receive CRC Error Frame Counter Interrupt Mask"] +pub type RxcrcerfimR = crate::BitReader; +#[doc = "Field `RXCRCERFIM` writer - MMC Receive CRC Error Frame Counter Interrupt Mask"] +pub type RxcrcerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXALGNERFIM` reader - MMC Receive Alignment Error Frame Counter Interrupt Mask"] +pub type RxalgnerfimR = crate::BitReader; +#[doc = "Field `RXALGNERFIM` writer - MMC Receive Alignment Error Frame Counter Interrupt Mask"] +pub type RxalgnerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXRUNTFIM` reader - MMC Receive Runt Frame Counter Interrupt Mask"] +pub type RxruntfimR = crate::BitReader; +#[doc = "Field `RXRUNTFIM` writer - MMC Receive Runt Frame Counter Interrupt Mask"] +pub type RxruntfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXJABERFIM` reader - MMC Receive Jabber Error Frame Counter Interrupt Mask"] +pub type RxjaberfimR = crate::BitReader; +#[doc = "Field `RXJABERFIM` writer - MMC Receive Jabber Error Frame Counter Interrupt Mask"] +pub type RxjaberfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXUSIZEGFIM` reader - MMC Receive Undersize Good Frame Counter Interrupt Mask"] +pub type RxusizegfimR = crate::BitReader; +#[doc = "Field `RXUSIZEGFIM` writer - MMC Receive Undersize Good Frame Counter Interrupt Mask"] +pub type RxusizegfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOSIZEGFIM` reader - MMC Receive Oversize Good Frame Counter Interrupt Mask"] +pub type RxosizegfimR = crate::BitReader; +#[doc = "Field `RXOSIZEGFIM` writer - MMC Receive Oversize Good Frame Counter Interrupt Mask"] +pub type RxosizegfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX64OCTGBFIM` reader - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx64octgbfimR = crate::BitReader; +#[doc = "Field `RX64OCTGBFIM` writer - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx64octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX65T127OCTGBFIM` reader - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx65t127octgbfimR = crate::BitReader; +#[doc = "Field `RX65T127OCTGBFIM` writer - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx65t127octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX128T255OCTGBFIM` reader - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx128t255octgbfimR = crate::BitReader; +#[doc = "Field `RX128T255OCTGBFIM` writer - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx128t255octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX256T511OCTGBFIM` reader - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx256t511octgbfimR = crate::BitReader; +#[doc = "Field `RX256T511OCTGBFIM` writer - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx256t511octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX512T1023OCTGBFIM` reader - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx512t1023octgbfimR = crate::BitReader; +#[doc = "Field `RX512T1023OCTGBFIM` writer - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx512t1023octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX1024TMAXOCTGBFIM` reader - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] +pub type Rx1024tmaxoctgbfimR = crate::BitReader; +#[doc = "Field `RX1024TMAXOCTGBFIM` writer - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] +pub type Rx1024tmaxoctgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXUCGFIM` reader - MMC Receive Unicast Good Frame Counter Interrupt Mask"] +pub type RxucgfimR = crate::BitReader; +#[doc = "Field `RXUCGFIM` writer - MMC Receive Unicast Good Frame Counter Interrupt Mask"] +pub type RxucgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXLENERFIM` reader - MMC Receive Length Error Frame Counter Interrupt Mask"] +pub type RxlenerfimR = crate::BitReader; +#[doc = "Field `RXLENERFIM` writer - MMC Receive Length Error Frame Counter Interrupt Mask"] +pub type RxlenerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXORANGEFIM` reader - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] +pub type RxorangefimR = crate::BitReader; +#[doc = "Field `RXORANGEFIM` writer - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] +pub type RxorangefimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXPAUSFIM` reader - MMC Receive Pause Frame Counter Interrupt Mask"] +pub type RxpausfimR = crate::BitReader; +#[doc = "Field `RXPAUSFIM` writer - MMC Receive Pause Frame Counter Interrupt Mask"] +pub type RxpausfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFOVFIM` reader - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] +pub type RxfovfimR = crate::BitReader; +#[doc = "Field `RXFOVFIM` writer - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] +pub type RxfovfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXVLANGBFIM` reader - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] +pub type RxvlangbfimR = crate::BitReader; +#[doc = "Field `RXVLANGBFIM` writer - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] +pub type RxvlangbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXWDOGFIM` reader - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] +pub type RxwdogfimR = crate::BitReader; +#[doc = "Field `RXWDOGFIM` writer - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] +pub type RxwdogfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXRCVERRFIM` reader - MMC Receive Error Frame Counter Interrupt Mask"] +pub type RxrcverrfimR = crate::BitReader; +#[doc = "Field `RXRCVERRFIM` writer - MMC Receive Error Frame Counter Interrupt Mask"] +pub type RxrcverrfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXCTRLFIM` reader - MMC Receive Control Frame Counter Interrupt Mask"] +pub type RxctrlfimR = crate::BitReader; +#[doc = "Field `RXCTRLFIM` writer - MMC Receive Control Frame Counter Interrupt Mask"] +pub type RxctrlfimW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgbfrmim(&self) -> RxgbfrmimR { + RxgbfrmimR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Mask."] + #[inline(always)] + pub fn rxgboctim(&self) -> RxgboctimR { + RxgboctimR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgoctim(&self) -> RxgoctimR { + RxgoctimR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxbcgfim(&self) -> RxbcgfimR { + RxbcgfimR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxmcgfim(&self) -> RxmcgfimR { + RxmcgfimR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxcrcerfim(&self) -> RxcrcerfimR { + RxcrcerfimR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxalgnerfim(&self) -> RxalgnerfimR { + RxalgnerfimR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxruntfim(&self) -> RxruntfimR { + RxruntfimR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxjaberfim(&self) -> RxjaberfimR { + RxjaberfimR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxusizegfim(&self) -> RxusizegfimR { + RxusizegfimR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxosizegfim(&self) -> RxosizegfimR { + RxosizegfimR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx64octgbfim(&self) -> Rx64octgbfimR { + Rx64octgbfimR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx65t127octgbfim(&self) -> Rx65t127octgbfimR { + Rx65t127octgbfimR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx128t255octgbfim(&self) -> Rx128t255octgbfimR { + Rx128t255octgbfimR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx256t511octgbfim(&self) -> Rx256t511octgbfimR { + Rx256t511octgbfimR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx512t1023octgbfim(&self) -> Rx512t1023octgbfimR { + Rx512t1023octgbfimR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] + #[inline(always)] + pub fn rx1024tmaxoctgbfim(&self) -> Rx1024tmaxoctgbfimR { + Rx1024tmaxoctgbfimR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxucgfim(&self) -> RxucgfimR { + RxucgfimR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxlenerfim(&self) -> RxlenerfimR { + RxlenerfimR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxorangefim(&self) -> RxorangefimR { + RxorangefimR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxpausfim(&self) -> RxpausfimR { + RxpausfimR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxfovfim(&self) -> RxfovfimR { + RxfovfimR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxvlangbfim(&self) -> RxvlangbfimR { + RxvlangbfimR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxwdogfim(&self) -> RxwdogfimR { + RxwdogfimR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxrcverrfim(&self) -> RxrcverrfimR { + RxrcverrfimR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxctrlfim(&self) -> RxctrlfimR { + RxctrlfimR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgbfrmim(&mut self) -> RxgbfrmimW<'_, MmcIntrMaskRxSpec> { + RxgbfrmimW::new(self, 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Mask."] + #[inline(always)] + pub fn rxgboctim(&mut self) -> RxgboctimW<'_, MmcIntrMaskRxSpec> { + RxgboctimW::new(self, 1) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgoctim(&mut self) -> RxgoctimW<'_, MmcIntrMaskRxSpec> { + RxgoctimW::new(self, 2) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxbcgfim(&mut self) -> RxbcgfimW<'_, MmcIntrMaskRxSpec> { + RxbcgfimW::new(self, 3) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxmcgfim(&mut self) -> RxmcgfimW<'_, MmcIntrMaskRxSpec> { + RxmcgfimW::new(self, 4) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxcrcerfim(&mut self) -> RxcrcerfimW<'_, MmcIntrMaskRxSpec> { + RxcrcerfimW::new(self, 5) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxalgnerfim(&mut self) -> RxalgnerfimW<'_, MmcIntrMaskRxSpec> { + RxalgnerfimW::new(self, 6) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxruntfim(&mut self) -> RxruntfimW<'_, MmcIntrMaskRxSpec> { + RxruntfimW::new(self, 7) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxjaberfim(&mut self) -> RxjaberfimW<'_, MmcIntrMaskRxSpec> { + RxjaberfimW::new(self, 8) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxusizegfim(&mut self) -> RxusizegfimW<'_, MmcIntrMaskRxSpec> { + RxusizegfimW::new(self, 9) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxosizegfim(&mut self) -> RxosizegfimW<'_, MmcIntrMaskRxSpec> { + RxosizegfimW::new(self, 10) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx64octgbfim(&mut self) -> Rx64octgbfimW<'_, MmcIntrMaskRxSpec> { + Rx64octgbfimW::new(self, 11) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx65t127octgbfim(&mut self) -> Rx65t127octgbfimW<'_, MmcIntrMaskRxSpec> { + Rx65t127octgbfimW::new(self, 12) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx128t255octgbfim(&mut self) -> Rx128t255octgbfimW<'_, MmcIntrMaskRxSpec> { + Rx128t255octgbfimW::new(self, 13) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx256t511octgbfim(&mut self) -> Rx256t511octgbfimW<'_, MmcIntrMaskRxSpec> { + Rx256t511octgbfimW::new(self, 14) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx512t1023octgbfim(&mut self) -> Rx512t1023octgbfimW<'_, MmcIntrMaskRxSpec> { + Rx512t1023octgbfimW::new(self, 15) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] + #[inline(always)] + pub fn rx1024tmaxoctgbfim(&mut self) -> Rx1024tmaxoctgbfimW<'_, MmcIntrMaskRxSpec> { + Rx1024tmaxoctgbfimW::new(self, 16) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxucgfim(&mut self) -> RxucgfimW<'_, MmcIntrMaskRxSpec> { + RxucgfimW::new(self, 17) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxlenerfim(&mut self) -> RxlenerfimW<'_, MmcIntrMaskRxSpec> { + RxlenerfimW::new(self, 18) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxorangefim(&mut self) -> RxorangefimW<'_, MmcIntrMaskRxSpec> { + RxorangefimW::new(self, 19) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxpausfim(&mut self) -> RxpausfimW<'_, MmcIntrMaskRxSpec> { + RxpausfimW::new(self, 20) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxfovfim(&mut self) -> RxfovfimW<'_, MmcIntrMaskRxSpec> { + RxfovfimW::new(self, 21) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxvlangbfim(&mut self) -> RxvlangbfimW<'_, MmcIntrMaskRxSpec> { + RxvlangbfimW::new(self, 22) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxwdogfim(&mut self) -> RxwdogfimW<'_, MmcIntrMaskRxSpec> { + RxwdogfimW::new(self, 23) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxrcverrfim(&mut self) -> RxrcverrfimW<'_, MmcIntrMaskRxSpec> { + RxrcverrfimW::new(self, 24) + } + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxctrlfim(&mut self) -> RxctrlfimW<'_, MmcIntrMaskRxSpec> { + RxctrlfimW::new(self, 25) + } +} +#[doc = "MMC Receive Interrupt Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_intr_mask_rx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_intr_mask_rx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcIntrMaskRxSpec; +impl crate::RegisterSpec for MmcIntrMaskRxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_intr_mask_rx::R`](R) reader structure"] +impl crate::Readable for MmcIntrMaskRxSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_intr_mask_rx::W`](W) writer structure"] +impl crate::Writable for MmcIntrMaskRxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MMC_INTR_MASK_RX to value 0"] +impl crate::Resettable for MmcIntrMaskRxSpec {} diff --git a/va416xx/va416xx/src/eth/mmc_intr_mask_tx.rs b/va416xx/va416xx/src/eth/mmc_intr_mask_tx.rs new file mode 100644 index 0000000..823e87f --- /dev/null +++ b/va416xx/va416xx/src/eth/mmc_intr_mask_tx.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MMC_INTR_MASK_TX` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_INTR_MASK_TX` writer"] +pub type W = crate::W; +#[doc = "Field `TXGBOCTIM` reader - MMC Transmit Good Bad Octet Counter Interrupt Mask"] +pub type TxgboctimR = crate::BitReader; +#[doc = "Field `TXGBOCTIM` writer - MMC Transmit Good Bad Octet Counter Interrupt Mask"] +pub type TxgboctimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGBFRMIM` reader - MMC Transmit Good Bad Frame Counter Interrupt Mask"] +pub type TxgbfrmimR = crate::BitReader; +#[doc = "Field `TXGBFRMIM` writer - MMC Transmit Good Bad Frame Counter Interrupt Mask"] +pub type TxgbfrmimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXBCGFIM` reader - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] +pub type TxbcgfimR = crate::BitReader; +#[doc = "Field `TXBCGFIM` writer - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] +pub type TxbcgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCGFIM` reader - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] +pub type TxmcgfimR = crate::BitReader; +#[doc = "Field `TXMCGFIM` writer - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] +pub type TxmcgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX64OCTGBFIM` reader - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx64octgbfimR = crate::BitReader; +#[doc = "Field `TX64OCTGBFIM` writer - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx64octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX65T127OCTGBFIM` reader - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx65t127octgbfimR = crate::BitReader; +#[doc = "Field `TX65T127OCTGBFIM` writer - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx65t127octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX128T255OCTGBFIM` reader - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx128t255octgbfimR = crate::BitReader; +#[doc = "Field `TX128T255OCTGBFIM` writer - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx128t255octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX256T511OCTGBFIM` reader - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx256t511octgbfimR = crate::BitReader; +#[doc = "Field `TX256T511OCTGBFIM` writer - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx256t511octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX512T1023OCTGBFIM` reader - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx512t1023octgbfimR = crate::BitReader; +#[doc = "Field `TX512T1023OCTGBFIM` writer - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx512t1023octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX1024TMAXOCTGBFIM` reader - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx1024tmaxoctgbfimR = crate::BitReader; +#[doc = "Field `TX1024TMAXOCTGBFIM` writer - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx1024tmaxoctgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUCGBFIM` reader - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] +pub type TxucgbfimR = crate::BitReader; +#[doc = "Field `TXUCGBFIM` writer - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] +pub type TxucgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCGBFIM` reader - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] +pub type TxmcgbfimR = crate::BitReader; +#[doc = "Field `TXMCGBFIM` writer - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] +pub type TxmcgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXBCGBFIM` reader - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] +pub type TxbcgbfimR = crate::BitReader; +#[doc = "Field `TXBCGBFIM` writer - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] +pub type TxbcgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUFLOWERFIM` reader - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] +pub type TxuflowerfimR = crate::BitReader; +#[doc = "Field `TXUFLOWERFIM` writer - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] +pub type TxuflowerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSCOLGFIM` reader - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] +pub type TxscolgfimR = crate::BitReader; +#[doc = "Field `TXSCOLGFIM` writer - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] +pub type TxscolgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCOLGFIM` reader - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] +pub type TxmcolgfimR = crate::BitReader; +#[doc = "Field `TXMCOLGFIM` writer - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] +pub type TxmcolgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXDEFFIM` reader - MMC Transmit Deferred Frame Counter Interrupt Mask"] +pub type TxdeffimR = crate::BitReader; +#[doc = "Field `TXDEFFIM` writer - MMC Transmit Deferred Frame Counter Interrupt Mask"] +pub type TxdeffimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXLATCOLFIM` reader - MMC Transmit Late Collision Frame Counter Interrupt Mask"] +pub type TxlatcolfimR = crate::BitReader; +#[doc = "Field `TXLATCOLFIM` writer - MMC Transmit Late Collision Frame Counter Interrupt Mask"] +pub type TxlatcolfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEXCOLFIM` reader - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] +pub type TxexcolfimR = crate::BitReader; +#[doc = "Field `TXEXCOLFIM` writer - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] +pub type TxexcolfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXCARERFIM` reader - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] +pub type TxcarerfimR = crate::BitReader; +#[doc = "Field `TXCARERFIM` writer - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] +pub type TxcarerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGOCTIM` reader - MMC Transmit Good Octet Counter Interrupt Mask"] +pub type TxgoctimR = crate::BitReader; +#[doc = "Field `TXGOCTIM` writer - MMC Transmit Good Octet Counter Interrupt Mask"] +pub type TxgoctimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGFRMIM` reader - MMC Transmit Good Frame Counter Interrupt Mask"] +pub type TxgfrmimR = crate::BitReader; +#[doc = "Field `TXGFRMIM` writer - MMC Transmit Good Frame Counter Interrupt Mask"] +pub type TxgfrmimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEXDEFFIM` reader - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] +pub type TxexdeffimR = crate::BitReader; +#[doc = "Field `TXEXDEFFIM` writer - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] +pub type TxexdeffimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXPAUSFIM` reader - MMC Transmit Pause Frame Counter Interrupt Mask"] +pub type TxpausfimR = crate::BitReader; +#[doc = "Field `TXPAUSFIM` writer - MMC Transmit Pause Frame Counter Interrupt Mask"] +pub type TxpausfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXVLANGFIM` reader - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] +pub type TxvlangfimR = crate::BitReader; +#[doc = "Field `TXVLANGFIM` writer - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] +pub type TxvlangfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXOSIZEGFIM` reader - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] +pub type TxosizegfimR = crate::BitReader; +#[doc = "Field `TXOSIZEGFIM` writer - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] +pub type TxosizegfimW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgboctim(&self) -> TxgboctimR { + TxgboctimR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgbfrmim(&self) -> TxgbfrmimR { + TxgbfrmimR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgfim(&self) -> TxbcgfimR { + TxbcgfimR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgfim(&self) -> TxmcgfimR { + TxmcgfimR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx64octgbfim(&self) -> Tx64octgbfimR { + Tx64octgbfimR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx65t127octgbfim(&self) -> Tx65t127octgbfimR { + Tx65t127octgbfimR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx128t255octgbfim(&self) -> Tx128t255octgbfimR { + Tx128t255octgbfimR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx256t511octgbfim(&self) -> Tx256t511octgbfimR { + Tx256t511octgbfimR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx512t1023octgbfim(&self) -> Tx512t1023octgbfimR { + Tx512t1023octgbfimR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx1024tmaxoctgbfim(&self) -> Tx1024tmaxoctgbfimR { + Tx1024tmaxoctgbfimR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txucgbfim(&self) -> TxucgbfimR { + TxucgbfimR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgbfim(&self) -> TxmcgbfimR { + TxmcgbfimR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgbfim(&self) -> TxbcgbfimR { + TxbcgbfimR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txuflowerfim(&self) -> TxuflowerfimR { + TxuflowerfimR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txscolgfim(&self) -> TxscolgfimR { + TxscolgfimR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcolgfim(&self) -> TxmcolgfimR { + TxmcolgfimR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txdeffim(&self) -> TxdeffimR { + TxdeffimR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txlatcolfim(&self) -> TxlatcolfimR { + TxlatcolfimR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexcolfim(&self) -> TxexcolfimR { + TxexcolfimR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txcarerfim(&self) -> TxcarerfimR { + TxcarerfimR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgoctim(&self) -> TxgoctimR { + TxgoctimR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgfrmim(&self) -> TxgfrmimR { + TxgfrmimR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexdeffim(&self) -> TxexdeffimR { + TxexdeffimR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txpausfim(&self) -> TxpausfimR { + TxpausfimR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txvlangfim(&self) -> TxvlangfimR { + TxvlangfimR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txosizegfim(&self) -> TxosizegfimR { + TxosizegfimR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgboctim(&mut self) -> TxgboctimW<'_, MmcIntrMaskTxSpec> { + TxgboctimW::new(self, 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgbfrmim(&mut self) -> TxgbfrmimW<'_, MmcIntrMaskTxSpec> { + TxgbfrmimW::new(self, 1) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgfim(&mut self) -> TxbcgfimW<'_, MmcIntrMaskTxSpec> { + TxbcgfimW::new(self, 2) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgfim(&mut self) -> TxmcgfimW<'_, MmcIntrMaskTxSpec> { + TxmcgfimW::new(self, 3) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx64octgbfim(&mut self) -> Tx64octgbfimW<'_, MmcIntrMaskTxSpec> { + Tx64octgbfimW::new(self, 4) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx65t127octgbfim(&mut self) -> Tx65t127octgbfimW<'_, MmcIntrMaskTxSpec> { + Tx65t127octgbfimW::new(self, 5) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx128t255octgbfim(&mut self) -> Tx128t255octgbfimW<'_, MmcIntrMaskTxSpec> { + Tx128t255octgbfimW::new(self, 6) + } + #[doc = "Bit 7 - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx256t511octgbfim(&mut self) -> Tx256t511octgbfimW<'_, MmcIntrMaskTxSpec> { + Tx256t511octgbfimW::new(self, 7) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx512t1023octgbfim(&mut self) -> Tx512t1023octgbfimW<'_, MmcIntrMaskTxSpec> { + Tx512t1023octgbfimW::new(self, 8) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx1024tmaxoctgbfim(&mut self) -> Tx1024tmaxoctgbfimW<'_, MmcIntrMaskTxSpec> { + Tx1024tmaxoctgbfimW::new(self, 9) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txucgbfim(&mut self) -> TxucgbfimW<'_, MmcIntrMaskTxSpec> { + TxucgbfimW::new(self, 10) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgbfim(&mut self) -> TxmcgbfimW<'_, MmcIntrMaskTxSpec> { + TxmcgbfimW::new(self, 11) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgbfim(&mut self) -> TxbcgbfimW<'_, MmcIntrMaskTxSpec> { + TxbcgbfimW::new(self, 12) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txuflowerfim(&mut self) -> TxuflowerfimW<'_, MmcIntrMaskTxSpec> { + TxuflowerfimW::new(self, 13) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txscolgfim(&mut self) -> TxscolgfimW<'_, MmcIntrMaskTxSpec> { + TxscolgfimW::new(self, 14) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcolgfim(&mut self) -> TxmcolgfimW<'_, MmcIntrMaskTxSpec> { + TxmcolgfimW::new(self, 15) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txdeffim(&mut self) -> TxdeffimW<'_, MmcIntrMaskTxSpec> { + TxdeffimW::new(self, 16) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txlatcolfim(&mut self) -> TxlatcolfimW<'_, MmcIntrMaskTxSpec> { + TxlatcolfimW::new(self, 17) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexcolfim(&mut self) -> TxexcolfimW<'_, MmcIntrMaskTxSpec> { + TxexcolfimW::new(self, 18) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txcarerfim(&mut self) -> TxcarerfimW<'_, MmcIntrMaskTxSpec> { + TxcarerfimW::new(self, 19) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgoctim(&mut self) -> TxgoctimW<'_, MmcIntrMaskTxSpec> { + TxgoctimW::new(self, 20) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgfrmim(&mut self) -> TxgfrmimW<'_, MmcIntrMaskTxSpec> { + TxgfrmimW::new(self, 21) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexdeffim(&mut self) -> TxexdeffimW<'_, MmcIntrMaskTxSpec> { + TxexdeffimW::new(self, 22) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txpausfim(&mut self) -> TxpausfimW<'_, MmcIntrMaskTxSpec> { + TxpausfimW::new(self, 23) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txvlangfim(&mut self) -> TxvlangfimW<'_, MmcIntrMaskTxSpec> { + TxvlangfimW::new(self, 24) + } + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txosizegfim(&mut self) -> TxosizegfimW<'_, MmcIntrMaskTxSpec> { + TxosizegfimW::new(self, 25) + } +} +#[doc = "MMC Transmit Interrupt Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_intr_mask_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_intr_mask_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcIntrMaskTxSpec; +impl crate::RegisterSpec for MmcIntrMaskTxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_intr_mask_tx::R`](R) reader structure"] +impl crate::Readable for MmcIntrMaskTxSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_intr_mask_tx::W`](W) writer structure"] +impl crate::Writable for MmcIntrMaskTxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MMC_INTR_MASK_TX to value 0"] +impl crate::Resettable for MmcIntrMaskTxSpec {} diff --git a/va416xx/va416xx/src/eth/mmc_intr_rx.rs b/va416xx/va416xx/src/eth/mmc_intr_rx.rs new file mode 100644 index 0000000..2fd8a2a --- /dev/null +++ b/va416xx/va416xx/src/eth/mmc_intr_rx.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MMC_INTR_RX` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_INTR_RX` writer"] +pub type W = crate::W; +#[doc = "Field `RXGBFRMIS` reader - MMC Receive Good Bad Frame Counter Interrupt Status"] +pub type RxgbfrmisR = crate::BitReader; +#[doc = "Field `RXGBFRMIS` writer - MMC Receive Good Bad Frame Counter Interrupt Status"] +pub type RxgbfrmisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXGBOCTIS` reader - MMC Receive Good Bad Octet Counter Interrupt Status"] +pub type RxgboctisR = crate::BitReader; +#[doc = "Field `RXGBOCTIS` writer - MMC Receive Good Bad Octet Counter Interrupt Status"] +pub type RxgboctisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXGOCTIS` reader - MMC Receive Good Octet Counter Interrupt Status"] +pub type RxgoctisR = crate::BitReader; +#[doc = "Field `RXGOCTIS` writer - MMC Receive Good Octet Counter Interrupt Status"] +pub type RxgoctisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXBCGFIS` reader - MMC Receive Broadcast Good Frame Counter Interrupt Status"] +pub type RxbcgfisR = crate::BitReader; +#[doc = "Field `RXBCGFIS` writer - MMC Receive Broadcast Good Frame Counter Interrupt Status"] +pub type RxbcgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXMCGFIS` reader - MMC Receive Multicast Good Frame Counter Interrupt Status"] +pub type RxmcgfisR = crate::BitReader; +#[doc = "Field `RXMCGFIS` writer - MMC Receive Multicast Good Frame Counter Interrupt Status"] +pub type RxmcgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXCRCERFIS` reader - MMC Receive CRC Error Frame Counter Interrupt Status"] +pub type RxcrcerfisR = crate::BitReader; +#[doc = "Field `RXCRCERFIS` writer - MMC Receive CRC Error Frame Counter Interrupt Status"] +pub type RxcrcerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXALGNERFIS` reader - MMC Receive Alignment Error Frame Counter Interrupt Status"] +pub type RxalgnerfisR = crate::BitReader; +#[doc = "Field `RXALGNERFIS` writer - MMC Receive Alignment Error Frame Counter Interrupt Status"] +pub type RxalgnerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXRUNTFIS` reader - MMC Receive Runt Frame Counter Interrupt Status"] +pub type RxruntfisR = crate::BitReader; +#[doc = "Field `RXRUNTFIS` writer - MMC Receive Runt Frame Counter Interrupt Status"] +pub type RxruntfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXJABERFIS` reader - MMC Receive Jabber Error Frame Counter Interrupt Status"] +pub type RxjaberfisR = crate::BitReader; +#[doc = "Field `RXJABERFIS` writer - MMC Receive Jabber Error Frame Counter Interrupt Status"] +pub type RxjaberfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXUSIZEGFIS` reader - MMC Receive Undersize Good Frame Counter Interrupt Status"] +pub type RxusizegfisR = crate::BitReader; +#[doc = "Field `RXUSIZEGFIS` writer - MMC Receive Undersize Good Frame Counter Interrupt Status"] +pub type RxusizegfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOSIZEGFIS` reader - MMC Receive Oversize Good Frame Counter Interrupt Status"] +pub type RxosizegfisR = crate::BitReader; +#[doc = "Field `RXOSIZEGFIS` writer - MMC Receive Oversize Good Frame Counter Interrupt Status"] +pub type RxosizegfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX64OCTGBFIS` reader - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx64octgbfisR = crate::BitReader; +#[doc = "Field `RX64OCTGBFIS` writer - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx64octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX65T127OCTGBFIS` reader - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx65t127octgbfisR = crate::BitReader; +#[doc = "Field `RX65T127OCTGBFIS` writer - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx65t127octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX128T255OCTGBFIS` reader - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx128t255octgbfisR = crate::BitReader; +#[doc = "Field `RX128T255OCTGBFIS` writer - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx128t255octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX256T511OCTGBFIS` reader - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx256t511octgbfisR = crate::BitReader; +#[doc = "Field `RX256T511OCTGBFIS` writer - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx256t511octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX512T1023OCTGBFIS` reader - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx512t1023octgbfisR = crate::BitReader; +#[doc = "Field `RX512T1023OCTGBFIS` writer - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx512t1023octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX1024TMAXOCTGBFIS` reader - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] +pub type Rx1024tmaxoctgbfisR = crate::BitReader; +#[doc = "Field `RX1024TMAXOCTGBFIS` writer - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] +pub type Rx1024tmaxoctgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXUCGFIS` reader - MMC Receive Unicast Good Frame Counter Interrupt Status"] +pub type RxucgfisR = crate::BitReader; +#[doc = "Field `RXUCGFIS` writer - MMC Receive Unicast Good Frame Counter Interrupt Status"] +pub type RxucgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXLENERFIS` reader - MMC Receive Length Error Frame Counter Interrupt Status"] +pub type RxlenerfisR = crate::BitReader; +#[doc = "Field `RXLENERFIS` writer - MMC Receive Length Error Frame Counter Interrupt Status"] +pub type RxlenerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXORANGEFIS` reader - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] +pub type RxorangefisR = crate::BitReader; +#[doc = "Field `RXORANGEFIS` writer - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] +pub type RxorangefisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXPAUSFIS` reader - MMC Receive Pause Frame Counter Interrupt Status"] +pub type RxpausfisR = crate::BitReader; +#[doc = "Field `RXPAUSFIS` writer - MMC Receive Pause Frame Counter Interrupt Status"] +pub type RxpausfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFOVFIS` reader - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] +pub type RxfovfisR = crate::BitReader; +#[doc = "Field `RXFOVFIS` writer - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] +pub type RxfovfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXVLANGBFIS` reader - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] +pub type RxvlangbfisR = crate::BitReader; +#[doc = "Field `RXVLANGBFIS` writer - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] +pub type RxvlangbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXWDOGFIS` reader - MMC Receive Watchdog Error Frame Counter Interrupt Status"] +pub type RxwdogfisR = crate::BitReader; +#[doc = "Field `RXWDOGFIS` writer - MMC Receive Watchdog Error Frame Counter Interrupt Status"] +pub type RxwdogfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXRCVERRFIS` reader - MMC Receive Error Frame Counter Interrupt Status"] +pub type RxrcverrfisR = crate::BitReader; +#[doc = "Field `RXRCVERRFIS` writer - MMC Receive Error Frame Counter Interrupt Status"] +pub type RxrcverrfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXCTRLFIS` reader - MMC Receive Control Frame Counter Interrupt Status"] +pub type RxctrlfisR = crate::BitReader; +#[doc = "Field `RXCTRLFIS` writer - MMC Receive Control Frame Counter Interrupt Status"] +pub type RxctrlfisW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxgbfrmis(&self) -> RxgbfrmisR { + RxgbfrmisR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgboctis(&self) -> RxgboctisR { + RxgboctisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgoctis(&self) -> RxgoctisR { + RxgoctisR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxbcgfis(&self) -> RxbcgfisR { + RxbcgfisR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxmcgfis(&self) -> RxmcgfisR { + RxmcgfisR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxcrcerfis(&self) -> RxcrcerfisR { + RxcrcerfisR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxalgnerfis(&self) -> RxalgnerfisR { + RxalgnerfisR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxruntfis(&self) -> RxruntfisR { + RxruntfisR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxjaberfis(&self) -> RxjaberfisR { + RxjaberfisR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxusizegfis(&self) -> RxusizegfisR { + RxusizegfisR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxosizegfis(&self) -> RxosizegfisR { + RxosizegfisR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx64octgbfis(&self) -> Rx64octgbfisR { + Rx64octgbfisR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx65t127octgbfis(&self) -> Rx65t127octgbfisR { + Rx65t127octgbfisR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx128t255octgbfis(&self) -> Rx128t255octgbfisR { + Rx128t255octgbfisR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx256t511octgbfis(&self) -> Rx256t511octgbfisR { + Rx256t511octgbfisR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx512t1023octgbfis(&self) -> Rx512t1023octgbfisR { + Rx512t1023octgbfisR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rx1024tmaxoctgbfis(&self) -> Rx1024tmaxoctgbfisR { + Rx1024tmaxoctgbfisR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxucgfis(&self) -> RxucgfisR { + RxucgfisR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxlenerfis(&self) -> RxlenerfisR { + RxlenerfisR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rxorangefis(&self) -> RxorangefisR { + RxorangefisR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxpausfis(&self) -> RxpausfisR { + RxpausfisR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxfovfis(&self) -> RxfovfisR { + RxfovfisR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxvlangbfis(&self) -> RxvlangbfisR { + RxvlangbfisR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxwdogfis(&self) -> RxwdogfisR { + RxwdogfisR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxrcverrfis(&self) -> RxrcverrfisR { + RxrcverrfisR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxctrlfis(&self) -> RxctrlfisR { + RxctrlfisR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxgbfrmis(&mut self) -> RxgbfrmisW<'_, MmcIntrRxSpec> { + RxgbfrmisW::new(self, 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgboctis(&mut self) -> RxgboctisW<'_, MmcIntrRxSpec> { + RxgboctisW::new(self, 1) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgoctis(&mut self) -> RxgoctisW<'_, MmcIntrRxSpec> { + RxgoctisW::new(self, 2) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxbcgfis(&mut self) -> RxbcgfisW<'_, MmcIntrRxSpec> { + RxbcgfisW::new(self, 3) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxmcgfis(&mut self) -> RxmcgfisW<'_, MmcIntrRxSpec> { + RxmcgfisW::new(self, 4) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxcrcerfis(&mut self) -> RxcrcerfisW<'_, MmcIntrRxSpec> { + RxcrcerfisW::new(self, 5) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxalgnerfis(&mut self) -> RxalgnerfisW<'_, MmcIntrRxSpec> { + RxalgnerfisW::new(self, 6) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxruntfis(&mut self) -> RxruntfisW<'_, MmcIntrRxSpec> { + RxruntfisW::new(self, 7) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxjaberfis(&mut self) -> RxjaberfisW<'_, MmcIntrRxSpec> { + RxjaberfisW::new(self, 8) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxusizegfis(&mut self) -> RxusizegfisW<'_, MmcIntrRxSpec> { + RxusizegfisW::new(self, 9) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxosizegfis(&mut self) -> RxosizegfisW<'_, MmcIntrRxSpec> { + RxosizegfisW::new(self, 10) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx64octgbfis(&mut self) -> Rx64octgbfisW<'_, MmcIntrRxSpec> { + Rx64octgbfisW::new(self, 11) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx65t127octgbfis(&mut self) -> Rx65t127octgbfisW<'_, MmcIntrRxSpec> { + Rx65t127octgbfisW::new(self, 12) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx128t255octgbfis(&mut self) -> Rx128t255octgbfisW<'_, MmcIntrRxSpec> { + Rx128t255octgbfisW::new(self, 13) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx256t511octgbfis(&mut self) -> Rx256t511octgbfisW<'_, MmcIntrRxSpec> { + Rx256t511octgbfisW::new(self, 14) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx512t1023octgbfis(&mut self) -> Rx512t1023octgbfisW<'_, MmcIntrRxSpec> { + Rx512t1023octgbfisW::new(self, 15) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rx1024tmaxoctgbfis(&mut self) -> Rx1024tmaxoctgbfisW<'_, MmcIntrRxSpec> { + Rx1024tmaxoctgbfisW::new(self, 16) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxucgfis(&mut self) -> RxucgfisW<'_, MmcIntrRxSpec> { + RxucgfisW::new(self, 17) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxlenerfis(&mut self) -> RxlenerfisW<'_, MmcIntrRxSpec> { + RxlenerfisW::new(self, 18) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rxorangefis(&mut self) -> RxorangefisW<'_, MmcIntrRxSpec> { + RxorangefisW::new(self, 19) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxpausfis(&mut self) -> RxpausfisW<'_, MmcIntrRxSpec> { + RxpausfisW::new(self, 20) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxfovfis(&mut self) -> RxfovfisW<'_, MmcIntrRxSpec> { + RxfovfisW::new(self, 21) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxvlangbfis(&mut self) -> RxvlangbfisW<'_, MmcIntrRxSpec> { + RxvlangbfisW::new(self, 22) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxwdogfis(&mut self) -> RxwdogfisW<'_, MmcIntrRxSpec> { + RxwdogfisW::new(self, 23) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxrcverrfis(&mut self) -> RxrcverrfisW<'_, MmcIntrRxSpec> { + RxrcverrfisW::new(self, 24) + } + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxctrlfis(&mut self) -> RxctrlfisW<'_, MmcIntrRxSpec> { + RxctrlfisW::new(self, 25) + } +} +#[doc = "MMC Receive Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_intr_rx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_intr_rx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcIntrRxSpec; +impl crate::RegisterSpec for MmcIntrRxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_intr_rx::R`](R) reader structure"] +impl crate::Readable for MmcIntrRxSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_intr_rx::W`](W) writer structure"] +impl crate::Writable for MmcIntrRxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MMC_INTR_RX to value 0"] +impl crate::Resettable for MmcIntrRxSpec {} diff --git a/va416xx/va416xx/src/eth/mmc_intr_tx.rs b/va416xx/va416xx/src/eth/mmc_intr_tx.rs new file mode 100644 index 0000000..9568ba7 --- /dev/null +++ b/va416xx/va416xx/src/eth/mmc_intr_tx.rs @@ -0,0 +1,385 @@ +#[doc = "Register `MMC_INTR_TX` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_INTR_TX` writer"] +pub type W = crate::W; +#[doc = "Field `TXGBOCTIS` reader - MMC Transmit Good Bad Octet Counter Interrupt Status"] +pub type TxgboctisR = crate::BitReader; +#[doc = "Field `TXGBOCTIS` writer - MMC Transmit Good Bad Octet Counter Interrupt Status"] +pub type TxgboctisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGBFRMIS` reader - MMC Transmit Good Bad Frame Counter Interrupt Status"] +pub type TxgbfrmisR = crate::BitReader; +#[doc = "Field `TXGBFRMIS` writer - MMC Transmit Good Bad Frame Counter Interrupt Status"] +pub type TxgbfrmisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXBCGFIS` reader - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] +pub type TxbcgfisR = crate::BitReader; +#[doc = "Field `TXBCGFIS` writer - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] +pub type TxbcgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCGFIS` reader - MMC Transmit Multicast Good Frame Counter Interrupt Status"] +pub type TxmcgfisR = crate::BitReader; +#[doc = "Field `TXMCGFIS` writer - MMC Transmit Multicast Good Frame Counter Interrupt Status"] +pub type TxmcgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX64OCTGBFIS` reader - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx64octgbfisR = crate::BitReader; +#[doc = "Field `TX64OCTGBFIS` writer - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx64octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX65T127OCTGBFIS` reader - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx65t127octgbfisR = crate::BitReader; +#[doc = "Field `TX65T127OCTGBFIS` writer - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx65t127octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX128T255OCTGBFIS` reader - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx128t255octgbfisR = crate::BitReader; +#[doc = "Field `TX128T255OCTGBFIS` writer - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx128t255octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX256T511OCTGBFIS` reader - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx256t511octgbfisR = crate::BitReader; +#[doc = "Field `TX256T511OCTGBFIS` writer - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx256t511octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX512T1023OCTGBFIS` reader - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx512t1023octgbfisR = crate::BitReader; +#[doc = "Field `TX512T1023OCTGBFIS` writer - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx512t1023octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX1024TMAXOCTGBFIS` reader - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] +pub type Tx1024tmaxoctgbfisR = crate::BitReader; +#[doc = "Field `TX1024TMAXOCTGBFIS` writer - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] +pub type Tx1024tmaxoctgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUCGBFIS` reader - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] +pub type TxucgbfisR = crate::BitReader; +#[doc = "Field `TXUCGBFIS` writer - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] +pub type TxucgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCGBFIS` reader - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] +pub type TxmcgbfisR = crate::BitReader; +#[doc = "Field `TXMCGBFIS` writer - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] +pub type TxmcgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXBCGBFIS` reader - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] +pub type TxbcgbfisR = crate::BitReader; +#[doc = "Field `TXBCGBFIS` writer - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] +pub type TxbcgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUFLOWERFIS` reader - MMC Transmit Underflow Error Frame Counter Interrupt Status"] +pub type TxuflowerfisR = crate::BitReader; +#[doc = "Field `TXUFLOWERFIS` writer - MMC Transmit Underflow Error Frame Counter Interrupt Status"] +pub type TxuflowerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSCOLGFIS` reader - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] +pub type TxscolgfisR = crate::BitReader; +#[doc = "Field `TXSCOLGFIS` writer - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] +pub type TxscolgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCOLGFIS` reader - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] +pub type TxmcolgfisR = crate::BitReader; +#[doc = "Field `TXMCOLGFIS` writer - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] +pub type TxmcolgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXDEFFIS` reader - MMC Transmit Deferred Frame Counter Interrupt Status"] +pub type TxdeffisR = crate::BitReader; +#[doc = "Field `TXDEFFIS` writer - MMC Transmit Deferred Frame Counter Interrupt Status"] +pub type TxdeffisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXLATCOLFIS` reader - MMC Transmit Late Collision Frame Counter Interrupt Status"] +pub type TxlatcolfisR = crate::BitReader; +#[doc = "Field `TXLATCOLFIS` writer - MMC Transmit Late Collision Frame Counter Interrupt Status"] +pub type TxlatcolfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEXCOLFIS` reader - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] +pub type TxexcolfisR = crate::BitReader; +#[doc = "Field `TXEXCOLFIS` writer - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] +pub type TxexcolfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXCARERFIS` reader - MMC Transmit Carrier Error Frame Counter Interrupt Status"] +pub type TxcarerfisR = crate::BitReader; +#[doc = "Field `TXCARERFIS` writer - MMC Transmit Carrier Error Frame Counter Interrupt Status"] +pub type TxcarerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGOCTIS` reader - MMC Transmit Good Octet Counter Interrupt Status"] +pub type TxgoctisR = crate::BitReader; +#[doc = "Field `TXGOCTIS` writer - MMC Transmit Good Octet Counter Interrupt Status"] +pub type TxgoctisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGFRMIS` reader - MMC Transmit Good Frame Counter Interrupt Status"] +pub type TxgfrmisR = crate::BitReader; +#[doc = "Field `TXGFRMIS` writer - MMC Transmit Good Frame Counter Interrupt Status"] +pub type TxgfrmisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEXDEFFIS` reader - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] +pub type TxexdeffisR = crate::BitReader; +#[doc = "Field `TXEXDEFFIS` writer - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] +pub type TxexdeffisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXPAUSFIS` reader - MMC Transmit Pause Frame Counter Interrupt Status"] +pub type TxpausfisR = crate::BitReader; +#[doc = "Field `TXPAUSFIS` writer - MMC Transmit Pause Frame Counter Interrupt Status"] +pub type TxpausfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXVLANGFIS` reader - MMC Transmit VLAN Good Frame Counter Interrupt Status"] +pub type TxvlangfisR = crate::BitReader; +#[doc = "Field `TXVLANGFIS` writer - MMC Transmit VLAN Good Frame Counter Interrupt Status"] +pub type TxvlangfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXOSIZEGFIS` reader - MMC Transmit Oversize Good Frame Counter Interrupt Status"] +pub type TxosizegfisR = crate::BitReader; +#[doc = "Field `TXOSIZEGFIS` writer - MMC Transmit Oversize Good Frame Counter Interrupt Status"] +pub type TxosizegfisW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgboctis(&self) -> TxgboctisR { + TxgboctisR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgbfrmis(&self) -> TxgbfrmisR { + TxgbfrmisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgfis(&self) -> TxbcgfisR { + TxbcgfisR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgfis(&self) -> TxmcgfisR { + TxmcgfisR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx64octgbfis(&self) -> Tx64octgbfisR { + Tx64octgbfisR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx65t127octgbfis(&self) -> Tx65t127octgbfisR { + Tx65t127octgbfisR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx128t255octgbfis(&self) -> Tx128t255octgbfisR { + Tx128t255octgbfisR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx256t511octgbfis(&self) -> Tx256t511octgbfisR { + Tx256t511octgbfisR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx512t1023octgbfis(&self) -> Tx512t1023octgbfisR { + Tx512t1023octgbfisR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] + #[inline(always)] + pub fn tx1024tmaxoctgbfis(&self) -> Tx1024tmaxoctgbfisR { + Tx1024tmaxoctgbfisR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txucgbfis(&self) -> TxucgbfisR { + TxucgbfisR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgbfis(&self) -> TxmcgbfisR { + TxmcgbfisR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgbfis(&self) -> TxbcgbfisR { + TxbcgbfisR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txuflowerfis(&self) -> TxuflowerfisR { + TxuflowerfisR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txscolgfis(&self) -> TxscolgfisR { + TxscolgfisR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcolgfis(&self) -> TxmcolgfisR { + TxmcolgfisR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txdeffis(&self) -> TxdeffisR { + TxdeffisR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txlatcolfis(&self) -> TxlatcolfisR { + TxlatcolfisR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexcolfis(&self) -> TxexcolfisR { + TxexcolfisR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txcarerfis(&self) -> TxcarerfisR { + TxcarerfisR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgoctis(&self) -> TxgoctisR { + TxgoctisR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgfrmis(&self) -> TxgfrmisR { + TxgfrmisR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexdeffis(&self) -> TxexdeffisR { + TxexdeffisR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txpausfis(&self) -> TxpausfisR { + TxpausfisR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txvlangfis(&self) -> TxvlangfisR { + TxvlangfisR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txosizegfis(&self) -> TxosizegfisR { + TxosizegfisR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgboctis(&mut self) -> TxgboctisW<'_, MmcIntrTxSpec> { + TxgboctisW::new(self, 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgbfrmis(&mut self) -> TxgbfrmisW<'_, MmcIntrTxSpec> { + TxgbfrmisW::new(self, 1) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgfis(&mut self) -> TxbcgfisW<'_, MmcIntrTxSpec> { + TxbcgfisW::new(self, 2) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgfis(&mut self) -> TxmcgfisW<'_, MmcIntrTxSpec> { + TxmcgfisW::new(self, 3) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx64octgbfis(&mut self) -> Tx64octgbfisW<'_, MmcIntrTxSpec> { + Tx64octgbfisW::new(self, 4) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx65t127octgbfis(&mut self) -> Tx65t127octgbfisW<'_, MmcIntrTxSpec> { + Tx65t127octgbfisW::new(self, 5) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx128t255octgbfis(&mut self) -> Tx128t255octgbfisW<'_, MmcIntrTxSpec> { + Tx128t255octgbfisW::new(self, 6) + } + #[doc = "Bit 7 - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx256t511octgbfis(&mut self) -> Tx256t511octgbfisW<'_, MmcIntrTxSpec> { + Tx256t511octgbfisW::new(self, 7) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx512t1023octgbfis(&mut self) -> Tx512t1023octgbfisW<'_, MmcIntrTxSpec> { + Tx512t1023octgbfisW::new(self, 8) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] + #[inline(always)] + pub fn tx1024tmaxoctgbfis(&mut self) -> Tx1024tmaxoctgbfisW<'_, MmcIntrTxSpec> { + Tx1024tmaxoctgbfisW::new(self, 9) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txucgbfis(&mut self) -> TxucgbfisW<'_, MmcIntrTxSpec> { + TxucgbfisW::new(self, 10) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgbfis(&mut self) -> TxmcgbfisW<'_, MmcIntrTxSpec> { + TxmcgbfisW::new(self, 11) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgbfis(&mut self) -> TxbcgbfisW<'_, MmcIntrTxSpec> { + TxbcgbfisW::new(self, 12) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txuflowerfis(&mut self) -> TxuflowerfisW<'_, MmcIntrTxSpec> { + TxuflowerfisW::new(self, 13) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txscolgfis(&mut self) -> TxscolgfisW<'_, MmcIntrTxSpec> { + TxscolgfisW::new(self, 14) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcolgfis(&mut self) -> TxmcolgfisW<'_, MmcIntrTxSpec> { + TxmcolgfisW::new(self, 15) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txdeffis(&mut self) -> TxdeffisW<'_, MmcIntrTxSpec> { + TxdeffisW::new(self, 16) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txlatcolfis(&mut self) -> TxlatcolfisW<'_, MmcIntrTxSpec> { + TxlatcolfisW::new(self, 17) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexcolfis(&mut self) -> TxexcolfisW<'_, MmcIntrTxSpec> { + TxexcolfisW::new(self, 18) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txcarerfis(&mut self) -> TxcarerfisW<'_, MmcIntrTxSpec> { + TxcarerfisW::new(self, 19) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgoctis(&mut self) -> TxgoctisW<'_, MmcIntrTxSpec> { + TxgoctisW::new(self, 20) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgfrmis(&mut self) -> TxgfrmisW<'_, MmcIntrTxSpec> { + TxgfrmisW::new(self, 21) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexdeffis(&mut self) -> TxexdeffisW<'_, MmcIntrTxSpec> { + TxexdeffisW::new(self, 22) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txpausfis(&mut self) -> TxpausfisW<'_, MmcIntrTxSpec> { + TxpausfisW::new(self, 23) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txvlangfis(&mut self) -> TxvlangfisW<'_, MmcIntrTxSpec> { + TxvlangfisW::new(self, 24) + } + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txosizegfis(&mut self) -> TxosizegfisW<'_, MmcIntrTxSpec> { + TxosizegfisW::new(self, 25) + } +} +#[doc = "MMC Transmit Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mmc_intr_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmc_intr_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcIntrTxSpec; +impl crate::RegisterSpec for MmcIntrTxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_intr_tx::R`](R) reader structure"] +impl crate::Readable for MmcIntrTxSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_intr_tx::W`](W) writer structure"] +impl crate::Writable for MmcIntrTxSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets MMC_INTR_TX to value 0"] +impl crate::Resettable for MmcIntrTxSpec {} diff --git a/va416xx/va416xx/src/eth/rx1024maxoct_gb.rs b/va416xx/va416xx/src/eth/rx1024maxoct_gb.rs new file mode 100644 index 0000000..38155b6 --- /dev/null +++ b/va416xx/va416xx/src/eth/rx1024maxoct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RX1024MAXOCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 1024 and max size bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx1024maxoct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx1024maxoctGbSpec; +impl crate::RegisterSpec for Rx1024maxoctGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx1024maxoct_gb::R`](R) reader structure"] +impl crate::Readable for Rx1024maxoctGbSpec {} +#[doc = "`reset()` method sets RX1024MAXOCT_GB to value 0"] +impl crate::Resettable for Rx1024maxoctGbSpec {} diff --git a/va416xx/va416xx/src/eth/rx128to255oct_gb.rs b/va416xx/va416xx/src/eth/rx128to255oct_gb.rs new file mode 100644 index 0000000..3c83a73 --- /dev/null +++ b/va416xx/va416xx/src/eth/rx128to255oct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RX128TO255OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 128 and 255 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx128to255oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx128to255octGbSpec; +impl crate::RegisterSpec for Rx128to255octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx128to255oct_gb::R`](R) reader structure"] +impl crate::Readable for Rx128to255octGbSpec {} +#[doc = "`reset()` method sets RX128TO255OCT_GB to value 0"] +impl crate::Resettable for Rx128to255octGbSpec {} diff --git a/va416xx/va416xx/src/eth/rx256to511oct_gb.rs b/va416xx/va416xx/src/eth/rx256to511oct_gb.rs new file mode 100644 index 0000000..d7715f2 --- /dev/null +++ b/va416xx/va416xx/src/eth/rx256to511oct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RX256TO511OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 256 and 511 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx256to511oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx256to511octGbSpec; +impl crate::RegisterSpec for Rx256to511octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx256to511oct_gb::R`](R) reader structure"] +impl crate::Readable for Rx256to511octGbSpec {} +#[doc = "`reset()` method sets RX256TO511OCT_GB to value 0"] +impl crate::Resettable for Rx256to511octGbSpec {} diff --git a/va416xx/va416xx/src/eth/rx512to1023oct_gb.rs b/va416xx/va416xx/src/eth/rx512to1023oct_gb.rs new file mode 100644 index 0000000..6302214 --- /dev/null +++ b/va416xx/va416xx/src/eth/rx512to1023oct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RX512TO1023OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 512 and 1023 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx512to1023oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx512to1023octGbSpec; +impl crate::RegisterSpec for Rx512to1023octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx512to1023oct_gb::R`](R) reader structure"] +impl crate::Readable for Rx512to1023octGbSpec {} +#[doc = "`reset()` method sets RX512TO1023OCT_GB to value 0"] +impl crate::Resettable for Rx512to1023octGbSpec {} diff --git a/va416xx/va416xx/src/eth/rx64octets_gb.rs b/va416xx/va416xx/src/eth/rx64octets_gb.rs new file mode 100644 index 0000000..b6b6e8e --- /dev/null +++ b/va416xx/va416xx/src/eth/rx64octets_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RX64OCTETS_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length 64 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx64octets_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx64octetsGbSpec; +impl crate::RegisterSpec for Rx64octetsGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx64octets_gb::R`](R) reader structure"] +impl crate::Readable for Rx64octetsGbSpec {} +#[doc = "`reset()` method sets RX64OCTETS_GB to value 0"] +impl crate::Resettable for Rx64octetsGbSpec {} diff --git a/va416xx/va416xx/src/eth/rx65to127oct_gb.rs b/va416xx/va416xx/src/eth/rx65to127oct_gb.rs new file mode 100644 index 0000000..46bb567 --- /dev/null +++ b/va416xx/va416xx/src/eth/rx65to127oct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RX65TO127OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 65 and 127 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rx65to127oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx65to127octGbSpec; +impl crate::RegisterSpec for Rx65to127octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx65to127oct_gb::R`](R) reader structure"] +impl crate::Readable for Rx65to127octGbSpec {} +#[doc = "`reset()` method sets RX65TO127OCT_GB to value 0"] +impl crate::Resettable for Rx65to127octGbSpec {} diff --git a/va416xx/va416xx/src/eth/rxalignerror.rs b/va416xx/va416xx/src/eth/rxalignerror.rs new file mode 100644 index 0000000..d7e1a53 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxalignerror.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXALIGNERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with alignment error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxalignerror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxalignerrorSpec; +impl crate::RegisterSpec for RxalignerrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxalignerror::R`](R) reader structure"] +impl crate::Readable for RxalignerrorSpec {} +#[doc = "`reset()` method sets RXALIGNERROR to value 0"] +impl crate::Resettable for RxalignerrorSpec {} diff --git a/va416xx/va416xx/src/eth/rxbcastframes_g.rs b/va416xx/va416xx/src/eth/rxbcastframes_g.rs new file mode 100644 index 0000000..391acb5 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxbcastframes_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXBCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good broadcast frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxbcastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxbcastframesGSpec; +impl crate::RegisterSpec for RxbcastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxbcastframes_g::R`](R) reader structure"] +impl crate::Readable for RxbcastframesGSpec {} +#[doc = "`reset()` method sets RXBCASTFRAMES_G to value 0"] +impl crate::Resettable for RxbcastframesGSpec {} diff --git a/va416xx/va416xx/src/eth/rxcrcerror.rs b/va416xx/va416xx/src/eth/rxcrcerror.rs new file mode 100644 index 0000000..822579c --- /dev/null +++ b/va416xx/va416xx/src/eth/rxcrcerror.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXCRCERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with CRC error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcrcerror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxcrcerrorSpec; +impl crate::RegisterSpec for RxcrcerrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxcrcerror::R`](R) reader structure"] +impl crate::Readable for RxcrcerrorSpec {} +#[doc = "`reset()` method sets RXCRCERROR to value 0"] +impl crate::Resettable for RxcrcerrorSpec {} diff --git a/va416xx/va416xx/src/eth/rxctrlframes_g.rs b/va416xx/va416xx/src/eth/rxctrlframes_g.rs new file mode 100644 index 0000000..d861e72 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxctrlframes_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXCTRLFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of received good control frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rxctrlframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxctrlframesGSpec; +impl crate::RegisterSpec for RxctrlframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxctrlframes_g::R`](R) reader structure"] +impl crate::Readable for RxctrlframesGSpec {} +#[doc = "`reset()` method sets RXCTRLFRAMES_G to value 0"] +impl crate::Resettable for RxctrlframesGSpec {} diff --git a/va416xx/va416xx/src/eth/rxfifooverflow.rs b/va416xx/va416xx/src/eth/rxfifooverflow.rs new file mode 100644 index 0000000..78d5815 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxfifooverflow.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXFIFOOVERFLOW` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of missed received frames because of FIFO overflow\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifooverflow::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifooverflowSpec; +impl crate::RegisterSpec for RxfifooverflowSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifooverflow::R`](R) reader structure"] +impl crate::Readable for RxfifooverflowSpec {} +#[doc = "`reset()` method sets RXFIFOOVERFLOW to value 0"] +impl crate::Resettable for RxfifooverflowSpec {} diff --git a/va416xx/va416xx/src/eth/rxframecount_gb.rs b/va416xx/va416xx/src/eth/rxframecount_gb.rs new file mode 100644 index 0000000..c2a0ff2 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxframecount_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXFRAMECOUNT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxframecount_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxframecountGbSpec; +impl crate::RegisterSpec for RxframecountGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxframecount_gb::R`](R) reader structure"] +impl crate::Readable for RxframecountGbSpec {} +#[doc = "`reset()` method sets RXFRAMECOUNT_GB to value 0"] +impl crate::Resettable for RxframecountGbSpec {} diff --git a/va416xx/va416xx/src/eth/rxjabbererror.rs b/va416xx/va416xx/src/eth/rxjabbererror.rs new file mode 100644 index 0000000..01461c6 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxjabbererror.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXJABBERERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of giant frames received with length greater than 1518 bytes and with CRC error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxjabbererror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxjabbererrorSpec; +impl crate::RegisterSpec for RxjabbererrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxjabbererror::R`](R) reader structure"] +impl crate::Readable for RxjabbererrorSpec {} +#[doc = "`reset()` method sets RXJABBERERROR to value 0"] +impl crate::Resettable for RxjabbererrorSpec {} diff --git a/va416xx/va416xx/src/eth/rxlengtherror.rs b/va416xx/va416xx/src/eth/rxlengtherror.rs new file mode 100644 index 0000000..96da0c3 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxlengtherror.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXLENGTHERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with length error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxlengtherror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxlengtherrorSpec; +impl crate::RegisterSpec for RxlengtherrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxlengtherror::R`](R) reader structure"] +impl crate::Readable for RxlengtherrorSpec {} +#[doc = "`reset()` method sets RXLENGTHERROR to value 0"] +impl crate::Resettable for RxlengtherrorSpec {} diff --git a/va416xx/va416xx/src/eth/rxmcastframes_g.rs b/va416xx/va416xx/src/eth/rxmcastframes_g.rs new file mode 100644 index 0000000..98a5384 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxmcastframes_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXMCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good multicast frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxmcastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxmcastframesGSpec; +impl crate::RegisterSpec for RxmcastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxmcastframes_g::R`](R) reader structure"] +impl crate::Readable for RxmcastframesGSpec {} +#[doc = "`reset()` method sets RXMCASTFRAMES_G to value 0"] +impl crate::Resettable for RxmcastframesGSpec {} diff --git a/va416xx/va416xx/src/eth/rxoctetcount_g.rs b/va416xx/va416xx/src/eth/rxoctetcount_g.rs new file mode 100644 index 0000000..ec8babd --- /dev/null +++ b/va416xx/va416xx/src/eth/rxoctetcount_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXOCTETCOUNT_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of bytes"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of bytes received in good frames only\n\nYou can [`read`](crate::Reg::read) this register and get [`rxoctetcount_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxoctetcountGSpec; +impl crate::RegisterSpec for RxoctetcountGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxoctetcount_g::R`](R) reader structure"] +impl crate::Readable for RxoctetcountGSpec {} +#[doc = "`reset()` method sets RXOCTETCOUNT_G to value 0"] +impl crate::Resettable for RxoctetcountGSpec {} diff --git a/va416xx/va416xx/src/eth/rxoctetcount_gb.rs b/va416xx/va416xx/src/eth/rxoctetcount_gb.rs new file mode 100644 index 0000000..29968e0 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxoctetcount_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXOCTETCOUNT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of bytes"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of bytes received in good and bad frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rxoctetcount_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxoctetcountGbSpec; +impl crate::RegisterSpec for RxoctetcountGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxoctetcount_gb::R`](R) reader structure"] +impl crate::Readable for RxoctetcountGbSpec {} +#[doc = "`reset()` method sets RXOCTETCOUNT_GB to value 0"] +impl crate::Resettable for RxoctetcountGbSpec {} diff --git a/va416xx/va416xx/src/eth/rxoutrangetype.rs b/va416xx/va416xx/src/eth/rxoutrangetype.rs new file mode 100644 index 0000000..2359618 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxoutrangetype.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXOUTRANGETYPE` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with length field not equal to the valid frame size\n\nYou can [`read`](crate::Reg::read) this register and get [`rxoutrangetype::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxoutrangetypeSpec; +impl crate::RegisterSpec for RxoutrangetypeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxoutrangetype::R`](R) reader structure"] +impl crate::Readable for RxoutrangetypeSpec {} +#[doc = "`reset()` method sets RXOUTRANGETYPE to value 0"] +impl crate::Resettable for RxoutrangetypeSpec {} diff --git a/va416xx/va416xx/src/eth/rxoversize_g.rs b/va416xx/va416xx/src/eth/rxoversize_g.rs new file mode 100644 index 0000000..389064c --- /dev/null +++ b/va416xx/va416xx/src/eth/rxoversize_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXOVERSIZE_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received without errors with length greater than the max size\n\nYou can [`read`](crate::Reg::read) this register and get [`rxoversize_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxoversizeGSpec; +impl crate::RegisterSpec for RxoversizeGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxoversize_g::R`](R) reader structure"] +impl crate::Readable for RxoversizeGSpec {} +#[doc = "`reset()` method sets RXOVERSIZE_G to value 0"] +impl crate::Resettable for RxoversizeGSpec {} diff --git a/va416xx/va416xx/src/eth/rxpauseframes.rs b/va416xx/va416xx/src/eth/rxpauseframes.rs new file mode 100644 index 0000000..b95ac05 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxpauseframes.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXPAUSEFRAMES` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and valid Pause frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxpauseframes::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxpauseframesSpec; +impl crate::RegisterSpec for RxpauseframesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxpauseframes::R`](R) reader structure"] +impl crate::Readable for RxpauseframesSpec {} +#[doc = "`reset()` method sets RXPAUSEFRAMES to value 0"] +impl crate::Resettable for RxpauseframesSpec {} diff --git a/va416xx/va416xx/src/eth/rxrcverror.rs b/va416xx/va416xx/src/eth/rxrcverror.rs new file mode 100644 index 0000000..249abe4 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxrcverror.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXRCVERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with Receive error or Frame Extension error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxrcverror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxrcverrorSpec; +impl crate::RegisterSpec for RxrcverrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxrcverror::R`](R) reader structure"] +impl crate::Readable for RxrcverrorSpec {} +#[doc = "`reset()` method sets RXRCVERROR to value 0"] +impl crate::Resettable for RxrcverrorSpec {} diff --git a/va416xx/va416xx/src/eth/rxrunterror.rs b/va416xx/va416xx/src/eth/rxrunterror.rs new file mode 100644 index 0000000..d1054cc --- /dev/null +++ b/va416xx/va416xx/src/eth/rxrunterror.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXRUNTERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with runt error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxrunterror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxrunterrorSpec; +impl crate::RegisterSpec for RxrunterrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxrunterror::R`](R) reader structure"] +impl crate::Readable for RxrunterrorSpec {} +#[doc = "`reset()` method sets RXRUNTERROR to value 0"] +impl crate::Resettable for RxrunterrorSpec {} diff --git a/va416xx/va416xx/src/eth/rxucastframes_g.rs b/va416xx/va416xx/src/eth/rxucastframes_g.rs new file mode 100644 index 0000000..3b6517f --- /dev/null +++ b/va416xx/va416xx/src/eth/rxucastframes_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXUCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of received good unicast frames\n\nYou can [`read`](crate::Reg::read) this register and get [`rxucastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxucastframesGSpec; +impl crate::RegisterSpec for RxucastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxucastframes_g::R`](R) reader structure"] +impl crate::Readable for RxucastframesGSpec {} +#[doc = "`reset()` method sets RXUCASTFRAMES_G to value 0"] +impl crate::Resettable for RxucastframesGSpec {} diff --git a/va416xx/va416xx/src/eth/rxundersize_g.rs b/va416xx/va416xx/src/eth/rxundersize_g.rs new file mode 100644 index 0000000..c2b2499 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxundersize_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXUNDERSIZE_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with length less than 64 bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`rxundersize_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxundersizeGSpec; +impl crate::RegisterSpec for RxundersizeGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxundersize_g::R`](R) reader structure"] +impl crate::Readable for RxundersizeGSpec {} +#[doc = "`reset()` method sets RXUNDERSIZE_G to value 0"] +impl crate::Resettable for RxundersizeGSpec {} diff --git a/va416xx/va416xx/src/eth/rxvlanframes_gb.rs b/va416xx/va416xx/src/eth/rxvlanframes_gb.rs new file mode 100644 index 0000000..112feea --- /dev/null +++ b/va416xx/va416xx/src/eth/rxvlanframes_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXVLANFRAMES_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad VLAN frames received\n\nYou can [`read`](crate::Reg::read) this register and get [`rxvlanframes_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxvlanframesGbSpec; +impl crate::RegisterSpec for RxvlanframesGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxvlanframes_gb::R`](R) reader structure"] +impl crate::Readable for RxvlanframesGbSpec {} +#[doc = "`reset()` method sets RXVLANFRAMES_GB to value 0"] +impl crate::Resettable for RxvlanframesGbSpec {} diff --git a/va416xx/va416xx/src/eth/rxwdogerror.rs b/va416xx/va416xx/src/eth/rxwdogerror.rs new file mode 100644 index 0000000..80931b0 --- /dev/null +++ b/va416xx/va416xx/src/eth/rxwdogerror.rs @@ -0,0 +1,20 @@ +#[doc = "Register `RXWDOGERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with error because of watchdog timeout error\n\nYou can [`read`](crate::Reg::read) this register and get [`rxwdogerror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxwdogerrorSpec; +impl crate::RegisterSpec for RxwdogerrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxwdogerror::R`](R) reader structure"] +impl crate::Readable for RxwdogerrorSpec {} +#[doc = "`reset()` method sets RXWDOGERROR to value 0"] +impl crate::Resettable for RxwdogerrorSpec {} diff --git a/va416xx/va416xx/src/eth/subsec_inc.rs b/va416xx/va416xx/src/eth/subsec_inc.rs new file mode 100644 index 0000000..ac4b267 --- /dev/null +++ b/va416xx/va416xx/src/eth/subsec_inc.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SUBSEC_INC` reader"] +pub type R = crate::R; +#[doc = "Register `SUBSEC_INC` writer"] +pub type W = crate::W; +#[doc = "Field `SSINC` reader - Sub-Second Increment Valuee"] +pub type SsincR = crate::FieldReader; +#[doc = "Field `SSINC` writer - Sub-Second Increment Valuee"] +pub type SsincW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Sub-Second Increment Valuee"] + #[inline(always)] + pub fn ssinc(&self) -> SsincR { + SsincR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Sub-Second Increment Valuee"] + #[inline(always)] + pub fn ssinc(&mut self) -> SsincW<'_, SubsecIncSpec> { + SsincW::new(self, 0) + } +} +#[doc = "Holds the 8-bit value by which the Sub-Second register is incremented\n\nYou can [`read`](crate::Reg::read) this register and get [`subsec_inc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`subsec_inc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SubsecIncSpec; +impl crate::RegisterSpec for SubsecIncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`subsec_inc::R`](R) reader structure"] +impl crate::Readable for SubsecIncSpec {} +#[doc = "`write(|w| ..)` method takes [`subsec_inc::W`](W) writer structure"] +impl crate::Writable for SubsecIncSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SUBSEC_INC to value 0"] +impl crate::Resettable for SubsecIncSpec {} diff --git a/va416xx/va416xx/src/eth/systime_nanosec.rs b/va416xx/va416xx/src/eth/systime_nanosec.rs new file mode 100644 index 0000000..929a0f7 --- /dev/null +++ b/va416xx/va416xx/src/eth/systime_nanosec.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SYSTIME_NANOSEC` reader"] +pub type R = crate::R; +#[doc = "Field `TSSS` reader - Timestamp Sub Seconds"] +pub type TsssR = crate::FieldReader; +impl R { + #[doc = "Bits 0:30 - Timestamp Sub Seconds"] + #[inline(always)] + pub fn tsss(&self) -> TsssR { + TsssR::new(self.bits & 0x7fff_ffff) + } +} +#[doc = "Holds 32 bits of the nano-second field of the system time\n\nYou can [`read`](crate::Reg::read) this register and get [`systime_nanosec::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SystimeNanosecSpec; +impl crate::RegisterSpec for SystimeNanosecSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`systime_nanosec::R`](R) reader structure"] +impl crate::Readable for SystimeNanosecSpec {} +#[doc = "`reset()` method sets SYSTIME_NANOSEC to value 0"] +impl crate::Resettable for SystimeNanosecSpec {} diff --git a/va416xx/va416xx/src/eth/systime_nsecup.rs b/va416xx/va416xx/src/eth/systime_nsecup.rs new file mode 100644 index 0000000..ded6a5c --- /dev/null +++ b/va416xx/va416xx/src/eth/systime_nsecup.rs @@ -0,0 +1,49 @@ +#[doc = "Register `SYSTIME_NSECUP` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIME_NSECUP` writer"] +pub type W = crate::W; +#[doc = "Field `TSSS` reader - Timestamp Sub Seconds"] +pub type TsssR = crate::FieldReader; +#[doc = "Field `TSSS` writer - Timestamp Sub Seconds"] +pub type TsssW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `ADDSUB` reader - Add or Subtract Time"] +pub type AddsubR = crate::BitReader; +#[doc = "Field `ADDSUB` writer - Add or Subtract Time"] +pub type AddsubW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - Timestamp Sub Seconds"] + #[inline(always)] + pub fn tsss(&self) -> TsssR { + TsssR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - Add or Subtract Time"] + #[inline(always)] + pub fn addsub(&self) -> AddsubR { + AddsubR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:30 - Timestamp Sub Seconds"] + #[inline(always)] + pub fn tsss(&mut self) -> TsssW<'_, SystimeNsecupSpec> { + TsssW::new(self, 0) + } + #[doc = "Bit 31 - Add or Subtract Time"] + #[inline(always)] + pub fn addsub(&mut self) -> AddsubW<'_, SystimeNsecupSpec> { + AddsubW::new(self, 31) + } +} +#[doc = "Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value\n\nYou can [`read`](crate::Reg::read) this register and get [`systime_nsecup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`systime_nsecup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SystimeNsecupSpec; +impl crate::RegisterSpec for SystimeNsecupSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`systime_nsecup::R`](R) reader structure"] +impl crate::Readable for SystimeNsecupSpec {} +#[doc = "`write(|w| ..)` method takes [`systime_nsecup::W`](W) writer structure"] +impl crate::Writable for SystimeNsecupSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SYSTIME_NSECUP to value 0"] +impl crate::Resettable for SystimeNsecupSpec {} diff --git a/va416xx/va416xx/src/eth/systime_seconds.rs b/va416xx/va416xx/src/eth/systime_seconds.rs new file mode 100644 index 0000000..e9b0a4b --- /dev/null +++ b/va416xx/va416xx/src/eth/systime_seconds.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SYSTIME_SECONDS` reader"] +pub type R = crate::R; +#[doc = "Field `TSS` reader - Timestamp Second"] +pub type TssR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Timestamp Second"] + #[inline(always)] + pub fn tss(&self) -> TssR { + TssR::new(self.bits) + } +} +#[doc = "Holds the lower 32 bits of the second field of the system time\n\nYou can [`read`](crate::Reg::read) this register and get [`systime_seconds::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SystimeSecondsSpec; +impl crate::RegisterSpec for SystimeSecondsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`systime_seconds::R`](R) reader structure"] +impl crate::Readable for SystimeSecondsSpec {} +#[doc = "`reset()` method sets SYSTIME_SECONDS to value 0"] +impl crate::Resettable for SystimeSecondsSpec {} diff --git a/va416xx/va416xx/src/eth/systime_secsupdat.rs b/va416xx/va416xx/src/eth/systime_secsupdat.rs new file mode 100644 index 0000000..9517922 --- /dev/null +++ b/va416xx/va416xx/src/eth/systime_secsupdat.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SYSTIME_SECSUPDAT` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIME_SECSUPDAT` writer"] +pub type W = crate::W; +#[doc = "Field `TSS` reader - Timestamp Second"] +pub type TssR = crate::FieldReader; +#[doc = "Field `TSS` writer - Timestamp Second"] +pub type TssW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timestamp Second"] + #[inline(always)] + pub fn tss(&self) -> TssR { + TssR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Timestamp Second"] + #[inline(always)] + pub fn tss(&mut self) -> TssW<'_, SystimeSecsupdatSpec> { + TssW::new(self, 0) + } +} +#[doc = "Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value\n\nYou can [`read`](crate::Reg::read) this register and get [`systime_secsupdat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`systime_secsupdat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SystimeSecsupdatSpec; +impl crate::RegisterSpec for SystimeSecsupdatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`systime_secsupdat::R`](R) reader structure"] +impl crate::Readable for SystimeSecsupdatSpec {} +#[doc = "`write(|w| ..)` method takes [`systime_secsupdat::W`](W) writer structure"] +impl crate::Writable for SystimeSecsupdatSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SYSTIME_SECSUPDAT to value 0"] +impl crate::Resettable for SystimeSecsupdatSpec {} diff --git a/va416xx/va416xx/src/eth/target_time_nsec.rs b/va416xx/va416xx/src/eth/target_time_nsec.rs new file mode 100644 index 0000000..7c9e49e --- /dev/null +++ b/va416xx/va416xx/src/eth/target_time_nsec.rs @@ -0,0 +1,49 @@ +#[doc = "Register `TARGET_TIME_NSEC` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET_TIME_NSEC` writer"] +pub type W = crate::W; +#[doc = "Field `TTSLO` reader - Target Timestamp Low Register"] +pub type TtsloR = crate::FieldReader; +#[doc = "Field `TTSLO` writer - Target Timestamp Low Register"] +pub type TtsloW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `TRGTBUSY` reader - 32 Bits of Hash Table"] +pub type TrgtbusyR = crate::BitReader; +#[doc = "Field `TRGTBUSY` writer - 32 Bits of Hash Table"] +pub type TrgtbusyW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - Target Timestamp Low Register"] + #[inline(always)] + pub fn ttslo(&self) -> TtsloR { + TtsloR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - 32 Bits of Hash Table"] + #[inline(always)] + pub fn trgtbusy(&self) -> TrgtbusyR { + TrgtbusyR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:30 - Target Timestamp Low Register"] + #[inline(always)] + pub fn ttslo(&mut self) -> TtsloW<'_, TargetTimeNsecSpec> { + TtsloW::new(self, 0) + } + #[doc = "Bit 31 - 32 Bits of Hash Table"] + #[inline(always)] + pub fn trgtbusy(&mut self) -> TrgtbusyW<'_, TargetTimeNsecSpec> { + TrgtbusyW::new(self, 31) + } +} +#[doc = "Holds the lower 32-bits of time to be compared with the system time\n\nYou can [`read`](crate::Reg::read) this register and get [`target_time_nsec::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`target_time_nsec::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TargetTimeNsecSpec; +impl crate::RegisterSpec for TargetTimeNsecSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`target_time_nsec::R`](R) reader structure"] +impl crate::Readable for TargetTimeNsecSpec {} +#[doc = "`write(|w| ..)` method takes [`target_time_nsec::W`](W) writer structure"] +impl crate::Writable for TargetTimeNsecSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TARGET_TIME_NSEC to value 0"] +impl crate::Resettable for TargetTimeNsecSpec {} diff --git a/va416xx/va416xx/src/eth/target_time_secs.rs b/va416xx/va416xx/src/eth/target_time_secs.rs new file mode 100644 index 0000000..0c5202e --- /dev/null +++ b/va416xx/va416xx/src/eth/target_time_secs.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TARGET_TIME_SECS` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET_TIME_SECS` writer"] +pub type W = crate::W; +#[doc = "Field `TSTR` reader - Target Time Seconds Registe"] +pub type TstrR = crate::FieldReader; +#[doc = "Field `TSTR` writer - Target Time Seconds Registe"] +pub type TstrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Target Time Seconds Registe"] + #[inline(always)] + pub fn tstr(&self) -> TstrR { + TstrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Target Time Seconds Registe"] + #[inline(always)] + pub fn tstr(&mut self) -> TstrW<'_, TargetTimeSecsSpec> { + TstrW::new(self, 0) + } +} +#[doc = "Holds the high 32-bits of time to be compared with the system time\n\nYou can [`read`](crate::Reg::read) this register and get [`target_time_secs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`target_time_secs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TargetTimeSecsSpec; +impl crate::RegisterSpec for TargetTimeSecsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`target_time_secs::R`](R) reader structure"] +impl crate::Readable for TargetTimeSecsSpec {} +#[doc = "`write(|w| ..)` method takes [`target_time_secs::W`](W) writer structure"] +impl crate::Writable for TargetTimeSecsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TARGET_TIME_SECS to value 0"] +impl crate::Resettable for TargetTimeSecsSpec {} diff --git a/va416xx/va416xx/src/eth/timestamp_ctrl.rs b/va416xx/va416xx/src/eth/timestamp_ctrl.rs new file mode 100644 index 0000000..aa71004 --- /dev/null +++ b/va416xx/va416xx/src/eth/timestamp_ctrl.rs @@ -0,0 +1,315 @@ +#[doc = "Register `TIMESTAMP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `TIMESTAMP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TSENA` reader - Timestamp Enable"] +pub type TsenaR = crate::BitReader; +#[doc = "Field `TSENA` writer - Timestamp Enable"] +pub type TsenaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSCFUPDT` reader - Timestamp Fine or Coarse Update"] +pub type TscfupdtR = crate::BitReader; +#[doc = "Field `TSCFUPDT` writer - Timestamp Fine or Coarse Update"] +pub type TscfupdtW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSINIT` reader - Timestamp Initialize"] +pub type TsinitR = crate::BitReader; +#[doc = "Field `TSINIT` writer - Timestamp Initialize"] +pub type TsinitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSUPDT` reader - Timestamp Update"] +pub type TsupdtR = crate::BitReader; +#[doc = "Field `TSUPDT` writer - Timestamp Update"] +pub type TsupdtW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSTRIG` reader - Timestamp Interrupt Trigger Enable"] +pub type TstrigR = crate::BitReader; +#[doc = "Field `TSTRIG` writer - Timestamp Interrupt Trigger Enable"] +pub type TstrigW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSADDRREG` reader - Addend Reg Update"] +pub type TsaddrregR = crate::BitReader; +#[doc = "Field `TSADDRREG` writer - Addend Reg Update"] +pub type TsaddrregW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSENALL` reader - Enable Timestamp for All Frames"] +pub type TsenallR = crate::BitReader; +#[doc = "Field `TSENALL` writer - Enable Timestamp for All Frames"] +pub type TsenallW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSCTRLSSR` reader - Timestamp Digital or Binary Rollover Control"] +pub type TsctrlssrR = crate::BitReader; +#[doc = "Field `TSCTRLSSR` writer - Timestamp Digital or Binary Rollover Control"] +pub type TsctrlssrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSVER2ENA` reader - Enable PTP packet Processing for Version 2 Format"] +pub type Tsver2enaR = crate::BitReader; +#[doc = "Field `TSVER2ENA` writer - Enable PTP packet Processing for Version 2 Format"] +pub type Tsver2enaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSIPENA` reader - Enable Processing of PTP over Ethernet Frames"] +pub type TsipenaR = crate::BitReader; +#[doc = "Field `TSIPENA` writer - Enable Processing of PTP over Ethernet Frames"] +pub type TsipenaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSIPV6ENA` reader - Enable Processing of PTP Frames Sent over IPv6-UDP"] +pub type Tsipv6enaR = crate::BitReader; +#[doc = "Field `TSIPV6ENA` writer - Enable Processing of PTP Frames Sent over IPv6-UDP"] +pub type Tsipv6enaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSIPV4ENA` reader - Enable Processing of PTP Frames Sent over IPv4-UDP"] +pub type Tsipv4enaR = crate::BitReader; +#[doc = "Field `TSIPV4ENA` writer - Enable Processing of PTP Frames Sent over IPv4-UDP"] +pub type Tsipv4enaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSEVNTENA` reader - Enable Timestamp Snapshot for Event Messages"] +pub type TsevntenaR = crate::BitReader; +#[doc = "Field `TSEVNTENA` writer - Enable Timestamp Snapshot for Event Messages"] +pub type TsevntenaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSMSTRENA` reader - Enable Snapshot for Messages Relevant to Master"] +pub type TsmstrenaR = crate::BitReader; +#[doc = "Field `TSMSTRENA` writer - Enable Snapshot for Messages Relevant to Master"] +pub type TsmstrenaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SNAPTYPSEL` reader - Select PTP packets for Taking Snapshots"] +pub type SnaptypselR = crate::FieldReader; +#[doc = "Field `SNAPTYPSEL` writer - Select PTP packets for Taking Snapshots"] +pub type SnaptypselW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TSENMACADDR` reader - Enable MAC address for PTP Frame Filtering"] +pub type TsenmacaddrR = crate::BitReader; +#[doc = "Field `TSENMACADDR` writer - Enable MAC address for PTP Frame Filtering"] +pub type TsenmacaddrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSFC` reader - Auxiliary Snapshot FIFO Clear"] +pub type AtsfcR = crate::BitReader; +#[doc = "Field `ATSFC` writer - Auxiliary Snapshot FIFO Clear"] +pub type AtsfcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSEN0` reader - Auxiliary Snapshot 0 Enable"] +pub type Atsen0R = crate::BitReader; +#[doc = "Field `ATSEN0` writer - Auxiliary Snapshot 0 Enable"] +pub type Atsen0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSEN1` reader - Auxiliary Snapshot 1 Enable"] +pub type Atsen1R = crate::BitReader; +#[doc = "Field `ATSEN1` writer - Auxiliary Snapshot 1 Enable"] +pub type Atsen1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSEN2` reader - Auxiliary Snapshot 2 Enable"] +pub type Atsen2R = crate::BitReader; +#[doc = "Field `ATSEN2` writer - Auxiliary Snapshot 2 Enable"] +pub type Atsen2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSEN3` reader - Auxiliary Snapshot 3 Enable"] +pub type Atsen3R = crate::BitReader; +#[doc = "Field `ATSEN3` writer - Auxiliary Snapshot 3 Enable"] +pub type Atsen3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Timestamp Enable"] + #[inline(always)] + pub fn tsena(&self) -> TsenaR { + TsenaR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timestamp Fine or Coarse Update"] + #[inline(always)] + pub fn tscfupdt(&self) -> TscfupdtR { + TscfupdtR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timestamp Initialize"] + #[inline(always)] + pub fn tsinit(&self) -> TsinitR { + TsinitR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timestamp Update"] + #[inline(always)] + pub fn tsupdt(&self) -> TsupdtR { + TsupdtR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Timestamp Interrupt Trigger Enable"] + #[inline(always)] + pub fn tstrig(&self) -> TstrigR { + TstrigR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Addend Reg Update"] + #[inline(always)] + pub fn tsaddrreg(&self) -> TsaddrregR { + TsaddrregR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Enable Timestamp for All Frames"] + #[inline(always)] + pub fn tsenall(&self) -> TsenallR { + TsenallR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Timestamp Digital or Binary Rollover Control"] + #[inline(always)] + pub fn tsctrlssr(&self) -> TsctrlssrR { + TsctrlssrR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable PTP packet Processing for Version 2 Format"] + #[inline(always)] + pub fn tsver2ena(&self) -> Tsver2enaR { + Tsver2enaR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable Processing of PTP over Ethernet Frames"] + #[inline(always)] + pub fn tsipena(&self) -> TsipenaR { + TsipenaR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable Processing of PTP Frames Sent over IPv6-UDP"] + #[inline(always)] + pub fn tsipv6ena(&self) -> Tsipv6enaR { + Tsipv6enaR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable Processing of PTP Frames Sent over IPv4-UDP"] + #[inline(always)] + pub fn tsipv4ena(&self) -> Tsipv4enaR { + Tsipv4enaR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Enable Timestamp Snapshot for Event Messages"] + #[inline(always)] + pub fn tsevntena(&self) -> TsevntenaR { + TsevntenaR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master"] + #[inline(always)] + pub fn tsmstrena(&self) -> TsmstrenaR { + TsmstrenaR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:17 - Select PTP packets for Taking Snapshots"] + #[inline(always)] + pub fn snaptypsel(&self) -> SnaptypselR { + SnaptypselR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Enable MAC address for PTP Frame Filtering"] + #[inline(always)] + pub fn tsenmacaddr(&self) -> TsenmacaddrR { + TsenmacaddrR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 24 - Auxiliary Snapshot FIFO Clear"] + #[inline(always)] + pub fn atsfc(&self) -> AtsfcR { + AtsfcR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Auxiliary Snapshot 0 Enable"] + #[inline(always)] + pub fn atsen0(&self) -> Atsen0R { + Atsen0R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Auxiliary Snapshot 1 Enable"] + #[inline(always)] + pub fn atsen1(&self) -> Atsen1R { + Atsen1R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Auxiliary Snapshot 2 Enable"] + #[inline(always)] + pub fn atsen2(&self) -> Atsen2R { + Atsen2R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Auxiliary Snapshot 3 Enable"] + #[inline(always)] + pub fn atsen3(&self) -> Atsen3R { + Atsen3R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timestamp Enable"] + #[inline(always)] + pub fn tsena(&mut self) -> TsenaW<'_, TimestampCtrlSpec> { + TsenaW::new(self, 0) + } + #[doc = "Bit 1 - Timestamp Fine or Coarse Update"] + #[inline(always)] + pub fn tscfupdt(&mut self) -> TscfupdtW<'_, TimestampCtrlSpec> { + TscfupdtW::new(self, 1) + } + #[doc = "Bit 2 - Timestamp Initialize"] + #[inline(always)] + pub fn tsinit(&mut self) -> TsinitW<'_, TimestampCtrlSpec> { + TsinitW::new(self, 2) + } + #[doc = "Bit 3 - Timestamp Update"] + #[inline(always)] + pub fn tsupdt(&mut self) -> TsupdtW<'_, TimestampCtrlSpec> { + TsupdtW::new(self, 3) + } + #[doc = "Bit 4 - Timestamp Interrupt Trigger Enable"] + #[inline(always)] + pub fn tstrig(&mut self) -> TstrigW<'_, TimestampCtrlSpec> { + TstrigW::new(self, 4) + } + #[doc = "Bit 5 - Addend Reg Update"] + #[inline(always)] + pub fn tsaddrreg(&mut self) -> TsaddrregW<'_, TimestampCtrlSpec> { + TsaddrregW::new(self, 5) + } + #[doc = "Bit 8 - Enable Timestamp for All Frames"] + #[inline(always)] + pub fn tsenall(&mut self) -> TsenallW<'_, TimestampCtrlSpec> { + TsenallW::new(self, 8) + } + #[doc = "Bit 9 - Timestamp Digital or Binary Rollover Control"] + #[inline(always)] + pub fn tsctrlssr(&mut self) -> TsctrlssrW<'_, TimestampCtrlSpec> { + TsctrlssrW::new(self, 9) + } + #[doc = "Bit 10 - Enable PTP packet Processing for Version 2 Format"] + #[inline(always)] + pub fn tsver2ena(&mut self) -> Tsver2enaW<'_, TimestampCtrlSpec> { + Tsver2enaW::new(self, 10) + } + #[doc = "Bit 11 - Enable Processing of PTP over Ethernet Frames"] + #[inline(always)] + pub fn tsipena(&mut self) -> TsipenaW<'_, TimestampCtrlSpec> { + TsipenaW::new(self, 11) + } + #[doc = "Bit 12 - Enable Processing of PTP Frames Sent over IPv6-UDP"] + #[inline(always)] + pub fn tsipv6ena(&mut self) -> Tsipv6enaW<'_, TimestampCtrlSpec> { + Tsipv6enaW::new(self, 12) + } + #[doc = "Bit 13 - Enable Processing of PTP Frames Sent over IPv4-UDP"] + #[inline(always)] + pub fn tsipv4ena(&mut self) -> Tsipv4enaW<'_, TimestampCtrlSpec> { + Tsipv4enaW::new(self, 13) + } + #[doc = "Bit 14 - Enable Timestamp Snapshot for Event Messages"] + #[inline(always)] + pub fn tsevntena(&mut self) -> TsevntenaW<'_, TimestampCtrlSpec> { + TsevntenaW::new(self, 14) + } + #[doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master"] + #[inline(always)] + pub fn tsmstrena(&mut self) -> TsmstrenaW<'_, TimestampCtrlSpec> { + TsmstrenaW::new(self, 15) + } + #[doc = "Bits 16:17 - Select PTP packets for Taking Snapshots"] + #[inline(always)] + pub fn snaptypsel(&mut self) -> SnaptypselW<'_, TimestampCtrlSpec> { + SnaptypselW::new(self, 16) + } + #[doc = "Bit 18 - Enable MAC address for PTP Frame Filtering"] + #[inline(always)] + pub fn tsenmacaddr(&mut self) -> TsenmacaddrW<'_, TimestampCtrlSpec> { + TsenmacaddrW::new(self, 18) + } + #[doc = "Bit 24 - Auxiliary Snapshot FIFO Clear"] + #[inline(always)] + pub fn atsfc(&mut self) -> AtsfcW<'_, TimestampCtrlSpec> { + AtsfcW::new(self, 24) + } + #[doc = "Bit 25 - Auxiliary Snapshot 0 Enable"] + #[inline(always)] + pub fn atsen0(&mut self) -> Atsen0W<'_, TimestampCtrlSpec> { + Atsen0W::new(self, 25) + } + #[doc = "Bit 26 - Auxiliary Snapshot 1 Enable"] + #[inline(always)] + pub fn atsen1(&mut self) -> Atsen1W<'_, TimestampCtrlSpec> { + Atsen1W::new(self, 26) + } + #[doc = "Bit 27 - Auxiliary Snapshot 2 Enable"] + #[inline(always)] + pub fn atsen2(&mut self) -> Atsen2W<'_, TimestampCtrlSpec> { + Atsen2W::new(self, 27) + } + #[doc = "Bit 28 - Auxiliary Snapshot 3 Enable"] + #[inline(always)] + pub fn atsen3(&mut self) -> Atsen3W<'_, TimestampCtrlSpec> { + Atsen3W::new(self, 28) + } +} +#[doc = "Controls the IEEE 1588 timestamp generation and update logic\n\nYou can [`read`](crate::Reg::read) this register and get [`timestamp_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timestamp_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimestampCtrlSpec; +impl crate::RegisterSpec for TimestampCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timestamp_ctrl::R`](R) reader structure"] +impl crate::Readable for TimestampCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`timestamp_ctrl::W`](W) writer structure"] +impl crate::Writable for TimestampCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMESTAMP_CTRL to value 0"] +impl crate::Resettable for TimestampCtrlSpec {} diff --git a/va416xx/va416xx/src/eth/timestampaddend.rs b/va416xx/va416xx/src/eth/timestampaddend.rs new file mode 100644 index 0000000..5a805cf --- /dev/null +++ b/va416xx/va416xx/src/eth/timestampaddend.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TIMESTAMPADDEND` reader"] +pub type R = crate::R; +#[doc = "Register `TIMESTAMPADDEND` writer"] +pub type W = crate::W; +#[doc = "Field `TSAR` reader - Timestamp Addend Register"] +pub type TsarR = crate::FieldReader; +#[doc = "Field `TSAR` writer - Timestamp Addend Register"] +pub type TsarW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timestamp Addend Register"] + #[inline(always)] + pub fn tsar(&self) -> TsarR { + TsarR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Timestamp Addend Register"] + #[inline(always)] + pub fn tsar(&mut self) -> TsarW<'_, TimestampaddendSpec> { + TsarW::new(self, 0) + } +} +#[doc = "This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency\n\nYou can [`read`](crate::Reg::read) this register and get [`timestampaddend::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timestampaddend::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimestampaddendSpec; +impl crate::RegisterSpec for TimestampaddendSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timestampaddend::R`](R) reader structure"] +impl crate::Readable for TimestampaddendSpec {} +#[doc = "`write(|w| ..)` method takes [`timestampaddend::W`](W) writer structure"] +impl crate::Writable for TimestampaddendSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIMESTAMPADDEND to value 0"] +impl crate::Resettable for TimestampaddendSpec {} diff --git a/va416xx/va416xx/src/eth/tx1024maxoct_gb.rs b/va416xx/va416xx/src/eth/tx1024maxoct_gb.rs new file mode 100644 index 0000000..2050700 --- /dev/null +++ b/va416xx/va416xx/src/eth/tx1024maxoct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TX1024MAXOCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 1024 to max bytes\n\nYou can [`read`](crate::Reg::read) this register and get [`tx1024maxoct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx1024maxoctGbSpec; +impl crate::RegisterSpec for Tx1024maxoctGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx1024maxoct_gb::R`](R) reader structure"] +impl crate::Readable for Tx1024maxoctGbSpec {} +#[doc = "`reset()` method sets TX1024MAXOCT_GB to value 0"] +impl crate::Resettable for Tx1024maxoctGbSpec {} diff --git a/va416xx/va416xx/src/eth/tx128to255oct_gb.rs b/va416xx/va416xx/src/eth/tx128to255oct_gb.rs new file mode 100644 index 0000000..67a7234 --- /dev/null +++ b/va416xx/va416xx/src/eth/tx128to255oct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TX128TO255OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 128 to 255\n\nYou can [`read`](crate::Reg::read) this register and get [`tx128to255oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx128to255octGbSpec; +impl crate::RegisterSpec for Tx128to255octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx128to255oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx128to255octGbSpec {} +#[doc = "`reset()` method sets TX128TO255OCT_GB to value 0"] +impl crate::Resettable for Tx128to255octGbSpec {} diff --git a/va416xx/va416xx/src/eth/tx256to511oct_gb.rs b/va416xx/va416xx/src/eth/tx256to511oct_gb.rs new file mode 100644 index 0000000..b5dd4d1 --- /dev/null +++ b/va416xx/va416xx/src/eth/tx256to511oct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TX256TO511OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 256 to 511\n\nYou can [`read`](crate::Reg::read) this register and get [`tx256to511oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx256to511octGbSpec; +impl crate::RegisterSpec for Tx256to511octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx256to511oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx256to511octGbSpec {} +#[doc = "`reset()` method sets TX256TO511OCT_GB to value 0"] +impl crate::Resettable for Tx256to511octGbSpec {} diff --git a/va416xx/va416xx/src/eth/tx512to1023oct_gb.rs b/va416xx/va416xx/src/eth/tx512to1023oct_gb.rs new file mode 100644 index 0000000..f96b27f --- /dev/null +++ b/va416xx/va416xx/src/eth/tx512to1023oct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TX512TO1023OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 512 to 1023\n\nYou can [`read`](crate::Reg::read) this register and get [`tx512to1023oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx512to1023octGbSpec; +impl crate::RegisterSpec for Tx512to1023octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx512to1023oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx512to1023octGbSpec {} +#[doc = "`reset()` method sets TX512TO1023OCT_GB to value 0"] +impl crate::Resettable for Tx512to1023octGbSpec {} diff --git a/va416xx/va416xx/src/eth/tx64oct_gb.rs b/va416xx/va416xx/src/eth/tx64oct_gb.rs new file mode 100644 index 0000000..78da65c --- /dev/null +++ b/va416xx/va416xx/src/eth/tx64oct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TX64OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 64\n\nYou can [`read`](crate::Reg::read) this register and get [`tx64oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx64octGbSpec; +impl crate::RegisterSpec for Tx64octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx64oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx64octGbSpec {} +#[doc = "`reset()` method sets TX64OCT_GB to value 0"] +impl crate::Resettable for Tx64octGbSpec {} diff --git a/va416xx/va416xx/src/eth/tx65to127oct_gb.rs b/va416xx/va416xx/src/eth/tx65to127oct_gb.rs new file mode 100644 index 0000000..e49f232 --- /dev/null +++ b/va416xx/va416xx/src/eth/tx65to127oct_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TX65TO127OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 65 to 127\n\nYou can [`read`](crate::Reg::read) this register and get [`tx65to127oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx65to127octGbSpec; +impl crate::RegisterSpec for Tx65to127octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx65to127oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx65to127octGbSpec {} +#[doc = "`reset()` method sets TX65TO127OCT_GB to value 0"] +impl crate::Resettable for Tx65to127octGbSpec {} diff --git a/va416xx/va416xx/src/eth/txbcastframe_gb.rs b/va416xx/va416xx/src/eth/txbcastframe_gb.rs new file mode 100644 index 0000000..8e65a26 --- /dev/null +++ b/va416xx/va416xx/src/eth/txbcastframe_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXBCASTFRAME_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC number of good and bad broadcast frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcastframe_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxbcastframeGbSpec; +impl crate::RegisterSpec for TxbcastframeGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txbcastframe_gb::R`](R) reader structure"] +impl crate::Readable for TxbcastframeGbSpec {} +#[doc = "`reset()` method sets TXBCASTFRAME_GB to value 0"] +impl crate::Resettable for TxbcastframeGbSpec {} diff --git a/va416xx/va416xx/src/eth/txbcastframes_g.rs b/va416xx/va416xx/src/eth/txbcastframes_g.rs new file mode 100644 index 0000000..62d2367 --- /dev/null +++ b/va416xx/va416xx/src/eth/txbcastframes_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXBCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good Broadcast Frames Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txbcastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxbcastframesGSpec; +impl crate::RegisterSpec for TxbcastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txbcastframes_g::R`](R) reader structure"] +impl crate::Readable for TxbcastframesGSpec {} +#[doc = "`reset()` method sets TXBCASTFRAMES_G to value 0"] +impl crate::Resettable for TxbcastframesGSpec {} diff --git a/va416xx/va416xx/src/eth/txcarriererror.rs b/va416xx/va416xx/src/eth/txcarriererror.rs new file mode 100644 index 0000000..e26c891 --- /dev/null +++ b/va416xx/va416xx/src/eth/txcarriererror.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXCARRIERERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of aborted frames because of carrier sense error\n\nYou can [`read`](crate::Reg::read) this register and get [`txcarriererror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxcarriererrorSpec; +impl crate::RegisterSpec for TxcarriererrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txcarriererror::R`](R) reader structure"] +impl crate::Readable for TxcarriererrorSpec {} +#[doc = "`reset()` method sets TXCARRIERERROR to value 0"] +impl crate::Resettable for TxcarriererrorSpec {} diff --git a/va416xx/va416xx/src/eth/txdeferred.rs b/va416xx/va416xx/src/eth/txdeferred.rs new file mode 100644 index 0000000..6f42369 --- /dev/null +++ b/va416xx/va416xx/src/eth/txdeferred.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXDEFERRED` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of successfully transmitted frames after a deferral\n\nYou can [`read`](crate::Reg::read) this register and get [`txdeferred::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxdeferredSpec; +impl crate::RegisterSpec for TxdeferredSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txdeferred::R`](R) reader structure"] +impl crate::Readable for TxdeferredSpec {} +#[doc = "`reset()` method sets TXDEFERRED to value 0"] +impl crate::Resettable for TxdeferredSpec {} diff --git a/va416xx/va416xx/src/eth/txexcessdef.rs b/va416xx/va416xx/src/eth/txexcessdef.rs new file mode 100644 index 0000000..2acc779 --- /dev/null +++ b/va416xx/va416xx/src/eth/txexcessdef.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXEXCESSDEF` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames aborted because of excessive deferral error\n\nYou can [`read`](crate::Reg::read) this register and get [`txexcessdef::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxexcessdefSpec; +impl crate::RegisterSpec for TxexcessdefSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txexcessdef::R`](R) reader structure"] +impl crate::Readable for TxexcessdefSpec {} +#[doc = "`reset()` method sets TXEXCESSDEF to value 0"] +impl crate::Resettable for TxexcessdefSpec {} diff --git a/va416xx/va416xx/src/eth/txexesscol.rs b/va416xx/va416xx/src/eth/txexesscol.rs new file mode 100644 index 0000000..dc62620 --- /dev/null +++ b/va416xx/va416xx/src/eth/txexesscol.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXEXESSCOL` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of aborted frames because of excessive collision errors\n\nYou can [`read`](crate::Reg::read) this register and get [`txexesscol::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxexesscolSpec; +impl crate::RegisterSpec for TxexesscolSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txexesscol::R`](R) reader structure"] +impl crate::Readable for TxexesscolSpec {} +#[doc = "`reset()` method sets TXEXESSCOL to value 0"] +impl crate::Resettable for TxexesscolSpec {} diff --git a/va416xx/va416xx/src/eth/txframecount_g.rs b/va416xx/va416xx/src/eth/txframecount_g.rs new file mode 100644 index 0000000..b5733aa --- /dev/null +++ b/va416xx/va416xx/src/eth/txframecount_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXFRAMECOUNT_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txframecount_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxframecountGSpec; +impl crate::RegisterSpec for TxframecountGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txframecount_g::R`](R) reader structure"] +impl crate::Readable for TxframecountGSpec {} +#[doc = "`reset()` method sets TXFRAMECOUNT_G to value 0"] +impl crate::Resettable for TxframecountGSpec {} diff --git a/va416xx/va416xx/src/eth/txframecount_gb.rs b/va416xx/va416xx/src/eth/txframecount_gb.rs new file mode 100644 index 0000000..cb0579a --- /dev/null +++ b/va416xx/va416xx/src/eth/txframecount_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXFRAMECOUNT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Frame Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txframecount_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxframecountGbSpec; +impl crate::RegisterSpec for TxframecountGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txframecount_gb::R`](R) reader structure"] +impl crate::Readable for TxframecountGbSpec {} +#[doc = "`reset()` method sets TXFRAMECOUNT_GB to value 0"] +impl crate::Resettable for TxframecountGbSpec {} diff --git a/va416xx/va416xx/src/eth/txlanframes_g.rs b/va416xx/va416xx/src/eth/txlanframes_g.rs new file mode 100644 index 0000000..b5a3707 --- /dev/null +++ b/va416xx/va416xx/src/eth/txlanframes_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXLANFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good VLAN frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txlanframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxlanframesGSpec; +impl crate::RegisterSpec for TxlanframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txlanframes_g::R`](R) reader structure"] +impl crate::Readable for TxlanframesGSpec {} +#[doc = "`reset()` method sets TXLANFRAMES_G to value 0"] +impl crate::Resettable for TxlanframesGSpec {} diff --git a/va416xx/va416xx/src/eth/txlatecol.rs b/va416xx/va416xx/src/eth/txlatecol.rs new file mode 100644 index 0000000..38fdb67 --- /dev/null +++ b/va416xx/va416xx/src/eth/txlatecol.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXLATECOL` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of aborted frames because of late collision error\n\nYou can [`read`](crate::Reg::read) this register and get [`txlatecol::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxlatecolSpec; +impl crate::RegisterSpec for TxlatecolSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txlatecol::R`](R) reader structure"] +impl crate::Readable for TxlatecolSpec {} +#[doc = "`reset()` method sets TXLATECOL to value 0"] +impl crate::Resettable for TxlatecolSpec {} diff --git a/va416xx/va416xx/src/eth/txmcastframe_gb.rs b/va416xx/va416xx/src/eth/txmcastframe_gb.rs new file mode 100644 index 0000000..36dd248 --- /dev/null +++ b/va416xx/va416xx/src/eth/txmcastframe_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXMCASTFRAME_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC number of good and bad MULTIcast frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txmcastframe_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxmcastframeGbSpec; +impl crate::RegisterSpec for TxmcastframeGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txmcastframe_gb::R`](R) reader structure"] +impl crate::Readable for TxmcastframeGbSpec {} +#[doc = "`reset()` method sets TXMCASTFRAME_GB to value 0"] +impl crate::Resettable for TxmcastframeGbSpec {} diff --git a/va416xx/va416xx/src/eth/txmcastframes_g.rs b/va416xx/va416xx/src/eth/txmcastframes_g.rs new file mode 100644 index 0000000..5556dd5 --- /dev/null +++ b/va416xx/va416xx/src/eth/txmcastframes_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXMCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good Multicast Frames Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txmcastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxmcastframesGSpec; +impl crate::RegisterSpec for TxmcastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txmcastframes_g::R`](R) reader structure"] +impl crate::Readable for TxmcastframesGSpec {} +#[doc = "`reset()` method sets TXMCASTFRAMES_G to value 0"] +impl crate::Resettable for TxmcastframesGSpec {} diff --git a/va416xx/va416xx/src/eth/txmulticol_g.rs b/va416xx/va416xx/src/eth/txmulticol_g.rs new file mode 100644 index 0000000..9c5f571 --- /dev/null +++ b/va416xx/va416xx/src/eth/txmulticol_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXMULTICOL_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of successfully transmitted frames after multiple collisions\n\nYou can [`read`](crate::Reg::read) this register and get [`txmulticol_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxmulticolGSpec; +impl crate::RegisterSpec for TxmulticolGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txmulticol_g::R`](R) reader structure"] +impl crate::Readable for TxmulticolGSpec {} +#[doc = "`reset()` method sets TXMULTICOL_G to value 0"] +impl crate::Resettable for TxmulticolGSpec {} diff --git a/va416xx/va416xx/src/eth/txoctetcount_g.rs b/va416xx/va416xx/src/eth/txoctetcount_g.rs new file mode 100644 index 0000000..5cf5343 --- /dev/null +++ b/va416xx/va416xx/src/eth/txoctetcount_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXOCTETCOUNT_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of bytes"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of bytes transmitted frames only in good frames\n\nYou can [`read`](crate::Reg::read) this register and get [`txoctetcount_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxoctetcountGSpec; +impl crate::RegisterSpec for TxoctetcountGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txoctetcount_g::R`](R) reader structure"] +impl crate::Readable for TxoctetcountGSpec {} +#[doc = "`reset()` method sets TXOCTETCOUNT_G to value 0"] +impl crate::Resettable for TxoctetcountGSpec {} diff --git a/va416xx/va416xx/src/eth/txoctetcount_gb.rs b/va416xx/va416xx/src/eth/txoctetcount_gb.rs new file mode 100644 index 0000000..b19c69f --- /dev/null +++ b/va416xx/va416xx/src/eth/txoctetcount_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXOCTETCOUNT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of bytes"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Transmit Count\n\nYou can [`read`](crate::Reg::read) this register and get [`txoctetcount_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxoctetcountGbSpec; +impl crate::RegisterSpec for TxoctetcountGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txoctetcount_gb::R`](R) reader structure"] +impl crate::Readable for TxoctetcountGbSpec {} +#[doc = "`reset()` method sets TXOCTETCOUNT_GB to value 0"] +impl crate::Resettable for TxoctetcountGbSpec {} diff --git a/va416xx/va416xx/src/eth/txoversize_g.rs b/va416xx/va416xx/src/eth/txoversize_g.rs new file mode 100644 index 0000000..29d598d --- /dev/null +++ b/va416xx/va416xx/src/eth/txoversize_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXOVERSIZE_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames transmitted without errors\n\nYou can [`read`](crate::Reg::read) this register and get [`txoversize_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxoversizeGSpec; +impl crate::RegisterSpec for TxoversizeGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txoversize_g::R`](R) reader structure"] +impl crate::Readable for TxoversizeGSpec {} +#[doc = "`reset()` method sets TXOVERSIZE_G to value 0"] +impl crate::Resettable for TxoversizeGSpec {} diff --git a/va416xx/va416xx/src/eth/txpauseframes.rs b/va416xx/va416xx/src/eth/txpauseframes.rs new file mode 100644 index 0000000..cbf34db --- /dev/null +++ b/va416xx/va416xx/src/eth/txpauseframes.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXPAUSEFRAMES` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good pause frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txpauseframes::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxpauseframesSpec; +impl crate::RegisterSpec for TxpauseframesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txpauseframes::R`](R) reader structure"] +impl crate::Readable for TxpauseframesSpec {} +#[doc = "`reset()` method sets TXPAUSEFRAMES to value 0"] +impl crate::Resettable for TxpauseframesSpec {} diff --git a/va416xx/va416xx/src/eth/txsinglecol_g.rs b/va416xx/va416xx/src/eth/txsinglecol_g.rs new file mode 100644 index 0000000..e791aaa --- /dev/null +++ b/va416xx/va416xx/src/eth/txsinglecol_g.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXSINGLECOL_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of successfully transmitted frames after a single collision\n\nYou can [`read`](crate::Reg::read) this register and get [`txsinglecol_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxsinglecolGSpec; +impl crate::RegisterSpec for TxsinglecolGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txsinglecol_g::R`](R) reader structure"] +impl crate::Readable for TxsinglecolGSpec {} +#[doc = "`reset()` method sets TXSINGLECOL_G to value 0"] +impl crate::Resettable for TxsinglecolGSpec {} diff --git a/va416xx/va416xx/src/eth/txucastframe_gb.rs b/va416xx/va416xx/src/eth/txucastframe_gb.rs new file mode 100644 index 0000000..bfcf1b8 --- /dev/null +++ b/va416xx/va416xx/src/eth/txucastframe_gb.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXUCASTFRAME_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC number of good and bad unicast frames transmitted\n\nYou can [`read`](crate::Reg::read) this register and get [`txucastframe_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxucastframeGbSpec; +impl crate::RegisterSpec for TxucastframeGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txucastframe_gb::R`](R) reader structure"] +impl crate::Readable for TxucastframeGbSpec {} +#[doc = "`reset()` method sets TXUCASTFRAME_GB to value 0"] +impl crate::Resettable for TxucastframeGbSpec {} diff --git a/va416xx/va416xx/src/eth/txundererr.rs b/va416xx/va416xx/src/eth/txundererr.rs new file mode 100644 index 0000000..33f08da --- /dev/null +++ b/va416xx/va416xx/src/eth/txundererr.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXUNDERERR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC number of frames aborted because of frame underflow error\n\nYou can [`read`](crate::Reg::read) this register and get [`txundererr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxundererrSpec; +impl crate::RegisterSpec for TxundererrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txundererr::R`](R) reader structure"] +impl crate::Readable for TxundererrSpec {} +#[doc = "`reset()` method sets TXUNDERERR to value 0"] +impl crate::Resettable for TxundererrSpec {} diff --git a/va416xx/va416xx/src/eth/vlan_hashtable.rs b/va416xx/va416xx/src/eth/vlan_hashtable.rs new file mode 100644 index 0000000..f8a1087 --- /dev/null +++ b/va416xx/va416xx/src/eth/vlan_hashtable.rs @@ -0,0 +1,35 @@ +#[doc = "Register `VLAN_HASHTABLE` reader"] +pub type R = crate::R; +#[doc = "Register `VLAN_HASHTABLE` writer"] +pub type W = crate::W; +#[doc = "Field `VLHT` reader - VLAN Hash Table"] +pub type VlhtR = crate::FieldReader; +#[doc = "Field `VLHT` writer - VLAN Hash Table"] +pub type VlhtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - VLAN Hash Table"] + #[inline(always)] + pub fn vlht(&self) -> VlhtR { + VlhtR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - VLAN Hash Table"] + #[inline(always)] + pub fn vlht(&mut self) -> VlhtW<'_, VlanHashtableSpec> { + VlhtW::new(self, 0) + } +} +#[doc = "Holds the VLAN Hash Table\n\nYou can [`read`](crate::Reg::read) this register and get [`vlan_hashtable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vlan_hashtable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VlanHashtableSpec; +impl crate::RegisterSpec for VlanHashtableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`vlan_hashtable::R`](R) reader structure"] +impl crate::Readable for VlanHashtableSpec {} +#[doc = "`write(|w| ..)` method takes [`vlan_hashtable::W`](W) writer structure"] +impl crate::Writable for VlanHashtableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets VLAN_HASHTABLE to value 0"] +impl crate::Resettable for VlanHashtableSpec {} diff --git a/va416xx/va416xx/src/eth/vlan_increplace.rs b/va416xx/va416xx/src/eth/vlan_increplace.rs new file mode 100644 index 0000000..e15afa0 --- /dev/null +++ b/va416xx/va416xx/src/eth/vlan_increplace.rs @@ -0,0 +1,77 @@ +#[doc = "Register `VLAN_INCREPLACE` reader"] +pub type R = crate::R; +#[doc = "Register `VLAN_INCREPLACE` writer"] +pub type W = crate::W; +#[doc = "Field `VLT` reader - VLAN Tag for Transmit Frames"] +pub type VltR = crate::FieldReader; +#[doc = "Field `VLT` writer - VLAN Tag for Transmit Frames"] +pub type VltW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `VLC` reader - VLAN Tag Control in Transmit Frames"] +pub type VlcR = crate::FieldReader; +#[doc = "Field `VLC` writer - VLAN Tag Control in Transmit Frames"] +pub type VlcW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `VLP` reader - VLAN Priority Control"] +pub type VlpR = crate::BitReader; +#[doc = "Field `VLP` writer - VLAN Priority Control"] +pub type VlpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSVL` reader - C-VLAN or S-VLAN"] +pub type CsvlR = crate::BitReader; +#[doc = "Field `CSVL` writer - C-VLAN or S-VLAN"] +pub type CsvlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - VLAN Tag for Transmit Frames"] + #[inline(always)] + pub fn vlt(&self) -> VltR { + VltR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:17 - VLAN Tag Control in Transmit Frames"] + #[inline(always)] + pub fn vlc(&self) -> VlcR { + VlcR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - VLAN Priority Control"] + #[inline(always)] + pub fn vlp(&self) -> VlpR { + VlpR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - C-VLAN or S-VLAN"] + #[inline(always)] + pub fn csvl(&self) -> CsvlR { + CsvlR::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - VLAN Tag for Transmit Frames"] + #[inline(always)] + pub fn vlt(&mut self) -> VltW<'_, VlanIncreplaceSpec> { + VltW::new(self, 0) + } + #[doc = "Bits 16:17 - VLAN Tag Control in Transmit Frames"] + #[inline(always)] + pub fn vlc(&mut self) -> VlcW<'_, VlanIncreplaceSpec> { + VlcW::new(self, 16) + } + #[doc = "Bit 18 - VLAN Priority Control"] + #[inline(always)] + pub fn vlp(&mut self) -> VlpW<'_, VlanIncreplaceSpec> { + VlpW::new(self, 18) + } + #[doc = "Bit 19 - C-VLAN or S-VLAN"] + #[inline(always)] + pub fn csvl(&mut self) -> CsvlW<'_, VlanIncreplaceSpec> { + CsvlW::new(self, 19) + } +} +#[doc = "Holds the VLAN Tag for insertion into or replacement in the transmit frames\n\nYou can [`read`](crate::Reg::read) this register and get [`vlan_increplace::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vlan_increplace::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VlanIncreplaceSpec; +impl crate::RegisterSpec for VlanIncreplaceSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`vlan_increplace::R`](R) reader structure"] +impl crate::Readable for VlanIncreplaceSpec {} +#[doc = "`write(|w| ..)` method takes [`vlan_increplace::W`](W) writer structure"] +impl crate::Writable for VlanIncreplaceSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets VLAN_INCREPLACE to value 0"] +impl crate::Resettable for VlanIncreplaceSpec {} diff --git a/va416xx/va416xx/src/generic.rs b/va416xx/va416xx/src/generic.rs new file mode 100644 index 0000000..1bb995a --- /dev/null +++ b/va416xx/va416xx/src/generic.rs @@ -0,0 +1,768 @@ +use core::marker; +#[doc = " Generic peripheral accessor"] +pub struct Periph { + _marker: marker::PhantomData, +} +unsafe impl Send for Periph {} +impl Periph { + #[doc = "Pointer to the register block"] + pub const PTR: *const RB = A as *const _; + #[doc = "Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const RB { + Self::PTR + } + #[doc = " Steal an instance of this peripheral"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = " that may race with any existing instances, for example by only"] + #[doc = " accessing read-only or write-only registers, or by consuming the"] + #[doc = " original peripheral and using critical sections to coordinate"] + #[doc = " access between multiple new instances."] + #[doc = ""] + #[doc = " Additionally, other software such as HALs may rely on only one"] + #[doc = " peripheral instance existing to ensure memory safety; ensure"] + #[doc = " no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: marker::PhantomData, + } + } +} +impl core::ops::Deref for Periph { + type Target = RB; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " `0`"] + const ZERO: Self; + #[doc = " `1`"] + const ONE: Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + const ZERO: Self = 0; + const ONE: Self = 1; + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + impl FieldSpec for $U { + type Ux = $U; + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + core::fmt::Debug + PartialEq + From; +} +#[doc = " Marker for fields with fixed values"] +pub trait IsEnum: FieldSpec {} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec {} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Is it safe to write any bits to register"] + type Safety; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux = Self::Ux::ZERO; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc(hidden)] +pub mod raw; +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub type R = raw::R; +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub const fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub type W = raw::W; +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +impl W +where + REG: Writable, +{ + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub fn set(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = raw::FieldReader; +#[doc = " Bit-wise field reader"] +pub type BitReader = raw::BitReader; +impl FieldReader { + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub const fn bits(&self) -> FI::Ux { + self.bits + } +} +impl core::fmt::Debug for FieldReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +impl PartialEq for FieldReader +where + FI: FieldSpec + Copy, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&FI::Ux::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub const fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub const fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub const fn bit_is_set(&self) -> bool { + self.bit() + } +} +impl core::fmt::Debug for BitReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +#[doc = " Marker for register/field writers which can take any value of specified width"] +pub struct Safe; +#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] +pub struct Unsafe; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct Range; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeFrom; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeTo; +#[doc = " Write field Proxy"] +pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> = + raw::FieldWriter<'a, REG, WI, FI, Safety>; +impl FieldWriter<'_, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } +} +impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64> + FieldWriter<'a, REG, WI, FI, Range> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN && value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: IsEnum, + REG::Ux: From, +{ + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; + impl<'a, REG, FI> $writer<'a, REG, FI> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + Self::WIDTH + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, REG, FI> BitWriter<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::ONE << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::ONE << self.o); + self.w + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> R { + R { + bits: self.register.get(), + _reg: marker::PhantomData, + } + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) -> REG::Ux + where + F: FnOnce(&mut W) -> &mut W, + { + let value = f(&mut W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }) + .bits; + self.register.set(value); + value + } + #[doc = " Writes bits to a `Writable` register and produce a value."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write_and(|w| {"] + #[doc = " w.field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write_and(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[doc = ""] + #[doc = " Values can be returned from the closure:"] + #[doc = " ```ignore"] + #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"] + #[doc = " ```"] + #[inline(always)] + pub fn from_write(&self, f: F) -> T + where + F: FnOnce(&mut W) -> T, + { + let mut writer = W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }; + let result = f(&mut writer); + self.register.set(writer.bits); + result + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) -> REG::Ux + where + F: FnOnce(&mut W) -> &mut W, + { + let value = f(&mut W { + bits: REG::Ux::ZERO, + _reg: marker::PhantomData, + }) + .bits; + self.register.set(value); + value + } + #[doc = " Writes 0 to a `Writable` register and produces a value."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn from_write_with_zero(&self, f: F) -> T + where + F: FnOnce(&mut W) -> T, + { + let mut writer = W { + bits: REG::Ux::ZERO, + _reg: marker::PhantomData, + }; + let result = f(&mut writer); + self.register.set(writer.bits); + result + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) -> REG::Ux + where + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, + { + let bits = self.register.get(); + let value = f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }, + ) + .bits; + self.register.set(value); + value + } + #[doc = " Modifies the contents of the register by reading and then writing it"] + #[doc = " and produces a value."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.modify(|r, w| {"] + #[doc = " let new_bits = r.bits() | 3;"] + #[doc = " unsafe {"] + #[doc = " w.bits(new_bits);"] + #[doc = " }"] + #[doc = ""] + #[doc = " new_bits"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT);"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn from_modify(&self, f: F) -> T + where + for<'w> F: FnOnce(&R, &'w mut W) -> T, + { + let bits = self.register.get(); + let mut writer = W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }; + let result = f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut writer, + ); + self.register.set(writer.bits); + result + } +} +impl core::fmt::Debug for crate::generic::Reg +where + R: core::fmt::Debug, +{ + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} diff --git a/va416xx/va416xx/src/generic/raw.rs b/va416xx/va416xx/src/generic/raw.rs new file mode 100644 index 0000000..d60a23a --- /dev/null +++ b/va416xx/va416xx/src/generic/raw.rs @@ -0,0 +1,95 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[must_use = "after creating `FieldWriter` you need to call field value setting method"] +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} +#[must_use = "after creating `BitWriter` you need to call bit setting method"] +pub struct BitWriter<'a, REG, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} diff --git a/va416xx/va416xx/src/i2c0.rs b/va416xx/va416xx/src/i2c0.rs new file mode 100644 index 0000000..dd08121 --- /dev/null +++ b/va416xx/va416xx/src/i2c0.rs @@ -0,0 +1,419 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + clkscale: Clkscale, + words: Words, + address: Address, + data: Data, + cmd: Cmd, + status: Status, + state: State, + txcount: Txcount, + rxcount: Rxcount, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + txfifoirqtrg: Txfifoirqtrg, + fifo_clr: FifoClr, + tmconfig: Tmconfig, + clktolimit: Clktolimit, + _reserved19: [u8; 0xb4], + s0_ctrl: S0Ctrl, + s0_maxwords: S0Maxwords, + s0_address: S0Address, + s0_addressmask: S0Addressmask, + s0_data: S0Data, + s0_lastaddress: S0Lastaddress, + s0_status: S0Status, + s0_state: S0State, + s0_txcount: S0Txcount, + s0_rxcount: S0Rxcount, + s0_irq_enb: S0IrqEnb, + s0_irq_raw: S0IrqRaw, + s0_irq_end: S0IrqEnd, + s0_irq_clr: S0IrqClr, + s0_rxfifoirqtrg: S0Rxfifoirqtrg, + s0_txfifoirqtrg: S0Txfifoirqtrg, + s0_fifo_clr: S0FifoClr, + s0_addressb: S0Addressb, + s0_addressmaskb: S0Addressmaskb, + _reserved38: [u8; 0x02b0], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - Clock Scale divide value"] + #[inline(always)] + pub const fn clkscale(&self) -> &Clkscale { + &self.clkscale + } + #[doc = "0x08 - Word Count value"] + #[inline(always)] + pub const fn words(&self) -> &Words { + &self.words + } + #[doc = "0x0c - I2C Address value"] + #[inline(always)] + pub const fn address(&self) -> &Address { + &self.address + } + #[doc = "0x10 - Data Input/Output"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x14 - Command Register"] + #[inline(always)] + pub const fn cmd(&self) -> &Cmd { + &self.cmd + } + #[doc = "0x18 - I2C Controller Status Register"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x1c - Internal STATE of I2C Master Controller"] + #[inline(always)] + pub const fn state(&self) -> &State { + &self.state + } + #[doc = "0x20 - TX Count Register"] + #[inline(always)] + pub const fn txcount(&self) -> &Txcount { + &self.txcount + } + #[doc = "0x24 - RX Count Register"] + #[inline(always)] + pub const fn rxcount(&self) -> &Rxcount { + &self.rxcount + } + #[doc = "0x28 - Interrupt Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x2c - Raw Interrupt Status Register"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x30 - Enabled Interrupt Status Register"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x34 - Clear Interrupt Status Register"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x38 - Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x3c - Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x40 - Clear FIFO Register"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x44 - Timing Config Register"] + #[inline(always)] + pub const fn tmconfig(&self) -> &Tmconfig { + &self.tmconfig + } + #[doc = "0x48 - Clock Low Timeout Limit Register"] + #[inline(always)] + pub const fn clktolimit(&self) -> &Clktolimit { + &self.clktolimit + } + #[doc = "0x100 - Slave Control Register"] + #[inline(always)] + pub const fn s0_ctrl(&self) -> &S0Ctrl { + &self.s0_ctrl + } + #[doc = "0x104 - Slave MaxWords Register"] + #[inline(always)] + pub const fn s0_maxwords(&self) -> &S0Maxwords { + &self.s0_maxwords + } + #[doc = "0x108 - Slave I2C Address Value"] + #[inline(always)] + pub const fn s0_address(&self) -> &S0Address { + &self.s0_address + } + #[doc = "0x10c - Slave I2C Address Mask value"] + #[inline(always)] + pub const fn s0_addressmask(&self) -> &S0Addressmask { + &self.s0_addressmask + } + #[doc = "0x110 - Slave Data Input/Output"] + #[inline(always)] + pub const fn s0_data(&self) -> &S0Data { + &self.s0_data + } + #[doc = "0x114 - Slave I2C Last Address value"] + #[inline(always)] + pub const fn s0_lastaddress(&self) -> &S0Lastaddress { + &self.s0_lastaddress + } + #[doc = "0x118 - Slave I2C Controller Status Register"] + #[inline(always)] + pub const fn s0_status(&self) -> &S0Status { + &self.s0_status + } + #[doc = "0x11c - Internal STATE of I2C Slave Controller"] + #[inline(always)] + pub const fn s0_state(&self) -> &S0State { + &self.s0_state + } + #[doc = "0x120 - Slave TX Count Register"] + #[inline(always)] + pub const fn s0_txcount(&self) -> &S0Txcount { + &self.s0_txcount + } + #[doc = "0x124 - Slave RX Count Register"] + #[inline(always)] + pub const fn s0_rxcount(&self) -> &S0Rxcount { + &self.s0_rxcount + } + #[doc = "0x128 - Slave Interrupt Enable Register"] + #[inline(always)] + pub const fn s0_irq_enb(&self) -> &S0IrqEnb { + &self.s0_irq_enb + } + #[doc = "0x12c - Slave Raw Interrupt Status Register"] + #[inline(always)] + pub const fn s0_irq_raw(&self) -> &S0IrqRaw { + &self.s0_irq_raw + } + #[doc = "0x130 - Slave Enabled Interrupt Status Register"] + #[inline(always)] + pub const fn s0_irq_end(&self) -> &S0IrqEnd { + &self.s0_irq_end + } + #[doc = "0x134 - Slave Clear Interrupt Status Register"] + #[inline(always)] + pub const fn s0_irq_clr(&self) -> &S0IrqClr { + &self.s0_irq_clr + } + #[doc = "0x138 - Slave Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn s0_rxfifoirqtrg(&self) -> &S0Rxfifoirqtrg { + &self.s0_rxfifoirqtrg + } + #[doc = "0x13c - Slave Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn s0_txfifoirqtrg(&self) -> &S0Txfifoirqtrg { + &self.s0_txfifoirqtrg + } + #[doc = "0x140 - Slave Clear FIFO Register"] + #[inline(always)] + pub const fn s0_fifo_clr(&self) -> &S0FifoClr { + &self.s0_fifo_clr + } + #[doc = "0x144 - Slave I2C Address B Value"] + #[inline(always)] + pub const fn s0_addressb(&self) -> &S0Addressb { + &self.s0_addressb + } + #[doc = "0x148 - Slave I2C Address B Mask value"] + #[inline(always)] + pub const fn s0_addressmaskb(&self) -> &S0Addressmaskb { + &self.s0_addressmaskb + } + #[doc = "0x3fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] module"] +#[doc(alias = "CLKSCALE")] +pub type Clkscale = crate::Reg; +#[doc = "Clock Scale divide value"] +pub mod clkscale; +#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`] module"] +#[doc(alias = "WORDS")] +pub type Words = crate::Reg; +#[doc = "Word Count value"] +pub mod words; +#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`] module"] +#[doc(alias = "ADDRESS")] +pub type Address = crate::Reg; +#[doc = "I2C Address value"] +pub mod address; +#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data Input/Output"] +pub mod data; +#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"] +#[doc(alias = "CMD")] +pub type Cmd = crate::Reg; +#[doc = "Command Register"] +pub mod cmd; +#[doc = "STATUS (rw) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "I2C Controller Status Register"] +pub mod status; +#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +#[doc(alias = "STATE")] +pub type State = crate::Reg; +#[doc = "Internal STATE of I2C Master Controller"] +pub mod state; +#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`] module"] +#[doc(alias = "TXCOUNT")] +pub type Txcount = crate::Reg; +#[doc = "TX Count Register"] +pub mod txcount; +#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`] module"] +#[doc(alias = "RXCOUNT")] +pub type Rxcount = crate::Reg; +#[doc = "RX Count Register"] +pub mod rxcount; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`] module"] +#[doc(alias = "TMCONFIG")] +pub type Tmconfig = crate::Reg; +#[doc = "Timing Config Register"] +pub mod tmconfig; +#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`] module"] +#[doc(alias = "CLKTOLIMIT")] +pub type Clktolimit = crate::Reg; +#[doc = "Clock Low Timeout Limit Register"] +pub mod clktolimit; +#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`] module"] +#[doc(alias = "S0_CTRL")] +pub type S0Ctrl = crate::Reg; +#[doc = "Slave Control Register"] +pub mod s0_ctrl; +#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`] module"] +#[doc(alias = "S0_MAXWORDS")] +pub type S0Maxwords = crate::Reg; +#[doc = "Slave MaxWords Register"] +pub mod s0_maxwords; +#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`] module"] +#[doc(alias = "S0_ADDRESS")] +pub type S0Address = crate::Reg; +#[doc = "Slave I2C Address Value"] +pub mod s0_address; +#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`] module"] +#[doc(alias = "S0_ADDRESSMASK")] +pub type S0Addressmask = crate::Reg; +#[doc = "Slave I2C Address Mask value"] +pub mod s0_addressmask; +#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`] module"] +#[doc(alias = "S0_DATA")] +pub type S0Data = crate::Reg; +#[doc = "Slave Data Input/Output"] +pub mod s0_data; +#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`] module"] +#[doc(alias = "S0_LASTADDRESS")] +pub type S0Lastaddress = crate::Reg; +#[doc = "Slave I2C Last Address value"] +pub mod s0_lastaddress; +#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`] module"] +#[doc(alias = "S0_STATUS")] +pub type S0Status = crate::Reg; +#[doc = "Slave I2C Controller Status Register"] +pub mod s0_status; +#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`] module"] +#[doc(alias = "S0_STATE")] +pub type S0State = crate::Reg; +#[doc = "Internal STATE of I2C Slave Controller"] +pub mod s0_state; +#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`] module"] +#[doc(alias = "S0_TXCOUNT")] +pub type S0Txcount = crate::Reg; +#[doc = "Slave TX Count Register"] +pub mod s0_txcount; +#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`] module"] +#[doc(alias = "S0_RXCOUNT")] +pub type S0Rxcount = crate::Reg; +#[doc = "Slave RX Count Register"] +pub mod s0_rxcount; +#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`] module"] +#[doc(alias = "S0_IRQ_ENB")] +pub type S0IrqEnb = crate::Reg; +#[doc = "Slave Interrupt Enable Register"] +pub mod s0_irq_enb; +pub use s0_irq_enb as s0_irq_raw; +pub use s0_irq_enb as s0_irq_end; +pub use s0_irq_enb as s0_irq_clr; +pub use S0IrqEnb as S0IrqRaw; +pub use S0IrqEnb as S0IrqEnd; +pub use S0IrqEnb as S0IrqClr; +#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`] module"] +#[doc(alias = "S0_RXFIFOIRQTRG")] +pub type S0Rxfifoirqtrg = crate::Reg; +#[doc = "Slave Rx FIFO IRQ Trigger Level"] +pub mod s0_rxfifoirqtrg; +#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`] module"] +#[doc(alias = "S0_TXFIFOIRQTRG")] +pub type S0Txfifoirqtrg = crate::Reg; +#[doc = "Slave Tx FIFO IRQ Trigger Level"] +pub mod s0_txfifoirqtrg; +#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`] module"] +#[doc(alias = "S0_FIFO_CLR")] +pub type S0FifoClr = crate::Reg; +#[doc = "Slave Clear FIFO Register"] +pub mod s0_fifo_clr; +#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`] module"] +#[doc(alias = "S0_ADDRESSB")] +pub type S0Addressb = crate::Reg; +#[doc = "Slave I2C Address B Value"] +pub mod s0_addressb; +#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`] module"] +#[doc(alias = "S0_ADDRESSMASKB")] +pub type S0Addressmaskb = crate::Reg; +#[doc = "Slave I2C Address B Mask value"] +pub mod s0_addressmaskb; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/i2c0/address.rs b/va416xx/va416xx/src/i2c0/address.rs new file mode 100644 index 0000000..af668ea --- /dev/null +++ b/va416xx/va416xx/src/i2c0/address.rs @@ -0,0 +1,24 @@ +#[doc = "Register `ADDRESS` reader"] +pub type R = crate::R; +#[doc = "Register `ADDRESS` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AddressSpec; +impl crate::RegisterSpec for AddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`address::R`](R) reader structure"] +impl crate::Readable for AddressSpec {} +#[doc = "`write(|w| ..)` method takes [`address::W`](W) writer structure"] +impl crate::Writable for AddressSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADDRESS to value 0"] +impl crate::Resettable for AddressSpec {} diff --git a/va416xx/va416xx/src/i2c0/clkscale.rs b/va416xx/va416xx/src/i2c0/clkscale.rs new file mode 100644 index 0000000..1562308 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/clkscale.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CLKSCALE` reader"] +pub type R = crate::R; +#[doc = "Register `CLKSCALE` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` reader - Enable FastMode"] +pub type ValueR = crate::FieldReader; +#[doc = "Field `VALUE` writer - Enable FastMode"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `FASTMODE` reader - Enable FastMode"] +pub type FastmodeR = crate::BitReader; +#[doc = "Field `FASTMODE` writer - Enable FastMode"] +pub type FastmodeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - Enable FastMode"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - Enable FastMode"] + #[inline(always)] + pub fn fastmode(&self) -> FastmodeR { + FastmodeR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:30 - Enable FastMode"] + #[inline(always)] + pub fn value(&mut self) -> ValueW<'_, ClkscaleSpec> { + ValueW::new(self, 0) + } + #[doc = "Bit 31 - Enable FastMode"] + #[inline(always)] + pub fn fastmode(&mut self) -> FastmodeW<'_, ClkscaleSpec> { + FastmodeW::new(self, 31) + } +} +#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkscaleSpec; +impl crate::RegisterSpec for ClkscaleSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkscale::R`](R) reader structure"] +impl crate::Readable for ClkscaleSpec {} +#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"] +impl crate::Writable for ClkscaleSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKSCALE to value 0"] +impl crate::Resettable for ClkscaleSpec {} diff --git a/va416xx/va416xx/src/i2c0/clktolimit.rs b/va416xx/va416xx/src/i2c0/clktolimit.rs new file mode 100644 index 0000000..fa91d73 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/clktolimit.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKTOLIMIT` reader"] +pub type R = crate::R; +#[doc = "Register `CLKTOLIMIT` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClktolimitSpec; +impl crate::RegisterSpec for ClktolimitSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clktolimit::R`](R) reader structure"] +impl crate::Readable for ClktolimitSpec {} +#[doc = "`write(|w| ..)` method takes [`clktolimit::W`](W) writer structure"] +impl crate::Writable for ClktolimitSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKTOLIMIT to value 0"] +impl crate::Resettable for ClktolimitSpec {} diff --git a/va416xx/va416xx/src/i2c0/cmd.rs b/va416xx/va416xx/src/i2c0/cmd.rs new file mode 100644 index 0000000..bc295f0 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/cmd.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CMD` reader"] +pub type R = crate::R; +#[doc = "Register `CMD` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CmdSpec; +impl crate::RegisterSpec for CmdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmd::R`](R) reader structure"] +impl crate::Readable for CmdSpec {} +#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"] +impl crate::Writable for CmdSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CMD to value 0"] +impl crate::Resettable for CmdSpec {} diff --git a/va416xx/va416xx/src/i2c0/ctrl.rs b/va416xx/va416xx/src/i2c0/ctrl.rs new file mode 100644 index 0000000..cdd52e2 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/ctrl.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CLKENABLED` reader - I2C CLK Enabled"] +pub type ClkenabledR = crate::BitReader; +#[doc = "Field `CLKENABLED` writer - I2C CLK Enabled"] +pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - I2C Activated"] +pub type EnabledR = crate::BitReader; +#[doc = "Field `ENABLED` writer - I2C Activated"] +pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - I2C Active"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - I2C Active"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"] +pub type TxfemdR = crate::BitReader; +#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"] +pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"] +pub type RxffmdR = crate::BitReader; +#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"] +pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALGFILTER` reader - Enable Input Analog Glitch Filter"] +pub type AlgfilterR = crate::BitReader; +#[doc = "Field `ALGFILTER` writer - Enable Input Analog Glitch Filter"] +pub type AlgfilterW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DLGFILTER` reader - Enable Input Digital Glitch Filter"] +pub type DlgfilterR = crate::BitReader; +#[doc = "Field `DLGFILTER` writer - Enable Input Digital Glitch Filter"] +pub type DlgfilterW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACK` reader - Enable LoopBack Mode"] +pub type LoopbackR = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Enable LoopBack Mode"] +pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMCONFIGENB` reader - Enable Timing Config Register"] +pub type TmconfigenbR = crate::BitReader; +#[doc = "Field `TMCONFIGENB` writer - Enable Timing Config Register"] +pub type TmconfigenbW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C CLK Enabled"] + #[inline(always)] + pub fn clkenabled(&self) -> ClkenabledR { + ClkenabledR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&self) -> EnabledR { + EnabledR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&self) -> TxfemdR { + TxfemdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&self) -> RxffmdR { + RxffmdR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable Input Analog Glitch Filter"] + #[inline(always)] + pub fn algfilter(&self) -> AlgfilterR { + AlgfilterR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable Input Digital Glitch Filter"] + #[inline(always)] + pub fn dlgfilter(&self) -> DlgfilterR { + DlgfilterR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Enable LoopBack Mode"] + #[inline(always)] + pub fn loopback(&self) -> LoopbackR { + LoopbackR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable Timing Config Register"] + #[inline(always)] + pub fn tmconfigenb(&self) -> TmconfigenbR { + TmconfigenbR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C CLK Enabled"] + #[inline(always)] + pub fn clkenabled(&mut self) -> ClkenabledW<'_, CtrlSpec> { + ClkenabledW::new(self, 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&mut self) -> EnabledW<'_, CtrlSpec> { + EnabledW::new(self, 1) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, CtrlSpec> { + EnableW::new(self, 2) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&mut self) -> TxfemdW<'_, CtrlSpec> { + TxfemdW::new(self, 3) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&mut self) -> RxffmdW<'_, CtrlSpec> { + RxffmdW::new(self, 4) + } + #[doc = "Bit 5 - Enable Input Analog Glitch Filter"] + #[inline(always)] + pub fn algfilter(&mut self) -> AlgfilterW<'_, CtrlSpec> { + AlgfilterW::new(self, 5) + } + #[doc = "Bit 6 - Enable Input Digital Glitch Filter"] + #[inline(always)] + pub fn dlgfilter(&mut self) -> DlgfilterW<'_, CtrlSpec> { + DlgfilterW::new(self, 6) + } + #[doc = "Bit 8 - Enable LoopBack Mode"] + #[inline(always)] + pub fn loopback(&mut self) -> LoopbackW<'_, CtrlSpec> { + LoopbackW::new(self, 8) + } + #[doc = "Bit 9 - Enable Timing Config Register"] + #[inline(always)] + pub fn tmconfigenb(&mut self) -> TmconfigenbW<'_, CtrlSpec> { + TmconfigenbW::new(self, 9) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/va416xx/va416xx/src/i2c0/data.rs b/va416xx/va416xx/src/i2c0/data.rs new file mode 100644 index 0000000..8968f26 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/data.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec {} diff --git a/va416xx/va416xx/src/i2c0/fifo_clr.rs b/va416xx/va416xx/src/i2c0/fifo_clr.rs new file mode 100644 index 0000000..339ac41 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/fifo_clr.rs @@ -0,0 +1,29 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> { + TxfifoW::new(self, 1) + } +} +#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec {} diff --git a/va416xx/va416xx/src/i2c0/irq_enb.rs b/va416xx/va416xx/src/i2c0/irq_enb.rs new file mode 100644 index 0000000..df35253 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/irq_enb.rs @@ -0,0 +1,217 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"] +pub type I2cidleR = crate::BitReader; +#[doc = "Field `I2CIDLE` writer - I2C Bus is Idle"] +pub type I2cidleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub type StalledR = crate::BitReader; +#[doc = "Field `STALLED` writer - Controller is Stalled"] +pub type StalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub type ArblostR = crate::BitReader; +#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"] +pub type ArblostW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub type NackaddrR = crate::BitReader; +#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"] +pub type NackaddrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"] +pub type ClklotoR = crate::BitReader; +#[doc = "Field `CLKLOTO` writer - I2C Clock Low Timeout"] +pub type ClklotoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"] +pub type TxoverflowR = crate::BitReader; +#[doc = "Field `TXOVERFLOW` writer - TX FIFO Overflowed"] +pub type TxoverflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub type RxoverflowR = crate::BitReader; +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub type TxreadyR = crate::BitReader; +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub type RxreadyR = crate::BitReader; +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&self) -> I2cidleR { + I2cidleR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> StalledR { + StalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ArblostR { + ArblostR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NackaddrR { + NackaddrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&self) -> ClklotoR { + ClklotoR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&self) -> TxoverflowR { + TxoverflowR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RxoverflowR { + RxoverflowR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TxreadyR { + TxreadyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RxreadyR { + RxreadyR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&mut self) -> I2cidleW<'_, IrqEnbSpec> { + I2cidleW::new(self, 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IdleW<'_, IrqEnbSpec> { + IdleW::new(self, 1) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WaitingW<'_, IrqEnbSpec> { + WaitingW::new(self, 2) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&mut self) -> StalledW<'_, IrqEnbSpec> { + StalledW::new(self, 3) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ArblostW<'_, IrqEnbSpec> { + ArblostW::new(self, 4) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&mut self) -> NackaddrW<'_, IrqEnbSpec> { + NackaddrW::new(self, 5) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NackdataW<'_, IrqEnbSpec> { + NackdataW::new(self, 6) + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&mut self) -> ClklotoW<'_, IrqEnbSpec> { + ClklotoW::new(self, 7) + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&mut self) -> TxoverflowW<'_, IrqEnbSpec> { + TxoverflowW::new(self, 10) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&mut self) -> RxoverflowW<'_, IrqEnbSpec> { + RxoverflowW::new(self, 11) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&mut self) -> TxreadyW<'_, IrqEnbSpec> { + TxreadyW::new(self, 12) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&mut self) -> RxreadyW<'_, IrqEnbSpec> { + RxreadyW::new(self, 13) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TxemptyW<'_, IrqEnbSpec> { + TxemptyW::new(self, 14) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RxfullW<'_, IrqEnbSpec> { + RxfullW::new(self, 15) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va416xx/va416xx/src/i2c0/perid.rs b/va416xx/va416xx/src/i2c0/perid.rs new file mode 100644 index 0000000..2f71382 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0214_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0214_07e9; +} diff --git a/va416xx/va416xx/src/i2c0/rxcount.rs b/va416xx/va416xx/src/i2c0/rxcount.rs new file mode 100644 index 0000000..eb4e7c1 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/rxcount.rs @@ -0,0 +1,17 @@ +#[doc = "Register `RXCOUNT` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxcountSpec; +impl crate::RegisterSpec for RxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxcount::R`](R) reader structure"] +impl crate::Readable for RxcountSpec {} +#[doc = "`reset()` method sets RXCOUNT to value 0"] +impl crate::Resettable for RxcountSpec {} diff --git a/va416xx/va416xx/src/i2c0/rxfifoirqtrg.rs b/va416xx/va416xx/src/i2c0/rxfifoirqtrg.rs new file mode 100644 index 0000000..e38d450 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/rxfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RxfifoirqtrgSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_address.rs b/va416xx/va416xx/src/i2c0/s0_address.rs new file mode 100644 index 0000000..5d3e659 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_address.rs @@ -0,0 +1,63 @@ +#[doc = "Register `S0_ADDRESS` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESS` writer"] +pub type W = crate::W; +#[doc = "Field `RW` reader - Read/Write value"] +pub type RwR = crate::BitReader; +#[doc = "Field `RW` writer - Read/Write value"] +pub type RwW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDRESS` reader - Address value"] +pub type AddressR = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - Address value"] +pub type AddressW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `A10MODE` reader - Enable 10b address mode"] +pub type A10modeR = crate::BitReader; +#[doc = "Field `A10MODE` writer - Enable 10b address mode"] +pub type A10modeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Read/Write value"] + #[inline(always)] + pub fn rw(&self) -> RwR { + RwR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&self) -> AddressR { + AddressR::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Enable 10b address mode"] + #[inline(always)] + pub fn a10mode(&self) -> A10modeR { + A10modeR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Read/Write value"] + #[inline(always)] + pub fn rw(&mut self) -> RwW<'_, S0AddressSpec> { + RwW::new(self, 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&mut self) -> AddressW<'_, S0AddressSpec> { + AddressW::new(self, 1) + } + #[doc = "Bit 15 - Enable 10b address mode"] + #[inline(always)] + pub fn a10mode(&mut self) -> A10modeW<'_, S0AddressSpec> { + A10modeW::new(self, 15) + } +} +#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressSpec; +impl crate::RegisterSpec for S0AddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_address::R`](R) reader structure"] +impl crate::Readable for S0AddressSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_address::W`](W) writer structure"] +impl crate::Writable for S0AddressSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_ADDRESS to value 0"] +impl crate::Resettable for S0AddressSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_addressb.rs b/va416xx/va416xx/src/i2c0/s0_addressb.rs new file mode 100644 index 0000000..dbdce92 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_addressb.rs @@ -0,0 +1,63 @@ +#[doc = "Register `S0_ADDRESSB` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESSB` writer"] +pub type W = crate::W; +#[doc = "Field `RW` reader - Read write value"] +pub type RwR = crate::BitReader; +#[doc = "Field `RW` writer - Read write value"] +pub type RwW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDRESS` reader - Address value"] +pub type AddressR = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - Address value"] +pub type AddressW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `ADDRESSBEN` reader - Enable Address B"] +pub type AddressbenR = crate::BitReader; +#[doc = "Field `ADDRESSBEN` writer - Enable Address B"] +pub type AddressbenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Read write value"] + #[inline(always)] + pub fn rw(&self) -> RwR { + RwR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&self) -> AddressR { + AddressR::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Enable Address B"] + #[inline(always)] + pub fn addressben(&self) -> AddressbenR { + AddressbenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Read write value"] + #[inline(always)] + pub fn rw(&mut self) -> RwW<'_, S0AddressbSpec> { + RwW::new(self, 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&mut self) -> AddressW<'_, S0AddressbSpec> { + AddressW::new(self, 1) + } + #[doc = "Bit 15 - Enable Address B"] + #[inline(always)] + pub fn addressben(&mut self) -> AddressbenW<'_, S0AddressbSpec> { + AddressbenW::new(self, 15) + } +} +#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressbSpec; +impl crate::RegisterSpec for S0AddressbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_addressb::R`](R) reader structure"] +impl crate::Readable for S0AddressbSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_addressb::W`](W) writer structure"] +impl crate::Writable for S0AddressbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_ADDRESSB to value 0"] +impl crate::Resettable for S0AddressbSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_addressmask.rs b/va416xx/va416xx/src/i2c0/s0_addressmask.rs new file mode 100644 index 0000000..1d7e82b --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_addressmask.rs @@ -0,0 +1,49 @@ +#[doc = "Register `S0_ADDRESSMASK` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESSMASK` writer"] +pub type W = crate::W; +#[doc = "Field `RWMASK` reader - Read/Write mask"] +pub type RwmaskR = crate::BitReader; +#[doc = "Field `RWMASK` writer - Read/Write mask"] +pub type RwmaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK` reader - Address mask value"] +pub type MaskR = crate::FieldReader; +#[doc = "Field `MASK` writer - Address mask value"] +pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bit 0 - Read/Write mask"] + #[inline(always)] + pub fn rwmask(&self) -> RwmaskR { + RwmaskR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&self) -> MaskR { + MaskR::new(((self.bits >> 1) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Read/Write mask"] + #[inline(always)] + pub fn rwmask(&mut self) -> RwmaskW<'_, S0AddressmaskSpec> { + RwmaskW::new(self, 0) + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&mut self) -> MaskW<'_, S0AddressmaskSpec> { + MaskW::new(self, 1) + } +} +#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressmaskSpec; +impl crate::RegisterSpec for S0AddressmaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_addressmask::R`](R) reader structure"] +impl crate::Readable for S0AddressmaskSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_addressmask::W`](W) writer structure"] +impl crate::Writable for S0AddressmaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"] +impl crate::Resettable for S0AddressmaskSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_addressmaskb.rs b/va416xx/va416xx/src/i2c0/s0_addressmaskb.rs new file mode 100644 index 0000000..f13b6e6 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_addressmaskb.rs @@ -0,0 +1,51 @@ +#[doc = "Register `S0_ADDRESSMASKB` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESSMASKB` writer"] +pub type W = crate::W; +#[doc = "Field `RWMASK` reader - Read write mask"] +pub type RwmaskR = crate::BitReader; +#[doc = "Field `RWMASK` writer - Read write mask"] +pub type RwmaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK` reader - Address mask value"] +pub type MaskR = crate::FieldReader; +#[doc = "Field `MASK` writer - Address mask value"] +pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bit 0 - Read write mask"] + #[inline(always)] + pub fn rwmask(&self) -> RwmaskR { + RwmaskR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&self) -> MaskR { + MaskR::new(((self.bits >> 1) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Read write mask"] + #[inline(always)] + pub fn rwmask(&mut self) -> RwmaskW<'_, S0AddressmaskbSpec> { + RwmaskW::new(self, 0) + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&mut self) -> MaskW<'_, S0AddressmaskbSpec> { + MaskW::new(self, 1) + } +} +#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressmaskbSpec; +impl crate::RegisterSpec for S0AddressmaskbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_addressmaskb::R`](R) reader structure"] +impl crate::Readable for S0AddressmaskbSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_addressmaskb::W`](W) writer structure"] +impl crate::Writable for S0AddressmaskbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0x07fe"] +impl crate::Resettable for S0AddressmaskbSpec { + const RESET_VALUE: u32 = 0x07fe; +} diff --git a/va416xx/va416xx/src/i2c0/s0_ctrl.rs b/va416xx/va416xx/src/i2c0/s0_ctrl.rs new file mode 100644 index 0000000..0bfde74 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_ctrl.rs @@ -0,0 +1,91 @@ +#[doc = "Register `S0_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `S0_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CLKENABLED` reader - I2C Enabled"] +pub type ClkenabledR = crate::BitReader; +#[doc = "Field `CLKENABLED` writer - I2C Enabled"] +pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - I2C Activated"] +pub type EnabledR = crate::BitReader; +#[doc = "Field `ENABLED` writer - I2C Activated"] +pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - I2C Active"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - I2C Active"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"] +pub type TxfemdR = crate::BitReader; +#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"] +pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"] +pub type RxffmdR = crate::BitReader; +#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"] +pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C Enabled"] + #[inline(always)] + pub fn clkenabled(&self) -> ClkenabledR { + ClkenabledR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&self) -> EnabledR { + EnabledR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&self) -> TxfemdR { + TxfemdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&self) -> RxffmdR { + RxffmdR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C Enabled"] + #[inline(always)] + pub fn clkenabled(&mut self) -> ClkenabledW<'_, S0CtrlSpec> { + ClkenabledW::new(self, 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&mut self) -> EnabledW<'_, S0CtrlSpec> { + EnabledW::new(self, 1) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, S0CtrlSpec> { + EnableW::new(self, 2) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&mut self) -> TxfemdW<'_, S0CtrlSpec> { + TxfemdW::new(self, 3) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&mut self) -> RxffmdW<'_, S0CtrlSpec> { + RxffmdW::new(self, 4) + } +} +#[doc = "Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0CtrlSpec; +impl crate::RegisterSpec for S0CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_ctrl::R`](R) reader structure"] +impl crate::Readable for S0CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_ctrl::W`](W) writer structure"] +impl crate::Writable for S0CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_CTRL to value 0"] +impl crate::Resettable for S0CtrlSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_data.rs b/va416xx/va416xx/src/i2c0/s0_data.rs new file mode 100644 index 0000000..aa7c40a --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_data.rs @@ -0,0 +1,35 @@ +#[doc = "Register `S0_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `S0_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` reader - I2C data value"] +pub type ValueR = crate::FieldReader; +#[doc = "Field `VALUE` writer - I2C data value"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - I2C data value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - I2C data value"] + #[inline(always)] + pub fn value(&mut self) -> ValueW<'_, S0DataSpec> { + ValueW::new(self, 0) + } +} +#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0DataSpec; +impl crate::RegisterSpec for S0DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_data::R`](R) reader structure"] +impl crate::Readable for S0DataSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_data::W`](W) writer structure"] +impl crate::Writable for S0DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_DATA to value 0"] +impl crate::Resettable for S0DataSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_fifo_clr.rs b/va416xx/va416xx/src/i2c0/s0_fifo_clr.rs new file mode 100644 index 0000000..b36d3e2 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_fifo_clr.rs @@ -0,0 +1,29 @@ +#[doc = "Register `S0_FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RxfifoW<'_, S0FifoClrSpec> { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TxfifoW<'_, S0FifoClrSpec> { + TxfifoW::new(self, 1) + } +} +#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0FifoClrSpec; +impl crate::RegisterSpec for S0FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`s0_fifo_clr::W`](W) writer structure"] +impl crate::Writable for S0FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_FIFO_CLR to value 0"] +impl crate::Resettable for S0FifoClrSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_irq_enb.rs b/va416xx/va416xx/src/i2c0/s0_irq_enb.rs new file mode 100644 index 0000000..47e6f08 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_irq_enb.rs @@ -0,0 +1,245 @@ +#[doc = "Register `S0_IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `S0_IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub type CompletedR = crate::BitReader; +#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"] +pub type CompletedW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub type TxstalledR = crate::BitReader; +#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"] +pub type TxstalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub type RxstalledR = crate::BitReader; +#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"] +pub type RxstalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub type AddressmatchR = crate::BitReader; +#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"] +pub type AddressmatchW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub type RxdatafirstR = crate::BitReader; +#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"] +pub type RxdatafirstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_START` reader - I2C Start Condition"] +pub type I2cStartR = crate::BitReader; +#[doc = "Field `I2C_START` writer - I2C Start Condition"] +pub type I2cStartW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"] +pub type I2cStopR = crate::BitReader; +#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"] +pub type I2cStopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"] +pub type TxunderflowR = crate::BitReader; +#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"] +pub type TxunderflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub type RxoverflowR = crate::BitReader; +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub type TxreadyR = crate::BitReader; +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub type RxreadyR = crate::BitReader; +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> CompletedR { + CompletedR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TxstalledR { + TxstalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RxstalledR { + RxstalledR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> AddressmatchR { + AddressmatchR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RxdatafirstR { + RxdatafirstR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&self) -> I2cStartR { + I2cStartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&self) -> I2cStopR { + I2cStopR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&self) -> TxunderflowR { + TxunderflowR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RxoverflowR { + RxoverflowR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TxreadyR { + TxreadyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RxreadyR { + RxreadyR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&mut self) -> CompletedW<'_, S0IrqEnbSpec> { + CompletedW::new(self, 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IdleW<'_, S0IrqEnbSpec> { + IdleW::new(self, 1) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WaitingW<'_, S0IrqEnbSpec> { + WaitingW::new(self, 2) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&mut self) -> TxstalledW<'_, S0IrqEnbSpec> { + TxstalledW::new(self, 3) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&mut self) -> RxstalledW<'_, S0IrqEnbSpec> { + RxstalledW::new(self, 4) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&mut self) -> AddressmatchW<'_, S0IrqEnbSpec> { + AddressmatchW::new(self, 5) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NackdataW<'_, S0IrqEnbSpec> { + NackdataW::new(self, 6) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&mut self) -> RxdatafirstW<'_, S0IrqEnbSpec> { + RxdatafirstW::new(self, 7) + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&mut self) -> I2cStartW<'_, S0IrqEnbSpec> { + I2cStartW::new(self, 8) + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&mut self) -> I2cStopW<'_, S0IrqEnbSpec> { + I2cStopW::new(self, 9) + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&mut self) -> TxunderflowW<'_, S0IrqEnbSpec> { + TxunderflowW::new(self, 10) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&mut self) -> RxoverflowW<'_, S0IrqEnbSpec> { + RxoverflowW::new(self, 11) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&mut self) -> TxreadyW<'_, S0IrqEnbSpec> { + TxreadyW::new(self, 12) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&mut self) -> RxreadyW<'_, S0IrqEnbSpec> { + RxreadyW::new(self, 13) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TxemptyW<'_, S0IrqEnbSpec> { + TxemptyW::new(self, 14) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RxfullW<'_, S0IrqEnbSpec> { + RxfullW::new(self, 15) + } +} +#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0IrqEnbSpec; +impl crate::RegisterSpec for S0IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_irq_enb::R`](R) reader structure"] +impl crate::Readable for S0IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"] +impl crate::Writable for S0IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_IRQ_ENB to value 0"] +impl crate::Resettable for S0IrqEnbSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_lastaddress.rs b/va416xx/va416xx/src/i2c0/s0_lastaddress.rs new file mode 100644 index 0000000..c71e2c6 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_lastaddress.rs @@ -0,0 +1,27 @@ +#[doc = "Register `S0_LASTADDRESS` reader"] +pub type R = crate::R; +#[doc = "Field `DIRECTION` reader - Transaction direction 0=master send, 1=master receive"] +pub type DirectionR = crate::BitReader; +#[doc = "Field `ADDRESS` reader - Address value"] +pub type AddressR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Transaction direction 0=master send, 1=master receive"] + #[inline(always)] + pub fn direction(&self) -> DirectionR { + DirectionR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&self) -> AddressR { + AddressR::new(((self.bits >> 1) & 0x03ff) as u16) + } +} +#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0LastaddressSpec; +impl crate::RegisterSpec for S0LastaddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_lastaddress::R`](R) reader structure"] +impl crate::Readable for S0LastaddressSpec {} +#[doc = "`reset()` method sets S0_LASTADDRESS to value 0"] +impl crate::Resettable for S0LastaddressSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_maxwords.rs b/va416xx/va416xx/src/i2c0/s0_maxwords.rs new file mode 100644 index 0000000..1e8956e --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_maxwords.rs @@ -0,0 +1,49 @@ +#[doc = "Register `S0_MAXWORDS` reader"] +pub type R = crate::R; +#[doc = "Register `S0_MAXWORDS` writer"] +pub type W = crate::W; +#[doc = "Field `MAXWORD` reader - Max Word Count"] +pub type MaxwordR = crate::FieldReader; +#[doc = "Field `MAXWORD` writer - Max Word Count"] +pub type MaxwordW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `ENABLE` reader - Enables the max word count"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enables the max word count"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - Max Word Count"] + #[inline(always)] + pub fn maxword(&self) -> MaxwordR { + MaxwordR::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 31 - Enables the max word count"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Max Word Count"] + #[inline(always)] + pub fn maxword(&mut self) -> MaxwordW<'_, S0MaxwordsSpec> { + MaxwordW::new(self, 0) + } + #[doc = "Bit 31 - Enables the max word count"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, S0MaxwordsSpec> { + EnableW::new(self, 31) + } +} +#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0MaxwordsSpec; +impl crate::RegisterSpec for S0MaxwordsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_maxwords::R`](R) reader structure"] +impl crate::Readable for S0MaxwordsSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_maxwords::W`](W) writer structure"] +impl crate::Writable for S0MaxwordsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_MAXWORDS to value 0"] +impl crate::Resettable for S0MaxwordsSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_rxcount.rs b/va416xx/va416xx/src/i2c0/s0_rxcount.rs new file mode 100644 index 0000000..099cfd3 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_rxcount.rs @@ -0,0 +1,20 @@ +#[doc = "Register `S0_RXCOUNT` reader"] +pub type R = crate::R; +#[doc = "Field `VALUE` reader - Count value"] +pub type ValueR = crate::FieldReader; +impl R { + #[doc = "Bits 0:10 - Count value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new((self.bits & 0x07ff) as u16) + } +} +#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0RxcountSpec; +impl crate::RegisterSpec for S0RxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_rxcount::R`](R) reader structure"] +impl crate::Readable for S0RxcountSpec {} +#[doc = "`reset()` method sets S0_RXCOUNT to value 0"] +impl crate::Resettable for S0RxcountSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_rxfifoirqtrg.rs b/va416xx/va416xx/src/i2c0/s0_rxfifoirqtrg.rs new file mode 100644 index 0000000..3343d2f --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_rxfifoirqtrg.rs @@ -0,0 +1,35 @@ +#[doc = "Register `S0_RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `S0_RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - Half full level for the Rx FIFO"] +pub type LevelR = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Half full level for the Rx FIFO"] +pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&self) -> LevelR { + LevelR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&mut self) -> LevelW<'_, S0RxfifoirqtrgSpec> { + LevelW::new(self, 0) + } +} +#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0RxfifoirqtrgSpec; +impl crate::RegisterSpec for S0RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for S0RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for S0RxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"] +impl crate::Resettable for S0RxfifoirqtrgSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_state.rs b/va416xx/va416xx/src/i2c0/s0_state.rs new file mode 100644 index 0000000..19c09e3 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_state.rs @@ -0,0 +1,17 @@ +#[doc = "Register `S0_STATE` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0StateSpec; +impl crate::RegisterSpec for S0StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_state::R`](R) reader structure"] +impl crate::Readable for S0StateSpec {} +#[doc = "`reset()` method sets S0_STATE to value 0"] +impl crate::Resettable for S0StateSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_status.rs b/va416xx/va416xx/src/i2c0/s0_status.rs new file mode 100644 index 0000000..ae6e4bb --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_status.rs @@ -0,0 +1,132 @@ +#[doc = "Register `S0_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub type CompletedR = crate::BitReader; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub type TxstalledR = crate::BitReader; +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub type RxstalledR = crate::BitReader; +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub type AddressmatchR = crate::BitReader; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub type RxdatafirstR = crate::BitReader; +#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"] +pub type RxnemptyR = crate::BitReader; +#[doc = "Field `RXFULL` reader - RX FIFO is Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub type RxtriggerR = crate::BitReader; +#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXNFULL` reader - TX FIFO is Full"] +pub type TxnfullR = crate::BitReader; +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub type TxtriggerR = crate::BitReader; +#[doc = "Field `RAW_BUSY` reader - I2C Raw Busy value"] +pub type RawBusyR = crate::BitReader; +#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"] +pub type RawSdaR = crate::BitReader; +#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"] +pub type RawSclR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> CompletedR { + CompletedR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TxstalledR { + TxstalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RxstalledR { + RxstalledR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> AddressmatchR { + AddressmatchR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RxdatafirstR { + RxdatafirstR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&self) -> RxnemptyR { + RxnemptyR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RxtriggerR { + RxtriggerR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&self) -> TxnfullR { + TxnfullR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TxtriggerR { + TxtriggerR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 29 - I2C Raw Busy value"] + #[inline(always)] + pub fn raw_busy(&self) -> RawBusyR { + RawBusyR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&self) -> RawSdaR { + RawSdaR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&self) -> RawSclR { + RawSclR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0StatusSpec; +impl crate::RegisterSpec for S0StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_status::R`](R) reader structure"] +impl crate::Readable for S0StatusSpec {} +#[doc = "`reset()` method sets S0_STATUS to value 0"] +impl crate::Resettable for S0StatusSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_txcount.rs b/va416xx/va416xx/src/i2c0/s0_txcount.rs new file mode 100644 index 0000000..a5e51e1 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_txcount.rs @@ -0,0 +1,20 @@ +#[doc = "Register `S0_TXCOUNT` reader"] +pub type R = crate::R; +#[doc = "Field `VALUE` reader - Count value"] +pub type ValueR = crate::FieldReader; +impl R { + #[doc = "Bits 0:10 - Count value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new((self.bits & 0x07ff) as u16) + } +} +#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0TxcountSpec; +impl crate::RegisterSpec for S0TxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_txcount::R`](R) reader structure"] +impl crate::Readable for S0TxcountSpec {} +#[doc = "`reset()` method sets S0_TXCOUNT to value 0"] +impl crate::Resettable for S0TxcountSpec {} diff --git a/va416xx/va416xx/src/i2c0/s0_txfifoirqtrg.rs b/va416xx/va416xx/src/i2c0/s0_txfifoirqtrg.rs new file mode 100644 index 0000000..d7c07bc --- /dev/null +++ b/va416xx/va416xx/src/i2c0/s0_txfifoirqtrg.rs @@ -0,0 +1,37 @@ +#[doc = "Register `S0_TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `S0_TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - Half full level for the Rx FIFO"] +pub type LevelR = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Half full level for the Rx FIFO"] +pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&self) -> LevelR { + LevelR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&mut self) -> LevelW<'_, S0TxfifoirqtrgSpec> { + LevelW::new(self, 0) + } +} +#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0TxfifoirqtrgSpec; +impl crate::RegisterSpec for S0TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for S0TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for S0TxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0x08"] +impl crate::Resettable for S0TxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0x08; +} diff --git a/va416xx/va416xx/src/i2c0/state.rs b/va416xx/va416xx/src/i2c0/state.rs new file mode 100644 index 0000000..e37bca4 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/state.rs @@ -0,0 +1,17 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StateSpec; +impl crate::RegisterSpec for StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for StateSpec {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for StateSpec {} diff --git a/va416xx/va416xx/src/i2c0/status.rs b/va416xx/va416xx/src/i2c0/status.rs new file mode 100644 index 0000000..5910c01 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/status.rs @@ -0,0 +1,231 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `I2CIDLE` reader - I2C bus is idle"] +pub type I2cidleR = crate::BitReader; +#[doc = "Field `I2CIDLE` writer - I2C bus is idle"] +pub type I2cidleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE` reader - I2C controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `IDLE` writer - I2C controller is Idle"] +pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub type StalledR = crate::BitReader; +#[doc = "Field `STALLED` writer - Controller is Stalled"] +pub type StalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub type ArblostR = crate::BitReader; +#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"] +pub type ArblostW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub type NackaddrR = crate::BitReader; +#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"] +pub type NackaddrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"] +pub type RxnemptyR = crate::BitReader; +#[doc = "Field `RXNEMPTY` writer - RX FIFO is Not Empty"] +pub type RxnemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFULL` reader - RX FIFO is Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXFULL` writer - RX FIFO is Full"] +pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub type RxtriggerR = crate::BitReader; +#[doc = "Field `RXTRIGGER` writer - RX FIFO Above Trigger Level"] +pub type RxtriggerW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXEMPTY` writer - TX FIFO is Empty"] +pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXNFULL` reader - TX FIFO is Full"] +pub type TxnfullR = crate::BitReader; +#[doc = "Field `TXNFULL` writer - TX FIFO is Full"] +pub type TxnfullW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub type TxtriggerR = crate::BitReader; +#[doc = "Field `TXTRIGGER` writer - TX FIFO Below Trigger Level"] +pub type TxtriggerW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"] +pub type RawSdaR = crate::BitReader; +#[doc = "Field `RAW_SDA` writer - I2C Raw SDA value"] +pub type RawSdaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"] +pub type RawSclR = crate::BitReader; +#[doc = "Field `RAW_SCL` writer - I2C Raw SCL value"] +pub type RawSclW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C bus is idle"] + #[inline(always)] + pub fn i2cidle(&self) -> I2cidleR { + I2cidleR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I2C controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> StalledR { + StalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ArblostR { + ArblostR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NackaddrR { + NackaddrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&self) -> RxnemptyR { + RxnemptyR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RxtriggerR { + RxtriggerR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&self) -> TxnfullR { + TxnfullR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TxtriggerR { + TxtriggerR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&self) -> RawSdaR { + RawSdaR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&self) -> RawSclR { + RawSclR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C bus is idle"] + #[inline(always)] + pub fn i2cidle(&mut self) -> I2cidleW<'_, StatusSpec> { + I2cidleW::new(self, 0) + } + #[doc = "Bit 1 - I2C controller is Idle"] + #[inline(always)] + pub fn idle(&mut self) -> IdleW<'_, StatusSpec> { + IdleW::new(self, 1) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&mut self) -> WaitingW<'_, StatusSpec> { + WaitingW::new(self, 2) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&mut self) -> StalledW<'_, StatusSpec> { + StalledW::new(self, 3) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ArblostW<'_, StatusSpec> { + ArblostW::new(self, 4) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&mut self) -> NackaddrW<'_, StatusSpec> { + NackaddrW::new(self, 5) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&mut self) -> NackdataW<'_, StatusSpec> { + NackdataW::new(self, 6) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&mut self) -> RxnemptyW<'_, StatusSpec> { + RxnemptyW::new(self, 8) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&mut self) -> RxfullW<'_, StatusSpec> { + RxfullW::new(self, 9) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&mut self) -> RxtriggerW<'_, StatusSpec> { + RxtriggerW::new(self, 11) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&mut self) -> TxemptyW<'_, StatusSpec> { + TxemptyW::new(self, 12) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&mut self) -> TxnfullW<'_, StatusSpec> { + TxnfullW::new(self, 13) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&mut self) -> TxtriggerW<'_, StatusSpec> { + TxtriggerW::new(self, 15) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&mut self) -> RawSdaW<'_, StatusSpec> { + RawSdaW::new(self, 30) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&mut self) -> RawSclW<'_, StatusSpec> { + RawSclW::new(self, 31) + } +} +#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] +impl crate::Writable for StatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec {} diff --git a/va416xx/va416xx/src/i2c0/tmconfig.rs b/va416xx/va416xx/src/i2c0/tmconfig.rs new file mode 100644 index 0000000..670f854 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/tmconfig.rs @@ -0,0 +1,24 @@ +#[doc = "Register `TMCONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `TMCONFIG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TmconfigSpec; +impl crate::RegisterSpec for TmconfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmconfig::R`](R) reader structure"] +impl crate::Readable for TmconfigSpec {} +#[doc = "`write(|w| ..)` method takes [`tmconfig::W`](W) writer structure"] +impl crate::Writable for TmconfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TMCONFIG to value 0"] +impl crate::Resettable for TmconfigSpec {} diff --git a/va416xx/va416xx/src/i2c0/txcount.rs b/va416xx/va416xx/src/i2c0/txcount.rs new file mode 100644 index 0000000..1a33820 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/txcount.rs @@ -0,0 +1,17 @@ +#[doc = "Register `TXCOUNT` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxcountSpec; +impl crate::RegisterSpec for TxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txcount::R`](R) reader structure"] +impl crate::Readable for TxcountSpec {} +#[doc = "`reset()` method sets TXCOUNT to value 0"] +impl crate::Resettable for TxcountSpec {} diff --git a/va416xx/va416xx/src/i2c0/txfifoirqtrg.rs b/va416xx/va416xx/src/i2c0/txfifoirqtrg.rs new file mode 100644 index 0000000..ea0e7d3 --- /dev/null +++ b/va416xx/va416xx/src/i2c0/txfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TxfifoirqtrgSpec {} diff --git a/va416xx/va416xx/src/i2c0/words.rs b/va416xx/va416xx/src/i2c0/words.rs new file mode 100644 index 0000000..ac3f45c --- /dev/null +++ b/va416xx/va416xx/src/i2c0/words.rs @@ -0,0 +1,24 @@ +#[doc = "Register `WORDS` reader"] +pub type R = crate::R; +#[doc = "Register `WORDS` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WordsSpec; +impl crate::RegisterSpec for WordsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`words::R`](R) reader structure"] +impl crate::Readable for WordsSpec {} +#[doc = "`write(|w| ..)` method takes [`words::W`](W) writer structure"] +impl crate::Writable for WordsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WORDS to value 0"] +impl crate::Resettable for WordsSpec {} diff --git a/va416xx/va416xx/src/ioconfig.rs b/va416xx/va416xx/src/ioconfig.rs new file mode 100644 index 0000000..bbd3a66 --- /dev/null +++ b/va416xx/va416xx/src/ioconfig.rs @@ -0,0 +1,208 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + porta: [Porta; 16], + portb: [Portb; 16], + portc: [Portc; 16], + portd: [Portd; 16], + porte: [Porte; 16], + portf: [Portf; 16], + portg: [Portg; 8], + _reserved7: [u8; 0x20], + clkdiv0: Clkdiv0, + clkdiv1: Clkdiv1, + clkdiv2: Clkdiv2, + clkdiv3: Clkdiv3, + clkdiv4: Clkdiv4, + clkdiv5: Clkdiv5, + clkdiv6: Clkdiv6, + clkdiv7: Clkdiv7, + _reserved15: [u8; 0x0e1c], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00..0x40 - PORTA Pin Configuration Register"] + #[inline(always)] + pub const fn porta(&self, n: usize) -> &Porta { + &self.porta[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x40 - PORTA Pin Configuration Register"] + #[inline(always)] + pub fn porta_iter(&self) -> impl Iterator { + self.porta.iter() + } + #[doc = "0x40..0x80 - PORTB Pin Configuration Register"] + #[inline(always)] + pub const fn portb(&self, n: usize) -> &Portb { + &self.portb[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x40..0x80 - PORTB Pin Configuration Register"] + #[inline(always)] + pub fn portb_iter(&self) -> impl Iterator { + self.portb.iter() + } + #[doc = "0x80..0xc0 - PORTC Pin Configuration Register"] + #[inline(always)] + pub const fn portc(&self, n: usize) -> &Portc { + &self.portc[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x80..0xc0 - PORTC Pin Configuration Register"] + #[inline(always)] + pub fn portc_iter(&self) -> impl Iterator { + self.portc.iter() + } + #[doc = "0xc0..0x100 - PORTD Pin Configuration Register"] + #[inline(always)] + pub const fn portd(&self, n: usize) -> &Portd { + &self.portd[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xc0..0x100 - PORTD Pin Configuration Register"] + #[inline(always)] + pub fn portd_iter(&self) -> impl Iterator { + self.portd.iter() + } + #[doc = "0x100..0x140 - PORTE Pin Configuration Register"] + #[inline(always)] + pub const fn porte(&self, n: usize) -> &Porte { + &self.porte[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x100..0x140 - PORTE Pin Configuration Register"] + #[inline(always)] + pub fn porte_iter(&self) -> impl Iterator { + self.porte.iter() + } + #[doc = "0x140..0x180 - PORTF Pin Configuration Register"] + #[inline(always)] + pub const fn portf(&self, n: usize) -> &Portf { + &self.portf[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x140..0x180 - PORTF Pin Configuration Register"] + #[inline(always)] + pub fn portf_iter(&self) -> impl Iterator { + self.portf.iter() + } + #[doc = "0x180..0x1a0 - PORTG Pin Configuration Register"] + #[inline(always)] + pub const fn portg(&self, n: usize) -> &Portg { + &self.portg[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x180..0x1a0 - PORTG Pin Configuration Register"] + #[inline(always)] + pub fn portg_iter(&self) -> impl Iterator { + self.portg.iter() + } + #[doc = "0x1c0 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv0(&self) -> &Clkdiv0 { + &self.clkdiv0 + } + #[doc = "0x1c4 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv1(&self) -> &Clkdiv1 { + &self.clkdiv1 + } + #[doc = "0x1c8 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv2(&self) -> &Clkdiv2 { + &self.clkdiv2 + } + #[doc = "0x1cc - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv3(&self) -> &Clkdiv3 { + &self.clkdiv3 + } + #[doc = "0x1d0 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv4(&self) -> &Clkdiv4 { + &self.clkdiv4 + } + #[doc = "0x1d4 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv5(&self) -> &Clkdiv5 { + &self.clkdiv5 + } + #[doc = "0x1d8 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv6(&self) -> &Clkdiv6 { + &self.clkdiv6 + } + #[doc = "0x1dc - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv7(&self) -> &Clkdiv7 { + &self.clkdiv7 + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`] module"] +#[doc(alias = "PORTA")] +pub type Porta = crate::Reg; +#[doc = "PORTA Pin Configuration Register"] +pub mod porta; +pub use porta as portb; +pub use porta as portc; +pub use porta as portd; +pub use porta as porte; +pub use porta as portf; +pub use porta as portg; +pub use Porta as Portb; +pub use Porta as Portc; +pub use Porta as Portd; +pub use Porta as Porte; +pub use Porta as Portf; +pub use Porta as Portg; +#[doc = "CLKDIV0 (r) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv0`] module"] +#[doc(alias = "CLKDIV0")] +pub type Clkdiv0 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv0; +#[doc = "CLKDIV1 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv1`] module"] +#[doc(alias = "CLKDIV1")] +pub type Clkdiv1 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv1; +#[doc = "CLKDIV2 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv2`] module"] +#[doc(alias = "CLKDIV2")] +pub type Clkdiv2 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv2; +#[doc = "CLKDIV3 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv3`] module"] +#[doc(alias = "CLKDIV3")] +pub type Clkdiv3 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv3; +#[doc = "CLKDIV4 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv4`] module"] +#[doc(alias = "CLKDIV4")] +pub type Clkdiv4 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv4; +#[doc = "CLKDIV5 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv5`] module"] +#[doc(alias = "CLKDIV5")] +pub type Clkdiv5 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv5; +#[doc = "CLKDIV6 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv6`] module"] +#[doc(alias = "CLKDIV6")] +pub type Clkdiv6 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv6; +#[doc = "CLKDIV7 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv7`] module"] +#[doc(alias = "CLKDIV7")] +pub type Clkdiv7 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv7; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/ioconfig/clkdiv0.rs b/va416xx/va416xx/src/ioconfig/clkdiv0.rs new file mode 100644 index 0000000..1d02409 --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/clkdiv0.rs @@ -0,0 +1,17 @@ +#[doc = "Register `CLKDIV0` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv0Spec; +impl crate::RegisterSpec for Clkdiv0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv0::R`](R) reader structure"] +impl crate::Readable for Clkdiv0Spec {} +#[doc = "`reset()` method sets CLKDIV0 to value 0"] +impl crate::Resettable for Clkdiv0Spec {} diff --git a/va416xx/va416xx/src/ioconfig/clkdiv1.rs b/va416xx/va416xx/src/ioconfig/clkdiv1.rs new file mode 100644 index 0000000..cbc567e --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/clkdiv1.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKDIV1` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV1` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv1Spec; +impl crate::RegisterSpec for Clkdiv1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv1::R`](R) reader structure"] +impl crate::Readable for Clkdiv1Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv1::W`](W) writer structure"] +impl crate::Writable for Clkdiv1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKDIV1 to value 0"] +impl crate::Resettable for Clkdiv1Spec {} diff --git a/va416xx/va416xx/src/ioconfig/clkdiv2.rs b/va416xx/va416xx/src/ioconfig/clkdiv2.rs new file mode 100644 index 0000000..c030549 --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/clkdiv2.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKDIV2` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV2` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv2Spec; +impl crate::RegisterSpec for Clkdiv2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv2::R`](R) reader structure"] +impl crate::Readable for Clkdiv2Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv2::W`](W) writer structure"] +impl crate::Writable for Clkdiv2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKDIV2 to value 0"] +impl crate::Resettable for Clkdiv2Spec {} diff --git a/va416xx/va416xx/src/ioconfig/clkdiv3.rs b/va416xx/va416xx/src/ioconfig/clkdiv3.rs new file mode 100644 index 0000000..31910c4 --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/clkdiv3.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKDIV3` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV3` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv3Spec; +impl crate::RegisterSpec for Clkdiv3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv3::R`](R) reader structure"] +impl crate::Readable for Clkdiv3Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv3::W`](W) writer structure"] +impl crate::Writable for Clkdiv3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKDIV3 to value 0"] +impl crate::Resettable for Clkdiv3Spec {} diff --git a/va416xx/va416xx/src/ioconfig/clkdiv4.rs b/va416xx/va416xx/src/ioconfig/clkdiv4.rs new file mode 100644 index 0000000..a9e217c --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/clkdiv4.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKDIV4` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV4` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv4Spec; +impl crate::RegisterSpec for Clkdiv4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv4::R`](R) reader structure"] +impl crate::Readable for Clkdiv4Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv4::W`](W) writer structure"] +impl crate::Writable for Clkdiv4Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKDIV4 to value 0"] +impl crate::Resettable for Clkdiv4Spec {} diff --git a/va416xx/va416xx/src/ioconfig/clkdiv5.rs b/va416xx/va416xx/src/ioconfig/clkdiv5.rs new file mode 100644 index 0000000..0754ee4 --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/clkdiv5.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKDIV5` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV5` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv5Spec; +impl crate::RegisterSpec for Clkdiv5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv5::R`](R) reader structure"] +impl crate::Readable for Clkdiv5Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv5::W`](W) writer structure"] +impl crate::Writable for Clkdiv5Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKDIV5 to value 0"] +impl crate::Resettable for Clkdiv5Spec {} diff --git a/va416xx/va416xx/src/ioconfig/clkdiv6.rs b/va416xx/va416xx/src/ioconfig/clkdiv6.rs new file mode 100644 index 0000000..04fabb8 --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/clkdiv6.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKDIV6` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV6` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv6Spec; +impl crate::RegisterSpec for Clkdiv6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv6::R`](R) reader structure"] +impl crate::Readable for Clkdiv6Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv6::W`](W) writer structure"] +impl crate::Writable for Clkdiv6Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKDIV6 to value 0"] +impl crate::Resettable for Clkdiv6Spec {} diff --git a/va416xx/va416xx/src/ioconfig/clkdiv7.rs b/va416xx/va416xx/src/ioconfig/clkdiv7.rs new file mode 100644 index 0000000..dbfa0e8 --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/clkdiv7.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKDIV7` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV7` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv7Spec; +impl crate::RegisterSpec for Clkdiv7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv7::R`](R) reader structure"] +impl crate::Readable for Clkdiv7Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv7::W`](W) writer structure"] +impl crate::Writable for Clkdiv7Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKDIV7 to value 0"] +impl crate::Resettable for Clkdiv7Spec {} diff --git a/va416xx/va416xx/src/ioconfig/perid.rs b/va416xx/va416xx/src/ioconfig/perid.rs new file mode 100644 index 0000000..8c23707 --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0282_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0282_07e9; +} diff --git a/va416xx/va416xx/src/ioconfig/porta.rs b/va416xx/va416xx/src/ioconfig/porta.rs new file mode 100644 index 0000000..26249e8 --- /dev/null +++ b/va416xx/va416xx/src/ioconfig/porta.rs @@ -0,0 +1,284 @@ +#[doc = "Register `PORTA[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `PORTA[%s]` writer"] +pub type W = crate::W; +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Flttype { + #[doc = "0: Synchronize to system clock"] + Sync = 0, + #[doc = "1: Direct input, no synchronization"] + Direct = 1, + #[doc = "2: Require 2 samples to have the same value"] + Filter1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + Filter2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + Filter3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + Filter4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Flttype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Flttype { + type Ux = u8; +} +impl crate::IsEnum for Flttype {} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub type FlttypeR = crate::FieldReader; +impl FlttypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Flttype::Sync), + 1 => Some(Flttype::Direct), + 2 => Some(Flttype::Filter1), + 3 => Some(Flttype::Filter2), + 4 => Some(Flttype::Filter3), + 5 => Some(Flttype::Filter4), + _ => None, + } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + *self == Flttype::Sync + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + *self == Flttype::Direct + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + *self == Flttype::Filter1 + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + *self == Flttype::Filter2 + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + *self == Flttype::Filter3 + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + *self == Flttype::Filter4 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub type FlttypeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Flttype>; +impl<'a, REG> FlttypeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut crate::W { + self.variant(Flttype::Sync) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut crate::W { + self.variant(Flttype::Direct) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut crate::W { + self.variant(Flttype::Filter1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut crate::W { + self.variant(Flttype::Filter2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut crate::W { + self.variant(Flttype::Filter3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut crate::W { + self.variant(Flttype::Filter4) + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub type FltclkR = crate::FieldReader; +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub type FltclkW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub type InvinpR = crate::BitReader; +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub type InvinpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub type IewoR = crate::BitReader; +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub type IewoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub type OpendrnR = crate::BitReader; +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub type OpendrnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub type InvoutR = crate::BitReader; +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub type InvoutW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub type PlevelR = crate::BitReader; +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub type PlevelW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub type PenR = crate::BitReader; +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub type PenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub type PwoaR = crate::BitReader; +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub type PwoaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub type FunselR = crate::FieldReader; +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub type FunselW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub type IodisR = crate::BitReader; +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub type IodisW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FlttypeR { + FlttypeR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FltclkR { + FltclkR::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> InvinpR { + InvinpR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IewoR { + IewoR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OpendrnR { + OpendrnR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> InvoutR { + InvoutR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PlevelR { + PlevelR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PenR { + PenR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PwoaR { + PwoaR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FunselR { + FunselR::new(((self.bits >> 13) & 7) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IodisR { + IodisR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&mut self) -> FlttypeW<'_, PortaSpec> { + FlttypeW::new(self, 0) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&mut self) -> FltclkW<'_, PortaSpec> { + FltclkW::new(self, 3) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&mut self) -> InvinpW<'_, PortaSpec> { + InvinpW::new(self, 6) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&mut self) -> IewoW<'_, PortaSpec> { + IewoW::new(self, 7) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&mut self) -> OpendrnW<'_, PortaSpec> { + OpendrnW::new(self, 8) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&mut self) -> InvoutW<'_, PortaSpec> { + InvoutW::new(self, 9) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&mut self) -> PlevelW<'_, PortaSpec> { + PlevelW::new(self, 10) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&mut self) -> PenW<'_, PortaSpec> { + PenW::new(self, 11) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&mut self) -> PwoaW<'_, PortaSpec> { + PwoaW::new(self, 12) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&mut self) -> FunselW<'_, PortaSpec> { + FunselW::new(self, 13) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&mut self) -> IodisW<'_, PortaSpec> { + IodisW::new(self, 16) + } +} +#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PortaSpec; +impl crate::RegisterSpec for PortaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`porta::R`](R) reader structure"] +impl crate::Readable for PortaSpec {} +#[doc = "`write(|w| ..)` method takes [`porta::W`](W) writer structure"] +impl crate::Writable for PortaSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PORTA[%s] to value 0"] +impl crate::Resettable for PortaSpec {} diff --git a/va416xx/va416xx/src/irq_router.rs b/va416xx/va416xx/src/irq_router.rs new file mode 100644 index 0000000..5f7589a --- /dev/null +++ b/va416xx/va416xx/src/irq_router.rs @@ -0,0 +1,172 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + dmasel0: Dmasel0, + dmasel1: Dmasel1, + dmasel2: Dmasel2, + dmasel3: Dmasel3, + dmattsel: Dmattsel, + adcsel: Adcsel, + dacsel0: Dacsel0, + dacsel1: Dacsel1, + irq_out0: IrqOut0, + irq_out1: IrqOut1, + irq_out2: IrqOut2, + irq_out3: IrqOut3, + irq_out4: IrqOut4, + irq_out5: IrqOut5, + _reserved14: [u8; 0x0fc4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Interrupt select for DMA channel 0"] + #[inline(always)] + pub const fn dmasel0(&self) -> &Dmasel0 { + &self.dmasel0 + } + #[doc = "0x04 - Interrupt select for DMA channel 1"] + #[inline(always)] + pub const fn dmasel1(&self) -> &Dmasel1 { + &self.dmasel1 + } + #[doc = "0x08 - Interrupt select for DMA channel 2"] + #[inline(always)] + pub const fn dmasel2(&self) -> &Dmasel2 { + &self.dmasel2 + } + #[doc = "0x0c - Interrupt select for DMA channel 3"] + #[inline(always)] + pub const fn dmasel3(&self) -> &Dmasel3 { + &self.dmasel3 + } + #[doc = "0x10 - Trigger select for the DMA channels"] + #[inline(always)] + pub const fn dmattsel(&self) -> &Dmattsel { + &self.dmattsel + } + #[doc = "0x14 - Interrupt select for ADC"] + #[inline(always)] + pub const fn adcsel(&self) -> &Adcsel { + &self.adcsel + } + #[doc = "0x18 - Interrupt select for DAC0"] + #[inline(always)] + pub const fn dacsel0(&self) -> &Dacsel0 { + &self.dacsel0 + } + #[doc = "0x1c - Interrupt select for DAC1"] + #[inline(always)] + pub const fn dacsel1(&self) -> &Dacsel1 { + &self.dacsel1 + } + #[doc = "0x20 - DEBUG IRQ_OUT\\[31:0\\]"] + #[inline(always)] + pub const fn irq_out0(&self) -> &IrqOut0 { + &self.irq_out0 + } + #[doc = "0x24 - DEBUG IRQ_OUT\\[63:32\\]"] + #[inline(always)] + pub const fn irq_out1(&self) -> &IrqOut1 { + &self.irq_out1 + } + #[doc = "0x28 - DEBUG IRQ_OUT\\[95:64\\]"] + #[inline(always)] + pub const fn irq_out2(&self) -> &IrqOut2 { + &self.irq_out2 + } + #[doc = "0x2c - DEBUG IRQ_OUT\\[127:96\\]"] + #[inline(always)] + pub const fn irq_out3(&self) -> &IrqOut3 { + &self.irq_out3 + } + #[doc = "0x30 - DEBUG IRQ_OUT\\[159:128\\]"] + #[inline(always)] + pub const fn irq_out4(&self) -> &IrqOut4 { + &self.irq_out4 + } + #[doc = "0x34 - DEBUG IRQ_OUT\\[179:160\\]"] + #[inline(always)] + pub const fn irq_out5(&self) -> &IrqOut5 { + &self.irq_out5 + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "DMASEL0 (rw) register accessor: Interrupt select for DMA channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasel0`] module"] +#[doc(alias = "DMASEL0")] +pub type Dmasel0 = crate::Reg; +#[doc = "Interrupt select for DMA channel 0"] +pub mod dmasel0; +#[doc = "DMASEL1 (rw) register accessor: Interrupt select for DMA channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasel1`] module"] +#[doc(alias = "DMASEL1")] +pub type Dmasel1 = crate::Reg; +#[doc = "Interrupt select for DMA channel 1"] +pub mod dmasel1; +#[doc = "DMASEL2 (rw) register accessor: Interrupt select for DMA channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasel2`] module"] +#[doc(alias = "DMASEL2")] +pub type Dmasel2 = crate::Reg; +#[doc = "Interrupt select for DMA channel 2"] +pub mod dmasel2; +#[doc = "DMASEL3 (rw) register accessor: Interrupt select for DMA channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasel3`] module"] +#[doc(alias = "DMASEL3")] +pub type Dmasel3 = crate::Reg; +#[doc = "Interrupt select for DMA channel 3"] +pub mod dmasel3; +#[doc = "DMATTSEL (rw) register accessor: Trigger select for the DMA channels\n\nYou can [`read`](crate::Reg::read) this register and get [`dmattsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmattsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmattsel`] module"] +#[doc(alias = "DMATTSEL")] +pub type Dmattsel = crate::Reg; +#[doc = "Trigger select for the DMA channels"] +pub mod dmattsel; +#[doc = "ADCSEL (rw) register accessor: Interrupt select for ADC\n\nYou can [`read`](crate::Reg::read) this register and get [`adcsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcsel`] module"] +#[doc(alias = "ADCSEL")] +pub type Adcsel = crate::Reg; +#[doc = "Interrupt select for ADC"] +pub mod adcsel; +#[doc = "DACSEL0 (rw) register accessor: Interrupt select for DAC0\n\nYou can [`read`](crate::Reg::read) this register and get [`dacsel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dacsel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dacsel0`] module"] +#[doc(alias = "DACSEL0")] +pub type Dacsel0 = crate::Reg; +#[doc = "Interrupt select for DAC0"] +pub mod dacsel0; +#[doc = "DACSEL1 (rw) register accessor: Interrupt select for DAC1\n\nYou can [`read`](crate::Reg::read) this register and get [`dacsel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dacsel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dacsel1`] module"] +#[doc(alias = "DACSEL1")] +pub type Dacsel1 = crate::Reg; +#[doc = "Interrupt select for DAC1"] +pub mod dacsel1; +#[doc = "IRQ_OUT0 (r) register accessor: DEBUG IRQ_OUT\\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out0`] module"] +#[doc(alias = "IRQ_OUT0")] +pub type IrqOut0 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[31:0\\]"] +pub mod irq_out0; +#[doc = "IRQ_OUT1 (r) register accessor: DEBUG IRQ_OUT\\[63:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out1`] module"] +#[doc(alias = "IRQ_OUT1")] +pub type IrqOut1 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[63:32\\]"] +pub mod irq_out1; +#[doc = "IRQ_OUT2 (r) register accessor: DEBUG IRQ_OUT\\[95:64\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out2`] module"] +#[doc(alias = "IRQ_OUT2")] +pub type IrqOut2 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[95:64\\]"] +pub mod irq_out2; +#[doc = "IRQ_OUT3 (r) register accessor: DEBUG IRQ_OUT\\[127:96\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out3`] module"] +#[doc(alias = "IRQ_OUT3")] +pub type IrqOut3 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[127:96\\]"] +pub mod irq_out3; +#[doc = "IRQ_OUT4 (r) register accessor: DEBUG IRQ_OUT\\[159:128\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out4`] module"] +#[doc(alias = "IRQ_OUT4")] +pub type IrqOut4 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[159:128\\]"] +pub mod irq_out4; +#[doc = "IRQ_OUT5 (r) register accessor: DEBUG IRQ_OUT\\[179:160\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out5`] module"] +#[doc(alias = "IRQ_OUT5")] +pub type IrqOut5 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[179:160\\]"] +pub mod irq_out5; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/irq_router/adcsel.rs b/va416xx/va416xx/src/irq_router/adcsel.rs new file mode 100644 index 0000000..65b8c33 --- /dev/null +++ b/va416xx/va416xx/src/irq_router/adcsel.rs @@ -0,0 +1,37 @@ +#[doc = "Register `ADCSEL` reader"] +pub type R = crate::R; +#[doc = "Register `ADCSEL` writer"] +pub type W = crate::W; +#[doc = "Field `ADCSEL` reader - ADC trigger source selection value"] +pub type AdcselR = crate::FieldReader; +#[doc = "Field `ADCSEL` writer - ADC trigger source selection value"] +pub type AdcselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - ADC trigger source selection value"] + #[inline(always)] + pub fn adcsel(&self) -> AdcselR { + AdcselR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - ADC trigger source selection value"] + #[inline(always)] + pub fn adcsel(&mut self) -> AdcselW<'_, AdcselSpec> { + AdcselW::new(self, 0) + } +} +#[doc = "Interrupt select for ADC\n\nYou can [`read`](crate::Reg::read) this register and get [`adcsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AdcselSpec; +impl crate::RegisterSpec for AdcselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`adcsel::R`](R) reader structure"] +impl crate::Readable for AdcselSpec {} +#[doc = "`write(|w| ..)` method takes [`adcsel::W`](W) writer structure"] +impl crate::Writable for AdcselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADCSEL to value 0x1f"] +impl crate::Resettable for AdcselSpec { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/va416xx/va416xx/src/irq_router/dacsel0.rs b/va416xx/va416xx/src/irq_router/dacsel0.rs new file mode 100644 index 0000000..5022b27 --- /dev/null +++ b/va416xx/va416xx/src/irq_router/dacsel0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DACSEL0` reader"] +pub type R = crate::R; +#[doc = "Register `DACSEL0` writer"] +pub type W = crate::W; +#[doc = "Field `DACSEL` reader - DAC trigger source selection value"] +pub type DacselR = crate::FieldReader; +#[doc = "Field `DACSEL` writer - DAC trigger source selection value"] +pub type DacselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&self) -> DacselR { + DacselR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&mut self) -> DacselW<'_, Dacsel0Spec> { + DacselW::new(self, 0) + } +} +#[doc = "Interrupt select for DAC0\n\nYou can [`read`](crate::Reg::read) this register and get [`dacsel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dacsel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dacsel0Spec; +impl crate::RegisterSpec for Dacsel0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dacsel0::R`](R) reader structure"] +impl crate::Readable for Dacsel0Spec {} +#[doc = "`write(|w| ..)` method takes [`dacsel0::W`](W) writer structure"] +impl crate::Writable for Dacsel0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DACSEL0 to value 0x1f"] +impl crate::Resettable for Dacsel0Spec { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/va416xx/va416xx/src/irq_router/dacsel1.rs b/va416xx/va416xx/src/irq_router/dacsel1.rs new file mode 100644 index 0000000..849d25c --- /dev/null +++ b/va416xx/va416xx/src/irq_router/dacsel1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DACSEL1` reader"] +pub type R = crate::R; +#[doc = "Register `DACSEL1` writer"] +pub type W = crate::W; +#[doc = "Field `DACSEL` reader - DAC trigger source selection value"] +pub type DacselR = crate::FieldReader; +#[doc = "Field `DACSEL` writer - DAC trigger source selection value"] +pub type DacselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&self) -> DacselR { + DacselR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&mut self) -> DacselW<'_, Dacsel1Spec> { + DacselW::new(self, 0) + } +} +#[doc = "Interrupt select for DAC1\n\nYou can [`read`](crate::Reg::read) this register and get [`dacsel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dacsel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dacsel1Spec; +impl crate::RegisterSpec for Dacsel1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dacsel1::R`](R) reader structure"] +impl crate::Readable for Dacsel1Spec {} +#[doc = "`write(|w| ..)` method takes [`dacsel1::W`](W) writer structure"] +impl crate::Writable for Dacsel1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DACSEL1 to value 0x1f"] +impl crate::Resettable for Dacsel1Spec { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/va416xx/va416xx/src/irq_router/dmasel0.rs b/va416xx/va416xx/src/irq_router/dmasel0.rs new file mode 100644 index 0000000..fb22f04 --- /dev/null +++ b/va416xx/va416xx/src/irq_router/dmasel0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DMASEL0` reader"] +pub type R = crate::R; +#[doc = "Register `DMASEL0` writer"] +pub type W = crate::W; +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub type DmaselR = crate::FieldReader; +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub type DmaselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DmaselR { + DmaselR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&mut self) -> DmaselW<'_, Dmasel0Spec> { + DmaselW::new(self, 0) + } +} +#[doc = "Interrupt select for DMA channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmasel0Spec; +impl crate::RegisterSpec for Dmasel0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmasel0::R`](R) reader structure"] +impl crate::Readable for Dmasel0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmasel0::W`](W) writer structure"] +impl crate::Writable for Dmasel0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMASEL0 to value 0x7f"] +impl crate::Resettable for Dmasel0Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/va416xx/va416xx/src/irq_router/dmasel1.rs b/va416xx/va416xx/src/irq_router/dmasel1.rs new file mode 100644 index 0000000..4ab1f0d --- /dev/null +++ b/va416xx/va416xx/src/irq_router/dmasel1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DMASEL1` reader"] +pub type R = crate::R; +#[doc = "Register `DMASEL1` writer"] +pub type W = crate::W; +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub type DmaselR = crate::FieldReader; +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub type DmaselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DmaselR { + DmaselR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&mut self) -> DmaselW<'_, Dmasel1Spec> { + DmaselW::new(self, 0) + } +} +#[doc = "Interrupt select for DMA channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmasel1Spec; +impl crate::RegisterSpec for Dmasel1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmasel1::R`](R) reader structure"] +impl crate::Readable for Dmasel1Spec {} +#[doc = "`write(|w| ..)` method takes [`dmasel1::W`](W) writer structure"] +impl crate::Writable for Dmasel1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMASEL1 to value 0x7f"] +impl crate::Resettable for Dmasel1Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/va416xx/va416xx/src/irq_router/dmasel2.rs b/va416xx/va416xx/src/irq_router/dmasel2.rs new file mode 100644 index 0000000..6671408 --- /dev/null +++ b/va416xx/va416xx/src/irq_router/dmasel2.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DMASEL2` reader"] +pub type R = crate::R; +#[doc = "Register `DMASEL2` writer"] +pub type W = crate::W; +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub type DmaselR = crate::FieldReader; +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub type DmaselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DmaselR { + DmaselR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&mut self) -> DmaselW<'_, Dmasel2Spec> { + DmaselW::new(self, 0) + } +} +#[doc = "Interrupt select for DMA channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmasel2Spec; +impl crate::RegisterSpec for Dmasel2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmasel2::R`](R) reader structure"] +impl crate::Readable for Dmasel2Spec {} +#[doc = "`write(|w| ..)` method takes [`dmasel2::W`](W) writer structure"] +impl crate::Writable for Dmasel2Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMASEL2 to value 0x7f"] +impl crate::Resettable for Dmasel2Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/va416xx/va416xx/src/irq_router/dmasel3.rs b/va416xx/va416xx/src/irq_router/dmasel3.rs new file mode 100644 index 0000000..6051e39 --- /dev/null +++ b/va416xx/va416xx/src/irq_router/dmasel3.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DMASEL3` reader"] +pub type R = crate::R; +#[doc = "Register `DMASEL3` writer"] +pub type W = crate::W; +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub type DmaselR = crate::FieldReader; +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub type DmaselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DmaselR { + DmaselR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&mut self) -> DmaselW<'_, Dmasel3Spec> { + DmaselW::new(self, 0) + } +} +#[doc = "Interrupt select for DMA channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmasel3Spec; +impl crate::RegisterSpec for Dmasel3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmasel3::R`](R) reader structure"] +impl crate::Readable for Dmasel3Spec {} +#[doc = "`write(|w| ..)` method takes [`dmasel3::W`](W) writer structure"] +impl crate::Writable for Dmasel3Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMASEL3 to value 0x7f"] +impl crate::Resettable for Dmasel3Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/va416xx/va416xx/src/irq_router/dmattsel.rs b/va416xx/va416xx/src/irq_router/dmattsel.rs new file mode 100644 index 0000000..2b4a834 --- /dev/null +++ b/va416xx/va416xx/src/irq_router/dmattsel.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMATTSEL` reader"] +pub type R = crate::R; +#[doc = "Register `DMATTSEL` writer"] +pub type W = crate::W; +#[doc = "Field `DMATTSEL` reader - DMA trigger type selection value"] +pub type DmattselR = crate::FieldReader; +#[doc = "Field `DMATTSEL` writer - DMA trigger type selection value"] +pub type DmattselW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - DMA trigger type selection value"] + #[inline(always)] + pub fn dmattsel(&self) -> DmattselR { + DmattselR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - DMA trigger type selection value"] + #[inline(always)] + pub fn dmattsel(&mut self) -> DmattselW<'_, DmattselSpec> { + DmattselW::new(self, 0) + } +} +#[doc = "Trigger select for the DMA channels\n\nYou can [`read`](crate::Reg::read) this register and get [`dmattsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmattsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmattselSpec; +impl crate::RegisterSpec for DmattselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmattsel::R`](R) reader structure"] +impl crate::Readable for DmattselSpec {} +#[doc = "`write(|w| ..)` method takes [`dmattsel::W`](W) writer structure"] +impl crate::Writable for DmattselSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMATTSEL to value 0"] +impl crate::Resettable for DmattselSpec {} diff --git a/va416xx/va416xx/src/irq_router/irq_out0.rs b/va416xx/va416xx/src/irq_router/irq_out0.rs new file mode 100644 index 0000000..cc4e96c --- /dev/null +++ b/va416xx/va416xx/src/irq_router/irq_out0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `IRQ_OUT0` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT0` reader - IRQ_OUT\\[31:0\\]"] +pub type IrqOut0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[31:0\\]"] + #[inline(always)] + pub fn irq_out0(&self) -> IrqOut0R { + IrqOut0R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut0Spec; +impl crate::RegisterSpec for IrqOut0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out0::R`](R) reader structure"] +impl crate::Readable for IrqOut0Spec {} +#[doc = "`reset()` method sets IRQ_OUT0 to value 0"] +impl crate::Resettable for IrqOut0Spec {} diff --git a/va416xx/va416xx/src/irq_router/irq_out1.rs b/va416xx/va416xx/src/irq_router/irq_out1.rs new file mode 100644 index 0000000..0395e87 --- /dev/null +++ b/va416xx/va416xx/src/irq_router/irq_out1.rs @@ -0,0 +1,20 @@ +#[doc = "Register `IRQ_OUT1` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT1` reader - IRQ_OUT\\[63:32\\]"] +pub type IrqOut1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[63:32\\]"] + #[inline(always)] + pub fn irq_out1(&self) -> IrqOut1R { + IrqOut1R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[63:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut1Spec; +impl crate::RegisterSpec for IrqOut1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out1::R`](R) reader structure"] +impl crate::Readable for IrqOut1Spec {} +#[doc = "`reset()` method sets IRQ_OUT1 to value 0"] +impl crate::Resettable for IrqOut1Spec {} diff --git a/va416xx/va416xx/src/irq_router/irq_out2.rs b/va416xx/va416xx/src/irq_router/irq_out2.rs new file mode 100644 index 0000000..4547084 --- /dev/null +++ b/va416xx/va416xx/src/irq_router/irq_out2.rs @@ -0,0 +1,20 @@ +#[doc = "Register `IRQ_OUT2` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT2` reader - IRQ_OUT\\[95:64\\]"] +pub type IrqOut2R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[95:64\\]"] + #[inline(always)] + pub fn irq_out2(&self) -> IrqOut2R { + IrqOut2R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[95:64\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut2Spec; +impl crate::RegisterSpec for IrqOut2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out2::R`](R) reader structure"] +impl crate::Readable for IrqOut2Spec {} +#[doc = "`reset()` method sets IRQ_OUT2 to value 0"] +impl crate::Resettable for IrqOut2Spec {} diff --git a/va416xx/va416xx/src/irq_router/irq_out3.rs b/va416xx/va416xx/src/irq_router/irq_out3.rs new file mode 100644 index 0000000..09872ac --- /dev/null +++ b/va416xx/va416xx/src/irq_router/irq_out3.rs @@ -0,0 +1,20 @@ +#[doc = "Register `IRQ_OUT3` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT3` reader - IRQ_OUT\\[127:96\\]"] +pub type IrqOut3R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[127:96\\]"] + #[inline(always)] + pub fn irq_out3(&self) -> IrqOut3R { + IrqOut3R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[127:96\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut3Spec; +impl crate::RegisterSpec for IrqOut3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out3::R`](R) reader structure"] +impl crate::Readable for IrqOut3Spec {} +#[doc = "`reset()` method sets IRQ_OUT3 to value 0"] +impl crate::Resettable for IrqOut3Spec {} diff --git a/va416xx/va416xx/src/irq_router/irq_out4.rs b/va416xx/va416xx/src/irq_router/irq_out4.rs new file mode 100644 index 0000000..7ad2a7e --- /dev/null +++ b/va416xx/va416xx/src/irq_router/irq_out4.rs @@ -0,0 +1,20 @@ +#[doc = "Register `IRQ_OUT4` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT4` reader - IRQ_OUT\\[159:128\\]"] +pub type IrqOut4R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[159:128\\]"] + #[inline(always)] + pub fn irq_out4(&self) -> IrqOut4R { + IrqOut4R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[159:128\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut4Spec; +impl crate::RegisterSpec for IrqOut4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out4::R`](R) reader structure"] +impl crate::Readable for IrqOut4Spec {} +#[doc = "`reset()` method sets IRQ_OUT4 to value 0"] +impl crate::Resettable for IrqOut4Spec {} diff --git a/va416xx/va416xx/src/irq_router/irq_out5.rs b/va416xx/va416xx/src/irq_router/irq_out5.rs new file mode 100644 index 0000000..f4e115c --- /dev/null +++ b/va416xx/va416xx/src/irq_router/irq_out5.rs @@ -0,0 +1,20 @@ +#[doc = "Register `IRQ_OUT5` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT5` reader - IRQ_OUT\\[179:160\\]"] +pub type IrqOut5R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - IRQ_OUT\\[179:160\\]"] + #[inline(always)] + pub fn irq_out5(&self) -> IrqOut5R { + IrqOut5R::new(self.bits & 0x000f_ffff) + } +} +#[doc = "DEBUG IRQ_OUT\\[179:160\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut5Spec; +impl crate::RegisterSpec for IrqOut5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out5::R`](R) reader structure"] +impl crate::Readable for IrqOut5Spec {} +#[doc = "`reset()` method sets IRQ_OUT5 to value 0"] +impl crate::Resettable for IrqOut5Spec {} diff --git a/va416xx/va416xx/src/irq_router/perid.rs b/va416xx/va416xx/src/irq_router/perid.rs new file mode 100644 index 0000000..339b0c6 --- /dev/null +++ b/va416xx/va416xx/src/irq_router/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0281_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0281_07e9; +} diff --git a/va416xx/va416xx/src/lib.rs b/va416xx/va416xx/src/lib.rs new file mode 100644 index 0000000..6b38971 --- /dev/null +++ b/va416xx/va416xx/src/lib.rs @@ -0,0 +1,1570 @@ +#![doc = "Peripheral access API for VA416XX microcontrollers (generated using svd2rust v0.37.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 4; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn U0(); + fn U1(); + fn U2(); + fn U3(); + fn U4(); + fn U5(); + fn U6(); + fn U7(); + fn U8(); + fn U9(); + fn U10(); + fn U11(); + fn U12(); + fn U13(); + fn U14(); + fn U15(); + fn SPI0_TX(); + fn SPI0_RX(); + fn SPI1_TX(); + fn SPI1_RX(); + fn SPI2_TX(); + fn SPI2_RX(); + fn SPI3_TX(); + fn SPI3_RX(); + fn UART0_TX(); + fn UART0_RX(); + fn UART1_TX(); + fn UART1_RX(); + fn UART2_TX(); + fn UART2_RX(); + fn I2C0_MS(); + fn I2C0_SL(); + fn I2C1_MS(); + fn I2C1_SL(); + fn I2C2_MS(); + fn I2C2_SL(); + fn Ethernet(); + fn U37(); + fn SpW(); + fn U39(); + fn DAC0(); + fn DAC1(); + fn TRNG(); + fn DMA_ERROR(); + fn ADC(); + fn LoCLK(); + fn LVD(); + fn WATCHDOG(); + fn TIM0(); + fn TIM1(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8(); + fn TIM9(); + fn TIM10(); + fn TIM11(); + fn TIM12(); + fn TIM13(); + fn TIM14(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM18(); + fn TIM19(); + fn TIM20(); + fn TIM21(); + fn TIM22(); + fn TIM23(); + fn CAN0(); + fn U73(); + fn CAN1(); + fn U75(); + fn EDAC_MBE(); + fn EDAC_SBE(); + fn PORTA0(); + fn PORTA1(); + fn PORTA2(); + fn PORTA3(); + fn PORTA4(); + fn PORTA5(); + fn PORTA6(); + fn PORTA7(); + fn PORTA8(); + fn PORTA9(); + fn PORTA10(); + fn PORTA11(); + fn PORTA12(); + fn PORTA13(); + fn PORTA14(); + fn PORTA15(); + fn PORTB0(); + fn PORTB1(); + fn PORTB2(); + fn PORTB3(); + fn PORTB4(); + fn PORTB5(); + fn PORTB6(); + fn PORTB7(); + fn PORTB8(); + fn PORTB9(); + fn PORTB10(); + fn PORTB11(); + fn PORTB12(); + fn PORTB13(); + fn PORTB14(); + fn PORTB15(); + fn PORTC0(); + fn PORTC1(); + fn PORTC2(); + fn PORTC3(); + fn PORTC4(); + fn PORTC5(); + fn PORTC6(); + fn PORTC7(); + fn PORTC8(); + fn PORTC9(); + fn PORTC10(); + fn PORTC11(); + fn PORTC12(); + fn PORTC13(); + fn PORTC14(); + fn PORTC15(); + fn PORTD0(); + fn PORTD1(); + fn PORTD2(); + fn PORTD3(); + fn PORTD4(); + fn PORTD5(); + fn PORTD6(); + fn PORTD7(); + fn PORTD8(); + fn PORTD9(); + fn PORTD10(); + fn PORTD11(); + fn PORTD12(); + fn PORTD13(); + fn PORTD14(); + fn PORTD15(); + fn PORTE0(); + fn PORTE1(); + fn PORTE2(); + fn PORTE3(); + fn PORTE4(); + fn PORTE5(); + fn PORTE6(); + fn PORTE7(); + fn PORTE8(); + fn PORTE9(); + fn PORTE10(); + fn PORTE11(); + fn PORTE12(); + fn PORTE13(); + fn PORTE14(); + fn PORTE15(); + fn PORTF0(); + fn PORTF1(); + fn PORTF2(); + fn PORTF3(); + fn PORTF4(); + fn PORTF5(); + fn PORTF6(); + fn PORTF7(); + fn PORTF8(); + fn PORTF9(); + fn PORTF10(); + fn PORTF11(); + fn PORTF12(); + fn PORTF13(); + fn PORTF14(); + fn PORTF15(); + fn DMA_ACTIVE0(); + fn DMA_ACTIVE1(); + fn DMA_ACTIVE2(); + fn DMA_ACTIVE3(); + fn DMA_DONE0(); + fn DMA_DONE1(); + fn DMA_DONE2(); + fn DMA_DONE3(); + fn I2C0_MS_RX(); + fn I2C0_MS_TX(); + fn I2C0_SL_RX(); + fn I2C0_SL_TX(); + fn I2C1_MS_RX(); + fn I2C1_MS_TX(); + fn I2C1_SL_RX(); + fn I2C1_SL_TX(); + fn I2C2_MS_RX(); + fn I2C2_MS_TX(); + fn I2C2_SL_RX(); + fn I2C2_SL_TX(); + fn FPU(); + fn TXEV(); +} +#[doc(hidden)] +#[repr(C)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 196] = [ + Vector { _handler: U0 }, + Vector { _handler: U1 }, + Vector { _handler: U2 }, + Vector { _handler: U3 }, + Vector { _handler: U4 }, + Vector { _handler: U5 }, + Vector { _handler: U6 }, + Vector { _handler: U7 }, + Vector { _handler: U8 }, + Vector { _handler: U9 }, + Vector { _handler: U10 }, + Vector { _handler: U11 }, + Vector { _handler: U12 }, + Vector { _handler: U13 }, + Vector { _handler: U14 }, + Vector { _handler: U15 }, + Vector { _handler: SPI0_TX }, + Vector { _handler: SPI0_RX }, + Vector { _handler: SPI1_TX }, + Vector { _handler: SPI1_RX }, + Vector { _handler: SPI2_TX }, + Vector { _handler: SPI2_RX }, + Vector { _handler: SPI3_TX }, + Vector { _handler: SPI3_RX }, + Vector { _handler: UART0_TX }, + Vector { _handler: UART0_RX }, + Vector { _handler: UART1_TX }, + Vector { _handler: UART1_RX }, + Vector { _handler: UART2_TX }, + Vector { _handler: UART2_RX }, + Vector { _handler: I2C0_MS }, + Vector { _handler: I2C0_SL }, + Vector { _handler: I2C1_MS }, + Vector { _handler: I2C1_SL }, + Vector { _handler: I2C2_MS }, + Vector { _handler: I2C2_SL }, + Vector { _handler: Ethernet }, + Vector { _handler: U37 }, + Vector { _handler: SpW }, + Vector { _handler: U39 }, + Vector { _handler: DAC0 }, + Vector { _handler: DAC1 }, + Vector { _handler: TRNG }, + Vector { + _handler: DMA_ERROR, + }, + Vector { _handler: ADC }, + Vector { _handler: LoCLK }, + Vector { _handler: LVD }, + Vector { _handler: WATCHDOG }, + Vector { _handler: TIM0 }, + Vector { _handler: TIM1 }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: TIM5 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { _handler: TIM8 }, + Vector { _handler: TIM9 }, + Vector { _handler: TIM10 }, + Vector { _handler: TIM11 }, + Vector { _handler: TIM12 }, + Vector { _handler: TIM13 }, + Vector { _handler: TIM14 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { _handler: TIM18 }, + Vector { _handler: TIM19 }, + Vector { _handler: TIM20 }, + Vector { _handler: TIM21 }, + Vector { _handler: TIM22 }, + Vector { _handler: TIM23 }, + Vector { _handler: CAN0 }, + Vector { _handler: U73 }, + Vector { _handler: CAN1 }, + Vector { _handler: U75 }, + Vector { _handler: EDAC_MBE }, + Vector { _handler: EDAC_SBE }, + Vector { _handler: PORTA0 }, + Vector { _handler: PORTA1 }, + Vector { _handler: PORTA2 }, + Vector { _handler: PORTA3 }, + Vector { _handler: PORTA4 }, + Vector { _handler: PORTA5 }, + Vector { _handler: PORTA6 }, + Vector { _handler: PORTA7 }, + Vector { _handler: PORTA8 }, + Vector { _handler: PORTA9 }, + Vector { _handler: PORTA10 }, + Vector { _handler: PORTA11 }, + Vector { _handler: PORTA12 }, + Vector { _handler: PORTA13 }, + Vector { _handler: PORTA14 }, + Vector { _handler: PORTA15 }, + Vector { _handler: PORTB0 }, + Vector { _handler: PORTB1 }, + Vector { _handler: PORTB2 }, + Vector { _handler: PORTB3 }, + Vector { _handler: PORTB4 }, + Vector { _handler: PORTB5 }, + Vector { _handler: PORTB6 }, + Vector { _handler: PORTB7 }, + Vector { _handler: PORTB8 }, + Vector { _handler: PORTB9 }, + Vector { _handler: PORTB10 }, + Vector { _handler: PORTB11 }, + Vector { _handler: PORTB12 }, + Vector { _handler: PORTB13 }, + Vector { _handler: PORTB14 }, + Vector { _handler: PORTB15 }, + Vector { _handler: PORTC0 }, + Vector { _handler: PORTC1 }, + Vector { _handler: PORTC2 }, + Vector { _handler: PORTC3 }, + Vector { _handler: PORTC4 }, + Vector { _handler: PORTC5 }, + Vector { _handler: PORTC6 }, + Vector { _handler: PORTC7 }, + Vector { _handler: PORTC8 }, + Vector { _handler: PORTC9 }, + Vector { _handler: PORTC10 }, + Vector { _handler: PORTC11 }, + Vector { _handler: PORTC12 }, + Vector { _handler: PORTC13 }, + Vector { _handler: PORTC14 }, + Vector { _handler: PORTC15 }, + Vector { _handler: PORTD0 }, + Vector { _handler: PORTD1 }, + Vector { _handler: PORTD2 }, + Vector { _handler: PORTD3 }, + Vector { _handler: PORTD4 }, + Vector { _handler: PORTD5 }, + Vector { _handler: PORTD6 }, + Vector { _handler: PORTD7 }, + Vector { _handler: PORTD8 }, + Vector { _handler: PORTD9 }, + Vector { _handler: PORTD10 }, + Vector { _handler: PORTD11 }, + Vector { _handler: PORTD12 }, + Vector { _handler: PORTD13 }, + Vector { _handler: PORTD14 }, + Vector { _handler: PORTD15 }, + Vector { _handler: PORTE0 }, + Vector { _handler: PORTE1 }, + Vector { _handler: PORTE2 }, + Vector { _handler: PORTE3 }, + Vector { _handler: PORTE4 }, + Vector { _handler: PORTE5 }, + Vector { _handler: PORTE6 }, + Vector { _handler: PORTE7 }, + Vector { _handler: PORTE8 }, + Vector { _handler: PORTE9 }, + Vector { _handler: PORTE10 }, + Vector { _handler: PORTE11 }, + Vector { _handler: PORTE12 }, + Vector { _handler: PORTE13 }, + Vector { _handler: PORTE14 }, + Vector { _handler: PORTE15 }, + Vector { _handler: PORTF0 }, + Vector { _handler: PORTF1 }, + Vector { _handler: PORTF2 }, + Vector { _handler: PORTF3 }, + Vector { _handler: PORTF4 }, + Vector { _handler: PORTF5 }, + Vector { _handler: PORTF6 }, + Vector { _handler: PORTF7 }, + Vector { _handler: PORTF8 }, + Vector { _handler: PORTF9 }, + Vector { _handler: PORTF10 }, + Vector { _handler: PORTF11 }, + Vector { _handler: PORTF12 }, + Vector { _handler: PORTF13 }, + Vector { _handler: PORTF14 }, + Vector { _handler: PORTF15 }, + Vector { + _handler: DMA_ACTIVE0, + }, + Vector { + _handler: DMA_ACTIVE1, + }, + Vector { + _handler: DMA_ACTIVE2, + }, + Vector { + _handler: DMA_ACTIVE3, + }, + Vector { + _handler: DMA_DONE0, + }, + Vector { + _handler: DMA_DONE1, + }, + Vector { + _handler: DMA_DONE2, + }, + Vector { + _handler: DMA_DONE3, + }, + Vector { + _handler: I2C0_MS_RX, + }, + Vector { + _handler: I2C0_MS_TX, + }, + Vector { + _handler: I2C0_SL_RX, + }, + Vector { + _handler: I2C0_SL_TX, + }, + Vector { + _handler: I2C1_MS_RX, + }, + Vector { + _handler: I2C1_MS_TX, + }, + Vector { + _handler: I2C1_SL_RX, + }, + Vector { + _handler: I2C1_SL_TX, + }, + Vector { + _handler: I2C2_MS_RX, + }, + Vector { + _handler: I2C2_MS_TX, + }, + Vector { + _handler: I2C2_SL_RX, + }, + Vector { + _handler: I2C2_SL_TX, + }, + Vector { _handler: FPU }, + Vector { _handler: TXEV }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - U0"] + U0 = 0, + #[doc = "1 - U1"] + U1 = 1, + #[doc = "2 - U2"] + U2 = 2, + #[doc = "3 - U3"] + U3 = 3, + #[doc = "4 - U4"] + U4 = 4, + #[doc = "5 - U5"] + U5 = 5, + #[doc = "6 - U6"] + U6 = 6, + #[doc = "7 - U7"] + U7 = 7, + #[doc = "8 - U8"] + U8 = 8, + #[doc = "9 - U9"] + U9 = 9, + #[doc = "10 - U10"] + U10 = 10, + #[doc = "11 - U11"] + U11 = 11, + #[doc = "12 - U12"] + U12 = 12, + #[doc = "13 - U13"] + U13 = 13, + #[doc = "14 - U14"] + U14 = 14, + #[doc = "15 - U15"] + U15 = 15, + #[doc = "16 - SPI0_TX"] + SPI0_TX = 16, + #[doc = "17 - SPI0_RX"] + SPI0_RX = 17, + #[doc = "18 - SPI1_TX"] + SPI1_TX = 18, + #[doc = "19 - SPI1_RX"] + SPI1_RX = 19, + #[doc = "20 - SPI2_TX"] + SPI2_TX = 20, + #[doc = "21 - SPI2_RX"] + SPI2_RX = 21, + #[doc = "22 - SPI3_TX"] + SPI3_TX = 22, + #[doc = "23 - SPI3_RX"] + SPI3_RX = 23, + #[doc = "24 - UART0_TX"] + UART0_TX = 24, + #[doc = "25 - UART0_RX"] + UART0_RX = 25, + #[doc = "26 - UART1_TX"] + UART1_TX = 26, + #[doc = "27 - UART1_RX"] + UART1_RX = 27, + #[doc = "28 - UART2_TX"] + UART2_TX = 28, + #[doc = "29 - UART2_RX"] + UART2_RX = 29, + #[doc = "30 - I2C0_MS"] + I2C0_MS = 30, + #[doc = "31 - I2C0_SL"] + I2C0_SL = 31, + #[doc = "32 - I2C1_MS"] + I2C1_MS = 32, + #[doc = "33 - I2C1_SL"] + I2C1_SL = 33, + #[doc = "34 - I2C2_MS"] + I2C2_MS = 34, + #[doc = "35 - I2C2_SL"] + I2C2_SL = 35, + #[doc = "36 - Ethernet"] + Ethernet = 36, + #[doc = "37 - U37"] + U37 = 37, + #[doc = "38 - SpW"] + SpW = 38, + #[doc = "39 - U39"] + U39 = 39, + #[doc = "40 - DAC0"] + DAC0 = 40, + #[doc = "41 - DAC1"] + DAC1 = 41, + #[doc = "42 - TRNG"] + TRNG = 42, + #[doc = "43 - DMA_ERROR"] + DMA_ERROR = 43, + #[doc = "44 - ADC"] + ADC = 44, + #[doc = "45 - LoCLK"] + LoCLK = 45, + #[doc = "46 - LVD"] + LVD = 46, + #[doc = "47 - WATCHDOG"] + WATCHDOG = 47, + #[doc = "48 - TIM0"] + TIM0 = 48, + #[doc = "49 - TIM1"] + TIM1 = 49, + #[doc = "50 - TIM2"] + TIM2 = 50, + #[doc = "51 - TIM3"] + TIM3 = 51, + #[doc = "52 - TIM4"] + TIM4 = 52, + #[doc = "53 - TIM5"] + TIM5 = 53, + #[doc = "54 - TIM6"] + TIM6 = 54, + #[doc = "55 - TIM7"] + TIM7 = 55, + #[doc = "56 - TIM8"] + TIM8 = 56, + #[doc = "57 - TIM9"] + TIM9 = 57, + #[doc = "58 - TIM10"] + TIM10 = 58, + #[doc = "59 - TIM11"] + TIM11 = 59, + #[doc = "60 - TIM12"] + TIM12 = 60, + #[doc = "61 - TIM13"] + TIM13 = 61, + #[doc = "62 - TIM14"] + TIM14 = 62, + #[doc = "63 - TIM15"] + TIM15 = 63, + #[doc = "64 - TIM16"] + TIM16 = 64, + #[doc = "65 - TIM17"] + TIM17 = 65, + #[doc = "66 - TIM18"] + TIM18 = 66, + #[doc = "67 - TIM19"] + TIM19 = 67, + #[doc = "68 - TIM20"] + TIM20 = 68, + #[doc = "69 - TIM21"] + TIM21 = 69, + #[doc = "70 - TIM22"] + TIM22 = 70, + #[doc = "71 - TIM23"] + TIM23 = 71, + #[doc = "72 - CAN0"] + CAN0 = 72, + #[doc = "73 - U73"] + U73 = 73, + #[doc = "74 - CAN1"] + CAN1 = 74, + #[doc = "75 - U75"] + U75 = 75, + #[doc = "76 - EDAC_MBE"] + EDAC_MBE = 76, + #[doc = "77 - EDAC_SBE"] + EDAC_SBE = 77, + #[doc = "78 - PORTA0"] + PORTA0 = 78, + #[doc = "79 - PORTA1"] + PORTA1 = 79, + #[doc = "80 - PORTA2"] + PORTA2 = 80, + #[doc = "81 - PORTA3"] + PORTA3 = 81, + #[doc = "82 - PORTA4"] + PORTA4 = 82, + #[doc = "83 - PORTA5"] + PORTA5 = 83, + #[doc = "84 - PORTA6"] + PORTA6 = 84, + #[doc = "85 - PORTA7"] + PORTA7 = 85, + #[doc = "86 - PORTA8"] + PORTA8 = 86, + #[doc = "87 - PORTA9"] + PORTA9 = 87, + #[doc = "88 - PORTA10"] + PORTA10 = 88, + #[doc = "89 - PORTA11"] + PORTA11 = 89, + #[doc = "90 - PORTA12"] + PORTA12 = 90, + #[doc = "91 - PORTA13"] + PORTA13 = 91, + #[doc = "92 - PORTA14"] + PORTA14 = 92, + #[doc = "93 - PORTA15"] + PORTA15 = 93, + #[doc = "94 - PORTB0"] + PORTB0 = 94, + #[doc = "95 - PORTB1"] + PORTB1 = 95, + #[doc = "96 - PORTB2"] + PORTB2 = 96, + #[doc = "97 - PORTB3"] + PORTB3 = 97, + #[doc = "98 - PORTB4"] + PORTB4 = 98, + #[doc = "99 - PORTB5"] + PORTB5 = 99, + #[doc = "100 - PORTB6"] + PORTB6 = 100, + #[doc = "101 - PORTB7"] + PORTB7 = 101, + #[doc = "102 - PORTB8"] + PORTB8 = 102, + #[doc = "103 - PORTB9"] + PORTB9 = 103, + #[doc = "104 - PORTB10"] + PORTB10 = 104, + #[doc = "105 - PORTB11"] + PORTB11 = 105, + #[doc = "106 - PORTB12"] + PORTB12 = 106, + #[doc = "107 - PORTB13"] + PORTB13 = 107, + #[doc = "108 - PORTB14"] + PORTB14 = 108, + #[doc = "109 - PORTB15"] + PORTB15 = 109, + #[doc = "110 - PORTC0"] + PORTC0 = 110, + #[doc = "111 - PORTC1"] + PORTC1 = 111, + #[doc = "112 - PORTC2"] + PORTC2 = 112, + #[doc = "113 - PORTC3"] + PORTC3 = 113, + #[doc = "114 - PORTC4"] + PORTC4 = 114, + #[doc = "115 - PORTC5"] + PORTC5 = 115, + #[doc = "116 - PORTC6"] + PORTC6 = 116, + #[doc = "117 - PORTC7"] + PORTC7 = 117, + #[doc = "118 - PORTC8"] + PORTC8 = 118, + #[doc = "119 - PORTC9"] + PORTC9 = 119, + #[doc = "120 - PORTC10"] + PORTC10 = 120, + #[doc = "121 - PORTC11"] + PORTC11 = 121, + #[doc = "122 - PORTC12"] + PORTC12 = 122, + #[doc = "123 - PORTC13"] + PORTC13 = 123, + #[doc = "124 - PORTC14"] + PORTC14 = 124, + #[doc = "125 - PORTC15"] + PORTC15 = 125, + #[doc = "126 - PORTD0"] + PORTD0 = 126, + #[doc = "127 - PORTD1"] + PORTD1 = 127, + #[doc = "128 - PORTD2"] + PORTD2 = 128, + #[doc = "129 - PORTD3"] + PORTD3 = 129, + #[doc = "130 - PORTD4"] + PORTD4 = 130, + #[doc = "131 - PORTD5"] + PORTD5 = 131, + #[doc = "132 - PORTD6"] + PORTD6 = 132, + #[doc = "133 - PORTD7"] + PORTD7 = 133, + #[doc = "134 - PORTD8"] + PORTD8 = 134, + #[doc = "135 - PORTD9"] + PORTD9 = 135, + #[doc = "136 - PORTD10"] + PORTD10 = 136, + #[doc = "137 - PORTD11"] + PORTD11 = 137, + #[doc = "138 - PORTD12"] + PORTD12 = 138, + #[doc = "139 - PORTD13"] + PORTD13 = 139, + #[doc = "140 - PORTD14"] + PORTD14 = 140, + #[doc = "141 - PORTD15"] + PORTD15 = 141, + #[doc = "142 - PORTE0"] + PORTE0 = 142, + #[doc = "143 - PORTE1"] + PORTE1 = 143, + #[doc = "144 - PORTE2"] + PORTE2 = 144, + #[doc = "145 - PORTE3"] + PORTE3 = 145, + #[doc = "146 - PORTE4"] + PORTE4 = 146, + #[doc = "147 - PORTE5"] + PORTE5 = 147, + #[doc = "148 - PORTE6"] + PORTE6 = 148, + #[doc = "149 - PORTE7"] + PORTE7 = 149, + #[doc = "150 - PORTE8"] + PORTE8 = 150, + #[doc = "151 - PORTE9"] + PORTE9 = 151, + #[doc = "152 - PORTE10"] + PORTE10 = 152, + #[doc = "153 - PORTE11"] + PORTE11 = 153, + #[doc = "154 - PORTE12"] + PORTE12 = 154, + #[doc = "155 - PORTE13"] + PORTE13 = 155, + #[doc = "156 - PORTE14"] + PORTE14 = 156, + #[doc = "157 - PORTE15"] + PORTE15 = 157, + #[doc = "158 - PORTF0"] + PORTF0 = 158, + #[doc = "159 - PORTF1"] + PORTF1 = 159, + #[doc = "160 - PORTF2"] + PORTF2 = 160, + #[doc = "161 - PORTF3"] + PORTF3 = 161, + #[doc = "162 - PORTF4"] + PORTF4 = 162, + #[doc = "163 - PORTF5"] + PORTF5 = 163, + #[doc = "164 - PORTF6"] + PORTF6 = 164, + #[doc = "165 - PORTF7"] + PORTF7 = 165, + #[doc = "166 - PORTF8"] + PORTF8 = 166, + #[doc = "167 - PORTF9"] + PORTF9 = 167, + #[doc = "168 - PORTF10"] + PORTF10 = 168, + #[doc = "169 - PORTF11"] + PORTF11 = 169, + #[doc = "170 - PORTF12"] + PORTF12 = 170, + #[doc = "171 - PORTF13"] + PORTF13 = 171, + #[doc = "172 - PORTF14"] + PORTF14 = 172, + #[doc = "173 - PORTF15"] + PORTF15 = 173, + #[doc = "174 - DMA_ACTIVE0"] + DMA_ACTIVE0 = 174, + #[doc = "175 - DMA_ACTIVE1"] + DMA_ACTIVE1 = 175, + #[doc = "176 - DMA_ACTIVE2"] + DMA_ACTIVE2 = 176, + #[doc = "177 - DMA_ACTIVE3"] + DMA_ACTIVE3 = 177, + #[doc = "178 - DMA_DONE0"] + DMA_DONE0 = 178, + #[doc = "179 - DMA_DONE1"] + DMA_DONE1 = 179, + #[doc = "180 - DMA_DONE2"] + DMA_DONE2 = 180, + #[doc = "181 - DMA_DONE3"] + DMA_DONE3 = 181, + #[doc = "182 - I2C0_MS_RX"] + I2C0_MS_RX = 182, + #[doc = "183 - I2C0_MS_TX"] + I2C0_MS_TX = 183, + #[doc = "184 - I2C0_SL_RX"] + I2C0_SL_RX = 184, + #[doc = "185 - I2C0_SL_TX"] + I2C0_SL_TX = 185, + #[doc = "186 - I2C1_MS_RX"] + I2C1_MS_RX = 186, + #[doc = "187 - I2C1_MS_TX"] + I2C1_MS_TX = 187, + #[doc = "188 - I2C1_SL_RX"] + I2C1_SL_RX = 188, + #[doc = "189 - I2C1_SL_TX"] + I2C1_SL_TX = 189, + #[doc = "190 - I2C2_MS_RX"] + I2C2_MS_RX = 190, + #[doc = "191 - I2C2_MS_TX"] + I2C2_MS_TX = 191, + #[doc = "192 - I2C2_SL_RX"] + I2C2_SL_RX = 192, + #[doc = "193 - I2C2_SL_TX"] + I2C2_SL_TX = 193, + #[doc = "194 - FPU"] + FPU = 194, + #[doc = "195 - TXEV"] + TXEV = 195, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Clock Generation Peripheral"] +pub type Clkgen = crate::Periph; +impl core::fmt::Debug for Clkgen { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Clkgen").finish() + } +} +#[doc = "Clock Generation Peripheral"] +pub mod clkgen; +#[doc = "System Configuration Peripheral"] +pub type Sysconfig = crate::Periph; +impl core::fmt::Debug for Sysconfig { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sysconfig").finish() + } +} +#[doc = "System Configuration Peripheral"] +pub mod sysconfig; +#[doc = "DMA Controller Block"] +pub type Dma = crate::Periph; +impl core::fmt::Debug for Dma { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dma").finish() + } +} +#[doc = "DMA Controller Block"] +pub mod dma; +#[doc = "IO Pin Configuration Peripheral"] +pub type Ioconfig = crate::Periph; +impl core::fmt::Debug for Ioconfig { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ioconfig").finish() + } +} +#[doc = "IO Pin Configuration Peripheral"] +pub mod ioconfig; +#[doc = "Utility Peripheral"] +pub type Utility = crate::Periph; +impl core::fmt::Debug for Utility { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Utility").finish() + } +} +#[doc = "Utility Peripheral"] +pub mod utility; +#[doc = "GPIO Peripheral"] +pub type Porta = crate::Periph; +impl core::fmt::Debug for Porta { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Porta").finish() + } +} +#[doc = "GPIO Peripheral"] +pub mod porta; +#[doc = "GPIO Peripheral"] +pub type Portb = crate::Periph; +impl core::fmt::Debug for Portb { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portb").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portb; +#[doc = "GPIO Peripheral"] +pub type Portc = crate::Periph; +impl core::fmt::Debug for Portc { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portc").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portc; +#[doc = "GPIO Peripheral"] +pub type Portd = crate::Periph; +impl core::fmt::Debug for Portd { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portd").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portd; +#[doc = "GPIO Peripheral"] +pub type Porte = crate::Periph; +impl core::fmt::Debug for Porte { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Porte").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as porte; +#[doc = "GPIO Peripheral"] +pub type Portf = crate::Periph; +impl core::fmt::Debug for Portf { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portf").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portf; +#[doc = "GPIO Peripheral"] +pub type Portg = crate::Periph; +impl core::fmt::Debug for Portg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portg").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portg; +#[doc = "Timer/Counter Peripheral"] +pub type Tim0 = crate::Periph; +impl core::fmt::Debug for Tim0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim0").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub mod tim0; +#[doc = "Timer/Counter Peripheral"] +pub type Tim1 = crate::Periph; +impl core::fmt::Debug for Tim1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim1").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim1; +#[doc = "Timer/Counter Peripheral"] +pub type Tim2 = crate::Periph; +impl core::fmt::Debug for Tim2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim2").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim2; +#[doc = "Timer/Counter Peripheral"] +pub type Tim3 = crate::Periph; +impl core::fmt::Debug for Tim3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim3").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim3; +#[doc = "Timer/Counter Peripheral"] +pub type Tim4 = crate::Periph; +impl core::fmt::Debug for Tim4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim4").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim4; +#[doc = "Timer/Counter Peripheral"] +pub type Tim5 = crate::Periph; +impl core::fmt::Debug for Tim5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim5").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim5; +#[doc = "Timer/Counter Peripheral"] +pub type Tim6 = crate::Periph; +impl core::fmt::Debug for Tim6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim6").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim6; +#[doc = "Timer/Counter Peripheral"] +pub type Tim7 = crate::Periph; +impl core::fmt::Debug for Tim7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim7").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim7; +#[doc = "Timer/Counter Peripheral"] +pub type Tim8 = crate::Periph; +impl core::fmt::Debug for Tim8 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim8").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim8; +#[doc = "Timer/Counter Peripheral"] +pub type Tim9 = crate::Periph; +impl core::fmt::Debug for Tim9 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim9").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim9; +#[doc = "Timer/Counter Peripheral"] +pub type Tim10 = crate::Periph; +impl core::fmt::Debug for Tim10 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim10").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim10; +#[doc = "Timer/Counter Peripheral"] +pub type Tim11 = crate::Periph; +impl core::fmt::Debug for Tim11 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim11").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim11; +#[doc = "Timer/Counter Peripheral"] +pub type Tim12 = crate::Periph; +impl core::fmt::Debug for Tim12 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim12").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim12; +#[doc = "Timer/Counter Peripheral"] +pub type Tim13 = crate::Periph; +impl core::fmt::Debug for Tim13 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim13").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim13; +#[doc = "Timer/Counter Peripheral"] +pub type Tim14 = crate::Periph; +impl core::fmt::Debug for Tim14 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim14").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim14; +#[doc = "Timer/Counter Peripheral"] +pub type Tim15 = crate::Periph; +impl core::fmt::Debug for Tim15 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim15").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim15; +#[doc = "Timer/Counter Peripheral"] +pub type Tim16 = crate::Periph; +impl core::fmt::Debug for Tim16 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim16").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim16; +#[doc = "Timer/Counter Peripheral"] +pub type Tim17 = crate::Periph; +impl core::fmt::Debug for Tim17 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim17").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim17; +#[doc = "Timer/Counter Peripheral"] +pub type Tim18 = crate::Periph; +impl core::fmt::Debug for Tim18 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim18").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim18; +#[doc = "Timer/Counter Peripheral"] +pub type Tim19 = crate::Periph; +impl core::fmt::Debug for Tim19 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim19").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim19; +#[doc = "Timer/Counter Peripheral"] +pub type Tim20 = crate::Periph; +impl core::fmt::Debug for Tim20 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim20").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim20; +#[doc = "Timer/Counter Peripheral"] +pub type Tim21 = crate::Periph; +impl core::fmt::Debug for Tim21 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim21").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim21; +#[doc = "Timer/Counter Peripheral"] +pub type Tim22 = crate::Periph; +impl core::fmt::Debug for Tim22 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim22").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim22; +#[doc = "Timer/Counter Peripheral"] +pub type Tim23 = crate::Periph; +impl core::fmt::Debug for Tim23 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim23").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim23; +#[doc = "UART Peripheral"] +pub type Uart0 = crate::Periph; +impl core::fmt::Debug for Uart0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Uart0").finish() + } +} +#[doc = "UART Peripheral"] +pub mod uart0; +#[doc = "UART Peripheral"] +pub type Uart1 = crate::Periph; +impl core::fmt::Debug for Uart1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Uart1").finish() + } +} +#[doc = "UART Peripheral"] +pub use self::uart0 as uart1; +#[doc = "UART Peripheral"] +pub type Uart2 = crate::Periph; +impl core::fmt::Debug for Uart2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Uart2").finish() + } +} +#[doc = "UART Peripheral"] +pub use self::uart0 as uart2; +#[doc = "SPI Peripheral"] +pub type Spi0 = crate::Periph; +impl core::fmt::Debug for Spi0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi0").finish() + } +} +#[doc = "SPI Peripheral"] +pub mod spi0; +#[doc = "SPI Peripheral"] +pub type Spi1 = crate::Periph; +impl core::fmt::Debug for Spi1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi1").finish() + } +} +#[doc = "SPI Peripheral"] +pub use self::spi0 as spi1; +#[doc = "SPI Peripheral"] +pub type Spi2 = crate::Periph; +impl core::fmt::Debug for Spi2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi2").finish() + } +} +#[doc = "SPI Peripheral"] +pub use self::spi0 as spi2; +#[doc = "SPI Peripheral"] +pub type Spi3 = crate::Periph; +impl core::fmt::Debug for Spi3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi3").finish() + } +} +#[doc = "SPI Peripheral"] +pub use self::spi0 as spi3; +#[doc = "I2C Peripheral"] +pub type I2c0 = crate::Periph; +impl core::fmt::Debug for I2c0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2c0").finish() + } +} +#[doc = "I2C Peripheral"] +pub mod i2c0; +#[doc = "I2C Peripheral"] +pub type I2c1 = crate::Periph; +impl core::fmt::Debug for I2c1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2c1").finish() + } +} +#[doc = "I2C Peripheral"] +pub use self::i2c0 as i2c1; +#[doc = "I2C Peripheral"] +pub type I2c2 = crate::Periph; +impl core::fmt::Debug for I2c2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2c2").finish() + } +} +#[doc = "I2C Peripheral"] +pub use self::i2c0 as i2c2; +#[doc = "CAN Peripheral"] +pub type Can0 = crate::Periph; +impl core::fmt::Debug for Can0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Can0").finish() + } +} +#[doc = "CAN Peripheral"] +pub mod can0; +#[doc = "CAN Peripheral"] +pub type Can1 = crate::Periph; +impl core::fmt::Debug for Can1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Can1").finish() + } +} +#[doc = "CAN Peripheral"] +pub use self::can0 as can1; +#[doc = "Analog to Digital Converter Peripheral"] +pub type Adc = crate::Periph; +impl core::fmt::Debug for Adc { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Adc").finish() + } +} +#[doc = "Analog to Digital Converter Peripheral"] +pub mod adc; +#[doc = "Digital to Analog Converter Peripheral"] +pub type Dac0 = crate::Periph; +impl core::fmt::Debug for Dac0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dac0").finish() + } +} +#[doc = "Digital to Analog Converter Peripheral"] +pub mod dac0; +#[doc = "Digital to Analog Converter Peripheral"] +pub type Dac1 = crate::Periph; +impl core::fmt::Debug for Dac1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dac1").finish() + } +} +#[doc = "Digital to Analog Converter Peripheral"] +pub use self::dac0 as dac1; +#[doc = "SpaceWire Peripheral"] +pub type Spw = crate::Periph; +impl core::fmt::Debug for Spw { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spw").finish() + } +} +#[doc = "SpaceWire Peripheral"] +pub mod spw; +#[doc = "Interrupt Router Peripheral"] +pub type IrqRouter = crate::Periph; +impl core::fmt::Debug for IrqRouter { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IrqRouter").finish() + } +} +#[doc = "Interrupt Router Peripheral"] +pub mod irq_router; +#[doc = "Watchdog Block Peripheral"] +pub type WatchDog = crate::Periph; +impl core::fmt::Debug for WatchDog { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WatchDog").finish() + } +} +#[doc = "Watchdog Block Peripheral"] +pub mod watch_dog; +#[doc = "True Random Number Generator"] +pub type Trng = crate::Periph; +impl core::fmt::Debug for Trng { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Trng").finish() + } +} +#[doc = "True Random Number Generator"] +pub mod trng; +#[doc = "Ethernet Block"] +pub type Eth = crate::Periph; +impl core::fmt::Debug for Eth { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Eth").finish() + } +} +#[doc = "Ethernet Block"] +pub mod eth; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "CLKGEN"] + pub clkgen: Clkgen, + #[doc = "SYSCONFIG"] + pub sysconfig: Sysconfig, + #[doc = "DMA"] + pub dma: Dma, + #[doc = "IOCONFIG"] + pub ioconfig: Ioconfig, + #[doc = "UTILITY"] + pub utility: Utility, + #[doc = "PORTA"] + pub porta: Porta, + #[doc = "PORTB"] + pub portb: Portb, + #[doc = "PORTC"] + pub portc: Portc, + #[doc = "PORTD"] + pub portd: Portd, + #[doc = "PORTE"] + pub porte: Porte, + #[doc = "PORTF"] + pub portf: Portf, + #[doc = "PORTG"] + pub portg: Portg, + #[doc = "TIM0"] + pub tim0: Tim0, + #[doc = "TIM1"] + pub tim1: Tim1, + #[doc = "TIM2"] + pub tim2: Tim2, + #[doc = "TIM3"] + pub tim3: Tim3, + #[doc = "TIM4"] + pub tim4: Tim4, + #[doc = "TIM5"] + pub tim5: Tim5, + #[doc = "TIM6"] + pub tim6: Tim6, + #[doc = "TIM7"] + pub tim7: Tim7, + #[doc = "TIM8"] + pub tim8: Tim8, + #[doc = "TIM9"] + pub tim9: Tim9, + #[doc = "TIM10"] + pub tim10: Tim10, + #[doc = "TIM11"] + pub tim11: Tim11, + #[doc = "TIM12"] + pub tim12: Tim12, + #[doc = "TIM13"] + pub tim13: Tim13, + #[doc = "TIM14"] + pub tim14: Tim14, + #[doc = "TIM15"] + pub tim15: Tim15, + #[doc = "TIM16"] + pub tim16: Tim16, + #[doc = "TIM17"] + pub tim17: Tim17, + #[doc = "TIM18"] + pub tim18: Tim18, + #[doc = "TIM19"] + pub tim19: Tim19, + #[doc = "TIM20"] + pub tim20: Tim20, + #[doc = "TIM21"] + pub tim21: Tim21, + #[doc = "TIM22"] + pub tim22: Tim22, + #[doc = "TIM23"] + pub tim23: Tim23, + #[doc = "UART0"] + pub uart0: Uart0, + #[doc = "UART1"] + pub uart1: Uart1, + #[doc = "UART2"] + pub uart2: Uart2, + #[doc = "SPI0"] + pub spi0: Spi0, + #[doc = "SPI1"] + pub spi1: Spi1, + #[doc = "SPI2"] + pub spi2: Spi2, + #[doc = "SPI3"] + pub spi3: Spi3, + #[doc = "I2C0"] + pub i2c0: I2c0, + #[doc = "I2C1"] + pub i2c1: I2c1, + #[doc = "I2C2"] + pub i2c2: I2c2, + #[doc = "CAN0"] + pub can0: Can0, + #[doc = "CAN1"] + pub can1: Can1, + #[doc = "ADC"] + pub adc: Adc, + #[doc = "DAC0"] + pub dac0: Dac0, + #[doc = "DAC1"] + pub dac1: Dac1, + #[doc = "SPW"] + pub spw: Spw, + #[doc = "IRQ_ROUTER"] + pub irq_router: IrqRouter, + #[doc = "WATCH_DOG"] + pub watch_dog: WatchDog, + #[doc = "TRNG"] + pub trng: Trng, + #[doc = "ETH"] + pub eth: Eth, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + clkgen: Clkgen::steal(), + sysconfig: Sysconfig::steal(), + dma: Dma::steal(), + ioconfig: Ioconfig::steal(), + utility: Utility::steal(), + porta: Porta::steal(), + portb: Portb::steal(), + portc: Portc::steal(), + portd: Portd::steal(), + porte: Porte::steal(), + portf: Portf::steal(), + portg: Portg::steal(), + tim0: Tim0::steal(), + tim1: Tim1::steal(), + tim2: Tim2::steal(), + tim3: Tim3::steal(), + tim4: Tim4::steal(), + tim5: Tim5::steal(), + tim6: Tim6::steal(), + tim7: Tim7::steal(), + tim8: Tim8::steal(), + tim9: Tim9::steal(), + tim10: Tim10::steal(), + tim11: Tim11::steal(), + tim12: Tim12::steal(), + tim13: Tim13::steal(), + tim14: Tim14::steal(), + tim15: Tim15::steal(), + tim16: Tim16::steal(), + tim17: Tim17::steal(), + tim18: Tim18::steal(), + tim19: Tim19::steal(), + tim20: Tim20::steal(), + tim21: Tim21::steal(), + tim22: Tim22::steal(), + tim23: Tim23::steal(), + uart0: Uart0::steal(), + uart1: Uart1::steal(), + uart2: Uart2::steal(), + spi0: Spi0::steal(), + spi1: Spi1::steal(), + spi2: Spi2::steal(), + spi3: Spi3::steal(), + i2c0: I2c0::steal(), + i2c1: I2c1::steal(), + i2c2: I2c2::steal(), + can0: Can0::steal(), + can1: Can1::steal(), + adc: Adc::steal(), + dac0: Dac0::steal(), + dac1: Dac1::steal(), + spw: Spw::steal(), + irq_router: IrqRouter::steal(), + watch_dog: WatchDog::steal(), + trng: Trng::steal(), + eth: Eth::steal(), + } + } +} diff --git a/va416xx/va416xx/src/porta.rs b/va416xx/va416xx/src/porta.rs new file mode 100644 index 0000000..88def19 --- /dev/null +++ b/va416xx/va416xx/src/porta.rs @@ -0,0 +1,424 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved_0_datain: [u8; 0x04], + _reserved_1_datainraw: [u8; 0x04], + _reserved_2_dataout: [u8; 0x04], + _reserved_3_dataoutraw: [u8; 0x04], + _reserved_4_setout: [u8; 0x04], + _reserved_5_clrout: [u8; 0x04], + _reserved_6_togout: [u8; 0x04], + _reserved_7_datamask: [u8; 0x04], + _reserved_8_dir: [u8; 0x04], + _reserved_9_pulse: [u8; 0x04], + _reserved_10_pulsebase: [u8; 0x04], + _reserved_11_delay: [u8; 0x04], + _reserved_12_delay: [u8; 0x04], + irq_sen: IrqSen, + irq_edge: IrqEdge, + irq_evt: IrqEvt, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + edge_status: EdgeStatus, + _reserved20: [u8; 0x03ac], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Data In Register by Byte"] + #[inline(always)] + pub const fn datainbyte(&self, n: usize) -> &Datainbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x00 - Data In Register by Byte"] + #[inline(always)] + pub fn datainbyte_iter(&self) -> impl Iterator { + (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(n).cast() }) + } + #[doc = "0x00 - Data In Register"] + #[inline(always)] + pub const fn datain(&self) -> &Datain { + unsafe { &*core::ptr::from_ref(self).cast::().cast() } + } + #[doc = "0x04 - Data In Raw Register by Byte"] + #[inline(always)] + pub const fn datainrawbyte(&self, n: usize) -> &Datainrawbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(4).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x04 - Data In Raw Register by Byte"] + #[inline(always)] + pub fn datainrawbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(4).add(n).cast() }) + } + #[doc = "0x04 - Data In Raw Register"] + #[inline(always)] + pub const fn datainraw(&self) -> &Datainraw { + unsafe { &*core::ptr::from_ref(self).cast::().add(4).cast() } + } + #[doc = "0x08 - Data Out Register by Byte"] + #[inline(always)] + pub const fn dataoutbyte(&self, n: usize) -> &Dataoutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(8).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x08 - Data Out Register by Byte"] + #[inline(always)] + pub fn dataoutbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(8).add(n).cast() }) + } + #[doc = "0x08 - Data Out Register"] + #[inline(always)] + pub const fn dataout(&self) -> &Dataout { + unsafe { &*core::ptr::from_ref(self).cast::().add(8).cast() } + } + #[doc = "0x0c - Data Out Register by Byte"] + #[inline(always)] + pub const fn dataoutrawbyte(&self, n: usize) -> &Dataoutrawbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(12).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x0c - Data Out Register by Byte"] + #[inline(always)] + pub fn dataoutrawbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(12).add(n).cast() }) + } + #[doc = "0x0c - Data Out Register"] + #[inline(always)] + pub const fn dataoutraw(&self) -> &Dataoutraw { + unsafe { &*core::ptr::from_ref(self).cast::().add(12).cast() } + } + #[doc = "0x10 - Set Out Register by Byte"] + #[inline(always)] + pub const fn setoutbyte(&self, n: usize) -> &Setoutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(16).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x10 - Set Out Register by Byte"] + #[inline(always)] + pub fn setoutbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(16).add(n).cast() }) + } + #[doc = "0x10 - Set Out Register"] + #[inline(always)] + pub const fn setout(&self) -> &Setout { + unsafe { &*core::ptr::from_ref(self).cast::().add(16).cast() } + } + #[doc = "0x14 - Clear Out Register by Byte"] + #[inline(always)] + pub const fn clroutbyte(&self, n: usize) -> &Clroutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(20).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x14 - Clear Out Register by Byte"] + #[inline(always)] + pub fn clroutbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(20).add(n).cast() }) + } + #[doc = "0x14 - Clear Out Register"] + #[inline(always)] + pub const fn clrout(&self) -> &Clrout { + unsafe { &*core::ptr::from_ref(self).cast::().add(20).cast() } + } + #[doc = "0x18 - Toggle Out Register by Byte"] + #[inline(always)] + pub const fn togoutbyte(&self, n: usize) -> &Togoutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(24).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x18 - Toggle Out Register by Byte"] + #[inline(always)] + pub fn togoutbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(24).add(n).cast() }) + } + #[doc = "0x18 - Toggle Out Register"] + #[inline(always)] + pub const fn togout(&self) -> &Togout { + unsafe { &*core::ptr::from_ref(self).cast::().add(24).cast() } + } + #[doc = "0x1c - Data Out Register by Byte"] + #[inline(always)] + pub const fn datamaskbyte(&self, n: usize) -> &Datamaskbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(28).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1c - Data Out Register by Byte"] + #[inline(always)] + pub fn datamaskbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(28).add(n).cast() }) + } + #[doc = "0x1c - Data mask Register"] + #[inline(always)] + pub const fn datamask(&self) -> &Datamask { + unsafe { &*core::ptr::from_ref(self).cast::().add(28).cast() } + } + #[doc = "0x20 - Direction Register by Byte"] + #[inline(always)] + pub const fn dirbyte(&self, n: usize) -> &Dirbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(32).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x20 - Direction Register by Byte"] + #[inline(always)] + pub fn dirbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(32).add(n).cast() }) + } + #[doc = "0x20 - Direction Register (1:Output, 0:Input)"] + #[inline(always)] + pub const fn dir(&self) -> &Dir { + unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } + } + #[doc = "0x24 - Pulse Mode Register by Byte"] + #[inline(always)] + pub const fn pulsebyte(&self, n: usize) -> &Pulsebyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(36).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x24 - Pulse Mode Register by Byte"] + #[inline(always)] + pub fn pulsebyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(36).add(n).cast() }) + } + #[doc = "0x24 - Pulse Mode Register"] + #[inline(always)] + pub const fn pulse(&self) -> &Pulse { + unsafe { &*core::ptr::from_ref(self).cast::().add(36).cast() } + } + #[doc = "0x28 - Pulse Base Mode Register by Byte"] + #[inline(always)] + pub const fn pulsebasebyte(&self, n: usize) -> &Pulsebasebyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(40).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x28 - Pulse Base Mode Register by Byte"] + #[inline(always)] + pub fn pulsebasebyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(40).add(n).cast() }) + } + #[doc = "0x28 - Pulse Base Value Register"] + #[inline(always)] + pub const fn pulsebase(&self) -> &Pulsebase { + unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } + } + #[doc = "0x2c - Delay1 Register by Byte"] + #[inline(always)] + pub const fn delay1byte(&self, n: usize) -> &Delay1byte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(44).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c - Delay1 Register by Byte"] + #[inline(always)] + pub fn delay1byte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(44).add(n).cast() }) + } + #[doc = "0x2c - Delay1 Register"] + #[inline(always)] + pub const fn delay1(&self) -> &Delay1 { + unsafe { &*core::ptr::from_ref(self).cast::().add(44).cast() } + } + #[doc = "0x30 - Delay2 Register by Byte"] + #[inline(always)] + pub const fn delay2byte(&self, n: usize) -> &Delay2byte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*core::ptr::from_ref(self).cast::().add(48).add(n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x30 - Delay2 Register by Byte"] + #[inline(always)] + pub fn delay2byte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::().add(48).add(n).cast() }) + } + #[doc = "0x30 - Delay2 Register"] + #[inline(always)] + pub const fn delay2(&self) -> &Delay2 { + unsafe { &*core::ptr::from_ref(self).cast::().add(48).cast() } + } + #[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] + #[inline(always)] + pub const fn irq_sen(&self) -> &IrqSen { + &self.irq_sen + } + #[doc = "0x38 - Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] + #[inline(always)] + pub const fn irq_edge(&self) -> &IrqEdge { + &self.irq_edge + } + #[doc = "0x3c - Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] + #[inline(always)] + pub const fn irq_evt(&self) -> &IrqEvt { + &self.irq_evt + } + #[doc = "0x40 - Interrupt Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x44 - Raw Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x48 - Masked Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x4c - Edge Status Register"] + #[inline(always)] + pub const fn edge_status(&self) -> &EdgeStatus { + &self.edge_status + } + #[doc = "0x3fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`] module"] +#[doc(alias = "DATAIN")] +pub type Datain = crate::Reg; +#[doc = "Data In Register"] +pub mod datain; +#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`] module"] +#[doc(alias = "DATAINBYTE")] +pub type Datainbyte = crate::Reg; +#[doc = "Data In Register by Byte"] +pub mod datainbyte; +pub use datain as datainraw; +pub use datainbyte as datainrawbyte; +pub use Datain as Datainraw; +pub use Datainbyte as Datainrawbyte; +#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`] module"] +#[doc(alias = "DATAOUT")] +pub type Dataout = crate::Reg; +#[doc = "Data Out Register"] +pub mod dataout; +#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`] module"] +#[doc(alias = "DATAOUTBYTE")] +pub type Dataoutbyte = crate::Reg; +#[doc = "Data Out Register by Byte"] +pub mod dataoutbyte; +pub use dataout as dataoutraw; +pub use dataout as setout; +pub use dataout as clrout; +pub use dataout as togout; +pub use dataoutbyte as dataoutrawbyte; +pub use dataoutbyte as setoutbyte; +pub use dataoutbyte as clroutbyte; +pub use dataoutbyte as togoutbyte; +pub use Dataout as Dataoutraw; +pub use Dataout as Setout; +pub use Dataout as Clrout; +pub use Dataout as Togout; +pub use Dataoutbyte as Dataoutrawbyte; +pub use Dataoutbyte as Setoutbyte; +pub use Dataoutbyte as Clroutbyte; +pub use Dataoutbyte as Togoutbyte; +#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`] module"] +#[doc(alias = "DATAMASK")] +pub type Datamask = crate::Reg; +#[doc = "Data mask Register"] +pub mod datamask; +#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`] module"] +#[doc(alias = "DATAMASKBYTE")] +pub type Datamaskbyte = crate::Reg; +#[doc = "Data Out Register by Byte"] +pub mod datamaskbyte; +pub use datamask as dir; +pub use datamask as pulse; +pub use datamask as pulsebase; +pub use datamask as delay1; +pub use datamask as delay2; +pub use datamaskbyte as dirbyte; +pub use datamaskbyte as pulsebyte; +pub use datamaskbyte as pulsebasebyte; +pub use datamaskbyte as delay1byte; +pub use datamaskbyte as delay2byte; +pub use Datamask as Dir; +pub use Datamask as Pulse; +pub use Datamask as Pulsebase; +pub use Datamask as Delay1; +pub use Datamask as Delay2; +pub use Datamaskbyte as Dirbyte; +pub use Datamaskbyte as Pulsebyte; +pub use Datamaskbyte as Pulsebasebyte; +pub use Datamaskbyte as Delay1byte; +pub use Datamaskbyte as Delay2byte; +#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`] module"] +#[doc(alias = "IRQ_SEN")] +pub type IrqSen = crate::Reg; +#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] +pub mod irq_sen; +#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`] module"] +#[doc(alias = "IRQ_EDGE")] +pub type IrqEdge = crate::Reg; +#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] +pub mod irq_edge; +#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`] module"] +#[doc(alias = "IRQ_EVT")] +pub type IrqEvt = crate::Reg; +#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] +pub mod irq_evt; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] module"] +#[doc(alias = "IRQ_RAW")] +pub type IrqRaw = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] module"] +#[doc(alias = "IRQ_END")] +pub type IrqEnd = crate::Reg; +#[doc = "Masked Interrupt Status"] +pub mod irq_end; +#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`] module"] +#[doc(alias = "EDGE_STATUS")] +pub type EdgeStatus = crate::Reg; +#[doc = "Edge Status Register"] +pub mod edge_status; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/porta/datain.rs b/va416xx/va416xx/src/porta/datain.rs new file mode 100644 index 0000000..713b210 --- /dev/null +++ b/va416xx/va416xx/src/porta/datain.rs @@ -0,0 +1,17 @@ +#[doc = "Register `DATAIN` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatainSpec; +impl crate::RegisterSpec for DatainSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`datain::R`](R) reader structure"] +impl crate::Readable for DatainSpec {} +#[doc = "`reset()` method sets DATAIN to value 0"] +impl crate::Resettable for DatainSpec {} diff --git a/va416xx/va416xx/src/porta/datainbyte.rs b/va416xx/va416xx/src/porta/datainbyte.rs new file mode 100644 index 0000000..2b15efa --- /dev/null +++ b/va416xx/va416xx/src/porta/datainbyte.rs @@ -0,0 +1,17 @@ +#[doc = "Register `DATAINBYTE[%s]` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatainbyteSpec; +impl crate::RegisterSpec for DatainbyteSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`datainbyte::R`](R) reader structure"] +impl crate::Readable for DatainbyteSpec {} +#[doc = "`reset()` method sets DATAINBYTE[%s] to value 0"] +impl crate::Resettable for DatainbyteSpec {} diff --git a/va416xx/va416xx/src/porta/datamask.rs b/va416xx/va416xx/src/porta/datamask.rs new file mode 100644 index 0000000..e9f72a7 --- /dev/null +++ b/va416xx/va416xx/src/porta/datamask.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATAMASK` reader"] +pub type R = crate::R; +#[doc = "Register `DATAMASK` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatamaskSpec; +impl crate::RegisterSpec for DatamaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`datamask::R`](R) reader structure"] +impl crate::Readable for DatamaskSpec {} +#[doc = "`write(|w| ..)` method takes [`datamask::W`](W) writer structure"] +impl crate::Writable for DatamaskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATAMASK to value 0"] +impl crate::Resettable for DatamaskSpec {} diff --git a/va416xx/va416xx/src/porta/datamaskbyte.rs b/va416xx/va416xx/src/porta/datamaskbyte.rs new file mode 100644 index 0000000..e7a812a --- /dev/null +++ b/va416xx/va416xx/src/porta/datamaskbyte.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATAMASKBYTE[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `DATAMASKBYTE[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatamaskbyteSpec; +impl crate::RegisterSpec for DatamaskbyteSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`datamaskbyte::R`](R) reader structure"] +impl crate::Readable for DatamaskbyteSpec {} +#[doc = "`write(|w| ..)` method takes [`datamaskbyte::W`](W) writer structure"] +impl crate::Writable for DatamaskbyteSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATAMASKBYTE[%s] to value 0"] +impl crate::Resettable for DatamaskbyteSpec {} diff --git a/va416xx/va416xx/src/porta/dataout.rs b/va416xx/va416xx/src/porta/dataout.rs new file mode 100644 index 0000000..59207cb --- /dev/null +++ b/va416xx/va416xx/src/porta/dataout.rs @@ -0,0 +1,20 @@ +#[doc = "Register `DATAOUT` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W {} +#[doc = "Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataoutSpec; +impl crate::RegisterSpec for DataoutSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`dataout::W`](W) writer structure"] +impl crate::Writable for DataoutSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATAOUT to value 0"] +impl crate::Resettable for DataoutSpec {} diff --git a/va416xx/va416xx/src/porta/dataoutbyte.rs b/va416xx/va416xx/src/porta/dataoutbyte.rs new file mode 100644 index 0000000..3261f34 --- /dev/null +++ b/va416xx/va416xx/src/porta/dataoutbyte.rs @@ -0,0 +1,20 @@ +#[doc = "Register `DATAOUTBYTE[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W {} +#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataoutbyteSpec; +impl crate::RegisterSpec for DataoutbyteSpec { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [`dataoutbyte::W`](W) writer structure"] +impl crate::Writable for DataoutbyteSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATAOUTBYTE[%s] to value 0"] +impl crate::Resettable for DataoutbyteSpec {} diff --git a/va416xx/va416xx/src/porta/edge_status.rs b/va416xx/va416xx/src/porta/edge_status.rs new file mode 100644 index 0000000..da93837 --- /dev/null +++ b/va416xx/va416xx/src/porta/edge_status.rs @@ -0,0 +1,24 @@ +#[doc = "Register `EDGE_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `EDGE_STATUS` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EdgeStatusSpec; +impl crate::RegisterSpec for EdgeStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`edge_status::R`](R) reader structure"] +impl crate::Readable for EdgeStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`edge_status::W`](W) writer structure"] +impl crate::Writable for EdgeStatusSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EDGE_STATUS to value 0"] +impl crate::Resettable for EdgeStatusSpec {} diff --git a/va416xx/va416xx/src/porta/irq_edge.rs b/va416xx/va416xx/src/porta/irq_edge.rs new file mode 100644 index 0000000..130ee47 --- /dev/null +++ b/va416xx/va416xx/src/porta/irq_edge.rs @@ -0,0 +1,24 @@ +#[doc = "Register `IRQ_EDGE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_EDGE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEdgeSpec; +impl crate::RegisterSpec for IrqEdgeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_edge::R`](R) reader structure"] +impl crate::Readable for IrqEdgeSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_edge::W`](W) writer structure"] +impl crate::Writable for IrqEdgeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_EDGE to value 0"] +impl crate::Resettable for IrqEdgeSpec {} diff --git a/va416xx/va416xx/src/porta/irq_enb.rs b/va416xx/va416xx/src/porta/irq_enb.rs new file mode 100644 index 0000000..64d6f21 --- /dev/null +++ b/va416xx/va416xx/src/porta/irq_enb.rs @@ -0,0 +1,24 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va416xx/va416xx/src/porta/irq_end.rs b/va416xx/va416xx/src/porta/irq_end.rs new file mode 100644 index 0000000..f051d70 --- /dev/null +++ b/va416xx/va416xx/src/porta/irq_end.rs @@ -0,0 +1,17 @@ +#[doc = "Register `IRQ_END` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEndSpec; +impl crate::RegisterSpec for IrqEndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"] +impl crate::Readable for IrqEndSpec {} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IrqEndSpec {} diff --git a/va416xx/va416xx/src/porta/irq_evt.rs b/va416xx/va416xx/src/porta/irq_evt.rs new file mode 100644 index 0000000..075b780 --- /dev/null +++ b/va416xx/va416xx/src/porta/irq_evt.rs @@ -0,0 +1,24 @@ +#[doc = "Register `IRQ_EVT` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_EVT` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEvtSpec; +impl crate::RegisterSpec for IrqEvtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_evt::R`](R) reader structure"] +impl crate::Readable for IrqEvtSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_evt::W`](W) writer structure"] +impl crate::Writable for IrqEvtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_EVT to value 0"] +impl crate::Resettable for IrqEvtSpec {} diff --git a/va416xx/va416xx/src/porta/irq_raw.rs b/va416xx/va416xx/src/porta/irq_raw.rs new file mode 100644 index 0000000..5278bfb --- /dev/null +++ b/va416xx/va416xx/src/porta/irq_raw.rs @@ -0,0 +1,17 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqRawSpec; +impl crate::RegisterSpec for IrqRawSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"] +impl crate::Readable for IrqRawSpec {} +#[doc = "`reset()` method sets IRQ_RAW to value 0"] +impl crate::Resettable for IrqRawSpec {} diff --git a/va416xx/va416xx/src/porta/irq_sen.rs b/va416xx/va416xx/src/porta/irq_sen.rs new file mode 100644 index 0000000..0f75eb6 --- /dev/null +++ b/va416xx/va416xx/src/porta/irq_sen.rs @@ -0,0 +1,24 @@ +#[doc = "Register `IRQ_SEN` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_SEN` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqSenSpec; +impl crate::RegisterSpec for IrqSenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_sen::R`](R) reader structure"] +impl crate::Readable for IrqSenSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_sen::W`](W) writer structure"] +impl crate::Writable for IrqSenSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_SEN to value 0"] +impl crate::Resettable for IrqSenSpec {} diff --git a/va416xx/va416xx/src/porta/perid.rs b/va416xx/va416xx/src/porta/perid.rs new file mode 100644 index 0000000..0ca4da2 --- /dev/null +++ b/va416xx/va416xx/src/porta/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0210_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0210_07e9; +} diff --git a/va416xx/va416xx/src/spi0.rs b/va416xx/va416xx/src/spi0.rs new file mode 100644 index 0000000..21f969b --- /dev/null +++ b/va416xx/va416xx/src/spi0.rs @@ -0,0 +1,152 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl0: Ctrl0, + ctrl1: Ctrl1, + data: Data, + status: Status, + clkprescale: Clkprescale, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + txfifoirqtrg: Txfifoirqtrg, + fifo_clr: FifoClr, + state: State, + _reserved13: [u8; 0x03c8], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register 0"] + #[inline(always)] + pub const fn ctrl0(&self) -> &Ctrl0 { + &self.ctrl0 + } + #[doc = "0x04 - Control Register 1"] + #[inline(always)] + pub const fn ctrl1(&self) -> &Ctrl1 { + &self.ctrl1 + } + #[doc = "0x08 - Data Input/Output"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x0c - Status Register"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x10 - Clock Pre Scale divide value"] + #[inline(always)] + pub const fn clkprescale(&self) -> &Clkprescale { + &self.clkprescale + } + #[doc = "0x14 - Interrupt Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x18 - Raw Interrupt Status Register"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x1c - Enabled Interrupt Status Register"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x20 - Clear Interrupt Status Register"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x24 - Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x28 - Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x2c - Clear FIFO Register"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x30 - Internal STATE of SPI Controller"] + #[inline(always)] + pub const fn state(&self) -> &State { + &self.state + } + #[doc = "0x3fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] module"] +#[doc(alias = "CTRL0")] +pub type Ctrl0 = crate::Reg; +#[doc = "Control Register 0"] +pub mod ctrl0; +#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"] +#[doc(alias = "CTRL1")] +pub type Ctrl1 = crate::Reg; +#[doc = "Control Register 1"] +pub mod ctrl1; +#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data Input/Output"] +pub mod data; +#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`] module"] +#[doc(alias = "CLKPRESCALE")] +pub type Clkprescale = crate::Reg; +#[doc = "Clock Pre Scale divide value"] +pub mod clkprescale; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +#[doc(alias = "STATE")] +pub type State = crate::Reg; +#[doc = "Internal STATE of SPI Controller"] +pub mod state; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/spi0/clkprescale.rs b/va416xx/va416xx/src/spi0/clkprescale.rs new file mode 100644 index 0000000..f202eb8 --- /dev/null +++ b/va416xx/va416xx/src/spi0/clkprescale.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CLKPRESCALE` reader"] +pub type R = crate::R; +#[doc = "Register `CLKPRESCALE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkprescaleSpec; +impl crate::RegisterSpec for ClkprescaleSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkprescale::R`](R) reader structure"] +impl crate::Readable for ClkprescaleSpec {} +#[doc = "`write(|w| ..)` method takes [`clkprescale::W`](W) writer structure"] +impl crate::Writable for ClkprescaleSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKPRESCALE to value 0"] +impl crate::Resettable for ClkprescaleSpec {} diff --git a/va416xx/va416xx/src/spi0/ctrl0.rs b/va416xx/va416xx/src/spi0/ctrl0.rs new file mode 100644 index 0000000..29abe30 --- /dev/null +++ b/va416xx/va416xx/src/spi0/ctrl0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `SIZE` reader - Data Size(0x3=>4, 0xf=>16)"] +pub type SizeR = crate::FieldReader; +#[doc = "Field `SIZE` writer - Data Size(0x3=>4, 0xf=>16)"] +pub type SizeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SPO` reader - SPI Clock Polarity"] +pub type SpoR = crate::BitReader; +#[doc = "Field `SPO` writer - SPI Clock Polarity"] +pub type SpoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPH` reader - SPI Clock Phase"] +pub type SphR = crate::BitReader; +#[doc = "Field `SPH` writer - SPI Clock Phase"] +pub type SphW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCRDV` reader - Serial Clock Rate divide+1 value"] +pub type ScrdvR = crate::FieldReader; +#[doc = "Field `SCRDV` writer - Serial Clock Rate divide+1 value"] +pub type ScrdvW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] + #[inline(always)] + pub fn size(&self) -> SizeR { + SizeR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - SPI Clock Polarity"] + #[inline(always)] + pub fn spo(&self) -> SpoR { + SpoR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - SPI Clock Phase"] + #[inline(always)] + pub fn sph(&self) -> SphR { + SphR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] + #[inline(always)] + pub fn scrdv(&self) -> ScrdvR { + ScrdvR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] + #[inline(always)] + pub fn size(&mut self) -> SizeW<'_, Ctrl0Spec> { + SizeW::new(self, 0) + } + #[doc = "Bit 6 - SPI Clock Polarity"] + #[inline(always)] + pub fn spo(&mut self) -> SpoW<'_, Ctrl0Spec> { + SpoW::new(self, 6) + } + #[doc = "Bit 7 - SPI Clock Phase"] + #[inline(always)] + pub fn sph(&mut self) -> SphW<'_, Ctrl0Spec> { + SphW::new(self, 7) + } + #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] + #[inline(always)] + pub fn scrdv(&mut self) -> ScrdvW<'_, Ctrl0Spec> { + ScrdvW::new(self, 8) + } +} +#[doc = "Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl0Spec; +impl crate::RegisterSpec for Ctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"] +impl crate::Readable for Ctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"] +impl crate::Writable for Ctrl0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL0 to value 0"] +impl crate::Resettable for Ctrl0Spec {} diff --git a/va416xx/va416xx/src/spi0/ctrl1.rs b/va416xx/va416xx/src/spi0/ctrl1.rs new file mode 100644 index 0000000..2c756fa --- /dev/null +++ b/va416xx/va416xx/src/spi0/ctrl1.rs @@ -0,0 +1,161 @@ +#[doc = "Register `CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `LBM` reader - Loop Back"] +pub type LbmR = crate::BitReader; +#[doc = "Field `LBM` writer - Loop Back"] +pub type LbmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MS` reader - Master/Slave (0:Master, 1:Slave)"] +pub type MsR = crate::BitReader; +#[doc = "Field `MS` writer - Master/Slave (0:Master, 1:Slave)"] +pub type MsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOD` reader - Slave output Disable"] +pub type SodR = crate::BitReader; +#[doc = "Field `SOD` writer - Slave output Disable"] +pub type SodW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SS` reader - Slave Select"] +pub type SsR = crate::FieldReader; +#[doc = "Field `SS` writer - Slave Select"] +pub type SsW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `BLOCKMODE` reader - Block Mode Enable"] +pub type BlockmodeR = crate::BitReader; +#[doc = "Field `BLOCKMODE` writer - Block Mode Enable"] +pub type BlockmodeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BMSTART` reader - Block Mode Start Status Enable"] +pub type BmstartR = crate::BitReader; +#[doc = "Field `BMSTART` writer - Block Mode Start Status Enable"] +pub type BmstartW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BMSTALL` reader - Block Mode Stall Enable"] +pub type BmstallR = crate::BitReader; +#[doc = "Field `BMSTALL` writer - Block Mode Stall Enable"] +pub type BmstallW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MDLYCAP` reader - Master Delayed Capture Enable"] +pub type MdlycapR = crate::BitReader; +#[doc = "Field `MDLYCAP` writer - Master Delayed Capture Enable"] +pub type MdlycapW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MTXPAUSE` reader - Master Tx Pause Enable"] +pub type MtxpauseR = crate::BitReader; +#[doc = "Field `MTXPAUSE` writer - Master Tx Pause Enable"] +pub type MtxpauseW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Loop Back"] + #[inline(always)] + pub fn lbm(&self) -> LbmR { + LbmR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] + #[inline(always)] + pub fn ms(&self) -> MsR { + MsR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave output Disable"] + #[inline(always)] + pub fn sod(&self) -> SodR { + SodR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Slave Select"] + #[inline(always)] + pub fn ss(&self) -> SsR { + SsR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Block Mode Enable"] + #[inline(always)] + pub fn blockmode(&self) -> BlockmodeR { + BlockmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Block Mode Start Status Enable"] + #[inline(always)] + pub fn bmstart(&self) -> BmstartR { + BmstartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Block Mode Stall Enable"] + #[inline(always)] + pub fn bmstall(&self) -> BmstallR { + BmstallR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Master Delayed Capture Enable"] + #[inline(always)] + pub fn mdlycap(&self) -> MdlycapR { + MdlycapR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Master Tx Pause Enable"] + #[inline(always)] + pub fn mtxpause(&self) -> MtxpauseR { + MtxpauseR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop Back"] + #[inline(always)] + pub fn lbm(&mut self) -> LbmW<'_, Ctrl1Spec> { + LbmW::new(self, 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, Ctrl1Spec> { + EnableW::new(self, 1) + } + #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] + #[inline(always)] + pub fn ms(&mut self) -> MsW<'_, Ctrl1Spec> { + MsW::new(self, 2) + } + #[doc = "Bit 3 - Slave output Disable"] + #[inline(always)] + pub fn sod(&mut self) -> SodW<'_, Ctrl1Spec> { + SodW::new(self, 3) + } + #[doc = "Bits 4:6 - Slave Select"] + #[inline(always)] + pub fn ss(&mut self) -> SsW<'_, Ctrl1Spec> { + SsW::new(self, 4) + } + #[doc = "Bit 7 - Block Mode Enable"] + #[inline(always)] + pub fn blockmode(&mut self) -> BlockmodeW<'_, Ctrl1Spec> { + BlockmodeW::new(self, 7) + } + #[doc = "Bit 8 - Block Mode Start Status Enable"] + #[inline(always)] + pub fn bmstart(&mut self) -> BmstartW<'_, Ctrl1Spec> { + BmstartW::new(self, 8) + } + #[doc = "Bit 9 - Block Mode Stall Enable"] + #[inline(always)] + pub fn bmstall(&mut self) -> BmstallW<'_, Ctrl1Spec> { + BmstallW::new(self, 9) + } + #[doc = "Bit 10 - Master Delayed Capture Enable"] + #[inline(always)] + pub fn mdlycap(&mut self) -> MdlycapW<'_, Ctrl1Spec> { + MdlycapW::new(self, 10) + } + #[doc = "Bit 11 - Master Tx Pause Enable"] + #[inline(always)] + pub fn mtxpause(&mut self) -> MtxpauseW<'_, Ctrl1Spec> { + MtxpauseW::new(self, 11) + } +} +#[doc = "Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1Spec; +impl crate::RegisterSpec for Ctrl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"] +impl crate::Readable for Ctrl1Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] +impl crate::Writable for Ctrl1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for Ctrl1Spec {} diff --git a/va416xx/va416xx/src/spi0/data.rs b/va416xx/va416xx/src/spi0/data.rs new file mode 100644 index 0000000..8968f26 --- /dev/null +++ b/va416xx/va416xx/src/spi0/data.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec {} diff --git a/va416xx/va416xx/src/spi0/fifo_clr.rs b/va416xx/va416xx/src/spi0/fifo_clr.rs new file mode 100644 index 0000000..339ac41 --- /dev/null +++ b/va416xx/va416xx/src/spi0/fifo_clr.rs @@ -0,0 +1,29 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> { + TxfifoW::new(self, 1) + } +} +#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec {} diff --git a/va416xx/va416xx/src/spi0/irq_enb.rs b/va416xx/va416xx/src/spi0/irq_enb.rs new file mode 100644 index 0000000..325da2d --- /dev/null +++ b/va416xx/va416xx/src/spi0/irq_enb.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `RORIM` reader - RX Overrun"] +pub type RorimR = crate::BitReader; +#[doc = "Field `RORIM` writer - RX Overrun"] +pub type RorimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTIM` reader - RX Timeout"] +pub type RtimR = crate::BitReader; +#[doc = "Field `RTIM` writer - RX Timeout"] +pub type RtimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXIM` reader - RX Fifo is at least half full"] +pub type RximR = crate::BitReader; +#[doc = "Field `RXIM` writer - RX Fifo is at least half full"] +pub type RximW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"] +pub type TximR = crate::BitReader; +#[doc = "Field `TXIM` writer - TX Fifo is at least half empty"] +pub type TximW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&self) -> RorimR { + RorimR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&self) -> RtimR { + RtimR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&self) -> RximR { + RximR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&self) -> TximR { + TximR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&mut self) -> RorimW<'_, IrqEnbSpec> { + RorimW::new(self, 0) + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&mut self) -> RtimW<'_, IrqEnbSpec> { + RtimW::new(self, 1) + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&mut self) -> RximW<'_, IrqEnbSpec> { + RximW::new(self, 2) + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&mut self) -> TximW<'_, IrqEnbSpec> { + TximW::new(self, 3) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va416xx/va416xx/src/spi0/perid.rs b/va416xx/va416xx/src/spi0/perid.rs new file mode 100644 index 0000000..e1b3ea3 --- /dev/null +++ b/va416xx/va416xx/src/spi0/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0213_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0213_07e9; +} diff --git a/va416xx/va416xx/src/spi0/rxfifoirqtrg.rs b/va416xx/va416xx/src/spi0/rxfifoirqtrg.rs new file mode 100644 index 0000000..e38d450 --- /dev/null +++ b/va416xx/va416xx/src/spi0/rxfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RxfifoirqtrgSpec {} diff --git a/va416xx/va416xx/src/spi0/state.rs b/va416xx/va416xx/src/spi0/state.rs new file mode 100644 index 0000000..3a494cd --- /dev/null +++ b/va416xx/va416xx/src/spi0/state.rs @@ -0,0 +1,17 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StateSpec; +impl crate::RegisterSpec for StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for StateSpec {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for StateSpec {} diff --git a/va416xx/va416xx/src/spi0/status.rs b/va416xx/va416xx/src/spi0/status.rs new file mode 100644 index 0000000..0000307 --- /dev/null +++ b/va416xx/va416xx/src/spi0/status.rs @@ -0,0 +1,69 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TFE` reader - Transmit FIFO empty"] +pub type TfeR = crate::BitReader; +#[doc = "Field `TNF` reader - Transmit FIFO not full"] +pub type TnfR = crate::BitReader; +#[doc = "Field `RNE` reader - Receive FIFO not empty"] +pub type RneR = crate::BitReader; +#[doc = "Field `RFF` reader - Receive FIFO Full"] +pub type RffR = crate::BitReader; +#[doc = "Field `BUSY` reader - Busy"] +pub type BusyR = crate::BitReader; +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte in BLOCKMODE"] +pub type RxdatafirstR = crate::BitReader; +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub type RxtriggerR = crate::BitReader; +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub type TxtriggerR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty"] + #[inline(always)] + pub fn tfe(&self) -> TfeR { + TfeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full"] + #[inline(always)] + pub fn tnf(&self) -> TnfR { + TnfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty"] + #[inline(always)] + pub fn rne(&self) -> RneR { + RneR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO Full"] + #[inline(always)] + pub fn rff(&self) -> RffR { + RffR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BusyR { + BusyR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pending Data is first Byte in BLOCKMODE"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RxdatafirstR { + RxdatafirstR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RxtriggerR { + RxtriggerR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TxtriggerR { + TxtriggerR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec {} diff --git a/va416xx/va416xx/src/spi0/txfifoirqtrg.rs b/va416xx/va416xx/src/spi0/txfifoirqtrg.rs new file mode 100644 index 0000000..ea0e7d3 --- /dev/null +++ b/va416xx/va416xx/src/spi0/txfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TxfifoirqtrgSpec {} diff --git a/va416xx/va416xx/src/spw.rs b/va416xx/va416xx/src/spw.rs new file mode 100644 index 0000000..6084321 --- /dev/null +++ b/va416xx/va416xx/src/spw.rs @@ -0,0 +1,139 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + sts: Sts, + defaddr: Defaddr, + clkdiv: Clkdiv, + dkey: Dkey, + tc: Tc, + tdr: Tdr, + _reserved7: [u8; 0x04], + dmactrl0: Dmactrl0, + dmamaxlen0: Dmamaxlen0, + dmatxdesc0: Dmatxdesc0, + dmarxdesc0: Dmarxdesc0, + dmaaddr0: Dmaaddr0, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - Status/Interrupt Source Register"] + #[inline(always)] + pub const fn sts(&self) -> &Sts { + &self.sts + } + #[doc = "0x08 - Node Address Register"] + #[inline(always)] + pub const fn defaddr(&self) -> &Defaddr { + &self.defaddr + } + #[doc = "0x0c - Clock Divisor Register"] + #[inline(always)] + pub const fn clkdiv(&self) -> &Clkdiv { + &self.clkdiv + } + #[doc = "0x10 - Destination Key"] + #[inline(always)] + pub const fn dkey(&self) -> &Dkey { + &self.dkey + } + #[doc = "0x14 - Time Code Register"] + #[inline(always)] + pub const fn tc(&self) -> &Tc { + &self.tc + } + #[doc = "0x18 - Timer and Disconnect Register"] + #[inline(always)] + pub const fn tdr(&self) -> &Tdr { + &self.tdr + } + #[doc = "0x20 - DMA Control Register"] + #[inline(always)] + pub const fn dmactrl0(&self) -> &Dmactrl0 { + &self.dmactrl0 + } + #[doc = "0x24 - DMA RX Maximum Length Register"] + #[inline(always)] + pub const fn dmamaxlen0(&self) -> &Dmamaxlen0 { + &self.dmamaxlen0 + } + #[doc = "0x28 - DMA Transmitter Descriptor Table Address Register"] + #[inline(always)] + pub const fn dmatxdesc0(&self) -> &Dmatxdesc0 { + &self.dmatxdesc0 + } + #[doc = "0x2c - DMA Receiver Table Destination Register"] + #[inline(always)] + pub const fn dmarxdesc0(&self) -> &Dmarxdesc0 { + &self.dmarxdesc0 + } + #[doc = "0x30 - DMA Receiver Table Address Register"] + #[inline(always)] + pub const fn dmaaddr0(&self) -> &Dmaaddr0 { + &self.dmaaddr0 + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "STS (rw) register accessor: Status/Interrupt Source Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sts`] module"] +#[doc(alias = "STS")] +pub type Sts = crate::Reg; +#[doc = "Status/Interrupt Source Register"] +pub mod sts; +#[doc = "DEFADDR (rw) register accessor: Node Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`defaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`defaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@defaddr`] module"] +#[doc(alias = "DEFADDR")] +pub type Defaddr = crate::Reg; +#[doc = "Node Address Register"] +pub mod defaddr; +#[doc = "CLKDIV (rw) register accessor: Clock Divisor Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`] module"] +#[doc(alias = "CLKDIV")] +pub type Clkdiv = crate::Reg; +#[doc = "Clock Divisor Register"] +pub mod clkdiv; +#[doc = "DKEY (rw) register accessor: Destination Key\n\nYou can [`read`](crate::Reg::read) this register and get [`dkey::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dkey::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dkey`] module"] +#[doc(alias = "DKEY")] +pub type Dkey = crate::Reg; +#[doc = "Destination Key"] +pub mod dkey; +#[doc = "TC (rw) register accessor: Time Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`] module"] +#[doc(alias = "TC")] +pub type Tc = crate::Reg; +#[doc = "Time Code Register"] +pub mod tc; +#[doc = "TDR (r) register accessor: Timer and Disconnect Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdr`] module"] +#[doc(alias = "TDR")] +pub type Tdr = crate::Reg; +#[doc = "Timer and Disconnect Register"] +pub mod tdr; +#[doc = "DMACTRL0 (rw) register accessor: DMA Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactrl0`] module"] +#[doc(alias = "DMACTRL0")] +pub type Dmactrl0 = crate::Reg; +#[doc = "DMA Control Register"] +pub mod dmactrl0; +#[doc = "DMAMAXLEN0 (rw) register accessor: DMA RX Maximum Length Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmamaxlen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmamaxlen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmamaxlen0`] module"] +#[doc(alias = "DMAMAXLEN0")] +pub type Dmamaxlen0 = crate::Reg; +#[doc = "DMA RX Maximum Length Register"] +pub mod dmamaxlen0; +#[doc = "DMATXDESC0 (rw) register accessor: DMA Transmitter Descriptor Table Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmatxdesc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmatxdesc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmatxdesc0`] module"] +#[doc(alias = "DMATXDESC0")] +pub type Dmatxdesc0 = crate::Reg; +#[doc = "DMA Transmitter Descriptor Table Address Register"] +pub mod dmatxdesc0; +#[doc = "DMARXDESC0 (rw) register accessor: DMA Receiver Table Destination Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmarxdesc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmarxdesc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmarxdesc0`] module"] +#[doc(alias = "DMARXDESC0")] +pub type Dmarxdesc0 = crate::Reg; +#[doc = "DMA Receiver Table Destination Register"] +pub mod dmarxdesc0; +#[doc = "DMAADDR0 (rw) register accessor: DMA Receiver Table Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmaaddr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmaaddr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaaddr0`] module"] +#[doc(alias = "DMAADDR0")] +pub type Dmaaddr0 = crate::Reg; +#[doc = "DMA Receiver Table Address Register"] +pub mod dmaaddr0; diff --git a/va416xx/va416xx/src/spw/clkdiv.rs b/va416xx/va416xx/src/spw/clkdiv.rs new file mode 100644 index 0000000..c3531db --- /dev/null +++ b/va416xx/va416xx/src/spw/clkdiv.rs @@ -0,0 +1,51 @@ +#[doc = "Register `CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `CLKDIVRUN` reader - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] +pub type ClkdivrunR = crate::FieldReader; +#[doc = "Field `CLKDIVRUN` writer - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] +pub type ClkdivrunW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CLKDIVSTART` reader - 8-bit Clock divisor value used for the clock-divider during startup"] +pub type ClkdivstartR = crate::FieldReader; +#[doc = "Field `CLKDIVSTART` writer - 8-bit Clock divisor value used for the clock-divider during startup"] +pub type ClkdivstartW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] + #[inline(always)] + pub fn clkdivrun(&self) -> ClkdivrunR { + ClkdivrunR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - 8-bit Clock divisor value used for the clock-divider during startup"] + #[inline(always)] + pub fn clkdivstart(&self) -> ClkdivstartR { + ClkdivstartR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] + #[inline(always)] + pub fn clkdivrun(&mut self) -> ClkdivrunW<'_, ClkdivSpec> { + ClkdivrunW::new(self, 0) + } + #[doc = "Bits 8:15 - 8-bit Clock divisor value used for the clock-divider during startup"] + #[inline(always)] + pub fn clkdivstart(&mut self) -> ClkdivstartW<'_, ClkdivSpec> { + ClkdivstartW::new(self, 8) + } +} +#[doc = "Clock Divisor Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkdivSpec; +impl crate::RegisterSpec for ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv::R`](R) reader structure"] +impl crate::Readable for ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"] +impl crate::Writable for ClkdivSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKDIV to value 0x0909"] +impl crate::Resettable for ClkdivSpec { + const RESET_VALUE: u32 = 0x0909; +} diff --git a/va416xx/va416xx/src/spw/ctrl.rs b/va416xx/va416xx/src/spw/ctrl.rs new file mode 100644 index 0000000..796d9ea --- /dev/null +++ b/va416xx/va416xx/src/spw/ctrl.rs @@ -0,0 +1,345 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LD` reader - Disable the SpaceWire CODEC"] +pub type LdR = crate::BitReader; +#[doc = "Field `LD` writer - Disable the SpaceWire CODEC"] +pub type LdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LS` reader - Start the link"] +pub type LsR = crate::BitReader; +#[doc = "Field `LS` writer - Start the link"] +pub type LsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AS` reader - Automatically start the link when a NULL has been received"] +pub type AsR = crate::BitReader; +#[doc = "Field `AS` writer - Automatically start the link when a NULL has been received"] +pub type AsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IE` reader - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] +pub type IeR = crate::BitReader; +#[doc = "Field `IE` writer - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] +pub type IeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TI` reader - The host can generate a tick by writing a one to this field"] +pub type TiR = crate::BitReader; +#[doc = "Field `TI` writer - The host can generate a tick by writing a one to this field"] +pub type TiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PM` reader - Enable Promiscuous mode"] +pub type PmR = crate::BitReader; +#[doc = "Field `PM` writer - Enable Promiscuous mode"] +pub type PmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS` reader - Make complete reset of the SpaceWire node. Self-clearing"] +pub type RsR = crate::BitReader; +#[doc = "Field `RS` writer - Make complete reset of the SpaceWire node. Self-clearing"] +pub type RsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TQ` reader - Generate interrupt when a valid time-code is received"] +pub type TqR = crate::BitReader; +#[doc = "Field `TQ` writer - Generate interrupt when a valid time-code is received"] +pub type TqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LI` reader - Generate interrupt when link error occurs"] +pub type LiR = crate::BitReader; +#[doc = "Field `LI` writer - Generate interrupt when link error occurs"] +pub type LiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TT` reader - Enable time-code transmissions"] +pub type TtR = crate::BitReader; +#[doc = "Field `TT` writer - Enable time-code transmissions"] +pub type TtW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TR` reader - Enable time-code receptions"] +pub type TrR = crate::BitReader; +#[doc = "Field `TR` writer - Enable time-code receptions"] +pub type TrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TF` reader - Time-code Flag Filter"] +pub type TfR = crate::BitReader; +#[doc = "Field `TF` writer - Time-code Flag Filter"] +pub type TfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TL` reader - Transmitter Enable Lock Control"] +pub type TlR = crate::BitReader; +#[doc = "Field `TL` writer - Transmitter Enable Lock Control"] +pub type TlW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PE` reader - SpW Plug-and-Play Enable"] +pub type PeR = crate::BitReader; +#[doc = "Field `PE` writer - SpW Plug-and-Play Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RE` reader - Enable RMAP command handler"] +pub type ReR = crate::BitReader; +#[doc = "Field `RE` writer - Enable RMAP command handler"] +pub type ReW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RD` reader - If set only one RMAP buffer is used"] +pub type RdR = crate::BitReader; +#[doc = "Field `RD` writer - If set only one RMAP buffer is used"] +pub type RdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PNPA` reader - SpW Plug-and-Play Available"] +pub type PnpaR = crate::FieldReader; +#[doc = "Field `NP` reader - Disable port force"] +pub type NpR = crate::BitReader; +#[doc = "Field `NP` writer - Disable port force"] +pub type NpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PS` reader - Selects the active port when the no port force bit is zero"] +pub type PsR = crate::BitReader; +#[doc = "Field `PS` writer - Selects the active port when the no port force bit is zero"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LE` reader - Loop-back Enable"] +pub type LeR = crate::BitReader; +#[doc = "Field `LE` writer - Loop-back Enable"] +pub type LeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ID` reader - Interrupt distribution available"] +pub type IdR = crate::BitReader; +#[doc = "Field `CC` reader - CCSDS/CCITT CRC-16"] +pub type CcR = crate::BitReader; +#[doc = "Field `PO` reader - The number of available SpaceWire ports minus one"] +pub type PoR = crate::BitReader; +#[doc = "Field `NCH` reader - Number of DMA Channels minus one"] +pub type NchR = crate::FieldReader; +#[doc = "Field `RC` reader - Reads as 1 if RMAP CRC is enabled in the core"] +pub type RcR = crate::BitReader; +#[doc = "Field `RX` reader - Reads as 1 if unaligned writes are available for the receiver"] +pub type RxR = crate::BitReader; +#[doc = "Field `RA` reader - Reads as 1 if the RMAP command handler is available"] +pub type RaR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Disable the SpaceWire CODEC"] + #[inline(always)] + pub fn ld(&self) -> LdR { + LdR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Start the link"] + #[inline(always)] + pub fn ls(&self) -> LsR { + LsR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Automatically start the link when a NULL has been received"] + #[inline(always)] + pub fn as_(&self) -> AsR { + AsR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] + #[inline(always)] + pub fn ie(&self) -> IeR { + IeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The host can generate a tick by writing a one to this field"] + #[inline(always)] + pub fn ti(&self) -> TiR { + TiR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable Promiscuous mode"] + #[inline(always)] + pub fn pm(&self) -> PmR { + PmR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Make complete reset of the SpaceWire node. Self-clearing"] + #[inline(always)] + pub fn rs(&self) -> RsR { + RsR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Generate interrupt when a valid time-code is received"] + #[inline(always)] + pub fn tq(&self) -> TqR { + TqR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Generate interrupt when link error occurs"] + #[inline(always)] + pub fn li(&self) -> LiR { + LiR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable time-code transmissions"] + #[inline(always)] + pub fn tt(&self) -> TtR { + TtR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable time-code receptions"] + #[inline(always)] + pub fn tr(&self) -> TrR { + TrR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Time-code Flag Filter"] + #[inline(always)] + pub fn tf(&self) -> TfR { + TfR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Transmitter Enable Lock Control"] + #[inline(always)] + pub fn tl(&self) -> TlR { + TlR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - SpW Plug-and-Play Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Enable RMAP command handler"] + #[inline(always)] + pub fn re(&self) -> ReR { + ReR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - If set only one RMAP buffer is used"] + #[inline(always)] + pub fn rd(&self) -> RdR { + RdR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - SpW Plug-and-Play Available"] + #[inline(always)] + pub fn pnpa(&self) -> PnpaR { + PnpaR::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 20 - Disable port force"] + #[inline(always)] + pub fn np(&self) -> NpR { + NpR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Selects the active port when the no port force bit is zero"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Loop-back Enable"] + #[inline(always)] + pub fn le(&self) -> LeR { + LeR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt distribution available"] + #[inline(always)] + pub fn id(&self) -> IdR { + IdR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - CCSDS/CCITT CRC-16"] + #[inline(always)] + pub fn cc(&self) -> CcR { + CcR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - The number of available SpaceWire ports minus one"] + #[inline(always)] + pub fn po(&self) -> PoR { + PoR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bits 27:28 - Number of DMA Channels minus one"] + #[inline(always)] + pub fn nch(&self) -> NchR { + NchR::new(((self.bits >> 27) & 3) as u8) + } + #[doc = "Bit 29 - Reads as 1 if RMAP CRC is enabled in the core"] + #[inline(always)] + pub fn rc(&self) -> RcR { + RcR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reads as 1 if unaligned writes are available for the receiver"] + #[inline(always)] + pub fn rx(&self) -> RxR { + RxR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reads as 1 if the RMAP command handler is available"] + #[inline(always)] + pub fn ra(&self) -> RaR { + RaR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Disable the SpaceWire CODEC"] + #[inline(always)] + pub fn ld(&mut self) -> LdW<'_, CtrlSpec> { + LdW::new(self, 0) + } + #[doc = "Bit 1 - Start the link"] + #[inline(always)] + pub fn ls(&mut self) -> LsW<'_, CtrlSpec> { + LsW::new(self, 1) + } + #[doc = "Bit 2 - Automatically start the link when a NULL has been received"] + #[inline(always)] + pub fn as_(&mut self) -> AsW<'_, CtrlSpec> { + AsW::new(self, 2) + } + #[doc = "Bit 3 - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] + #[inline(always)] + pub fn ie(&mut self) -> IeW<'_, CtrlSpec> { + IeW::new(self, 3) + } + #[doc = "Bit 4 - The host can generate a tick by writing a one to this field"] + #[inline(always)] + pub fn ti(&mut self) -> TiW<'_, CtrlSpec> { + TiW::new(self, 4) + } + #[doc = "Bit 5 - Enable Promiscuous mode"] + #[inline(always)] + pub fn pm(&mut self) -> PmW<'_, CtrlSpec> { + PmW::new(self, 5) + } + #[doc = "Bit 6 - Make complete reset of the SpaceWire node. Self-clearing"] + #[inline(always)] + pub fn rs(&mut self) -> RsW<'_, CtrlSpec> { + RsW::new(self, 6) + } + #[doc = "Bit 8 - Generate interrupt when a valid time-code is received"] + #[inline(always)] + pub fn tq(&mut self) -> TqW<'_, CtrlSpec> { + TqW::new(self, 8) + } + #[doc = "Bit 9 - Generate interrupt when link error occurs"] + #[inline(always)] + pub fn li(&mut self) -> LiW<'_, CtrlSpec> { + LiW::new(self, 9) + } + #[doc = "Bit 10 - Enable time-code transmissions"] + #[inline(always)] + pub fn tt(&mut self) -> TtW<'_, CtrlSpec> { + TtW::new(self, 10) + } + #[doc = "Bit 11 - Enable time-code receptions"] + #[inline(always)] + pub fn tr(&mut self) -> TrW<'_, CtrlSpec> { + TrW::new(self, 11) + } + #[doc = "Bit 12 - Time-code Flag Filter"] + #[inline(always)] + pub fn tf(&mut self) -> TfW<'_, CtrlSpec> { + TfW::new(self, 12) + } + #[doc = "Bit 13 - Transmitter Enable Lock Control"] + #[inline(always)] + pub fn tl(&mut self) -> TlW<'_, CtrlSpec> { + TlW::new(self, 13) + } + #[doc = "Bit 15 - SpW Plug-and-Play Enable"] + #[inline(always)] + pub fn pe(&mut self) -> PeW<'_, CtrlSpec> { + PeW::new(self, 15) + } + #[doc = "Bit 16 - Enable RMAP command handler"] + #[inline(always)] + pub fn re(&mut self) -> ReW<'_, CtrlSpec> { + ReW::new(self, 16) + } + #[doc = "Bit 17 - If set only one RMAP buffer is used"] + #[inline(always)] + pub fn rd(&mut self) -> RdW<'_, CtrlSpec> { + RdW::new(self, 17) + } + #[doc = "Bit 20 - Disable port force"] + #[inline(always)] + pub fn np(&mut self) -> NpW<'_, CtrlSpec> { + NpW::new(self, 20) + } + #[doc = "Bit 21 - Selects the active port when the no port force bit is zero"] + #[inline(always)] + pub fn ps(&mut self) -> PsW<'_, CtrlSpec> { + PsW::new(self, 21) + } + #[doc = "Bit 22 - Loop-back Enable"] + #[inline(always)] + pub fn le(&mut self) -> LeW<'_, CtrlSpec> { + LeW::new(self, 22) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0xa201_0004"] +impl crate::Resettable for CtrlSpec { + const RESET_VALUE: u32 = 0xa201_0004; +} diff --git a/va416xx/va416xx/src/spw/defaddr.rs b/va416xx/va416xx/src/spw/defaddr.rs new file mode 100644 index 0000000..414c6d6 --- /dev/null +++ b/va416xx/va416xx/src/spw/defaddr.rs @@ -0,0 +1,51 @@ +#[doc = "Register `DEFADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DEFADDR` writer"] +pub type W = crate::W; +#[doc = "Field `DEFADDR` reader - 8-bit node address used for node identification on the SpaceWire network"] +pub type DefaddrR = crate::FieldReader; +#[doc = "Field `DEFADDR` writer - 8-bit node address used for node identification on the SpaceWire network"] +pub type DefaddrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DEFMASK` reader - 8-bit default mask used for node identification on the SpaceWire network"] +pub type DefmaskR = crate::FieldReader; +#[doc = "Field `DEFMASK` writer - 8-bit default mask used for node identification on the SpaceWire network"] +pub type DefmaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - 8-bit node address used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defaddr(&self) -> DefaddrR { + DefaddrR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - 8-bit default mask used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defmask(&self) -> DefmaskR { + DefmaskR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - 8-bit node address used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defaddr(&mut self) -> DefaddrW<'_, DefaddrSpec> { + DefaddrW::new(self, 0) + } + #[doc = "Bits 8:15 - 8-bit default mask used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defmask(&mut self) -> DefmaskW<'_, DefaddrSpec> { + DefmaskW::new(self, 8) + } +} +#[doc = "Node Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`defaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`defaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DefaddrSpec; +impl crate::RegisterSpec for DefaddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`defaddr::R`](R) reader structure"] +impl crate::Readable for DefaddrSpec {} +#[doc = "`write(|w| ..)` method takes [`defaddr::W`](W) writer structure"] +impl crate::Writable for DefaddrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DEFADDR to value 0xfe"] +impl crate::Resettable for DefaddrSpec { + const RESET_VALUE: u32 = 0xfe; +} diff --git a/va416xx/va416xx/src/spw/dkey.rs b/va416xx/va416xx/src/spw/dkey.rs new file mode 100644 index 0000000..692a17c --- /dev/null +++ b/va416xx/va416xx/src/spw/dkey.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DKEY` reader"] +pub type R = crate::R; +#[doc = "Register `DKEY` writer"] +pub type W = crate::W; +#[doc = "Field `DESTKEY` reader - RMAP destination key"] +pub type DestkeyR = crate::FieldReader; +#[doc = "Field `DESTKEY` writer - RMAP destination key"] +pub type DestkeyW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - RMAP destination key"] + #[inline(always)] + pub fn destkey(&self) -> DestkeyR { + DestkeyR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - RMAP destination key"] + #[inline(always)] + pub fn destkey(&mut self) -> DestkeyW<'_, DkeySpec> { + DestkeyW::new(self, 0) + } +} +#[doc = "Destination Key\n\nYou can [`read`](crate::Reg::read) this register and get [`dkey::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dkey::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DkeySpec; +impl crate::RegisterSpec for DkeySpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dkey::R`](R) reader structure"] +impl crate::Readable for DkeySpec {} +#[doc = "`write(|w| ..)` method takes [`dkey::W`](W) writer structure"] +impl crate::Writable for DkeySpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DKEY to value 0"] +impl crate::Resettable for DkeySpec {} diff --git a/va416xx/va416xx/src/spw/dmaaddr0.rs b/va416xx/va416xx/src/spw/dmaaddr0.rs new file mode 100644 index 0000000..9d31ded --- /dev/null +++ b/va416xx/va416xx/src/spw/dmaaddr0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DMAADDR0` reader"] +pub type R = crate::R; +#[doc = "Register `DMAADDR0` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - Address"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `MASK` reader - Mask"] +pub type MaskR = crate::FieldReader; +#[doc = "Field `MASK` writer - Mask"] +pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Address"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Mask"] + #[inline(always)] + pub fn mask(&self) -> MaskR { + MaskR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address"] + #[inline(always)] + pub fn addr(&mut self) -> AddrW<'_, Dmaaddr0Spec> { + AddrW::new(self, 0) + } + #[doc = "Bits 8:15 - Mask"] + #[inline(always)] + pub fn mask(&mut self) -> MaskW<'_, Dmaaddr0Spec> { + MaskW::new(self, 8) + } +} +#[doc = "DMA Receiver Table Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmaaddr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmaaddr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmaaddr0Spec; +impl crate::RegisterSpec for Dmaaddr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmaaddr0::R`](R) reader structure"] +impl crate::Readable for Dmaaddr0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmaaddr0::W`](W) writer structure"] +impl crate::Writable for Dmaaddr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMAADDR0 to value 0"] +impl crate::Resettable for Dmaaddr0Spec {} diff --git a/va416xx/va416xx/src/spw/dmactrl0.rs b/va416xx/va416xx/src/spw/dmactrl0.rs new file mode 100644 index 0000000..1384f72 --- /dev/null +++ b/va416xx/va416xx/src/spw/dmactrl0.rs @@ -0,0 +1,357 @@ +#[doc = "Register `DMACTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `DMACTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `TE` reader - Write a one to this bit each time new descriptors are activated in the table"] +pub type TeR = crate::BitReader; +#[doc = "Field `TE` writer - Write a one to this bit each time new descriptors are activated in the table"] +pub type TeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RE` reader - Packets are allowed to be received to this channel"] +pub type ReR = crate::BitReader; +#[doc = "Field `RE` writer - Packets are allowed to be received to this channel"] +pub type ReW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TI` reader - An interrupt will be generated each time a packet is transmitted"] +pub type TiR = crate::BitReader; +#[doc = "Field `TI` writer - An interrupt will be generated each time a packet is transmitted"] +pub type TiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RI` reader - An interrupt will be generated each time a packet has been received"] +pub type RiR = crate::BitReader; +#[doc = "Field `RI` writer - An interrupt will be generated each time a packet has been received"] +pub type RiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AI` reader - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] +pub type AiR = crate::BitReader; +#[doc = "Field `AI` writer - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] +pub type AiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PS` reader - Set each time a packet has been sent"] +pub type PsR = crate::BitReader; +#[doc = "Field `PS` writer - Set each time a packet has been sent"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PR` reader - Set each time a packet has been received"] +pub type PrR = crate::BitReader; +#[doc = "Field `PR` writer - Set each time a packet has been received"] +pub type PrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TA` reader - An error response was detected on the AHB bus - DMA transmit"] +pub type TaR = crate::BitReader; +#[doc = "Field `TA` writer - An error response was detected on the AHB bus - DMA transmit"] +pub type TaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RA` reader - An error response was detected on the AHB bus - DMA receive"] +pub type RaR = crate::BitReader; +#[doc = "Field `RA` writer - An error response was detected on the AHB bus - DMA receive"] +pub type RaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT` reader - Abort the currently transmitting packet and disable transmissions"] +pub type AtR = crate::BitReader; +#[doc = "Field `RX` reader - Reception to the DMA channel is currently active"] +pub type RxR = crate::BitReader; +#[doc = "Field `RD` reader - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] +pub type RdR = crate::BitReader; +#[doc = "Field `RD` writer - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] +pub type RdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NS` reader - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] +pub type NsR = crate::BitReader; +#[doc = "Field `NS` writer - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] +pub type NsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - Enable Address"] +pub type EnR = crate::BitReader; +#[doc = "Field `EN` writer - Enable Address"] +pub type EnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SA` reader - Strip Address"] +pub type SaR = crate::BitReader; +#[doc = "Field `SA` writer - Strip Address"] +pub type SaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - Strip PID"] +pub type SpR = crate::BitReader; +#[doc = "Field `SP` writer - Strip PID"] +pub type SpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LE` reader - Disable transmitter when a link error occurs"] +pub type LeR = crate::BitReader; +#[doc = "Field `LE` writer - Disable transmitter when a link error occurs"] +pub type LeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TL` reader - Transmit Enable Lock"] +pub type TlR = crate::BitReader; +#[doc = "Field `TL` writer - Transmit Enable Lock"] +pub type TlW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TP` reader - Transmit Packet IRQ"] +pub type TpR = crate::BitReader; +#[doc = "Field `TP` writer - Transmit Packet IRQ"] +pub type TpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RP` reader - Receive Packet IRQ"] +pub type RpR = crate::BitReader; +#[doc = "Field `RP` writer - Receive Packet IRQ"] +pub type RpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IT` reader - Interrupt code transmit enable on truncation"] +pub type ItR = crate::BitReader; +#[doc = "Field `IT` writer - Interrupt code transmit enable on truncation"] +pub type ItW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IE` reader - Interrupt code transmit enable on EEP"] +pub type IeR = crate::BitReader; +#[doc = "Field `IE` writer - Interrupt code transmit enable on EEP"] +pub type IeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TR` reader - Truncated"] +pub type TrR = crate::BitReader; +#[doc = "Field `TR` writer - Truncated"] +pub type TrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP` reader - EEP Termination"] +pub type EpR = crate::BitReader; +#[doc = "Field `EP` writer - EEP Termination"] +pub type EpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTNUM` reader - Interrupt number used for this channel"] +pub type IntnumR = crate::FieldReader; +#[doc = "Field `INTNUM` writer - Interrupt number used for this channel"] +pub type IntnumW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Write a one to this bit each time new descriptors are activated in the table"] + #[inline(always)] + pub fn te(&self) -> TeR { + TeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Packets are allowed to be received to this channel"] + #[inline(always)] + pub fn re(&self) -> ReR { + ReR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - An interrupt will be generated each time a packet is transmitted"] + #[inline(always)] + pub fn ti(&self) -> TiR { + TiR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - An interrupt will be generated each time a packet has been received"] + #[inline(always)] + pub fn ri(&self) -> RiR { + RiR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] + #[inline(always)] + pub fn ai(&self) -> AiR { + AiR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set each time a packet has been sent"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set each time a packet has been received"] + #[inline(always)] + pub fn pr(&self) -> PrR { + PrR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - An error response was detected on the AHB bus - DMA transmit"] + #[inline(always)] + pub fn ta(&self) -> TaR { + TaR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - An error response was detected on the AHB bus - DMA receive"] + #[inline(always)] + pub fn ra(&self) -> RaR { + RaR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Abort the currently transmitting packet and disable transmissions"] + #[inline(always)] + pub fn at(&self) -> AtR { + AtR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reception to the DMA channel is currently active"] + #[inline(always)] + pub fn rx(&self) -> RxR { + RxR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] + #[inline(always)] + pub fn rd(&self) -> RdR { + RdR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] + #[inline(always)] + pub fn ns(&self) -> NsR { + NsR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable Address"] + #[inline(always)] + pub fn en(&self) -> EnR { + EnR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Strip Address"] + #[inline(always)] + pub fn sa(&self) -> SaR { + SaR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Strip PID"] + #[inline(always)] + pub fn sp(&self) -> SpR { + SpR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Disable transmitter when a link error occurs"] + #[inline(always)] + pub fn le(&self) -> LeR { + LeR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Transmit Enable Lock"] + #[inline(always)] + pub fn tl(&self) -> TlR { + TlR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Transmit Packet IRQ"] + #[inline(always)] + pub fn tp(&self) -> TpR { + TpR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Receive Packet IRQ"] + #[inline(always)] + pub fn rp(&self) -> RpR { + RpR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt code transmit enable on truncation"] + #[inline(always)] + pub fn it(&self) -> ItR { + ItR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt code transmit enable on EEP"] + #[inline(always)] + pub fn ie(&self) -> IeR { + IeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Truncated"] + #[inline(always)] + pub fn tr(&self) -> TrR { + TrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - EEP Termination"] + #[inline(always)] + pub fn ep(&self) -> EpR { + EpR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 26:31 - Interrupt number used for this channel"] + #[inline(always)] + pub fn intnum(&self) -> IntnumR { + IntnumR::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Write a one to this bit each time new descriptors are activated in the table"] + #[inline(always)] + pub fn te(&mut self) -> TeW<'_, Dmactrl0Spec> { + TeW::new(self, 0) + } + #[doc = "Bit 1 - Packets are allowed to be received to this channel"] + #[inline(always)] + pub fn re(&mut self) -> ReW<'_, Dmactrl0Spec> { + ReW::new(self, 1) + } + #[doc = "Bit 2 - An interrupt will be generated each time a packet is transmitted"] + #[inline(always)] + pub fn ti(&mut self) -> TiW<'_, Dmactrl0Spec> { + TiW::new(self, 2) + } + #[doc = "Bit 3 - An interrupt will be generated each time a packet has been received"] + #[inline(always)] + pub fn ri(&mut self) -> RiW<'_, Dmactrl0Spec> { + RiW::new(self, 3) + } + #[doc = "Bit 4 - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] + #[inline(always)] + pub fn ai(&mut self) -> AiW<'_, Dmactrl0Spec> { + AiW::new(self, 4) + } + #[doc = "Bit 5 - Set each time a packet has been sent"] + #[inline(always)] + pub fn ps(&mut self) -> PsW<'_, Dmactrl0Spec> { + PsW::new(self, 5) + } + #[doc = "Bit 6 - Set each time a packet has been received"] + #[inline(always)] + pub fn pr(&mut self) -> PrW<'_, Dmactrl0Spec> { + PrW::new(self, 6) + } + #[doc = "Bit 7 - An error response was detected on the AHB bus - DMA transmit"] + #[inline(always)] + pub fn ta(&mut self) -> TaW<'_, Dmactrl0Spec> { + TaW::new(self, 7) + } + #[doc = "Bit 8 - An error response was detected on the AHB bus - DMA receive"] + #[inline(always)] + pub fn ra(&mut self) -> RaW<'_, Dmactrl0Spec> { + RaW::new(self, 8) + } + #[doc = "Bit 11 - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] + #[inline(always)] + pub fn rd(&mut self) -> RdW<'_, Dmactrl0Spec> { + RdW::new(self, 11) + } + #[doc = "Bit 12 - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] + #[inline(always)] + pub fn ns(&mut self) -> NsW<'_, Dmactrl0Spec> { + NsW::new(self, 12) + } + #[doc = "Bit 13 - Enable Address"] + #[inline(always)] + pub fn en(&mut self) -> EnW<'_, Dmactrl0Spec> { + EnW::new(self, 13) + } + #[doc = "Bit 14 - Strip Address"] + #[inline(always)] + pub fn sa(&mut self) -> SaW<'_, Dmactrl0Spec> { + SaW::new(self, 14) + } + #[doc = "Bit 15 - Strip PID"] + #[inline(always)] + pub fn sp(&mut self) -> SpW<'_, Dmactrl0Spec> { + SpW::new(self, 15) + } + #[doc = "Bit 16 - Disable transmitter when a link error occurs"] + #[inline(always)] + pub fn le(&mut self) -> LeW<'_, Dmactrl0Spec> { + LeW::new(self, 16) + } + #[doc = "Bit 17 - Transmit Enable Lock"] + #[inline(always)] + pub fn tl(&mut self) -> TlW<'_, Dmactrl0Spec> { + TlW::new(self, 17) + } + #[doc = "Bit 18 - Transmit Packet IRQ"] + #[inline(always)] + pub fn tp(&mut self) -> TpW<'_, Dmactrl0Spec> { + TpW::new(self, 18) + } + #[doc = "Bit 19 - Receive Packet IRQ"] + #[inline(always)] + pub fn rp(&mut self) -> RpW<'_, Dmactrl0Spec> { + RpW::new(self, 19) + } + #[doc = "Bit 20 - Interrupt code transmit enable on truncation"] + #[inline(always)] + pub fn it(&mut self) -> ItW<'_, Dmactrl0Spec> { + ItW::new(self, 20) + } + #[doc = "Bit 21 - Interrupt code transmit enable on EEP"] + #[inline(always)] + pub fn ie(&mut self) -> IeW<'_, Dmactrl0Spec> { + IeW::new(self, 21) + } + #[doc = "Bit 22 - Truncated"] + #[inline(always)] + pub fn tr(&mut self) -> TrW<'_, Dmactrl0Spec> { + TrW::new(self, 22) + } + #[doc = "Bit 23 - EEP Termination"] + #[inline(always)] + pub fn ep(&mut self) -> EpW<'_, Dmactrl0Spec> { + EpW::new(self, 23) + } + #[doc = "Bits 26:31 - Interrupt number used for this channel"] + #[inline(always)] + pub fn intnum(&mut self) -> IntnumW<'_, Dmactrl0Spec> { + IntnumW::new(self, 26) + } +} +#[doc = "DMA Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmactrl0Spec; +impl crate::RegisterSpec for Dmactrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmactrl0::R`](R) reader structure"] +impl crate::Readable for Dmactrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmactrl0::W`](W) writer structure"] +impl crate::Writable for Dmactrl0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMACTRL0 to value 0"] +impl crate::Resettable for Dmactrl0Spec {} diff --git a/va416xx/va416xx/src/spw/dmamaxlen0.rs b/va416xx/va416xx/src/spw/dmamaxlen0.rs new file mode 100644 index 0000000..438d2c0 --- /dev/null +++ b/va416xx/va416xx/src/spw/dmamaxlen0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DMAMAXLEN0` reader"] +pub type R = crate::R; +#[doc = "Register `DMAMAXLEN0` writer"] +pub type W = crate::W; +#[doc = "Field `RXMAXLEN` reader - Receiver packet maximum length in bytes"] +pub type RxmaxlenR = crate::FieldReader; +#[doc = "Field `RXMAXLEN` writer - Receiver packet maximum length in bytes"] +pub type RxmaxlenW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>; +impl R { + #[doc = "Bits 2:24 - Receiver packet maximum length in bytes"] + #[inline(always)] + pub fn rxmaxlen(&self) -> RxmaxlenR { + RxmaxlenR::new((self.bits >> 2) & 0x007f_ffff) + } +} +impl W { + #[doc = "Bits 2:24 - Receiver packet maximum length in bytes"] + #[inline(always)] + pub fn rxmaxlen(&mut self) -> RxmaxlenW<'_, Dmamaxlen0Spec> { + RxmaxlenW::new(self, 2) + } +} +#[doc = "DMA RX Maximum Length Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmamaxlen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmamaxlen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmamaxlen0Spec; +impl crate::RegisterSpec for Dmamaxlen0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmamaxlen0::R`](R) reader structure"] +impl crate::Readable for Dmamaxlen0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmamaxlen0::W`](W) writer structure"] +impl crate::Writable for Dmamaxlen0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMAMAXLEN0 to value 0"] +impl crate::Resettable for Dmamaxlen0Spec {} diff --git a/va416xx/va416xx/src/spw/dmarxdesc0.rs b/va416xx/va416xx/src/spw/dmarxdesc0.rs new file mode 100644 index 0000000..e28e8f5 --- /dev/null +++ b/va416xx/va416xx/src/spw/dmarxdesc0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DMARXDESC0` reader"] +pub type R = crate::R; +#[doc = "Register `DMARXDESC0` writer"] +pub type W = crate::W; +#[doc = "Field `DESCSEL` reader - Offset into the descriptor table"] +pub type DescselR = crate::FieldReader; +#[doc = "Field `DESCSEL` writer - Offset into the descriptor table"] +pub type DescselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `DESCBASEADDR` reader - Sets the base address of the descriptor table"] +pub type DescbaseaddrR = crate::FieldReader; +#[doc = "Field `DESCBASEADDR` writer - Sets the base address of the descriptor table"] +pub type DescbaseaddrW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 3:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&self) -> DescselR { + DescselR::new(((self.bits >> 3) & 0x7f) as u8) + } + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&self) -> DescbaseaddrR { + DescbaseaddrR::new((self.bits >> 10) & 0x003f_ffff) + } +} +impl W { + #[doc = "Bits 3:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&mut self) -> DescselW<'_, Dmarxdesc0Spec> { + DescselW::new(self, 3) + } + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&mut self) -> DescbaseaddrW<'_, Dmarxdesc0Spec> { + DescbaseaddrW::new(self, 10) + } +} +#[doc = "DMA Receiver Table Destination Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmarxdesc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmarxdesc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmarxdesc0Spec; +impl crate::RegisterSpec for Dmarxdesc0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmarxdesc0::R`](R) reader structure"] +impl crate::Readable for Dmarxdesc0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmarxdesc0::W`](W) writer structure"] +impl crate::Writable for Dmarxdesc0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMARXDESC0 to value 0"] +impl crate::Resettable for Dmarxdesc0Spec {} diff --git a/va416xx/va416xx/src/spw/dmatxdesc0.rs b/va416xx/va416xx/src/spw/dmatxdesc0.rs new file mode 100644 index 0000000..5496552 --- /dev/null +++ b/va416xx/va416xx/src/spw/dmatxdesc0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `DMATXDESC0` reader"] +pub type R = crate::R; +#[doc = "Register `DMATXDESC0` writer"] +pub type W = crate::W; +#[doc = "Field `DESCSEL` reader - Offset into the descriptor table"] +pub type DescselR = crate::FieldReader; +#[doc = "Field `DESCSEL` writer - Offset into the descriptor table"] +pub type DescselW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DESCBASEADDR` reader - Sets the base address of the descriptor table"] +pub type DescbaseaddrR = crate::FieldReader; +#[doc = "Field `DESCBASEADDR` writer - Sets the base address of the descriptor table"] +pub type DescbaseaddrW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 4:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&self) -> DescselR { + DescselR::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&self) -> DescbaseaddrR { + DescbaseaddrR::new((self.bits >> 10) & 0x003f_ffff) + } +} +impl W { + #[doc = "Bits 4:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&mut self) -> DescselW<'_, Dmatxdesc0Spec> { + DescselW::new(self, 4) + } + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&mut self) -> DescbaseaddrW<'_, Dmatxdesc0Spec> { + DescbaseaddrW::new(self, 10) + } +} +#[doc = "DMA Transmitter Descriptor Table Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmatxdesc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmatxdesc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmatxdesc0Spec; +impl crate::RegisterSpec for Dmatxdesc0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmatxdesc0::R`](R) reader structure"] +impl crate::Readable for Dmatxdesc0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmatxdesc0::W`](W) writer structure"] +impl crate::Writable for Dmatxdesc0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DMATXDESC0 to value 0"] +impl crate::Resettable for Dmatxdesc0Spec {} diff --git a/va416xx/va416xx/src/spw/sts.rs b/va416xx/va416xx/src/spw/sts.rs new file mode 100644 index 0000000..f6b5f13 --- /dev/null +++ b/va416xx/va416xx/src/spw/sts.rs @@ -0,0 +1,191 @@ +#[doc = "Register `STS` reader"] +pub type R = crate::R; +#[doc = "Register `STS` writer"] +pub type W = crate::W; +#[doc = "Field `TO` reader - A new time count value was received"] +pub type ToR = crate::BitReader; +#[doc = "Field `TO` writer - A new time count value was received"] +pub type ToW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CE` reader - Credit has occurred"] +pub type CeR = crate::BitReader; +#[doc = "Field `CE` writer - Credit has occurred"] +pub type CeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ER` reader - Escape error has occurred"] +pub type ErR = crate::BitReader; +#[doc = "Field `ER` writer - Escape error has occurred"] +pub type ErW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE` reader - Disconnection error has occurred"] +pub type DeR = crate::BitReader; +#[doc = "Field `DE` writer - Disconnection error has occurred"] +pub type DeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PE` reader - Parity error has occurred"] +pub type PeR = crate::BitReader; +#[doc = "Field `PE` writer - Parity error has occurred"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WE` reader - A synchronization problem has occurred when receiving NChars"] +pub type WeR = crate::BitReader; +#[doc = "Field `WE` writer - A synchronization problem has occurred when receiving NChars"] +pub type WeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IA` reader - Packet is received with an invalid destination address field"] +pub type IaR = crate::BitReader; +#[doc = "Field `IA` writer - Packet is received with an invalid destination address field"] +pub type IaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EE` reader - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] +pub type EeR = crate::BitReader; +#[doc = "Field `EE` writer - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] +pub type EeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AP` reader - Active port"] +pub type ApR = crate::BitReader; +#[doc = "Field `AP` writer - Active port"] +pub type ApW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LS` reader - Link State"] +pub type LsR = crate::FieldReader; +#[doc = "Field `LS` writer - Link State"] +pub type LsW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `NTXD` reader - Number of Transmit Descriptors"] +pub type NtxdR = crate::FieldReader; +#[doc = "Field `NTXD` writer - Number of Transmit Descriptors"] +pub type NtxdW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `NRXD` reader - Number of Receive Descriptors"] +pub type NrxdR = crate::FieldReader; +#[doc = "Field `NRXD` writer - Number of Receive Descriptors"] +pub type NrxdW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - A new time count value was received"] + #[inline(always)] + pub fn to(&self) -> ToR { + ToR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Credit has occurred"] + #[inline(always)] + pub fn ce(&self) -> CeR { + CeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Escape error has occurred"] + #[inline(always)] + pub fn er(&self) -> ErR { + ErR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Disconnection error has occurred"] + #[inline(always)] + pub fn de(&self) -> DeR { + DeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Parity error has occurred"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - A synchronization problem has occurred when receiving NChars"] + #[inline(always)] + pub fn we(&self) -> WeR { + WeR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Packet is received with an invalid destination address field"] + #[inline(always)] + pub fn ia(&self) -> IaR { + IaR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] + #[inline(always)] + pub fn ee(&self) -> EeR { + EeR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Active port"] + #[inline(always)] + pub fn ap(&self) -> ApR { + ApR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 21:23 - Link State"] + #[inline(always)] + pub fn ls(&self) -> LsR { + LsR::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:25 - Number of Transmit Descriptors"] + #[inline(always)] + pub fn ntxd(&self) -> NtxdR { + NtxdR::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Number of Receive Descriptors"] + #[inline(always)] + pub fn nrxd(&self) -> NrxdR { + NrxdR::new(((self.bits >> 26) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - A new time count value was received"] + #[inline(always)] + pub fn to(&mut self) -> ToW<'_, StsSpec> { + ToW::new(self, 0) + } + #[doc = "Bit 1 - Credit has occurred"] + #[inline(always)] + pub fn ce(&mut self) -> CeW<'_, StsSpec> { + CeW::new(self, 1) + } + #[doc = "Bit 2 - Escape error has occurred"] + #[inline(always)] + pub fn er(&mut self) -> ErW<'_, StsSpec> { + ErW::new(self, 2) + } + #[doc = "Bit 3 - Disconnection error has occurred"] + #[inline(always)] + pub fn de(&mut self) -> DeW<'_, StsSpec> { + DeW::new(self, 3) + } + #[doc = "Bit 4 - Parity error has occurred"] + #[inline(always)] + pub fn pe(&mut self) -> PeW<'_, StsSpec> { + PeW::new(self, 4) + } + #[doc = "Bit 6 - A synchronization problem has occurred when receiving NChars"] + #[inline(always)] + pub fn we(&mut self) -> WeW<'_, StsSpec> { + WeW::new(self, 6) + } + #[doc = "Bit 7 - Packet is received with an invalid destination address field"] + #[inline(always)] + pub fn ia(&mut self) -> IaW<'_, StsSpec> { + IaW::new(self, 7) + } + #[doc = "Bit 8 - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] + #[inline(always)] + pub fn ee(&mut self) -> EeW<'_, StsSpec> { + EeW::new(self, 8) + } + #[doc = "Bit 9 - Active port"] + #[inline(always)] + pub fn ap(&mut self) -> ApW<'_, StsSpec> { + ApW::new(self, 9) + } + #[doc = "Bits 21:23 - Link State"] + #[inline(always)] + pub fn ls(&mut self) -> LsW<'_, StsSpec> { + LsW::new(self, 21) + } + #[doc = "Bits 24:25 - Number of Transmit Descriptors"] + #[inline(always)] + pub fn ntxd(&mut self) -> NtxdW<'_, StsSpec> { + NtxdW::new(self, 24) + } + #[doc = "Bits 26:27 - Number of Receive Descriptors"] + #[inline(always)] + pub fn nrxd(&mut self) -> NrxdW<'_, StsSpec> { + NrxdW::new(self, 26) + } +} +#[doc = "Status/Interrupt Source Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StsSpec; +impl crate::RegisterSpec for StsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sts::R`](R) reader structure"] +impl crate::Readable for StsSpec {} +#[doc = "`write(|w| ..)` method takes [`sts::W`](W) writer structure"] +impl crate::Writable for StsSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets STS to value 0x0640_0000"] +impl crate::Resettable for StsSpec { + const RESET_VALUE: u32 = 0x0640_0000; +} diff --git a/va416xx/va416xx/src/spw/tc.rs b/va416xx/va416xx/src/spw/tc.rs new file mode 100644 index 0000000..0f1d9ad --- /dev/null +++ b/va416xx/va416xx/src/spw/tc.rs @@ -0,0 +1,49 @@ +#[doc = "Register `TC` reader"] +pub type R = crate::R; +#[doc = "Register `TC` writer"] +pub type W = crate::W; +#[doc = "Field `TIMECNT` reader - The current value of the system time counter"] +pub type TimecntR = crate::FieldReader; +#[doc = "Field `TIMECNT` writer - The current value of the system time counter"] +pub type TimecntW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `TIRQ_END` reader - The current value of the time control flags"] +pub type TirqEndR = crate::FieldReader; +#[doc = "Field `TIRQ_END` writer - The current value of the time control flags"] +pub type TirqEndW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:5 - The current value of the system time counter"] + #[inline(always)] + pub fn timecnt(&self) -> TimecntR { + TimecntR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:7 - The current value of the time control flags"] + #[inline(always)] + pub fn tirq_end(&self) -> TirqEndR { + TirqEndR::new(((self.bits >> 6) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - The current value of the system time counter"] + #[inline(always)] + pub fn timecnt(&mut self) -> TimecntW<'_, TcSpec> { + TimecntW::new(self, 0) + } + #[doc = "Bits 6:7 - The current value of the time control flags"] + #[inline(always)] + pub fn tirq_end(&mut self) -> TirqEndW<'_, TcSpec> { + TirqEndW::new(self, 6) + } +} +#[doc = "Time Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcSpec; +impl crate::RegisterSpec for TcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tc::R`](R) reader structure"] +impl crate::Readable for TcSpec {} +#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"] +impl crate::Writable for TcSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TC to value 0"] +impl crate::Resettable for TcSpec {} diff --git a/va416xx/va416xx/src/spw/tdr.rs b/va416xx/va416xx/src/spw/tdr.rs new file mode 100644 index 0000000..a3f658c --- /dev/null +++ b/va416xx/va416xx/src/spw/tdr.rs @@ -0,0 +1,27 @@ +#[doc = "Register `TDR` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER64` reader - Used to generate the 6.4 and 12.8 us time periods"] +pub type Timer64R = crate::FieldReader; +#[doc = "Field `DISCONNECT` reader - Used to generate the 850 ns disconnect time period"] +pub type DisconnectR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Used to generate the 6.4 and 12.8 us time periods"] + #[inline(always)] + pub fn timer64(&self) -> Timer64R { + Timer64R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:21 - Used to generate the 850 ns disconnect time period"] + #[inline(always)] + pub fn disconnect(&self) -> DisconnectR { + DisconnectR::new(((self.bits >> 12) & 0x03ff) as u16) + } +} +#[doc = "Timer and Disconnect Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TdrSpec; +impl crate::RegisterSpec for TdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tdr::R`](R) reader structure"] +impl crate::Readable for TdrSpec {} +#[doc = "`reset()` method sets TDR to value 0"] +impl crate::Resettable for TdrSpec {} diff --git a/va416xx/va416xx/src/sysconfig.rs b/va416xx/va416xx/src/sysconfig.rs new file mode 100644 index 0000000..44182dd --- /dev/null +++ b/va416xx/va416xx/src/sysconfig.rs @@ -0,0 +1,465 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + rst_stat: RstStat, + rst_cntl_rom: RstCntlRom, + rst_cntl_ram0: RstCntlRam0, + rst_cntl_ram1: RstCntlRam1, + rom_prot: RomProt, + rom_scrub: RomScrub, + ram0_scrub: Ram0Scrub, + ram1_scrub: Ram1Scrub, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + ram0_sbe: Ram0Sbe, + ram1_sbe: Ram1Sbe, + ram0_mbe: Ram0Mbe, + ram1_mbe: Ram1Mbe, + rom_sbe: RomSbe, + rom_mbe: RomMbe, + rom_retries: RomRetries, + refresh_config_h: RefreshConfigH, + tim_reset: TimReset, + tim_clk_enable: TimClkEnable, + peripheral_reset: PeripheralReset, + peripheral_clk_enable: PeripheralClkEnable, + spw_m4_ctrl: SpwM4Ctrl, + pmu_ctrl: PmuCtrl, + wakeup_cnt: WakeupCnt, + ebi_cfg0: EbiCfg0, + ebi_cfg1: EbiCfg1, + ebi_cfg2: EbiCfg2, + ebi_cfg3: EbiCfg3, + analog_cntl: AnalogCntl, + sw_clkdiv10: SwClkdiv10, + refresh_config_l: RefreshConfigL, + _reserved34: [u8; 0x0f48], + dac0_cal: Dac0Cal, + dac1_cal: Dac1Cal, + adc_cal: AdcCal, + bg_cal: BgCal, + dreg_cal: DregCal, + areg_cal: AregCal, + hbo_cal: HboCal, + ef_config: EfConfig, + ef_id0: EfId0, + ef_id1: EfId1, + procid: Procid, + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - System Reset Status"] + #[inline(always)] + pub const fn rst_stat(&self) -> &RstStat { + &self.rst_stat + } + #[doc = "0x04 - ROM Reset Control"] + #[inline(always)] + pub const fn rst_cntl_rom(&self) -> &RstCntlRom { + &self.rst_cntl_rom + } + #[doc = "0x08 - RAM Reset Control"] + #[inline(always)] + pub const fn rst_cntl_ram0(&self) -> &RstCntlRam0 { + &self.rst_cntl_ram0 + } + #[doc = "0x0c - RAM Reset Control"] + #[inline(always)] + pub const fn rst_cntl_ram1(&self) -> &RstCntlRam1 { + &self.rst_cntl_ram1 + } + #[doc = "0x10 - ROM Protection Configuration"] + #[inline(always)] + pub const fn rom_prot(&self) -> &RomProt { + &self.rom_prot + } + #[doc = "0x14 - ROM Scrub Period Configuration"] + #[inline(always)] + pub const fn rom_scrub(&self) -> &RomScrub { + &self.rom_scrub + } + #[doc = "0x18 - RAM0 Scrub Period Configuration"] + #[inline(always)] + pub const fn ram0_scrub(&self) -> &Ram0Scrub { + &self.ram0_scrub + } + #[doc = "0x1c - RAM1 Scrub Period Configuration"] + #[inline(always)] + pub const fn ram1_scrub(&self) -> &Ram1Scrub { + &self.ram1_scrub + } + #[doc = "0x20 - Enable EDAC Error Interrupt Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x24 - Raw EDAC Error Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x28 - Enabled EDAC Error Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x2c - Clear EDAC Error Interrupt Status"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x30 - Count of RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub const fn ram0_sbe(&self) -> &Ram0Sbe { + &self.ram0_sbe + } + #[doc = "0x34 - Count of RAM1 EDAC Single Bit Errors"] + #[inline(always)] + pub const fn ram1_sbe(&self) -> &Ram1Sbe { + &self.ram1_sbe + } + #[doc = "0x38 - Count of RAM0 EDAC Multi Bit Errors"] + #[inline(always)] + pub const fn ram0_mbe(&self) -> &Ram0Mbe { + &self.ram0_mbe + } + #[doc = "0x3c - Count of RAM1 EDAC Multi Bit Errors"] + #[inline(always)] + pub const fn ram1_mbe(&self) -> &Ram1Mbe { + &self.ram1_mbe + } + #[doc = "0x40 - Count of ROM EDAC Single Bit Errors"] + #[inline(always)] + pub const fn rom_sbe(&self) -> &RomSbe { + &self.rom_sbe + } + #[doc = "0x44 - Count of ROM EDAC Multi Bit Errors"] + #[inline(always)] + pub const fn rom_mbe(&self) -> &RomMbe { + &self.rom_mbe + } + #[doc = "0x48 - ROM BOOT Retry count"] + #[inline(always)] + pub const fn rom_retries(&self) -> &RomRetries { + &self.rom_retries + } + #[doc = "0x4c - Register Refresh Rate for TMR registers"] + #[inline(always)] + pub const fn refresh_config_h(&self) -> &RefreshConfigH { + &self.refresh_config_h + } + #[doc = "0x50 - TIM Reset Control"] + #[inline(always)] + pub const fn tim_reset(&self) -> &TimReset { + &self.tim_reset + } + #[doc = "0x54 - TIM Enable Control"] + #[inline(always)] + pub const fn tim_clk_enable(&self) -> &TimClkEnable { + &self.tim_clk_enable + } + #[doc = "0x58 - Peripheral Reset Control"] + #[inline(always)] + pub const fn peripheral_reset(&self) -> &PeripheralReset { + &self.peripheral_reset + } + #[doc = "0x5c - Peripheral Enable Control"] + #[inline(always)] + pub const fn peripheral_clk_enable(&self) -> &PeripheralClkEnable { + &self.peripheral_clk_enable + } + #[doc = "0x60 - SPW M4 control register"] + #[inline(always)] + pub const fn spw_m4_ctrl(&self) -> &SpwM4Ctrl { + &self.spw_m4_ctrl + } + #[doc = "0x64 - PMU Control Register"] + #[inline(always)] + pub const fn pmu_ctrl(&self) -> &PmuCtrl { + &self.pmu_ctrl + } + #[doc = "0x68 - Wakeup Control"] + #[inline(always)] + pub const fn wakeup_cnt(&self) -> &WakeupCnt { + &self.wakeup_cnt + } + #[doc = "0x6c - EBI Config Register 0"] + #[inline(always)] + pub const fn ebi_cfg0(&self) -> &EbiCfg0 { + &self.ebi_cfg0 + } + #[doc = "0x70 - EBI Config Register 1"] + #[inline(always)] + pub const fn ebi_cfg1(&self) -> &EbiCfg1 { + &self.ebi_cfg1 + } + #[doc = "0x74 - EBI Config Register 2"] + #[inline(always)] + pub const fn ebi_cfg2(&self) -> &EbiCfg2 { + &self.ebi_cfg2 + } + #[doc = "0x78 - EBI Config Register 3"] + #[inline(always)] + pub const fn ebi_cfg3(&self) -> &EbiCfg3 { + &self.ebi_cfg3 + } + #[doc = "0x7c - Analog Control Register"] + #[inline(always)] + pub const fn analog_cntl(&self) -> &AnalogCntl { + &self.analog_cntl + } + #[doc = "0x80 - Initial SpW Clock Divider Value"] + #[inline(always)] + pub const fn sw_clkdiv10(&self) -> &SwClkdiv10 { + &self.sw_clkdiv10 + } + #[doc = "0x84 - Register Refresh Rate for TMR registers"] + #[inline(always)] + pub const fn refresh_config_l(&self) -> &RefreshConfigL { + &self.refresh_config_l + } + #[doc = "0xfd0 - DAC0 Calibration Register"] + #[inline(always)] + pub const fn dac0_cal(&self) -> &Dac0Cal { + &self.dac0_cal + } + #[doc = "0xfd4 - DAC1 Calibration Register"] + #[inline(always)] + pub const fn dac1_cal(&self) -> &Dac1Cal { + &self.dac1_cal + } + #[doc = "0xfd8 - ADC Calibration Register"] + #[inline(always)] + pub const fn adc_cal(&self) -> &AdcCal { + &self.adc_cal + } + #[doc = "0xfdc - Bandgap Calibration Register"] + #[inline(always)] + pub const fn bg_cal(&self) -> &BgCal { + &self.bg_cal + } + #[doc = "0xfe0 - Digital LDO Regulator Calibration Register"] + #[inline(always)] + pub const fn dreg_cal(&self) -> &DregCal { + &self.dreg_cal + } + #[doc = "0xfe4 - Analog LDO Regulator Calibration Register"] + #[inline(always)] + pub const fn areg_cal(&self) -> &AregCal { + &self.areg_cal + } + #[doc = "0xfe8 - Heart Beat OSC Calibration Register"] + #[inline(always)] + pub const fn hbo_cal(&self) -> &HboCal { + &self.hbo_cal + } + #[doc = "0xfec - EFuse Config Register"] + #[inline(always)] + pub const fn ef_config(&self) -> &EfConfig { + &self.ef_config + } + #[doc = "0xff0 - EFuse ID0 Register"] + #[inline(always)] + pub const fn ef_id0(&self) -> &EfId0 { + &self.ef_id0 + } + #[doc = "0xff4 - EFuse ID1 Register"] + #[inline(always)] + pub const fn ef_id1(&self) -> &EfId1 { + &self.ef_id1 + } + #[doc = "0xff8 - Processor ID Register"] + #[inline(always)] + pub const fn procid(&self) -> &Procid { + &self.procid + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`] module"] +#[doc(alias = "RST_STAT")] +pub type RstStat = crate::Reg; +#[doc = "System Reset Status"] +pub mod rst_stat; +pub use rst_stat as rst_cntl_rom; +pub use rst_stat as rst_cntl_ram0; +pub use rst_stat as rst_cntl_ram1; +pub use RstStat as RstCntlRom; +pub use RstStat as RstCntlRam0; +pub use RstStat as RstCntlRam1; +#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`] module"] +#[doc(alias = "ROM_PROT")] +pub type RomProt = crate::Reg; +#[doc = "ROM Protection Configuration"] +pub mod rom_prot; +#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`] module"] +#[doc(alias = "ROM_SCRUB")] +pub type RomScrub = crate::Reg; +#[doc = "ROM Scrub Period Configuration"] +pub mod rom_scrub; +pub use rom_scrub as ram0_scrub; +pub use rom_scrub as ram1_scrub; +pub use RomScrub as Ram0Scrub; +pub use RomScrub as Ram1Scrub; +#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Enable EDAC Error Interrupt Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RAM0_SBE (rw) register accessor: Count of RAM0 EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram0_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram0_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram0_sbe`] module"] +#[doc(alias = "RAM0_SBE")] +pub type Ram0Sbe = crate::Reg; +#[doc = "Count of RAM0 EDAC Single Bit Errors"] +pub mod ram0_sbe; +pub use ram0_sbe as ram1_sbe; +pub use Ram0Sbe as Ram1Sbe; +#[doc = "RAM0_MBE (rw) register accessor: Count of RAM0 EDAC Multi Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram0_mbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram0_mbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram0_mbe`] module"] +#[doc(alias = "RAM0_MBE")] +pub type Ram0Mbe = crate::Reg; +#[doc = "Count of RAM0 EDAC Multi Bit Errors"] +pub mod ram0_mbe; +pub use ram0_mbe as ram1_mbe; +pub use ram0_mbe as rom_mbe; +pub use ram0_sbe as rom_sbe; +pub use Ram0Mbe as Ram1Mbe; +pub use Ram0Mbe as RomMbe; +pub use Ram0Sbe as RomSbe; +#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`] module"] +#[doc(alias = "ROM_RETRIES")] +pub type RomRetries = crate::Reg; +#[doc = "ROM BOOT Retry count"] +pub mod rom_retries; +#[doc = "REFRESH_CONFIG_H (rw) register accessor: Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config_h`] module"] +#[doc(alias = "REFRESH_CONFIG_H")] +pub type RefreshConfigH = crate::Reg; +#[doc = "Register Refresh Rate for TMR registers"] +pub mod refresh_config_h; +#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`] module"] +#[doc(alias = "TIM_RESET")] +pub type TimReset = crate::Reg; +#[doc = "TIM Reset Control"] +pub mod tim_reset; +#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`] module"] +#[doc(alias = "TIM_CLK_ENABLE")] +pub type TimClkEnable = crate::Reg; +#[doc = "TIM Enable Control"] +pub mod tim_clk_enable; +#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`] module"] +#[doc(alias = "PERIPHERAL_RESET")] +pub type PeripheralReset = crate::Reg; +#[doc = "Peripheral Reset Control"] +pub mod peripheral_reset; +pub use peripheral_reset as peripheral_clk_enable; +pub use PeripheralReset as PeripheralClkEnable; +#[doc = "SPW_M4_CTRL (rw) register accessor: SPW M4 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spw_m4_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spw_m4_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spw_m4_ctrl`] module"] +#[doc(alias = "SPW_M4_CTRL")] +pub type SpwM4Ctrl = crate::Reg; +#[doc = "SPW M4 control register"] +pub mod spw_m4_ctrl; +#[doc = "PMU_CTRL (rw) register accessor: PMU Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pmu_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmu_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmu_ctrl`] module"] +#[doc(alias = "PMU_CTRL")] +pub type PmuCtrl = crate::Reg; +#[doc = "PMU Control Register"] +pub mod pmu_ctrl; +#[doc = "WAKEUP_CNT (rw) register accessor: Wakeup Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeup_cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeup_cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup_cnt`] module"] +#[doc(alias = "WAKEUP_CNT")] +pub type WakeupCnt = crate::Reg; +#[doc = "Wakeup Control"] +pub mod wakeup_cnt; +#[doc = "EBI_CFG0 (rw) register accessor: EBI Config Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ebi_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ebi_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ebi_cfg0`] module"] +#[doc(alias = "EBI_CFG0")] +pub type EbiCfg0 = crate::Reg; +#[doc = "EBI Config Register 0"] +pub mod ebi_cfg0; +pub use ebi_cfg0 as ebi_cfg1; +pub use ebi_cfg0 as ebi_cfg2; +pub use ebi_cfg0 as ebi_cfg3; +pub use EbiCfg0 as EbiCfg1; +pub use EbiCfg0 as EbiCfg2; +pub use EbiCfg0 as EbiCfg3; +#[doc = "ANALOG_CNTL (rw) register accessor: Analog Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`analog_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`analog_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@analog_cntl`] module"] +#[doc(alias = "ANALOG_CNTL")] +pub type AnalogCntl = crate::Reg; +#[doc = "Analog Control Register"] +pub mod analog_cntl; +#[doc = "SW_CLKDIV10 (rw) register accessor: Initial SpW Clock Divider Value\n\nYou can [`read`](crate::Reg::read) this register and get [`sw_clkdiv10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_clkdiv10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_clkdiv10`] module"] +#[doc(alias = "SW_CLKDIV10")] +pub type SwClkdiv10 = crate::Reg; +#[doc = "Initial SpW Clock Divider Value"] +pub mod sw_clkdiv10; +#[doc = "REFRESH_CONFIG_L (rw) register accessor: Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config_l`] module"] +#[doc(alias = "REFRESH_CONFIG_L")] +pub type RefreshConfigL = crate::Reg; +#[doc = "Register Refresh Rate for TMR registers"] +pub mod refresh_config_l; +#[doc = "DAC0_CAL (r) register accessor: DAC0 Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dac0_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac0_cal`] module"] +#[doc(alias = "DAC0_CAL")] +pub type Dac0Cal = crate::Reg; +#[doc = "DAC0 Calibration Register"] +pub mod dac0_cal; +#[doc = "DAC1_CAL (r) register accessor: DAC1 Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dac1_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac1_cal`] module"] +#[doc(alias = "DAC1_CAL")] +pub type Dac1Cal = crate::Reg; +#[doc = "DAC1 Calibration Register"] +pub mod dac1_cal; +#[doc = "ADC_CAL (r) register accessor: ADC Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`adc_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc_cal`] module"] +#[doc(alias = "ADC_CAL")] +pub type AdcCal = crate::Reg; +#[doc = "ADC Calibration Register"] +pub mod adc_cal; +#[doc = "BG_CAL (r) register accessor: Bandgap Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`bg_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bg_cal`] module"] +#[doc(alias = "BG_CAL")] +pub type BgCal = crate::Reg; +#[doc = "Bandgap Calibration Register"] +pub mod bg_cal; +#[doc = "DREG_CAL (r) register accessor: Digital LDO Regulator Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dreg_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dreg_cal`] module"] +#[doc(alias = "DREG_CAL")] +pub type DregCal = crate::Reg; +#[doc = "Digital LDO Regulator Calibration Register"] +pub mod dreg_cal; +#[doc = "AREG_CAL (r) register accessor: Analog LDO Regulator Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`areg_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@areg_cal`] module"] +#[doc(alias = "AREG_CAL")] +pub type AregCal = crate::Reg; +#[doc = "Analog LDO Regulator Calibration Register"] +pub mod areg_cal; +#[doc = "HBO_CAL (r) register accessor: Heart Beat OSC Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hbo_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hbo_cal`] module"] +#[doc(alias = "HBO_CAL")] +pub type HboCal = crate::Reg; +#[doc = "Heart Beat OSC Calibration Register"] +pub mod hbo_cal; +#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`] module"] +#[doc(alias = "EF_CONFIG")] +pub type EfConfig = crate::Reg; +#[doc = "EFuse Config Register"] +pub mod ef_config; +#[doc = "EF_ID0 (r) register accessor: EFuse ID0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id0`] module"] +#[doc(alias = "EF_ID0")] +pub type EfId0 = crate::Reg; +#[doc = "EFuse ID0 Register"] +pub mod ef_id0; +#[doc = "EF_ID1 (r) register accessor: EFuse ID1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id1`] module"] +#[doc(alias = "EF_ID1")] +pub type EfId1 = crate::Reg; +#[doc = "EFuse ID1 Register"] +pub mod ef_id1; +#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`] module"] +#[doc(alias = "PROCID")] +pub type Procid = crate::Reg; +#[doc = "Processor ID Register"] +pub mod procid; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/sysconfig/adc_cal.rs b/va416xx/va416xx/src/sysconfig/adc_cal.rs new file mode 100644 index 0000000..7ea8670 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/adc_cal.rs @@ -0,0 +1,20 @@ +#[doc = "Register `ADC_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `ADC_CAL` reader - ADC Calibration bits"] +pub type AdcCalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - ADC Calibration bits"] + #[inline(always)] + pub fn adc_cal(&self) -> AdcCalR { + AdcCalR::new((self.bits & 0x1f) as u8) + } +} +#[doc = "ADC Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`adc_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AdcCalSpec; +impl crate::RegisterSpec for AdcCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc_cal::R`](R) reader structure"] +impl crate::Readable for AdcCalSpec {} +#[doc = "`reset()` method sets ADC_CAL to value 0"] +impl crate::Resettable for AdcCalSpec {} diff --git a/va416xx/va416xx/src/sysconfig/analog_cntl.rs b/va416xx/va416xx/src/sysconfig/analog_cntl.rs new file mode 100644 index 0000000..7c403b8 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/analog_cntl.rs @@ -0,0 +1,217 @@ +#[doc = "Register `ANALOG_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `ANALOG_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `TMOSC` reader - Test Mode"] +pub type TmoscR = crate::BitReader; +#[doc = "Field `TMOSC` writer - Test Mode"] +pub type TmoscW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMPOKDIS` reader - Test Mode"] +pub type TmpokdisR = crate::BitReader; +#[doc = "Field `TMPOKDIS` writer - Test Mode"] +pub type TmpokdisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TM_ADCMUX_N` reader - Test Mode"] +pub type TmAdcmuxNR = crate::BitReader; +#[doc = "Field `TM_ADCMUX_N` writer - Test Mode"] +pub type TmAdcmuxNW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TM_ADCMUX_P` reader - Test Mode"] +pub type TmAdcmuxPR = crate::BitReader; +#[doc = "Field `TM_ADCMUX_P` writer - Test Mode"] +pub type TmAdcmuxPW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMRATIO` reader - Test Mode"] +pub type TmratioR = crate::BitReader; +#[doc = "Field `TMRATIO` writer - Test Mode"] +pub type TmratioW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMATOMUX` reader - Test Mode"] +pub type TmatomuxR = crate::FieldReader; +#[doc = "Field `TMATOMUX` writer - Test Mode"] +pub type TmatomuxW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ADC_STEST` reader - Number of clocks for sample time"] +pub type AdcStestR = crate::FieldReader; +#[doc = "Field `ADC_STEST` writer - Number of clocks for sample time"] +pub type AdcStestW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RCLK_POS_EN` reader - Enable normal test clock"] +pub type RclkPosEnR = crate::BitReader; +#[doc = "Field `RCLK_POS_EN` writer - Enable normal test clock"] +pub type RclkPosEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RCLK_NEG_EN` reader - Enable inverted test clock"] +pub type RclkNegEnR = crate::BitReader; +#[doc = "Field `RCLK_NEG_EN` writer - Enable inverted test clock"] +pub type RclkNegEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB2CLK_POS_EN` reader - Enable normal APB2CLK for test output"] +pub type Apb2clkPosEnR = crate::BitReader; +#[doc = "Field `APB2CLK_POS_EN` writer - Enable normal APB2CLK for test output"] +pub type Apb2clkPosEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB2CLK_NEG_EN` reader - Enable inverted APB2CLK for test output"] +pub type Apb2clkNegEnR = crate::BitReader; +#[doc = "Field `APB2CLK_NEG_EN` writer - Enable inverted APB2CLK for test output"] +pub type Apb2clkNegEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TM_ANALOG_PD_EN` reader - Enables pull down on analog pads"] +pub type TmAnalogPdEnR = crate::BitReader; +#[doc = "Field `TM_ANALOG_PD_EN` writer - Enables pull down on analog pads"] +pub type TmAnalogPdEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JMP2BOOT` reader - Enables a skip of all delay counters and eFuse read"] +pub type Jmp2bootR = crate::BitReader; +#[doc = "Field `JMP2BOOT` writer - Enables a skip of all delay counters and eFuse read"] +pub type Jmp2bootW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SKIPBOOT` reader - Enables a skip of all delay counters, eFuse read, and boot"] +pub type SkipbootR = crate::BitReader; +#[doc = "Field `SKIPBOOT` writer - Enables a skip of all delay counters, eFuse read, and boot"] +pub type SkipbootW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Test Mode"] + #[inline(always)] + pub fn tmosc(&self) -> TmoscR { + TmoscR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Test Mode"] + #[inline(always)] + pub fn tmpokdis(&self) -> TmpokdisR { + TmpokdisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_n(&self) -> TmAdcmuxNR { + TmAdcmuxNR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_p(&self) -> TmAdcmuxPR { + TmAdcmuxPR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Test Mode"] + #[inline(always)] + pub fn tmratio(&self) -> TmratioR { + TmratioR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Test Mode"] + #[inline(always)] + pub fn tmatomux(&self) -> TmatomuxR { + TmatomuxR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bits 9:12 - Number of clocks for sample time"] + #[inline(always)] + pub fn adc_stest(&self) -> AdcStestR { + AdcStestR::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bit 14 - Enable normal test clock"] + #[inline(always)] + pub fn rclk_pos_en(&self) -> RclkPosEnR { + RclkPosEnR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Enable inverted test clock"] + #[inline(always)] + pub fn rclk_neg_en(&self) -> RclkNegEnR { + RclkNegEnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Enable normal APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_pos_en(&self) -> Apb2clkPosEnR { + Apb2clkPosEnR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable inverted APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_neg_en(&self) -> Apb2clkNegEnR { + Apb2clkNegEnR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enables pull down on analog pads"] + #[inline(always)] + pub fn tm_analog_pd_en(&self) -> TmAnalogPdEnR { + TmAnalogPdEnR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"] + #[inline(always)] + pub fn jmp2boot(&self) -> Jmp2bootR { + Jmp2bootR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"] + #[inline(always)] + pub fn skipboot(&self) -> SkipbootR { + SkipbootR::new(((self.bits >> 20) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Test Mode"] + #[inline(always)] + pub fn tmosc(&mut self) -> TmoscW<'_, AnalogCntlSpec> { + TmoscW::new(self, 0) + } + #[doc = "Bit 1 - Test Mode"] + #[inline(always)] + pub fn tmpokdis(&mut self) -> TmpokdisW<'_, AnalogCntlSpec> { + TmpokdisW::new(self, 1) + } + #[doc = "Bit 2 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_n(&mut self) -> TmAdcmuxNW<'_, AnalogCntlSpec> { + TmAdcmuxNW::new(self, 2) + } + #[doc = "Bit 3 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_p(&mut self) -> TmAdcmuxPW<'_, AnalogCntlSpec> { + TmAdcmuxPW::new(self, 3) + } + #[doc = "Bit 4 - Test Mode"] + #[inline(always)] + pub fn tmratio(&mut self) -> TmratioW<'_, AnalogCntlSpec> { + TmratioW::new(self, 4) + } + #[doc = "Bits 5:6 - Test Mode"] + #[inline(always)] + pub fn tmatomux(&mut self) -> TmatomuxW<'_, AnalogCntlSpec> { + TmatomuxW::new(self, 5) + } + #[doc = "Bits 9:12 - Number of clocks for sample time"] + #[inline(always)] + pub fn adc_stest(&mut self) -> AdcStestW<'_, AnalogCntlSpec> { + AdcStestW::new(self, 9) + } + #[doc = "Bit 14 - Enable normal test clock"] + #[inline(always)] + pub fn rclk_pos_en(&mut self) -> RclkPosEnW<'_, AnalogCntlSpec> { + RclkPosEnW::new(self, 14) + } + #[doc = "Bit 15 - Enable inverted test clock"] + #[inline(always)] + pub fn rclk_neg_en(&mut self) -> RclkNegEnW<'_, AnalogCntlSpec> { + RclkNegEnW::new(self, 15) + } + #[doc = "Bit 16 - Enable normal APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_pos_en(&mut self) -> Apb2clkPosEnW<'_, AnalogCntlSpec> { + Apb2clkPosEnW::new(self, 16) + } + #[doc = "Bit 17 - Enable inverted APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_neg_en(&mut self) -> Apb2clkNegEnW<'_, AnalogCntlSpec> { + Apb2clkNegEnW::new(self, 17) + } + #[doc = "Bit 18 - Enables pull down on analog pads"] + #[inline(always)] + pub fn tm_analog_pd_en(&mut self) -> TmAnalogPdEnW<'_, AnalogCntlSpec> { + TmAnalogPdEnW::new(self, 18) + } + #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"] + #[inline(always)] + pub fn jmp2boot(&mut self) -> Jmp2bootW<'_, AnalogCntlSpec> { + Jmp2bootW::new(self, 19) + } + #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"] + #[inline(always)] + pub fn skipboot(&mut self) -> SkipbootW<'_, AnalogCntlSpec> { + SkipbootW::new(self, 20) + } +} +#[doc = "Analog Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`analog_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`analog_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AnalogCntlSpec; +impl crate::RegisterSpec for AnalogCntlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`analog_cntl::R`](R) reader structure"] +impl crate::Readable for AnalogCntlSpec {} +#[doc = "`write(|w| ..)` method takes [`analog_cntl::W`](W) writer structure"] +impl crate::Writable for AnalogCntlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ANALOG_CNTL to value 0"] +impl crate::Resettable for AnalogCntlSpec {} diff --git a/va416xx/va416xx/src/sysconfig/areg_cal.rs b/va416xx/va416xx/src/sysconfig/areg_cal.rs new file mode 100644 index 0000000..109c377 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/areg_cal.rs @@ -0,0 +1,20 @@ +#[doc = "Register `AREG_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `AREG_CAL` reader - Analog LDO Regulator Calibration bits"] +pub type AregCalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:8 - Analog LDO Regulator Calibration bits"] + #[inline(always)] + pub fn areg_cal(&self) -> AregCalR { + AregCalR::new((self.bits & 0x01ff) as u16) + } +} +#[doc = "Analog LDO Regulator Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`areg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AregCalSpec; +impl crate::RegisterSpec for AregCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`areg_cal::R`](R) reader structure"] +impl crate::Readable for AregCalSpec {} +#[doc = "`reset()` method sets AREG_CAL to value 0"] +impl crate::Resettable for AregCalSpec {} diff --git a/va416xx/va416xx/src/sysconfig/bg_cal.rs b/va416xx/va416xx/src/sysconfig/bg_cal.rs new file mode 100644 index 0000000..4c90b2b --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/bg_cal.rs @@ -0,0 +1,20 @@ +#[doc = "Register `BG_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `BG_CAL` reader - Bandgap Calibration bits"] +pub type BgCalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Bandgap Calibration bits"] + #[inline(always)] + pub fn bg_cal(&self) -> BgCalR { + BgCalR::new((self.bits & 7) as u8) + } +} +#[doc = "Bandgap Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`bg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BgCalSpec; +impl crate::RegisterSpec for BgCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bg_cal::R`](R) reader structure"] +impl crate::Readable for BgCalSpec {} +#[doc = "`reset()` method sets BG_CAL to value 0"] +impl crate::Resettable for BgCalSpec {} diff --git a/va416xx/va416xx/src/sysconfig/dac0_cal.rs b/va416xx/va416xx/src/sysconfig/dac0_cal.rs new file mode 100644 index 0000000..29ea22f --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/dac0_cal.rs @@ -0,0 +1,20 @@ +#[doc = "Register `DAC0_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `DAC0_CAL` reader - DAC0 Calibration bits"] +pub type Dac0CalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - DAC0 Calibration bits"] + #[inline(always)] + pub fn dac0_cal(&self) -> Dac0CalR { + Dac0CalR::new((self.bits & 0x1f) as u8) + } +} +#[doc = "DAC0 Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dac0_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dac0CalSpec; +impl crate::RegisterSpec for Dac0CalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dac0_cal::R`](R) reader structure"] +impl crate::Readable for Dac0CalSpec {} +#[doc = "`reset()` method sets DAC0_CAL to value 0"] +impl crate::Resettable for Dac0CalSpec {} diff --git a/va416xx/va416xx/src/sysconfig/dac1_cal.rs b/va416xx/va416xx/src/sysconfig/dac1_cal.rs new file mode 100644 index 0000000..26680cc --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/dac1_cal.rs @@ -0,0 +1,20 @@ +#[doc = "Register `DAC1_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `DAC1_CAL` reader - DAC1 Calibration bits"] +pub type Dac1CalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - DAC1 Calibration bits"] + #[inline(always)] + pub fn dac1_cal(&self) -> Dac1CalR { + Dac1CalR::new((self.bits & 0x1f) as u8) + } +} +#[doc = "DAC1 Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dac1_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dac1CalSpec; +impl crate::RegisterSpec for Dac1CalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dac1_cal::R`](R) reader structure"] +impl crate::Readable for Dac1CalSpec {} +#[doc = "`reset()` method sets DAC1_CAL to value 0"] +impl crate::Resettable for Dac1CalSpec {} diff --git a/va416xx/va416xx/src/sysconfig/dreg_cal.rs b/va416xx/va416xx/src/sysconfig/dreg_cal.rs new file mode 100644 index 0000000..e43b927 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/dreg_cal.rs @@ -0,0 +1,20 @@ +#[doc = "Register `DREG_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `DREG_CAL` reader - Digital LDO Regulator Calibration bits"] +pub type DregCalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:8 - Digital LDO Regulator Calibration bits"] + #[inline(always)] + pub fn dreg_cal(&self) -> DregCalR { + DregCalR::new((self.bits & 0x01ff) as u16) + } +} +#[doc = "Digital LDO Regulator Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dreg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DregCalSpec; +impl crate::RegisterSpec for DregCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dreg_cal::R`](R) reader structure"] +impl crate::Readable for DregCalSpec {} +#[doc = "`reset()` method sets DREG_CAL to value 0"] +impl crate::Resettable for DregCalSpec {} diff --git a/va416xx/va416xx/src/sysconfig/ebi_cfg0.rs b/va416xx/va416xx/src/sysconfig/ebi_cfg0.rs new file mode 100644 index 0000000..af6863f --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/ebi_cfg0.rs @@ -0,0 +1,105 @@ +#[doc = "Register `EBI_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `EBI_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"] +pub type Addrlow0R = crate::FieldReader; +#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"] +pub type Addrlow0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"] +pub type Addrhigh0R = crate::FieldReader; +#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"] +pub type Addrhigh0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"] +pub type CfgreadcycleR = crate::FieldReader; +#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"] +pub type CfgreadcycleW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"] +pub type CfgwritecycleR = crate::FieldReader; +#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"] +pub type CfgwritecycleW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"] +pub type CfgturnaroundcycleR = crate::FieldReader; +#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"] +pub type CfgturnaroundcycleW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"] +pub type CfgsizeR = crate::BitReader; +#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"] +pub type CfgsizeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&self) -> Addrlow0R { + Addrlow0R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&self) -> Addrhigh0R { + Addrhigh0R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&self) -> CfgreadcycleR { + CfgreadcycleR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&self) -> CfgwritecycleR { + CfgwritecycleR::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&self) -> CfgturnaroundcycleR { + CfgturnaroundcycleR::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&self) -> CfgsizeR { + CfgsizeR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&mut self) -> Addrlow0W<'_, EbiCfg0Spec> { + Addrlow0W::new(self, 0) + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&mut self) -> Addrhigh0W<'_, EbiCfg0Spec> { + Addrhigh0W::new(self, 8) + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&mut self) -> CfgreadcycleW<'_, EbiCfg0Spec> { + CfgreadcycleW::new(self, 16) + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&mut self) -> CfgwritecycleW<'_, EbiCfg0Spec> { + CfgwritecycleW::new(self, 19) + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&mut self) -> CfgturnaroundcycleW<'_, EbiCfg0Spec> { + CfgturnaroundcycleW::new(self, 22) + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&mut self) -> CfgsizeW<'_, EbiCfg0Spec> { + CfgsizeW::new(self, 25) + } +} +#[doc = "EBI Config Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ebi_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ebi_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EbiCfg0Spec; +impl crate::RegisterSpec for EbiCfg0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ebi_cfg0::R`](R) reader structure"] +impl crate::Readable for EbiCfg0Spec {} +#[doc = "`write(|w| ..)` method takes [`ebi_cfg0::W`](W) writer structure"] +impl crate::Writable for EbiCfg0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets EBI_CFG0 to value 0"] +impl crate::Resettable for EbiCfg0Spec {} diff --git a/va416xx/va416xx/src/sysconfig/ef_config.rs b/va416xx/va416xx/src/sysconfig/ef_config.rs new file mode 100644 index 0000000..003f68f --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/ef_config.rs @@ -0,0 +1,92 @@ +#[doc = "Register `EF_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Field `ROM_SPEED` reader - Specifies the speed of ROM_SCK"] +pub type RomSpeedR = crate::FieldReader; +#[doc = "Field `ROM_SIZE` reader - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"] +pub type RomSizeR = crate::FieldReader; +#[doc = "Field `ROM_NOCHECK` reader - When set to 1, the ROM check is skipped"] +pub type RomNocheckR = crate::BitReader; +#[doc = "Field `BOOT_DELAY` reader - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"] +pub type BootDelayR = crate::FieldReader; +#[doc = "Field `ROM_READ` reader - SPI ROM read instruction code"] +pub type RomReadR = crate::FieldReader; +#[doc = "Field `ROM_LATENCY` reader - Number of bits of latency from Address until data from the SPI ROM"] +pub type RomLatencyR = crate::FieldReader; +#[doc = "Field `ROM_ADDRESS` reader - ROM Address Mode"] +pub type RomAddressR = crate::FieldReader; +#[doc = "Field `ROM_DLYCAP` reader - ROM SPI Delayed capture"] +pub type RomDlycapR = crate::BitReader; +#[doc = "Field `ROM_STATUS` reader - The first data byte from the SPI ROM following an address is taken as a status byte"] +pub type RomStatusR = crate::BitReader; +#[doc = "Field `RM` reader - This bit controls the internal RAM read timing and must be maintained at this value"] +pub type RmR = crate::BitReader; +#[doc = "Field `WM` reader - This bit controls the internal RAM write timing and must be maintained at this value"] +pub type WmR = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - Specifies the speed of ROM_SCK"] + #[inline(always)] + pub fn rom_speed(&self) -> RomSpeedR { + RomSpeedR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:5 - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"] + #[inline(always)] + pub fn rom_size(&self) -> RomSizeR { + RomSizeR::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - When set to 1, the ROM check is skipped"] + #[inline(always)] + pub fn rom_nocheck(&self) -> RomNocheckR { + RomNocheckR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:9 - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"] + #[inline(always)] + pub fn boot_delay(&self) -> BootDelayR { + BootDelayR::new(((self.bits >> 7) & 7) as u8) + } + #[doc = "Bits 10:17 - SPI ROM read instruction code"] + #[inline(always)] + pub fn rom_read(&self) -> RomReadR { + RomReadR::new(((self.bits >> 10) & 0xff) as u8) + } + #[doc = "Bits 18:22 - Number of bits of latency from Address until data from the SPI ROM"] + #[inline(always)] + pub fn rom_latency(&self) -> RomLatencyR { + RomLatencyR::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bits 23:24 - ROM Address Mode"] + #[inline(always)] + pub fn rom_address(&self) -> RomAddressR { + RomAddressR::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - ROM SPI Delayed capture"] + #[inline(always)] + pub fn rom_dlycap(&self) -> RomDlycapR { + RomDlycapR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - The first data byte from the SPI ROM following an address is taken as a status byte"] + #[inline(always)] + pub fn rom_status(&self) -> RomStatusR { + RomStatusR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - This bit controls the internal RAM read timing and must be maintained at this value"] + #[inline(always)] + pub fn rm(&self) -> RmR { + RmR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - This bit controls the internal RAM write timing and must be maintained at this value"] + #[inline(always)] + pub fn wm(&self) -> WmR { + WmR::new(((self.bits >> 28) & 1) != 0) + } +} +#[doc = "EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EfConfigSpec; +impl crate::RegisterSpec for EfConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ef_config::R`](R) reader structure"] +impl crate::Readable for EfConfigSpec {} +#[doc = "`reset()` method sets EF_CONFIG to value 0x0a80_0c40"] +impl crate::Resettable for EfConfigSpec { + const RESET_VALUE: u32 = 0x0a80_0c40; +} diff --git a/va416xx/va416xx/src/sysconfig/ef_id0.rs b/va416xx/va416xx/src/sysconfig/ef_id0.rs new file mode 100644 index 0000000..7e5988c --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/ef_id0.rs @@ -0,0 +1,17 @@ +#[doc = "Register `EF_ID0` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EFuse ID0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EfId0Spec; +impl crate::RegisterSpec for EfId0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ef_id0::R`](R) reader structure"] +impl crate::Readable for EfId0Spec {} +#[doc = "`reset()` method sets EF_ID0 to value 0"] +impl crate::Resettable for EfId0Spec {} diff --git a/va416xx/va416xx/src/sysconfig/ef_id1.rs b/va416xx/va416xx/src/sysconfig/ef_id1.rs new file mode 100644 index 0000000..eb6816c --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/ef_id1.rs @@ -0,0 +1,17 @@ +#[doc = "Register `EF_ID1` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EFuse ID1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EfId1Spec; +impl crate::RegisterSpec for EfId1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ef_id1::R`](R) reader structure"] +impl crate::Readable for EfId1Spec {} +#[doc = "`reset()` method sets EF_ID1 to value 0"] +impl crate::Resettable for EfId1Spec {} diff --git a/va416xx/va416xx/src/sysconfig/hbo_cal.rs b/va416xx/va416xx/src/sysconfig/hbo_cal.rs new file mode 100644 index 0000000..c715344 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/hbo_cal.rs @@ -0,0 +1,27 @@ +#[doc = "Register `HBO_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `HBO_CAL` reader - Heart Beat OSC Calibration bits"] +pub type HboCalR = crate::FieldReader; +#[doc = "Field `OSC_CAL` reader - 1MHz OSC Calibration bit"] +pub type OscCalR = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - Heart Beat OSC Calibration bits"] + #[inline(always)] + pub fn hbo_cal(&self) -> HboCalR { + HboCalR::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - 1MHz OSC Calibration bit"] + #[inline(always)] + pub fn osc_cal(&self) -> OscCalR { + OscCalR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Heart Beat OSC Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hbo_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HboCalSpec; +impl crate::RegisterSpec for HboCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`hbo_cal::R`](R) reader structure"] +impl crate::Readable for HboCalSpec {} +#[doc = "`reset()` method sets HBO_CAL to value 0"] +impl crate::Resettable for HboCalSpec {} diff --git a/va416xx/va416xx/src/sysconfig/irq_enb.rs b/va416xx/va416xx/src/sysconfig/irq_enb.rs new file mode 100644 index 0000000..e355f19 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/irq_enb.rs @@ -0,0 +1,105 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"] +pub type RommbeR = crate::BitReader; +#[doc = "Field `ROMMBE` writer - ROM Multi Bit Interrupt"] +pub type RommbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"] +pub type RomsbeR = crate::BitReader; +#[doc = "Field `ROMSBE` writer - ROM Single Bit Interrupt"] +pub type RomsbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM0MBE` reader - RAM0 Multi Bit Interrupt"] +pub type Ram0mbeR = crate::BitReader; +#[doc = "Field `RAM0MBE` writer - RAM0 Multi Bit Interrupt"] +pub type Ram0mbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM0SBE` reader - RAM0 Single Bit Interrupt"] +pub type Ram0sbeR = crate::BitReader; +#[doc = "Field `RAM0SBE` writer - RAM0 Single Bit Interrupt"] +pub type Ram0sbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM1MBE` reader - RAM1 Multi Bit Interrupt"] +pub type Ram1mbeR = crate::BitReader; +#[doc = "Field `RAM1MBE` writer - RAM1 Multi Bit Interrupt"] +pub type Ram1mbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM1SBE` reader - RAM1 Single Bit Interrupt"] +pub type Ram1sbeR = crate::BitReader; +#[doc = "Field `RAM1SBE` writer - RAM1 Single Bit Interrupt"] +pub type Ram1sbeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&self) -> RommbeR { + RommbeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&self) -> RomsbeR { + RomsbeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram0mbe(&self) -> Ram0mbeR { + Ram0mbeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RAM0 Single Bit Interrupt"] + #[inline(always)] + pub fn ram0sbe(&self) -> Ram0sbeR { + Ram0sbeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram1mbe(&self) -> Ram1mbeR { + Ram1mbeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RAM1 Single Bit Interrupt"] + #[inline(always)] + pub fn ram1sbe(&self) -> Ram1sbeR { + Ram1sbeR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&mut self) -> RommbeW<'_, IrqEnbSpec> { + RommbeW::new(self, 0) + } + #[doc = "Bit 1 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&mut self) -> RomsbeW<'_, IrqEnbSpec> { + RomsbeW::new(self, 1) + } + #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram0mbe(&mut self) -> Ram0mbeW<'_, IrqEnbSpec> { + Ram0mbeW::new(self, 2) + } + #[doc = "Bit 3 - RAM0 Single Bit Interrupt"] + #[inline(always)] + pub fn ram0sbe(&mut self) -> Ram0sbeW<'_, IrqEnbSpec> { + Ram0sbeW::new(self, 3) + } + #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram1mbe(&mut self) -> Ram1mbeW<'_, IrqEnbSpec> { + Ram1mbeW::new(self, 4) + } + #[doc = "Bit 5 - RAM1 Single Bit Interrupt"] + #[inline(always)] + pub fn ram1sbe(&mut self) -> Ram1sbeW<'_, IrqEnbSpec> { + Ram1sbeW::new(self, 5) + } +} +#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va416xx/va416xx/src/sysconfig/perid.rs b/va416xx/va416xx/src/sysconfig/perid.rs new file mode 100644 index 0000000..33f5643 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/perid.rs @@ -0,0 +1,36 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[doc = "Field `MANUFACTURER_ID` reader - MANUFACTURER_ID"] +pub type ManufacturerIdR = crate::FieldReader; +#[doc = "Field `PERIPHERAL_ID` reader - PERIPHERAL_ID"] +pub type PeripheralIdR = crate::FieldReader; +#[doc = "Field `PERIPHERAL_VER` reader - PERIPHERAL_VER"] +pub type PeripheralVerR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - MANUFACTURER_ID"] + #[inline(always)] + pub fn manufacturer_id(&self) -> ManufacturerIdR { + ManufacturerIdR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:23 - PERIPHERAL_ID"] + #[inline(always)] + pub fn peripheral_id(&self) -> PeripheralIdR { + PeripheralIdR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - PERIPHERAL_VER"] + #[inline(always)] + pub fn peripheral_ver(&self) -> PeripheralVerR { + PeripheralVerR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0280_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0280_07e9; +} diff --git a/va416xx/va416xx/src/sysconfig/peripheral_reset.rs b/va416xx/va416xx/src/sysconfig/peripheral_reset.rs new file mode 100644 index 0000000..3d03aff --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/peripheral_reset.rs @@ -0,0 +1,457 @@ +#[doc = "Register `PERIPHERAL_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPHERAL_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `SPI0` reader - Resetn of SPI0"] +pub type Spi0R = crate::BitReader; +#[doc = "Field `SPI0` writer - Resetn of SPI0"] +pub type Spi0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI1` reader - Resetn of SPI1"] +pub type Spi1R = crate::BitReader; +#[doc = "Field `SPI1` writer - Resetn of SPI1"] +pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI2` reader - Resetn of SPI2"] +pub type Spi2R = crate::BitReader; +#[doc = "Field `SPI2` writer - Resetn of SPI2"] +pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI3` reader - Resetn of SPI3"] +pub type Spi3R = crate::BitReader; +#[doc = "Field `SPI3` writer - Resetn of SPI3"] +pub type Spi3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART0` reader - Resetn of UART0"] +pub type Uart0R = crate::BitReader; +#[doc = "Field `UART0` writer - Resetn of UART0"] +pub type Uart0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART1` reader - Resetn of UART1"] +pub type Uart1R = crate::BitReader; +#[doc = "Field `UART1` writer - Resetn of UART1"] +pub type Uart1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART2` reader - Resetn of UART2"] +pub type Uart2R = crate::BitReader; +#[doc = "Field `UART2` writer - Resetn of UART2"] +pub type Uart2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C0` reader - Resetn of I2C0"] +pub type I2c0R = crate::BitReader; +#[doc = "Field `I2C0` writer - Resetn of I2C0"] +pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C1` reader - Resetn of I2C1"] +pub type I2c1R = crate::BitReader; +#[doc = "Field `I2C1` writer - Resetn of I2C1"] +pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C2` reader - Resetn of I2C2"] +pub type I2c2R = crate::BitReader; +#[doc = "Field `I2C2` writer - Resetn of I2C2"] +pub type I2c2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAN0` reader - Resetn of CAN0"] +pub type Can0R = crate::BitReader; +#[doc = "Field `CAN0` writer - Resetn of CAN0"] +pub type Can0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAN1` reader - Resetn of CAN1"] +pub type Can1R = crate::BitReader; +#[doc = "Field `CAN1` writer - Resetn of CAN1"] +pub type Can1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRNG` reader - Resetn of TRNG"] +pub type TrngR = crate::BitReader; +#[doc = "Field `TRNG` writer - Resetn of TRNG"] +pub type TrngW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC` reader - Resetn of ADC"] +pub type AdcR = crate::BitReader; +#[doc = "Field `ADC` writer - Resetn of ADC"] +pub type AdcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DAC` reader - Resetn of DAC"] +pub type DacR = crate::BitReader; +#[doc = "Field `DAC` writer - Resetn of DAC"] +pub type DacW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - Resetn of DMA"] +pub type DmaR = crate::BitReader; +#[doc = "Field `DMA` writer - Resetn of DMA"] +pub type DmaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EBI` reader - Resetn of EBI"] +pub type EbiR = crate::BitReader; +#[doc = "Field `EBI` writer - Resetn of EBI"] +pub type EbiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETH` reader - Resetn of Ethernet"] +pub type EthR = crate::BitReader; +#[doc = "Field `ETH` writer - Resetn of Ethernet"] +pub type EthW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPW` reader - Resetn of SpaceWire"] +pub type SpwR = crate::BitReader; +#[doc = "Field `SPW` writer - Resetn of SpaceWire"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLKGEN` reader - RESETn of PLL in Clock Generation Module"] +pub type ClkgenR = crate::BitReader; +#[doc = "Field `CLKGEN` writer - RESETn of PLL in Clock Generation Module"] +pub type ClkgenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ` reader - Resetn of IRQ Router"] +pub type IrqR = crate::BitReader; +#[doc = "Field `IRQ` writer - Resetn of IRQ Router"] +pub type IrqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IOCONFIG` reader - Resetn of IO CONFIG"] +pub type IoconfigR = crate::BitReader; +#[doc = "Field `IOCONFIG` writer - Resetn of IO CONFIG"] +pub type IoconfigW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UTILITY` reader - Resetn of UTILITY peripheral"] +pub type UtilityR = crate::BitReader; +#[doc = "Field `UTILITY` writer - Resetn of UTILITY peripheral"] +pub type UtilityW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDOG` reader - Resetn of WDOG"] +pub type WdogR = crate::BitReader; +#[doc = "Field `WDOG` writer - Resetn of WDOG"] +pub type WdogW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTA` reader - Resetn of PORTA"] +pub type PortaR = crate::BitReader; +#[doc = "Field `PORTA` writer - Resetn of PORTA"] +pub type PortaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTB` reader - Resetn of PORTB"] +pub type PortbR = crate::BitReader; +#[doc = "Field `PORTB` writer - Resetn of PORTB"] +pub type PortbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTC` reader - Resetn of PORTC"] +pub type PortcR = crate::BitReader; +#[doc = "Field `PORTC` writer - Resetn of PORTC"] +pub type PortcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTD` reader - Resetn of PORTD"] +pub type PortdR = crate::BitReader; +#[doc = "Field `PORTD` writer - Resetn of PORTD"] +pub type PortdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTE` reader - Resetn of PORTE"] +pub type PorteR = crate::BitReader; +#[doc = "Field `PORTE` writer - Resetn of PORTE"] +pub type PorteW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTF` reader - Resetn of PORTF"] +pub type PortfR = crate::BitReader; +#[doc = "Field `PORTF` writer - Resetn of PORTF"] +pub type PortfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTG` reader - Resetn of PORTG"] +pub type PortgR = crate::BitReader; +#[doc = "Field `PORTG` writer - Resetn of PORTG"] +pub type PortgW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Resetn of SPI0"] + #[inline(always)] + pub fn spi0(&self) -> Spi0R { + Spi0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Resetn of SPI1"] + #[inline(always)] + pub fn spi1(&self) -> Spi1R { + Spi1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Resetn of SPI2"] + #[inline(always)] + pub fn spi2(&self) -> Spi2R { + Spi2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Resetn of SPI3"] + #[inline(always)] + pub fn spi3(&self) -> Spi3R { + Spi3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Resetn of UART0"] + #[inline(always)] + pub fn uart0(&self) -> Uart0R { + Uart0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Resetn of UART1"] + #[inline(always)] + pub fn uart1(&self) -> Uart1R { + Uart1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Resetn of UART2"] + #[inline(always)] + pub fn uart2(&self) -> Uart2R { + Uart2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Resetn of I2C0"] + #[inline(always)] + pub fn i2c0(&self) -> I2c0R { + I2c0R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Resetn of I2C1"] + #[inline(always)] + pub fn i2c1(&self) -> I2c1R { + I2c1R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Resetn of I2C2"] + #[inline(always)] + pub fn i2c2(&self) -> I2c2R { + I2c2R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Resetn of CAN0"] + #[inline(always)] + pub fn can0(&self) -> Can0R { + Can0R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Resetn of CAN1"] + #[inline(always)] + pub fn can1(&self) -> Can1R { + Can1R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Resetn of TRNG"] + #[inline(always)] + pub fn trng(&self) -> TrngR { + TrngR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Resetn of ADC"] + #[inline(always)] + pub fn adc(&self) -> AdcR { + AdcR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Resetn of DAC"] + #[inline(always)] + pub fn dac(&self) -> DacR { + DacR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Resetn of DMA"] + #[inline(always)] + pub fn dma(&self) -> DmaR { + DmaR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Resetn of EBI"] + #[inline(always)] + pub fn ebi(&self) -> EbiR { + EbiR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Resetn of Ethernet"] + #[inline(always)] + pub fn eth(&self) -> EthR { + EthR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Resetn of SpaceWire"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"] + #[inline(always)] + pub fn clkgen(&self) -> ClkgenR { + ClkgenR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Resetn of IRQ Router"] + #[inline(always)] + pub fn irq(&self) -> IrqR { + IrqR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Resetn of IO CONFIG"] + #[inline(always)] + pub fn ioconfig(&self) -> IoconfigR { + IoconfigR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Resetn of UTILITY peripheral"] + #[inline(always)] + pub fn utility(&self) -> UtilityR { + UtilityR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Resetn of WDOG"] + #[inline(always)] + pub fn wdog(&self) -> WdogR { + WdogR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Resetn of PORTA"] + #[inline(always)] + pub fn porta(&self) -> PortaR { + PortaR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Resetn of PORTB"] + #[inline(always)] + pub fn portb(&self) -> PortbR { + PortbR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Resetn of PORTC"] + #[inline(always)] + pub fn portc(&self) -> PortcR { + PortcR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Resetn of PORTD"] + #[inline(always)] + pub fn portd(&self) -> PortdR { + PortdR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Resetn of PORTE"] + #[inline(always)] + pub fn porte(&self) -> PorteR { + PorteR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Resetn of PORTF"] + #[inline(always)] + pub fn portf(&self) -> PortfR { + PortfR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Resetn of PORTG"] + #[inline(always)] + pub fn portg(&self) -> PortgR { + PortgR::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Resetn of SPI0"] + #[inline(always)] + pub fn spi0(&mut self) -> Spi0W<'_, PeripheralResetSpec> { + Spi0W::new(self, 0) + } + #[doc = "Bit 1 - Resetn of SPI1"] + #[inline(always)] + pub fn spi1(&mut self) -> Spi1W<'_, PeripheralResetSpec> { + Spi1W::new(self, 1) + } + #[doc = "Bit 2 - Resetn of SPI2"] + #[inline(always)] + pub fn spi2(&mut self) -> Spi2W<'_, PeripheralResetSpec> { + Spi2W::new(self, 2) + } + #[doc = "Bit 3 - Resetn of SPI3"] + #[inline(always)] + pub fn spi3(&mut self) -> Spi3W<'_, PeripheralResetSpec> { + Spi3W::new(self, 3) + } + #[doc = "Bit 4 - Resetn of UART0"] + #[inline(always)] + pub fn uart0(&mut self) -> Uart0W<'_, PeripheralResetSpec> { + Uart0W::new(self, 4) + } + #[doc = "Bit 5 - Resetn of UART1"] + #[inline(always)] + pub fn uart1(&mut self) -> Uart1W<'_, PeripheralResetSpec> { + Uart1W::new(self, 5) + } + #[doc = "Bit 6 - Resetn of UART2"] + #[inline(always)] + pub fn uart2(&mut self) -> Uart2W<'_, PeripheralResetSpec> { + Uart2W::new(self, 6) + } + #[doc = "Bit 7 - Resetn of I2C0"] + #[inline(always)] + pub fn i2c0(&mut self) -> I2c0W<'_, PeripheralResetSpec> { + I2c0W::new(self, 7) + } + #[doc = "Bit 8 - Resetn of I2C1"] + #[inline(always)] + pub fn i2c1(&mut self) -> I2c1W<'_, PeripheralResetSpec> { + I2c1W::new(self, 8) + } + #[doc = "Bit 9 - Resetn of I2C2"] + #[inline(always)] + pub fn i2c2(&mut self) -> I2c2W<'_, PeripheralResetSpec> { + I2c2W::new(self, 9) + } + #[doc = "Bit 10 - Resetn of CAN0"] + #[inline(always)] + pub fn can0(&mut self) -> Can0W<'_, PeripheralResetSpec> { + Can0W::new(self, 10) + } + #[doc = "Bit 11 - Resetn of CAN1"] + #[inline(always)] + pub fn can1(&mut self) -> Can1W<'_, PeripheralResetSpec> { + Can1W::new(self, 11) + } + #[doc = "Bit 12 - Resetn of TRNG"] + #[inline(always)] + pub fn trng(&mut self) -> TrngW<'_, PeripheralResetSpec> { + TrngW::new(self, 12) + } + #[doc = "Bit 13 - Resetn of ADC"] + #[inline(always)] + pub fn adc(&mut self) -> AdcW<'_, PeripheralResetSpec> { + AdcW::new(self, 13) + } + #[doc = "Bit 14 - Resetn of DAC"] + #[inline(always)] + pub fn dac(&mut self) -> DacW<'_, PeripheralResetSpec> { + DacW::new(self, 14) + } + #[doc = "Bit 15 - Resetn of DMA"] + #[inline(always)] + pub fn dma(&mut self) -> DmaW<'_, PeripheralResetSpec> { + DmaW::new(self, 15) + } + #[doc = "Bit 16 - Resetn of EBI"] + #[inline(always)] + pub fn ebi(&mut self) -> EbiW<'_, PeripheralResetSpec> { + EbiW::new(self, 16) + } + #[doc = "Bit 17 - Resetn of Ethernet"] + #[inline(always)] + pub fn eth(&mut self) -> EthW<'_, PeripheralResetSpec> { + EthW::new(self, 17) + } + #[doc = "Bit 18 - Resetn of SpaceWire"] + #[inline(always)] + pub fn spw(&mut self) -> SpwW<'_, PeripheralResetSpec> { + SpwW::new(self, 18) + } + #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"] + #[inline(always)] + pub fn clkgen(&mut self) -> ClkgenW<'_, PeripheralResetSpec> { + ClkgenW::new(self, 19) + } + #[doc = "Bit 20 - Resetn of IRQ Router"] + #[inline(always)] + pub fn irq(&mut self) -> IrqW<'_, PeripheralResetSpec> { + IrqW::new(self, 20) + } + #[doc = "Bit 21 - Resetn of IO CONFIG"] + #[inline(always)] + pub fn ioconfig(&mut self) -> IoconfigW<'_, PeripheralResetSpec> { + IoconfigW::new(self, 21) + } + #[doc = "Bit 22 - Resetn of UTILITY peripheral"] + #[inline(always)] + pub fn utility(&mut self) -> UtilityW<'_, PeripheralResetSpec> { + UtilityW::new(self, 22) + } + #[doc = "Bit 23 - Resetn of WDOG"] + #[inline(always)] + pub fn wdog(&mut self) -> WdogW<'_, PeripheralResetSpec> { + WdogW::new(self, 23) + } + #[doc = "Bit 24 - Resetn of PORTA"] + #[inline(always)] + pub fn porta(&mut self) -> PortaW<'_, PeripheralResetSpec> { + PortaW::new(self, 24) + } + #[doc = "Bit 25 - Resetn of PORTB"] + #[inline(always)] + pub fn portb(&mut self) -> PortbW<'_, PeripheralResetSpec> { + PortbW::new(self, 25) + } + #[doc = "Bit 26 - Resetn of PORTC"] + #[inline(always)] + pub fn portc(&mut self) -> PortcW<'_, PeripheralResetSpec> { + PortcW::new(self, 26) + } + #[doc = "Bit 27 - Resetn of PORTD"] + #[inline(always)] + pub fn portd(&mut self) -> PortdW<'_, PeripheralResetSpec> { + PortdW::new(self, 27) + } + #[doc = "Bit 28 - Resetn of PORTE"] + #[inline(always)] + pub fn porte(&mut self) -> PorteW<'_, PeripheralResetSpec> { + PorteW::new(self, 28) + } + #[doc = "Bit 29 - Resetn of PORTF"] + #[inline(always)] + pub fn portf(&mut self) -> PortfW<'_, PeripheralResetSpec> { + PortfW::new(self, 29) + } + #[doc = "Bit 30 - Resetn of PORTG"] + #[inline(always)] + pub fn portg(&mut self) -> PortgW<'_, PeripheralResetSpec> { + PortgW::new(self, 30) + } +} +#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeripheralResetSpec; +impl crate::RegisterSpec for PeripheralResetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`peripheral_reset::R`](R) reader structure"] +impl crate::Readable for PeripheralResetSpec {} +#[doc = "`write(|w| ..)` method takes [`peripheral_reset::W`](W) writer structure"] +impl crate::Writable for PeripheralResetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PERIPHERAL_RESET to value 0x7f7b_efff"] +impl crate::Resettable for PeripheralResetSpec { + const RESET_VALUE: u32 = 0x7f7b_efff; +} diff --git a/va416xx/va416xx/src/sysconfig/pmu_ctrl.rs b/va416xx/va416xx/src/sysconfig/pmu_ctrl.rs new file mode 100644 index 0000000..868f445 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/pmu_ctrl.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PMU_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `PMU_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LVL_SLCT` reader - Select the POK detect level"] +pub type LvlSlctR = crate::FieldReader; +#[doc = "Field `LVL_SLCT` writer - Select the POK detect level"] +pub type LvlSlctW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Select the POK detect level"] + #[inline(always)] + pub fn lvl_slct(&self) -> LvlSlctR { + LvlSlctR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Select the POK detect level"] + #[inline(always)] + pub fn lvl_slct(&mut self) -> LvlSlctW<'_, PmuCtrlSpec> { + LvlSlctW::new(self, 0) + } +} +#[doc = "PMU Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pmu_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmu_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PmuCtrlSpec; +impl crate::RegisterSpec for PmuCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmu_ctrl::R`](R) reader structure"] +impl crate::Readable for PmuCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`pmu_ctrl::W`](W) writer structure"] +impl crate::Writable for PmuCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PMU_CTRL to value 0"] +impl crate::Resettable for PmuCtrlSpec {} diff --git a/va416xx/va416xx/src/sysconfig/procid.rs b/va416xx/va416xx/src/sysconfig/procid.rs new file mode 100644 index 0000000..05497b9 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/procid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PROCID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ProcidSpec; +impl crate::RegisterSpec for ProcidSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`procid::R`](R) reader structure"] +impl crate::Readable for ProcidSpec {} +#[doc = "`reset()` method sets PROCID to value 0x0400_57e3"] +impl crate::Resettable for ProcidSpec { + const RESET_VALUE: u32 = 0x0400_57e3; +} diff --git a/va416xx/va416xx/src/sysconfig/ram0_mbe.rs b/va416xx/va416xx/src/sysconfig/ram0_mbe.rs new file mode 100644 index 0000000..ea876c8 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/ram0_mbe.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RAM0_MBE` reader"] +pub type R = crate::R; +#[doc = "Register `RAM0_MBE` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - RAM0 Multi Bit Errors"] +pub type CountR = crate::FieldReader; +#[doc = "Field `COUNT` writer - RAM0 Multi Bit Errors"] +pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + pub fn count(&mut self) -> CountW<'_, Ram0MbeSpec> { + CountW::new(self, 0) + } +} +#[doc = "Count of RAM0 EDAC Multi Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram0_mbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram0_mbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ram0MbeSpec; +impl crate::RegisterSpec for Ram0MbeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram0_mbe::R`](R) reader structure"] +impl crate::Readable for Ram0MbeSpec {} +#[doc = "`write(|w| ..)` method takes [`ram0_mbe::W`](W) writer structure"] +impl crate::Writable for Ram0MbeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RAM0_MBE to value 0"] +impl crate::Resettable for Ram0MbeSpec {} diff --git a/va416xx/va416xx/src/sysconfig/ram0_sbe.rs b/va416xx/va416xx/src/sysconfig/ram0_sbe.rs new file mode 100644 index 0000000..5eaddf8 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/ram0_sbe.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RAM0_SBE` reader"] +pub type R = crate::R; +#[doc = "Register `RAM0_SBE` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - RAM0 EDAC Single Bit Errors"] +pub type CountR = crate::FieldReader; +#[doc = "Field `COUNT` writer - RAM0 EDAC Single Bit Errors"] +pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub fn count(&mut self) -> CountW<'_, Ram0SbeSpec> { + CountW::new(self, 0) + } +} +#[doc = "Count of RAM0 EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram0_sbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram0_sbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ram0SbeSpec; +impl crate::RegisterSpec for Ram0SbeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram0_sbe::R`](R) reader structure"] +impl crate::Readable for Ram0SbeSpec {} +#[doc = "`write(|w| ..)` method takes [`ram0_sbe::W`](W) writer structure"] +impl crate::Writable for Ram0SbeSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RAM0_SBE to value 0"] +impl crate::Resettable for Ram0SbeSpec {} diff --git a/va416xx/va416xx/src/sysconfig/refresh_config_h.rs b/va416xx/va416xx/src/sysconfig/refresh_config_h.rs new file mode 100644 index 0000000..fc30ee6 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/refresh_config_h.rs @@ -0,0 +1,49 @@ +#[doc = "Register `REFRESH_CONFIG_H` reader"] +pub type R = crate::R; +#[doc = "Register `REFRESH_CONFIG_H` writer"] +pub type W = crate::W; +#[doc = "Field `DIVCOUNT` reader - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub type DivcountR = crate::FieldReader; +#[doc = "Field `DIVCOUNT` writer - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub type DivcountW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TESTMODE` reader - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] +pub type TestmodeR = crate::FieldReader; +#[doc = "Field `TESTMODE` writer - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] +pub type TestmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&self) -> DivcountR { + DivcountR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] + #[inline(always)] + pub fn testmode(&self) -> TestmodeR { + TestmodeR::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&mut self) -> DivcountW<'_, RefreshConfigHSpec> { + DivcountW::new(self, 0) + } + #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] + #[inline(always)] + pub fn testmode(&mut self) -> TestmodeW<'_, RefreshConfigHSpec> { + TestmodeW::new(self, 30) + } +} +#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RefreshConfigHSpec; +impl crate::RegisterSpec for RefreshConfigHSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`refresh_config_h::R`](R) reader structure"] +impl crate::Readable for RefreshConfigHSpec {} +#[doc = "`write(|w| ..)` method takes [`refresh_config_h::W`](W) writer structure"] +impl crate::Writable for RefreshConfigHSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets REFRESH_CONFIG_H to value 0"] +impl crate::Resettable for RefreshConfigHSpec {} diff --git a/va416xx/va416xx/src/sysconfig/refresh_config_l.rs b/va416xx/va416xx/src/sysconfig/refresh_config_l.rs new file mode 100644 index 0000000..0b46422 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/refresh_config_l.rs @@ -0,0 +1,37 @@ +#[doc = "Register `REFRESH_CONFIG_L` reader"] +pub type R = crate::R; +#[doc = "Register `REFRESH_CONFIG_L` writer"] +pub type W = crate::W; +#[doc = "Field `DIVCOUNT` reader - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub type DivcountR = crate::FieldReader; +#[doc = "Field `DIVCOUNT` writer - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub type DivcountW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&self) -> DivcountR { + DivcountR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&mut self) -> DivcountW<'_, RefreshConfigLSpec> { + DivcountW::new(self, 0) + } +} +#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RefreshConfigLSpec; +impl crate::RegisterSpec for RefreshConfigLSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`refresh_config_l::R`](R) reader structure"] +impl crate::Readable for RefreshConfigLSpec {} +#[doc = "`write(|w| ..)` method takes [`refresh_config_l::W`](W) writer structure"] +impl crate::Writable for RefreshConfigLSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets REFRESH_CONFIG_L to value 0x0f"] +impl crate::Resettable for RefreshConfigLSpec { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/va416xx/va416xx/src/sysconfig/rom_prot.rs b/va416xx/va416xx/src/sysconfig/rom_prot.rs new file mode 100644 index 0000000..50fefab --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/rom_prot.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ROM_PROT` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_PROT` writer"] +pub type W = crate::W; +#[doc = "Field `WREN` reader - ROM Write Enable Bit"] +pub type WrenR = crate::BitReader; +#[doc = "Field `WREN` writer - ROM Write Enable Bit"] +pub type WrenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - ROM Write Enable Bit"] + #[inline(always)] + pub fn wren(&self) -> WrenR { + WrenR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ROM Write Enable Bit"] + #[inline(always)] + pub fn wren(&mut self) -> WrenW<'_, RomProtSpec> { + WrenW::new(self, 0) + } +} +#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomProtSpec; +impl crate::RegisterSpec for RomProtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_prot::R`](R) reader structure"] +impl crate::Readable for RomProtSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_prot::W`](W) writer structure"] +impl crate::Writable for RomProtSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ROM_PROT to value 0"] +impl crate::Resettable for RomProtSpec {} diff --git a/va416xx/va416xx/src/sysconfig/rom_retries.rs b/va416xx/va416xx/src/sysconfig/rom_retries.rs new file mode 100644 index 0000000..b86870a --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/rom_retries.rs @@ -0,0 +1,20 @@ +#[doc = "Register `ROM_RETRIES` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Count of ROM block Retries"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Count of ROM block Retries"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new((self.bits & 0xff) as u8) + } +} +#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomRetriesSpec; +impl crate::RegisterSpec for RomRetriesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_retries::R`](R) reader structure"] +impl crate::Readable for RomRetriesSpec {} +#[doc = "`reset()` method sets ROM_RETRIES to value 0"] +impl crate::Resettable for RomRetriesSpec {} diff --git a/va416xx/va416xx/src/sysconfig/rom_scrub.rs b/va416xx/va416xx/src/sysconfig/rom_scrub.rs new file mode 100644 index 0000000..19de208 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/rom_scrub.rs @@ -0,0 +1,43 @@ +#[doc = "Register `ROM_SCRUB` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_SCRUB` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` reader - Counter divide value"] +pub type ValueR = crate::FieldReader; +#[doc = "Field `VALUE` writer - Counter divide value"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `RESET` writer - Reset Counter"] +pub type ResetW<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&mut self) -> ValueW<'_, RomScrubSpec> { + ValueW::new(self, 0) + } + #[doc = "Bit 31 - Reset Counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW<'_, RomScrubSpec> { + ResetW::new(self, 31) + } +} +#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomScrubSpec; +impl crate::RegisterSpec for RomScrubSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_scrub::R`](R) reader structure"] +impl crate::Readable for RomScrubSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_scrub::W`](W) writer structure"] +impl crate::Writable for RomScrubSpec { + type Safety = crate::Unsafe; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000; +} +#[doc = "`reset()` method sets ROM_SCRUB to value 0"] +impl crate::Resettable for RomScrubSpec {} diff --git a/va416xx/va416xx/src/sysconfig/rst_stat.rs b/va416xx/va416xx/src/sysconfig/rst_stat.rs new file mode 100644 index 0000000..fa2f66f --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/rst_stat.rs @@ -0,0 +1,98 @@ +#[doc = "Register `RST_STAT` reader"] +pub type R = crate::R; +#[doc = "Register `RST_STAT` writer"] +pub type W = crate::W; +#[doc = "Field `POR` reader - Power On Reset Status"] +pub type PorR = crate::BitReader; +#[doc = "Field `POR` writer - Power On Reset Status"] +pub type PorW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTRST` reader - External Reset Status"] +pub type ExtrstR = crate::BitReader; +#[doc = "Field `EXTRST` writer - External Reset Status"] +pub type ExtrstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"] +pub type SysrstreqR = crate::BitReader; +#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"] +pub type SysrstreqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"] +pub type LookupR = crate::BitReader; +#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"] +pub type LookupW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"] +pub type WatchdogR = crate::BitReader; +#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"] +pub type WatchdogW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEMERR` reader - Memory Error Reset Status"] +pub type MemerrR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&self) -> PorR { + PorR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&self) -> ExtrstR { + ExtrstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&self) -> SysrstreqR { + SysrstreqR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&self) -> LookupR { + LookupR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&self) -> WatchdogR { + WatchdogR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Memory Error Reset Status"] + #[inline(always)] + pub fn memerr(&self) -> MemerrR { + MemerrR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&mut self) -> PorW<'_, RstStatSpec> { + PorW::new(self, 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&mut self) -> ExtrstW<'_, RstStatSpec> { + ExtrstW::new(self, 1) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&mut self) -> SysrstreqW<'_, RstStatSpec> { + SysrstreqW::new(self, 2) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&mut self) -> LookupW<'_, RstStatSpec> { + LookupW::new(self, 3) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&mut self) -> WatchdogW<'_, RstStatSpec> { + WatchdogW::new(self, 4) + } +} +#[doc = "System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RstStatSpec; +impl crate::RegisterSpec for RstStatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_stat::R`](R) reader structure"] +impl crate::Readable for RstStatSpec {} +#[doc = "`write(|w| ..)` method takes [`rst_stat::W`](W) writer structure"] +impl crate::Writable for RstStatSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RST_STAT to value 0"] +impl crate::Resettable for RstStatSpec {} diff --git a/va416xx/va416xx/src/sysconfig/spw_m4_ctrl.rs b/va416xx/va416xx/src/sysconfig/spw_m4_ctrl.rs new file mode 100644 index 0000000..966a733 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/spw_m4_ctrl.rs @@ -0,0 +1,65 @@ +#[doc = "Register `SPW_M4_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPW_M4_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `REG_WR_KEY` reader - Fuse-analog register writes enabled when key = 0xfeed"] +pub type RegWrKeyR = crate::FieldReader; +#[doc = "Field `REG_WR_KEY` writer - Fuse-analog register writes enabled when key = 0xfeed"] +pub type RegWrKeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPW_PAD_EN` reader - SPW pad enable"] +pub type SpwPadEnR = crate::BitReader; +#[doc = "Field `SPW_PAD_EN` writer - SPW pad enable"] +pub type SpwPadEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LREN` reader - Lockup reset enable"] +pub type LrenR = crate::BitReader; +#[doc = "Field `LREN` writer - Lockup reset enable"] +pub type LrenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"] + #[inline(always)] + pub fn reg_wr_key(&self) -> RegWrKeyR { + RegWrKeyR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - SPW pad enable"] + #[inline(always)] + pub fn spw_pad_en(&self) -> SpwPadEnR { + SpwPadEnR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Lockup reset enable"] + #[inline(always)] + pub fn lren(&self) -> LrenR { + LrenR::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"] + #[inline(always)] + pub fn reg_wr_key(&mut self) -> RegWrKeyW<'_, SpwM4CtrlSpec> { + RegWrKeyW::new(self, 0) + } + #[doc = "Bit 16 - SPW pad enable"] + #[inline(always)] + pub fn spw_pad_en(&mut self) -> SpwPadEnW<'_, SpwM4CtrlSpec> { + SpwPadEnW::new(self, 16) + } + #[doc = "Bit 17 - Lockup reset enable"] + #[inline(always)] + pub fn lren(&mut self) -> LrenW<'_, SpwM4CtrlSpec> { + LrenW::new(self, 17) + } +} +#[doc = "SPW M4 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spw_m4_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spw_m4_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpwM4CtrlSpec; +impl crate::RegisterSpec for SpwM4CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spw_m4_ctrl::R`](R) reader structure"] +impl crate::Readable for SpwM4CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`spw_m4_ctrl::W`](W) writer structure"] +impl crate::Writable for SpwM4CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SPW_M4_CTRL to value 0x0003_0000"] +impl crate::Resettable for SpwM4CtrlSpec { + const RESET_VALUE: u32 = 0x0003_0000; +} diff --git a/va416xx/va416xx/src/sysconfig/sw_clkdiv10.rs b/va416xx/va416xx/src/sysconfig/sw_clkdiv10.rs new file mode 100644 index 0000000..a1aa6d6 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/sw_clkdiv10.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SW_CLKDIV10` reader"] +pub type R = crate::R; +#[doc = "Register `SW_CLKDIV10` writer"] +pub type W = crate::W; +#[doc = "Field `SW_CLKDIV10` reader - Defines the initial value for the SpW clock, defaults to divide by ten"] +pub type SwClkdiv10R = crate::FieldReader; +#[doc = "Field `SW_CLKDIV10` writer - Defines the initial value for the SpW clock, defaults to divide by ten"] +pub type SwClkdiv10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"] + #[inline(always)] + pub fn sw_clkdiv10(&self) -> SwClkdiv10R { + SwClkdiv10R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"] + #[inline(always)] + pub fn sw_clkdiv10(&mut self) -> SwClkdiv10W<'_, SwClkdiv10Spec> { + SwClkdiv10W::new(self, 0) + } +} +#[doc = "Initial SpW Clock Divider Value\n\nYou can [`read`](crate::Reg::read) this register and get [`sw_clkdiv10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_clkdiv10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwClkdiv10Spec; +impl crate::RegisterSpec for SwClkdiv10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_clkdiv10::R`](R) reader structure"] +impl crate::Readable for SwClkdiv10Spec {} +#[doc = "`write(|w| ..)` method takes [`sw_clkdiv10::W`](W) writer structure"] +impl crate::Writable for SwClkdiv10Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SW_CLKDIV10 to value 0x09"] +impl crate::Resettable for SwClkdiv10Spec { + const RESET_VALUE: u32 = 0x09; +} diff --git a/va416xx/va416xx/src/sysconfig/tim_clk_enable.rs b/va416xx/va416xx/src/sysconfig/tim_clk_enable.rs new file mode 100644 index 0000000..53c9a2a --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/tim_clk_enable.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TIM_CLK_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `TIM_CLK_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `TIMERS` reader - Clock enable of a given TIMER"] +pub type TimersR = crate::FieldReader; +#[doc = "Field `TIMERS` writer - Clock enable of a given TIMER"] +pub type TimersW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Clock enable of a given TIMER"] + #[inline(always)] + pub fn timers(&self) -> TimersR { + TimersR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Clock enable of a given TIMER"] + #[inline(always)] + pub fn timers(&mut self) -> TimersW<'_, TimClkEnableSpec> { + TimersW::new(self, 0) + } +} +#[doc = "TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimClkEnableSpec; +impl crate::RegisterSpec for TimClkEnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tim_clk_enable::R`](R) reader structure"] +impl crate::Readable for TimClkEnableSpec {} +#[doc = "`write(|w| ..)` method takes [`tim_clk_enable::W`](W) writer structure"] +impl crate::Writable for TimClkEnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIM_CLK_ENABLE to value 0"] +impl crate::Resettable for TimClkEnableSpec {} diff --git a/va416xx/va416xx/src/sysconfig/tim_reset.rs b/va416xx/va416xx/src/sysconfig/tim_reset.rs new file mode 100644 index 0000000..4f378f9 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/tim_reset.rs @@ -0,0 +1,37 @@ +#[doc = "Register `TIM_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `TIM_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `TIM_RESET` reader - Reset of a given TIMER"] +pub type TimResetR = crate::FieldReader; +#[doc = "Field `TIM_RESET` writer - Reset of a given TIMER"] +pub type TimResetW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Reset of a given TIMER"] + #[inline(always)] + pub fn tim_reset(&self) -> TimResetR { + TimResetR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Reset of a given TIMER"] + #[inline(always)] + pub fn tim_reset(&mut self) -> TimResetW<'_, TimResetSpec> { + TimResetW::new(self, 0) + } +} +#[doc = "TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimResetSpec; +impl crate::RegisterSpec for TimResetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tim_reset::R`](R) reader structure"] +impl crate::Readable for TimResetSpec {} +#[doc = "`write(|w| ..)` method takes [`tim_reset::W`](W) writer structure"] +impl crate::Writable for TimResetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TIM_RESET to value 0xffff_ffff"] +impl crate::Resettable for TimResetSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va416xx/va416xx/src/sysconfig/wakeup_cnt.rs b/va416xx/va416xx/src/sysconfig/wakeup_cnt.rs new file mode 100644 index 0000000..324af64 --- /dev/null +++ b/va416xx/va416xx/src/sysconfig/wakeup_cnt.rs @@ -0,0 +1,51 @@ +#[doc = "Register `WAKEUP_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `WAKEUP_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `WKUP_CNT` reader - Used to set a time to wake up the processor after the device has been put in a low power state"] +pub type WkupCntR = crate::FieldReader; +#[doc = "Field `WKUP_CNT` writer - Used to set a time to wake up the processor after the device has been put in a low power state"] +pub type WkupCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CNTSTRT` reader - Launch SLP mode in analog block"] +pub type CntstrtR = crate::BitReader; +#[doc = "Field `CNTSTRT` writer - Launch SLP mode in analog block"] +pub type CntstrtW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"] + #[inline(always)] + pub fn wkup_cnt(&self) -> WkupCntR { + WkupCntR::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Launch SLP mode in analog block"] + #[inline(always)] + pub fn cntstrt(&self) -> CntstrtR { + CntstrtR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"] + #[inline(always)] + pub fn wkup_cnt(&mut self) -> WkupCntW<'_, WakeupCntSpec> { + WkupCntW::new(self, 0) + } + #[doc = "Bit 3 - Launch SLP mode in analog block"] + #[inline(always)] + pub fn cntstrt(&mut self) -> CntstrtW<'_, WakeupCntSpec> { + CntstrtW::new(self, 3) + } +} +#[doc = "Wakeup Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeup_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeup_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WakeupCntSpec; +impl crate::RegisterSpec for WakeupCntSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wakeup_cnt::R`](R) reader structure"] +impl crate::Readable for WakeupCntSpec {} +#[doc = "`write(|w| ..)` method takes [`wakeup_cnt::W`](W) writer structure"] +impl crate::Writable for WakeupCntSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WAKEUP_CNT to value 0x07"] +impl crate::Resettable for WakeupCntSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/va416xx/va416xx/src/tim0.rs b/va416xx/va416xx/src/tim0.rs new file mode 100644 index 0000000..5da31f8 --- /dev/null +++ b/va416xx/va416xx/src/tim0.rs @@ -0,0 +1,132 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + rst_value: RstValue, + cnt_value: CntValue, + enable: Enable, + csd_ctrl: CsdCtrl, + cascade0: Cascade0, + cascade1: Cascade1, + cascade2: Cascade2, + _reserved_8_pwm_value: [u8; 0x04], + pwmb_value: PwmbValue, + _reserved10: [u8; 0x03d4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - The value that counter start from after reaching 0."] + #[inline(always)] + pub const fn rst_value(&self) -> &RstValue { + &self.rst_value + } + #[doc = "0x08 - The current value of the counter"] + #[inline(always)] + pub const fn cnt_value(&self) -> &CntValue { + &self.cnt_value + } + #[doc = "0x0c - Alternate access to the Counter ENABLE bit in the CTRL Register"] + #[inline(always)] + pub const fn enable(&self) -> &Enable { + &self.enable + } + #[doc = "0x10 - The Cascade Control Register. Controls the counter external enable signals"] + #[inline(always)] + pub const fn csd_ctrl(&self) -> &CsdCtrl { + &self.csd_ctrl + } + #[doc = "0x14 - Cascade Enable Selection"] + #[inline(always)] + pub const fn cascade0(&self) -> &Cascade0 { + &self.cascade0 + } + #[doc = "0x18 - Cascade Enable Selection"] + #[inline(always)] + pub const fn cascade1(&self) -> &Cascade1 { + &self.cascade1 + } + #[doc = "0x1c - Cascade Enable Selection"] + #[inline(always)] + pub const fn cascade2(&self) -> &Cascade2 { + &self.cascade2 + } + #[doc = "0x20 - The Pulse Width Modulation ValueA"] + #[inline(always)] + pub const fn pwma_value(&self) -> &PwmaValue { + unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } + } + #[doc = "0x20 - The Pulse Width Modulation Value"] + #[inline(always)] + pub const fn pwm_value(&self) -> &PwmValue { + unsafe { &*core::ptr::from_ref(self).cast::().add(32).cast() } + } + #[doc = "0x24 - The Pulse Width Modulation ValueB"] + #[inline(always)] + pub const fn pwmb_value(&self) -> &PwmbValue { + &self.pwmb_value + } + #[doc = "0x3fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "RST_VALUE (rw) register accessor: The value that counter start from after reaching 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_value`] module"] +#[doc(alias = "RST_VALUE")] +pub type RstValue = crate::Reg; +#[doc = "The value that counter start from after reaching 0."] +pub mod rst_value; +#[doc = "CNT_VALUE (rw) register accessor: The current value of the counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt_value`] module"] +#[doc(alias = "CNT_VALUE")] +pub type CntValue = crate::Reg; +#[doc = "The current value of the counter"] +pub mod cnt_value; +#[doc = "ENABLE (rw) register accessor: Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] +#[doc(alias = "ENABLE")] +pub type Enable = crate::Reg; +#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register"] +pub mod enable; +#[doc = "CSD_CTRL (rw) register accessor: The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::Reg::read) this register and get [`csd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csd_ctrl`] module"] +#[doc(alias = "CSD_CTRL")] +pub type CsdCtrl = crate::Reg; +#[doc = "The Cascade Control Register. Controls the counter external enable signals"] +pub mod csd_ctrl; +#[doc = "CASCADE0 (rw) register accessor: Cascade Enable Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`cascade0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cascade0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cascade0`] module"] +#[doc(alias = "CASCADE0")] +pub type Cascade0 = crate::Reg; +#[doc = "Cascade Enable Selection"] +pub mod cascade0; +pub use cascade0 as cascade1; +pub use cascade0 as cascade2; +pub use Cascade0 as Cascade1; +pub use Cascade0 as Cascade2; +#[doc = "PWM_VALUE (rw) register accessor: The Pulse Width Modulation Value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_value`] module"] +#[doc(alias = "PWM_VALUE")] +pub type PwmValue = crate::Reg; +#[doc = "The Pulse Width Modulation Value"] +pub mod pwm_value; +#[doc = "PWMA_VALUE (rw) register accessor: The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::Reg::read) this register and get [`pwma_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwma_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwma_value`] module"] +#[doc(alias = "PWMA_VALUE")] +pub type PwmaValue = crate::Reg; +#[doc = "The Pulse Width Modulation ValueA"] +pub mod pwma_value; +#[doc = "PWMB_VALUE (rw) register accessor: The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmb_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmb_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmb_value`] module"] +#[doc(alias = "PWMB_VALUE")] +pub type PwmbValue = crate::Reg; +#[doc = "The Pulse Width Modulation ValueB"] +pub mod pwmb_value; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/tim0/cascade0.rs b/va416xx/va416xx/src/tim0/cascade0.rs new file mode 100644 index 0000000..216d7bd --- /dev/null +++ b/va416xx/va416xx/src/tim0/cascade0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CASCADE0` reader"] +pub type R = crate::R; +#[doc = "Register `CASCADE0` writer"] +pub type W = crate::W; +#[doc = "Field `CASSEL` reader - Cascade Selection"] +pub type CasselR = crate::FieldReader; +#[doc = "Field `CASSEL` writer - Cascade Selection"] +pub type CasselW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&self) -> CasselR { + CasselR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&mut self) -> CasselW<'_, Cascade0Spec> { + CasselW::new(self, 0) + } +} +#[doc = "Cascade Enable Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`cascade0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cascade0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cascade0Spec; +impl crate::RegisterSpec for Cascade0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cascade0::R`](R) reader structure"] +impl crate::Readable for Cascade0Spec {} +#[doc = "`write(|w| ..)` method takes [`cascade0::W`](W) writer structure"] +impl crate::Writable for Cascade0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CASCADE0 to value 0"] +impl crate::Resettable for Cascade0Spec {} diff --git a/va416xx/va416xx/src/tim0/cnt_value.rs b/va416xx/va416xx/src/tim0/cnt_value.rs new file mode 100644 index 0000000..39350ff --- /dev/null +++ b/va416xx/va416xx/src/tim0/cnt_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `CNT_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `CNT_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The current value of the counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CntValueSpec; +impl crate::RegisterSpec for CntValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnt_value::R`](R) reader structure"] +impl crate::Readable for CntValueSpec {} +#[doc = "`write(|w| ..)` method takes [`cnt_value::W`](W) writer structure"] +impl crate::Writable for CntValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CNT_VALUE to value 0"] +impl crate::Resettable for CntValueSpec {} diff --git a/va416xx/va416xx/src/tim0/csd_ctrl.rs b/va416xx/va416xx/src/tim0/csd_ctrl.rs new file mode 100644 index 0000000..57f9064 --- /dev/null +++ b/va416xx/va416xx/src/tim0/csd_ctrl.rs @@ -0,0 +1,161 @@ +#[doc = "Register `CSD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CSD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CSDEN0` reader - Cascade 0 Enable"] +pub type Csden0R = crate::BitReader; +#[doc = "Field `CSDEN0` writer - Cascade 0 Enable"] +pub type Csden0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDINV0` reader - Cascade 0 Invert"] +pub type Csdinv0R = crate::BitReader; +#[doc = "Field `CSDINV0` writer - Cascade 0 Invert"] +pub type Csdinv0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDEN1` reader - Cascade 1 Enable"] +pub type Csden1R = crate::BitReader; +#[doc = "Field `CSDEN1` writer - Cascade 1 Enable"] +pub type Csden1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDINV1` reader - Cascade 1 Invert"] +pub type Csdinv1R = crate::BitReader; +#[doc = "Field `CSDINV1` writer - Cascade 1 Invert"] +pub type Csdinv1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCASOP` reader - Dual Cascade Operation (0:AND, 1:OR)"] +pub type DcasopR = crate::BitReader; +#[doc = "Field `DCASOP` writer - Dual Cascade Operation (0:AND, 1:OR)"] +pub type DcasopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDTRG0` reader - Cascade 0 Enabled as Trigger"] +pub type Csdtrg0R = crate::BitReader; +#[doc = "Field `CSDTRG0` writer - Cascade 0 Enabled as Trigger"] +pub type Csdtrg0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDTRG1` reader - Cascade 1 Enabled as Trigger"] +pub type Csdtrg1R = crate::BitReader; +#[doc = "Field `CSDTRG1` writer - Cascade 1 Enabled as Trigger"] +pub type Csdtrg1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDEN2` reader - Cascade 2 Enable"] +pub type Csden2R = crate::BitReader; +#[doc = "Field `CSDEN2` writer - Cascade 2 Enable"] +pub type Csden2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDINV2` reader - Cascade 2 Invert"] +pub type Csdinv2R = crate::BitReader; +#[doc = "Field `CSDINV2` writer - Cascade 2 Invert"] +pub type Csdinv2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDTRG2` reader - Cascade 2 Trigger mode"] +pub type Csdtrg2R = crate::BitReader; +#[doc = "Field `CSDTRG2` writer - Cascade 2 Trigger mode"] +pub type Csdtrg2W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Cascade 0 Enable"] + #[inline(always)] + pub fn csden0(&self) -> Csden0R { + Csden0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Cascade 0 Invert"] + #[inline(always)] + pub fn csdinv0(&self) -> Csdinv0R { + Csdinv0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Cascade 1 Enable"] + #[inline(always)] + pub fn csden1(&self) -> Csden1R { + Csden1R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Cascade 1 Invert"] + #[inline(always)] + pub fn csdinv1(&self) -> Csdinv1R { + Csdinv1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"] + #[inline(always)] + pub fn dcasop(&self) -> DcasopR { + DcasopR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg0(&self) -> Csdtrg0R { + Csdtrg0R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg1(&self) -> Csdtrg1R { + Csdtrg1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Cascade 2 Enable"] + #[inline(always)] + pub fn csden2(&self) -> Csden2R { + Csden2R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Cascade 2 Invert"] + #[inline(always)] + pub fn csdinv2(&self) -> Csdinv2R { + Csdinv2R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Cascade 2 Trigger mode"] + #[inline(always)] + pub fn csdtrg2(&self) -> Csdtrg2R { + Csdtrg2R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cascade 0 Enable"] + #[inline(always)] + pub fn csden0(&mut self) -> Csden0W<'_, CsdCtrlSpec> { + Csden0W::new(self, 0) + } + #[doc = "Bit 1 - Cascade 0 Invert"] + #[inline(always)] + pub fn csdinv0(&mut self) -> Csdinv0W<'_, CsdCtrlSpec> { + Csdinv0W::new(self, 1) + } + #[doc = "Bit 2 - Cascade 1 Enable"] + #[inline(always)] + pub fn csden1(&mut self) -> Csden1W<'_, CsdCtrlSpec> { + Csden1W::new(self, 2) + } + #[doc = "Bit 3 - Cascade 1 Invert"] + #[inline(always)] + pub fn csdinv1(&mut self) -> Csdinv1W<'_, CsdCtrlSpec> { + Csdinv1W::new(self, 3) + } + #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"] + #[inline(always)] + pub fn dcasop(&mut self) -> DcasopW<'_, CsdCtrlSpec> { + DcasopW::new(self, 4) + } + #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg0(&mut self) -> Csdtrg0W<'_, CsdCtrlSpec> { + Csdtrg0W::new(self, 6) + } + #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg1(&mut self) -> Csdtrg1W<'_, CsdCtrlSpec> { + Csdtrg1W::new(self, 7) + } + #[doc = "Bit 8 - Cascade 2 Enable"] + #[inline(always)] + pub fn csden2(&mut self) -> Csden2W<'_, CsdCtrlSpec> { + Csden2W::new(self, 8) + } + #[doc = "Bit 9 - Cascade 2 Invert"] + #[inline(always)] + pub fn csdinv2(&mut self) -> Csdinv2W<'_, CsdCtrlSpec> { + Csdinv2W::new(self, 9) + } + #[doc = "Bit 10 - Cascade 2 Trigger mode"] + #[inline(always)] + pub fn csdtrg2(&mut self) -> Csdtrg2W<'_, CsdCtrlSpec> { + Csdtrg2W::new(self, 10) + } +} +#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::Reg::read) this register and get [`csd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CsdCtrlSpec; +impl crate::RegisterSpec for CsdCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`csd_ctrl::R`](R) reader structure"] +impl crate::Readable for CsdCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`csd_ctrl::W`](W) writer structure"] +impl crate::Writable for CsdCtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CSD_CTRL to value 0"] +impl crate::Resettable for CsdCtrlSpec {} diff --git a/va416xx/va416xx/src/tim0/ctrl.rs b/va416xx/va416xx/src/tim0/ctrl.rs new file mode 100644 index 0000000..bab9535 --- /dev/null +++ b/va416xx/va416xx/src/tim0/ctrl.rs @@ -0,0 +1,248 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Counter Enable"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Counter Enable"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE` reader - Counter Active"] +pub type ActiveR = crate::BitReader; +#[doc = "Field `AUTO_DISABLE` reader - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] +pub type AutoDisableR = crate::BitReader; +#[doc = "Field `AUTO_DISABLE` writer - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] +pub type AutoDisableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTO_DEACTIVATE` reader - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] +pub type AutoDeactivateR = crate::BitReader; +#[doc = "Field `AUTO_DEACTIVATE` writer - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] +pub type AutoDeactivateW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_ENB` reader - Interrupt Enable"] +pub type IrqEnbR = crate::BitReader; +#[doc = "Field `IRQ_ENB` writer - Interrupt Enable"] +pub type IrqEnbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Counter Status Selection\n\nValue on reset: 0"] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum StatusSel { + #[doc = "0: Single cycle pulse when the counter reaches 0"] + Done = 0, + #[doc = "1: Returns the counter ACTIVE bit"] + Active = 1, + #[doc = "2: Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + Toggle = 2, + #[doc = "3: Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + Pwma = 3, + #[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + Pwmb = 4, + #[doc = "5: Returns the counter ENABLED bit"] + Enabled = 5, + #[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + PwmaActive = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: StatusSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for StatusSel { + type Ux = u8; +} +impl crate::IsEnum for StatusSel {} +#[doc = "Field `STATUS_SEL` reader - Counter Status Selection"] +pub type StatusSelR = crate::FieldReader; +impl StatusSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(StatusSel::Done), + 1 => Some(StatusSel::Active), + 2 => Some(StatusSel::Toggle), + 3 => Some(StatusSel::Pwma), + 4 => Some(StatusSel::Pwmb), + 5 => Some(StatusSel::Enabled), + 6 => Some(StatusSel::PwmaActive), + _ => None, + } + } + #[doc = "Single cycle pulse when the counter reaches 0"] + #[inline(always)] + pub fn is_done(&self) -> bool { + *self == StatusSel::Done + } + #[doc = "Returns the counter ACTIVE bit"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == StatusSel::Active + } + #[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + *self == StatusSel::Toggle + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + #[inline(always)] + pub fn is_pwma(&self) -> bool { + *self == StatusSel::Pwma + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + #[inline(always)] + pub fn is_pwmb(&self) -> bool { + *self == StatusSel::Pwmb + } + #[doc = "Returns the counter ENABLED bit"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == StatusSel::Enabled + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + #[inline(always)] + pub fn is_pwma_active(&self) -> bool { + *self == StatusSel::PwmaActive + } +} +#[doc = "Field `STATUS_SEL` writer - Counter Status Selection"] +pub type StatusSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, StatusSel>; +impl<'a, REG> StatusSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single cycle pulse when the counter reaches 0"] + #[inline(always)] + pub fn done(self) -> &'a mut crate::W { + self.variant(StatusSel::Done) + } + #[doc = "Returns the counter ACTIVE bit"] + #[inline(always)] + pub fn active(self) -> &'a mut crate::W { + self.variant(StatusSel::Active) + } + #[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + #[inline(always)] + pub fn toggle(self) -> &'a mut crate::W { + self.variant(StatusSel::Toggle) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + #[inline(always)] + pub fn pwma(self) -> &'a mut crate::W { + self.variant(StatusSel::Pwma) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + #[inline(always)] + pub fn pwmb(self) -> &'a mut crate::W { + self.variant(StatusSel::Pwmb) + } + #[doc = "Returns the counter ENABLED bit"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(StatusSel::Enabled) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + #[inline(always)] + pub fn pwma_active(self) -> &'a mut crate::W { + self.variant(StatusSel::PwmaActive) + } +} +#[doc = "Field `STATUS_INV` reader - Invert the Output Status"] +pub type StatusInvR = crate::BitReader; +#[doc = "Field `STATUS_INV` writer - Invert the Output Status"] +pub type StatusInvW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REQ_STOP` reader - Stop Request"] +pub type ReqStopR = crate::BitReader; +#[doc = "Field `REQ_STOP` writer - Stop Request"] +pub type ReqStopW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Counter Active"] + #[inline(always)] + pub fn active(&self) -> ActiveR { + ActiveR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_disable(&self) -> AutoDisableR { + AutoDisableR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_deactivate(&self) -> AutoDeactivateR { + AutoDeactivateR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt Enable"] + #[inline(always)] + pub fn irq_enb(&self) -> IrqEnbR { + IrqEnbR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - Counter Status Selection"] + #[inline(always)] + pub fn status_sel(&self) -> StatusSelR { + StatusSelR::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 8 - Invert the Output Status"] + #[inline(always)] + pub fn status_inv(&self) -> StatusInvR { + StatusInvR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Stop Request"] + #[inline(always)] + pub fn req_stop(&self) -> ReqStopR { + ReqStopR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, CtrlSpec> { + EnableW::new(self, 0) + } + #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_disable(&mut self) -> AutoDisableW<'_, CtrlSpec> { + AutoDisableW::new(self, 2) + } + #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_deactivate(&mut self) -> AutoDeactivateW<'_, CtrlSpec> { + AutoDeactivateW::new(self, 3) + } + #[doc = "Bit 4 - Interrupt Enable"] + #[inline(always)] + pub fn irq_enb(&mut self) -> IrqEnbW<'_, CtrlSpec> { + IrqEnbW::new(self, 4) + } + #[doc = "Bits 5:7 - Counter Status Selection"] + #[inline(always)] + pub fn status_sel(&mut self) -> StatusSelW<'_, CtrlSpec> { + StatusSelW::new(self, 5) + } + #[doc = "Bit 8 - Invert the Output Status"] + #[inline(always)] + pub fn status_inv(&mut self) -> StatusInvW<'_, CtrlSpec> { + StatusInvW::new(self, 8) + } + #[doc = "Bit 9 - Stop Request"] + #[inline(always)] + pub fn req_stop(&mut self) -> ReqStopW<'_, CtrlSpec> { + ReqStopW::new(self, 9) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/va416xx/va416xx/src/tim0/enable.rs b/va416xx/va416xx/src/tim0/enable.rs new file mode 100644 index 0000000..f142b05 --- /dev/null +++ b/va416xx/va416xx/src/tim0/enable.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Counter Enable"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Counter Enable"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, EnableSpec> { + EnableW::new(self, 0) + } +} +#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EnableSpec; +impl crate::RegisterSpec for EnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`enable::R`](R) reader structure"] +impl crate::Readable for EnableSpec {} +#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"] +impl crate::Writable for EnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for EnableSpec {} diff --git a/va416xx/va416xx/src/tim0/perid.rs b/va416xx/va416xx/src/tim0/perid.rs new file mode 100644 index 0000000..c1a7193 --- /dev/null +++ b/va416xx/va416xx/src/tim0/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0211_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0211_07e9; +} diff --git a/va416xx/va416xx/src/tim0/pwm_value.rs b/va416xx/va416xx/src/tim0/pwm_value.rs new file mode 100644 index 0000000..6ac3389 --- /dev/null +++ b/va416xx/va416xx/src/tim0/pwm_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `PWM_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `PWM_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The Pulse Width Modulation Value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmValueSpec; +impl crate::RegisterSpec for PwmValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm_value::R`](R) reader structure"] +impl crate::Readable for PwmValueSpec {} +#[doc = "`write(|w| ..)` method takes [`pwm_value::W`](W) writer structure"] +impl crate::Writable for PwmValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWM_VALUE to value 0"] +impl crate::Resettable for PwmValueSpec {} diff --git a/va416xx/va416xx/src/tim0/pwma_value.rs b/va416xx/va416xx/src/tim0/pwma_value.rs new file mode 100644 index 0000000..ada6a2f --- /dev/null +++ b/va416xx/va416xx/src/tim0/pwma_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `PWMA_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `PWMA_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::Reg::read) this register and get [`pwma_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwma_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmaValueSpec; +impl crate::RegisterSpec for PwmaValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwma_value::R`](R) reader structure"] +impl crate::Readable for PwmaValueSpec {} +#[doc = "`write(|w| ..)` method takes [`pwma_value::W`](W) writer structure"] +impl crate::Writable for PwmaValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWMA_VALUE to value 0"] +impl crate::Resettable for PwmaValueSpec {} diff --git a/va416xx/va416xx/src/tim0/pwmb_value.rs b/va416xx/va416xx/src/tim0/pwmb_value.rs new file mode 100644 index 0000000..6f09486 --- /dev/null +++ b/va416xx/va416xx/src/tim0/pwmb_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `PWMB_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `PWMB_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmb_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmb_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmbValueSpec; +impl crate::RegisterSpec for PwmbValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwmb_value::R`](R) reader structure"] +impl crate::Readable for PwmbValueSpec {} +#[doc = "`write(|w| ..)` method takes [`pwmb_value::W`](W) writer structure"] +impl crate::Writable for PwmbValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets PWMB_VALUE to value 0"] +impl crate::Resettable for PwmbValueSpec {} diff --git a/va416xx/va416xx/src/tim0/rst_value.rs b/va416xx/va416xx/src/tim0/rst_value.rs new file mode 100644 index 0000000..69d5109 --- /dev/null +++ b/va416xx/va416xx/src/tim0/rst_value.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RST_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `RST_VALUE` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The value that counter start from after reaching 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RstValueSpec; +impl crate::RegisterSpec for RstValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_value::R`](R) reader structure"] +impl crate::Readable for RstValueSpec {} +#[doc = "`write(|w| ..)` method takes [`rst_value::W`](W) writer structure"] +impl crate::Writable for RstValueSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RST_VALUE to value 0"] +impl crate::Resettable for RstValueSpec {} diff --git a/va416xx/va416xx/src/trng.rs b/va416xx/va416xx/src/trng.rs new file mode 100644 index 0000000..45daa34 --- /dev/null +++ b/va416xx/va416xx/src/trng.rs @@ -0,0 +1,220 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x0100], + imr: Imr, + isr: Isr, + icr: Icr, + config: Config, + valid: Valid, + ehr_data0: EhrData0, + ehr_data1: EhrData1, + ehr_data2: EhrData2, + ehr_data3: EhrData3, + ehr_data4: EhrData4, + ehr_data5: EhrData5, + rnd_source_enable: RndSourceEnable, + sample_cnt1: SampleCnt1, + autocorr_statistic: AutocorrStatistic, + debug_control: DebugControl, + _reserved15: [u8; 0x04], + sw_reset: SwReset, + _reserved16: [u8; 0x74], + busy: Busy, + rst_bits_counter: RstBitsCounter, + _reserved18: [u8; 0x20], + bist_cntr0: BistCntr0, + bist_cntr1: BistCntr1, + bist_cntr2: BistCntr2, +} +impl RegisterBlock { + #[doc = "0x100 - Interrupt Mask Register"] + #[inline(always)] + pub const fn imr(&self) -> &Imr { + &self.imr + } + #[doc = "0x104 - Interrupt Status Register"] + #[inline(always)] + pub const fn isr(&self) -> &Isr { + &self.isr + } + #[doc = "0x108 - Interrupt Clear Register"] + #[inline(always)] + pub const fn icr(&self) -> &Icr { + &self.icr + } + #[doc = "0x10c - Configuration Register"] + #[inline(always)] + pub const fn config(&self) -> &Config { + &self.config + } + #[doc = "0x110 - Valid Register"] + #[inline(always)] + pub const fn valid(&self) -> &Valid { + &self.valid + } + #[doc = "0x114 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data0(&self) -> &EhrData0 { + &self.ehr_data0 + } + #[doc = "0x118 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data1(&self) -> &EhrData1 { + &self.ehr_data1 + } + #[doc = "0x11c - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data2(&self) -> &EhrData2 { + &self.ehr_data2 + } + #[doc = "0x120 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data3(&self) -> &EhrData3 { + &self.ehr_data3 + } + #[doc = "0x124 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data4(&self) -> &EhrData4 { + &self.ehr_data4 + } + #[doc = "0x128 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data5(&self) -> &EhrData5 { + &self.ehr_data5 + } + #[doc = "0x12c - Random Source Enable Register"] + #[inline(always)] + pub const fn rnd_source_enable(&self) -> &RndSourceEnable { + &self.rnd_source_enable + } + #[doc = "0x130 - Section TBD"] + #[inline(always)] + pub const fn sample_cnt1(&self) -> &SampleCnt1 { + &self.sample_cnt1 + } + #[doc = "0x134 - Auto-correlator Statistic Register"] + #[inline(always)] + pub const fn autocorr_statistic(&self) -> &AutocorrStatistic { + &self.autocorr_statistic + } + #[doc = "0x138 - Section TBD"] + #[inline(always)] + pub const fn debug_control(&self) -> &DebugControl { + &self.debug_control + } + #[doc = "0x140 - Reset Register"] + #[inline(always)] + pub const fn sw_reset(&self) -> &SwReset { + &self.sw_reset + } + #[doc = "0x1b8 - Busy Register"] + #[inline(always)] + pub const fn busy(&self) -> &Busy { + &self.busy + } + #[doc = "0x1bc - Reset Bits Counter Register"] + #[inline(always)] + pub const fn rst_bits_counter(&self) -> &RstBitsCounter { + &self.rst_bits_counter + } + #[doc = "0x1e0 - BIST Counter Register"] + #[inline(always)] + pub const fn bist_cntr0(&self) -> &BistCntr0 { + &self.bist_cntr0 + } + #[doc = "0x1e4 - BIST Counter Register"] + #[inline(always)] + pub const fn bist_cntr1(&self) -> &BistCntr1 { + &self.bist_cntr1 + } + #[doc = "0x1e8 - BIST Counter Register"] + #[inline(always)] + pub const fn bist_cntr2(&self) -> &BistCntr2 { + &self.bist_cntr2 + } +} +#[doc = "IMR (rw) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`imr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imr`] module"] +#[doc(alias = "IMR")] +pub type Imr = crate::Reg; +#[doc = "Interrupt Mask Register"] +pub mod imr; +#[doc = "ISR (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`] module"] +#[doc(alias = "ISR")] +pub type Isr = crate::Reg; +#[doc = "Interrupt Status Register"] +pub mod isr; +#[doc = "ICR (rw) register accessor: Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`] module"] +#[doc(alias = "ICR")] +pub type Icr = crate::Reg; +#[doc = "Interrupt Clear Register"] +pub mod icr; +#[doc = "CONFIG (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +#[doc(alias = "CONFIG")] +pub type Config = crate::Reg; +#[doc = "Configuration Register"] +pub mod config; +#[doc = "VALID (r) register accessor: Valid Register\n\nYou can [`read`](crate::Reg::read) this register and get [`valid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@valid`] module"] +#[doc(alias = "VALID")] +pub type Valid = crate::Reg; +#[doc = "Valid Register"] +pub mod valid; +#[doc = "EHR_DATA0 (r) register accessor: Entropy Holding Register Data Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ehr_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ehr_data0`] module"] +#[doc(alias = "EHR_DATA0")] +pub type EhrData0 = crate::Reg; +#[doc = "Entropy Holding Register Data Register"] +pub mod ehr_data0; +pub use ehr_data0 as ehr_data1; +pub use ehr_data0 as ehr_data2; +pub use ehr_data0 as ehr_data3; +pub use ehr_data0 as ehr_data4; +pub use ehr_data0 as ehr_data5; +pub use EhrData0 as EhrData1; +pub use EhrData0 as EhrData2; +pub use EhrData0 as EhrData3; +pub use EhrData0 as EhrData4; +pub use EhrData0 as EhrData5; +#[doc = "RND_SOURCE_ENABLE (rw) register accessor: Random Source Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rnd_source_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rnd_source_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_source_enable`] module"] +#[doc(alias = "RND_SOURCE_ENABLE")] +pub type RndSourceEnable = crate::Reg; +#[doc = "Random Source Enable Register"] +pub mod rnd_source_enable; +#[doc = "SAMPLE_CNT1 (rw) register accessor: Section TBD\n\nYou can [`read`](crate::Reg::read) this register and get [`sample_cnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sample_cnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sample_cnt1`] module"] +#[doc(alias = "SAMPLE_CNT1")] +pub type SampleCnt1 = crate::Reg; +#[doc = "Section TBD"] +pub mod sample_cnt1; +#[doc = "AUTOCORR_STATISTIC (rw) register accessor: Auto-correlator Statistic Register\n\nYou can [`read`](crate::Reg::read) this register and get [`autocorr_statistic::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`autocorr_statistic::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@autocorr_statistic`] module"] +#[doc(alias = "AUTOCORR_STATISTIC")] +pub type AutocorrStatistic = crate::Reg; +#[doc = "Auto-correlator Statistic Register"] +pub mod autocorr_statistic; +#[doc = "DEBUG_CONTROL (rw) register accessor: Section TBD\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_control`] module"] +#[doc(alias = "DEBUG_CONTROL")] +pub type DebugControl = crate::Reg; +#[doc = "Section TBD"] +pub mod debug_control; +#[doc = "SW_RESET (rw) register accessor: Reset Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sw_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_reset`] module"] +#[doc(alias = "SW_RESET")] +pub type SwReset = crate::Reg; +#[doc = "Reset Register"] +pub mod sw_reset; +#[doc = "BUSY (r) register accessor: Busy Register\n\nYou can [`read`](crate::Reg::read) this register and get [`busy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@busy`] module"] +#[doc(alias = "BUSY")] +pub type Busy = crate::Reg; +#[doc = "Busy Register"] +pub mod busy; +#[doc = "RST_BITS_COUNTER (rw) register accessor: Reset Bits Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_bits_counter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_bits_counter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_bits_counter`] module"] +#[doc(alias = "RST_BITS_COUNTER")] +pub type RstBitsCounter = crate::Reg; +#[doc = "Reset Bits Counter Register"] +pub mod rst_bits_counter; +#[doc = "BIST_CNTR0 (r) register accessor: BIST Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`bist_cntr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bist_cntr0`] module"] +#[doc(alias = "BIST_CNTR0")] +pub type BistCntr0 = crate::Reg; +#[doc = "BIST Counter Register"] +pub mod bist_cntr0; +pub use bist_cntr0 as bist_cntr1; +pub use bist_cntr0 as bist_cntr2; +pub use BistCntr0 as BistCntr1; +pub use BistCntr0 as BistCntr2; diff --git a/va416xx/va416xx/src/trng/autocorr_statistic.rs b/va416xx/va416xx/src/trng/autocorr_statistic.rs new file mode 100644 index 0000000..258a8df --- /dev/null +++ b/va416xx/va416xx/src/trng/autocorr_statistic.rs @@ -0,0 +1,49 @@ +#[doc = "Register `AUTOCORR_STATISTIC` reader"] +pub type R = crate::R; +#[doc = "Register `AUTOCORR_STATISTIC` writer"] +pub type W = crate::W; +#[doc = "Field `AUTOCORR_TRYS` reader - Count each time an autocorrelation test starts"] +pub type AutocorrTrysR = crate::FieldReader; +#[doc = "Field `AUTOCORR_TRYS` writer - Count each time an autocorrelation test starts"] +pub type AutocorrTrysW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `AUTOCORR_FAILS` reader - Count each time an autocorrelation test fails"] +pub type AutocorrFailsR = crate::FieldReader; +#[doc = "Field `AUTOCORR_FAILS` writer - Count each time an autocorrelation test fails"] +pub type AutocorrFailsW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:13 - Count each time an autocorrelation test starts"] + #[inline(always)] + pub fn autocorr_trys(&self) -> AutocorrTrysR { + AutocorrTrysR::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 14:21 - Count each time an autocorrelation test fails"] + #[inline(always)] + pub fn autocorr_fails(&self) -> AutocorrFailsR { + AutocorrFailsR::new(((self.bits >> 14) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:13 - Count each time an autocorrelation test starts"] + #[inline(always)] + pub fn autocorr_trys(&mut self) -> AutocorrTrysW<'_, AutocorrStatisticSpec> { + AutocorrTrysW::new(self, 0) + } + #[doc = "Bits 14:21 - Count each time an autocorrelation test fails"] + #[inline(always)] + pub fn autocorr_fails(&mut self) -> AutocorrFailsW<'_, AutocorrStatisticSpec> { + AutocorrFailsW::new(self, 14) + } +} +#[doc = "Auto-correlator Statistic Register\n\nYou can [`read`](crate::Reg::read) this register and get [`autocorr_statistic::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`autocorr_statistic::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AutocorrStatisticSpec; +impl crate::RegisterSpec for AutocorrStatisticSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`autocorr_statistic::R`](R) reader structure"] +impl crate::Readable for AutocorrStatisticSpec {} +#[doc = "`write(|w| ..)` method takes [`autocorr_statistic::W`](W) writer structure"] +impl crate::Writable for AutocorrStatisticSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets AUTOCORR_STATISTIC to value 0"] +impl crate::Resettable for AutocorrStatisticSpec {} diff --git a/va416xx/va416xx/src/trng/bist_cntr0.rs b/va416xx/va416xx/src/trng/bist_cntr0.rs new file mode 100644 index 0000000..e08c44b --- /dev/null +++ b/va416xx/va416xx/src/trng/bist_cntr0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `BIST_CNTR0` reader"] +pub type R = crate::R; +#[doc = "Field `ROSC_CNTR_VAL` reader - Returns the results of the TRNG BIST counter"] +pub type RoscCntrValR = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - Returns the results of the TRNG BIST counter"] + #[inline(always)] + pub fn rosc_cntr_val(&self) -> RoscCntrValR { + RoscCntrValR::new(self.bits & 0x003f_ffff) + } +} +#[doc = "BIST Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`bist_cntr0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BistCntr0Spec; +impl crate::RegisterSpec for BistCntr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bist_cntr0::R`](R) reader structure"] +impl crate::Readable for BistCntr0Spec {} +#[doc = "`reset()` method sets BIST_CNTR0 to value 0"] +impl crate::Resettable for BistCntr0Spec {} diff --git a/va416xx/va416xx/src/trng/busy.rs b/va416xx/va416xx/src/trng/busy.rs new file mode 100644 index 0000000..6cc0986 --- /dev/null +++ b/va416xx/va416xx/src/trng/busy.rs @@ -0,0 +1,20 @@ +#[doc = "Register `BUSY` reader"] +pub type R = crate::R; +#[doc = "Field `BUSY` reader - Reflects the status of the rng_busy signal"] +pub type BusyR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Reflects the status of the rng_busy signal"] + #[inline(always)] + pub fn busy(&self) -> BusyR { + BusyR::new((self.bits & 1) != 0) + } +} +#[doc = "Busy Register\n\nYou can [`read`](crate::Reg::read) this register and get [`busy::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BusySpec; +impl crate::RegisterSpec for BusySpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`busy::R`](R) reader structure"] +impl crate::Readable for BusySpec {} +#[doc = "`reset()` method sets BUSY to value 0"] +impl crate::Resettable for BusySpec {} diff --git a/va416xx/va416xx/src/trng/config.rs b/va416xx/va416xx/src/trng/config.rs new file mode 100644 index 0000000..127e9a5 --- /dev/null +++ b/va416xx/va416xx/src/trng/config.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `RND_SRC_SEL` reader - Selects the number of inverters (out of four possible selections) in the ring oscillator"] +pub type RndSrcSelR = crate::FieldReader; +#[doc = "Field `RND_SRC_SEL` writer - Selects the number of inverters (out of four possible selections) in the ring oscillator"] +pub type RndSrcSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Selects the number of inverters (out of four possible selections) in the ring oscillator"] + #[inline(always)] + pub fn rnd_src_sel(&self) -> RndSrcSelR { + RndSrcSelR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects the number of inverters (out of four possible selections) in the ring oscillator"] + #[inline(always)] + pub fn rnd_src_sel(&mut self) -> RndSrcSelW<'_, ConfigSpec> { + RndSrcSelW::new(self, 0) + } +} +#[doc = "Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ConfigSpec; +impl crate::RegisterSpec for ConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for ConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for ConfigSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for ConfigSpec {} diff --git a/va416xx/va416xx/src/trng/debug_control.rs b/va416xx/va416xx/src/trng/debug_control.rs new file mode 100644 index 0000000..16b6e6f --- /dev/null +++ b/va416xx/va416xx/src/trng/debug_control.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DEBUG_CONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `DEBUG_CONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `VNC_PYPASS` reader - The Von Neumann balancer is bypassed"] +pub type VncPypassR = crate::BitReader; +#[doc = "Field `VNC_PYPASS` writer - The Von Neumann balancer is bypassed"] +pub type VncPypassW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRNGT_BYPASS` reader - The CRNGT test in the TRNG is bypassed"] +pub type CrngtBypassR = crate::BitReader; +#[doc = "Field `CRNGT_BYPASS` writer - The CRNGT test in the TRNG is bypassed"] +pub type CrngtBypassW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTO_CORRELATE_BYPASS` reader - The autocorrelation test in the TRNG module is bypassed"] +pub type AutoCorrelateBypassR = crate::BitReader; +#[doc = "Field `AUTO_CORRELATE_BYPASS` writer - The autocorrelation test in the TRNG module is bypassed"] +pub type AutoCorrelateBypassW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - The Von Neumann balancer is bypassed"] + #[inline(always)] + pub fn vnc_pypass(&self) -> VncPypassR { + VncPypassR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The CRNGT test in the TRNG is bypassed"] + #[inline(always)] + pub fn crngt_bypass(&self) -> CrngtBypassR { + CrngtBypassR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The autocorrelation test in the TRNG module is bypassed"] + #[inline(always)] + pub fn auto_correlate_bypass(&self) -> AutoCorrelateBypassR { + AutoCorrelateBypassR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - The Von Neumann balancer is bypassed"] + #[inline(always)] + pub fn vnc_pypass(&mut self) -> VncPypassW<'_, DebugControlSpec> { + VncPypassW::new(self, 1) + } + #[doc = "Bit 2 - The CRNGT test in the TRNG is bypassed"] + #[inline(always)] + pub fn crngt_bypass(&mut self) -> CrngtBypassW<'_, DebugControlSpec> { + CrngtBypassW::new(self, 2) + } + #[doc = "Bit 3 - The autocorrelation test in the TRNG module is bypassed"] + #[inline(always)] + pub fn auto_correlate_bypass(&mut self) -> AutoCorrelateBypassW<'_, DebugControlSpec> { + AutoCorrelateBypassW::new(self, 3) + } +} +#[doc = "Section TBD\n\nYou can [`read`](crate::Reg::read) this register and get [`debug_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DebugControlSpec; +impl crate::RegisterSpec for DebugControlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_control::R`](R) reader structure"] +impl crate::Readable for DebugControlSpec {} +#[doc = "`write(|w| ..)` method takes [`debug_control::W`](W) writer structure"] +impl crate::Writable for DebugControlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DEBUG_CONTROL to value 0"] +impl crate::Resettable for DebugControlSpec {} diff --git a/va416xx/va416xx/src/trng/ehr_data0.rs b/va416xx/va416xx/src/trng/ehr_data0.rs new file mode 100644 index 0000000..42ceffa --- /dev/null +++ b/va416xx/va416xx/src/trng/ehr_data0.rs @@ -0,0 +1,20 @@ +#[doc = "Register `EHR_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `EHR_DATA` reader - 32 Bits of Entropy Holding Register"] +pub type EhrDataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - 32 Bits of Entropy Holding Register"] + #[inline(always)] + pub fn ehr_data(&self) -> EhrDataR { + EhrDataR::new(self.bits) + } +} +#[doc = "Entropy Holding Register Data Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ehr_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EhrData0Spec; +impl crate::RegisterSpec for EhrData0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ehr_data0::R`](R) reader structure"] +impl crate::Readable for EhrData0Spec {} +#[doc = "`reset()` method sets EHR_DATA0 to value 0"] +impl crate::Resettable for EhrData0Spec {} diff --git a/va416xx/va416xx/src/trng/icr.rs b/va416xx/va416xx/src/trng/icr.rs new file mode 100644 index 0000000..33c7989 --- /dev/null +++ b/va416xx/va416xx/src/trng/icr.rs @@ -0,0 +1,77 @@ +#[doc = "Register `ICR` reader"] +pub type R = crate::R; +#[doc = "Register `ICR` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_VALID` reader - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] registers have been read"] +pub type EhrValidR = crate::BitReader; +#[doc = "Field `EHR_VALID` writer - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] registers have been read"] +pub type EhrValidW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOCORR_ERR` reader - Software cannot clear this bit. Only a TRNG reset can clear this bit"] +pub type AutocorrErrR = crate::BitReader; +#[doc = "Field `AUTOCORR_ERR` writer - Software cannot clear this bit. Only a TRNG reset can clear this bit"] +pub type AutocorrErrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRNGT_ERR` reader - Clear a Continuous Random Number Generation Testing (CRNGT) error"] +pub type CrngtErrR = crate::BitReader; +#[doc = "Field `CRNGT_ERR` writer - Clear a Continuous Random Number Generation Testing (CRNGT) error"] +pub type CrngtErrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VN_ERR` reader - Clears a Von Neumann error"] +pub type VnErrR = crate::BitReader; +#[doc = "Field `VN_ERR` writer - Clears a Von Neumann error"] +pub type VnErrW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] registers have been read"] + #[inline(always)] + pub fn ehr_valid(&self) -> EhrValidR { + EhrValidR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software cannot clear this bit. Only a TRNG reset can clear this bit"] + #[inline(always)] + pub fn autocorr_err(&self) -> AutocorrErrR { + AutocorrErrR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Clear a Continuous Random Number Generation Testing (CRNGT) error"] + #[inline(always)] + pub fn crngt_err(&self) -> CrngtErrR { + CrngtErrR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Clears a Von Neumann error"] + #[inline(always)] + pub fn vn_err(&self) -> VnErrR { + VnErrR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] registers have been read"] + #[inline(always)] + pub fn ehr_valid(&mut self) -> EhrValidW<'_, IcrSpec> { + EhrValidW::new(self, 0) + } + #[doc = "Bit 1 - Software cannot clear this bit. Only a TRNG reset can clear this bit"] + #[inline(always)] + pub fn autocorr_err(&mut self) -> AutocorrErrW<'_, IcrSpec> { + AutocorrErrW::new(self, 1) + } + #[doc = "Bit 2 - Clear a Continuous Random Number Generation Testing (CRNGT) error"] + #[inline(always)] + pub fn crngt_err(&mut self) -> CrngtErrW<'_, IcrSpec> { + CrngtErrW::new(self, 2) + } + #[doc = "Bit 3 - Clears a Von Neumann error"] + #[inline(always)] + pub fn vn_err(&mut self) -> VnErrW<'_, IcrSpec> { + VnErrW::new(self, 3) + } +} +#[doc = "Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IcrSpec; +impl crate::RegisterSpec for IcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`icr::R`](R) reader structure"] +impl crate::Readable for IcrSpec {} +#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] +impl crate::Writable for IcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ICR to value 0"] +impl crate::Resettable for IcrSpec {} diff --git a/va416xx/va416xx/src/trng/imr.rs b/va416xx/va416xx/src/trng/imr.rs new file mode 100644 index 0000000..018be0d --- /dev/null +++ b/va416xx/va416xx/src/trng/imr.rs @@ -0,0 +1,79 @@ +#[doc = "Register `IMR` reader"] +pub type R = crate::R; +#[doc = "Register `IMR` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_VALID_INT_MASK` reader - Mask when the TRNG has collected 192 bits"] +pub type EhrValidIntMaskR = crate::BitReader; +#[doc = "Field `EHR_VALID_INT_MASK` writer - Mask when the TRNG has collected 192 bits"] +pub type EhrValidIntMaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOCORR_ERR_INT_MASK` reader - Mask the Autocorrelation error"] +pub type AutocorrErrIntMaskR = crate::BitReader; +#[doc = "Field `AUTOCORR_ERR_INT_MASK` writer - Mask the Autocorrelation error"] +pub type AutocorrErrIntMaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRNGT_ERR_INT_MASK` reader - Mask the CRNGT error"] +pub type CrngtErrIntMaskR = crate::BitReader; +#[doc = "Field `CRNGT_ERR_INT_MASK` writer - Mask the CRNGT error"] +pub type CrngtErrIntMaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VN_ERR_INT_MASK` reader - Mask the Von Neumann error"] +pub type VnErrIntMaskR = crate::BitReader; +#[doc = "Field `VN_ERR_INT_MASK` writer - Mask the Von Neumann error"] +pub type VnErrIntMaskW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Mask when the TRNG has collected 192 bits"] + #[inline(always)] + pub fn ehr_valid_int_mask(&self) -> EhrValidIntMaskR { + EhrValidIntMaskR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mask the Autocorrelation error"] + #[inline(always)] + pub fn autocorr_err_int_mask(&self) -> AutocorrErrIntMaskR { + AutocorrErrIntMaskR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Mask the CRNGT error"] + #[inline(always)] + pub fn crngt_err_int_mask(&self) -> CrngtErrIntMaskR { + CrngtErrIntMaskR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Mask the Von Neumann error"] + #[inline(always)] + pub fn vn_err_int_mask(&self) -> VnErrIntMaskR { + VnErrIntMaskR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Mask when the TRNG has collected 192 bits"] + #[inline(always)] + pub fn ehr_valid_int_mask(&mut self) -> EhrValidIntMaskW<'_, ImrSpec> { + EhrValidIntMaskW::new(self, 0) + } + #[doc = "Bit 1 - Mask the Autocorrelation error"] + #[inline(always)] + pub fn autocorr_err_int_mask(&mut self) -> AutocorrErrIntMaskW<'_, ImrSpec> { + AutocorrErrIntMaskW::new(self, 1) + } + #[doc = "Bit 2 - Mask the CRNGT error"] + #[inline(always)] + pub fn crngt_err_int_mask(&mut self) -> CrngtErrIntMaskW<'_, ImrSpec> { + CrngtErrIntMaskW::new(self, 2) + } + #[doc = "Bit 3 - Mask the Von Neumann error"] + #[inline(always)] + pub fn vn_err_int_mask(&mut self) -> VnErrIntMaskW<'_, ImrSpec> { + VnErrIntMaskW::new(self, 3) + } +} +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ImrSpec; +impl crate::RegisterSpec for ImrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for ImrSpec {} +#[doc = "`write(|w| ..)` method takes [`imr::W`](W) writer structure"] +impl crate::Writable for ImrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IMR to value 0x0f"] +impl crate::Resettable for ImrSpec { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/va416xx/va416xx/src/trng/isr.rs b/va416xx/va416xx/src/trng/isr.rs new file mode 100644 index 0000000..5590006 --- /dev/null +++ b/va416xx/va416xx/src/trng/isr.rs @@ -0,0 +1,41 @@ +#[doc = "Register `ISR` reader"] +pub type R = crate::R; +#[doc = "Field `EHR_VALID` reader - 192 bits have been collected in the TRNG"] +pub type EhrValidR = crate::BitReader; +#[doc = "Field `AUTOCORR_ERR` reader - Indicates that the Autocorrelation test failed four times in a row"] +pub type AutocorrErrR = crate::BitReader; +#[doc = "Field `CRNGT_ERR` reader - Indicates a Continuous Random Number Generation Testing (CRNGT) error"] +pub type CrngtErrR = crate::BitReader; +#[doc = "Field `VN_ERR` reader - Indicates a Von Neumann error"] +pub type VnErrR = crate::BitReader; +impl R { + #[doc = "Bit 0 - 192 bits have been collected in the TRNG"] + #[inline(always)] + pub fn ehr_valid(&self) -> EhrValidR { + EhrValidR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates that the Autocorrelation test failed four times in a row"] + #[inline(always)] + pub fn autocorr_err(&self) -> AutocorrErrR { + AutocorrErrR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a Continuous Random Number Generation Testing (CRNGT) error"] + #[inline(always)] + pub fn crngt_err(&self) -> CrngtErrR { + CrngtErrR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates a Von Neumann error"] + #[inline(always)] + pub fn vn_err(&self) -> VnErrR { + VnErrR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IsrSpec; +impl crate::RegisterSpec for IsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for IsrSpec {} +#[doc = "`reset()` method sets ISR to value 0"] +impl crate::Resettable for IsrSpec {} diff --git a/va416xx/va416xx/src/trng/rnd_source_enable.rs b/va416xx/va416xx/src/trng/rnd_source_enable.rs new file mode 100644 index 0000000..35ad2df --- /dev/null +++ b/va416xx/va416xx/src/trng/rnd_source_enable.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RND_SOURCE_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `RND_SOURCE_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `RND_SRC_EN` reader - The entropy source, ring oscillator, is enabled"] +pub type RndSrcEnR = crate::BitReader; +#[doc = "Field `RND_SRC_EN` writer - The entropy source, ring oscillator, is enabled"] +pub type RndSrcEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The entropy source, ring oscillator, is enabled"] + #[inline(always)] + pub fn rnd_src_en(&self) -> RndSrcEnR { + RndSrcEnR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - The entropy source, ring oscillator, is enabled"] + #[inline(always)] + pub fn rnd_src_en(&mut self) -> RndSrcEnW<'_, RndSourceEnableSpec> { + RndSrcEnW::new(self, 0) + } +} +#[doc = "Random Source Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rnd_source_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rnd_source_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RndSourceEnableSpec; +impl crate::RegisterSpec for RndSourceEnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_source_enable::R`](R) reader structure"] +impl crate::Readable for RndSourceEnableSpec {} +#[doc = "`write(|w| ..)` method takes [`rnd_source_enable::W`](W) writer structure"] +impl crate::Writable for RndSourceEnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RND_SOURCE_ENABLE to value 0"] +impl crate::Resettable for RndSourceEnableSpec {} diff --git a/va416xx/va416xx/src/trng/rst_bits_counter.rs b/va416xx/va416xx/src/trng/rst_bits_counter.rs new file mode 100644 index 0000000..c44f176 --- /dev/null +++ b/va416xx/va416xx/src/trng/rst_bits_counter.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RST_BITS_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Register `RST_BITS_COUNTER` writer"] +pub type W = crate::W; +#[doc = "Field `RST_BITS_COUNTER` reader - Writing any value to this bit resets the bits counter and TRNG valid registers"] +pub type RstBitsCounterR = crate::BitReader; +#[doc = "Field `RST_BITS_COUNTER` writer - Writing any value to this bit resets the bits counter and TRNG valid registers"] +pub type RstBitsCounterW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Writing any value to this bit resets the bits counter and TRNG valid registers"] + #[inline(always)] + pub fn rst_bits_counter(&self) -> RstBitsCounterR { + RstBitsCounterR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Writing any value to this bit resets the bits counter and TRNG valid registers"] + #[inline(always)] + pub fn rst_bits_counter(&mut self) -> RstBitsCounterW<'_, RstBitsCounterSpec> { + RstBitsCounterW::new(self, 0) + } +} +#[doc = "Reset Bits Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_bits_counter::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_bits_counter::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RstBitsCounterSpec; +impl crate::RegisterSpec for RstBitsCounterSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_bits_counter::R`](R) reader structure"] +impl crate::Readable for RstBitsCounterSpec {} +#[doc = "`write(|w| ..)` method takes [`rst_bits_counter::W`](W) writer structure"] +impl crate::Writable for RstBitsCounterSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RST_BITS_COUNTER to value 0"] +impl crate::Resettable for RstBitsCounterSpec {} diff --git a/va416xx/va416xx/src/trng/sample_cnt1.rs b/va416xx/va416xx/src/trng/sample_cnt1.rs new file mode 100644 index 0000000..73db298 --- /dev/null +++ b/va416xx/va416xx/src/trng/sample_cnt1.rs @@ -0,0 +1,37 @@ +#[doc = "Register `SAMPLE_CNT1` reader"] +pub type R = crate::R; +#[doc = "Register `SAMPLE_CNT1` writer"] +pub type W = crate::W; +#[doc = "Field `SAMPLE_CNTR1` reader - Sets the number of clk cycles between two consecutive ring oscillator samples"] +pub type SampleCntr1R = crate::FieldReader; +#[doc = "Field `SAMPLE_CNTR1` writer - Sets the number of clk cycles between two consecutive ring oscillator samples"] +pub type SampleCntr1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Sets the number of clk cycles between two consecutive ring oscillator samples"] + #[inline(always)] + pub fn sample_cntr1(&self) -> SampleCntr1R { + SampleCntr1R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Sets the number of clk cycles between two consecutive ring oscillator samples"] + #[inline(always)] + pub fn sample_cntr1(&mut self) -> SampleCntr1W<'_, SampleCnt1Spec> { + SampleCntr1W::new(self, 0) + } +} +#[doc = "Section TBD\n\nYou can [`read`](crate::Reg::read) this register and get [`sample_cnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sample_cnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SampleCnt1Spec; +impl crate::RegisterSpec for SampleCnt1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sample_cnt1::R`](R) reader structure"] +impl crate::Readable for SampleCnt1Spec {} +#[doc = "`write(|w| ..)` method takes [`sample_cnt1::W`](W) writer structure"] +impl crate::Writable for SampleCnt1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SAMPLE_CNT1 to value 0xffff"] +impl crate::Resettable for SampleCnt1Spec { + const RESET_VALUE: u32 = 0xffff; +} diff --git a/va416xx/va416xx/src/trng/sw_reset.rs b/va416xx/va416xx/src/trng/sw_reset.rs new file mode 100644 index 0000000..8f19a60 --- /dev/null +++ b/va416xx/va416xx/src/trng/sw_reset.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SW_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `SW_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `SW_RESET` reader - Writing 1 to this register causes an internal TRNG reset"] +pub type SwResetR = crate::BitReader; +#[doc = "Field `SW_RESET` writer - Writing 1 to this register causes an internal TRNG reset"] +pub type SwResetW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Writing 1 to this register causes an internal TRNG reset"] + #[inline(always)] + pub fn sw_reset(&self) -> SwResetR { + SwResetR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Writing 1 to this register causes an internal TRNG reset"] + #[inline(always)] + pub fn sw_reset(&mut self) -> SwResetW<'_, SwResetSpec> { + SwResetW::new(self, 0) + } +} +#[doc = "Reset Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sw_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwResetSpec; +impl crate::RegisterSpec for SwResetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_reset::R`](R) reader structure"] +impl crate::Readable for SwResetSpec {} +#[doc = "`write(|w| ..)` method takes [`sw_reset::W`](W) writer structure"] +impl crate::Writable for SwResetSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SW_RESET to value 0"] +impl crate::Resettable for SwResetSpec {} diff --git a/va416xx/va416xx/src/trng/valid.rs b/va416xx/va416xx/src/trng/valid.rs new file mode 100644 index 0000000..16d5542 --- /dev/null +++ b/va416xx/va416xx/src/trng/valid.rs @@ -0,0 +1,20 @@ +#[doc = "Register `VALID` reader"] +pub type R = crate::R; +#[doc = "Field `EHR_VALID` reader - Indicates that the collection of bits in the TRNG is complete"] +pub type EhrValidR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates that the collection of bits in the TRNG is complete"] + #[inline(always)] + pub fn ehr_valid(&self) -> EhrValidR { + EhrValidR::new((self.bits & 1) != 0) + } +} +#[doc = "Valid Register\n\nYou can [`read`](crate::Reg::read) this register and get [`valid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ValidSpec; +impl crate::RegisterSpec for ValidSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`valid::R`](R) reader structure"] +impl crate::Readable for ValidSpec {} +#[doc = "`reset()` method sets VALID to value 0"] +impl crate::Resettable for ValidSpec {} diff --git a/va416xx/va416xx/src/uart0.rs b/va416xx/va416xx/src/uart0.rs new file mode 100644 index 0000000..43216ab --- /dev/null +++ b/va416xx/va416xx/src/uart0.rs @@ -0,0 +1,207 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + data: Data, + enable: Enable, + ctrl: Ctrl, + clkscale: Clkscale, + rxstatus: Rxstatus, + txstatus: Txstatus, + fifo_clr: FifoClr, + txbreak: Txbreak, + addr9: Addr9, + addr9mask: Addr9mask, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + txfifoirqtrg: Txfifoirqtrg, + rxfifortstrg: Rxfifortstrg, + state: State, + _reserved18: [u8; 0x0fb4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Data In/Out Register"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x04 - Enable Register"] + #[inline(always)] + pub const fn enable(&self) -> &Enable { + &self.enable + } + #[doc = "0x08 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x0c - Clock Scale Register"] + #[inline(always)] + pub const fn clkscale(&self) -> &Clkscale { + &self.clkscale + } + #[doc = "0x10 - Status Register"] + #[inline(always)] + pub const fn rxstatus(&self) -> &Rxstatus { + &self.rxstatus + } + #[doc = "0x14 - Status Register"] + #[inline(always)] + pub const fn txstatus(&self) -> &Txstatus { + &self.txstatus + } + #[doc = "0x18 - Clear FIFO Register"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x1c - Break Transmit Register"] + #[inline(always)] + pub const fn txbreak(&self) -> &Txbreak { + &self.txbreak + } + #[doc = "0x20 - Address9 Register"] + #[inline(always)] + pub const fn addr9(&self) -> &Addr9 { + &self.addr9 + } + #[doc = "0x24 - Address9 Mask Register"] + #[inline(always)] + pub const fn addr9mask(&self) -> &Addr9mask { + &self.addr9mask + } + #[doc = "0x28 - IRQ Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x2c - IRQ Raw Status Register"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x30 - IRQ Enabled Status Register"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x34 - IRQ Clear Status Register"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x38 - Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x3c - Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x40 - Rx FIFO RTS Trigger Level"] + #[inline(always)] + pub const fn rxfifortstrg(&self) -> &Rxfifortstrg { + &self.rxfifortstrg + } + #[doc = "0x44 - Internal STATE of UART Controller"] + #[inline(always)] + pub const fn state(&self) -> &State { + &self.state + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "DATA (rw) register accessor: Data In/Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data In/Out Register"] +pub mod data; +#[doc = "ENABLE (rw) register accessor: Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] +#[doc(alias = "ENABLE")] +pub type Enable = crate::Reg; +#[doc = "Enable Register"] +pub mod enable; +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "CLKSCALE (rw) register accessor: Clock Scale Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] module"] +#[doc(alias = "CLKSCALE")] +pub type Clkscale = crate::Reg; +#[doc = "Clock Scale Register"] +pub mod clkscale; +#[doc = "RXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxstatus`] module"] +#[doc(alias = "RXSTATUS")] +pub type Rxstatus = crate::Reg; +#[doc = "Status Register"] +pub mod rxstatus; +#[doc = "TXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txstatus`] module"] +#[doc(alias = "TXSTATUS")] +pub type Txstatus = crate::Reg; +#[doc = "Status Register"] +pub mod txstatus; +#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "TXBREAK (w) register accessor: Break Transmit Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbreak::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbreak`] module"] +#[doc(alias = "TXBREAK")] +pub type Txbreak = crate::Reg; +#[doc = "Break Transmit Register"] +pub mod txbreak; +#[doc = "ADDR9 (rw) register accessor: Address9 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9`] module"] +#[doc(alias = "ADDR9")] +pub type Addr9 = crate::Reg; +#[doc = "Address9 Register"] +pub mod addr9; +#[doc = "ADDR9MASK (rw) register accessor: Address9 Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9mask`] module"] +#[doc(alias = "ADDR9MASK")] +pub type Addr9mask = crate::Reg; +#[doc = "Address9 Mask Register"] +pub mod addr9mask; +#[doc = "IRQ_ENB (rw) register accessor: IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "IRQ Enable Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "RXFIFORTSTRG (rw) register accessor: Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifortstrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifortstrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifortstrg`] module"] +#[doc(alias = "RXFIFORTSTRG")] +pub type Rxfifortstrg = crate::Reg; +#[doc = "Rx FIFO RTS Trigger Level"] +pub mod rxfifortstrg; +#[doc = "STATE (r) register accessor: Internal STATE of UART Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +#[doc(alias = "STATE")] +pub type State = crate::Reg; +#[doc = "Internal STATE of UART Controller"] +pub mod state; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/uart0/addr9.rs b/va416xx/va416xx/src/uart0/addr9.rs new file mode 100644 index 0000000..56b06b3 --- /dev/null +++ b/va416xx/va416xx/src/uart0/addr9.rs @@ -0,0 +1,24 @@ +#[doc = "Register `ADDR9` reader"] +pub type R = crate::R; +#[doc = "Register `ADDR9` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Address9 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Addr9Spec; +impl crate::RegisterSpec for Addr9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`addr9::R`](R) reader structure"] +impl crate::Readable for Addr9Spec {} +#[doc = "`write(|w| ..)` method takes [`addr9::W`](W) writer structure"] +impl crate::Writable for Addr9Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADDR9 to value 0"] +impl crate::Resettable for Addr9Spec {} diff --git a/va416xx/va416xx/src/uart0/addr9mask.rs b/va416xx/va416xx/src/uart0/addr9mask.rs new file mode 100644 index 0000000..4b47c5c --- /dev/null +++ b/va416xx/va416xx/src/uart0/addr9mask.rs @@ -0,0 +1,24 @@ +#[doc = "Register `ADDR9MASK` reader"] +pub type R = crate::R; +#[doc = "Register `ADDR9MASK` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Address9 Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Addr9maskSpec; +impl crate::RegisterSpec for Addr9maskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`addr9mask::R`](R) reader structure"] +impl crate::Readable for Addr9maskSpec {} +#[doc = "`write(|w| ..)` method takes [`addr9mask::W`](W) writer structure"] +impl crate::Writable for Addr9maskSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ADDR9MASK to value 0"] +impl crate::Resettable for Addr9maskSpec {} diff --git a/va416xx/va416xx/src/uart0/clkscale.rs b/va416xx/va416xx/src/uart0/clkscale.rs new file mode 100644 index 0000000..2b5b7af --- /dev/null +++ b/va416xx/va416xx/src/uart0/clkscale.rs @@ -0,0 +1,56 @@ +#[doc = "Register `CLKSCALE` reader"] +pub type R = crate::R; +#[doc = "Register `CLKSCALE` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional Divide (64ths)"] +pub type FracR = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional Divide (64ths)"] +pub type FracW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `INT` reader - Integer Divide"] +pub type IntR = crate::FieldReader; +#[doc = "Field `INT` writer - Integer Divide"] +pub type IntW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `RESET` writer - Reset Baud Counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - Fractional Divide (64ths)"] + #[inline(always)] + pub fn frac(&self) -> FracR { + FracR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Integer Divide"] + #[inline(always)] + pub fn int(&self) -> IntR { + IntR::new((self.bits >> 6) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bits 0:5 - Fractional Divide (64ths)"] + #[inline(always)] + pub fn frac(&mut self) -> FracW<'_, ClkscaleSpec> { + FracW::new(self, 0) + } + #[doc = "Bits 6:23 - Integer Divide"] + #[inline(always)] + pub fn int(&mut self) -> IntW<'_, ClkscaleSpec> { + IntW::new(self, 6) + } + #[doc = "Bit 31 - Reset Baud Counter"] + #[inline(always)] + pub fn reset(&mut self) -> ResetW<'_, ClkscaleSpec> { + ResetW::new(self, 31) + } +} +#[doc = "Clock Scale Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkscaleSpec; +impl crate::RegisterSpec for ClkscaleSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkscale::R`](R) reader structure"] +impl crate::Readable for ClkscaleSpec {} +#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"] +impl crate::Writable for ClkscaleSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CLKSCALE to value 0"] +impl crate::Resettable for ClkscaleSpec {} diff --git a/va416xx/va416xx/src/uart0/ctrl.rs b/va416xx/va416xx/src/uart0/ctrl.rs new file mode 100644 index 0000000..117e6a5 --- /dev/null +++ b/va416xx/va416xx/src/uart0/ctrl.rs @@ -0,0 +1,175 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PAREN` reader - Parity Enable"] +pub type ParenR = crate::BitReader; +#[doc = "Field `PAREN` writer - Parity Enable"] +pub type ParenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAREVEN` reader - Parity Even/Odd(1/0)"] +pub type ParevenR = crate::BitReader; +#[doc = "Field `PAREVEN` writer - Parity Even/Odd(1/0)"] +pub type ParevenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARSTK` reader - Parity Sticky"] +pub type ParstkR = crate::BitReader; +#[doc = "Field `PARSTK` writer - Parity Sticky"] +pub type ParstkW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STOPBITS` reader - Stop Bits 1/2(0/1)"] +pub type StopbitsR = crate::BitReader; +#[doc = "Field `STOPBITS` writer - Stop Bits 1/2(0/1)"] +pub type StopbitsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WORDSIZE` reader - Word Size in Bits 5/6/7/8(00/01/10/11)"] +pub type WordsizeR = crate::FieldReader; +#[doc = "Field `WORDSIZE` writer - Word Size in Bits 5/6/7/8(00/01/10/11)"] +pub type WordsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LOOPBACK` reader - Loopback Enable"] +pub type LoopbackR = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Loopback Enable"] +pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACKBLK` reader - Loopback Block"] +pub type LoopbackblkR = crate::BitReader; +#[doc = "Field `LOOPBACKBLK` writer - Loopback Block"] +pub type LoopbackblkW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOCTS` reader - Enable Auto CTS mode"] +pub type AutoctsR = crate::BitReader; +#[doc = "Field `AUTOCTS` writer - Enable Auto CTS mode"] +pub type AutoctsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEFRTS` reader - Default RTSn value"] +pub type DefrtsR = crate::BitReader; +#[doc = "Field `DEFRTS` writer - Default RTSn value"] +pub type DefrtsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTORTS` reader - Enable Auto RTS mode"] +pub type AutortsR = crate::BitReader; +#[doc = "Field `AUTORTS` writer - Enable Auto RTS mode"] +pub type AutortsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BAUD8` reader - Enable BAUD8 mode"] +pub type Baud8R = crate::BitReader; +#[doc = "Field `BAUD8` writer - Enable BAUD8 mode"] +pub type Baud8W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Parity Enable"] + #[inline(always)] + pub fn paren(&self) -> ParenR { + ParenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Parity Even/Odd(1/0)"] + #[inline(always)] + pub fn pareven(&self) -> ParevenR { + ParevenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Parity Sticky"] + #[inline(always)] + pub fn parstk(&self) -> ParstkR { + ParstkR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Stop Bits 1/2(0/1)"] + #[inline(always)] + pub fn stopbits(&self) -> StopbitsR { + StopbitsR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"] + #[inline(always)] + pub fn wordsize(&self) -> WordsizeR { + WordsizeR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Loopback Enable"] + #[inline(always)] + pub fn loopback(&self) -> LoopbackR { + LoopbackR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Loopback Block"] + #[inline(always)] + pub fn loopbackblk(&self) -> LoopbackblkR { + LoopbackblkR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable Auto CTS mode"] + #[inline(always)] + pub fn autocts(&self) -> AutoctsR { + AutoctsR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Default RTSn value"] + #[inline(always)] + pub fn defrts(&self) -> DefrtsR { + DefrtsR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable Auto RTS mode"] + #[inline(always)] + pub fn autorts(&self) -> AutortsR { + AutortsR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable BAUD8 mode"] + #[inline(always)] + pub fn baud8(&self) -> Baud8R { + Baud8R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Enable"] + #[inline(always)] + pub fn paren(&mut self) -> ParenW<'_, CtrlSpec> { + ParenW::new(self, 0) + } + #[doc = "Bit 1 - Parity Even/Odd(1/0)"] + #[inline(always)] + pub fn pareven(&mut self) -> ParevenW<'_, CtrlSpec> { + ParevenW::new(self, 1) + } + #[doc = "Bit 2 - Parity Sticky"] + #[inline(always)] + pub fn parstk(&mut self) -> ParstkW<'_, CtrlSpec> { + ParstkW::new(self, 2) + } + #[doc = "Bit 3 - Stop Bits 1/2(0/1)"] + #[inline(always)] + pub fn stopbits(&mut self) -> StopbitsW<'_, CtrlSpec> { + StopbitsW::new(self, 3) + } + #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"] + #[inline(always)] + pub fn wordsize(&mut self) -> WordsizeW<'_, CtrlSpec> { + WordsizeW::new(self, 4) + } + #[doc = "Bit 6 - Loopback Enable"] + #[inline(always)] + pub fn loopback(&mut self) -> LoopbackW<'_, CtrlSpec> { + LoopbackW::new(self, 6) + } + #[doc = "Bit 7 - Loopback Block"] + #[inline(always)] + pub fn loopbackblk(&mut self) -> LoopbackblkW<'_, CtrlSpec> { + LoopbackblkW::new(self, 7) + } + #[doc = "Bit 8 - Enable Auto CTS mode"] + #[inline(always)] + pub fn autocts(&mut self) -> AutoctsW<'_, CtrlSpec> { + AutoctsW::new(self, 8) + } + #[doc = "Bit 9 - Default RTSn value"] + #[inline(always)] + pub fn defrts(&mut self) -> DefrtsW<'_, CtrlSpec> { + DefrtsW::new(self, 9) + } + #[doc = "Bit 10 - Enable Auto RTS mode"] + #[inline(always)] + pub fn autorts(&mut self) -> AutortsW<'_, CtrlSpec> { + AutortsW::new(self, 10) + } + #[doc = "Bit 11 - Enable BAUD8 mode"] + #[inline(always)] + pub fn baud8(&mut self) -> Baud8W<'_, CtrlSpec> { + Baud8W::new(self, 11) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec {} diff --git a/va416xx/va416xx/src/uart0/data.rs b/va416xx/va416xx/src/uart0/data.rs new file mode 100644 index 0000000..e14fd45 --- /dev/null +++ b/va416xx/va416xx/src/uart0/data.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data In/Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec {} diff --git a/va416xx/va416xx/src/uart0/enable.rs b/va416xx/va416xx/src/uart0/enable.rs new file mode 100644 index 0000000..ca6957e --- /dev/null +++ b/va416xx/va416xx/src/uart0/enable.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `RXENABLE` reader - Rx Enable"] +pub type RxenableR = crate::BitReader; +#[doc = "Field `RXENABLE` writer - Rx Enable"] +pub type RxenableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXENABLE` reader - Tx Enable"] +pub type TxenableR = crate::BitReader; +#[doc = "Field `TXENABLE` writer - Tx Enable"] +pub type TxenableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Rx Enable"] + #[inline(always)] + pub fn rxenable(&self) -> RxenableR { + RxenableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tx Enable"] + #[inline(always)] + pub fn txenable(&self) -> TxenableR { + TxenableR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx Enable"] + #[inline(always)] + pub fn rxenable(&mut self) -> RxenableW<'_, EnableSpec> { + RxenableW::new(self, 0) + } + #[doc = "Bit 1 - Tx Enable"] + #[inline(always)] + pub fn txenable(&mut self) -> TxenableW<'_, EnableSpec> { + TxenableW::new(self, 1) + } +} +#[doc = "Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EnableSpec; +impl crate::RegisterSpec for EnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`enable::R`](R) reader structure"] +impl crate::Readable for EnableSpec {} +#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"] +impl crate::Writable for EnableSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for EnableSpec {} diff --git a/va416xx/va416xx/src/uart0/fifo_clr.rs b/va416xx/va416xx/src/uart0/fifo_clr.rs new file mode 100644 index 0000000..339ac41 --- /dev/null +++ b/va416xx/va416xx/src/uart0/fifo_clr.rs @@ -0,0 +1,29 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> { + TxfifoW::new(self, 1) + } +} +#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec {} diff --git a/va416xx/va416xx/src/uart0/irq_enb.rs b/va416xx/va416xx/src/uart0/irq_enb.rs new file mode 100644 index 0000000..3965a8c --- /dev/null +++ b/va416xx/va416xx/src/uart0/irq_enb.rs @@ -0,0 +1,119 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `IRQ_RX` reader - RX Interrupt"] +pub type IrqRxR = crate::BitReader; +#[doc = "Field `IRQ_RX` writer - RX Interrupt"] +pub type IrqRxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_RX_STATUS` reader - RX Status Interrupt"] +pub type IrqRxStatusR = crate::BitReader; +#[doc = "Field `IRQ_RX_STATUS` writer - RX Status Interrupt"] +pub type IrqRxStatusW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_RX_TO` reader - RX Timeout Interrupt"] +pub type IrqRxToR = crate::BitReader; +#[doc = "Field `IRQ_RX_TO` writer - RX Timeout Interrupt"] +pub type IrqRxToW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX` reader - TX Interrupt"] +pub type IrqTxR = crate::BitReader; +#[doc = "Field `IRQ_TX` writer - TX Interrupt"] +pub type IrqTxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX_STATUS` reader - TX Status Interrupt"] +pub type IrqTxStatusR = crate::BitReader; +#[doc = "Field `IRQ_TX_STATUS` writer - TX Status Interrupt"] +pub type IrqTxStatusW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX_EMPTY` reader - TX Empty Interrupt"] +pub type IrqTxEmptyR = crate::BitReader; +#[doc = "Field `IRQ_TX_EMPTY` writer - TX Empty Interrupt"] +pub type IrqTxEmptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX_CTS` reader - TX CTS Change Interrupt"] +pub type IrqTxCtsR = crate::BitReader; +#[doc = "Field `IRQ_TX_CTS` writer - TX CTS Change Interrupt"] +pub type IrqTxCtsW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&self) -> IrqRxR { + IrqRxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&self) -> IrqRxStatusR { + IrqRxStatusR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&self) -> IrqRxToR { + IrqRxToR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&self) -> IrqTxR { + IrqTxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&self) -> IrqTxStatusR { + IrqTxStatusR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&self) -> IrqTxEmptyR { + IrqTxEmptyR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&self) -> IrqTxCtsR { + IrqTxCtsR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&mut self) -> IrqRxW<'_, IrqEnbSpec> { + IrqRxW::new(self, 0) + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&mut self) -> IrqRxStatusW<'_, IrqEnbSpec> { + IrqRxStatusW::new(self, 1) + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&mut self) -> IrqRxToW<'_, IrqEnbSpec> { + IrqRxToW::new(self, 2) + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&mut self) -> IrqTxW<'_, IrqEnbSpec> { + IrqTxW::new(self, 4) + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&mut self) -> IrqTxStatusW<'_, IrqEnbSpec> { + IrqTxStatusW::new(self, 5) + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&mut self) -> IrqTxEmptyW<'_, IrqEnbSpec> { + IrqTxEmptyW::new(self, 6) + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&mut self) -> IrqTxCtsW<'_, IrqEnbSpec> { + IrqTxCtsW::new(self, 7) + } +} +#[doc = "IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec {} diff --git a/va416xx/va416xx/src/uart0/perid.rs b/va416xx/va416xx/src/uart0/perid.rs new file mode 100644 index 0000000..9f5c112 --- /dev/null +++ b/va416xx/va416xx/src/uart0/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0212_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0212_07e9; +} diff --git a/va416xx/va416xx/src/uart0/rxfifoirqtrg.rs b/va416xx/va416xx/src/uart0/rxfifoirqtrg.rs new file mode 100644 index 0000000..e38d450 --- /dev/null +++ b/va416xx/va416xx/src/uart0/rxfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RxfifoirqtrgSpec {} diff --git a/va416xx/va416xx/src/uart0/rxfifortstrg.rs b/va416xx/va416xx/src/uart0/rxfifortstrg.rs new file mode 100644 index 0000000..370a154 --- /dev/null +++ b/va416xx/va416xx/src/uart0/rxfifortstrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `RXFIFORTSTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFORTSTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifortstrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifortstrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifortstrgSpec; +impl crate::RegisterSpec for RxfifortstrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifortstrg::R`](R) reader structure"] +impl crate::Readable for RxfifortstrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifortstrg::W`](W) writer structure"] +impl crate::Writable for RxfifortstrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RXFIFORTSTRG to value 0"] +impl crate::Resettable for RxfifortstrgSpec {} diff --git a/va416xx/va416xx/src/uart0/rxstatus.rs b/va416xx/va416xx/src/uart0/rxstatus.rs new file mode 100644 index 0000000..1b0ab58 --- /dev/null +++ b/va416xx/va416xx/src/uart0/rxstatus.rs @@ -0,0 +1,90 @@ +#[doc = "Register `RXSTATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RDAVL` reader - Read Data Available"] +pub type RdavlR = crate::BitReader; +#[doc = "Field `RDNFULL` reader - Read Fifo NOT Full"] +pub type RdnfullR = crate::BitReader; +#[doc = "Field `RXBUSY` reader - RX Busy Receiving"] +pub type RxbusyR = crate::BitReader; +#[doc = "Field `RXTO` reader - RX Receive Timeout"] +pub type RxtoR = crate::BitReader; +#[doc = "Field `RXOVR` reader - Read Fifo Overflow"] +pub type RxovrR = crate::BitReader; +#[doc = "Field `RXFRM` reader - RX Framing Error"] +pub type RxfrmR = crate::BitReader; +#[doc = "Field `RXPAR` reader - RX Parity Error"] +pub type RxparR = crate::BitReader; +#[doc = "Field `RXBRK` reader - RX Break Error"] +pub type RxbrkR = crate::BitReader; +#[doc = "Field `RXBUSYBRK` reader - RX Busy Receiving Break"] +pub type RxbusybrkR = crate::BitReader; +#[doc = "Field `RXADDR9` reader - Address Match for 9 bit mode"] +pub type Rxaddr9R = crate::BitReader; +#[doc = "Field `RXRTSN` reader - RX RTSn Output Value"] +pub type RxrtsnR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read Data Available"] + #[inline(always)] + pub fn rdavl(&self) -> RdavlR { + RdavlR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Read Fifo NOT Full"] + #[inline(always)] + pub fn rdnfull(&self) -> RdnfullR { + RdnfullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Busy Receiving"] + #[inline(always)] + pub fn rxbusy(&self) -> RxbusyR { + RxbusyR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RX Receive Timeout"] + #[inline(always)] + pub fn rxto(&self) -> RxtoR { + RxtoR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Read Fifo Overflow"] + #[inline(always)] + pub fn rxovr(&self) -> RxovrR { + RxovrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RX Framing Error"] + #[inline(always)] + pub fn rxfrm(&self) -> RxfrmR { + RxfrmR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RX Parity Error"] + #[inline(always)] + pub fn rxpar(&self) -> RxparR { + RxparR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - RX Break Error"] + #[inline(always)] + pub fn rxbrk(&self) -> RxbrkR { + RxbrkR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX Busy Receiving Break"] + #[inline(always)] + pub fn rxbusybrk(&self) -> RxbusybrkR { + RxbusybrkR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Address Match for 9 bit mode"] + #[inline(always)] + pub fn rxaddr9(&self) -> Rxaddr9R { + Rxaddr9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 15 - RX RTSn Output Value"] + #[inline(always)] + pub fn rxrtsn(&self) -> RxrtsnR { + RxrtsnR::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxstatusSpec; +impl crate::RegisterSpec for RxstatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxstatus::R`](R) reader structure"] +impl crate::Readable for RxstatusSpec {} +#[doc = "`reset()` method sets RXSTATUS to value 0"] +impl crate::Resettable for RxstatusSpec {} diff --git a/va416xx/va416xx/src/uart0/state.rs b/va416xx/va416xx/src/uart0/state.rs new file mode 100644 index 0000000..f8dd56a --- /dev/null +++ b/va416xx/va416xx/src/uart0/state.rs @@ -0,0 +1,17 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of UART Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StateSpec; +impl crate::RegisterSpec for StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for StateSpec {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for StateSpec {} diff --git a/va416xx/va416xx/src/uart0/txbreak.rs b/va416xx/va416xx/src/uart0/txbreak.rs new file mode 100644 index 0000000..d943200 --- /dev/null +++ b/va416xx/va416xx/src/uart0/txbreak.rs @@ -0,0 +1,20 @@ +#[doc = "Register `TXBREAK` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W {} +#[doc = "Break Transmit Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbreak::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxbreakSpec; +impl crate::RegisterSpec for TxbreakSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`txbreak::W`](W) writer structure"] +impl crate::Writable for TxbreakSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TXBREAK to value 0"] +impl crate::Resettable for TxbreakSpec {} diff --git a/va416xx/va416xx/src/uart0/txfifoirqtrg.rs b/va416xx/va416xx/src/uart0/txfifoirqtrg.rs new file mode 100644 index 0000000..ea0e7d3 --- /dev/null +++ b/va416xx/va416xx/src/uart0/txfifoirqtrg.rs @@ -0,0 +1,24 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TxfifoirqtrgSpec {} diff --git a/va416xx/va416xx/src/uart0/txstatus.rs b/va416xx/va416xx/src/uart0/txstatus.rs new file mode 100644 index 0000000..1ad3856 --- /dev/null +++ b/va416xx/va416xx/src/uart0/txstatus.rs @@ -0,0 +1,48 @@ +#[doc = "Register `TXSTATUS` reader"] +pub type R = crate::R; +#[doc = "Field `WRRDY` reader - Write Fifo NOT Full"] +pub type WrrdyR = crate::BitReader; +#[doc = "Field `WRBUSY` reader - Write Fifo Full"] +pub type WrbusyR = crate::BitReader; +#[doc = "Field `TXBUSY` reader - TX Busy Transmitting"] +pub type TxbusyR = crate::BitReader; +#[doc = "Field `WRLOST` reader - Write Data Lost (Fifo Overflow)"] +pub type WrlostR = crate::BitReader; +#[doc = "Field `TXCTSN` reader - TX CTSn Input Value"] +pub type TxctsnR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Write Fifo NOT Full"] + #[inline(always)] + pub fn wrrdy(&self) -> WrrdyR { + WrrdyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write Fifo Full"] + #[inline(always)] + pub fn wrbusy(&self) -> WrbusyR { + WrbusyR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - TX Busy Transmitting"] + #[inline(always)] + pub fn txbusy(&self) -> TxbusyR { + TxbusyR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write Data Lost (Fifo Overflow)"] + #[inline(always)] + pub fn wrlost(&self) -> WrlostR { + WrlostR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 15 - TX CTSn Input Value"] + #[inline(always)] + pub fn txctsn(&self) -> TxctsnR { + TxctsnR::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxstatusSpec; +impl crate::RegisterSpec for TxstatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txstatus::R`](R) reader structure"] +impl crate::Readable for TxstatusSpec {} +#[doc = "`reset()` method sets TXSTATUS to value 0"] +impl crate::Resettable for TxstatusSpec {} diff --git a/va416xx/va416xx/src/utility.rs b/va416xx/va416xx/src/utility.rs new file mode 100644 index 0000000..751c3ce --- /dev/null +++ b/va416xx/va416xx/src/utility.rs @@ -0,0 +1,173 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + synd_data: SyndData, + synd_synd: SyndSynd, + synd_enc_32_44: SyndEnc32_44, + synd_check_32_44_data: SyndCheck32_44Data, + synd_check_32_44_synd: SyndCheck32_44Synd, + rom_trap_address: RomTrapAddress, + rom_trap_synd: RomTrapSynd, + ram_trap_addr0: RamTrapAddr0, + ram_trap_synd0: RamTrapSynd0, + ram_trap_addr1: RamTrapAddr1, + ram_trap_synd1: RamTrapSynd1, + _reserved11: [u8; 0xf4], + synd_enc_32_52: SyndEnc32_52, + synd_check_32_52_data: SyndCheck32_52Data, + synd_check_32_52_synd: SyndCheck32_52Synd, + _reserved14: [u8; 0x0ed0], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Data Register"] + #[inline(always)] + pub const fn synd_data(&self) -> &SyndData { + &self.synd_data + } + #[doc = "0x04 - Syndrome Data Register"] + #[inline(always)] + pub const fn synd_synd(&self) -> &SyndSynd { + &self.synd_synd + } + #[doc = "0x08 - EDAC Encode"] + #[inline(always)] + pub const fn synd_enc_32_44(&self) -> &SyndEnc32_44 { + &self.synd_enc_32_44 + } + #[doc = "0x0c - EDAC Decode Data"] + #[inline(always)] + pub const fn synd_check_32_44_data(&self) -> &SyndCheck32_44Data { + &self.synd_check_32_44_data + } + #[doc = "0x10 - EDAC Decode Syndrome"] + #[inline(always)] + pub const fn synd_check_32_44_synd(&self) -> &SyndCheck32_44Synd { + &self.synd_check_32_44_synd + } + #[doc = "0x14 - ROM EDAC Trap Address"] + #[inline(always)] + pub const fn rom_trap_address(&self) -> &RomTrapAddress { + &self.rom_trap_address + } + #[doc = "0x18 - ROM EDAC Trap Syndrome"] + #[inline(always)] + pub const fn rom_trap_synd(&self) -> &RomTrapSynd { + &self.rom_trap_synd + } + #[doc = "0x1c - RAM0 EDAC Trap Address"] + #[inline(always)] + pub const fn ram_trap_addr0(&self) -> &RamTrapAddr0 { + &self.ram_trap_addr0 + } + #[doc = "0x20 - RAM0 EDAC Trap Syndrome"] + #[inline(always)] + pub const fn ram_trap_synd0(&self) -> &RamTrapSynd0 { + &self.ram_trap_synd0 + } + #[doc = "0x24 - RAM1 EDAC Trap Address"] + #[inline(always)] + pub const fn ram_trap_addr1(&self) -> &RamTrapAddr1 { + &self.ram_trap_addr1 + } + #[doc = "0x28 - RAM1 EDAC Trap Syndrome"] + #[inline(always)] + pub const fn ram_trap_synd1(&self) -> &RamTrapSynd1 { + &self.ram_trap_synd1 + } + #[doc = "0x120 - EDAC Encode"] + #[inline(always)] + pub const fn synd_enc_32_52(&self) -> &SyndEnc32_52 { + &self.synd_enc_32_52 + } + #[doc = "0x124 - EDAC Decode Data"] + #[inline(always)] + pub const fn synd_check_32_52_data(&self) -> &SyndCheck32_52Data { + &self.synd_check_32_52_data + } + #[doc = "0x128 - EDAC Decode Syndrome"] + #[inline(always)] + pub const fn synd_check_32_52_synd(&self) -> &SyndCheck32_52Synd { + &self.synd_check_32_52_synd + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "SYND_DATA (rw) register accessor: Data Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_data`] module"] +#[doc(alias = "SYND_DATA")] +pub type SyndData = crate::Reg; +#[doc = "Data Register"] +pub mod synd_data; +#[doc = "SYND_SYND (rw) register accessor: Syndrome Data Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_synd`] module"] +#[doc(alias = "SYND_SYND")] +pub type SyndSynd = crate::Reg; +#[doc = "Syndrome Data Register"] +pub mod synd_synd; +#[doc = "SYND_ENC_32_44 (rw) register accessor: EDAC Encode\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32_44::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_enc_32_44::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32_44`] module"] +#[doc(alias = "SYND_ENC_32_44")] +pub type SyndEnc32_44 = crate::Reg; +#[doc = "EDAC Encode"] +pub mod synd_enc_32_44; +#[doc = "SYND_CHECK_32_44_DATA (r) register accessor: EDAC Decode Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_44_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_44_data`] module"] +#[doc(alias = "SYND_CHECK_32_44_DATA")] +pub type SyndCheck32_44Data = crate::Reg; +#[doc = "EDAC Decode Data"] +pub mod synd_check_32_44_data; +#[doc = "SYND_CHECK_32_44_SYND (r) register accessor: EDAC Decode Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_44_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_44_synd`] module"] +#[doc(alias = "SYND_CHECK_32_44_SYND")] +pub type SyndCheck32_44Synd = crate::Reg; +#[doc = "EDAC Decode Syndrome"] +pub mod synd_check_32_44_synd; +#[doc = "ROM_TRAP_ADDRESS (rw) register accessor: ROM EDAC Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_address`] module"] +#[doc(alias = "ROM_TRAP_ADDRESS")] +pub type RomTrapAddress = crate::Reg; +#[doc = "ROM EDAC Trap Address"] +pub mod rom_trap_address; +#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM EDAC Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`] module"] +#[doc(alias = "ROM_TRAP_SYND")] +pub type RomTrapSynd = crate::Reg; +#[doc = "ROM EDAC Trap Syndrome"] +pub mod rom_trap_synd; +#[doc = "RAM_TRAP_ADDR0 (rw) register accessor: RAM0 EDAC Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_trap_addr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_trap_addr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_trap_addr0`] module"] +#[doc(alias = "RAM_TRAP_ADDR0")] +pub type RamTrapAddr0 = crate::Reg; +#[doc = "RAM0 EDAC Trap Address"] +pub mod ram_trap_addr0; +#[doc = "RAM_TRAP_SYND0 (rw) register accessor: RAM0 EDAC Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_trap_synd0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_trap_synd0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_trap_synd0`] module"] +#[doc(alias = "RAM_TRAP_SYND0")] +pub type RamTrapSynd0 = crate::Reg; +#[doc = "RAM0 EDAC Trap Syndrome"] +pub mod ram_trap_synd0; +#[doc = "RAM_TRAP_ADDR1 (rw) register accessor: RAM1 EDAC Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_trap_addr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_trap_addr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_trap_addr1`] module"] +#[doc(alias = "RAM_TRAP_ADDR1")] +pub type RamTrapAddr1 = crate::Reg; +#[doc = "RAM1 EDAC Trap Address"] +pub mod ram_trap_addr1; +#[doc = "RAM_TRAP_SYND1 (rw) register accessor: RAM1 EDAC Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_trap_synd1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_trap_synd1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_trap_synd1`] module"] +#[doc(alias = "RAM_TRAP_SYND1")] +pub type RamTrapSynd1 = crate::Reg; +#[doc = "RAM1 EDAC Trap Syndrome"] +pub mod ram_trap_synd1; +#[doc = "SYND_ENC_32_52 (r) register accessor: EDAC Encode\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32_52::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32_52`] module"] +#[doc(alias = "SYND_ENC_32_52")] +pub type SyndEnc32_52 = crate::Reg; +#[doc = "EDAC Encode"] +pub mod synd_enc_32_52; +#[doc = "SYND_CHECK_32_52_DATA (r) register accessor: EDAC Decode Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_data`] module"] +#[doc(alias = "SYND_CHECK_32_52_DATA")] +pub type SyndCheck32_52Data = crate::Reg; +#[doc = "EDAC Decode Data"] +pub mod synd_check_32_52_data; +#[doc = "SYND_CHECK_32_52_SYND (r) register accessor: EDAC Decode Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_synd`] module"] +#[doc(alias = "SYND_CHECK_32_52_SYND")] +pub type SyndCheck32_52Synd = crate::Reg; +#[doc = "EDAC Decode Syndrome"] +pub mod synd_check_32_52_synd; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/va416xx/src/utility/perid.rs b/va416xx/va416xx/src/utility/perid.rs new file mode 100644 index 0000000..89f37f1 --- /dev/null +++ b/va416xx/va416xx/src/utility/perid.rs @@ -0,0 +1,19 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0284_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0284_07e9; +} diff --git a/va416xx/va416xx/src/utility/ram_trap_addr0.rs b/va416xx/va416xx/src/utility/ram_trap_addr0.rs new file mode 100644 index 0000000..f8ee41f --- /dev/null +++ b/va416xx/va416xx/src/utility/ram_trap_addr0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `RAM_TRAP_ADDR0` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_TRAP_ADDR0` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - Address bits for trap match"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address bits for trap match"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; +#[doc = "Field `ENABLE` reader - Enable Trap mode"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable Trap mode"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits >> 2) & 0x1fff_ffff) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&mut self) -> AddrW<'_, RamTrapAddr0Spec> { + AddrW::new(self, 2) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, RamTrapAddr0Spec> { + EnableW::new(self, 31) + } +} +#[doc = "RAM0 EDAC Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_trap_addr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_trap_addr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamTrapAddr0Spec; +impl crate::RegisterSpec for RamTrapAddr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_trap_addr0::R`](R) reader structure"] +impl crate::Readable for RamTrapAddr0Spec {} +#[doc = "`write(|w| ..)` method takes [`ram_trap_addr0::W`](W) writer structure"] +impl crate::Writable for RamTrapAddr0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RAM_TRAP_ADDR0 to value 0"] +impl crate::Resettable for RamTrapAddr0Spec {} diff --git a/va416xx/va416xx/src/utility/ram_trap_addr1.rs b/va416xx/va416xx/src/utility/ram_trap_addr1.rs new file mode 100644 index 0000000..d2d91f7 --- /dev/null +++ b/va416xx/va416xx/src/utility/ram_trap_addr1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `RAM_TRAP_ADDR1` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_TRAP_ADDR1` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - Address bits for trap match"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address bits for trap match"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; +#[doc = "Field `ENABLE` reader - Enable Trap mode"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable Trap mode"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits >> 2) & 0x1fff_ffff) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&mut self) -> AddrW<'_, RamTrapAddr1Spec> { + AddrW::new(self, 2) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, RamTrapAddr1Spec> { + EnableW::new(self, 31) + } +} +#[doc = "RAM1 EDAC Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_trap_addr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_trap_addr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamTrapAddr1Spec; +impl crate::RegisterSpec for RamTrapAddr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_trap_addr1::R`](R) reader structure"] +impl crate::Readable for RamTrapAddr1Spec {} +#[doc = "`write(|w| ..)` method takes [`ram_trap_addr1::W`](W) writer structure"] +impl crate::Writable for RamTrapAddr1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RAM_TRAP_ADDR1 to value 0"] +impl crate::Resettable for RamTrapAddr1Spec {} diff --git a/va416xx/va416xx/src/utility/ram_trap_synd0.rs b/va416xx/va416xx/src/utility/ram_trap_synd0.rs new file mode 100644 index 0000000..a8b7ca9 --- /dev/null +++ b/va416xx/va416xx/src/utility/ram_trap_synd0.rs @@ -0,0 +1,49 @@ +#[doc = "Register `RAM_TRAP_SYND0` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_TRAP_SYND0` writer"] +pub type W = crate::W; +#[doc = "Field `RAM_SYND_7_0` reader - 6-bit syndrome value for bits 15-0"] +pub type RamSynd7_0R = crate::FieldReader; +#[doc = "Field `RAM_SYND_7_0` writer - 6-bit syndrome value for bits 15-0"] +pub type RamSynd7_0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `RAM_SYND_31_16` reader - 6-bit syndrome value for bits 31-16"] +pub type RamSynd31_16R = crate::FieldReader; +#[doc = "Field `RAM_SYND_31_16` writer - 6-bit syndrome value for bits 31-16"] +pub type RamSynd31_16W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&self) -> RamSynd7_0R { + RamSynd7_0R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&self) -> RamSynd31_16R { + RamSynd31_16R::new(((self.bits >> 6) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&mut self) -> RamSynd7_0W<'_, RamTrapSynd0Spec> { + RamSynd7_0W::new(self, 0) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&mut self) -> RamSynd31_16W<'_, RamTrapSynd0Spec> { + RamSynd31_16W::new(self, 6) + } +} +#[doc = "RAM0 EDAC Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_trap_synd0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_trap_synd0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamTrapSynd0Spec; +impl crate::RegisterSpec for RamTrapSynd0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_trap_synd0::R`](R) reader structure"] +impl crate::Readable for RamTrapSynd0Spec {} +#[doc = "`write(|w| ..)` method takes [`ram_trap_synd0::W`](W) writer structure"] +impl crate::Writable for RamTrapSynd0Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RAM_TRAP_SYND0 to value 0"] +impl crate::Resettable for RamTrapSynd0Spec {} diff --git a/va416xx/va416xx/src/utility/ram_trap_synd1.rs b/va416xx/va416xx/src/utility/ram_trap_synd1.rs new file mode 100644 index 0000000..7dd7e3b --- /dev/null +++ b/va416xx/va416xx/src/utility/ram_trap_synd1.rs @@ -0,0 +1,49 @@ +#[doc = "Register `RAM_TRAP_SYND1` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_TRAP_SYND1` writer"] +pub type W = crate::W; +#[doc = "Field `RAM_SYND_7_0` reader - 6-bit syndrome value for bits 15-0"] +pub type RamSynd7_0R = crate::FieldReader; +#[doc = "Field `RAM_SYND_7_0` writer - 6-bit syndrome value for bits 15-0"] +pub type RamSynd7_0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `RAM_SYND_31_16` reader - 6-bit syndrome value for bits 31-16"] +pub type RamSynd31_16R = crate::FieldReader; +#[doc = "Field `RAM_SYND_31_16` writer - 6-bit syndrome value for bits 31-16"] +pub type RamSynd31_16W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&self) -> RamSynd7_0R { + RamSynd7_0R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&self) -> RamSynd31_16R { + RamSynd31_16R::new(((self.bits >> 6) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&mut self) -> RamSynd7_0W<'_, RamTrapSynd1Spec> { + RamSynd7_0W::new(self, 0) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&mut self) -> RamSynd31_16W<'_, RamTrapSynd1Spec> { + RamSynd31_16W::new(self, 6) + } +} +#[doc = "RAM1 EDAC Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_trap_synd1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_trap_synd1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamTrapSynd1Spec; +impl crate::RegisterSpec for RamTrapSynd1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_trap_synd1::R`](R) reader structure"] +impl crate::Readable for RamTrapSynd1Spec {} +#[doc = "`write(|w| ..)` method takes [`ram_trap_synd1::W`](W) writer structure"] +impl crate::Writable for RamTrapSynd1Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets RAM_TRAP_SYND1 to value 0"] +impl crate::Resettable for RamTrapSynd1Spec {} diff --git a/va416xx/va416xx/src/utility/rom_trap_address.rs b/va416xx/va416xx/src/utility/rom_trap_address.rs new file mode 100644 index 0000000..7d0843d --- /dev/null +++ b/va416xx/va416xx/src/utility/rom_trap_address.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ROM_TRAP_ADDRESS` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_TRAP_ADDRESS` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - Address bits for trap match"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address bits for trap match"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; +#[doc = "Field `ENABLE` reader - Enable Trap mode"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable Trap mode"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits >> 2) & 0x1fff_ffff) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&mut self) -> AddrW<'_, RomTrapAddressSpec> { + AddrW::new(self, 2) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&mut self) -> EnableW<'_, RomTrapAddressSpec> { + EnableW::new(self, 31) + } +} +#[doc = "ROM EDAC Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomTrapAddressSpec; +impl crate::RegisterSpec for RomTrapAddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_trap_address::R`](R) reader structure"] +impl crate::Readable for RomTrapAddressSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_trap_address::W`](W) writer structure"] +impl crate::Writable for RomTrapAddressSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ROM_TRAP_ADDRESS to value 0"] +impl crate::Resettable for RomTrapAddressSpec {} diff --git a/va416xx/va416xx/src/utility/rom_trap_synd.rs b/va416xx/va416xx/src/utility/rom_trap_synd.rs new file mode 100644 index 0000000..ab6c9b8 --- /dev/null +++ b/va416xx/va416xx/src/utility/rom_trap_synd.rs @@ -0,0 +1,49 @@ +#[doc = "Register `ROM_TRAP_SYND` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_TRAP_SYND` writer"] +pub type W = crate::W; +#[doc = "Field `ROM_SYND_7_0` reader - 6-bit syndrome value for bits 15-0"] +pub type RomSynd7_0R = crate::FieldReader; +#[doc = "Field `ROM_SYND_7_0` writer - 6-bit syndrome value for bits 15-0"] +pub type RomSynd7_0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `R0M_SYND_31_16` reader - 6-bit syndrome value for bits 31-16"] +pub type R0mSynd31_16R = crate::FieldReader; +#[doc = "Field `R0M_SYND_31_16` writer - 6-bit syndrome value for bits 31-16"] +pub type R0mSynd31_16W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn rom_synd_7_0(&self) -> RomSynd7_0R { + RomSynd7_0R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn r0m_synd_31_16(&self) -> R0mSynd31_16R { + R0mSynd31_16R::new(((self.bits >> 6) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn rom_synd_7_0(&mut self) -> RomSynd7_0W<'_, RomTrapSyndSpec> { + RomSynd7_0W::new(self, 0) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn r0m_synd_31_16(&mut self) -> R0mSynd31_16W<'_, RomTrapSyndSpec> { + R0mSynd31_16W::new(self, 6) + } +} +#[doc = "ROM EDAC Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomTrapSyndSpec; +impl crate::RegisterSpec for RomTrapSyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_trap_synd::R`](R) reader structure"] +impl crate::Readable for RomTrapSyndSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_trap_synd::W`](W) writer structure"] +impl crate::Writable for RomTrapSyndSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets ROM_TRAP_SYND to value 0"] +impl crate::Resettable for RomTrapSyndSpec {} diff --git a/va416xx/va416xx/src/utility/synd_check_32_44_data.rs b/va416xx/va416xx/src/utility/synd_check_32_44_data.rs new file mode 100644 index 0000000..77338e3 --- /dev/null +++ b/va416xx/va416xx/src/utility/synd_check_32_44_data.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_CHECK_32_44_DATA` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EDAC Decode Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_44_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_44DataSpec; +impl crate::RegisterSpec for SyndCheck32_44DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_44_data::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_44DataSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_44_DATA to value 0"] +impl crate::Resettable for SyndCheck32_44DataSpec {} diff --git a/va416xx/va416xx/src/utility/synd_check_32_44_synd.rs b/va416xx/va416xx/src/utility/synd_check_32_44_synd.rs new file mode 100644 index 0000000..e49c635 --- /dev/null +++ b/va416xx/va416xx/src/utility/synd_check_32_44_synd.rs @@ -0,0 +1,34 @@ +#[doc = "Register `SYND_CHECK_32_44_SYND` reader"] +pub type R = crate::R; +#[doc = "Field `SYND_CHECK_32_44_SYND` reader - Correct syndrome value"] +pub type SyndCheck32_44SyndR = crate::FieldReader; +#[doc = "Field `SBE` reader - Single bit error detect status"] +pub type SbeR = crate::FieldReader; +#[doc = "Field `MBE` reader - Multiple bit error detect status"] +pub type MbeR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Correct syndrome value"] + #[inline(always)] + pub fn synd_check_32_44_synd(&self) -> SyndCheck32_44SyndR { + SyndCheck32_44SyndR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:13 - Single bit error detect status"] + #[inline(always)] + pub fn sbe(&self) -> SbeR { + SbeR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Multiple bit error detect status"] + #[inline(always)] + pub fn mbe(&self) -> MbeR { + MbeR::new(((self.bits >> 14) & 3) as u8) + } +} +#[doc = "EDAC Decode Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_44_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_44SyndSpec; +impl crate::RegisterSpec for SyndCheck32_44SyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_44_synd::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_44SyndSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_44_SYND to value 0"] +impl crate::Resettable for SyndCheck32_44SyndSpec {} diff --git a/va416xx/va416xx/src/utility/synd_check_32_52_data.rs b/va416xx/va416xx/src/utility/synd_check_32_52_data.rs new file mode 100644 index 0000000..52046b6 --- /dev/null +++ b/va416xx/va416xx/src/utility/synd_check_32_52_data.rs @@ -0,0 +1,17 @@ +#[doc = "Register `SYND_CHECK_32_52_DATA` reader"] +pub type R = crate::R; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EDAC Decode Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_52DataSpec; +impl crate::RegisterSpec for SyndCheck32_52DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_52_data::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_52DataSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_52_DATA to value 0"] +impl crate::Resettable for SyndCheck32_52DataSpec {} diff --git a/va416xx/va416xx/src/utility/synd_check_32_52_synd.rs b/va416xx/va416xx/src/utility/synd_check_32_52_synd.rs new file mode 100644 index 0000000..5af3a5a --- /dev/null +++ b/va416xx/va416xx/src/utility/synd_check_32_52_synd.rs @@ -0,0 +1,34 @@ +#[doc = "Register `SYND_CHECK_32_52_SYND` reader"] +pub type R = crate::R; +#[doc = "Field `SYND_CHECK_32_52_SYND` reader - Corrected syndrome value"] +pub type SyndCheck32_52SyndR = crate::FieldReader; +#[doc = "Field `SBE` reader - Single bit error detect status"] +pub type SbeR = crate::FieldReader; +#[doc = "Field `MBE` reader - Multiple bit error detect status"] +pub type MbeR = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - Corrected syndrome value"] + #[inline(always)] + pub fn synd_check_32_52_synd(&self) -> SyndCheck32_52SyndR { + SyndCheck32_52SyndR::new(self.bits & 0x000f_ffff) + } + #[doc = "Bits 24:27 - Single bit error detect status"] + #[inline(always)] + pub fn sbe(&self) -> SbeR { + SbeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Multiple bit error detect status"] + #[inline(always)] + pub fn mbe(&self) -> MbeR { + MbeR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "EDAC Decode Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_52SyndSpec; +impl crate::RegisterSpec for SyndCheck32_52SyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_52_synd::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_52SyndSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_52_SYND to value 0"] +impl crate::Resettable for SyndCheck32_52SyndSpec {} diff --git a/va416xx/va416xx/src/utility/synd_data.rs b/va416xx/va416xx/src/utility/synd_data.rs new file mode 100644 index 0000000..68c6407 --- /dev/null +++ b/va416xx/va416xx/src/utility/synd_data.rs @@ -0,0 +1,24 @@ +#[doc = "Register `SYND_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `SYND_DATA` writer"] +pub type W = crate::W; +#[cfg(feature = "debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndDataSpec; +impl crate::RegisterSpec for SyndDataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_data::R`](R) reader structure"] +impl crate::Readable for SyndDataSpec {} +#[doc = "`write(|w| ..)` method takes [`synd_data::W`](W) writer structure"] +impl crate::Writable for SyndDataSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SYND_DATA to value 0"] +impl crate::Resettable for SyndDataSpec {} diff --git a/va416xx/va416xx/src/utility/synd_enc_32_44.rs b/va416xx/va416xx/src/utility/synd_enc_32_44.rs new file mode 100644 index 0000000..4511611 --- /dev/null +++ b/va416xx/va416xx/src/utility/synd_enc_32_44.rs @@ -0,0 +1,49 @@ +#[doc = "Register `SYND_ENC_32_44` reader"] +pub type R = crate::R; +#[doc = "Register `SYND_ENC_32_44` writer"] +pub type W = crate::W; +#[doc = "Field `SYND_ENC_7_0` reader - Computed syndrome value for bits 15-0"] +pub type SyndEnc7_0R = crate::FieldReader; +#[doc = "Field `SYND_ENC_7_0` writer - Computed syndrome value for bits 15-0"] +pub type SyndEnc7_0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SYND_ENC_31_16` reader - Computed syndrome value for bits 31-16"] +pub type SyndEnc31_16R = crate::FieldReader; +#[doc = "Field `SYND_ENC_31_16` writer - Computed syndrome value for bits 31-16"] +pub type SyndEnc31_16W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Computed syndrome value for bits 15-0"] + #[inline(always)] + pub fn synd_enc_7_0(&self) -> SyndEnc7_0R { + SyndEnc7_0R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Computed syndrome value for bits 31-16"] + #[inline(always)] + pub fn synd_enc_31_16(&self) -> SyndEnc31_16R { + SyndEnc31_16R::new(((self.bits >> 6) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Computed syndrome value for bits 15-0"] + #[inline(always)] + pub fn synd_enc_7_0(&mut self) -> SyndEnc7_0W<'_, SyndEnc32_44Spec> { + SyndEnc7_0W::new(self, 0) + } + #[doc = "Bits 6:11 - Computed syndrome value for bits 31-16"] + #[inline(always)] + pub fn synd_enc_31_16(&mut self) -> SyndEnc31_16W<'_, SyndEnc32_44Spec> { + SyndEnc31_16W::new(self, 6) + } +} +#[doc = "EDAC Encode\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32_44::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_enc_32_44::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndEnc32_44Spec; +impl crate::RegisterSpec for SyndEnc32_44Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_enc_32_44::R`](R) reader structure"] +impl crate::Readable for SyndEnc32_44Spec {} +#[doc = "`write(|w| ..)` method takes [`synd_enc_32_44::W`](W) writer structure"] +impl crate::Writable for SyndEnc32_44Spec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SYND_ENC_32_44 to value 0"] +impl crate::Resettable for SyndEnc32_44Spec {} diff --git a/va416xx/va416xx/src/utility/synd_enc_32_52.rs b/va416xx/va416xx/src/utility/synd_enc_32_52.rs new file mode 100644 index 0000000..3cc532e --- /dev/null +++ b/va416xx/va416xx/src/utility/synd_enc_32_52.rs @@ -0,0 +1,20 @@ +#[doc = "Register `SYND_ENC_32_52` reader"] +pub type R = crate::R; +#[doc = "Field `SYND_ENC_32_52` reader - Computed syndrome value for bits 15-0"] +pub type SyndEnc32_52R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - Computed syndrome value for bits 15-0"] + #[inline(always)] + pub fn synd_enc_32_52(&self) -> SyndEnc32_52R { + SyndEnc32_52R::new(self.bits & 0x000f_ffff) + } +} +#[doc = "EDAC Encode\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32_52::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndEnc32_52Spec; +impl crate::RegisterSpec for SyndEnc32_52Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_enc_32_52::R`](R) reader structure"] +impl crate::Readable for SyndEnc32_52Spec {} +#[doc = "`reset()` method sets SYND_ENC_32_52 to value 0"] +impl crate::Resettable for SyndEnc32_52Spec {} diff --git a/va416xx/va416xx/src/utility/synd_synd.rs b/va416xx/va416xx/src/utility/synd_synd.rs new file mode 100644 index 0000000..d2a2bc9 --- /dev/null +++ b/va416xx/va416xx/src/utility/synd_synd.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SYND_SYND` reader"] +pub type R = crate::R; +#[doc = "Register `SYND_SYND` writer"] +pub type W = crate::W; +#[doc = "Field `SYND_SYND` reader - Provides bits 11:0 for syndrome, 2x6-bit"] +pub type SyndSyndR = crate::FieldReader; +#[doc = "Field `SYND_SYND` writer - Provides bits 11:0 for syndrome, 2x6-bit"] +pub type SyndSyndW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - Provides bits 11:0 for syndrome, 2x6-bit"] + #[inline(always)] + pub fn synd_synd(&self) -> SyndSyndR { + SyndSyndR::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Provides bits 11:0 for syndrome, 2x6-bit"] + #[inline(always)] + pub fn synd_synd(&mut self) -> SyndSyndW<'_, SyndSyndSpec> { + SyndSyndW::new(self, 0) + } +} +#[doc = "Syndrome Data Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_synd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_synd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndSyndSpec; +impl crate::RegisterSpec for SyndSyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_synd::R`](R) reader structure"] +impl crate::Readable for SyndSyndSpec {} +#[doc = "`write(|w| ..)` method takes [`synd_synd::W`](W) writer structure"] +impl crate::Writable for SyndSyndSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets SYND_SYND to value 0"] +impl crate::Resettable for SyndSyndSpec {} diff --git a/va416xx/va416xx/src/watch_dog.rs b/va416xx/va416xx/src/watch_dog.rs new file mode 100644 index 0000000..9425493 --- /dev/null +++ b/va416xx/va416xx/src/watch_dog.rs @@ -0,0 +1,196 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + wdogload: Wdogload, + wdogvalue: Wdogvalue, + wdogcontrol: Wdogcontrol, + wdogintclr: Wdogintclr, + wdogris: Wdogris, + wdogmis: Wdogmis, + _reserved6: [u8; 0xa8], + wdoglock: Wdoglock, + _reserved7: [u8; 0x0e3c], + wdogitcr: Wdogitcr, + wdogitop: Wdogitop, + _reserved9: [u8; 0xd8], + wdogperiphid0: Wdogperiphid0, + wdogperiphid1: Wdogperiphid1, + wdogperiphid2: Wdogperiphid2, + wdogperiphid3: Wdogperiphid3, + wdogpcellid0: Wdogpcellid0, + wdogpcellid1: Wdogpcellid1, + wdogpcellid2: Wdogpcellid2, + wdogpcellid3: Wdogpcellid3, +} +impl RegisterBlock { + #[doc = "0x00 - Counter Start Value"] + #[inline(always)] + pub const fn wdogload(&self) -> &Wdogload { + &self.wdogload + } + #[doc = "0x04 - Down Counter Value"] + #[inline(always)] + pub const fn wdogvalue(&self) -> &Wdogvalue { + &self.wdogvalue + } + #[doc = "0x08 - Enable for block reset and interrupt"] + #[inline(always)] + pub const fn wdogcontrol(&self) -> &Wdogcontrol { + &self.wdogcontrol + } + #[doc = "0x0c - A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register"] + #[inline(always)] + pub const fn wdogintclr(&self) -> &Wdogintclr { + &self.wdogintclr + } + #[doc = "0x10 - Raw interrupt status"] + #[inline(always)] + pub const fn wdogris(&self) -> &Wdogris { + &self.wdogris + } + #[doc = "0x14 - Interrupt status"] + #[inline(always)] + pub const fn wdogmis(&self) -> &Wdogmis { + &self.wdogmis + } + #[doc = "0xc0 - Lock"] + #[inline(always)] + pub const fn wdoglock(&self) -> &Wdoglock { + &self.wdoglock + } + #[doc = "0xf00 - Integration test control"] + #[inline(always)] + pub const fn wdogitcr(&self) -> &Wdogitcr { + &self.wdogitcr + } + #[doc = "0xf04 - Integration test output set"] + #[inline(always)] + pub const fn wdogitop(&self) -> &Wdogitop { + &self.wdogitop + } + #[doc = "0xfe0 - Peripheral ID"] + #[inline(always)] + pub const fn wdogperiphid0(&self) -> &Wdogperiphid0 { + &self.wdogperiphid0 + } + #[doc = "0xfe4 - Peripheral ID"] + #[inline(always)] + pub const fn wdogperiphid1(&self) -> &Wdogperiphid1 { + &self.wdogperiphid1 + } + #[doc = "0xfe8 - Peripheral ID"] + #[inline(always)] + pub const fn wdogperiphid2(&self) -> &Wdogperiphid2 { + &self.wdogperiphid2 + } + #[doc = "0xfec - Peripheral ID"] + #[inline(always)] + pub const fn wdogperiphid3(&self) -> &Wdogperiphid3 { + &self.wdogperiphid3 + } + #[doc = "0xff0 - PrimeCell ID"] + #[inline(always)] + pub const fn wdogpcellid0(&self) -> &Wdogpcellid0 { + &self.wdogpcellid0 + } + #[doc = "0xff4 - PrimeCell ID"] + #[inline(always)] + pub const fn wdogpcellid1(&self) -> &Wdogpcellid1 { + &self.wdogpcellid1 + } + #[doc = "0xff8 - PrimeCell ID"] + #[inline(always)] + pub const fn wdogpcellid2(&self) -> &Wdogpcellid2 { + &self.wdogpcellid2 + } + #[doc = "0xffc - PrimeCell ID"] + #[inline(always)] + pub const fn wdogpcellid3(&self) -> &Wdogpcellid3 { + &self.wdogpcellid3 + } +} +#[doc = "WDOGLOAD (rw) register accessor: Counter Start Value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogload::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogload::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogload`] module"] +#[doc(alias = "WDOGLOAD")] +pub type Wdogload = crate::Reg; +#[doc = "Counter Start Value"] +pub mod wdogload; +#[doc = "WDOGVALUE (r) register accessor: Down Counter Value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogvalue::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogvalue`] module"] +#[doc(alias = "WDOGVALUE")] +pub type Wdogvalue = crate::Reg; +#[doc = "Down Counter Value"] +pub mod wdogvalue; +#[doc = "WDOGCONTROL (rw) register accessor: Enable for block reset and interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogcontrol::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogcontrol::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogcontrol`] module"] +#[doc(alias = "WDOGCONTROL")] +pub type Wdogcontrol = crate::Reg; +#[doc = "Enable for block reset and interrupt"] +pub mod wdogcontrol; +#[doc = "WDOGINTCLR (rw) register accessor: A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogintclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogintclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogintclr`] module"] +#[doc(alias = "WDOGINTCLR")] +pub type Wdogintclr = crate::Reg; +#[doc = "A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register"] +pub mod wdogintclr; +#[doc = "WDOGRIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogris`] module"] +#[doc(alias = "WDOGRIS")] +pub type Wdogris = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod wdogris; +#[doc = "WDOGMIS (r) register accessor: Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogmis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogmis`] module"] +#[doc(alias = "WDOGMIS")] +pub type Wdogmis = crate::Reg; +#[doc = "Interrupt status"] +pub mod wdogmis; +#[doc = "WDOGLOCK (rw) register accessor: Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`wdoglock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdoglock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdoglock`] module"] +#[doc(alias = "WDOGLOCK")] +pub type Wdoglock = crate::Reg; +#[doc = "Lock"] +pub mod wdoglock; +#[doc = "WDOGITCR (rw) register accessor: Integration test control\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogitcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogitcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogitcr`] module"] +#[doc(alias = "WDOGITCR")] +pub type Wdogitcr = crate::Reg; +#[doc = "Integration test control"] +pub mod wdogitcr; +#[doc = "WDOGITOP (rw) register accessor: Integration test output set\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogitop::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogitop::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogitop`] module"] +#[doc(alias = "WDOGITOP")] +pub type Wdogitop = crate::Reg; +#[doc = "Integration test output set"] +pub mod wdogitop; +#[doc = "WDOGPERIPHID0 (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogperiphid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogperiphid0`] module"] +#[doc(alias = "WDOGPERIPHID0")] +pub type Wdogperiphid0 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid0; +#[doc = "WDOGPERIPHID1 (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogperiphid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogperiphid1`] module"] +#[doc(alias = "WDOGPERIPHID1")] +pub type Wdogperiphid1 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid1; +#[doc = "WDOGPERIPHID2 (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogperiphid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogperiphid2`] module"] +#[doc(alias = "WDOGPERIPHID2")] +pub type Wdogperiphid2 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid2; +#[doc = "WDOGPERIPHID3 (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogperiphid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogperiphid3`] module"] +#[doc(alias = "WDOGPERIPHID3")] +pub type Wdogperiphid3 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid3; +#[doc = "WDOGPCELLID0 (r) register accessor: PrimeCell ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogpcellid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogpcellid0`] module"] +#[doc(alias = "WDOGPCELLID0")] +pub type Wdogpcellid0 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid0; +#[doc = "WDOGPCELLID1 (r) register accessor: PrimeCell ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogpcellid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogpcellid1`] module"] +#[doc(alias = "WDOGPCELLID1")] +pub type Wdogpcellid1 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid1; +#[doc = "WDOGPCELLID2 (r) register accessor: PrimeCell ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogpcellid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogpcellid2`] module"] +#[doc(alias = "WDOGPCELLID2")] +pub type Wdogpcellid2 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid2; +#[doc = "WDOGPCELLID3 (r) register accessor: PrimeCell ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogpcellid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogpcellid3`] module"] +#[doc(alias = "WDOGPCELLID3")] +pub type Wdogpcellid3 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid3; diff --git a/va416xx/va416xx/src/watch_dog/wdogcontrol.rs b/va416xx/va416xx/src/watch_dog/wdogcontrol.rs new file mode 100644 index 0000000..64456c1 --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogcontrol.rs @@ -0,0 +1,49 @@ +#[doc = "Register `WDOGCONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGCONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `INTEN` reader - Enable watchdog interrupt"] +pub type IntenR = crate::BitReader; +#[doc = "Field `INTEN` writer - Enable watchdog interrupt"] +pub type IntenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESEN` reader - Enable watchdog reset output"] +pub type ResenR = crate::BitReader; +#[doc = "Field `RESEN` writer - Enable watchdog reset output"] +pub type ResenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable watchdog interrupt"] + #[inline(always)] + pub fn inten(&self) -> IntenR { + IntenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable watchdog reset output"] + #[inline(always)] + pub fn resen(&self) -> ResenR { + ResenR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable watchdog interrupt"] + #[inline(always)] + pub fn inten(&mut self) -> IntenW<'_, WdogcontrolSpec> { + IntenW::new(self, 0) + } + #[doc = "Bit 1 - Enable watchdog reset output"] + #[inline(always)] + pub fn resen(&mut self) -> ResenW<'_, WdogcontrolSpec> { + ResenW::new(self, 1) + } +} +#[doc = "Enable for block reset and interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogcontrol::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogcontrol::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogcontrolSpec; +impl crate::RegisterSpec for WdogcontrolSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogcontrol::R`](R) reader structure"] +impl crate::Readable for WdogcontrolSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogcontrol::W`](W) writer structure"] +impl crate::Writable for WdogcontrolSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WDOGCONTROL to value 0"] +impl crate::Resettable for WdogcontrolSpec {} diff --git a/va416xx/va416xx/src/watch_dog/wdogintclr.rs b/va416xx/va416xx/src/watch_dog/wdogintclr.rs new file mode 100644 index 0000000..69d07bc --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogintclr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `WDOGINTCLR` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGINTCLR` writer"] +pub type W = crate::W; +#[doc = "Field `CLEAR` reader - Write any value to clear interrupt"] +pub type ClearR = crate::FieldReader; +#[doc = "Field `CLEAR` writer - Write any value to clear interrupt"] +pub type ClearW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Write any value to clear interrupt"] + #[inline(always)] + pub fn clear(&self) -> ClearR { + ClearR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Write any value to clear interrupt"] + #[inline(always)] + pub fn clear(&mut self) -> ClearW<'_, WdogintclrSpec> { + ClearW::new(self, 0) + } +} +#[doc = "A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogintclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogintclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogintclrSpec; +impl crate::RegisterSpec for WdogintclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogintclr::R`](R) reader structure"] +impl crate::Readable for WdogintclrSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogintclr::W`](W) writer structure"] +impl crate::Writable for WdogintclrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WDOGINTCLR to value 0"] +impl crate::Resettable for WdogintclrSpec {} diff --git a/va416xx/va416xx/src/watch_dog/wdogitcr.rs b/va416xx/va416xx/src/watch_dog/wdogitcr.rs new file mode 100644 index 0000000..880b085 --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogitcr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `WDOGITCR` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGITCR` writer"] +pub type W = crate::W; +#[doc = "Field `TEST_MODE_EN` reader - Enable test mode of WDOGINT and WDOGRES"] +pub type TestModeEnR = crate::BitReader; +#[doc = "Field `TEST_MODE_EN` writer - Enable test mode of WDOGINT and WDOGRES"] +pub type TestModeEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable test mode of WDOGINT and WDOGRES"] + #[inline(always)] + pub fn test_mode_en(&self) -> TestModeEnR { + TestModeEnR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable test mode of WDOGINT and WDOGRES"] + #[inline(always)] + pub fn test_mode_en(&mut self) -> TestModeEnW<'_, WdogitcrSpec> { + TestModeEnW::new(self, 0) + } +} +#[doc = "Integration test control\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogitcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogitcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogitcrSpec; +impl crate::RegisterSpec for WdogitcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogitcr::R`](R) reader structure"] +impl crate::Readable for WdogitcrSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogitcr::W`](W) writer structure"] +impl crate::Writable for WdogitcrSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WDOGITCR to value 0"] +impl crate::Resettable for WdogitcrSpec {} diff --git a/va416xx/va416xx/src/watch_dog/wdogitop.rs b/va416xx/va416xx/src/watch_dog/wdogitop.rs new file mode 100644 index 0000000..864ef1f --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogitop.rs @@ -0,0 +1,49 @@ +#[doc = "Register `WDOGITOP` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGITOP` writer"] +pub type W = crate::W; +#[doc = "Field `WDOGRES` reader - Set output value"] +pub type WdogresR = crate::BitReader; +#[doc = "Field `WDOGRES` writer - Set output value"] +pub type WdogresW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDOGINT` reader - Set output value"] +pub type WdogintR = crate::BitReader; +#[doc = "Field `WDOGINT` writer - Set output value"] +pub type WdogintW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set output value"] + #[inline(always)] + pub fn wdogres(&self) -> WdogresR { + WdogresR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set output value"] + #[inline(always)] + pub fn wdogint(&self) -> WdogintR { + WdogintR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Set output value"] + #[inline(always)] + pub fn wdogres(&mut self) -> WdogresW<'_, WdogitopSpec> { + WdogresW::new(self, 0) + } + #[doc = "Bit 1 - Set output value"] + #[inline(always)] + pub fn wdogint(&mut self) -> WdogintW<'_, WdogitopSpec> { + WdogintW::new(self, 1) + } +} +#[doc = "Integration test output set\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogitop::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogitop::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogitopSpec; +impl crate::RegisterSpec for WdogitopSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogitop::R`](R) reader structure"] +impl crate::Readable for WdogitopSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogitop::W`](W) writer structure"] +impl crate::Writable for WdogitopSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WDOGITOP to value 0"] +impl crate::Resettable for WdogitopSpec {} diff --git a/va416xx/va416xx/src/watch_dog/wdogload.rs b/va416xx/va416xx/src/watch_dog/wdogload.rs new file mode 100644 index 0000000..6795201 --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogload.rs @@ -0,0 +1,37 @@ +#[doc = "Register `WDOGLOAD` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGLOAD` writer"] +pub type W = crate::W; +#[doc = "Field `CNT` reader - Count to load"] +pub type CntR = crate::FieldReader; +#[doc = "Field `CNT` writer - Count to load"] +pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Count to load"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Count to load"] + #[inline(always)] + pub fn cnt(&mut self) -> CntW<'_, WdogloadSpec> { + CntW::new(self, 0) + } +} +#[doc = "Counter Start Value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogload::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdogload::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogloadSpec; +impl crate::RegisterSpec for WdogloadSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogload::R`](R) reader structure"] +impl crate::Readable for WdogloadSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogload::W`](W) writer structure"] +impl crate::Writable for WdogloadSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WDOGLOAD to value 0xffff_ffff"] +impl crate::Resettable for WdogloadSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va416xx/va416xx/src/watch_dog/wdoglock.rs b/va416xx/va416xx/src/watch_dog/wdoglock.rs new file mode 100644 index 0000000..e58110b --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdoglock.rs @@ -0,0 +1,35 @@ +#[doc = "Register `WDOGLOCK` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGLOCK` writer"] +pub type W = crate::W; +#[doc = "Field `REG_WR_EN` reader - Register write enable status"] +pub type RegWrEnR = crate::FieldReader; +#[doc = "Field `REG_WR_EN` writer - Register write enable status"] +pub type RegWrEnW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Register write enable status"] + #[inline(always)] + pub fn reg_wr_en(&self) -> RegWrEnR { + RegWrEnR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Register write enable status"] + #[inline(always)] + pub fn reg_wr_en(&mut self) -> RegWrEnW<'_, WdoglockSpec> { + RegWrEnW::new(self, 0) + } +} +#[doc = "Lock\n\nYou can [`read`](crate::Reg::read) this register and get [`wdoglock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdoglock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdoglockSpec; +impl crate::RegisterSpec for WdoglockSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdoglock::R`](R) reader structure"] +impl crate::Readable for WdoglockSpec {} +#[doc = "`write(|w| ..)` method takes [`wdoglock::W`](W) writer structure"] +impl crate::Writable for WdoglockSpec { + type Safety = crate::Unsafe; +} +#[doc = "`reset()` method sets WDOGLOCK to value 0"] +impl crate::Resettable for WdoglockSpec {} diff --git a/va416xx/va416xx/src/watch_dog/wdogmis.rs b/va416xx/va416xx/src/watch_dog/wdogmis.rs new file mode 100644 index 0000000..2662c85 --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogmis.rs @@ -0,0 +1,20 @@ +#[doc = "Register `WDOGMIS` reader"] +pub type R = crate::R; +#[doc = "Field `INTERRUPT` reader - Masked Interrupt Status"] +pub type InterruptR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Masked Interrupt Status"] + #[inline(always)] + pub fn interrupt(&self) -> InterruptR { + InterruptR::new((self.bits & 1) != 0) + } +} +#[doc = "Interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogmis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogmisSpec; +impl crate::RegisterSpec for WdogmisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogmis::R`](R) reader structure"] +impl crate::Readable for WdogmisSpec {} +#[doc = "`reset()` method sets WDOGMIS to value 0"] +impl crate::Resettable for WdogmisSpec {} diff --git a/va416xx/va416xx/src/watch_dog/wdogpcellid0.rs b/va416xx/va416xx/src/watch_dog/wdogpcellid0.rs new file mode 100644 index 0000000..df5eb89 --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogpcellid0.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPCELLID0` reader"] +pub type R = crate::R; +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub type PcellidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PcellidR { + PcellidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogpcellid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogpcellid0Spec; +impl crate::RegisterSpec for Wdogpcellid0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogpcellid0::R`](R) reader structure"] +impl crate::Readable for Wdogpcellid0Spec {} +#[doc = "`reset()` method sets WDOGPCELLID0 to value 0x0d"] +impl crate::Resettable for Wdogpcellid0Spec { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/va416xx/va416xx/src/watch_dog/wdogpcellid1.rs b/va416xx/va416xx/src/watch_dog/wdogpcellid1.rs new file mode 100644 index 0000000..51d134a --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogpcellid1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPCELLID1` reader"] +pub type R = crate::R; +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub type PcellidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PcellidR { + PcellidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogpcellid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogpcellid1Spec; +impl crate::RegisterSpec for Wdogpcellid1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogpcellid1::R`](R) reader structure"] +impl crate::Readable for Wdogpcellid1Spec {} +#[doc = "`reset()` method sets WDOGPCELLID1 to value 0xf0"] +impl crate::Resettable for Wdogpcellid1Spec { + const RESET_VALUE: u32 = 0xf0; +} diff --git a/va416xx/va416xx/src/watch_dog/wdogpcellid2.rs b/va416xx/va416xx/src/watch_dog/wdogpcellid2.rs new file mode 100644 index 0000000..c53aa5f --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogpcellid2.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPCELLID2` reader"] +pub type R = crate::R; +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub type PcellidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PcellidR { + PcellidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogpcellid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogpcellid2Spec; +impl crate::RegisterSpec for Wdogpcellid2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogpcellid2::R`](R) reader structure"] +impl crate::Readable for Wdogpcellid2Spec {} +#[doc = "`reset()` method sets WDOGPCELLID2 to value 0x05"] +impl crate::Resettable for Wdogpcellid2Spec { + const RESET_VALUE: u32 = 0x05; +} diff --git a/va416xx/va416xx/src/watch_dog/wdogpcellid3.rs b/va416xx/va416xx/src/watch_dog/wdogpcellid3.rs new file mode 100644 index 0000000..9432d19 --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogpcellid3.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPCELLID3` reader"] +pub type R = crate::R; +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub type PcellidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PcellidR { + PcellidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogpcellid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogpcellid3Spec; +impl crate::RegisterSpec for Wdogpcellid3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogpcellid3::R`](R) reader structure"] +impl crate::Readable for Wdogpcellid3Spec {} +#[doc = "`reset()` method sets WDOGPCELLID3 to value 0xb1"] +impl crate::Resettable for Wdogpcellid3Spec { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/va416xx/va416xx/src/watch_dog/wdogperiphid0.rs b/va416xx/va416xx/src/watch_dog/wdogperiphid0.rs new file mode 100644 index 0000000..6f4d16f --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogperiphid0.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPERIPHID0` reader"] +pub type R = crate::R; +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub type PeriphidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PeriphidR { + PeriphidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogperiphid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogperiphid0Spec; +impl crate::RegisterSpec for Wdogperiphid0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogperiphid0::R`](R) reader structure"] +impl crate::Readable for Wdogperiphid0Spec {} +#[doc = "`reset()` method sets WDOGPERIPHID0 to value 0x24"] +impl crate::Resettable for Wdogperiphid0Spec { + const RESET_VALUE: u32 = 0x24; +} diff --git a/va416xx/va416xx/src/watch_dog/wdogperiphid1.rs b/va416xx/va416xx/src/watch_dog/wdogperiphid1.rs new file mode 100644 index 0000000..e0b761f --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogperiphid1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPERIPHID1` reader"] +pub type R = crate::R; +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub type PeriphidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PeriphidR { + PeriphidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogperiphid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogperiphid1Spec; +impl crate::RegisterSpec for Wdogperiphid1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogperiphid1::R`](R) reader structure"] +impl crate::Readable for Wdogperiphid1Spec {} +#[doc = "`reset()` method sets WDOGPERIPHID1 to value 0xb8"] +impl crate::Resettable for Wdogperiphid1Spec { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/va416xx/va416xx/src/watch_dog/wdogperiphid2.rs b/va416xx/va416xx/src/watch_dog/wdogperiphid2.rs new file mode 100644 index 0000000..013a22b --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogperiphid2.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPERIPHID2` reader"] +pub type R = crate::R; +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub type PeriphidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PeriphidR { + PeriphidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogperiphid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogperiphid2Spec; +impl crate::RegisterSpec for Wdogperiphid2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogperiphid2::R`](R) reader structure"] +impl crate::Readable for Wdogperiphid2Spec {} +#[doc = "`reset()` method sets WDOGPERIPHID2 to value 0x1b"] +impl crate::Resettable for Wdogperiphid2Spec { + const RESET_VALUE: u32 = 0x1b; +} diff --git a/va416xx/va416xx/src/watch_dog/wdogperiphid3.rs b/va416xx/va416xx/src/watch_dog/wdogperiphid3.rs new file mode 100644 index 0000000..57c2c71 --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogperiphid3.rs @@ -0,0 +1,20 @@ +#[doc = "Register `WDOGPERIPHID3` reader"] +pub type R = crate::R; +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub type PeriphidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PeriphidR { + PeriphidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogperiphid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogperiphid3Spec; +impl crate::RegisterSpec for Wdogperiphid3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogperiphid3::R`](R) reader structure"] +impl crate::Readable for Wdogperiphid3Spec {} +#[doc = "`reset()` method sets WDOGPERIPHID3 to value 0"] +impl crate::Resettable for Wdogperiphid3Spec {} diff --git a/va416xx/va416xx/src/watch_dog/wdogris.rs b/va416xx/va416xx/src/watch_dog/wdogris.rs new file mode 100644 index 0000000..3d7f768 --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogris.rs @@ -0,0 +1,20 @@ +#[doc = "Register `WDOGRIS` reader"] +pub type R = crate::R; +#[doc = "Field `INTERRUPT` reader - Interrupt Status"] +pub type InterruptR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Interrupt Status"] + #[inline(always)] + pub fn interrupt(&self) -> InterruptR { + InterruptR::new((self.bits & 1) != 0) + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogrisSpec; +impl crate::RegisterSpec for WdogrisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogris::R`](R) reader structure"] +impl crate::Readable for WdogrisSpec {} +#[doc = "`reset()` method sets WDOGRIS to value 0"] +impl crate::Resettable for WdogrisSpec {} diff --git a/va416xx/va416xx/src/watch_dog/wdogvalue.rs b/va416xx/va416xx/src/watch_dog/wdogvalue.rs new file mode 100644 index 0000000..843338f --- /dev/null +++ b/va416xx/va416xx/src/watch_dog/wdogvalue.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGVALUE` reader"] +pub type R = crate::R; +#[doc = "Field `CNT` reader - Actual Count"] +pub type CntR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Actual Count"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new(self.bits) + } +} +#[doc = "Down Counter Value\n\nYou can [`read`](crate::Reg::read) this register and get [`wdogvalue::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogvalueSpec; +impl crate::RegisterSpec for WdogvalueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogvalue::R`](R) reader structure"] +impl crate::Readable for WdogvalueSpec {} +#[doc = "`reset()` method sets WDOGVALUE to value 0xffff_ffff"] +impl crate::Resettable for WdogvalueSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va416xx/va416xx/svd/va416xx-patch.yml b/va416xx/va416xx/svd/va416xx-patch.yml new file mode 100644 index 0000000..3eae97a --- /dev/null +++ b/va416xx/va416xx/svd/va416xx-patch.yml @@ -0,0 +1,8 @@ +_svd: va416xx.svd + +# Read-only access for a write-only register does not really make sense.. +DMA: + CFG: + _modify: + MASTER_ENABLE: + access: read-write diff --git a/va416xx/va416xx/svd/va416xx.svd b/va416xx/va416xx/svd/va416xx.svd new file mode 100644 index 0000000..8427204 --- /dev/null +++ b/va416xx/va416xx/svd/va416xx.svd @@ -0,0 +1,12884 @@ + + + VORAGO TECHNOLOGIES + SST + va416xx + M4 + 1.3 + + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 100MHz + + VORAGO Technologies \n +\n +----------------------------------------------------------------------------\n + Copyright (c) 2013-2020 VORAGO Technologies\n +\n + BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n + AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n +\n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n + FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n + + + CM4 + r0p1 + little + false + true + 4 + false + + system_va416xx + VOR_ + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + CLKGEN + 1.0 + Clock Generation Peripheral + 0x40006000 + + 0 + 0x00000100 + registers + + + LoCLK + 45 + + + + CTRL0 + Clock Generation Module Control Register 0 + 0x000 + 0x00000030 + + + SYS_CLK_LOST_DET_EN + Enable the circuit that detects loss of SYS_CLK + [31:31] + + + PLL_RESET + Writing this bit to 1 puts the PLL into reset + [30:30] + + + CLK_DIV_SEL + Selects the PLL out divider to divide by 1/2/4/8 + [29:28] + + + PLL_CLKR + PLL Symbol; selects the values 1-16 for the reference divider + [27:24] + + + PLL_CLKF + PLL Symbol; selects the values 1-64 for the multiplication factor + [23:18] + + + PLL_CLKOD + PLL Symbol; selects the values 1-16 for the post VCO divider + [17:14] + + + PLL_BWADJ + PLL Symbol; selects the values 1-64 for the bandwidth divider + [13:8] + + + PLL_TEST + PLL Symbol; Reference-to-counters-to-output bypass when high + [7:7] + + + PLL_BYPASS + PLL Symbol; reference-to-output bypass when high + [6:6] + + + PLL_PWDN + PLL Symbol; power down when high + [5:5] + + + PLL_INTFB + PLL Symbol; select internal feedback path when high rather than FCLK + [4:4] + + + CLKSEL_SYS + Input clock select to PLL + [3:2] + + + REF_CLK_SEL + PLL Reference Clock Select + [1:0] + + + + + STAT + Clock Generation Module Status Register + 0x004 + read-only + 0x00000000 + + + SYSCLKLOST + Set when SYS_CLK has dropped to less than 1MHz + [3:3] + read-only + + + LOCKLOST + LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles + [2:2] + read-only + + + RFSLIP + Reference cycle slip output (CLKOUT frequency high) + [1:1] + read-only + + + FBSLIP + Feedback cycle slip output (CLKOUT frequency low) + [0:0] + read-only + + + + + CTRL1 + Clock Generation Module Control Register 1 + 0x008 + read-write + 0x00000000 + + + ADC_CLK_DIV_SEL + Clock divider select for ADC + [6:5] + + + XTAL_N_EN + Enables XTAL_N output + [4:4] + + + XTAL_EN + Enables the crystal oscillator + [3:3] + + + PLL_LOST_LOCK_DET_EN + Enables the PLL lock lost detection circuit + [2:2] + + + PLL_LCK_DET_REARM + Resets/Rearms the PLL lock detect circuit + [1:1] + + + SYS_CLK_LOST_DET_REARM + Resets/Rearms the SYS_CLK lost detection feature + [0:0] + + + + + + + + SYSCONFIG + 1.0 + System Configuration Peripheral + 0x40010000 + + 0 + 0x00001000 + registers + + + LVD + 46 + + + EDAC_MBE + 76 + + + EDAC_SBE + 77 + + + + RST_STAT + System Reset Status + 0x000 + read-write + 0x00000000 + + + POR + Power On Reset Status + [0:0] + + + EXTRST + External Reset Status + [1:1] + + + SYSRSTREQ + SYSRESETREQ Reset Status + [2:2] + + + LOOKUP + LOOKUP Reset Status + [3:3] + + + WATCHDOG + WATCHDOG Reset Status + [4:4] + + + MEMERR + Memory Error Reset Status + [5:5] + read-only + + + + + RST_CNTL_ROM + ROM Reset Control + 0x004 + 0x0000003F + + + RST_CNTL_RAM0 + RAM Reset Control + 0x008 + 0x0000003F + + + RST_CNTL_RAM1 + RAM Reset Control + 0x00C + 0x0000003F + + + ROM_PROT + ROM Protection Configuration + 0x010 + 0x00000000 + + + WREN + ROM Write Enable Bit + [0:0] + + + + + ROM_SCRUB + ROM Scrub Period Configuration + 0x014 + read-write + 0x00000000 + + + VALUE + Counter divide value + [23:0] + + + RESET + Reset Counter + [31:31] + write-only + + oneToClear + + + + + + RAM0_SCRUB + RAM0 Scrub Period Configuration + 0x018 + + + RAM1_SCRUB + RAM1 Scrub Period Configuration + 0x01C + + + IRQ_ENB + Enable EDAC Error Interrupt Register + 0x020 + read-write + 0x00000000 + + + ROMMBE + ROM Multi Bit Interrupt + [0:0] + + + ROMSBE + ROM Single Bit Interrupt + [1:1] + + + RAM0MBE + RAM0 Multi Bit Interrupt + [2:2] + + + RAM0SBE + RAM0 Single Bit Interrupt + [3:3] + + + RAM1MBE + RAM1 Multi Bit Interrupt + [4:4] + + + RAM1SBE + RAM1 Single Bit Interrupt + [5:5] + + + + + IRQ_RAW + Raw EDAC Error Interrupt Status + 0x024 + read-only + 0x00000000 + + + IRQ_END + Enabled EDAC Error Interrupt Status + 0x028 + read-only + 0x00000000 + + + IRQ_CLR + Clear EDAC Error Interrupt Status + 0x02C + write-only + 0x00000000 + + oneToClear + + + + RAM0_SBE + Count of RAM0 EDAC Single Bit Errors + 0x030 + 0x00000000 + + + COUNT + RAM0 EDAC Single Bit Errors + [15:0] + + + + + RAM1_SBE + Count of RAM1 EDAC Single Bit Errors + 0x034 + + + RAM0_MBE + Count of RAM0 EDAC Multi Bit Errors + 0x038 + 0x00000000 + + + COUNT + RAM0 Multi Bit Errors + [15:0] + + + + + RAM1_MBE + Count of RAM1 EDAC Multi Bit Errors + 0x03C + + + ROM_SBE + Count of ROM EDAC Single Bit Errors + 0x040 + + + ROM_MBE + Count of ROM EDAC Multi Bit Errors + 0x044 + + + ROM_RETRIES + ROM BOOT Retry count + 0x048 + read-only + 0x00000000 + + + COUNT + Count of ROM block Retries + [7:0] + + + + + REFRESH_CONFIG_H + Register Refresh Rate for TMR registers + 0x04C + 0x00000000 + + + DIVCOUNT + Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles + [7:0] + + + TESTMODE + Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly. + [31:30] + + + + + TIM_RESET + TIM Reset Control + 0x050 + 0xFFFFFFFF + + + TIM_RESET + Reset of a given TIMER + [23:0] + + + + + TIM_CLK_ENABLE + TIM Enable Control + 0x054 + 0x00000000 + + + TIMERS + Clock enable of a given TIMER + [23:0] + + + + + PERIPHERAL_RESET + Peripheral Reset Control + 0x058 + 0x7F7BEFFF + + + SPI0 + Resetn of SPI0 + [0:0] + + + SPI1 + Resetn of SPI1 + [1:1] + + + SPI2 + Resetn of SPI2 + [2:2] + + + SPI3 + Resetn of SPI3 + [3:3] + + + UART0 + Resetn of UART0 + [4:4] + + + UART1 + Resetn of UART1 + [5:5] + + + UART2 + Resetn of UART2 + [6:6] + + + I2C0 + Resetn of I2C0 + [7:7] + + + I2C1 + Resetn of I2C1 + [8:8] + + + I2C2 + Resetn of I2C2 + [9:9] + + + CAN0 + Resetn of CAN0 + [10:10] + + + CAN1 + Resetn of CAN1 + [11:11] + + + TRNG + Resetn of TRNG + [12:12] + + + ADC + Resetn of ADC + [13:13] + + + DAC + Resetn of DAC + [14:14] + + + DMA + Resetn of DMA + [15:15] + + + EBI + Resetn of EBI + [16:16] + + + ETH + Resetn of Ethernet + [17:17] + + + SPW + Resetn of SpaceWire + [18:18] + + + CLKGEN + RESETn of PLL in Clock Generation Module + [19:19] + + + IRQ + Resetn of IRQ Router + [20:20] + + + IOCONFIG + Resetn of IO CONFIG + [21:21] + + + UTILITY + Resetn of UTILITY peripheral + [22:22] + + + WDOG + Resetn of WDOG + [23:23] + + + PORTA + Resetn of PORTA + [24:24] + + + PORTB + Resetn of PORTB + [25:25] + + + PORTC + Resetn of PORTC + [26:26] + + + PORTD + Resetn of PORTD + [27:27] + + + PORTE + Resetn of PORTE + [28:28] + + + PORTF + Resetn of PORTF + [29:29] + + + PORTG + Resetn of PORTG + [30:30] + + + + + PERIPHERAL_CLK_ENABLE + Peripheral Enable Control + 0x05C + 0x00880000 + + + SPW_M4_CTRL + SPW M4 control register + 0x060 + 0x00030000 + + + LREN + Lockup reset enable + [17:17] + + + SPW_PAD_EN + SPW pad enable + [16:16] + + + REG_WR_KEY + Fuse-analog register writes enabled when key = 0xfeed + [15:0] + + + + + PMU_CTRL + PMU Control Register + 0x064 + 0x00000000 + + + LVL_SLCT + Select the POK detect level + [1:0] + + + + + WAKEUP_CNT + Wakeup Control + 0x068 + 0x00000007 + + + CNTSTRT + Launch SLP mode in analog block + [3:3] + + + WKUP_CNT + Used to set a time to wake up the processor after the device has been put in a low power state + [2:0] + + + + + EBI_CFG0 + EBI Config Register 0 + 0x06C + 0x00000000 + + + ADDRLOW0 + Lower bound address for CEN0 + [7:0] + + + ADDRHIGH0 + Upper bound address for CEN0 + [15:8] + + + CFGREADCYCLE + Number of cycles for a read - N plus 1 + [18:16] + + + CFGWRITECYCLE + Number of cycles for a write - N plus 1 + [21:19] + + + CFGTURNAROUNDCYCLE + Number of cycles for turnaround - N plus 1 + [24:22] + + + CFGSIZE + 8 bit (0) or 16 bit (1) port size + [25:25] + + + + + EBI_CFG1 + EBI Config Register 1 + 0x070 + 0x00000000 + + + EBI_CFG2 + EBI Config Register 2 + 0x074 + 0x00000000 + + + EBI_CFG3 + EBI Config Register 3 + 0x078 + 0x00000000 + + + ANALOG_CNTL + Analog Control Register + 0x07C + 0x00000000 + + + TMOSC + Test Mode + [0:0] + + + TMPOKDIS + Test Mode + [1:1] + + + TM_ADCMUX_N + Test Mode + [2:2] + + + TM_ADCMUX_P + Test Mode + [3:3] + + + TMRATIO + Test Mode + [4:4] + + + TMATOMUX + Test Mode + [6:5] + + + ADC_STEST + Number of clocks for sample time + [12:9] + + + RCLK_POS_EN + Enable normal test clock + [14:14] + + + RCLK_NEG_EN + Enable inverted test clock + [15:15] + + + APB2CLK_POS_EN + Enable normal APB2CLK for test output + [16:16] + + + APB2CLK_NEG_EN + Enable inverted APB2CLK for test output + [17:17] + + + TM_ANALOG_PD_EN + Enables pull down on analog pads + [18:18] + + + JMP2BOOT + Enables a skip of all delay counters and eFuse read + [19:19] + + SKIPBOOT + Enables a skip of all delay counters, eFuse read, and boot + [20:20] + + + + + SW_CLKDIV10 + Initial SpW Clock Divider Value + 0x080 + read-write + 0x00000009 + + + SW_CLKDIV10 + Defines the initial value for the SpW clock, defaults to divide by ten + [7:0] + + + + + REFRESH_CONFIG_L + Register Refresh Rate for TMR registers + 0x084 + read-write + 0x0000000f + + + DIVCOUNT + Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles + [31:0] + + + + + DAC0_CAL + DAC0 Calibration Register + 0xFD0 + read-only + 0x00000000 + + + DAC0_CAL + DAC0 Calibration bits + [4:0] + + + + + DAC1_CAL + DAC1 Calibration Register + 0xFD4 + read-only + 0x00000000 + + + DAC1_CAL + DAC1 Calibration bits + [4:0] + + + + + ADC_CAL + ADC Calibration Register + 0xFD8 + read-only + 0x00000000 + + + ADC_CAL + ADC Calibration bits + [4:0] + + + + + BG_CAL + Bandgap Calibration Register + 0xFDC + read-only + 0x00000000 + + + BG_CAL + Bandgap Calibration bits + [2:0] + + + + + DREG_CAL + Digital LDO Regulator Calibration Register + 0xFE0 + read-only + 0x00000000 + + + DREG_CAL + Digital LDO Regulator Calibration bits + [8:0] + + + + + AREG_CAL + Analog LDO Regulator Calibration Register + 0xFE4 + read-only + 0x00000000 + + + AREG_CAL + Analog LDO Regulator Calibration bits + [8:0] + + + + + HBO_CAL + Heart Beat OSC Calibration Register + 0xFE8 + read-only + 0x00000000 + + + OSC_CAL + 1MHz OSC Calibration bit + [3:3] + + + HBO_CAL + Heart Beat OSC Calibration bits + [2:0] + + + + + EF_CONFIG + EFuse Config Register + 0xFEC + read-only + 0x0A800C40 + + + ROM_SPEED + Specifies the speed of ROM_SCK + [1:0] + + + ROM_SIZE + Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset + [5:2] + + + ROM_NOCHECK + When set to 1, the ROM check is skipped + [6:6] + + + BOOT_DELAY + Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset + [9:7] + + + ROM_READ + SPI ROM read instruction code + [17:10] + + + ROM_LATENCY + Number of bits of latency from Address until data from the SPI ROM + [22:18] + + + ROM_ADDRESS + ROM Address Mode + [24:23] + + + ROM_DLYCAP + ROM SPI Delayed capture + [25:25] + + + ROM_STATUS + The first data byte from the SPI ROM following an address is taken as a status byte + [26:26] + + + RM + This bit controls the internal RAM read timing and must be maintained at this value + [27:27] + + + WM + This bit controls the internal RAM write timing and must be maintained at this value + [28:28] + + + + + EF_ID0 + EFuse ID0 Register + 0xFF0 + read-only + 0x00000000 + + + EF_ID1 + EFuse ID1 Register + 0xFF4 + read-only + 0x00000000 + + + PROCID + Processor ID Register + 0xFF8 + read-only + 0x040057e3 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028007e9 + + + MANUFACTURER_ID + MANUFACTURER_ID + [11:0] + read-only + + + PERIPHERAL_ID + PERIPHERAL_ID + [23:16] + read-only + + + PERIPHERAL_VER + PERIPHERAL_VER + [31:24] + read-only + + + + + + + DMA + 1.0 + DMA Controller Block + 0x40001000 + + 0 + 0x00001000 + registers + + + DMA_ERROR + 43 + + + DMA_ACTIVE0 + 174 + + + DMA_ACTIVE1 + 175 + + + DMA_ACTIVE2 + 176 + + + DMA_ACTIVE3 + 177 + + + DMA_DONE0 + 178 + + + DMA_DONE1 + 179 + + + DMA_DONE2 + 180 + + + DMA_DONE3 + 181 + + + + STATUS + DMA Status + 0x000 + 0x00000000 + read-only + + + TEST_STATUS + Test Status Logic Included + [31:28] + read-write + + + CHNLS_MINUS1 + Number of Available Channels Minus 1 + [20:16] + + + STATE + Current State of the control state machine + [7:4] + + + MASTER_ENABLE + Enable status of the controller + [0:0] + + + + + CFG + DMA Configuration + 0x004 + write-only + 0x00000000 + + + CHNL_PROT_CTRL + HPROT[3:0] + [7:5] + + + MASTER_ENABLE + PLL Symbol; Feedback cycle slip output (CLKOUT frequency low) + [0:0] + read-only + + + + + CTRL_BASE_PTR + Base Pointer for DMA Control Registers + 0x008 + 0x00000000 + + + CTRL_BASE_PTR + Base Pointer for DMA Control Registers + [31:7] + + + + + ALT_CTRL_BASE_PTR + DMA Channel alternate control data base pointer + 0x00C + read-write + 0x00000000 + + + ALT_CTRL_BASE_PTR + Base Pointer for Alternate DMA Control Register + [31:0] + + + + + WAITONREQ_STATUS + DMA channel wait on request status + 0x010 + read-only + 0x00000000 + + + CH3 + DMA wait on request + [3:3] + read-write + + + CH2 + DMA wait on request + [2:2] + read-write + + + CH1 + DMA wait on request + [1:1] + read-write + + + CH0 + DMA wait on request + [0:0] + read-write + + + + + CHNL_SW_REQUEST + DMA channel software request + 0x014 + write-only + 0x00000000 + + + CH3 + Channel SW request + [3:3] + read-write + + + CH2 + Channel SW request + [2:2] + read-write + + + CH1 + Channel SW request + [1:1] + read-write + + + CH0 + Channel SW request + [0:0] + read-write + + + + + CHNL_USEBURST_SET + DMA channel useburst set + 0x018 + 0x00000000 + + + CH3 + Channel use burst set + [3:3] + read-write + + + CH2 + Channel use burst set + [2:2] + read-write + + + CH1 + Channel use burst set + [1:1] + read-write + + + CH0 + Channel use burst set + [0:0] + read-write + + + + + CHNL_USEBURST_CLR + DMA channel useburst clear + 0x01C + 0x00000000 + + + CH3 + Channel use burst clear + [3:3] + read-write + + + CH2 + Channel use burst clear + [2:2] + read-write + + + CH1 + Channel use burst clear + [1:1] + read-write + + + CH0 + Channel use burst clear + [0:0] + read-write + + + + + CHNL_REQ_MASK_SET + DMA channel request mask set + 0x020 + 0x00000000 + + + CH3 + Channel Request Mask set + [3:3] + read-write + + + CH2 + Channel Request Mask set + [2:2] + read-write + + + CH1 + Channel Request Mask set + [1:1] + read-write + + + CH0 + Channel Request Mask set + [0:0] + read-write + + + + + CHNL_REQ_MASK_CLR + DMA channel request mask clear + 0x024 + 0x00000000 + + + CH3 + Channel Request Mask clear + [3:3] + read-write + + + CH2 + Channel Request Mask clear + [2:2] + read-write + + + CH1 + Channel Request Mask clear + [1:1] + read-write + + + CH0 + Channel Request Mask clear + [0:0] + read-write + + + + + CHNL_ENABLE_SET + DMA channel enable set + 0x028 + 0x00000000 + + + CH3 + Channel Enable set + [3:3] + read-write + + + CH2 + Channel Enable set + [2:2] + read-write + + + CH1 + Channel Enable set + [1:1] + read-write + + + CH0 + Channel Enable set + [0:0] + read-write + + + + + CHNL_ENABLE_CLR + DMA channel enable clear + 0x02C + 0x00000000 + + + CH3 + Channel Enable clear + [3:3] + read-write + + + CH2 + Channel Enable clear + [2:2] + read-write + + + CH1 + Channel Enable clear + [1:1] + read-write + + + CH0 + Channel Enable clear + [0:0] + read-write + + + + + CHNL_PRI_ALT_SET + DMA channel primary alternate set + 0x030 + 0x00000000 + + + CH3 + Channel PRI_ALT set + [3:3] + read-write + + + CH2 + Channel PRI_ALT set + [2:2] + read-write + + + CH1 + Channel PRI_ALT set + [1:1] + read-write + + + CH0 + Channel PRI_ALT set + [0:0] + read-write + + + + + CHNL_PRI_ALT_CLR + DMA channel primary alternate clear + 0x034 + 0x00000000 + + + CH3 + Channel PRI_ALT clear + [3:3] + read-write + + + CH2 + Channel PRI_ALT clear + [2:2] + read-write + + + CH1 + Channel PRI_ALT clear + [1:1] + read-write + + + CH0 + Channel PRI_ALT clear + [0:0] + read-write + + + + + CHNL_PRIORITY_SET + DMA channel priority set + 0x038 + read-write + 0x00000000 + + + CH3 + Channel PRIORITY set + [3:3] + read-write + + + CH2 + Channel PRIORITY set + [2:2] + read-write + + + CH1 + Channel PRIORITY set + [1:1] + read-write + + + CH0 + Channel PRIORITY set + [0:0] + read-write + + + + + CHNL_PRIORITY_CLR + DMA channel priority clear + 0x03C + write-only + 0x00000000 + + + CH3 + Channel PRIORITY clear + [3:3] + write-only + + + CH2 + Channel PRIORITY clear + [2:2] + write-only + + + CH1 + Channel PRIORITY clear + [1:1] + write-only + + + CH0 + Channel PRIORITY clear + [0:0] + write-only + + + + + ERR_CLR + DMA bus error clear + 0x04C + 0x00000000 + + + ERR_CLR + Error Clear + [0:0] + read-write + + + + + INTEGRATION_CFG + DMA integration configuration + 0xE00 + 0x00000000 + + + INT_TEST_EN + Error Clear + [0:0] + read-write + + + + + STALL_STATUS + DMA stall status + 0xE08 + 0x00000000 + + + STALL_STATUS + DMA is stalled + [0:0] + read-only + + + + + DMA_REQ_STATUS + DMA Configuration + 0xE10 + 0x00000000 + + + CH3 + DMA Request Status for this CH + [3:3] + read-write + + + CH2 + DMA Request Status for this CH + [2:2] + read-write + + + CH1 + DMA Request Status for this CH + [1:1] + read-write + + + CH0 + DMA Request Status for this CH + [0:0] + read-write + + + + + DMA_SREQ_STATUS + DMA single request status + 0xE18 + 0x00000000 + + + CH3 + DMA SRequest Status for this CH + [3:3] + read-write + + + CH2 + DMA SRequest Status for this CH + [2:2] + read-write + + + CH1 + DMA SRequest Status for this CH + [1:1] + read-write + + + CH0 + DMA SRequest Status for this CH + [0:0] + read-write + + + + + DMA_DONE_SET + DMA done set + 0xE20 + 0x00000000 + + + CH3 + DMA Done Set for this CH + [3:3] + read-write + + + CH2 + DMA Done Set for this CH + [2:2] + read-write + + + CH1 + DMA Done Set for this CH + [1:1] + read-write + + + CH0 + DMA Done Set for this CH + [0:0] + read-write + + + + + DMA_DONE_CLR + DMA done clear + 0xE24 + 0x00000000 + + + CH3 + DMA Done clear for this CH + [3:3] + read-write + + + CH2 + DMA Done clear for this CH + [2:2] + read-write + + + CH1 + DMA Done clear for this CH + [1:1] + read-write + + + CH0 + DMA Done clear for this CH + [0:0] + read-write + + + + + DMA_ACTIVE_SET + DMA active set + 0xE28 + 0x00000000 + + + CH3 + DMA Active Set + [3:3] + read-write + + + CH2 + DMA Active Set + [2:2] + read-write + + + CH1 + DMA Active Set + [1:1] + read-write + + + CH0 + DMA Active Set + [0:0] + read-write + + + + + DMA_ACTIVE_CLR + DMA active clear + 0xE2C + 0x00000000 + + + CH3 + DMA Active clear + [3:3] + read-write + + + CH2 + DMA Active clear + [2:2] + read-write + + + CH1 + DMA Active clear + [1:1] + read-write + + + CH0 + DMA Active clear + [0:0] + read-write + + + + + ERR_SET + DMA bus error set + 0xE48 + 0x00000000 + + + ERR_SET + Set Error + [0:0] + read-only + + + + + PERIPH_ID_4 + DMA Peripheral ID 4 + 0xFD0 + 0x00000004 + + + BLOCK_COUNT + The Number of 4k Address Blocks Required + [7:4] + + + JEP106_C_CODE + JEP106 + [3:0] + + + + + PERIPH_ID_0 + DMA Peripheral ID 0 + 0xFE0 + 0x00000030 + + + PART_NUMBER_0 + Part Number + [7:0] + + + + + PERIPH_ID_1 + DMA Peripheral ID 1 + 0xFE4 + read-only + 0x000000B2 + + + JEP106_ID_3_0 + Indentity Code + [7:4] + + + PART_NUMBER_1 + Part Number 1 + [3:0] + + + + + PERIPH_ID_2 + DMA Peripheral ID 2 + 0xFE8 + 0x000000BC + + + REVISION + Revision + [7:4] + + + JEDEC_USED + JEDEC + [3:3] + + + JEP106_ID_6_4 + JEP106 + [2:0] + + + + + PERIPH_ID_3 + DMA Peripheral ID 3 + 0xFEC + 0x00000000 + + + MOD_NUMBER + Controller Modifications + [3:0] + + + + + PRIMECELL_ID_0 + DMA PrimeCell ID 0 + 0xFF0 + 0x0000000D + + + PRIMECELL_ID_0 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_1 + DMA PrimeCell ID 1 + 0xFF4 + 0x000000F0 + + + PRIMECELL_ID_1 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_2 + DMA PrimeCell ID 2 + 0xFF8 + 0x00000005 + + + PRIMECELL_ID_2 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_3 + DMA PrimeCell ID 3 + 0xFFC + 0x000000B1 + + + PRIMECELL_ID_3 + PrimeCell Identification + [7:0] + + + + + + + + IOCONFIG + 1.0 + IO Pin Configuration Peripheral + 0x40011000 + + 0 + 0x00001000 + registers + + + + 16 + 4 + PORTA[%s] + PORTA Pin Configuration Register + 0x000 + 0x00000000 + + + FLTTYPE + Input Filter Selectoin + [2:0] + + + SYNC + Synchronize to system clock + 0 + + + DIRECT + Direct input, no synchronization + 1 + + + FILTER1 + Require 2 samples to have the same value + 2 + + + FILTER2 + Require 3 samples to have the same value + 3 + + + FILTER3 + Require 4 samples to have the same value + 4 + + + FILTER4 + Require 5 samples to have the same value + 5 + + + + + FLTCLK + Input Filter Clock Selection + [5:3] + + + INVINP + Input Invert Selection + [6:6] + + + IEWO + Input Enable While Output enabled + [7:7] + + + OPENDRN + Output Open Drain Mode + [8:8] + + + INVOUT + Output Invert Selection + [9:9] + + + PLEVEL + Internal Pull up/down level + [10:10] + + + PEN + Enable Internal Pull up/down + [11:11] + + + PWOA + Enable Pull when output active + [12:12] + + + FUNSEL + Pin Function Selection + [15:13] + + + IODIS + IO Pin Disable + [16:16] + + + + + PORTB[%s] + PORTB Pin Configuration Register + 0x0040 + 0x00000000 + + + PORTC[%s] + PORTC Pin Configuration Register + 0x0080 + 0x00000000 + + + PORTD[%s] + PORTD Pin Configuration Register + 0x00C0 + 0x00000000 + + + PORTE[%s] + PORTE Pin Configuration Register + 0x0100 + 0x00000000 + + + PORTF[%s] + PORTF Pin Configuration Register + 0x0140 + 0x00000000 + + + 8 + 4 + PORTG[%s] + PORTG Pin Configuration Register + 0x0180 + 0x00000000 + + + CLKDIV0 + Clock divide value. 0 will disable the clock + 0x1C0 + read-only + 0x00000000 + + + CLKDIV1 + Clock divide value. 0 will disable the clock + 0x1C4 + read-write + 0x00000000 + + + CLKDIV2 + Clock divide value. 0 will disable the clock + 0x1C8 + read-write + 0x00000000 + + + CLKDIV3 + Clock divide value. 0 will disable the clock + 0x1CC + read-write + 0x00000000 + + + CLKDIV4 + Clock divide value. 0 will disable the clock + 0x1D0 + read-write + 0x00000000 + + + CLKDIV5 + Clock divide value. 0 will disable the clock + 0x1D4 + read-write + 0x00000000 + + + CLKDIV6 + Clock divide value. 0 will disable the clock + 0x1D8 + read-write + 0x00000000 + + + CLKDIV7 + Clock divide value. 0 will disable the clock + 0x1DC + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x028207e9 + + + + + + + UTILITY + 1.0 + Utility Peripheral + 0x40020000 + + 0 + 0x00001000 + registers + + + + SYND_DATA + Data Register + 0x000 + read-write + 0x00000000 + + + SYND_SYND + Syndrome Data Register + 0x004 + read-write + 0x00000000 + + + SYND_SYND + Provides bits 11:0 for syndrome, 2x6-bit + [11:0] + + + + + SYND_ENC_32_44 + EDAC Encode + 0x008 + read-write + 0x00000000 + + + SYND_ENC_31_16 + Computed syndrome value for bits 31-16 + [11:6] + + + SYND_ENC_7_0 + Computed syndrome value for bits 15-0 + [5:0] + + + + + SYND_CHECK_32_44_DATA + EDAC Decode Data + 0x00c + read-only + 0x00000000 + + + SYND_CHECK_32_44_SYND + EDAC Decode Syndrome + 0x010 + read-only + 0x00000000 + + + MBE + Multiple bit error detect status + [15:14] + + + SBE + Single bit error detect status + [13:12] + + + SYND_CHECK_32_44_SYND + Correct syndrome value + [11:0] + + + + + ROM_TRAP_ADDRESS + ROM EDAC Trap Address + 0x014 + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + ROM_TRAP_SYND + ROM EDAC Trap Syndrome + 0x018 + read-write + 0x00000000 + + + R0M_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + ROM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + RAM_TRAP_ADDR0 + RAM0 EDAC Trap Address + 0x01c + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + RAM_TRAP_SYND0 + RAM0 EDAC Trap Syndrome + 0x020 + read-write + 0x00000000 + + + RAM_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + RAM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + RAM_TRAP_ADDR1 + RAM1 EDAC Trap Address + 0x024 + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + RAM_TRAP_SYND1 + RAM1 EDAC Trap Syndrome + 0x028 + read-write + 0x00000000 + + + RAM_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + RAM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + SYND_ENC_32_52 + EDAC Encode + 0x120 + read-only + 0x00000000 + + + SYND_ENC_32_52 + Computed syndrome value for bits 15-0 + [19:0] + + + + + SYND_CHECK_32_52_DATA + EDAC Decode Data + 0x124 + read-only + 0x00000000 + + + SYND_CHECK_32_52_SYND + EDAC Decode Syndrome + 0x128 + read-only + 0x00000000 + + + MBE + Multiple bit error detect status + [31:28] + + + SBE + Single bit error detect status + [27:24] + + + SYND_CHECK_32_52_SYND + Corrected syndrome value + [19:0] + + + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x028407e9 + + + + + + + PORTA + 1.0 + GPIO Peripheral + GPIO + 0x40012000 + + 0 + 0x00000400 + registers + + + PORTA0 + 78 + + + PORTA1 + 79 + + + PORTA2 + 80 + + + PORTA3 + 81 + + + PORTA4 + 82 + + + PORTA5 + 83 + + + PORTA6 + 84 + + + PORTA7 + 85 + + + PORTA8 + 86 + + + PORTA9 + 87 + + + PORTA10 + 88 + + + PORTA11 + 89 + + + PORTA12 + 90 + + + PORTA13 + 91 + + + PORTA14 + 92 + + + PORTA15 + 93 + + + PORTB0 + 94 + + + PORTB1 + 95 + + + PORTB2 + 96 + + + PORTB3 + 97 + + + PORTB4 + 98 + + + PORTB5 + 99 + + + PORTB6 + 100 + + + PORTB7 + 101 + + + PORTB8 + 102 + + + PORTB9 + 103 + + + PORTB10 + 104 + + + PORTB11 + 105 + + + PORTB12 + 106 + + + PORTB13 + 107 + + + PORTB14 + 108 + + + PORTB15 + 109 + + + PORTC0 + 110 + + + PORTC1 + 111 + + + PORTC2 + 112 + + + PORTC3 + 113 + + + PORTC4 + 114 + + + PORTC5 + 115 + + + PORTC6 + 116 + + + PORTC7 + 117 + + + PORTC8 + 118 + + + PORTC9 + 119 + + + PORTC10 + 120 + + + PORTC11 + 121 + + + PORTC12 + 122 + + + PORTC13 + 123 + + + PORTC14 + 124 + + + PORTC15 + 125 + + + PORTD0 + 126 + + + PORTD1 + 127 + + + PORTD2 + 128 + + + PORTD3 + 129 + + + PORTD4 + 130 + + + PORTD5 + 131 + + + PORTD6 + 132 + + + PORTD7 + 133 + + + PORTD8 + 134 + + + PORTD9 + 135 + + + PORTD10 + 136 + + + PORTD11 + 137 + + + PORTD12 + 138 + + + PORTD13 + 139 + + + PORTD14 + 140 + + + PORTD15 + 141 + + + PORTE0 + 142 + + + PORTE1 + 143 + + + PORTE2 + 144 + + + PORTE3 + 145 + + + PORTE4 + 146 + + + PORTE5 + 147 + + + PORTE6 + 148 + + + PORTE7 + 149 + + + PORTE8 + 150 + + + PORTE9 + 151 + + + PORTE10 + 152 + + + PORTE11 + 153 + + + PORTE12 + 154 + + + PORTE13 + 155 + + + PORTE14 + 156 + + + PORTE15 + 157 + + + PORTF0 + 158 + + + PORTF1 + 159 + + + PORTF2 + 160 + + + PORTF3 + 161 + + + PORTF4 + 162 + + + PORTF5 + 163 + + + PORTF6 + 164 + + + PORTF7 + 165 + + + PORTF8 + 166 + + + PORTF9 + 167 + + + PORTF10 + 168 + + + PORTF11 + 169 + + + PORTF12 + 170 + + + PORTF13 + 171 + + + PORTF14 + 172 + + + PORTF15 + 173 + + GPIO + + + DATAIN + Data In Register + 0x000 + read-only + 0x00000000 + + + 4 + 1 + DATAINBYTE[%s] + Data In Register by Byte + DATAIN + 0x000 + 8 + read-only + 0x00000000 + + + DATAINRAW + Data In Raw Register + 0x004 + 0x00000000 + + + DATAINRAWBYTE[%s] + Data In Raw Register by Byte + DATAINRAW + 0x004 + 0x00000000 + + + DATAOUT + Data Out Register + 0x008 + write-only + 0x00000000 + + + 4 + 1 + DATAOUTBYTE[%s] + Data Out Register by Byte + DATAOUT + 0x008 + 8 + write-only + 0x00000000 + + + DATAOUTRAW + Data Out Register + 0x00c + 0x00000000 + + + DATAOUTRAWBYTE[%s] + Data Out Register by Byte + DATAOUTRAW + 0x00c + 0x00000000 + + + SETOUT + Set Out Register + 0x010 + 0x00000000 + + + SETOUTBYTE[%s] + Set Out Register by Byte + SETOUT + 0x010 + 0x00000000 + + + CLROUT + Clear Out Register + 0x014 + 0x00000000 + + + CLROUTBYTE[%s] + Clear Out Register by Byte + CLROUT + 0x014 + 0x00000000 + + + TOGOUT + Toggle Out Register + 0x018 + 0x00000000 + + + TOGOUTBYTE[%s] + Toggle Out Register by Byte + TOGOUT + 0x018 + 0x00000000 + + + DATAMASK + Data mask Register + 0x01c + 0x00000000 + + + 4 + 1 + DATAMASKBYTE[%s] + Data Out Register by Byte + DATAMASK + 0x01c + 8 + 0x00000000 + + + DIR + Direction Register (1:Output, 0:Input) + 0x020 + 0x00000000 + + + DIRBYTE[%s] + Direction Register by Byte + DIR + 0x020 + 0x00000000 + + + PULSE + Pulse Mode Register + 0x024 + 0x00000000 + + + PULSEBYTE[%s] + Pulse Mode Register by Byte + PULSE + 0x024 + 0x00000000 + + + PULSEBASE + Pulse Base Value Register + 0x028 + 0x00000000 + + + PULSEBASEBYTE[%s] + Pulse Base Mode Register by Byte + PULSEBASE + 0x028 + 0x00000000 + + + DELAY1 + Delay1 Register + 0x02c + 0x00000000 + + + DELAY1BYTE[%s] + Delay1 Register by Byte + DELAY1 + 0x02c + 0x00000000 + + + DELAY2 + Delay2 Register + 0x030 + 32 + read-write + 0x00000000 + + + DELAY2BYTE[%s] + Delay2 Register by Byte + DELAY2 + 0x030 + 0x00000000 + + + IRQ_SEN + Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive) + 0x034 + 0x00000000 + + + IRQ_EDGE + Interrupt Both Edge Register (1:Both Edges, 0:Single Edge) + 0x038 + 0x00000000 + + + IRQ_EVT + Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) + 0x03c + 0x00000000 + + + IRQ_ENB + Interrupt Enable Register + 0x040 + 0x00000000 + + + IRQ_RAW + Raw Interrupt Status + 0x044 + read-only + 0x00000000 + + + IRQ_END + Masked Interrupt Status + 0x048 + read-only + 0x00000000 + + + EDGE_STATUS + Edge Status Register + 0x04c + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0x3fc + 32 + read-only + 0x021007e9 + + + + + PORTB + 0x40012400 + + + PORTC + 0x40012800 + + + PORTD + 0x40012C00 + + + PORTE + 0x40013000 + + + PORTF + 0x40013400 + + + PORTG + 0x40013800 + + + + + TIM0 + 1.0 + Timer/Counter Peripheral + Timer_Counter + 0x40018000 + + 0 + 0x00000400 + registers + + + TIM0 + 48 + + + TIM1 + 49 + + + TIM2 + 50 + + + TIM3 + 51 + + + TIM4 + 52 + + + TIM5 + 53 + + + TIM6 + 54 + + + TIM7 + 55 + + + TIM8 + 56 + + + TIM9 + 57 + + + TIM10 + 58 + + + TIM11 + 59 + + + TIM12 + 60 + + + TIM13 + 61 + + + TIM14 + 62 + + + TIM15 + 63 + + + TIM16 + 64 + + + TIM17 + 65 + + + TIM18 + 66 + + + TIM19 + 67 + + + TIM20 + 68 + + + TIM21 + 69 + + + TIM22 + 70 + + + TIM23 + 71 + + TIM + + + CTRL + Control Register + 0x000 + read-write + + + ENABLE + Counter Enable + [0:0] + + + ACTIVE + Counter Active + [1:1] + read-only + + + AUTO_DISABLE + Auto Disables the counter (set ENABLE to 0) when the count reaches 0 + [2:2] + + + AUTO_DEACTIVATE + Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0 + [3:3] + + + IRQ_ENB + Interrupt Enable + [4:4] + + + STATUS_SEL + Counter Status Selection + [7:5] + + + DONE + Single cycle pulse when the counter reaches 0 + 0 + + + ACTIVE + Returns the counter ACTIVE bit + 1 + + + TOGGLE + Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output. + 2 + + + PWMA + Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE + 3 + + + PWMB + Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE + 4 + + + ENABLED + Returns the counter ENABLED bit + 5 + + + PWMA_ACTIVE + Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0 + 6 + + + + + STATUS_INV + Invert the Output Status + [8:8] + + + REQ_STOP + Stop Request + [9:9] + + + + + RST_VALUE + The value that counter start from after reaching 0. + 0x004 + + + CNT_VALUE + The current value of the counter + 0x008 + + + ENABLE + Alternate access to the Counter ENABLE bit in the CTRL Register + 0x00c + + + ENABLE + Counter Enable + [0:0] + + + + + CSD_CTRL + The Cascade Control Register. Controls the counter external enable signals + 0x010 + + + CSDEN0 + Cascade 0 Enable + [0:0] + + + CSDINV0 + Cascade 0 Invert + [1:1] + + + CSDEN1 + Cascade 1 Enable + [2:2] + + + CSDINV1 + Cascade 1 Invert + [3:3] + + + DCASOP + Dual Cascade Operation (0:AND, 1:OR) + [4:4] + + + CSDTRG0 + Cascade 0 Enabled as Trigger + [6:6] + + + CSDTRG1 + Cascade 1 Enabled as Trigger + [7:7] + + + CSDEN2 + Cascade 2 Enable + [8:8] + + + CSDINV2 + Cascade 2 Invert + [9:9] + + + CSDTRG2 + Cascade 2 Trigger mode + [10:10] + + + + + CASCADE0 + Cascade Enable Selection + 0x014 + + + CASSEL + Cascade Selection + [7:0] + + + + + CASCADE1 + Cascade Enable Selection + 0x018 + + + CASCADE2 + Cascade Enable Selection + 0x01c + + + PWM_VALUE + The Pulse Width Modulation Value + 0x020 + + + PWMA_VALUE + The Pulse Width Modulation ValueA + PWM_VALUE + 0x020 + + + PWMB_VALUE + The Pulse Width Modulation ValueB + 0x024 + + + PERID + Peripheral ID Register + 0x3fc + read-only + 0x021107e9 + + + + + TIM1 + 0x40018400 + + + TIM2 + 0x40018800 + + + TIM3 + 0x40018C00 + + + TIM4 + 0x40019000 + + + TIM5 + 0x40019400 + + + TIM6 + 0x40019800 + + + TIM7 + 0x40019C00 + + + TIM8 + 0x4001A000 + + + TIM9 + 0x4001A400 + + + TIM10 + 0x4001A800 + + + TIM11 + 0x4001AC00 + + + TIM12 + 0x4001B000 + + + TIM13 + 0x4001B400 + + + TIM14 + 0x4001B800 + + + TIM15 + 0x4001BC00 + + + TIM16 + 0x40028000 + + + TIM17 + 0x40028400 + + + TIM18 + 0x40028800 + + + TIM19 + 0x40028C00 + + + TIM20 + 0x40029000 + + + TIM21 + 0x40029400 + + + TIM22 + 0x40029800 + + + TIM23 + 0x40029C00 + + + + + UART0 + 1.0 + UART Peripheral + UART + 0x40024000 + + 0 + 0x00001000 + registers + + + UART0_TX + 24 + + + UART0_RX + 25 + + + UART1_TX + 26 + + + UART1_RX + 27 + + + UART2_TX + 28 + + + UART2_RX + 29 + + UART + + + DATA + Data In/Out Register + 0x000 + 0x00000000 + + + ENABLE + Enable Register + 0x004 + 0x00000000 + + + RXENABLE + Rx Enable + [0:0] + + + TXENABLE + Tx Enable + [1:1] + + + + + CTRL + Control Register + 0x008 + 0x00000000 + + + PAREN + Parity Enable + [0:0] + + + PAREVEN + Parity Even/Odd(1/0) + [1:1] + + + PARSTK + Parity Sticky + [2:2] + + + STOPBITS + Stop Bits 1/2(0/1) + [3:3] + + + WORDSIZE + Word Size in Bits 5/6/7/8(00/01/10/11) + [5:4] + + + LOOPBACK + Loopback Enable + [6:6] + + + LOOPBACKBLK + Loopback Block + [7:7] + + + AUTOCTS + Enable Auto CTS mode + [8:8] + + + DEFRTS + Default RTSn value + [9:9] + + + AUTORTS + Enable Auto RTS mode + [10:10] + + + BAUD8 + Enable BAUD8 mode + [11:11] + + + + + CLKSCALE + Clock Scale Register + 0x00c + 0x00000000 + + + FRAC + Fractional Divide (64ths) + [5:0] + + + INT + Integer Divide + [23:6] + + + RESET + Reset Baud Counter + [31:31] + write-only + + + + + RXSTATUS + Status Register + 0x010 + read-only + 0x00000000 + + + RDAVL + Read Data Available + [0:0] + + + RDNFULL + Read Fifo NOT Full + [1:1] + + + RXBUSY + RX Busy Receiving + [2:2] + + + RXTO + RX Receive Timeout + [3:3] + + + RXOVR + Read Fifo Overflow + [4:4] + + + RXFRM + RX Framing Error + [5:5] + + + RXPAR + RX Parity Error + [6:6] + + + RXBRK + RX Break Error + [7:7] + + + RXBUSYBRK + RX Busy Receiving Break + [8:8] + + + RXADDR9 + Address Match for 9 bit mode + [9:9] + + + RXRTSN + RX RTSn Output Value + [15:15] + + + + + TXSTATUS + Status Register + 0x014 + read-only + 0x00000000 + + + WRRDY + Write Fifo NOT Full + [0:0] + + + WRBUSY + Write Fifo Full + [1:1] + + + TXBUSY + TX Busy Transmitting + [2:2] + + + WRLOST + Write Data Lost (Fifo Overflow) + [3:3] + + + TXCTSN + TX CTSn Input Value + [15:15] + + + + + FIFO_CLR + Clear FIFO Register + 0x018 + write-only + 0x00000000 + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TXBREAK + Break Transmit Register + 0x01c + write-only + 0x00000000 + + + ADDR9 + Address9 Register + 0x020 + read-write + 0x00000000 + + + ADDR9MASK + Address9 Mask Register + 0x024 + read-write + 0x00000000 + + + IRQ_ENB + IRQ Enable Register + 0x028 + read-write + 0x00000000 + + + IRQ_RX + RX Interrupt + [0:0] + + + IRQ_RX_STATUS + RX Status Interrupt + [1:1] + + + IRQ_RX_TO + RX Timeout Interrupt + [2:2] + + + IRQ_TX + TX Interrupt + [4:4] + + + IRQ_TX_STATUS + TX Status Interrupt + [5:5] + + + IRQ_TX_EMPTY + TX Empty Interrupt + [6:6] + + + IRQ_TX_CTS + TX CTS Change Interrupt + [7:7] + + + + + IRQ_RAW + IRQ Raw Status Register + 0x02c + read-only + 0x00000000 + + + IRQ_END + IRQ Enabled Status Register + 0x030 + read-only + 0x00000000 + + + IRQ_CLR + IRQ Clear Status Register + 0x034 + write-only + 0x00000000 + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x038 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x03c + + + RXFIFORTSTRG + Rx FIFO RTS Trigger Level + 0x040 + + + STATE + Internal STATE of UART Controller + 0x044 + 32 + read-only + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x021207e9 + + + + + UART1 + 0x40025000 + + + UART2 + 0x40017000 + + + + + SPI0 + 1.0 + SPI Peripheral + SPI + 0x40015000 + + 0 + 0x00000400 + registers + + + SPI0_TX + 16 + + + SPI0_RX + 17 + + + SPI1_TX + 18 + + + SPI1_RX + 19 + + + SPI2_TX + 20 + + + SPI2_RX + 21 + + + SPI3_TX + 22 + + + SPI3_RX + 23 + + SPI + + + CTRL0 + Control Register 0 + 0x000 + 0x00000000 + + + SIZE + Data Size(0x3=>4, 0xf=>16) + [3:0] + + + SPO + SPI Clock Polarity + [6:6] + + + SPH + SPI Clock Phase + [7:7] + + + SCRDV + Serial Clock Rate divide+1 value + [15:8] + + + + + CTRL1 + Control Register 1 + 0x004 + 0x00000000 + + + LBM + Loop Back + [0:0] + + + ENABLE + Enable + [1:1] + + + MS + Master/Slave (0:Master, 1:Slave) + [2:2] + + + SOD + Slave output Disable + [3:3] + + + SS + Slave Select + [6:4] + + + BLOCKMODE + Block Mode Enable + [7:7] + + + BMSTART + Block Mode Start Status Enable + [8:8] + + + BMSTALL + Block Mode Stall Enable + [9:9] + + + MDLYCAP + Master Delayed Capture Enable + [10:10] + + + MTXPAUSE + Master Tx Pause Enable + [11:11] + + + + + DATA + Data Input/Output + 0x008 + + + STATUS + Status Register + 0x00C + read-only + 0x00000000 + + + TFE + Transmit FIFO empty + [0:0] + + + TNF + Transmit FIFO not full + [1:1] + + + RNE + Receive FIFO not empty + [2:2] + + + RFF + Receive FIFO Full + [3:3] + + + BUSY + Busy + [4:4] + + + RXDATAFIRST + Pending Data is first Byte in BLOCKMODE + [5:5] + + + RXTRIGGER + RX FIFO Above Trigger Level + [6:6] + + + TXTRIGGER + TX FIFO Below Trigger Level + [7:7] + + + + + CLKPRESCALE + Clock Pre Scale divide value + 0x010 + + + IRQ_ENB + Interrupt Enable Register + 0x014 + read-write + 0x00000000 + + + RORIM + RX Overrun + [0:0] + + + RTIM + RX Timeout + [1:1] + + + RXIM + RX Fifo is at least half full + [2:2] + + + TXIM + TX Fifo is at least half empty + [3:3] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x018 + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x01C + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x020 + write-only + + oneToClear + + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x024 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x028 + + + FIFO_CLR + Clear FIFO Register + 0x02c + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + STATE + Internal STATE of SPI Controller + 0x030 + read-only + + + PERID + Peripheral ID Register + 0x3fc + read-only + 0x021307e9 + + + + + SPI1 + 0x40015400 + + + SPI2 + 0x40015800 + + + SPI3 + 0x40015C00 + + + + + I2C0 + 1.0 + I2C Peripheral + I2C + 0x40016000 + + 0 + 0x00000400 + registers + + + I2C0_MS + 30 + + + I2C0_SL + 31 + + + I2C1_MS + 32 + + + I2C1_SL + 33 + + + I2C2_MS + 34 + + + I2C2_SL + 35 + + + I2C0_MS_RX + 182 + + + I2C0_MS_TX + 183 + + + I2C0_SL_RX + 184 + + + I2C0_SL_TX + 185 + + + I2C1_MS_RX + 186 + + + I2C1_MS_TX + 187 + + + I2C1_SL_RX + 188 + + + I2C1_SL_TX + 189 + + + I2C2_MS_RX + 190 + + + I2C2_MS_TX + 191 + + + I2C2_SL_RX + 192 + + + I2C2_SL_TX + 193 + + I2C + + + + CTRL + Control Register + 0x000 + 0x00000000 + + + CLKENABLED + I2C CLK Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + ALGFILTER + Enable Input Analog Glitch Filter + [5:5] + + + DLGFILTER + Enable Input Digital Glitch Filter + [6:6] + + + LOOPBACK + Enable LoopBack Mode + [8:8] + + + TMCONFIGENB + Enable Timing Config Register + [9:9] + + + + + CLKSCALE + Clock Scale divide value + 0x004 + + + VALUE + Enable FastMode + [30:0] + + + FASTMODE + Enable FastMode + [31:31] + + + + + WORDS + Word Count value + 0x008 + + + ADDRESS + I2C Address value + 0x00c + + + DATA + Data Input/Output + 0x010 + + + CMD + Command Register + 0x014 + + + STATUS + I2C Controller Status Register + 0x018 + + + I2CIDLE + I2C bus is idle + [0:0] + + + IDLE + I2C controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + STATE + Internal STATE of I2C Master Controller + 0x01c + read-only + + + TXCOUNT + TX Count Register + 0x020 + read-only + + + RXCOUNT + RX Count Register + 0x024 + read-only + + + IRQ_ENB + Interrupt Enable Register + 0x028 + read-write + 0x00000000 + + + I2CIDLE + I2C Bus is Idle + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + CLKLOTO + I2C Clock Low Timeout + [7:7] + + + TXOVERFLOW + TX FIFO Overflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x02c + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x030 + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x034 + write-only + + oneToClear + + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x038 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x03c + + + FIFO_CLR + Clear FIFO Register + 0x040 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TMCONFIG + Timing Config Register + 0x044 + + + CLKTOLIMIT + Clock Low Timeout Limit Register + 0x048 + + + + S0_CTRL + Slave Control Register + 0x100 + 0x00000000 + + + CLKENABLED + I2C Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + + + S0_MAXWORDS + Slave MaxWords Register + 0x104 + 0x00000000 + + + MAXWORD + Max Word Count + [10:0] + + + ENABLE + Enables the max word count + [31:31] + + + + + S0_ADDRESS + Slave I2C Address Value + 0x108 + 0x00000000 + + + A10MODE + Enable 10b address mode + [15:15] + + + ADDRESS + Address value + [10:1] + + + RW + Read/Write value + [0:0] + + + + + S0_ADDRESSMASK + Slave I2C Address Mask value + 0x10c + 0x00000000 + + + MASK + Address mask value + [10:1] + + + RWMASK + Read/Write mask + [0:0] + + + + + S0_DATA + Slave Data Input/Output + 0x110 + 0x00000000 + + + VALUE + I2C data value + [7:0] + + + + + S0_LASTADDRESS + Slave I2C Last Address value + 0x114 + read-only + 0x00000000 + + + ADDRESS + Address value + [10:1] + + + DIRECTION + Transaction direction 0=master send, 1=master receive + [0:0] + + + + + S0_STATUS + Slave I2C Controller Status Register + 0x118 + read-only + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_BUSY + I2C Raw Busy value + [29:29] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + S0_STATE + Internal STATE of I2C Slave Controller + 0x11c + read-only + + + S0_TXCOUNT + Slave TX Count Register + 0x120 + read-only + 0x00000000 + + + VALUE + Count value + [10:0] + + + + + S0_RXCOUNT + Slave RX Count Register + 0x124 + read-only + 0x00000000 + + + VALUE + Count value + [10:0] + + + + + S0_IRQ_ENB + Slave Interrupt Enable Register + 0x128 + read-write + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + I2C_START + I2C Start Condition + [8:8] + + + I2C_STOP + I2C Stop Condition + [9:9] + + + TXUNDERFLOW + TX FIFO Underflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + S0_IRQ_RAW + Slave Raw Interrupt Status Register + 0x12c + read-only + + + S0_IRQ_END + Slave Enabled Interrupt Status Register + 0x130 + read-only + + + S0_IRQ_CLR + Slave Clear Interrupt Status Register + 0x134 + write-only + + oneToClear + + + + S0_RXFIFOIRQTRG + Slave Rx FIFO IRQ Trigger Level + 0x138 + 0x00000000 + + + LEVEL + Half full level for the Rx FIFO + [4:0] + + + + + S0_TXFIFOIRQTRG + Slave Tx FIFO IRQ Trigger Level + 0x13c + 0x00000008 + + + LEVEL + Half full level for the Rx FIFO + [4:0] + + + + + S0_FIFO_CLR + Slave Clear FIFO Register + 0x140 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + S0_ADDRESSB + Slave I2C Address B Value + 0x144 + 0x00000000 + + + RW + Read write value + [0:0] + + + ADDRESS + Address value + [10:1] + + + ADDRESSBEN + Enable Address B + [15:15] + + + + + S0_ADDRESSMASKB + Slave I2C Address B Mask value + 0x148 + 0x000007FE + + + RWMASK + Read write mask + [0:0] + + + MASK + Address mask value + [10:1] + + + + + PERID + Peripheral ID Register + 0x3fc + read-only + 0x021407e9 + + + + + I2C1 + 0x40016400 + + + I2C2 + 0x40016800 + + + + + CAN0 + 1.0 + CAN Peripheral + CAN + 0x40014000 + + 0 + 0x00000400 + registers + + + CAN0 + 72 + + + CAN1 + 74 + + CAN + + + CNSTAT_CMB0 + Buffer Status / Control Register + 0x000 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB0 + CAN Frame Timestamp + 0x004 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB0 + CAN Frame Data Word 3 + 0x008 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB0 + CAN Frame Data Word 2 + 0x00C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB0 + CAN Frame Data Word 1 + 0x010 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB0 + CAN Frame Data Word 0 + 0x014 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB0 + CAN Frame Identifier Word 0 + 0x018 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB0 + CAN Frame Identifier Word 1 + 0x01C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB1 + Buffer Status / Control Register + 0x020 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB1 + CAN Frame Timestamp + 0x024 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB1 + CAN Frame Data Word 3 + 0x028 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB1 + CAN Frame Data Word 2 + 0x02C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB1 + CAN Frame Data Word 2 + 0x030 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB1 + CAN Frame Data Word 0 + 0x034 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB1 + CAN Frame Identifier Word 0 + 0x038 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB1 + CAN Frame Identifier Word 1 + 0x03C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB2 + Buffer Status / Control Register + 0x040 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB2 + CAN Frame Timestamp + 0x044 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB2 + CAN Frame Data Word 3 + 0x048 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB2 + CAN Frame Data Word 2 + 0x04C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB2 + CAN Frame Data Word 2 + 0x050 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB2 + CAN Frame Data Word 0 + 0x054 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB2 + CAN Frame Identifier Word 0 + 0x058 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB2 + CAN Frame Identifier Word 1 + 0x05C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB3 + Buffer Status / Control Register + 0x060 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB3 + CAN Frame Timestamp + 0x064 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB3 + CAN Frame Data Word 3 + 0x068 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB3 + CAN Frame Data Word 2 + 0x06C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB3 + CAN Frame Data Word 2 + 0x070 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB3 + CAN Frame Data Word 0 + 0x074 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB3 + CAN Frame Identifier Word 0 + 0x078 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB3 + CAN Frame Identifier Word 1 + 0x07C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB4 + Buffer Status / Control Register + 0x080 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB4 + CAN Frame Timestamp + 0x084 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB4 + CAN Frame Data Word 3 + 0x088 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB4 + CAN Frame Data Word 2 + 0x08C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB4 + CAN Frame Data Word 2 + 0x090 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB4 + CAN Frame Data Word 0 + 0x094 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB4 + CAN Frame Identifier Word 0 + 0x098 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB4 + CAN Frame Identifier Word 1 + 0x09C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB5 + Buffer Status / Control Register + 0x0A0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB5 + CAN Frame Timestamp + 0x0A4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB5 + CAN Frame Data Word 3 + 0x0A8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB5 + CAN Frame Data Word 2 + 0x0AC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB5 + CAN Frame Data Word 2 + 0x0B0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB5 + CAN Frame Data Word 0 + 0x0B4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB5 + CAN Frame Identifier Word 0 + 0x0B8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB5 + CAN Frame Identifier Word 1 + 0x0BC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB6 + Buffer Status / Control Register + 0x0C0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB6 + CAN Frame Timestamp + 0x0C4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB6 + CAN Frame Data Word 3 + 0x0C8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB6 + CAN Frame Data Word 2 + 0x0CC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB6 + CAN Frame Data Word 2 + 0x0D0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB6 + CAN Frame Data Word 0 + 0x0D4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB6 + CAN Frame Identifier Word 0 + 0x0D8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB6 + CAN Frame Identifier Word 1 + 0x0DC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB7 + Buffer Status / Control Register + 0x0E0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB7 + CAN Frame Timestamp + 0x0E4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB7 + CAN Frame Data Word 3 + 0x0E8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB7 + CAN Frame Data Word 2 + 0x0EC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB7 + CAN Frame Data Word 2 + 0x0F0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB7 + CAN Frame Data Word 0 + 0x0F4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB7 + CAN Frame Identifier Word 0 + 0x0F8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB7 + CAN Frame Identifier Word 1 + 0x0FC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB8 + Buffer Status / Control Register + 0x100 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB8 + CAN Frame Timestamp + 0x104 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB8 + CAN Frame Data Word 3 + 0x108 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB8 + CAN Frame Data Word 2 + 0x10C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB8 + CAN Frame Data Word 2 + 0x110 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB8 + CAN Frame Data Word 0 + 0x114 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB8 + CAN Frame Identifier Word 0 + 0x118 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB8 + CAN Frame Identifier Word 1 + 0x11C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB9 + Buffer Status / Control Register + 0x120 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB9 + CAN Frame Timestamp + 0x124 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB9 + CAN Frame Data Word 3 + 0x128 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB9 + CAN Frame Data Word 2 + 0x12C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB9 + CAN Frame Data Word 2 + 0x130 + 0x00000000 + + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB9 + CAN Frame Data Word 0 + 0x134 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB9 + CAN Frame Identifier Word 0 + 0x138 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB9 + CAN Frame Identifier Word 1 + 0x13C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB10 + Buffer Status / Control Register + 0x140 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB10 + CAN Frame Timestamp + 0x144 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB10 + CAN Frame Data Word 3 + 0x148 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB10 + CAN Frame Data Word 2 + 0x14C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB10 + CAN Frame Data Word 2 + 0x150 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB10 + CAN Frame Data Word 0 + 0x154 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB10 + CAN Frame Identifier Word 0 + 0x158 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB10 + CAN Frame Identifier Word 1 + 0x15C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB11 + Buffer Status / Control Register + 0x160 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB11 + CAN Frame Timestamp + 0x164 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB11 + CAN Frame Data Word 3 + 0x168 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB11 + CAN Frame Data Word 2 + 0x16C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB11 + CAN Frame Data Word 2 + 0x170 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB11 + CAN Frame Data Word 0 + 0x174 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB11 + CAN Frame Identifier Word 0 + 0x178 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB11 + CAN Frame Identifier Word 1 + 0x17C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB12 + Buffer Status / Control Register + 0x180 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB12 + CAN Frame Timestamp + 0x184 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB12 + CAN Frame Data Word 3 + 0x188 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB12 + CAN Frame Data Word 2 + 0x18C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB12 + CAN Frame Data Word 2 + 0x190 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB12 + CAN Frame Data Word 0 + 0x194 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB12 + CAN Frame Identifier Word 0 + 0x198 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB12 + CAN Frame Identifier Word 1 + 0x19C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB13 + Buffer Status / Control Register + 0x1A0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB13 + CAN Frame Timestamp + 0x1A4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB13 + CAN Frame Data Word 3 + 0x1A8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB13 + CAN Frame Data Word 2 + 0x1AC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB13 + CAN Frame Data Word 2 + 0x1B0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB13 + CAN Frame Data Word 0 + 0x1B4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB13 + CAN Frame Identifier Word 0 + 0x1B8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB13 + CAN Frame Identifier Word 1 + 0x1BC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB14 + Buffer Status / Control Register + 0x1C0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB14 + CAN Frame Timestamp + 0x1C4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB14 + CAN Frame Data Word 3 + 0x1C8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB14 + CAN Frame Data Word 2 + 0x1CC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB14 + CAN Frame Data Word 2 + 0x1D0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB14 + CAN Frame Data Word 0 + 0x1D4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB14 + CAN Frame Identifier Word 0 + 0x1D8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB14 + CAN Frame Identifier Word 1 + 0x1DC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_HCMB + Buffer Status / Control Register + 0x1E0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_HCMB + CAN Frame Timestamp + 0x1E4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_HCMB + CAN Frame Data Word 3 + 0x1E8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_HCMB + CAN Frame Data Word 2 + 0x1EC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_HCMB + CAN Frame Data Word 2 + 0x1F0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_HCMB + CAN Frame Data Word 0 + 0x1F4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_HCMB + CAN Frame Identifier Word 0 + 0x1F8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_HCMB + CAN Frame Identifier Word 1 + 0x1FC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CGCR + CAN Global Configuration Register + 0x200 + 0x00000000 + + + EIT + Error Interrupt Type + [11:11] + + + DIAGEN + Diagnostic Enable + [10:10] + + + INTERNAL + Internal + [9:9] + + + LOOPBACK + Loopback + [8:8] + + + IGNACK + Ignore Acknowledge + [7:7] + + + LO + Listen Only + [6:6] + + + DDIR + Data Direction + [5:5] + + + TSTPEN + Time Sync Enable + [4:4] + + + BUFFLOCK + Buffer Lock + [3:3] + + + CTX + RW,Control Transmit + [2:2] + + + CRX + RW,Control Receive + [1:1] + + + CANEN + CAN Enable + [0:0] + + + + + CTIM + CAN Timing Register + 0x204 + 0x00000000 + + + PSC + Prescaler Configuration + [15:9] + + + SJW + Synchronization Jump Width + [8:7] + + + TSEG1 + Time Segment 1 + [6:3] + + + TSEG2 + Time Segment 2 + [2:0] + + + + + GMSKX + CAN Global Mask Extension + 0x208 + 0x00000000 + + + GM + GM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard + [15:1] + + + XRTR + Extended Remote transmission Request Bit + [0:0] + + + + + GMSKB + CAN Global Mask Base + 0x20C + 0x00000000 + + + GM1 + GM[28:18] - ID[10:0] in standard, ID[28:18] in extended + [15:5] + + + RTR + Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended + [4:4] + + + IDE + Identifier Extension Bit + [3:3] + + + GM0 + GM[17:15] - Unused in standard, ID[17:15] in extended + [2:0] + + + + + BMSKX + CAN Basic Mask Extension + 0x210 + 0x00000000 + + + BM + BM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard + [15:1] + + + XRTR + Extended Remote transmission Request Bit + [0:0] + + + + + BMSKB + CAN Basic Mask Base + 0x214 + 0x00000000 + + + BM1 + BM[28:18] - ID[10:0] in standard, ID[28:18] in extended + [15:5] + + + RTR + Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended + [4:4] + + + IDE + Identifier Extension Bit + [3:3] + + + BM0 + BM[17:15] - Unused in standard, ID[17:15] in extended + [2:0] + + + + + CIEN + CAN Interrupt Enable Register + 0x218 + 0x00000000 + + + EIEN + Error Interrupt Enable + [15:15] + + + IEN + Buffer Interrupt Enable[14:0] + [14:0] + + + + + CIPND + CAN Interrupt Pending Register + 0x21C + 0x00000000 + + + EIPND + Error Interrupt Pending + [15:15] + + + IPND + Buffer Interrupt Pending[14:0] + [14:0] + + + + + CICLR + CAN Interrupt Clear Register + 0x220 + 0x00000000 + + + EICLR + Error Interrupt Clear + [15:15] + + + ICLR + Buffer Interrupt Clear[14:0] + [14:0] + + + + + CICEN + CAN Interrupt Code Enable Register + 0x224 + 0x00000000 + + + EICEN + Error Interrupt Code Enable + [15:15] + + + ICEN + Buffer Interrupt Code Enable[14:0] + [14:0] + + + + + CSTPND + CAN Status Pending Register + 0x228 + 0x00000000 + + + NS + CAN Node Status + [7:5] + + + IRQ + Interrupt Request portion of Interrupt Code + [4:4] + + + IST + Interrupt Source portion of Interrupt Code + [3:0] + + + + + CANEC + CAN Error Counter Register + 0x22C + 0x00000000 + + + REC + Receive Error Counter + [15:8] + + + TEC + Transmit Error Counter + [7:0] + + + + + CEDIAG + CAN Error Diagnostic Register + 0x230 + 0x00000000 + + + DRIVE + Drive + [14:14] + + + MON + Monitor + [13:13] + + + CRC + CRC + [12:12] + + + STUFF + Stuff Error + [11:11] + + + TXE + Transmit Error + [10:10] + + + EBID + Error Bit Identifier + [9:4] + + + EFID + Error Field Identifier + [3:0] + + + + + CTMR + CAN Timer Register + 0x234 + 0x00000000 + + + CTMR + Time Stamp Counter + [15:0] + read-only + + + + + + + CAN1 + 0x40014400 + + + + + ADC + 1.0 + Analog to Digital Converter Peripheral + ADC + 0x40022000 + + 0 + 0x00001000 + registers + + + ADC + 44 + + ADC + + + CTRL + Control Register + 0x000 + 0x00000000 + + + CONV_CNT + Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions) + [23:20] + + + MANUAL_TRIG + Starts analog acquisition + [19:19] + + + EXT_TRIG_EN + Allows the external trigger to start analog acquisition + [18:18] + + + SWEEP_EN + ADC data acquisition for all enabled channel + [17:17] + + + CHAN_TAG_EN + Enables the channel tag to be saved with the ADC data + [16:16] + + + CHAN_EN + Enables the channel for data collection + [15:0] + + + + + FIFO_DATA + FIFO data + 0x004 + read-only + 0x00000000 + + + CHAN_TAG + If enabled, this will include the number of the channel corresponding to the measurement + [15:12] + read-only + + + ADC_DATA + ADC acquisition data from the FIFO + [11:0] + + + + + STATUS + Status + 0x008 + read-only + 0x00000000 + + + ADC_BUSY + Indicates an ADC data acquisition is in process + [7:7] + + + FIFO_ENTRY_CNT + Indicates the number of entries in the FIFO + [5:0] + + + + + IRQ_ENB + Interrupt Enable + 0x00C + 0x00000000 + + + FIFO_DEPTH_TRIG + Enables the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Enables the interrupt for a trigger error + [5:5] + + + ADC_DONE + Enables the interrupt for an ADC data acquisition completion + [4:4] + + + FIFO_UFLOW + Enables the interrupt for a FIFO underflow + [3:3] + + + FIFO_OFLOW + Enables the interrupt for a FIFO overflow + [2:2] + + + FIFO_FULL + Enables the interrupt for FIFO full + [1:1] + + + FIFO_EMPTY + Enables the interrupt for FIFO empty + [0:0] + + + + + IRQ_RAW + Raw Interrupt Status + 0x010 + read-only + 0x00000001 + + + FIFO_DEPTH_TRIG + Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion + [5:5] + + + ADC_DONE + Indicates that a ADC conversion is done + [4:4] + + + FIFO_UFLOW + Indicates data was unavailable when a new trigger for ADC update is received + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred (FIFO was full when new data was written) + [2:2] + + + FIFO_FULL + Indicates the FIFO is full + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty + [0:0] + + + + + IRQ_END + Enabled Interrupt Status + 0x014 + read-only + 0x00000000 + + + FIFO_DEPTH_TRIG + Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled + [5:5] + + + ADC_DONE + Indicates that a ADC conversion is done and the interrupt is enabled + [4:4] + + + FIFO_UFLOW + Indicates a FIFO underflow occurred and the interrupt is enabled + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred and the interrupt is enabled + [2:2] + + + FIFO_FULL + Indicates the FIFO is full and the interrupt is enabled + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty and the interrupt is enabled + [0:0] + + + + + IRQ_CLR + Clear Interrupt + 0x018 + write-only + 0x00000000 + + + TRIG_ERROR + Clears the trigger error interrupt status. Always reads 0 + [3:3] + + + ADC_DONE + Clears the ADC done interrupt status. Always reads 0 + [2:2] + + + FIFO_UFLOW + Clears the FIFO underflow interrupt status. Always reads 0 + [1:1] + + + FIFO_OFLOW + Clears the FIFO overflow interrupt status. Always reads 0 + [0:0] + + + + + RXFIFOIRQTRG + Receive FIFO Interrupt Trigger Value + 0x01C + 0x00000010 + + + LEVEL + Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt + [4:0] + + + + + FIFO_CLR + FIFO Clear + 0x020 + 0x00000000 + + + FIFO_CLR + Clears the ADC FIFO. Always reads 0 + [0:0] + write-only + + + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001907e9 + + + + + + + DAC0 + 1.0 + Digital to Analog Converter Peripheral + DAC + 0x40023000 + + 0 + 0x00000800 + registers + + + DAC0 + 40 + + + DAC1 + 41 + + DAC + + + CTRL0 + Control Register 0 + 0x000 + 0x00000000 + + + MAN_TRIG_EN + Enables manual trigger + [11:11] + + + EXT_TRIG_EN + Enables external trigger + [10:10] + + + + + CTRL1 + Control Register 1 + 0x004 + 0x00000000 + + + DAC_EN + Enables the DAC analog block + [8:8] + + + DAC_SETTLING + Sets the the amount of time in microseconds the control FSM waits for the DAC settling time + [7:5] + + + + + FIFO_DATA + FIFO data + 0x008 + read-write + 0x00000000 + + + DATA + Data for FIFO write + [11:0] + write-only + + + + + STATUS + Status + 0x00C + read-only + 0x00000000 + + + DAC_BUSY + Indicates a DAC data acquisition is in process + [7:7] + + + FIFO_ENTRY_CNT + Indicates the number of entries in the FIFO + [5:0] + + + + + IRQ_ENB + Interrupt Enable + 0x010 + 0x00000000 + + + FIFO_DEPTH_TRIG + Enables the interrupt for the FIFO entry count is less than or equal to the trigger level + [6:6] + + + TRIG_ERROR + Enables the interrupt for a trigger error + [5:5] + + + DAC_DONE + Enables the interrupt for a DAC data acquisition completion + [4:4] + + + FIFO_UFLOW + Enables the interrupt for a FIFO underflow + [3:3] + + + FIFO_OFLOW + Enables the interrupt for a FIFO overflow + [2:2] + + + FIFO_FULL + Enables the interrupt for FIFO full + [1:1] + + + FIFO_EMPTY + Enables the interrupt for FIFO empty + [0:0] + + + + + IRQ_RAW + Raw Interrupt Status + 0x014 + read-only + 0x00000041 + + + FIFO_DEPTH_TRIG + Indicates the FIFO entry count is less than or equal to the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion + [5:5] + + + DAC_DONE + Indicates that a DAC conversion is done + [4:4] + + + FIFO_UFLOW + Indicates data was unavailable when a new trigger for DAC update is received + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred (FIFO was full when new data was written) + [2:2] + + + FIFO_FULL + Indicates the FIFO is full + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty + [0:0] + + + + + IRQ_END + Enabled Interrupt Status + 0x018 + read-only + 0x00000000 + + + FIFO_DEPTH_TRIG + Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled + [5:5] + + + DAC_DONE + Indicates that a DAC conversion is done and the interrupt is enabled + [4:4] + + + FIFO_UFLOW + Indicates a FIFO underflow occurred and the interrupt is enabled + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred and the interrupt is enabled + [2:2] + + + FIFO_FULL + Indicates the FIFO is full and the interrupt is enabled + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty and the interrupt is enabled + [0:0] + + + + + IRQ_CLR + Clear Interrupt + 0x01C + write-only + 0x00000000 + + + TRIG_ERROR + Clears the trigger error interrupt status. Always reads 0 + [3:3] + + + DAC_DONE + Clears the DAC done interrupt status. Always reads 0 + [2:2] + + + FIFO_UFLOW + Clears the FIFO underflow interrupt status. Always reads 0 + [1:1] + + + FIFO_OFLOW + Clears the FIFO overflow interrupt status. Always reads 0 + [0:0] + + + + + TXFIFOIRQTRG + Receive FIFO Interrupt Trigger Value + 0x020 + 0x00000010 + + + LEVEL + Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt + [4:0] + + + + + FIFO_CLR + FIFO Clear + 0x024 + 0x00000000 + + + FIFO_CLR + Clears the DAC FIFO. Always reads 0 + [0:0] + write-only + + + + + PERID + Peripheral ID Register + 0x7fc + read-only + 0x002007e9 + + + + + DAC1 + 0x40023800 + + + + + SPW + 1.0 + SpaceWire Peripheral + SPW + 0x40003000 + + 0 + 0x00000400 + registers + + + SpW + 38 + + SPW + + + CTRL + Control Register + 0x000 + 0xA2010004 + + + RA + Reads as 1 if the RMAP command handler is available + [31:31] + read-only + + + RX + Reads as 1 if unaligned writes are available for the receiver + [30:30] + read-only + + + RC + Reads as 1 if RMAP CRC is enabled in the core + [29:29] + read-only + + + NCH + Number of DMA Channels minus one + [28:27] + read-only + + + PO + The number of available SpaceWire ports minus one + [26:26] + read-only + + + CC + CCSDS/CCITT CRC-16 + [25:25] + read-only + + + ID + Interrupt distribution available + [24:24] + read-only + + + LE + Loop-back Enable + [22:22] + read-write + + + PS + Selects the active port when the no port force bit is zero + [21:21] + read-write + + + NP + Disable port force + [20:20] + read-write + + + PNPA + SpW Plug-and-Play Available + [19:18] + read-only + + + RD + If set only one RMAP buffer is used + [17:17] + read-write + + + RE + Enable RMAP command handler + [16:16] + read-write + + + PE + SpW Plug-and-Play Enable + [15:15] + read-write + + + TL + Transmitter Enable Lock Control + [13:13] + read-write + + + TF + Time-code Flag Filter + [12:12] + read-write + + + TR + Enable time-code receptions + [11:11] + + + TT + Enable time-code transmissions + [10:10] + + + LI + Generate interrupt when link error occurs + [9:9] + + + TQ + Generate interrupt when a valid time-code is received + [8:8] + + RS + Make complete reset of the SpaceWire node. Self-clearing + [6:6] + + PM + Enable Promiscuous mode + [5:5] + + TI + The host can generate a tick by writing a one to this field + [4:4] + + + IE + If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs + [3:3] + + + AS + Automatically start the link when a NULL has been received + [2:2] + + + LS + Start the link + [1:1] + + + LD + Disable the SpaceWire CODEC + [0:0] + + + + + STS + Status/Interrupt Source Register + 0x004 + 0x06400000 + + + NRXD + Number of Receive Descriptors + [27:26] + + + NTXD + Number of Transmit Descriptors + [25:24] + + + LS + Link State + [23:21] + + + AP + Active port + [9:9] + + + EE + Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet + [8:8] + + + IA + Packet is received with an invalid destination address field + [7:7] + + + WE + A synchronization problem has occurred when receiving NChars + [6:6] + + + PE + Parity error has occurred + [4:4] + + + DE + Disconnection error has occurred + [3:3] + + + ER + Escape error has occurred + [2:2] + + + CE + Credit has occurred + [1:1] + + + TO + A new time count value was received + [0:0] + + + + + DEFADDR + Node Address Register + 0x008 + read-write + 0x000000FE + + + DEFMASK + 8-bit default mask used for node identification on the SpaceWire network + [15:8] + + + DEFADDR + 8-bit node address used for node identification on the SpaceWire network + [7:0] + + + + + CLKDIV + Clock Divisor Register + 0x00C + read-write + 0x00000909 + + + CLKDIVSTART + 8-bit Clock divisor value used for the clock-divider during startup + [15:8] + + + CLKDIVRUN + 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state + [7:0] + + + + + DKEY + Destination Key + 0x010 + 0x00000000 + + + DESTKEY + RMAP destination key + [7:0] + + + + + TC + Time Code Register + 0x014 + read-write + 0x00000000 + + + TIRQ_END + The current value of the time control flags + [7:6] + + + TIMECNT + The current value of the system time counter + [5:0] + + + + + TDR + Timer and Disconnect Register + 0x018 + read-only + 0x00000000 + + + DISCONNECT + Used to generate the 850 ns disconnect time period + [21:12] + + + TIMER64 + Used to generate the 6.4 and 12.8 us time periods + [11:0] + + + + + DMACTRL0 + DMA Control Register + 0x020 + read-write + 0x00000000 + + + INTNUM + Interrupt number used for this channel + [31:26] + + + EP + EEP Termination + [23:23] + + + TR + Truncated + [22:22] + + + IE + Interrupt code transmit enable on EEP + [21:21] + + + IT + Interrupt code transmit enable on truncation + [20:20] + + + RP + Receive Packet IRQ + [19:19] + + + TP + Transmit Packet IRQ + [18:18] + + + TL + Transmit Enable Lock + [17:17] + + + LE + Disable transmitter when a link error occurs + [16:16] + + + SP + Strip PID + [15:15] + + + SA + Strip Address + [14:14] + + + EN + Enable Address + [13:13] + + + NS + If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated + [12:12] + + + RD + Indicates to the GRSPW that there are enabled descriptors in the descriptor table + [11:11] + + + RX + Reception to the DMA channel is currently active + [10:10] + read-only + + + AT + Abort the currently transmitting packet and disable transmissions + [9:9] + read-only + + + RA + An error response was detected on the AHB bus - DMA receive + [8:8] + + + TA + An error response was detected on the AHB bus - DMA transmit + [7:7] + + + PR + Set each time a packet has been received + [6:6] + + + PS + Set each time a packet has been sent + [5:5] + + + AI + An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus + [4:4] + + + RI + An interrupt will be generated each time a packet has been received + [3:3] + + + TI + An interrupt will be generated each time a packet is transmitted + [2:2] + + + RE + Packets are allowed to be received to this channel + [1:1] + + + TE + Write a one to this bit each time new descriptors are activated in the table + [0:0] + + + + + DMAMAXLEN0 + DMA RX Maximum Length Register + 0x024 + read-write + 0x00000000 + + + RXMAXLEN + Receiver packet maximum length in bytes + [24:2] + + + + + DMATXDESC0 + DMA Transmitter Descriptor Table Address Register + 0x028 + read-write + 0x00000000 + + + DESCBASEADDR + Sets the base address of the descriptor table + [31:10] + + + DESCSEL + Offset into the descriptor table + [9:4] + + + + + DMARXDESC0 + DMA Receiver Table Destination Register + 0x02C + read-write + 0x00000000 + + + DESCBASEADDR + Sets the base address of the descriptor table + [31:10] + + + DESCSEL + Offset into the descriptor table + [9:3] + + + + + DMAADDR0 + DMA Receiver Table Address Register + 0x030 + read-write + 0x00000000 + + + MASK + Mask + [15:8] + + + ADDR + Address + [7:0] + + + + + + + + + + + + IRQ_ROUTER + 1.0 + Interrupt Router Peripheral + 0x40002000 + + 0 + 0x00001000 + registers + + + U0 + 0 + + + U1 + 1 + + + U2 + 2 + + + U3 + 3 + + + U4 + 4 + + + U5 + 5 + + + U6 + 6 + + + U7 + 7 + + + U8 + 8 + + + U9 + 9 + + + U10 + 10 + + + U11 + 11 + + + U12 + 12 + + + U13 + 13 + + + U14 + 14 + + + U15 + 15 + + + U37 + 37 + + + U39 + 39 + + + U73 + 73 + + + U75 + 75 + + + FPU + 194 + + + TXEV + 195 + + IRQ + + + DMASEL0 + Interrupt select for DMA channel 0 + 0x0000 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL1 + Interrupt select for DMA channel 1 + 0x0004 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL2 + Interrupt select for DMA channel 2 + 0x0008 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL3 + Interrupt select for DMA channel 3 + 0x000C + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMATTSEL + Trigger select for the DMA channels + 0x0010 + read-write + 0x00000000 + + + DMATTSEL + DMA trigger type selection value + [3:0] + + + + + ADCSEL + Interrupt select for ADC + 0x0014 + read-write + 0x0000001F + + + ADCSEL + ADC trigger source selection value + [4:0] + + + + + DACSEL0 + Interrupt select for DAC0 + 0x0018 + read-write + 0x0000001F + + + DACSEL + DAC trigger source selection value + [4:0] + + + + + DACSEL1 + Interrupt select for DAC1 + 0x001C + read-write + 0x0000001F + + + DACSEL + DAC trigger source selection value + [4:0] + + + + + IRQ_OUT0 + DEBUG IRQ_OUT[31:0] + 0x0020 + read-only + 0x00000000 + + + IRQ_OUT0 + IRQ_OUT[31:0] + [31:0] + + + + + IRQ_OUT1 + DEBUG IRQ_OUT[63:32] + 0x0024 + read-only + 0x00000000 + + + IRQ_OUT1 + IRQ_OUT[63:32] + [31:0] + + + + + IRQ_OUT2 + DEBUG IRQ_OUT[95:64] + 0x0028 + read-only + 0x00000000 + + + IRQ_OUT2 + IRQ_OUT[95:64] + [31:0] + + + + + IRQ_OUT3 + DEBUG IRQ_OUT[127:96] + 0x002c + read-only + 0x00000000 + + + IRQ_OUT3 + IRQ_OUT[127:96] + [31:0] + + + + + IRQ_OUT4 + DEBUG IRQ_OUT[159:128] + 0x0030 + read-only + 0x00000000 + + + IRQ_OUT4 + IRQ_OUT[159:128] + [31:0] + + + + + IRQ_OUT5 + DEBUG IRQ_OUT[179:160] + 0x0034 + read-only + 0x00000000 + + + IRQ_OUT5 + IRQ_OUT[179:160] + [19:0] + + + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x028107e9 + + + + + + + WATCH_DOG + 1.0 + Watchdog Block Peripheral + 0x40021000 + + 0 + 0x00001000 + registers + + + WATCHDOG + 47 + + WDOG + + + WDOGLOAD + Counter Start Value + 0x0000 + read-write + 0xFFFFFFFF + + + CNT + Count to load + [31:0] + + + + + WDOGVALUE + Down Counter Value + 0x0004 + read-only + 0xFFFFFFFF + + + CNT + Actual Count + [31:0] + + + + + WDOGCONTROL + Enable for block reset and interrupt + 0x0008 + read-write + 0x00000000 + + + RESEN + Enable watchdog reset output + [1:1] + + + INTEN + Enable watchdog interrupt + [0:0] + + + + + WDOGINTCLR + A write of any value clears the WDT module interrupt, and reloads +the counter from the value in the WDOGLOAD Register + 0x000C + read-write + 0x00000000 + + + CLEAR + Write any value to clear interrupt + [31:0] + + + + + WDOGRIS + Raw interrupt status + 0x0010 + read-only + 0x00000000 + + + INTERRUPT + Interrupt Status + [0:0] + + + + + WDOGMIS + Interrupt status + 0x0014 + read-only + 0x00000000 + + + INTERRUPT + Masked Interrupt Status + [0:0] + + + + + WDOGLOCK + Lock + 0x00C0 + read-write + 0x00000000 + + + REG_WR_EN + Register write enable status + [31:0] + + + + + WDOGITCR + Integration test control + 0x0F00 + read-write + 0x00000000 + + + TEST_MODE_EN + Enable test mode of WDOGINT and WDOGRES + [0:0] + + + + + WDOGITOP + Integration test output set + 0x0F04 + read-write + 0x00000000 + + + WDOGINT + Set output value + [1:1] + + + WDOGRES + Set output value + [0:0] + + + + + WDOGPERIPHID0 + Peripheral ID + 0x0FE0 + read-only + 0x00000024 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID1 + Peripheral ID + 0x0FE4 + read-only + 0x000000B8 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID2 + Peripheral ID + 0x0FE8 + read-only + 0x0000001B + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID3 + Peripheral ID + 0x0FEC + read-only + 0x00000000 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPCELLID0 + PrimeCell ID + 0x0FF0 + read-only + 0x0000000D + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID1 + PrimeCell ID + 0x0FF4 + read-only + 0x000000F0 + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID2 + PrimeCell ID + 0x0FF8 + read-only + 0x00000005 + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID3 + PrimeCell ID + 0x0FFC + read-only + 0x000000B1 + + + PCELLID + Prime Cell ID + [7:0] + + + + + + + + + TRNG + 1.0 + True Random Number Generator + 0x40027000 + + 0 + 0x00000400 + registers + + + TRNG + 42 + + TRNG + + + IMR + Interrupt Mask Register + 0x0100 + read-write + 0x0000000F + + + VN_ERR_INT_MASK + Mask the Von Neumann error + [3:3] + + + CRNGT_ERR_INT_MASK + Mask the CRNGT error + [2:2] + + + AUTOCORR_ERR_INT_MASK + Mask the Autocorrelation error + [1:1] + + + EHR_VALID_INT_MASK + Mask when the TRNG has collected 192 bits + [0:0] + + + + + ISR + Interrupt Status Register + 0x0104 + read-only + 0x00000000 + + + VN_ERR + Indicates a Von Neumann error + [3:3] + + + CRNGT_ERR + Indicates a Continuous Random Number Generation Testing (CRNGT) error + [2:2] + + + AUTOCORR_ERR + Indicates that the Autocorrelation test failed four times in a row + [1:1] + + + EHR_VALID + 192 bits have been collected in the TRNG + [0:0] + + + + + ICR + Interrupt Clear Register + 0x0108 + read-write + 0x00000000 + + + VN_ERR + Clears a Von Neumann error + [3:3] + + + CRNGT_ERR + Clear a Continuous Random Number Generation Testing (CRNGT) error + [2:2] + + + AUTOCORR_ERR + Software cannot clear this bit. Only a TRNG reset can clear this bit + [1:1] + + + EHR_VALID + Set to 1 after the EHR_DATA[0,1,2,3,4,5] registers have been read + [0:0] + + + + + CONFIG + Configuration Register + 0x010C + read-write + 0x00000000 + + + RND_SRC_SEL + Selects the number of inverters (out of four possible selections) in the ring oscillator + [1:0] + + + + + VALID + Valid Register + 0x0110 + read-only + 0x00000000 + + + EHR_VALID + Indicates that the collection of bits in the TRNG is complete + [0:0] + + + + + EHR_DATA0 + Entropy Holding Register Data Register + 0x0114 + read-only + 0x00000000 + + + EHR_DATA + 32 Bits of Entropy Holding Register + [31:0] + + + + + EHR_DATA1 + Entropy Holding Register Data Register + 0x0118 + + + EHR_DATA2 + Entropy Holding Register Data Register + 0x011C + + + EHR_DATA3 + Entropy Holding Register Data Register + 0x0120 + + + EHR_DATA4 + Entropy Holding Register Data Register + 0x0124 + + + EHR_DATA5 + Entropy Holding Register Data Register + 0x0128 + + + RND_SOURCE_ENABLE + Random Source Enable Register + 0x012C + read-write + 0x00000000 + + + RND_SRC_EN + The entropy source, ring oscillator, is enabled + [0:0] + + + + + SAMPLE_CNT1 + Section TBD + 0x0130 + read-write + 0x0000FFFF + + + SAMPLE_CNTR1 + Sets the number of clk cycles between two consecutive ring oscillator samples + [31:0] + + + + + AUTOCORR_STATISTIC + Auto-correlator Statistic Register + 0x0134 + read-write + 0x00000000 + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails + [21:14] + + + AUTOCORR_TRYS + Count each time an autocorrelation test starts + [13:0] + + + + + DEBUG_CONTROL + Section TBD + 0x0138 + read-write + 0x00000000 + + + AUTO_CORRELATE_BYPASS + The autocorrelation test in the TRNG module is bypassed + [3:3] + + + CRNGT_BYPASS + The CRNGT test in the TRNG is bypassed + [2:2] + + + VNC_PYPASS + The Von Neumann balancer is bypassed + [1:1] + + + + + SW_RESET + Reset Register + 0x0140 + read-write + 0x00000000 + + + SW_RESET + Writing 1 to this register causes an internal TRNG reset + [0:0] + + + + + BUSY + Busy Register + 0x01B8 + read-only + 0x00000000 + + + BUSY + Reflects the status of the rng_busy signal + [0:0] + + + + + RST_BITS_COUNTER + Reset Bits Counter Register + 0x01BC + read-write + 0x00000000 + + + RST_BITS_COUNTER + Writing any value to this bit resets the bits counter and TRNG valid registers + [0:0] + + + + + BIST_CNTR0 + BIST Counter Register + 0x01E0 + read-only + 0x00000000 + + + ROSC_CNTR_VAL + Returns the results of the TRNG BIST counter + [21:0] + + + + + BIST_CNTR1 + BIST Counter Register + 0x01E4 + + + BIST_CNTR2 + BIST Counter Register + 0x01E8 + + + + + + + ETH + 1.1 + Ethernet Block + 0x40004000 + + 0 + 0x00002000 + registers + + + Ethernet + 36 + + ETH + + + + MAC_CONFIG + Operation mode register for the MAC + 0x0000 + read-write + 0x00000000 + + + WD + Watchdog disable + [23:23] + + + JD + Jabber Disable + [22:22] + + + BE + Frame Burst Enable + [21:21] + + + JE + Jumbo Frame Enable + [20:20] + + + IFG + Inter-Frame Gap + [19:17] + + + DCRS + Disable Carrier Sense During Transmission + [16:16] + + + PS + Port Select + [15:15] + + + FES + Speed + [14:14] + + + DRO + Disable Receive Own + [13:13] + + + LM + Loopback Mode + [12:12] + + + DM + Duplex Mode + [11:11] + + + IPC + Checksum Offload + [10:10] + + + DR + Disable Retry + [9:9] + + + ACS + Automatic Pad, or CRC Stripping + [7:7] + + + BL + Back-Off-Limit + [6:5] + + + DC + Deferral Check + [4:4] + + + TE + Transmitter Enable + [3:3] + + + RE + Receiver Enable + [2:2] + + + PRELEN + Preamble Length for Transmit frames + [1:0] + + + + + MAC_FRAME_FLTR + Contains the frame filtering controls + 0x0004 + read-write + 0x00000000 + + + RA + Receive All + [31:31] + + + DNTU + Drop non TCP/UDP over IP Frames + [21:21] + + + VFTE + VLAN Tag Filter Enable + [16:16] + + + HDF + Hash or Perfect Filter + [10:10] + + + SAF + Source Address Filter Enable + [9:9] + + + SAIF + SA Inverse Filtering + [8:8] + + + PCF + Pass Control Frames + [7:6] + + + DBF + Disable Broadcast Frames + [5:5] + + + PM + Pass All Multicast + [4:4] + + + DAIF + DA Inverse Filtering + [3:3] + + + HMC + Hash Multicast + [2:2] + + + HUC + Hash Unicast + [1:1] + + + PR + Promiscuous Mode + [0:0] + + + + + MAC_GMII_ADDR + Controls the management cycles to an external PHY + 0x0010 + read-write + 0x00000000 + + + PA + Physical Layer Address + [15:11] + + + GR + GMII Register + [10:6] + + + CR + CSR Clock Range + [5:2] + + + GW + GMII Write/Read + [1:1] + + + GB + GMII Busy + [0:0] + + + + + MAC_GMII_DATA + Contains the data to be written to or read from the PHY register + 0x0014 + read-write + 0x00000000 + + + GD + GMII Data + [15:0] + + + + + MAC_FLOW_CTRL + Controls the generation of control frames + 0x0018 + read-write + 0x00000000 + + + PT + Pause time + [31:16] + + + DZPQ + Disable Zero-Quanta Pause + [7:7] + + + PLT + Pause Low Threshold + [5:4] + + + UP + Unicast Pause Frame Detect + [3:3] + + + RFE + Receive Flow Control Enable + [2:2] + + + TFE + Transmit Flow Control Enable + [1:1] + + + FCB_BPA + Flow Control Busy or Backpressure Activate + [0:0] + + + + + MAC_VLAN_TAG + Identifies IEEE 802.1Q VLAN type frames + 0x001C + read-write + 0x00000000 + + + ESVL + Enable S-VLAN + [18:18] + + + VTIM + VLAN Tag Inverse Match Enable + [17:17] + + + ETV + Enable 12-Bit VLAN Tag Comparison + [16:16] + + + VL + VLAN Tag identifier for Receive Frames + [15:0] + + + + + MAC_DEBUG + Gives the status of the various internal blocks for debugging + 0x0024 + read-only + 0x00000000 + + + TXSTSFSTS + MTL TxStatus FIFO Full Status + [25:25] + + + TXFSTS + MTL Tx FIFO Not Empty Status + [24:24] + + + TWCSTS + MTL Tx FIFO Write Controller Status + [22:22] + + + TRCSTS + MTL Tx FIFO Read Controller Status + [21:20] + + + TXPAUSED + MAC Transmitter in Pause + [19:19] + + + TFCSTS + PAC Transmit Frame Controller Status + [18:17] + + + TPESTS + MAC GMII or MII Transmit Protocol Engine Status + [16:16] + + + RXFSTS + MTL RxFIFO Fill-Level Status + [9:8] + + + RRCSTS + MTL RxFIFO Read Controller State + [6:5] + + + RWCSTS + MTL Rx FIFO Write Controller Active Status + [4:4] + + + RFCFCSTS + MAC Receive Frame FIFO Controller Status + [2:1] + + + RPESTS + MAC GMII or MII Receive Protocol Engine Status + [0:0] + + + + + MAC_INTR_STAT + Contains the interrupt status + 0x0038 + read-only + 0x00000000 + + + TSIS + Timestamp Interrupt Status + [9:9] + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status + [7:7] + + + MMCTXIS + MMC Transmit Interrupt Status + [6:6] + + + MMCRXIS + MMC Receive Interrupt Status + [5:5] + + + MMCIS + MMC Interrupt Status + [4:4] + + + + + MAC_INTR_MASK + Contains the masks for generating interrupt + 0x003C + read-write + 0x00000000 + + + TSIM + Timestamp Interrupt Mask + [9:9] + + + + + MAC_ADDR_H + Contains the high 16-bits of the first MAC Address + 0x0040 + read-write + 0x8000FFFF + + + AE + Address Enable, This bit is always set to 1 + [31:31] + read-only + + + ADDRHI + MAC Address0[47:32] + [15:0] + read-only + + + + + MAC_ADDR_L + Contains the Low 32-bits of the first MAC Address + 0x0044 + read-write + 0xFFFFFFFF + + + ADDRLO + MAC Address0[31:0] + [31:0] + read-only + + + + + MAC_WDOG_TO + Controls the watchdog time-out for received frames + 0x00DC + read-write + 0x00000000 + + + PWE + Programmable Watchdog Enable + [16:16] + + + WTO + Watchdog Timeout + [13:0] + + + + + + MMC_CNTRL + MMC Control Register + 0x0100 + read-write + 0x00000000 + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames + [8:8] + + + CNTPRSTLVL + Full-Half Preset + [5:5] + + + CNTPRST + Counters Preset + [4:4] + + + CNTFREEZ + MMC Counter Freeze + [3:3] + + + RSTONRD + Reset on Read + [2:2] + + + CNTSTOPRO + Counter Stop Rollover + [1:1] + + + CNTRST + Counters Reset + [0:0] + + + + + MMC_INTR_RX + MMC Receive Interrupt Register + 0x0104 + read-write + 0x00000000 + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status + [25:25] + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status + [24:24] + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status + [23:23] + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status + [22:22] + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status + [21:21] + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status + [20:20] + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status. + [19:19] + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status + [18:18] + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status + [17:17] + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. + [16:16] + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + [15:15] + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status + [14:14] + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status + [13:13] + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status + [12:12] + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status + [11:11] + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status + [10:10] + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status + [9:9] + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status + [8:8] + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status + [7:7] + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status + [6:6] + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status + [5:5] + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status + [4:4] + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status + [3:3] + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status + [2:2] + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status + [1:1] + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status + [0:0] + + + + + MMC_INTR_TX + MMC Transmit Interrupt Register + 0x0108 + read-write + 0x00000000 + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status + [25:25] + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status + [24:24] + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status + [23:23] + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status + [22:22] + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status + [21:21] + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status + [20:20] + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status + [19:19] + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status + [18:18] + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status + [17:17] + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status + [16:16] + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status + [15:15] + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status + [14:14] + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status + [13:13] + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status + [12:12] + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status + [11:11] + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status + [10:10] + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + [9:9] + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + [8:8] + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status + [7:7] + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status + [6:6] + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status + [5:5] + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status + [4:4] + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status + [3:3] + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status + [2:2] + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status + [1:1] + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status + [0:0] + + + + + MMC_INTR_MASK_RX + MMC Receive Interrupt Mask Register + 0x010c + read-write + 0x00000000 + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask + [25:25] + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask + [24:24] + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask + [23:23] + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask + [22:22] + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask + [21:21] + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask + [20:20] + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask + [19:19] + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask + [18:18] + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask + [17:17] + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. + [16:16] + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + [15:15] + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + [14:14] + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + [13:13] + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + [12:12] + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask + [11:11] + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask + [10:10] + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask + [9:9] + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask + [8:8] + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask + [7:7] + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask + [6:6] + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask + [5:5] + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask + [4:4] + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask + [3:3] + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask + [2:2] + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask. + [1:1] + + + RXGBFRMIM + MMC Receive Good Bad Frame Counter Interrupt Mask + [0:0] + + + + + MMC_INTR_MASK_TX + MMC Transmit Interrupt Mask Register + 0x0110 + read-write + 0x00000000 + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask + [25:25] + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask + [24:24] + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask + [23:23] + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask + [22:22] + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask + [21:21] + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask + [20:20] + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask + [19:19] + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask + [18:18] + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask + [17:17] + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask + [16:16] + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask + [15:15] + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask + [14:14] + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask + [13:13] + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask + [12:12] + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask + [11:11] + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask + [10:10] + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + [9:9] + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + [8:8] + + + TX256T511OCTGBFIM + MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + [7:7] + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + [6:6] + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + [5:5] + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask + [4:4] + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask + [3:3] + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask + [2:2] + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask + [1:1] + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask + [0:0] + + + + + TXOCTETCOUNT_GB + MMC Transmit Count + 0x0114 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + TXFRAMECOUNT_GB + MMC Frame Count Register + 0x0118 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXBCASTFRAMES_G + MMC Good Broadcast Frames Register + 0x011c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMCASTFRAMES_G + MMC Good Multicast Frames Register + 0x0120 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX64OCT_GB + MMC Good and bad Frames transmitted with length 64 + 0x0124 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX65TO127OCT_GB + MMC Good and bad Frames transmitted with length 65 to 127 + 0x0128 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX128TO255OCT_GB + MMC Good and bad Frames transmitted with length 128 to 255 + 0x012c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX256TO511OCT_GB + MMC Good and bad Frames transmitted with length 256 to 511 + 0x0130 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX512TO1023OCT_GB + MMC Good and bad Frames transmitted with length 512 to 1023 + 0x0134 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX1024MAXOCT_GB + MMC Good and bad Frames transmitted with length 1024 to max bytes + 0x0138 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXUCASTFRAME_GB + MMC number of good and bad unicast frames transmitted + 0x013c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMCASTFRAME_GB + MMC number of good and bad MULTIcast frames transmitted + 0x0140 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXBCASTFRAME_GB + MMC number of good and bad broadcast frames transmitted + 0x0144 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXUNDERERR + MMC number of frames aborted because of frame underflow error + 0x0148 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXSINGLECOL_G + MMC Number of successfully transmitted frames after a single collision + 0x014c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMULTICOL_G + MMC Number of successfully transmitted frames after multiple collisions + 0x0150 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXDEFERRED + MMC Number of successfully transmitted frames after a deferral + 0x0154 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXLATECOL + MMC Number of aborted frames because of late collision error + 0x0158 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXEXESSCOL + MMC Number of aborted frames because of excessive collision errors + 0x015c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXCARRIERERROR + MMC Number of aborted frames because of carrier sense error + 0x0160 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXOCTETCOUNT_G + MMC Number of bytes transmitted frames only in good frames + 0x0164 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + TXFRAMECOUNT_G + MMC Number of good frames transmitted + 0x0168 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXEXCESSDEF + MMC Number of frames aborted because of excessive deferral error + 0x016c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXPAUSEFRAMES + MMC Number of good pause frames transmitted + 0x0170 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXLANFRAMES_G + MMC Number of good VLAN frames transmitted + 0x0174 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXOVERSIZE_G + MMC Number of frames transmitted without errors + 0x0178 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXFRAMECOUNT_GB + MMC Number of good and bad frames received + 0x0180 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOCTETCOUNT_GB + MMC Number of bytes received in good and bad frames + 0x0184 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + RXOCTETCOUNT_G + MMC Number of bytes received in good frames only + 0x0188 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + RXBCASTFRAMES_G + MMC Number of good broadcast frames received + 0x018c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXMCASTFRAMES_G + MMC Number of good multicast frames received + 0x0190 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXCRCERROR + MMC Number of frames received with CRC error + 0x0194 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXALIGNERROR + MMC Number of frames received with alignment error + 0x0198 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXRUNTERROR + MMC Number of frames received with runt error + 0x019c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXJABBERERROR + MMC Number of giant frames received with length greater than 1518 bytes and with CRC error + 0x01a0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXUNDERSIZE_G + MMC Number of frames received with length less than 64 bytes + 0x01a4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOVERSIZE_G + MMC Number of frames received without errors with length greater than the max size + 0x01a8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX64OCTETS_GB + MMC Number of good and bad frames received with length 64 bytes + 0x01ac + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX65TO127OCT_GB + MMC Number of good and bad frames received with length between 65 and 127 bytes + 0x01b0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX128TO255OCT_GB + MMC Number of good and bad frames received with length between 128 and 255 bytes + 0x01b4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX256TO511OCT_GB + MMC Number of good and bad frames received with length between 256 and 511 bytes + 0x01b8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX512TO1023OCT_GB + MMC Number of good and bad frames received with length between 512 and 1023 bytes + 0x01bc + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX1024MAXOCT_GB + MMC Number of good and bad frames received with length between 1024 and max size bytes + 0x01C0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXUCASTFRAMES_G + MMC Number of received good unicast frames + 0x01C4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXLENGTHERROR + MMC Number of frames received with length error + 0x01C8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOUTRANGETYPE + MMC Number of frames received with length field not equal to the valid frame size + 0x01CC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXPAUSEFRAMES + MMC Number of good and valid Pause frames received + 0x01D0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXFIFOOVERFLOW + MMC Number of missed received frames because of FIFO overflow + 0x01D4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXVLANFRAMES_GB + MMC Number of good and bad VLAN frames received + 0x01D8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXWDOGERROR + MMC Number of frames received with error because of watchdog timeout error + 0x01DC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXRCVERROR + MMC Number of frames received with Receive error or Frame Extension error + 0x01E0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXCTRLFRAMES_G + MMC Number of received good control frames + 0x01E4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + VLAN_INCREPLACE + Holds the VLAN Tag for insertion into or replacement in the transmit frames + 0x0584 + read-write + 0x00000000 + + + CSVL + C-VLAN or S-VLAN + [19:19] + + + VLP + VLAN Priority Control + [18:18] + + + VLC + VLAN Tag Control in Transmit Frames + [17:16] + + + VLT + VLAN Tag for Transmit Frames + [15:0] + + + + + VLAN_HASHTABLE + Holds the VLAN Hash Table + 0x0588 + read-write + 0x00000000 + + + VLHT + VLAN Hash Table + [15:0] + + + + + TIMESTAMP_CTRL + Controls the IEEE 1588 timestamp generation and update logic + 0x0700 + read-write + 0x00000000 + + + ATSEN3 + Auxiliary Snapshot 3 Enable + [28:28] + + + ATSEN2 + Auxiliary Snapshot 2 Enable + [27:27] + + + ATSEN1 + Auxiliary Snapshot 1 Enable + [26:26] + + + ATSEN0 + Auxiliary Snapshot 0 Enable + [25:25] + + + ATSFC + Auxiliary Snapshot FIFO Clear + [24:24] + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering + [18:18] + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + [17:16] + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master + [15:15] + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages + [14:14] + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + [13:13] + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP + [12:12] + + + TSIPENA + Enable Processing of PTP over Ethernet Frames + [11:11] + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format + [10:10] + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control + [9:9] + + + TSENALL + Enable Timestamp for All Frames + [8:8] + + + TSADDRREG + Addend Reg Update + [5:5] + + + TSTRIG + Timestamp Interrupt Trigger Enable + [4:4] + + + TSUPDT + Timestamp Update + [3:3] + + + TSINIT + Timestamp Initialize + [2:2] + + + TSCFUPDT + Timestamp Fine or Coarse Update + [1:1] + + + TSENA + Timestamp Enable + [0:0] + + + + + SUBSEC_INC + Holds the 8-bit value by which the Sub-Second register is incremented + 0x0704 + read-write + 0x00000000 + + + SSINC + Sub-Second Increment Valuee + [7:0] + + + + + SYSTIME_SECONDS + Holds the lower 32 bits of the second field of the system time + 0x0708 + read-only + 0x00000000 + + + TSS + Timestamp Second + [31:0] + + + + + SYSTIME_NANOSEC + Holds 32 bits of the nano-second field of the system time + 0x070C + read-only + 0x00000000 + + + TSSS + Timestamp Sub Seconds + [30:0] + + + + + SYSTIME_SECSUPDAT + Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value + 0x0710 + read-write + 0x00000000 + + + TSS + Timestamp Second + [31:0] + + + + + SYSTIME_NSECUP + Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value + 0x0714 + read-write + 0x00000000 + + + ADDSUB + Add or Subtract Time + [31:31] + + + TSSS + Timestamp Sub Seconds + [30:0] + + + + + TIMESTAMPADDEND + This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency + 0x0718 + read-write + 0x00000000 + + + TSAR + Timestamp Addend Register + [31:0] + + + + + TARGET_TIME_SECS + Holds the high 32-bits of time to be compared with the system time + 0x071C + read-write + 0x00000000 + + + TSTR + Target Time Seconds Registe + [31:0] + + + + + TARGET_TIME_NSEC + Holds the lower 32-bits of time to be compared with the system time + 0x0720 + read-write + 0x00000000 + + + TRGTBUSY + 32 Bits of Hash Table + [31:31] + + + TTSLO + Target Timestamp Low Register + [30:0] + + + + + + DMA_BUS_MODE + Controls the DMA Host Interface Mode + 0x1000 + read-write + 0x00020101 + + + RIB + Rebuild INCRx Burst + [31:31] + + + PRWG + Channel Priority Weights + [29:28] + + + TXPR + Transmit Priority + [27:27] + + + MB + Mixed Burst + [26:26] + + + AAL + Address-Aligned Beats + [25:25] + + + PBLx8 + PBLx8 Mode + [24:24] + + + USP + Use Separate PBL + [23:23] + + + RPBL + Rx DMA PBL + [22:17] + + + FB + Fixed Burste + [16:16] + + + PR + Priority Ratio + [15:14] + + + PBL + Programmable Burst Lengthe + [13:8] + + + DSL + Descriptor Skip Length + [6:2] + + + DA + DMA Arbitration Scheme + [1:1] + + + SWR + Software Reset (Read, Write Set, and Self Clear) + [0:0] + + + + + DMA_TX_POLL_DEMAND + Used by the host to instruct the DMA to poll the transmit Descriptor list + 0x1004 + read-write + 0x00000000 + + + TPD + Transmit Poll Demand (Read Only and Write Trigger) + [31:0] + + + + + DMA_RX_POLL_DEMAND + Used by the host to instruct the DMA to poll the Receive Descriptor list + 0x1008 + read-write + 0x00000000 + + + RPD + Receive Poll Demand (Read Only and Write Trigger) + [31:0] + + + + + DMA_RX_DESC_LIST_ADDR + Points the DMA to the start of the Receive Descriptor list + 0x100C + read-write + 0x00000000 + + + RDESLA + Start of Receive List + [31:0] + + + + + DMA_TX_DESC_LIST_ADDR + Points the DMA to the start of the Transmit Descriptor list + 0x1010 + read-write + 0x00000000 + + + TDESLA + Start of Transmit List + [31:0] + + + + + DMA_STATUS + Used to determine the status of the DMA + 0x1014 + read-only + 0x00000000 + + + TTI + Timestamp Trigger Interrupt + [29:29] + + + GMI + GMAC MMC Interrupt + [27:27] + + + EB + Error Bits + [25:23] + + + TS + Transmit Process State + [22:20] + + + RS + Receive Process State + [19:17] + + + NIS + Normal Interrupt Summary + [16:16] + + + AIS + Abnormal Interrupt Summary + [15:15] + + + ERI + Early Receive Interrupt + [14:14] + + + FBI + Fatal Bus Error Interruptble + [13:13] + + + ETI + Early Transmit Interrupt + [10:10] + + + RWT + Receive Watchdog Timeout + [9:9] + + + RPS + Receive Process Stopped + [8:8] + + + RU + Receive Buffer Unavailable + [7:7] + + + RI + Receive Interrupt + [6:6] + + + UNF + Transmit Underflow + [5:5] + + + OVF + Receive Underflow + [4:4] + + + TJT + Transmit Jabber Timeout + [3:3] + + + TU + Transmit Buffer Unavailable + [2:2] + + + TPS + Transmit Process Stopped + [1:1] + + + TI + Transmit Interrupt + [0:0] + + + + + DMA_OPER_MODE + Sets the Receive and Transmit operation mode and command + 0x1018 + read-write + 0x00000000 + + + DT + Disable Dropping of TCP/IP Checksum Error Frames + [26:26] + + + RSF + Receive Store and Forward + [25:25] + + + DFF + Disable Flushing of Received Frames + [24:24] + + + TSF + Transmit Store and Forward + [21:21] + + + FTF + Flush Transmit FIFO + [20:20] + + + TTC + Transmit Threshold Control + [16:14] + + + ST + Start or Stop Transmission Command + [13:13] + + + RFD + Threshold for Deactivating Flow Control + [12:11] + + + RFA + Threshold for Activating Flow Control + [10:9] + + + FEF + Forward Error Frames + [7:7] + + + FUF + Forward Undersized Good Frames + [6:6] + + + DGF + Drop Giant Frames + [5:5] + + + RTC + Receive Threshold Control + [4:3] + + + OSF + Operate on Second Frame + [2:2] + + + SR + Start or Stop Receive + [1:1] + + + + + DMA_INTR_EN + Enables the interrupts reported in the status register + 0x101C + read-write + 0x00000000 + + + NIE + Normal Interrupt Summary Enable + [16:16] + + + AIE + Abnormal Interrupt Summary Enable + [15:15] + + + ERE + Early Receive Interrupt Enable + [14:14] + + + FBE + Fatal Bus Error Enable + [13:13] + + + ETE + Early Transmit Interrupt Enable + [10:10] + + + RWE + Receive Watchdog Timeout Enable + [9:9] + + + RSE + Receive Stopped Enable + [8:8] + + + RUE + Receive Buffer Unavailable Enable + [7:7] + + + RIE + Receive Interrupt Enable + [6:6] + + + UNE + Underflow Interrupt Enable + [5:5] + + + OVE + Overflow Interrupt Enable + [4:4] + + + THE + Transmit Jabber Timeout Enable + [3:3] + + + TUE + Transmit Buffer Unavailable Enable + [2:2] + + + TSE + Transmit Stopped Enable + [1:1] + + + TIE + Transmit Interrupt Enable + [0:0] + + + + + DMA_MISS_OVER_COUNTER + Contains the counters for discarded frames because no Receive Descriptor is available + 0x1020 + read-write + 0x00000000 + + + OVFCNTOVF + This bit is set every time the Overflow Frame Counter (Bits[27:17])overflows + [28:28] + + + OVFFRMCNT + This field indicates the number of frames missed by the application + [27:17] + + + MISCNTOVF + This bit is set every time Missed Frame Counter (Bits[15:0]) overflows + [16:16] + + + MISFRMCNT + This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. + [15:0] + + + + + DMA_RX_INTR_WDOG_TIMER + Watchdog timeout for Receive Interrupt from DMA + 0x1024 + read-write + 0x00000000 + + + RIWT + These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set. + [7:0] + + + + + DMA_AHB_STATUS + Provides the active status of the read and write channels of the AHB master interface + 0x102C + read-write + 0x00000000 + + + AHBMASTRSTS + When high, indicates that the AHB master interface FSMs are in the non-idle state + [0:0] + + + + + DMA_CURR_TX_DESC + Contains the start address of the current Transmit Descriptor read by the DMA + 0x1048 + read-write + 0x00000000 + + + CURTDESAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_RX_DESC + Contains the start address of the current Receive Descriptor read by the DMA + 0x104C + read-write + 0x00000000 + + + CURRDESAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_TX_BUFR_ADDR + Contains the start address of the current Receive Descriptor read by the DMA + 0x1050 + read-write + 0x00000000 + + + CURTBUFAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_RX_BUFR_ADDR + Contains the current Receive Buffer address read by the DMA + 0x1054 + read-write + 0x00000000 + + + CURTBUFAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + + + \ No newline at end of file diff --git a/va416xx/va416xx/svd/va416xx.svd.patched b/va416xx/va416xx/svd/va416xx.svd.patched new file mode 100644 index 0000000..5e7a24a --- /dev/null +++ b/va416xx/va416xx/svd/va416xx.svd.patched @@ -0,0 +1,12271 @@ + + + VORAGO TECHNOLOGIES + SST + va416xx + M4 + 1.3 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 100MHz + VORAGO Technologies \n +\n +----------------------------------------------------------------------------\n + Copyright (c) 2013-2020 VORAGO Technologies\n +\n + BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n + AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n +\n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n + FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n + + CM4 + r0p1 + little + false + true + 4 + false + + system_va416xx + VOR_ + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CLKGEN + 1.0 + Clock Generation Peripheral + 0x40006000 + + 0x0 + 0x100 + registers + + + LoCLK + 45 + + + + CTRL0 + Clock Generation Module Control Register 0 + 0x0 + 0x00000030 + + + SYS_CLK_LOST_DET_EN + Enable the circuit that detects loss of SYS_CLK + [31:31] + + + PLL_RESET + Writing this bit to 1 puts the PLL into reset + [30:30] + + + CLK_DIV_SEL + Selects the PLL out divider to divide by 1/2/4/8 + [29:28] + + + PLL_CLKR + PLL Symbol; selects the values 1-16 for the reference divider + [27:24] + + + PLL_CLKF + PLL Symbol; selects the values 1-64 for the multiplication factor + [23:18] + + + PLL_CLKOD + PLL Symbol; selects the values 1-16 for the post VCO divider + [17:14] + + + PLL_BWADJ + PLL Symbol; selects the values 1-64 for the bandwidth divider + [13:8] + + + PLL_TEST + PLL Symbol; Reference-to-counters-to-output bypass when high + [7:7] + + + PLL_BYPASS + PLL Symbol; reference-to-output bypass when high + [6:6] + + + PLL_PWDN + PLL Symbol; power down when high + [5:5] + + + PLL_INTFB + PLL Symbol; select internal feedback path when high rather than FCLK + [4:4] + + + CLKSEL_SYS + Input clock select to PLL + [3:2] + + + REF_CLK_SEL + PLL Reference Clock Select + [1:0] + + + + + STAT + Clock Generation Module Status Register + 0x4 + read-only + 0x00000000 + + + SYSCLKLOST + Set when SYS_CLK has dropped to less than 1MHz + [3:3] + read-only + + + LOCKLOST + LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles + [2:2] + read-only + + + RFSLIP + Reference cycle slip output (CLKOUT frequency high) + [1:1] + read-only + + + FBSLIP + Feedback cycle slip output (CLKOUT frequency low) + [0:0] + read-only + + + + + CTRL1 + Clock Generation Module Control Register 1 + 0x8 + read-write + 0x00000000 + + + ADC_CLK_DIV_SEL + Clock divider select for ADC + [6:5] + + + XTAL_N_EN + Enables XTAL_N output + [4:4] + + + XTAL_EN + Enables the crystal oscillator + [3:3] + + + PLL_LOST_LOCK_DET_EN + Enables the PLL lock lost detection circuit + [2:2] + + + PLL_LCK_DET_REARM + Resets/Rearms the PLL lock detect circuit + [1:1] + + + SYS_CLK_LOST_DET_REARM + Resets/Rearms the SYS_CLK lost detection feature + [0:0] + + + + + + + SYSCONFIG + 1.0 + System Configuration Peripheral + 0x40010000 + + 0x0 + 0x1000 + registers + + + LVD + 46 + + + EDAC_MBE + 76 + + + EDAC_SBE + 77 + + + + RST_STAT + System Reset Status + 0x0 + read-write + 0x00000000 + + + POR + Power On Reset Status + [0:0] + + + EXTRST + External Reset Status + [1:1] + + + SYSRSTREQ + SYSRESETREQ Reset Status + [2:2] + + + LOOKUP + LOOKUP Reset Status + [3:3] + + + WATCHDOG + WATCHDOG Reset Status + [4:4] + + + MEMERR + Memory Error Reset Status + [5:5] + read-only + + + + + RST_CNTL_ROM + ROM Reset Control + 0x4 + 0x0000003F + + + RST_CNTL_RAM0 + RAM Reset Control + 0x8 + 0x0000003F + + + RST_CNTL_RAM1 + RAM Reset Control + 0xC + 0x0000003F + + + ROM_PROT + ROM Protection Configuration + 0x10 + 0x00000000 + + + WREN + ROM Write Enable Bit + [0:0] + + + + + ROM_SCRUB + ROM Scrub Period Configuration + 0x14 + read-write + 0x00000000 + + + VALUE + Counter divide value + [23:0] + + + RESET + Reset Counter + [31:31] + write-only + oneToClear + + + + + RAM0_SCRUB + RAM0 Scrub Period Configuration + 0x18 + + + RAM1_SCRUB + RAM1 Scrub Period Configuration + 0x1C + + + IRQ_ENB + Enable EDAC Error Interrupt Register + 0x20 + read-write + 0x00000000 + + + ROMMBE + ROM Multi Bit Interrupt + [0:0] + + + ROMSBE + ROM Single Bit Interrupt + [1:1] + + + RAM0MBE + RAM0 Multi Bit Interrupt + [2:2] + + + RAM0SBE + RAM0 Single Bit Interrupt + [3:3] + + + RAM1MBE + RAM1 Multi Bit Interrupt + [4:4] + + + RAM1SBE + RAM1 Single Bit Interrupt + [5:5] + + + + + IRQ_RAW + Raw EDAC Error Interrupt Status + 0x24 + read-only + 0x00000000 + + + IRQ_END + Enabled EDAC Error Interrupt Status + 0x28 + read-only + 0x00000000 + + + IRQ_CLR + Clear EDAC Error Interrupt Status + 0x2C + write-only + 0x00000000 + oneToClear + + + RAM0_SBE + Count of RAM0 EDAC Single Bit Errors + 0x30 + 0x00000000 + + + COUNT + RAM0 EDAC Single Bit Errors + [15:0] + + + + + RAM1_SBE + Count of RAM1 EDAC Single Bit Errors + 0x34 + + + RAM0_MBE + Count of RAM0 EDAC Multi Bit Errors + 0x38 + 0x00000000 + + + COUNT + RAM0 Multi Bit Errors + [15:0] + + + + + RAM1_MBE + Count of RAM1 EDAC Multi Bit Errors + 0x3C + + + ROM_SBE + Count of ROM EDAC Single Bit Errors + 0x40 + + + ROM_MBE + Count of ROM EDAC Multi Bit Errors + 0x44 + + + ROM_RETRIES + ROM BOOT Retry count + 0x48 + read-only + 0x00000000 + + + COUNT + Count of ROM block Retries + [7:0] + + + + + REFRESH_CONFIG_H + Register Refresh Rate for TMR registers + 0x4C + 0x00000000 + + + DIVCOUNT + Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles + [7:0] + + + TESTMODE + Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly. + [31:30] + + + + + TIM_RESET + TIM Reset Control + 0x50 + 0xFFFFFFFF + + + TIM_RESET + Reset of a given TIMER + [23:0] + + + + + TIM_CLK_ENABLE + TIM Enable Control + 0x54 + 0x00000000 + + + TIMERS + Clock enable of a given TIMER + [23:0] + + + + + PERIPHERAL_RESET + Peripheral Reset Control + 0x58 + 0x7F7BEFFF + + + SPI0 + Resetn of SPI0 + [0:0] + + + SPI1 + Resetn of SPI1 + [1:1] + + + SPI2 + Resetn of SPI2 + [2:2] + + + SPI3 + Resetn of SPI3 + [3:3] + + + UART0 + Resetn of UART0 + [4:4] + + + UART1 + Resetn of UART1 + [5:5] + + + UART2 + Resetn of UART2 + [6:6] + + + I2C0 + Resetn of I2C0 + [7:7] + + + I2C1 + Resetn of I2C1 + [8:8] + + + I2C2 + Resetn of I2C2 + [9:9] + + + CAN0 + Resetn of CAN0 + [10:10] + + + CAN1 + Resetn of CAN1 + [11:11] + + + TRNG + Resetn of TRNG + [12:12] + + + ADC + Resetn of ADC + [13:13] + + + DAC + Resetn of DAC + [14:14] + + + DMA + Resetn of DMA + [15:15] + + + EBI + Resetn of EBI + [16:16] + + + ETH + Resetn of Ethernet + [17:17] + + + SPW + Resetn of SpaceWire + [18:18] + + + CLKGEN + RESETn of PLL in Clock Generation Module + [19:19] + + + IRQ + Resetn of IRQ Router + [20:20] + + + IOCONFIG + Resetn of IO CONFIG + [21:21] + + + UTILITY + Resetn of UTILITY peripheral + [22:22] + + + WDOG + Resetn of WDOG + [23:23] + + + PORTA + Resetn of PORTA + [24:24] + + + PORTB + Resetn of PORTB + [25:25] + + + PORTC + Resetn of PORTC + [26:26] + + + PORTD + Resetn of PORTD + [27:27] + + + PORTE + Resetn of PORTE + [28:28] + + + PORTF + Resetn of PORTF + [29:29] + + + PORTG + Resetn of PORTG + [30:30] + + + + + PERIPHERAL_CLK_ENABLE + Peripheral Enable Control + 0x5C + 0x00880000 + + + SPW_M4_CTRL + SPW M4 control register + 0x60 + 0x00030000 + + + LREN + Lockup reset enable + [17:17] + + + SPW_PAD_EN + SPW pad enable + [16:16] + + + REG_WR_KEY + Fuse-analog register writes enabled when key = 0xfeed + [15:0] + + + + + PMU_CTRL + PMU Control Register + 0x64 + 0x00000000 + + + LVL_SLCT + Select the POK detect level + [1:0] + + + + + WAKEUP_CNT + Wakeup Control + 0x68 + 0x00000007 + + + CNTSTRT + Launch SLP mode in analog block + [3:3] + + + WKUP_CNT + Used to set a time to wake up the processor after the device has been put in a low power state + [2:0] + + + + + EBI_CFG0 + EBI Config Register 0 + 0x6C + 0x00000000 + + + ADDRLOW0 + Lower bound address for CEN0 + [7:0] + + + ADDRHIGH0 + Upper bound address for CEN0 + [15:8] + + + CFGREADCYCLE + Number of cycles for a read - N plus 1 + [18:16] + + + CFGWRITECYCLE + Number of cycles for a write - N plus 1 + [21:19] + + + CFGTURNAROUNDCYCLE + Number of cycles for turnaround - N plus 1 + [24:22] + + + CFGSIZE + 8 bit (0) or 16 bit (1) port size + [25:25] + + + + + EBI_CFG1 + EBI Config Register 1 + 0x70 + 0x00000000 + + + EBI_CFG2 + EBI Config Register 2 + 0x74 + 0x00000000 + + + EBI_CFG3 + EBI Config Register 3 + 0x78 + 0x00000000 + + + ANALOG_CNTL + Analog Control Register + 0x7C + 0x00000000 + + + TMOSC + Test Mode + [0:0] + + + TMPOKDIS + Test Mode + [1:1] + + + TM_ADCMUX_N + Test Mode + [2:2] + + + TM_ADCMUX_P + Test Mode + [3:3] + + + TMRATIO + Test Mode + [4:4] + + + TMATOMUX + Test Mode + [6:5] + + + ADC_STEST + Number of clocks for sample time + [12:9] + + + RCLK_POS_EN + Enable normal test clock + [14:14] + + + RCLK_NEG_EN + Enable inverted test clock + [15:15] + + + APB2CLK_POS_EN + Enable normal APB2CLK for test output + [16:16] + + + APB2CLK_NEG_EN + Enable inverted APB2CLK for test output + [17:17] + + + TM_ANALOG_PD_EN + Enables pull down on analog pads + [18:18] + + + JMP2BOOT + Enables a skip of all delay counters and eFuse read + [19:19] + + + SKIPBOOT + Enables a skip of all delay counters, eFuse read, and boot + [20:20] + + + + + SW_CLKDIV10 + Initial SpW Clock Divider Value + 0x80 + read-write + 0x00000009 + + + SW_CLKDIV10 + Defines the initial value for the SpW clock, defaults to divide by ten + [7:0] + + + + + REFRESH_CONFIG_L + Register Refresh Rate for TMR registers + 0x84 + read-write + 0x0000000F + + + DIVCOUNT + Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles + [31:0] + + + + + DAC0_CAL + DAC0 Calibration Register + 0xFD0 + read-only + 0x00000000 + + + DAC0_CAL + DAC0 Calibration bits + [4:0] + + + + + DAC1_CAL + DAC1 Calibration Register + 0xFD4 + read-only + 0x00000000 + + + DAC1_CAL + DAC1 Calibration bits + [4:0] + + + + + ADC_CAL + ADC Calibration Register + 0xFD8 + read-only + 0x00000000 + + + ADC_CAL + ADC Calibration bits + [4:0] + + + + + BG_CAL + Bandgap Calibration Register + 0xFDC + read-only + 0x00000000 + + + BG_CAL + Bandgap Calibration bits + [2:0] + + + + + DREG_CAL + Digital LDO Regulator Calibration Register + 0xFE0 + read-only + 0x00000000 + + + DREG_CAL + Digital LDO Regulator Calibration bits + [8:0] + + + + + AREG_CAL + Analog LDO Regulator Calibration Register + 0xFE4 + read-only + 0x00000000 + + + AREG_CAL + Analog LDO Regulator Calibration bits + [8:0] + + + + + HBO_CAL + Heart Beat OSC Calibration Register + 0xFE8 + read-only + 0x00000000 + + + OSC_CAL + 1MHz OSC Calibration bit + [3:3] + + + HBO_CAL + Heart Beat OSC Calibration bits + [2:0] + + + + + EF_CONFIG + EFuse Config Register + 0xFEC + read-only + 0x0A800C40 + + + ROM_SPEED + Specifies the speed of ROM_SCK + [1:0] + + + ROM_SIZE + Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset + [5:2] + + + ROM_NOCHECK + When set to 1, the ROM check is skipped + [6:6] + + + BOOT_DELAY + Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset + [9:7] + + + ROM_READ + SPI ROM read instruction code + [17:10] + + + ROM_LATENCY + Number of bits of latency from Address until data from the SPI ROM + [22:18] + + + ROM_ADDRESS + ROM Address Mode + [24:23] + + + ROM_DLYCAP + ROM SPI Delayed capture + [25:25] + + + ROM_STATUS + The first data byte from the SPI ROM following an address is taken as a status byte + [26:26] + + + RM + This bit controls the internal RAM read timing and must be maintained at this value + [27:27] + + + WM + This bit controls the internal RAM write timing and must be maintained at this value + [28:28] + + + + + EF_ID0 + EFuse ID0 Register + 0xFF0 + read-only + 0x00000000 + + + EF_ID1 + EFuse ID1 Register + 0xFF4 + read-only + 0x00000000 + + + PROCID + Processor ID Register + 0xFF8 + read-only + 0x040057E3 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028007E9 + + + MANUFACTURER_ID + MANUFACTURER_ID + [11:0] + read-only + + + PERIPHERAL_ID + PERIPHERAL_ID + [23:16] + read-only + + + PERIPHERAL_VER + PERIPHERAL_VER + [31:24] + read-only + + + + + + + DMA + 1.0 + DMA Controller Block + 0x40001000 + + 0x0 + 0x1000 + registers + + + DMA_ERROR + 43 + + + DMA_ACTIVE0 + 174 + + + DMA_ACTIVE1 + 175 + + + DMA_ACTIVE2 + 176 + + + DMA_ACTIVE3 + 177 + + + DMA_DONE0 + 178 + + + DMA_DONE1 + 179 + + + DMA_DONE2 + 180 + + + DMA_DONE3 + 181 + + + + STATUS + DMA Status + 0x0 + read-only + 0x00000000 + + + TEST_STATUS + Test Status Logic Included + [31:28] + read-write + + + CHNLS_MINUS1 + Number of Available Channels Minus 1 + [20:16] + + + STATE + Current State of the control state machine + [7:4] + + + MASTER_ENABLE + Enable status of the controller + [0:0] + + + + + CFG + DMA Configuration + 0x4 + write-only + 0x00000000 + + + CHNL_PROT_CTRL + HPROT[3:0] + [7:5] + + + MASTER_ENABLE + PLL Symbol; Feedback cycle slip output (CLKOUT frequency low) + [0:0] + read-write + + + + + CTRL_BASE_PTR + Base Pointer for DMA Control Registers + 0x8 + 0x00000000 + + + CTRL_BASE_PTR + Base Pointer for DMA Control Registers + [31:7] + + + + + ALT_CTRL_BASE_PTR + DMA Channel alternate control data base pointer + 0xC + read-write + 0x00000000 + + + ALT_CTRL_BASE_PTR + Base Pointer for Alternate DMA Control Register + [31:0] + + + + + WAITONREQ_STATUS + DMA channel wait on request status + 0x10 + read-only + 0x00000000 + + + CH3 + DMA wait on request + [3:3] + read-write + + + CH2 + DMA wait on request + [2:2] + read-write + + + CH1 + DMA wait on request + [1:1] + read-write + + + CH0 + DMA wait on request + [0:0] + read-write + + + + + CHNL_SW_REQUEST + DMA channel software request + 0x14 + write-only + 0x00000000 + + + CH3 + Channel SW request + [3:3] + read-write + + + CH2 + Channel SW request + [2:2] + read-write + + + CH1 + Channel SW request + [1:1] + read-write + + + CH0 + Channel SW request + [0:0] + read-write + + + + + CHNL_USEBURST_SET + DMA channel useburst set + 0x18 + 0x00000000 + + + CH3 + Channel use burst set + [3:3] + read-write + + + CH2 + Channel use burst set + [2:2] + read-write + + + CH1 + Channel use burst set + [1:1] + read-write + + + CH0 + Channel use burst set + [0:0] + read-write + + + + + CHNL_USEBURST_CLR + DMA channel useburst clear + 0x1C + 0x00000000 + + + CH3 + Channel use burst clear + [3:3] + read-write + + + CH2 + Channel use burst clear + [2:2] + read-write + + + CH1 + Channel use burst clear + [1:1] + read-write + + + CH0 + Channel use burst clear + [0:0] + read-write + + + + + CHNL_REQ_MASK_SET + DMA channel request mask set + 0x20 + 0x00000000 + + + CH3 + Channel Request Mask set + [3:3] + read-write + + + CH2 + Channel Request Mask set + [2:2] + read-write + + + CH1 + Channel Request Mask set + [1:1] + read-write + + + CH0 + Channel Request Mask set + [0:0] + read-write + + + + + CHNL_REQ_MASK_CLR + DMA channel request mask clear + 0x24 + 0x00000000 + + + CH3 + Channel Request Mask clear + [3:3] + read-write + + + CH2 + Channel Request Mask clear + [2:2] + read-write + + + CH1 + Channel Request Mask clear + [1:1] + read-write + + + CH0 + Channel Request Mask clear + [0:0] + read-write + + + + + CHNL_ENABLE_SET + DMA channel enable set + 0x28 + 0x00000000 + + + CH3 + Channel Enable set + [3:3] + read-write + + + CH2 + Channel Enable set + [2:2] + read-write + + + CH1 + Channel Enable set + [1:1] + read-write + + + CH0 + Channel Enable set + [0:0] + read-write + + + + + CHNL_ENABLE_CLR + DMA channel enable clear + 0x2C + 0x00000000 + + + CH3 + Channel Enable clear + [3:3] + read-write + + + CH2 + Channel Enable clear + [2:2] + read-write + + + CH1 + Channel Enable clear + [1:1] + read-write + + + CH0 + Channel Enable clear + [0:0] + read-write + + + + + CHNL_PRI_ALT_SET + DMA channel primary alternate set + 0x30 + 0x00000000 + + + CH3 + Channel PRI_ALT set + [3:3] + read-write + + + CH2 + Channel PRI_ALT set + [2:2] + read-write + + + CH1 + Channel PRI_ALT set + [1:1] + read-write + + + CH0 + Channel PRI_ALT set + [0:0] + read-write + + + + + CHNL_PRI_ALT_CLR + DMA channel primary alternate clear + 0x34 + 0x00000000 + + + CH3 + Channel PRI_ALT clear + [3:3] + read-write + + + CH2 + Channel PRI_ALT clear + [2:2] + read-write + + + CH1 + Channel PRI_ALT clear + [1:1] + read-write + + + CH0 + Channel PRI_ALT clear + [0:0] + read-write + + + + + CHNL_PRIORITY_SET + DMA channel priority set + 0x38 + read-write + 0x00000000 + + + CH3 + Channel PRIORITY set + [3:3] + read-write + + + CH2 + Channel PRIORITY set + [2:2] + read-write + + + CH1 + Channel PRIORITY set + [1:1] + read-write + + + CH0 + Channel PRIORITY set + [0:0] + read-write + + + + + CHNL_PRIORITY_CLR + DMA channel priority clear + 0x3C + write-only + 0x00000000 + + + CH3 + Channel PRIORITY clear + [3:3] + write-only + + + CH2 + Channel PRIORITY clear + [2:2] + write-only + + + CH1 + Channel PRIORITY clear + [1:1] + write-only + + + CH0 + Channel PRIORITY clear + [0:0] + write-only + + + + + ERR_CLR + DMA bus error clear + 0x4C + 0x00000000 + + + ERR_CLR + Error Clear + [0:0] + read-write + + + + + INTEGRATION_CFG + DMA integration configuration + 0xE00 + 0x00000000 + + + INT_TEST_EN + Error Clear + [0:0] + read-write + + + + + STALL_STATUS + DMA stall status + 0xE08 + 0x00000000 + + + STALL_STATUS + DMA is stalled + [0:0] + read-only + + + + + DMA_REQ_STATUS + DMA Configuration + 0xE10 + 0x00000000 + + + CH3 + DMA Request Status for this CH + [3:3] + read-write + + + CH2 + DMA Request Status for this CH + [2:2] + read-write + + + CH1 + DMA Request Status for this CH + [1:1] + read-write + + + CH0 + DMA Request Status for this CH + [0:0] + read-write + + + + + DMA_SREQ_STATUS + DMA single request status + 0xE18 + 0x00000000 + + + CH3 + DMA SRequest Status for this CH + [3:3] + read-write + + + CH2 + DMA SRequest Status for this CH + [2:2] + read-write + + + CH1 + DMA SRequest Status for this CH + [1:1] + read-write + + + CH0 + DMA SRequest Status for this CH + [0:0] + read-write + + + + + DMA_DONE_SET + DMA done set + 0xE20 + 0x00000000 + + + CH3 + DMA Done Set for this CH + [3:3] + read-write + + + CH2 + DMA Done Set for this CH + [2:2] + read-write + + + CH1 + DMA Done Set for this CH + [1:1] + read-write + + + CH0 + DMA Done Set for this CH + [0:0] + read-write + + + + + DMA_DONE_CLR + DMA done clear + 0xE24 + 0x00000000 + + + CH3 + DMA Done clear for this CH + [3:3] + read-write + + + CH2 + DMA Done clear for this CH + [2:2] + read-write + + + CH1 + DMA Done clear for this CH + [1:1] + read-write + + + CH0 + DMA Done clear for this CH + [0:0] + read-write + + + + + DMA_ACTIVE_SET + DMA active set + 0xE28 + 0x00000000 + + + CH3 + DMA Active Set + [3:3] + read-write + + + CH2 + DMA Active Set + [2:2] + read-write + + + CH1 + DMA Active Set + [1:1] + read-write + + + CH0 + DMA Active Set + [0:0] + read-write + + + + + DMA_ACTIVE_CLR + DMA active clear + 0xE2C + 0x00000000 + + + CH3 + DMA Active clear + [3:3] + read-write + + + CH2 + DMA Active clear + [2:2] + read-write + + + CH1 + DMA Active clear + [1:1] + read-write + + + CH0 + DMA Active clear + [0:0] + read-write + + + + + ERR_SET + DMA bus error set + 0xE48 + 0x00000000 + + + ERR_SET + Set Error + [0:0] + read-only + + + + + PERIPH_ID_4 + DMA Peripheral ID 4 + 0xFD0 + 0x00000004 + + + BLOCK_COUNT + The Number of 4k Address Blocks Required + [7:4] + + + JEP106_C_CODE + JEP106 + [3:0] + + + + + PERIPH_ID_0 + DMA Peripheral ID 0 + 0xFE0 + 0x00000030 + + + PART_NUMBER_0 + Part Number + [7:0] + + + + + PERIPH_ID_1 + DMA Peripheral ID 1 + 0xFE4 + read-only + 0x000000B2 + + + JEP106_ID_3_0 + Indentity Code + [7:4] + + + PART_NUMBER_1 + Part Number 1 + [3:0] + + + + + PERIPH_ID_2 + DMA Peripheral ID 2 + 0xFE8 + 0x000000BC + + + REVISION + Revision + [7:4] + + + JEDEC_USED + JEDEC + [3:3] + + + JEP106_ID_6_4 + JEP106 + [2:0] + + + + + PERIPH_ID_3 + DMA Peripheral ID 3 + 0xFEC + 0x00000000 + + + MOD_NUMBER + Controller Modifications + [3:0] + + + + + PRIMECELL_ID_0 + DMA PrimeCell ID 0 + 0xFF0 + 0x0000000D + + + PRIMECELL_ID_0 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_1 + DMA PrimeCell ID 1 + 0xFF4 + 0x000000F0 + + + PRIMECELL_ID_1 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_2 + DMA PrimeCell ID 2 + 0xFF8 + 0x00000005 + + + PRIMECELL_ID_2 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_3 + DMA PrimeCell ID 3 + 0xFFC + 0x000000B1 + + + PRIMECELL_ID_3 + PrimeCell Identification + [7:0] + + + + + + + IOCONFIG + 1.0 + IO Pin Configuration Peripheral + 0x40011000 + + 0x0 + 0x1000 + registers + + + + 16 + 0x4 + PORTA[%s] + PORTA Pin Configuration Register + 0x0 + 0x00000000 + + + FLTTYPE + Input Filter Selectoin + [2:0] + + + SYNC + Synchronize to system clock + 0 + + + DIRECT + Direct input, no synchronization + 1 + + + FILTER1 + Require 2 samples to have the same value + 2 + + + FILTER2 + Require 3 samples to have the same value + 3 + + + FILTER3 + Require 4 samples to have the same value + 4 + + + FILTER4 + Require 5 samples to have the same value + 5 + + + + + FLTCLK + Input Filter Clock Selection + [5:3] + + + INVINP + Input Invert Selection + [6:6] + + + IEWO + Input Enable While Output enabled + [7:7] + + + OPENDRN + Output Open Drain Mode + [8:8] + + + INVOUT + Output Invert Selection + [9:9] + + + PLEVEL + Internal Pull up/down level + [10:10] + + + PEN + Enable Internal Pull up/down + [11:11] + + + PWOA + Enable Pull when output active + [12:12] + + + FUNSEL + Pin Function Selection + [15:13] + + + IODIS + IO Pin Disable + [16:16] + + + + + PORTB[%s] + PORTB Pin Configuration Register + 0x40 + 0x00000000 + + + PORTC[%s] + PORTC Pin Configuration Register + 0x80 + 0x00000000 + + + PORTD[%s] + PORTD Pin Configuration Register + 0xC0 + 0x00000000 + + + PORTE[%s] + PORTE Pin Configuration Register + 0x100 + 0x00000000 + + + PORTF[%s] + PORTF Pin Configuration Register + 0x140 + 0x00000000 + + + 8 + 0x4 + PORTG[%s] + PORTG Pin Configuration Register + 0x180 + 0x00000000 + + + CLKDIV0 + Clock divide value. 0 will disable the clock + 0x1C0 + read-only + 0x00000000 + + + CLKDIV1 + Clock divide value. 0 will disable the clock + 0x1C4 + read-write + 0x00000000 + + + CLKDIV2 + Clock divide value. 0 will disable the clock + 0x1C8 + read-write + 0x00000000 + + + CLKDIV3 + Clock divide value. 0 will disable the clock + 0x1CC + read-write + 0x00000000 + + + CLKDIV4 + Clock divide value. 0 will disable the clock + 0x1D0 + read-write + 0x00000000 + + + CLKDIV5 + Clock divide value. 0 will disable the clock + 0x1D4 + read-write + 0x00000000 + + + CLKDIV6 + Clock divide value. 0 will disable the clock + 0x1D8 + read-write + 0x00000000 + + + CLKDIV7 + Clock divide value. 0 will disable the clock + 0x1DC + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028207E9 + + + + + UTILITY + 1.0 + Utility Peripheral + 0x40020000 + + 0x0 + 0x1000 + registers + + + + SYND_DATA + Data Register + 0x0 + read-write + 0x00000000 + + + SYND_SYND + Syndrome Data Register + 0x4 + read-write + 0x00000000 + + + SYND_SYND + Provides bits 11:0 for syndrome, 2x6-bit + [11:0] + + + + + SYND_ENC_32_44 + EDAC Encode + 0x8 + read-write + 0x00000000 + + + SYND_ENC_31_16 + Computed syndrome value for bits 31-16 + [11:6] + + + SYND_ENC_7_0 + Computed syndrome value for bits 15-0 + [5:0] + + + + + SYND_CHECK_32_44_DATA + EDAC Decode Data + 0xC + read-only + 0x00000000 + + + SYND_CHECK_32_44_SYND + EDAC Decode Syndrome + 0x10 + read-only + 0x00000000 + + + MBE + Multiple bit error detect status + [15:14] + + + SBE + Single bit error detect status + [13:12] + + + SYND_CHECK_32_44_SYND + Correct syndrome value + [11:0] + + + + + ROM_TRAP_ADDRESS + ROM EDAC Trap Address + 0x14 + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + ROM_TRAP_SYND + ROM EDAC Trap Syndrome + 0x18 + read-write + 0x00000000 + + + R0M_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + ROM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + RAM_TRAP_ADDR0 + RAM0 EDAC Trap Address + 0x1C + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + RAM_TRAP_SYND0 + RAM0 EDAC Trap Syndrome + 0x20 + read-write + 0x00000000 + + + RAM_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + RAM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + RAM_TRAP_ADDR1 + RAM1 EDAC Trap Address + 0x24 + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + RAM_TRAP_SYND1 + RAM1 EDAC Trap Syndrome + 0x28 + read-write + 0x00000000 + + + RAM_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + RAM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + SYND_ENC_32_52 + EDAC Encode + 0x120 + read-only + 0x00000000 + + + SYND_ENC_32_52 + Computed syndrome value for bits 15-0 + [19:0] + + + + + SYND_CHECK_32_52_DATA + EDAC Decode Data + 0x124 + read-only + 0x00000000 + + + SYND_CHECK_32_52_SYND + EDAC Decode Syndrome + 0x128 + read-only + 0x00000000 + + + MBE + Multiple bit error detect status + [31:28] + + + SBE + Single bit error detect status + [27:24] + + + SYND_CHECK_32_52_SYND + Corrected syndrome value + [19:0] + + + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028407E9 + + + + + PORTA + 1.0 + GPIO Peripheral + GPIO + GPIO + 0x40012000 + + 0x0 + 0x400 + registers + + + PORTA0 + 78 + + + PORTA1 + 79 + + + PORTA2 + 80 + + + PORTA3 + 81 + + + PORTA4 + 82 + + + PORTA5 + 83 + + + PORTA6 + 84 + + + PORTA7 + 85 + + + PORTA8 + 86 + + + PORTA9 + 87 + + + PORTA10 + 88 + + + PORTA11 + 89 + + + PORTA12 + 90 + + + PORTA13 + 91 + + + PORTA14 + 92 + + + PORTA15 + 93 + + + PORTB0 + 94 + + + PORTB1 + 95 + + + PORTB2 + 96 + + + PORTB3 + 97 + + + PORTB4 + 98 + + + PORTB5 + 99 + + + PORTB6 + 100 + + + PORTB7 + 101 + + + PORTB8 + 102 + + + PORTB9 + 103 + + + PORTB10 + 104 + + + PORTB11 + 105 + + + PORTB12 + 106 + + + PORTB13 + 107 + + + PORTB14 + 108 + + + PORTB15 + 109 + + + PORTC0 + 110 + + + PORTC1 + 111 + + + PORTC2 + 112 + + + PORTC3 + 113 + + + PORTC4 + 114 + + + PORTC5 + 115 + + + PORTC6 + 116 + + + PORTC7 + 117 + + + PORTC8 + 118 + + + PORTC9 + 119 + + + PORTC10 + 120 + + + PORTC11 + 121 + + + PORTC12 + 122 + + + PORTC13 + 123 + + + PORTC14 + 124 + + + PORTC15 + 125 + + + PORTD0 + 126 + + + PORTD1 + 127 + + + PORTD2 + 128 + + + PORTD3 + 129 + + + PORTD4 + 130 + + + PORTD5 + 131 + + + PORTD6 + 132 + + + PORTD7 + 133 + + + PORTD8 + 134 + + + PORTD9 + 135 + + + PORTD10 + 136 + + + PORTD11 + 137 + + + PORTD12 + 138 + + + PORTD13 + 139 + + + PORTD14 + 140 + + + PORTD15 + 141 + + + PORTE0 + 142 + + + PORTE1 + 143 + + + PORTE2 + 144 + + + PORTE3 + 145 + + + PORTE4 + 146 + + + PORTE5 + 147 + + + PORTE6 + 148 + + + PORTE7 + 149 + + + PORTE8 + 150 + + + PORTE9 + 151 + + + PORTE10 + 152 + + + PORTE11 + 153 + + + PORTE12 + 154 + + + PORTE13 + 155 + + + PORTE14 + 156 + + + PORTE15 + 157 + + + PORTF0 + 158 + + + PORTF1 + 159 + + + PORTF2 + 160 + + + PORTF3 + 161 + + + PORTF4 + 162 + + + PORTF5 + 163 + + + PORTF6 + 164 + + + PORTF7 + 165 + + + PORTF8 + 166 + + + PORTF9 + 167 + + + PORTF10 + 168 + + + PORTF11 + 169 + + + PORTF12 + 170 + + + PORTF13 + 171 + + + PORTF14 + 172 + + + PORTF15 + 173 + + + + DATAIN + Data In Register + 0x0 + read-only + 0x00000000 + + + 4 + 0x1 + DATAINBYTE[%s] + Data In Register by Byte + DATAIN + 0x0 + 0x8 + read-only + 0x00000000 + + + DATAINRAW + Data In Raw Register + 0x4 + 0x00000000 + + + DATAINRAWBYTE[%s] + Data In Raw Register by Byte + DATAINRAW + 0x4 + 0x00000000 + + + DATAOUT + Data Out Register + 0x8 + write-only + 0x00000000 + + + 4 + 0x1 + DATAOUTBYTE[%s] + Data Out Register by Byte + DATAOUT + 0x8 + 0x8 + write-only + 0x00000000 + + + DATAOUTRAW + Data Out Register + 0xC + 0x00000000 + + + DATAOUTRAWBYTE[%s] + Data Out Register by Byte + DATAOUTRAW + 0xC + 0x00000000 + + + SETOUT + Set Out Register + 0x10 + 0x00000000 + + + SETOUTBYTE[%s] + Set Out Register by Byte + SETOUT + 0x10 + 0x00000000 + + + CLROUT + Clear Out Register + 0x14 + 0x00000000 + + + CLROUTBYTE[%s] + Clear Out Register by Byte + CLROUT + 0x14 + 0x00000000 + + + TOGOUT + Toggle Out Register + 0x18 + 0x00000000 + + + TOGOUTBYTE[%s] + Toggle Out Register by Byte + TOGOUT + 0x18 + 0x00000000 + + + DATAMASK + Data mask Register + 0x1C + 0x00000000 + + + 4 + 0x1 + DATAMASKBYTE[%s] + Data Out Register by Byte + DATAMASK + 0x1C + 0x8 + 0x00000000 + + + DIR + Direction Register (1:Output, 0:Input) + 0x20 + 0x00000000 + + + DIRBYTE[%s] + Direction Register by Byte + DIR + 0x20 + 0x00000000 + + + PULSE + Pulse Mode Register + 0x24 + 0x00000000 + + + PULSEBYTE[%s] + Pulse Mode Register by Byte + PULSE + 0x24 + 0x00000000 + + + PULSEBASE + Pulse Base Value Register + 0x28 + 0x00000000 + + + PULSEBASEBYTE[%s] + Pulse Base Mode Register by Byte + PULSEBASE + 0x28 + 0x00000000 + + + DELAY1 + Delay1 Register + 0x2C + 0x00000000 + + + DELAY1BYTE[%s] + Delay1 Register by Byte + DELAY1 + 0x2C + 0x00000000 + + + DELAY2 + Delay2 Register + 0x30 + 0x20 + read-write + 0x00000000 + + + DELAY2BYTE[%s] + Delay2 Register by Byte + DELAY2 + 0x30 + 0x00000000 + + + IRQ_SEN + Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive) + 0x34 + 0x00000000 + + + IRQ_EDGE + Interrupt Both Edge Register (1:Both Edges, 0:Single Edge) + 0x38 + 0x00000000 + + + IRQ_EVT + Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) + 0x3C + 0x00000000 + + + IRQ_ENB + Interrupt Enable Register + 0x40 + 0x00000000 + + + IRQ_RAW + Raw Interrupt Status + 0x44 + read-only + 0x00000000 + + + IRQ_END + Masked Interrupt Status + 0x48 + read-only + 0x00000000 + + + EDGE_STATUS + Edge Status Register + 0x4C + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0x3FC + 0x20 + read-only + 0x021007E9 + + + + + PORTB + 0x40012400 + + + PORTC + 0x40012800 + + + PORTD + 0x40012C00 + + + PORTE + 0x40013000 + + + PORTF + 0x40013400 + + + PORTG + 0x40013800 + + + TIM0 + 1.0 + Timer/Counter Peripheral + Timer_Counter + TIM + 0x40018000 + + 0x0 + 0x400 + registers + + + TIM0 + 48 + + + TIM1 + 49 + + + TIM2 + 50 + + + TIM3 + 51 + + + TIM4 + 52 + + + TIM5 + 53 + + + TIM6 + 54 + + + TIM7 + 55 + + + TIM8 + 56 + + + TIM9 + 57 + + + TIM10 + 58 + + + TIM11 + 59 + + + TIM12 + 60 + + + TIM13 + 61 + + + TIM14 + 62 + + + TIM15 + 63 + + + TIM16 + 64 + + + TIM17 + 65 + + + TIM18 + 66 + + + TIM19 + 67 + + + TIM20 + 68 + + + TIM21 + 69 + + + TIM22 + 70 + + + TIM23 + 71 + + + + CTRL + Control Register + 0x0 + read-write + + + ENABLE + Counter Enable + [0:0] + + + ACTIVE + Counter Active + [1:1] + read-only + + + AUTO_DISABLE + Auto Disables the counter (set ENABLE to 0) when the count reaches 0 + [2:2] + + + AUTO_DEACTIVATE + Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0 + [3:3] + + + IRQ_ENB + Interrupt Enable + [4:4] + + + STATUS_SEL + Counter Status Selection + [7:5] + + + DONE + Single cycle pulse when the counter reaches 0 + 0 + + + ACTIVE + Returns the counter ACTIVE bit + 1 + + + TOGGLE + Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output. + 2 + + + PWMA + Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE + 3 + + + PWMB + Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE + 4 + + + ENABLED + Returns the counter ENABLED bit + 5 + + + PWMA_ACTIVE + Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0 + 6 + + + + + STATUS_INV + Invert the Output Status + [8:8] + + + REQ_STOP + Stop Request + [9:9] + + + + + RST_VALUE + The value that counter start from after reaching 0. + 0x4 + + + CNT_VALUE + The current value of the counter + 0x8 + + + ENABLE + Alternate access to the Counter ENABLE bit in the CTRL Register + 0xC + + + ENABLE + Counter Enable + [0:0] + + + + + CSD_CTRL + The Cascade Control Register. Controls the counter external enable signals + 0x10 + + + CSDEN0 + Cascade 0 Enable + [0:0] + + + CSDINV0 + Cascade 0 Invert + [1:1] + + + CSDEN1 + Cascade 1 Enable + [2:2] + + + CSDINV1 + Cascade 1 Invert + [3:3] + + + DCASOP + Dual Cascade Operation (0:AND, 1:OR) + [4:4] + + + CSDTRG0 + Cascade 0 Enabled as Trigger + [6:6] + + + CSDTRG1 + Cascade 1 Enabled as Trigger + [7:7] + + + CSDEN2 + Cascade 2 Enable + [8:8] + + + CSDINV2 + Cascade 2 Invert + [9:9] + + + CSDTRG2 + Cascade 2 Trigger mode + [10:10] + + + + + CASCADE0 + Cascade Enable Selection + 0x14 + + + CASSEL + Cascade Selection + [7:0] + + + + + CASCADE1 + Cascade Enable Selection + 0x18 + + + CASCADE2 + Cascade Enable Selection + 0x1C + + + PWM_VALUE + The Pulse Width Modulation Value + 0x20 + + + PWMA_VALUE + The Pulse Width Modulation ValueA + PWM_VALUE + 0x20 + + + PWMB_VALUE + The Pulse Width Modulation ValueB + 0x24 + + + PERID + Peripheral ID Register + 0x3FC + read-only + 0x021107E9 + + + + + TIM1 + 0x40018400 + + + TIM2 + 0x40018800 + + + TIM3 + 0x40018C00 + + + TIM4 + 0x40019000 + + + TIM5 + 0x40019400 + + + TIM6 + 0x40019800 + + + TIM7 + 0x40019C00 + + + TIM8 + 0x4001A000 + + + TIM9 + 0x4001A400 + + + TIM10 + 0x4001A800 + + + TIM11 + 0x4001AC00 + + + TIM12 + 0x4001B000 + + + TIM13 + 0x4001B400 + + + TIM14 + 0x4001B800 + + + TIM15 + 0x4001BC00 + + + TIM16 + 0x40028000 + + + TIM17 + 0x40028400 + + + TIM18 + 0x40028800 + + + TIM19 + 0x40028C00 + + + TIM20 + 0x40029000 + + + TIM21 + 0x40029400 + + + TIM22 + 0x40029800 + + + TIM23 + 0x40029C00 + + + UART0 + 1.0 + UART Peripheral + UART + UART + 0x40024000 + + 0x0 + 0x1000 + registers + + + UART0_TX + 24 + + + UART0_RX + 25 + + + UART1_TX + 26 + + + UART1_RX + 27 + + + UART2_TX + 28 + + + UART2_RX + 29 + + + + DATA + Data In/Out Register + 0x0 + 0x00000000 + + + ENABLE + Enable Register + 0x4 + 0x00000000 + + + RXENABLE + Rx Enable + [0:0] + + + TXENABLE + Tx Enable + [1:1] + + + + + CTRL + Control Register + 0x8 + 0x00000000 + + + PAREN + Parity Enable + [0:0] + + + PAREVEN + Parity Even/Odd(1/0) + [1:1] + + + PARSTK + Parity Sticky + [2:2] + + + STOPBITS + Stop Bits 1/2(0/1) + [3:3] + + + WORDSIZE + Word Size in Bits 5/6/7/8(00/01/10/11) + [5:4] + + + LOOPBACK + Loopback Enable + [6:6] + + + LOOPBACKBLK + Loopback Block + [7:7] + + + AUTOCTS + Enable Auto CTS mode + [8:8] + + + DEFRTS + Default RTSn value + [9:9] + + + AUTORTS + Enable Auto RTS mode + [10:10] + + + BAUD8 + Enable BAUD8 mode + [11:11] + + + + + CLKSCALE + Clock Scale Register + 0xC + 0x00000000 + + + FRAC + Fractional Divide (64ths) + [5:0] + + + INT + Integer Divide + [23:6] + + + RESET + Reset Baud Counter + [31:31] + write-only + + + + + RXSTATUS + Status Register + 0x10 + read-only + 0x00000000 + + + RDAVL + Read Data Available + [0:0] + + + RDNFULL + Read Fifo NOT Full + [1:1] + + + RXBUSY + RX Busy Receiving + [2:2] + + + RXTO + RX Receive Timeout + [3:3] + + + RXOVR + Read Fifo Overflow + [4:4] + + + RXFRM + RX Framing Error + [5:5] + + + RXPAR + RX Parity Error + [6:6] + + + RXBRK + RX Break Error + [7:7] + + + RXBUSYBRK + RX Busy Receiving Break + [8:8] + + + RXADDR9 + Address Match for 9 bit mode + [9:9] + + + RXRTSN + RX RTSn Output Value + [15:15] + + + + + TXSTATUS + Status Register + 0x14 + read-only + 0x00000000 + + + WRRDY + Write Fifo NOT Full + [0:0] + + + WRBUSY + Write Fifo Full + [1:1] + + + TXBUSY + TX Busy Transmitting + [2:2] + + + WRLOST + Write Data Lost (Fifo Overflow) + [3:3] + + + TXCTSN + TX CTSn Input Value + [15:15] + + + + + FIFO_CLR + Clear FIFO Register + 0x18 + write-only + 0x00000000 + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TXBREAK + Break Transmit Register + 0x1C + write-only + 0x00000000 + + + ADDR9 + Address9 Register + 0x20 + read-write + 0x00000000 + + + ADDR9MASK + Address9 Mask Register + 0x24 + read-write + 0x00000000 + + + IRQ_ENB + IRQ Enable Register + 0x28 + read-write + 0x00000000 + + + IRQ_RX + RX Interrupt + [0:0] + + + IRQ_RX_STATUS + RX Status Interrupt + [1:1] + + + IRQ_RX_TO + RX Timeout Interrupt + [2:2] + + + IRQ_TX + TX Interrupt + [4:4] + + + IRQ_TX_STATUS + TX Status Interrupt + [5:5] + + + IRQ_TX_EMPTY + TX Empty Interrupt + [6:6] + + + IRQ_TX_CTS + TX CTS Change Interrupt + [7:7] + + + + + IRQ_RAW + IRQ Raw Status Register + 0x2C + read-only + 0x00000000 + + + IRQ_END + IRQ Enabled Status Register + 0x30 + read-only + 0x00000000 + + + IRQ_CLR + IRQ Clear Status Register + 0x34 + write-only + 0x00000000 + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x38 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x3C + + + RXFIFORTSTRG + Rx FIFO RTS Trigger Level + 0x40 + + + STATE + Internal STATE of UART Controller + 0x44 + 0x20 + read-only + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x021207E9 + + + + + UART1 + 0x40025000 + + + UART2 + 0x40017000 + + + SPI0 + 1.0 + SPI Peripheral + SPI + SPI + 0x40015000 + + 0x0 + 0x400 + registers + + + SPI0_TX + 16 + + + SPI0_RX + 17 + + + SPI1_TX + 18 + + + SPI1_RX + 19 + + + SPI2_TX + 20 + + + SPI2_RX + 21 + + + SPI3_TX + 22 + + + SPI3_RX + 23 + + + + CTRL0 + Control Register 0 + 0x0 + 0x00000000 + + + SIZE + Data Size(0x3=>4, 0xf=>16) + [3:0] + + + SPO + SPI Clock Polarity + [6:6] + + + SPH + SPI Clock Phase + [7:7] + + + SCRDV + Serial Clock Rate divide+1 value + [15:8] + + + + + CTRL1 + Control Register 1 + 0x4 + 0x00000000 + + + LBM + Loop Back + [0:0] + + + ENABLE + Enable + [1:1] + + + MS + Master/Slave (0:Master, 1:Slave) + [2:2] + + + SOD + Slave output Disable + [3:3] + + + SS + Slave Select + [6:4] + + + BLOCKMODE + Block Mode Enable + [7:7] + + + BMSTART + Block Mode Start Status Enable + [8:8] + + + BMSTALL + Block Mode Stall Enable + [9:9] + + + MDLYCAP + Master Delayed Capture Enable + [10:10] + + + MTXPAUSE + Master Tx Pause Enable + [11:11] + + + + + DATA + Data Input/Output + 0x8 + + + STATUS + Status Register + 0xC + read-only + 0x00000000 + + + TFE + Transmit FIFO empty + [0:0] + + + TNF + Transmit FIFO not full + [1:1] + + + RNE + Receive FIFO not empty + [2:2] + + + RFF + Receive FIFO Full + [3:3] + + + BUSY + Busy + [4:4] + + + RXDATAFIRST + Pending Data is first Byte in BLOCKMODE + [5:5] + + + RXTRIGGER + RX FIFO Above Trigger Level + [6:6] + + + TXTRIGGER + TX FIFO Below Trigger Level + [7:7] + + + + + CLKPRESCALE + Clock Pre Scale divide value + 0x10 + + + IRQ_ENB + Interrupt Enable Register + 0x14 + read-write + 0x00000000 + + + RORIM + RX Overrun + [0:0] + + + RTIM + RX Timeout + [1:1] + + + RXIM + RX Fifo is at least half full + [2:2] + + + TXIM + TX Fifo is at least half empty + [3:3] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x18 + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x1C + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x20 + write-only + oneToClear + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x24 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x28 + + + FIFO_CLR + Clear FIFO Register + 0x2C + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + STATE + Internal STATE of SPI Controller + 0x30 + read-only + + + PERID + Peripheral ID Register + 0x3FC + read-only + 0x021307E9 + + + + + SPI1 + 0x40015400 + + + SPI2 + 0x40015800 + + + SPI3 + 0x40015C00 + + + I2C0 + 1.0 + I2C Peripheral + I2C + I2C + 0x40016000 + + 0x0 + 0x400 + registers + + + I2C0_MS + 30 + + + I2C0_SL + 31 + + + I2C1_MS + 32 + + + I2C1_SL + 33 + + + I2C2_MS + 34 + + + I2C2_SL + 35 + + + I2C0_MS_RX + 182 + + + I2C0_MS_TX + 183 + + + I2C0_SL_RX + 184 + + + I2C0_SL_TX + 185 + + + I2C1_MS_RX + 186 + + + I2C1_MS_TX + 187 + + + I2C1_SL_RX + 188 + + + I2C1_SL_TX + 189 + + + I2C2_MS_RX + 190 + + + I2C2_MS_TX + 191 + + + I2C2_SL_RX + 192 + + + I2C2_SL_TX + 193 + + + + CTRL + Control Register + 0x0 + 0x00000000 + + + CLKENABLED + I2C CLK Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + ALGFILTER + Enable Input Analog Glitch Filter + [5:5] + + + DLGFILTER + Enable Input Digital Glitch Filter + [6:6] + + + LOOPBACK + Enable LoopBack Mode + [8:8] + + + TMCONFIGENB + Enable Timing Config Register + [9:9] + + + + + CLKSCALE + Clock Scale divide value + 0x4 + + + VALUE + Enable FastMode + [30:0] + + + FASTMODE + Enable FastMode + [31:31] + + + + + WORDS + Word Count value + 0x8 + + + ADDRESS + I2C Address value + 0xC + + + DATA + Data Input/Output + 0x10 + + + CMD + Command Register + 0x14 + + + STATUS + I2C Controller Status Register + 0x18 + + + I2CIDLE + I2C bus is idle + [0:0] + + + IDLE + I2C controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + STATE + Internal STATE of I2C Master Controller + 0x1C + read-only + + + TXCOUNT + TX Count Register + 0x20 + read-only + + + RXCOUNT + RX Count Register + 0x24 + read-only + + + IRQ_ENB + Interrupt Enable Register + 0x28 + read-write + 0x00000000 + + + I2CIDLE + I2C Bus is Idle + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + CLKLOTO + I2C Clock Low Timeout + [7:7] + + + TXOVERFLOW + TX FIFO Overflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x2C + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x30 + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x34 + write-only + oneToClear + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x38 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x3C + + + FIFO_CLR + Clear FIFO Register + 0x40 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TMCONFIG + Timing Config Register + 0x44 + + + CLKTOLIMIT + Clock Low Timeout Limit Register + 0x48 + + + S0_CTRL + Slave Control Register + 0x100 + 0x00000000 + + + CLKENABLED + I2C Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + + + S0_MAXWORDS + Slave MaxWords Register + 0x104 + 0x00000000 + + + MAXWORD + Max Word Count + [10:0] + + + ENABLE + Enables the max word count + [31:31] + + + + + S0_ADDRESS + Slave I2C Address Value + 0x108 + 0x00000000 + + + A10MODE + Enable 10b address mode + [15:15] + + + ADDRESS + Address value + [10:1] + + + RW + Read/Write value + [0:0] + + + + + S0_ADDRESSMASK + Slave I2C Address Mask value + 0x10C + 0x00000000 + + + MASK + Address mask value + [10:1] + + + RWMASK + Read/Write mask + [0:0] + + + + + S0_DATA + Slave Data Input/Output + 0x110 + 0x00000000 + + + VALUE + I2C data value + [7:0] + + + + + S0_LASTADDRESS + Slave I2C Last Address value + 0x114 + read-only + 0x00000000 + + + ADDRESS + Address value + [10:1] + + + DIRECTION + Transaction direction 0=master send, 1=master receive + [0:0] + + + + + S0_STATUS + Slave I2C Controller Status Register + 0x118 + read-only + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_BUSY + I2C Raw Busy value + [29:29] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + S0_STATE + Internal STATE of I2C Slave Controller + 0x11C + read-only + + + S0_TXCOUNT + Slave TX Count Register + 0x120 + read-only + 0x00000000 + + + VALUE + Count value + [10:0] + + + + + S0_RXCOUNT + Slave RX Count Register + 0x124 + read-only + 0x00000000 + + + VALUE + Count value + [10:0] + + + + + S0_IRQ_ENB + Slave Interrupt Enable Register + 0x128 + read-write + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + I2C_START + I2C Start Condition + [8:8] + + + I2C_STOP + I2C Stop Condition + [9:9] + + + TXUNDERFLOW + TX FIFO Underflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + S0_IRQ_RAW + Slave Raw Interrupt Status Register + 0x12C + read-only + + + S0_IRQ_END + Slave Enabled Interrupt Status Register + 0x130 + read-only + + + S0_IRQ_CLR + Slave Clear Interrupt Status Register + 0x134 + write-only + oneToClear + + + S0_RXFIFOIRQTRG + Slave Rx FIFO IRQ Trigger Level + 0x138 + 0x00000000 + + + LEVEL + Half full level for the Rx FIFO + [4:0] + + + + + S0_TXFIFOIRQTRG + Slave Tx FIFO IRQ Trigger Level + 0x13C + 0x00000008 + + + LEVEL + Half full level for the Rx FIFO + [4:0] + + + + + S0_FIFO_CLR + Slave Clear FIFO Register + 0x140 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + S0_ADDRESSB + Slave I2C Address B Value + 0x144 + 0x00000000 + + + RW + Read write value + [0:0] + + + ADDRESS + Address value + [10:1] + + + ADDRESSBEN + Enable Address B + [15:15] + + + + + S0_ADDRESSMASKB + Slave I2C Address B Mask value + 0x148 + 0x000007FE + + + RWMASK + Read write mask + [0:0] + + + MASK + Address mask value + [10:1] + + + + + PERID + Peripheral ID Register + 0x3FC + read-only + 0x021407E9 + + + + + I2C1 + 0x40016400 + + + I2C2 + 0x40016800 + + + CAN0 + 1.0 + CAN Peripheral + CAN + CAN + 0x40014000 + + 0x0 + 0x400 + registers + + + CAN0 + 72 + + + CAN1 + 74 + + + + CNSTAT_CMB0 + Buffer Status / Control Register + 0x0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB0 + CAN Frame Timestamp + 0x4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB0 + CAN Frame Data Word 3 + 0x8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB0 + CAN Frame Data Word 2 + 0xC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB0 + CAN Frame Data Word 1 + 0x10 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB0 + CAN Frame Data Word 0 + 0x14 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB0 + CAN Frame Identifier Word 0 + 0x18 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB0 + CAN Frame Identifier Word 1 + 0x1C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB1 + Buffer Status / Control Register + 0x20 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB1 + CAN Frame Timestamp + 0x24 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB1 + CAN Frame Data Word 3 + 0x28 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB1 + CAN Frame Data Word 2 + 0x2C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB1 + CAN Frame Data Word 2 + 0x30 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB1 + CAN Frame Data Word 0 + 0x34 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB1 + CAN Frame Identifier Word 0 + 0x38 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB1 + CAN Frame Identifier Word 1 + 0x3C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB2 + Buffer Status / Control Register + 0x40 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB2 + CAN Frame Timestamp + 0x44 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB2 + CAN Frame Data Word 3 + 0x48 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB2 + CAN Frame Data Word 2 + 0x4C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB2 + CAN Frame Data Word 2 + 0x50 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB2 + CAN Frame Data Word 0 + 0x54 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB2 + CAN Frame Identifier Word 0 + 0x58 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB2 + CAN Frame Identifier Word 1 + 0x5C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB3 + Buffer Status / Control Register + 0x60 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB3 + CAN Frame Timestamp + 0x64 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB3 + CAN Frame Data Word 3 + 0x68 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB3 + CAN Frame Data Word 2 + 0x6C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB3 + CAN Frame Data Word 2 + 0x70 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB3 + CAN Frame Data Word 0 + 0x74 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB3 + CAN Frame Identifier Word 0 + 0x78 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB3 + CAN Frame Identifier Word 1 + 0x7C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB4 + Buffer Status / Control Register + 0x80 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB4 + CAN Frame Timestamp + 0x84 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB4 + CAN Frame Data Word 3 + 0x88 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB4 + CAN Frame Data Word 2 + 0x8C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB4 + CAN Frame Data Word 2 + 0x90 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB4 + CAN Frame Data Word 0 + 0x94 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB4 + CAN Frame Identifier Word 0 + 0x98 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB4 + CAN Frame Identifier Word 1 + 0x9C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB5 + Buffer Status / Control Register + 0xA0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB5 + CAN Frame Timestamp + 0xA4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB5 + CAN Frame Data Word 3 + 0xA8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB5 + CAN Frame Data Word 2 + 0xAC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB5 + CAN Frame Data Word 2 + 0xB0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB5 + CAN Frame Data Word 0 + 0xB4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB5 + CAN Frame Identifier Word 0 + 0xB8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB5 + CAN Frame Identifier Word 1 + 0xBC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB6 + Buffer Status / Control Register + 0xC0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB6 + CAN Frame Timestamp + 0xC4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB6 + CAN Frame Data Word 3 + 0xC8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB6 + CAN Frame Data Word 2 + 0xCC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB6 + CAN Frame Data Word 2 + 0xD0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB6 + CAN Frame Data Word 0 + 0xD4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB6 + CAN Frame Identifier Word 0 + 0xD8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB6 + CAN Frame Identifier Word 1 + 0xDC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB7 + Buffer Status / Control Register + 0xE0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB7 + CAN Frame Timestamp + 0xE4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB7 + CAN Frame Data Word 3 + 0xE8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB7 + CAN Frame Data Word 2 + 0xEC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB7 + CAN Frame Data Word 2 + 0xF0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB7 + CAN Frame Data Word 0 + 0xF4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB7 + CAN Frame Identifier Word 0 + 0xF8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB7 + CAN Frame Identifier Word 1 + 0xFC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB8 + Buffer Status / Control Register + 0x100 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB8 + CAN Frame Timestamp + 0x104 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB8 + CAN Frame Data Word 3 + 0x108 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB8 + CAN Frame Data Word 2 + 0x10C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB8 + CAN Frame Data Word 2 + 0x110 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB8 + CAN Frame Data Word 0 + 0x114 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB8 + CAN Frame Identifier Word 0 + 0x118 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB8 + CAN Frame Identifier Word 1 + 0x11C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB9 + Buffer Status / Control Register + 0x120 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB9 + CAN Frame Timestamp + 0x124 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB9 + CAN Frame Data Word 3 + 0x128 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB9 + CAN Frame Data Word 2 + 0x12C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB9 + CAN Frame Data Word 2 + 0x130 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB9 + CAN Frame Data Word 0 + 0x134 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB9 + CAN Frame Identifier Word 0 + 0x138 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB9 + CAN Frame Identifier Word 1 + 0x13C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB10 + Buffer Status / Control Register + 0x140 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB10 + CAN Frame Timestamp + 0x144 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB10 + CAN Frame Data Word 3 + 0x148 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB10 + CAN Frame Data Word 2 + 0x14C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB10 + CAN Frame Data Word 2 + 0x150 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB10 + CAN Frame Data Word 0 + 0x154 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB10 + CAN Frame Identifier Word 0 + 0x158 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB10 + CAN Frame Identifier Word 1 + 0x15C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB11 + Buffer Status / Control Register + 0x160 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB11 + CAN Frame Timestamp + 0x164 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB11 + CAN Frame Data Word 3 + 0x168 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB11 + CAN Frame Data Word 2 + 0x16C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB11 + CAN Frame Data Word 2 + 0x170 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB11 + CAN Frame Data Word 0 + 0x174 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB11 + CAN Frame Identifier Word 0 + 0x178 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB11 + CAN Frame Identifier Word 1 + 0x17C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB12 + Buffer Status / Control Register + 0x180 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB12 + CAN Frame Timestamp + 0x184 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB12 + CAN Frame Data Word 3 + 0x188 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB12 + CAN Frame Data Word 2 + 0x18C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB12 + CAN Frame Data Word 2 + 0x190 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB12 + CAN Frame Data Word 0 + 0x194 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB12 + CAN Frame Identifier Word 0 + 0x198 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB12 + CAN Frame Identifier Word 1 + 0x19C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB13 + Buffer Status / Control Register + 0x1A0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB13 + CAN Frame Timestamp + 0x1A4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB13 + CAN Frame Data Word 3 + 0x1A8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB13 + CAN Frame Data Word 2 + 0x1AC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB13 + CAN Frame Data Word 2 + 0x1B0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB13 + CAN Frame Data Word 0 + 0x1B4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB13 + CAN Frame Identifier Word 0 + 0x1B8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB13 + CAN Frame Identifier Word 1 + 0x1BC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB14 + Buffer Status / Control Register + 0x1C0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB14 + CAN Frame Timestamp + 0x1C4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB14 + CAN Frame Data Word 3 + 0x1C8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB14 + CAN Frame Data Word 2 + 0x1CC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB14 + CAN Frame Data Word 2 + 0x1D0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB14 + CAN Frame Data Word 0 + 0x1D4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB14 + CAN Frame Identifier Word 0 + 0x1D8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB14 + CAN Frame Identifier Word 1 + 0x1DC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_HCMB + Buffer Status / Control Register + 0x1E0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_HCMB + CAN Frame Timestamp + 0x1E4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_HCMB + CAN Frame Data Word 3 + 0x1E8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_HCMB + CAN Frame Data Word 2 + 0x1EC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_HCMB + CAN Frame Data Word 2 + 0x1F0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_HCMB + CAN Frame Data Word 0 + 0x1F4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_HCMB + CAN Frame Identifier Word 0 + 0x1F8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_HCMB + CAN Frame Identifier Word 1 + 0x1FC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CGCR + CAN Global Configuration Register + 0x200 + 0x00000000 + + + EIT + Error Interrupt Type + [11:11] + + + DIAGEN + Diagnostic Enable + [10:10] + + + INTERNAL + Internal + [9:9] + + + LOOPBACK + Loopback + [8:8] + + + IGNACK + Ignore Acknowledge + [7:7] + + + LO + Listen Only + [6:6] + + + DDIR + Data Direction + [5:5] + + + TSTPEN + Time Sync Enable + [4:4] + + + BUFFLOCK + Buffer Lock + [3:3] + + + CTX + RW,Control Transmit + [2:2] + + + CRX + RW,Control Receive + [1:1] + + + CANEN + CAN Enable + [0:0] + + + + + CTIM + CAN Timing Register + 0x204 + 0x00000000 + + + PSC + Prescaler Configuration + [15:9] + + + SJW + Synchronization Jump Width + [8:7] + + + TSEG1 + Time Segment 1 + [6:3] + + + TSEG2 + Time Segment 2 + [2:0] + + + + + GMSKX + CAN Global Mask Extension + 0x208 + 0x00000000 + + + GM + GM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard + [15:1] + + + XRTR + Extended Remote transmission Request Bit + [0:0] + + + + + GMSKB + CAN Global Mask Base + 0x20C + 0x00000000 + + + GM1 + GM[28:18] - ID[10:0] in standard, ID[28:18] in extended + [15:5] + + + RTR + Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended + [4:4] + + + IDE + Identifier Extension Bit + [3:3] + + + GM0 + GM[17:15] - Unused in standard, ID[17:15] in extended + [2:0] + + + + + BMSKX + CAN Basic Mask Extension + 0x210 + 0x00000000 + + + BM + BM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard + [15:1] + + + XRTR + Extended Remote transmission Request Bit + [0:0] + + + + + BMSKB + CAN Basic Mask Base + 0x214 + 0x00000000 + + + BM1 + BM[28:18] - ID[10:0] in standard, ID[28:18] in extended + [15:5] + + + RTR + Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended + [4:4] + + + IDE + Identifier Extension Bit + [3:3] + + + BM0 + BM[17:15] - Unused in standard, ID[17:15] in extended + [2:0] + + + + + CIEN + CAN Interrupt Enable Register + 0x218 + 0x00000000 + + + EIEN + Error Interrupt Enable + [15:15] + + + IEN + Buffer Interrupt Enable[14:0] + [14:0] + + + + + CIPND + CAN Interrupt Pending Register + 0x21C + 0x00000000 + + + EIPND + Error Interrupt Pending + [15:15] + + + IPND + Buffer Interrupt Pending[14:0] + [14:0] + + + + + CICLR + CAN Interrupt Clear Register + 0x220 + 0x00000000 + + + EICLR + Error Interrupt Clear + [15:15] + + + ICLR + Buffer Interrupt Clear[14:0] + [14:0] + + + + + CICEN + CAN Interrupt Code Enable Register + 0x224 + 0x00000000 + + + EICEN + Error Interrupt Code Enable + [15:15] + + + ICEN + Buffer Interrupt Code Enable[14:0] + [14:0] + + + + + CSTPND + CAN Status Pending Register + 0x228 + 0x00000000 + + + NS + CAN Node Status + [7:5] + + + IRQ + Interrupt Request portion of Interrupt Code + [4:4] + + + IST + Interrupt Source portion of Interrupt Code + [3:0] + + + + + CANEC + CAN Error Counter Register + 0x22C + 0x00000000 + + + REC + Receive Error Counter + [15:8] + + + TEC + Transmit Error Counter + [7:0] + + + + + CEDIAG + CAN Error Diagnostic Register + 0x230 + 0x00000000 + + + DRIVE + Drive + [14:14] + + + MON + Monitor + [13:13] + + + CRC + CRC + [12:12] + + + STUFF + Stuff Error + [11:11] + + + TXE + Transmit Error + [10:10] + + + EBID + Error Bit Identifier + [9:4] + + + EFID + Error Field Identifier + [3:0] + + + + + CTMR + CAN Timer Register + 0x234 + 0x00000000 + + + CTMR + Time Stamp Counter + [15:0] + read-only + + + + + + + CAN1 + 0x40014400 + + + ADC + 1.0 + Analog to Digital Converter Peripheral + ADC + ADC + 0x40022000 + + 0x0 + 0x1000 + registers + + + ADC + 44 + + + + CTRL + Control Register + 0x0 + 0x00000000 + + + CONV_CNT + Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions) + [23:20] + + + MANUAL_TRIG + Starts analog acquisition + [19:19] + + + EXT_TRIG_EN + Allows the external trigger to start analog acquisition + [18:18] + + + SWEEP_EN + ADC data acquisition for all enabled channel + [17:17] + + + CHAN_TAG_EN + Enables the channel tag to be saved with the ADC data + [16:16] + + + CHAN_EN + Enables the channel for data collection + [15:0] + + + + + FIFO_DATA + FIFO data + 0x4 + read-only + 0x00000000 + + + CHAN_TAG + If enabled, this will include the number of the channel corresponding to the measurement + [15:12] + read-only + + + ADC_DATA + ADC acquisition data from the FIFO + [11:0] + + + + + STATUS + Status + 0x8 + read-only + 0x00000000 + + + ADC_BUSY + Indicates an ADC data acquisition is in process + [7:7] + + + FIFO_ENTRY_CNT + Indicates the number of entries in the FIFO + [5:0] + + + + + IRQ_ENB + Interrupt Enable + 0xC + 0x00000000 + + + FIFO_DEPTH_TRIG + Enables the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Enables the interrupt for a trigger error + [5:5] + + + ADC_DONE + Enables the interrupt for an ADC data acquisition completion + [4:4] + + + FIFO_UFLOW + Enables the interrupt for a FIFO underflow + [3:3] + + + FIFO_OFLOW + Enables the interrupt for a FIFO overflow + [2:2] + + + FIFO_FULL + Enables the interrupt for FIFO full + [1:1] + + + FIFO_EMPTY + Enables the interrupt for FIFO empty + [0:0] + + + + + IRQ_RAW + Raw Interrupt Status + 0x10 + read-only + 0x00000001 + + + FIFO_DEPTH_TRIG + Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion + [5:5] + + + ADC_DONE + Indicates that a ADC conversion is done + [4:4] + + + FIFO_UFLOW + Indicates data was unavailable when a new trigger for ADC update is received + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred (FIFO was full when new data was written) + [2:2] + + + FIFO_FULL + Indicates the FIFO is full + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty + [0:0] + + + + + IRQ_END + Enabled Interrupt Status + 0x14 + read-only + 0x00000000 + + + FIFO_DEPTH_TRIG + Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled + [5:5] + + + ADC_DONE + Indicates that a ADC conversion is done and the interrupt is enabled + [4:4] + + + FIFO_UFLOW + Indicates a FIFO underflow occurred and the interrupt is enabled + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred and the interrupt is enabled + [2:2] + + + FIFO_FULL + Indicates the FIFO is full and the interrupt is enabled + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty and the interrupt is enabled + [0:0] + + + + + IRQ_CLR + Clear Interrupt + 0x18 + write-only + 0x00000000 + + + TRIG_ERROR + Clears the trigger error interrupt status. Always reads 0 + [3:3] + + + ADC_DONE + Clears the ADC done interrupt status. Always reads 0 + [2:2] + + + FIFO_UFLOW + Clears the FIFO underflow interrupt status. Always reads 0 + [1:1] + + + FIFO_OFLOW + Clears the FIFO overflow interrupt status. Always reads 0 + [0:0] + + + + + RXFIFOIRQTRG + Receive FIFO Interrupt Trigger Value + 0x1C + 0x00000010 + + + LEVEL + Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt + [4:0] + + + + + FIFO_CLR + FIFO Clear + 0x20 + 0x00000000 + + + FIFO_CLR + Clears the ADC FIFO. Always reads 0 + [0:0] + write-only + + + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x001907E9 + + + + + DAC0 + 1.0 + Digital to Analog Converter Peripheral + DAC + DAC + 0x40023000 + + 0x0 + 0x800 + registers + + + DAC0 + 40 + + + DAC1 + 41 + + + + CTRL0 + Control Register 0 + 0x0 + 0x00000000 + + + MAN_TRIG_EN + Enables manual trigger + [11:11] + + + EXT_TRIG_EN + Enables external trigger + [10:10] + + + + + CTRL1 + Control Register 1 + 0x4 + 0x00000000 + + + DAC_EN + Enables the DAC analog block + [8:8] + + + DAC_SETTLING + Sets the the amount of time in microseconds the control FSM waits for the DAC settling time + [7:5] + + + + + FIFO_DATA + FIFO data + 0x8 + read-write + 0x00000000 + + + DATA + Data for FIFO write + [11:0] + write-only + + + + + STATUS + Status + 0xC + read-only + 0x00000000 + + + DAC_BUSY + Indicates a DAC data acquisition is in process + [7:7] + + + FIFO_ENTRY_CNT + Indicates the number of entries in the FIFO + [5:0] + + + + + IRQ_ENB + Interrupt Enable + 0x10 + 0x00000000 + + + FIFO_DEPTH_TRIG + Enables the interrupt for the FIFO entry count is less than or equal to the trigger level + [6:6] + + + TRIG_ERROR + Enables the interrupt for a trigger error + [5:5] + + + DAC_DONE + Enables the interrupt for a DAC data acquisition completion + [4:4] + + + FIFO_UFLOW + Enables the interrupt for a FIFO underflow + [3:3] + + + FIFO_OFLOW + Enables the interrupt for a FIFO overflow + [2:2] + + + FIFO_FULL + Enables the interrupt for FIFO full + [1:1] + + + FIFO_EMPTY + Enables the interrupt for FIFO empty + [0:0] + + + + + IRQ_RAW + Raw Interrupt Status + 0x14 + read-only + 0x00000041 + + + FIFO_DEPTH_TRIG + Indicates the FIFO entry count is less than or equal to the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion + [5:5] + + + DAC_DONE + Indicates that a DAC conversion is done + [4:4] + + + FIFO_UFLOW + Indicates data was unavailable when a new trigger for DAC update is received + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred (FIFO was full when new data was written) + [2:2] + + + FIFO_FULL + Indicates the FIFO is full + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty + [0:0] + + + + + IRQ_END + Enabled Interrupt Status + 0x18 + read-only + 0x00000000 + + + FIFO_DEPTH_TRIG + Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled + [5:5] + + + DAC_DONE + Indicates that a DAC conversion is done and the interrupt is enabled + [4:4] + + + FIFO_UFLOW + Indicates a FIFO underflow occurred and the interrupt is enabled + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred and the interrupt is enabled + [2:2] + + + FIFO_FULL + Indicates the FIFO is full and the interrupt is enabled + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty and the interrupt is enabled + [0:0] + + + + + IRQ_CLR + Clear Interrupt + 0x1C + write-only + 0x00000000 + + + TRIG_ERROR + Clears the trigger error interrupt status. Always reads 0 + [3:3] + + + DAC_DONE + Clears the DAC done interrupt status. Always reads 0 + [2:2] + + + FIFO_UFLOW + Clears the FIFO underflow interrupt status. Always reads 0 + [1:1] + + + FIFO_OFLOW + Clears the FIFO overflow interrupt status. Always reads 0 + [0:0] + + + + + TXFIFOIRQTRG + Receive FIFO Interrupt Trigger Value + 0x20 + 0x00000010 + + + LEVEL + Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt + [4:0] + + + + + FIFO_CLR + FIFO Clear + 0x24 + 0x00000000 + + + FIFO_CLR + Clears the DAC FIFO. Always reads 0 + [0:0] + write-only + + + + + PERID + Peripheral ID Register + 0x7FC + read-only + 0x002007E9 + + + + + DAC1 + 0x40023800 + + + SPW + 1.0 + SpaceWire Peripheral + SPW + SPW + 0x40003000 + + 0x0 + 0x400 + registers + + + SpW + 38 + + + + CTRL + Control Register + 0x0 + 0xA2010004 + + + RA + Reads as 1 if the RMAP command handler is available + [31:31] + read-only + + + RX + Reads as 1 if unaligned writes are available for the receiver + [30:30] + read-only + + + RC + Reads as 1 if RMAP CRC is enabled in the core + [29:29] + read-only + + + NCH + Number of DMA Channels minus one + [28:27] + read-only + + + PO + The number of available SpaceWire ports minus one + [26:26] + read-only + + + CC + CCSDS/CCITT CRC-16 + [25:25] + read-only + + + ID + Interrupt distribution available + [24:24] + read-only + + + LE + Loop-back Enable + [22:22] + read-write + + + PS + Selects the active port when the no port force bit is zero + [21:21] + read-write + + + NP + Disable port force + [20:20] + read-write + + + PNPA + SpW Plug-and-Play Available + [19:18] + read-only + + + RD + If set only one RMAP buffer is used + [17:17] + read-write + + + RE + Enable RMAP command handler + [16:16] + read-write + + + PE + SpW Plug-and-Play Enable + [15:15] + read-write + + + TL + Transmitter Enable Lock Control + [13:13] + read-write + + + TF + Time-code Flag Filter + [12:12] + read-write + + + TR + Enable time-code receptions + [11:11] + + + TT + Enable time-code transmissions + [10:10] + + + LI + Generate interrupt when link error occurs + [9:9] + + + TQ + Generate interrupt when a valid time-code is received + [8:8] + + + RS + Make complete reset of the SpaceWire node. Self-clearing + [6:6] + + + PM + Enable Promiscuous mode + [5:5] + + + TI + The host can generate a tick by writing a one to this field + [4:4] + + + IE + If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs + [3:3] + + + AS + Automatically start the link when a NULL has been received + [2:2] + + + LS + Start the link + [1:1] + + + LD + Disable the SpaceWire CODEC + [0:0] + + + + + STS + Status/Interrupt Source Register + 0x4 + 0x06400000 + + + NRXD + Number of Receive Descriptors + [27:26] + + + NTXD + Number of Transmit Descriptors + [25:24] + + + LS + Link State + [23:21] + + + AP + Active port + [9:9] + + + EE + Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet + [8:8] + + + IA + Packet is received with an invalid destination address field + [7:7] + + + WE + A synchronization problem has occurred when receiving NChars + [6:6] + + + PE + Parity error has occurred + [4:4] + + + DE + Disconnection error has occurred + [3:3] + + + ER + Escape error has occurred + [2:2] + + + CE + Credit has occurred + [1:1] + + + TO + A new time count value was received + [0:0] + + + + + DEFADDR + Node Address Register + 0x8 + read-write + 0x000000FE + + + DEFMASK + 8-bit default mask used for node identification on the SpaceWire network + [15:8] + + + DEFADDR + 8-bit node address used for node identification on the SpaceWire network + [7:0] + + + + + CLKDIV + Clock Divisor Register + 0xC + read-write + 0x00000909 + + + CLKDIVSTART + 8-bit Clock divisor value used for the clock-divider during startup + [15:8] + + + CLKDIVRUN + 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state + [7:0] + + + + + DKEY + Destination Key + 0x10 + 0x00000000 + + + DESTKEY + RMAP destination key + [7:0] + + + + + TC + Time Code Register + 0x14 + read-write + 0x00000000 + + + TIRQ_END + The current value of the time control flags + [7:6] + + + TIMECNT + The current value of the system time counter + [5:0] + + + + + TDR + Timer and Disconnect Register + 0x18 + read-only + 0x00000000 + + + DISCONNECT + Used to generate the 850 ns disconnect time period + [21:12] + + + TIMER64 + Used to generate the 6.4 and 12.8 us time periods + [11:0] + + + + + DMACTRL0 + DMA Control Register + 0x20 + read-write + 0x00000000 + + + INTNUM + Interrupt number used for this channel + [31:26] + + + EP + EEP Termination + [23:23] + + + TR + Truncated + [22:22] + + + IE + Interrupt code transmit enable on EEP + [21:21] + + + IT + Interrupt code transmit enable on truncation + [20:20] + + + RP + Receive Packet IRQ + [19:19] + + + TP + Transmit Packet IRQ + [18:18] + + + TL + Transmit Enable Lock + [17:17] + + + LE + Disable transmitter when a link error occurs + [16:16] + + + SP + Strip PID + [15:15] + + + SA + Strip Address + [14:14] + + + EN + Enable Address + [13:13] + + + NS + If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated + [12:12] + + + RD + Indicates to the GRSPW that there are enabled descriptors in the descriptor table + [11:11] + + + RX + Reception to the DMA channel is currently active + [10:10] + read-only + + + AT + Abort the currently transmitting packet and disable transmissions + [9:9] + read-only + + + RA + An error response was detected on the AHB bus - DMA receive + [8:8] + + + TA + An error response was detected on the AHB bus - DMA transmit + [7:7] + + + PR + Set each time a packet has been received + [6:6] + + + PS + Set each time a packet has been sent + [5:5] + + + AI + An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus + [4:4] + + + RI + An interrupt will be generated each time a packet has been received + [3:3] + + + TI + An interrupt will be generated each time a packet is transmitted + [2:2] + + + RE + Packets are allowed to be received to this channel + [1:1] + + + TE + Write a one to this bit each time new descriptors are activated in the table + [0:0] + + + + + DMAMAXLEN0 + DMA RX Maximum Length Register + 0x24 + read-write + 0x00000000 + + + RXMAXLEN + Receiver packet maximum length in bytes + [24:2] + + + + + DMATXDESC0 + DMA Transmitter Descriptor Table Address Register + 0x28 + read-write + 0x00000000 + + + DESCBASEADDR + Sets the base address of the descriptor table + [31:10] + + + DESCSEL + Offset into the descriptor table + [9:4] + + + + + DMARXDESC0 + DMA Receiver Table Destination Register + 0x2C + read-write + 0x00000000 + + + DESCBASEADDR + Sets the base address of the descriptor table + [31:10] + + + DESCSEL + Offset into the descriptor table + [9:3] + + + + + DMAADDR0 + DMA Receiver Table Address Register + 0x30 + read-write + 0x00000000 + + + MASK + Mask + [15:8] + + + ADDR + Address + [7:0] + + + + + + + IRQ_ROUTER + 1.0 + Interrupt Router Peripheral + IRQ + 0x40002000 + + 0x0 + 0x1000 + registers + + + U0 + 0 + + + U1 + 1 + + + U2 + 2 + + + U3 + 3 + + + U4 + 4 + + + U5 + 5 + + + U6 + 6 + + + U7 + 7 + + + U8 + 8 + + + U9 + 9 + + + U10 + 10 + + + U11 + 11 + + + U12 + 12 + + + U13 + 13 + + + U14 + 14 + + + U15 + 15 + + + U37 + 37 + + + U39 + 39 + + + U73 + 73 + + + U75 + 75 + + + FPU + 194 + + + TXEV + 195 + + + + DMASEL0 + Interrupt select for DMA channel 0 + 0x0 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL1 + Interrupt select for DMA channel 1 + 0x4 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL2 + Interrupt select for DMA channel 2 + 0x8 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL3 + Interrupt select for DMA channel 3 + 0xC + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMATTSEL + Trigger select for the DMA channels + 0x10 + read-write + 0x00000000 + + + DMATTSEL + DMA trigger type selection value + [3:0] + + + + + ADCSEL + Interrupt select for ADC + 0x14 + read-write + 0x0000001F + + + ADCSEL + ADC trigger source selection value + [4:0] + + + + + DACSEL0 + Interrupt select for DAC0 + 0x18 + read-write + 0x0000001F + + + DACSEL + DAC trigger source selection value + [4:0] + + + + + DACSEL1 + Interrupt select for DAC1 + 0x1C + read-write + 0x0000001F + + + DACSEL + DAC trigger source selection value + [4:0] + + + + + IRQ_OUT0 + DEBUG IRQ_OUT[31:0] + 0x20 + read-only + 0x00000000 + + + IRQ_OUT0 + IRQ_OUT[31:0] + [31:0] + + + + + IRQ_OUT1 + DEBUG IRQ_OUT[63:32] + 0x24 + read-only + 0x00000000 + + + IRQ_OUT1 + IRQ_OUT[63:32] + [31:0] + + + + + IRQ_OUT2 + DEBUG IRQ_OUT[95:64] + 0x28 + read-only + 0x00000000 + + + IRQ_OUT2 + IRQ_OUT[95:64] + [31:0] + + + + + IRQ_OUT3 + DEBUG IRQ_OUT[127:96] + 0x2C + read-only + 0x00000000 + + + IRQ_OUT3 + IRQ_OUT[127:96] + [31:0] + + + + + IRQ_OUT4 + DEBUG IRQ_OUT[159:128] + 0x30 + read-only + 0x00000000 + + + IRQ_OUT4 + IRQ_OUT[159:128] + [31:0] + + + + + IRQ_OUT5 + DEBUG IRQ_OUT[179:160] + 0x34 + read-only + 0x00000000 + + + IRQ_OUT5 + IRQ_OUT[179:160] + [19:0] + + + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028107E9 + + + + + WATCH_DOG + 1.0 + Watchdog Block Peripheral + WDOG + 0x40021000 + + 0x0 + 0x1000 + registers + + + WATCHDOG + 47 + + + + WDOGLOAD + Counter Start Value + 0x0 + read-write + 0xFFFFFFFF + + + CNT + Count to load + [31:0] + + + + + WDOGVALUE + Down Counter Value + 0x4 + read-only + 0xFFFFFFFF + + + CNT + Actual Count + [31:0] + + + + + WDOGCONTROL + Enable for block reset and interrupt + 0x8 + read-write + 0x00000000 + + + RESEN + Enable watchdog reset output + [1:1] + + + INTEN + Enable watchdog interrupt + [0:0] + + + + + WDOGINTCLR + A write of any value clears the WDT module interrupt, and reloads +the counter from the value in the WDOGLOAD Register + 0xC + read-write + 0x00000000 + + + CLEAR + Write any value to clear interrupt + [31:0] + + + + + WDOGRIS + Raw interrupt status + 0x10 + read-only + 0x00000000 + + + INTERRUPT + Interrupt Status + [0:0] + + + + + WDOGMIS + Interrupt status + 0x14 + read-only + 0x00000000 + + + INTERRUPT + Masked Interrupt Status + [0:0] + + + + + WDOGLOCK + Lock + 0xC0 + read-write + 0x00000000 + + + REG_WR_EN + Register write enable status + [31:0] + + + + + WDOGITCR + Integration test control + 0xF00 + read-write + 0x00000000 + + + TEST_MODE_EN + Enable test mode of WDOGINT and WDOGRES + [0:0] + + + + + WDOGITOP + Integration test output set + 0xF04 + read-write + 0x00000000 + + + WDOGINT + Set output value + [1:1] + + + WDOGRES + Set output value + [0:0] + + + + + WDOGPERIPHID0 + Peripheral ID + 0xFE0 + read-only + 0x00000024 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID1 + Peripheral ID + 0xFE4 + read-only + 0x000000B8 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID2 + Peripheral ID + 0xFE8 + read-only + 0x0000001B + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID3 + Peripheral ID + 0xFEC + read-only + 0x00000000 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPCELLID0 + PrimeCell ID + 0xFF0 + read-only + 0x0000000D + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID1 + PrimeCell ID + 0xFF4 + read-only + 0x000000F0 + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID2 + PrimeCell ID + 0xFF8 + read-only + 0x00000005 + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID3 + PrimeCell ID + 0xFFC + read-only + 0x000000B1 + + + PCELLID + Prime Cell ID + [7:0] + + + + + + + TRNG + 1.0 + True Random Number Generator + TRNG + 0x40027000 + + 0x0 + 0x400 + registers + + + TRNG + 42 + + + + IMR + Interrupt Mask Register + 0x100 + read-write + 0x0000000F + + + VN_ERR_INT_MASK + Mask the Von Neumann error + [3:3] + + + CRNGT_ERR_INT_MASK + Mask the CRNGT error + [2:2] + + + AUTOCORR_ERR_INT_MASK + Mask the Autocorrelation error + [1:1] + + + EHR_VALID_INT_MASK + Mask when the TRNG has collected 192 bits + [0:0] + + + + + ISR + Interrupt Status Register + 0x104 + read-only + 0x00000000 + + + VN_ERR + Indicates a Von Neumann error + [3:3] + + + CRNGT_ERR + Indicates a Continuous Random Number Generation Testing (CRNGT) error + [2:2] + + + AUTOCORR_ERR + Indicates that the Autocorrelation test failed four times in a row + [1:1] + + + EHR_VALID + 192 bits have been collected in the TRNG + [0:0] + + + + + ICR + Interrupt Clear Register + 0x108 + read-write + 0x00000000 + + + VN_ERR + Clears a Von Neumann error + [3:3] + + + CRNGT_ERR + Clear a Continuous Random Number Generation Testing (CRNGT) error + [2:2] + + + AUTOCORR_ERR + Software cannot clear this bit. Only a TRNG reset can clear this bit + [1:1] + + + EHR_VALID + Set to 1 after the EHR_DATA[0,1,2,3,4,5] registers have been read + [0:0] + + + + + CONFIG + Configuration Register + 0x10C + read-write + 0x00000000 + + + RND_SRC_SEL + Selects the number of inverters (out of four possible selections) in the ring oscillator + [1:0] + + + + + VALID + Valid Register + 0x110 + read-only + 0x00000000 + + + EHR_VALID + Indicates that the collection of bits in the TRNG is complete + [0:0] + + + + + EHR_DATA0 + Entropy Holding Register Data Register + 0x114 + read-only + 0x00000000 + + + EHR_DATA + 32 Bits of Entropy Holding Register + [31:0] + + + + + EHR_DATA1 + Entropy Holding Register Data Register + 0x118 + + + EHR_DATA2 + Entropy Holding Register Data Register + 0x11C + + + EHR_DATA3 + Entropy Holding Register Data Register + 0x120 + + + EHR_DATA4 + Entropy Holding Register Data Register + 0x124 + + + EHR_DATA5 + Entropy Holding Register Data Register + 0x128 + + + RND_SOURCE_ENABLE + Random Source Enable Register + 0x12C + read-write + 0x00000000 + + + RND_SRC_EN + The entropy source, ring oscillator, is enabled + [0:0] + + + + + SAMPLE_CNT1 + Section TBD + 0x130 + read-write + 0x0000FFFF + + + SAMPLE_CNTR1 + Sets the number of clk cycles between two consecutive ring oscillator samples + [31:0] + + + + + AUTOCORR_STATISTIC + Auto-correlator Statistic Register + 0x134 + read-write + 0x00000000 + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails + [21:14] + + + AUTOCORR_TRYS + Count each time an autocorrelation test starts + [13:0] + + + + + DEBUG_CONTROL + Section TBD + 0x138 + read-write + 0x00000000 + + + AUTO_CORRELATE_BYPASS + The autocorrelation test in the TRNG module is bypassed + [3:3] + + + CRNGT_BYPASS + The CRNGT test in the TRNG is bypassed + [2:2] + + + VNC_PYPASS + The Von Neumann balancer is bypassed + [1:1] + + + + + SW_RESET + Reset Register + 0x140 + read-write + 0x00000000 + + + SW_RESET + Writing 1 to this register causes an internal TRNG reset + [0:0] + + + + + BUSY + Busy Register + 0x1B8 + read-only + 0x00000000 + + + BUSY + Reflects the status of the rng_busy signal + [0:0] + + + + + RST_BITS_COUNTER + Reset Bits Counter Register + 0x1BC + read-write + 0x00000000 + + + RST_BITS_COUNTER + Writing any value to this bit resets the bits counter and TRNG valid registers + [0:0] + + + + + BIST_CNTR0 + BIST Counter Register + 0x1E0 + read-only + 0x00000000 + + + ROSC_CNTR_VAL + Returns the results of the TRNG BIST counter + [21:0] + + + + + BIST_CNTR1 + BIST Counter Register + 0x1E4 + + + BIST_CNTR2 + BIST Counter Register + 0x1E8 + + + + + ETH + 1.1 + Ethernet Block + ETH + 0x40004000 + + 0x0 + 0x2000 + registers + + + Ethernet + 36 + + + + MAC_CONFIG + Operation mode register for the MAC + 0x0 + read-write + 0x00000000 + + + WD + Watchdog disable + [23:23] + + + JD + Jabber Disable + [22:22] + + + BE + Frame Burst Enable + [21:21] + + + JE + Jumbo Frame Enable + [20:20] + + + IFG + Inter-Frame Gap + [19:17] + + + DCRS + Disable Carrier Sense During Transmission + [16:16] + + + PS + Port Select + [15:15] + + + FES + Speed + [14:14] + + + DRO + Disable Receive Own + [13:13] + + + LM + Loopback Mode + [12:12] + + + DM + Duplex Mode + [11:11] + + + IPC + Checksum Offload + [10:10] + + + DR + Disable Retry + [9:9] + + + ACS + Automatic Pad, or CRC Stripping + [7:7] + + + BL + Back-Off-Limit + [6:5] + + + DC + Deferral Check + [4:4] + + + TE + Transmitter Enable + [3:3] + + + RE + Receiver Enable + [2:2] + + + PRELEN + Preamble Length for Transmit frames + [1:0] + + + + + MAC_FRAME_FLTR + Contains the frame filtering controls + 0x4 + read-write + 0x00000000 + + + RA + Receive All + [31:31] + + + DNTU + Drop non TCP/UDP over IP Frames + [21:21] + + + VFTE + VLAN Tag Filter Enable + [16:16] + + + HDF + Hash or Perfect Filter + [10:10] + + + SAF + Source Address Filter Enable + [9:9] + + + SAIF + SA Inverse Filtering + [8:8] + + + PCF + Pass Control Frames + [7:6] + + + DBF + Disable Broadcast Frames + [5:5] + + + PM + Pass All Multicast + [4:4] + + + DAIF + DA Inverse Filtering + [3:3] + + + HMC + Hash Multicast + [2:2] + + + HUC + Hash Unicast + [1:1] + + + PR + Promiscuous Mode + [0:0] + + + + + MAC_GMII_ADDR + Controls the management cycles to an external PHY + 0x10 + read-write + 0x00000000 + + + PA + Physical Layer Address + [15:11] + + + GR + GMII Register + [10:6] + + + CR + CSR Clock Range + [5:2] + + + GW + GMII Write/Read + [1:1] + + + GB + GMII Busy + [0:0] + + + + + MAC_GMII_DATA + Contains the data to be written to or read from the PHY register + 0x14 + read-write + 0x00000000 + + + GD + GMII Data + [15:0] + + + + + MAC_FLOW_CTRL + Controls the generation of control frames + 0x18 + read-write + 0x00000000 + + + PT + Pause time + [31:16] + + + DZPQ + Disable Zero-Quanta Pause + [7:7] + + + PLT + Pause Low Threshold + [5:4] + + + UP + Unicast Pause Frame Detect + [3:3] + + + RFE + Receive Flow Control Enable + [2:2] + + + TFE + Transmit Flow Control Enable + [1:1] + + + FCB_BPA + Flow Control Busy or Backpressure Activate + [0:0] + + + + + MAC_VLAN_TAG + Identifies IEEE 802.1Q VLAN type frames + 0x1C + read-write + 0x00000000 + + + ESVL + Enable S-VLAN + [18:18] + + + VTIM + VLAN Tag Inverse Match Enable + [17:17] + + + ETV + Enable 12-Bit VLAN Tag Comparison + [16:16] + + + VL + VLAN Tag identifier for Receive Frames + [15:0] + + + + + MAC_DEBUG + Gives the status of the various internal blocks for debugging + 0x24 + read-only + 0x00000000 + + + TXSTSFSTS + MTL TxStatus FIFO Full Status + [25:25] + + + TXFSTS + MTL Tx FIFO Not Empty Status + [24:24] + + + TWCSTS + MTL Tx FIFO Write Controller Status + [22:22] + + + TRCSTS + MTL Tx FIFO Read Controller Status + [21:20] + + + TXPAUSED + MAC Transmitter in Pause + [19:19] + + + TFCSTS + PAC Transmit Frame Controller Status + [18:17] + + + TPESTS + MAC GMII or MII Transmit Protocol Engine Status + [16:16] + + + RXFSTS + MTL RxFIFO Fill-Level Status + [9:8] + + + RRCSTS + MTL RxFIFO Read Controller State + [6:5] + + + RWCSTS + MTL Rx FIFO Write Controller Active Status + [4:4] + + + RFCFCSTS + MAC Receive Frame FIFO Controller Status + [2:1] + + + RPESTS + MAC GMII or MII Receive Protocol Engine Status + [0:0] + + + + + MAC_INTR_STAT + Contains the interrupt status + 0x38 + read-only + 0x00000000 + + + TSIS + Timestamp Interrupt Status + [9:9] + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status + [7:7] + + + MMCTXIS + MMC Transmit Interrupt Status + [6:6] + + + MMCRXIS + MMC Receive Interrupt Status + [5:5] + + + MMCIS + MMC Interrupt Status + [4:4] + + + + + MAC_INTR_MASK + Contains the masks for generating interrupt + 0x3C + read-write + 0x00000000 + + + TSIM + Timestamp Interrupt Mask + [9:9] + + + + + MAC_ADDR_H + Contains the high 16-bits of the first MAC Address + 0x40 + read-write + 0x8000FFFF + + + AE + Address Enable, This bit is always set to 1 + [31:31] + read-only + + + ADDRHI + MAC Address0[47:32] + [15:0] + read-only + + + + + MAC_ADDR_L + Contains the Low 32-bits of the first MAC Address + 0x44 + read-write + 0xFFFFFFFF + + + ADDRLO + MAC Address0[31:0] + [31:0] + read-only + + + + + MAC_WDOG_TO + Controls the watchdog time-out for received frames + 0xDC + read-write + 0x00000000 + + + PWE + Programmable Watchdog Enable + [16:16] + + + WTO + Watchdog Timeout + [13:0] + + + + + MMC_CNTRL + MMC Control Register + 0x100 + read-write + 0x00000000 + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames + [8:8] + + + CNTPRSTLVL + Full-Half Preset + [5:5] + + + CNTPRST + Counters Preset + [4:4] + + + CNTFREEZ + MMC Counter Freeze + [3:3] + + + RSTONRD + Reset on Read + [2:2] + + + CNTSTOPRO + Counter Stop Rollover + [1:1] + + + CNTRST + Counters Reset + [0:0] + + + + + MMC_INTR_RX + MMC Receive Interrupt Register + 0x104 + read-write + 0x00000000 + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status + [25:25] + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status + [24:24] + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status + [23:23] + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status + [22:22] + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status + [21:21] + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status + [20:20] + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status. + [19:19] + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status + [18:18] + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status + [17:17] + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. + [16:16] + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + [15:15] + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status + [14:14] + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status + [13:13] + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status + [12:12] + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status + [11:11] + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status + [10:10] + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status + [9:9] + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status + [8:8] + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status + [7:7] + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status + [6:6] + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status + [5:5] + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status + [4:4] + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status + [3:3] + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status + [2:2] + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status + [1:1] + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status + [0:0] + + + + + MMC_INTR_TX + MMC Transmit Interrupt Register + 0x108 + read-write + 0x00000000 + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status + [25:25] + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status + [24:24] + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status + [23:23] + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status + [22:22] + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status + [21:21] + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status + [20:20] + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status + [19:19] + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status + [18:18] + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status + [17:17] + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status + [16:16] + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status + [15:15] + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status + [14:14] + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status + [13:13] + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status + [12:12] + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status + [11:11] + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status + [10:10] + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + [9:9] + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + [8:8] + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status + [7:7] + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status + [6:6] + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status + [5:5] + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status + [4:4] + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status + [3:3] + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status + [2:2] + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status + [1:1] + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status + [0:0] + + + + + MMC_INTR_MASK_RX + MMC Receive Interrupt Mask Register + 0x10C + read-write + 0x00000000 + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask + [25:25] + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask + [24:24] + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask + [23:23] + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask + [22:22] + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask + [21:21] + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask + [20:20] + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask + [19:19] + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask + [18:18] + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask + [17:17] + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. + [16:16] + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + [15:15] + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + [14:14] + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + [13:13] + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + [12:12] + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask + [11:11] + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask + [10:10] + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask + [9:9] + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask + [8:8] + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask + [7:7] + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask + [6:6] + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask + [5:5] + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask + [4:4] + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask + [3:3] + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask + [2:2] + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask. + [1:1] + + + RXGBFRMIM + MMC Receive Good Bad Frame Counter Interrupt Mask + [0:0] + + + + + MMC_INTR_MASK_TX + MMC Transmit Interrupt Mask Register + 0x110 + read-write + 0x00000000 + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask + [25:25] + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask + [24:24] + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask + [23:23] + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask + [22:22] + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask + [21:21] + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask + [20:20] + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask + [19:19] + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask + [18:18] + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask + [17:17] + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask + [16:16] + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask + [15:15] + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask + [14:14] + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask + [13:13] + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask + [12:12] + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask + [11:11] + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask + [10:10] + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + [9:9] + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + [8:8] + + + TX256T511OCTGBFIM + MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + [7:7] + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + [6:6] + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + [5:5] + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask + [4:4] + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask + [3:3] + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask + [2:2] + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask + [1:1] + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask + [0:0] + + + + + TXOCTETCOUNT_GB + MMC Transmit Count + 0x114 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + TXFRAMECOUNT_GB + MMC Frame Count Register + 0x118 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXBCASTFRAMES_G + MMC Good Broadcast Frames Register + 0x11C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMCASTFRAMES_G + MMC Good Multicast Frames Register + 0x120 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX64OCT_GB + MMC Good and bad Frames transmitted with length 64 + 0x124 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX65TO127OCT_GB + MMC Good and bad Frames transmitted with length 65 to 127 + 0x128 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX128TO255OCT_GB + MMC Good and bad Frames transmitted with length 128 to 255 + 0x12C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX256TO511OCT_GB + MMC Good and bad Frames transmitted with length 256 to 511 + 0x130 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX512TO1023OCT_GB + MMC Good and bad Frames transmitted with length 512 to 1023 + 0x134 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX1024MAXOCT_GB + MMC Good and bad Frames transmitted with length 1024 to max bytes + 0x138 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXUCASTFRAME_GB + MMC number of good and bad unicast frames transmitted + 0x13C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMCASTFRAME_GB + MMC number of good and bad MULTIcast frames transmitted + 0x140 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXBCASTFRAME_GB + MMC number of good and bad broadcast frames transmitted + 0x144 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXUNDERERR + MMC number of frames aborted because of frame underflow error + 0x148 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXSINGLECOL_G + MMC Number of successfully transmitted frames after a single collision + 0x14C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMULTICOL_G + MMC Number of successfully transmitted frames after multiple collisions + 0x150 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXDEFERRED + MMC Number of successfully transmitted frames after a deferral + 0x154 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXLATECOL + MMC Number of aborted frames because of late collision error + 0x158 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXEXESSCOL + MMC Number of aborted frames because of excessive collision errors + 0x15C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXCARRIERERROR + MMC Number of aborted frames because of carrier sense error + 0x160 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXOCTETCOUNT_G + MMC Number of bytes transmitted frames only in good frames + 0x164 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + TXFRAMECOUNT_G + MMC Number of good frames transmitted + 0x168 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXEXCESSDEF + MMC Number of frames aborted because of excessive deferral error + 0x16C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXPAUSEFRAMES + MMC Number of good pause frames transmitted + 0x170 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXLANFRAMES_G + MMC Number of good VLAN frames transmitted + 0x174 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXOVERSIZE_G + MMC Number of frames transmitted without errors + 0x178 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXFRAMECOUNT_GB + MMC Number of good and bad frames received + 0x180 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOCTETCOUNT_GB + MMC Number of bytes received in good and bad frames + 0x184 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + RXOCTETCOUNT_G + MMC Number of bytes received in good frames only + 0x188 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + RXBCASTFRAMES_G + MMC Number of good broadcast frames received + 0x18C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXMCASTFRAMES_G + MMC Number of good multicast frames received + 0x190 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXCRCERROR + MMC Number of frames received with CRC error + 0x194 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXALIGNERROR + MMC Number of frames received with alignment error + 0x198 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXRUNTERROR + MMC Number of frames received with runt error + 0x19C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXJABBERERROR + MMC Number of giant frames received with length greater than 1518 bytes and with CRC error + 0x1A0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXUNDERSIZE_G + MMC Number of frames received with length less than 64 bytes + 0x1A4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOVERSIZE_G + MMC Number of frames received without errors with length greater than the max size + 0x1A8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX64OCTETS_GB + MMC Number of good and bad frames received with length 64 bytes + 0x1AC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX65TO127OCT_GB + MMC Number of good and bad frames received with length between 65 and 127 bytes + 0x1B0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX128TO255OCT_GB + MMC Number of good and bad frames received with length between 128 and 255 bytes + 0x1B4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX256TO511OCT_GB + MMC Number of good and bad frames received with length between 256 and 511 bytes + 0x1B8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX512TO1023OCT_GB + MMC Number of good and bad frames received with length between 512 and 1023 bytes + 0x1BC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX1024MAXOCT_GB + MMC Number of good and bad frames received with length between 1024 and max size bytes + 0x1C0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXUCASTFRAMES_G + MMC Number of received good unicast frames + 0x1C4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXLENGTHERROR + MMC Number of frames received with length error + 0x1C8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOUTRANGETYPE + MMC Number of frames received with length field not equal to the valid frame size + 0x1CC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXPAUSEFRAMES + MMC Number of good and valid Pause frames received + 0x1D0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXFIFOOVERFLOW + MMC Number of missed received frames because of FIFO overflow + 0x1D4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXVLANFRAMES_GB + MMC Number of good and bad VLAN frames received + 0x1D8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXWDOGERROR + MMC Number of frames received with error because of watchdog timeout error + 0x1DC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXRCVERROR + MMC Number of frames received with Receive error or Frame Extension error + 0x1E0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXCTRLFRAMES_G + MMC Number of received good control frames + 0x1E4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + VLAN_INCREPLACE + Holds the VLAN Tag for insertion into or replacement in the transmit frames + 0x584 + read-write + 0x00000000 + + + CSVL + C-VLAN or S-VLAN + [19:19] + + + VLP + VLAN Priority Control + [18:18] + + + VLC + VLAN Tag Control in Transmit Frames + [17:16] + + + VLT + VLAN Tag for Transmit Frames + [15:0] + + + + + VLAN_HASHTABLE + Holds the VLAN Hash Table + 0x588 + read-write + 0x00000000 + + + VLHT + VLAN Hash Table + [15:0] + + + + + TIMESTAMP_CTRL + Controls the IEEE 1588 timestamp generation and update logic + 0x700 + read-write + 0x00000000 + + + ATSEN3 + Auxiliary Snapshot 3 Enable + [28:28] + + + ATSEN2 + Auxiliary Snapshot 2 Enable + [27:27] + + + ATSEN1 + Auxiliary Snapshot 1 Enable + [26:26] + + + ATSEN0 + Auxiliary Snapshot 0 Enable + [25:25] + + + ATSFC + Auxiliary Snapshot FIFO Clear + [24:24] + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering + [18:18] + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + [17:16] + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master + [15:15] + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages + [14:14] + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + [13:13] + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP + [12:12] + + + TSIPENA + Enable Processing of PTP over Ethernet Frames + [11:11] + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format + [10:10] + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control + [9:9] + + + TSENALL + Enable Timestamp for All Frames + [8:8] + + + TSADDRREG + Addend Reg Update + [5:5] + + + TSTRIG + Timestamp Interrupt Trigger Enable + [4:4] + + + TSUPDT + Timestamp Update + [3:3] + + + TSINIT + Timestamp Initialize + [2:2] + + + TSCFUPDT + Timestamp Fine or Coarse Update + [1:1] + + + TSENA + Timestamp Enable + [0:0] + + + + + SUBSEC_INC + Holds the 8-bit value by which the Sub-Second register is incremented + 0x704 + read-write + 0x00000000 + + + SSINC + Sub-Second Increment Valuee + [7:0] + + + + + SYSTIME_SECONDS + Holds the lower 32 bits of the second field of the system time + 0x708 + read-only + 0x00000000 + + + TSS + Timestamp Second + [31:0] + + + + + SYSTIME_NANOSEC + Holds 32 bits of the nano-second field of the system time + 0x70C + read-only + 0x00000000 + + + TSSS + Timestamp Sub Seconds + [30:0] + + + + + SYSTIME_SECSUPDAT + Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value + 0x710 + read-write + 0x00000000 + + + TSS + Timestamp Second + [31:0] + + + + + SYSTIME_NSECUP + Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value + 0x714 + read-write + 0x00000000 + + + ADDSUB + Add or Subtract Time + [31:31] + + + TSSS + Timestamp Sub Seconds + [30:0] + + + + + TIMESTAMPADDEND + This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency + 0x718 + read-write + 0x00000000 + + + TSAR + Timestamp Addend Register + [31:0] + + + + + TARGET_TIME_SECS + Holds the high 32-bits of time to be compared with the system time + 0x71C + read-write + 0x00000000 + + + TSTR + Target Time Seconds Registe + [31:0] + + + + + TARGET_TIME_NSEC + Holds the lower 32-bits of time to be compared with the system time + 0x720 + read-write + 0x00000000 + + + TRGTBUSY + 32 Bits of Hash Table + [31:31] + + + TTSLO + Target Timestamp Low Register + [30:0] + + + + + DMA_BUS_MODE + Controls the DMA Host Interface Mode + 0x1000 + read-write + 0x00020101 + + + RIB + Rebuild INCRx Burst + [31:31] + + + PRWG + Channel Priority Weights + [29:28] + + + TXPR + Transmit Priority + [27:27] + + + MB + Mixed Burst + [26:26] + + + AAL + Address-Aligned Beats + [25:25] + + + PBLx8 + PBLx8 Mode + [24:24] + + + USP + Use Separate PBL + [23:23] + + + RPBL + Rx DMA PBL + [22:17] + + + FB + Fixed Burste + [16:16] + + + PR + Priority Ratio + [15:14] + + + PBL + Programmable Burst Lengthe + [13:8] + + + DSL + Descriptor Skip Length + [6:2] + + + DA + DMA Arbitration Scheme + [1:1] + + + SWR + Software Reset (Read, Write Set, and Self Clear) + [0:0] + + + + + DMA_TX_POLL_DEMAND + Used by the host to instruct the DMA to poll the transmit Descriptor list + 0x1004 + read-write + 0x00000000 + + + TPD + Transmit Poll Demand (Read Only and Write Trigger) + [31:0] + + + + + DMA_RX_POLL_DEMAND + Used by the host to instruct the DMA to poll the Receive Descriptor list + 0x1008 + read-write + 0x00000000 + + + RPD + Receive Poll Demand (Read Only and Write Trigger) + [31:0] + + + + + DMA_RX_DESC_LIST_ADDR + Points the DMA to the start of the Receive Descriptor list + 0x100C + read-write + 0x00000000 + + + RDESLA + Start of Receive List + [31:0] + + + + + DMA_TX_DESC_LIST_ADDR + Points the DMA to the start of the Transmit Descriptor list + 0x1010 + read-write + 0x00000000 + + + TDESLA + Start of Transmit List + [31:0] + + + + + DMA_STATUS + Used to determine the status of the DMA + 0x1014 + read-only + 0x00000000 + + + TTI + Timestamp Trigger Interrupt + [29:29] + + + GMI + GMAC MMC Interrupt + [27:27] + + + EB + Error Bits + [25:23] + + + TS + Transmit Process State + [22:20] + + + RS + Receive Process State + [19:17] + + + NIS + Normal Interrupt Summary + [16:16] + + + AIS + Abnormal Interrupt Summary + [15:15] + + + ERI + Early Receive Interrupt + [14:14] + + + FBI + Fatal Bus Error Interruptble + [13:13] + + + ETI + Early Transmit Interrupt + [10:10] + + + RWT + Receive Watchdog Timeout + [9:9] + + + RPS + Receive Process Stopped + [8:8] + + + RU + Receive Buffer Unavailable + [7:7] + + + RI + Receive Interrupt + [6:6] + + + UNF + Transmit Underflow + [5:5] + + + OVF + Receive Underflow + [4:4] + + + TJT + Transmit Jabber Timeout + [3:3] + + + TU + Transmit Buffer Unavailable + [2:2] + + + TPS + Transmit Process Stopped + [1:1] + + + TI + Transmit Interrupt + [0:0] + + + + + DMA_OPER_MODE + Sets the Receive and Transmit operation mode and command + 0x1018 + read-write + 0x00000000 + + + DT + Disable Dropping of TCP/IP Checksum Error Frames + [26:26] + + + RSF + Receive Store and Forward + [25:25] + + + DFF + Disable Flushing of Received Frames + [24:24] + + + TSF + Transmit Store and Forward + [21:21] + + + FTF + Flush Transmit FIFO + [20:20] + + + TTC + Transmit Threshold Control + [16:14] + + + ST + Start or Stop Transmission Command + [13:13] + + + RFD + Threshold for Deactivating Flow Control + [12:11] + + + RFA + Threshold for Activating Flow Control + [10:9] + + + FEF + Forward Error Frames + [7:7] + + + FUF + Forward Undersized Good Frames + [6:6] + + + DGF + Drop Giant Frames + [5:5] + + + RTC + Receive Threshold Control + [4:3] + + + OSF + Operate on Second Frame + [2:2] + + + SR + Start or Stop Receive + [1:1] + + + + + DMA_INTR_EN + Enables the interrupts reported in the status register + 0x101C + read-write + 0x00000000 + + + NIE + Normal Interrupt Summary Enable + [16:16] + + + AIE + Abnormal Interrupt Summary Enable + [15:15] + + + ERE + Early Receive Interrupt Enable + [14:14] + + + FBE + Fatal Bus Error Enable + [13:13] + + + ETE + Early Transmit Interrupt Enable + [10:10] + + + RWE + Receive Watchdog Timeout Enable + [9:9] + + + RSE + Receive Stopped Enable + [8:8] + + + RUE + Receive Buffer Unavailable Enable + [7:7] + + + RIE + Receive Interrupt Enable + [6:6] + + + UNE + Underflow Interrupt Enable + [5:5] + + + OVE + Overflow Interrupt Enable + [4:4] + + + THE + Transmit Jabber Timeout Enable + [3:3] + + + TUE + Transmit Buffer Unavailable Enable + [2:2] + + + TSE + Transmit Stopped Enable + [1:1] + + + TIE + Transmit Interrupt Enable + [0:0] + + + + + DMA_MISS_OVER_COUNTER + Contains the counters for discarded frames because no Receive Descriptor is available + 0x1020 + read-write + 0x00000000 + + + OVFCNTOVF + This bit is set every time the Overflow Frame Counter (Bits[27:17])overflows + [28:28] + + + OVFFRMCNT + This field indicates the number of frames missed by the application + [27:17] + + + MISCNTOVF + This bit is set every time Missed Frame Counter (Bits[15:0]) overflows + [16:16] + + + MISFRMCNT + This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. + [15:0] + + + + + DMA_RX_INTR_WDOG_TIMER + Watchdog timeout for Receive Interrupt from DMA + 0x1024 + read-write + 0x00000000 + + + RIWT + These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set. + [7:0] + + + + + DMA_AHB_STATUS + Provides the active status of the read and write channels of the AHB master interface + 0x102C + read-write + 0x00000000 + + + AHBMASTRSTS + When high, indicates that the AHB master interface FSMs are in the non-idle state + [0:0] + + + + + DMA_CURR_TX_DESC + Contains the start address of the current Transmit Descriptor read by the DMA + 0x1048 + read-write + 0x00000000 + + + CURTDESAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_RX_DESC + Contains the start address of the current Receive Descriptor read by the DMA + 0x104C + read-write + 0x00000000 + + + CURRDESAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_TX_BUFR_ADDR + Contains the start address of the current Receive Descriptor read by the DMA + 0x1050 + read-write + 0x00000000 + + + CURTBUFAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_RX_BUFR_ADDR + Contains the current Receive Buffer address read by the DMA + 0x1054 + read-write + 0x00000000 + + + CURTBUFAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + + + \ No newline at end of file diff --git a/va416xx/vorago-peb1/.gitignore b/va416xx/vorago-peb1/.gitignore new file mode 100644 index 0000000..962b190 --- /dev/null +++ b/va416xx/vorago-peb1/.gitignore @@ -0,0 +1,4 @@ +/target +Cargo.lock + +/.cargo/config.toml diff --git a/va416xx/vorago-peb1/CHANGELOG.md b/va416xx/vorago-peb1/CHANGELOG.md new file mode 100644 index 0000000..a5418bd --- /dev/null +++ b/va416xx/vorago-peb1/CHANGELOG.md @@ -0,0 +1,31 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +# [unreleased] + +# [v0.1.3] 2025-09-03 + +- Bump HAL version to v0.6 + +# [v0.1.2] 2025-03-07 + +- Bump allowed HAL version to v0.5 + +# [v0.1.1] 2025-02-18 + +- Bump allowed HAL version to v0.4 + +# [v0.1.0] 2024-10-01 + +- Initial release + +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.3...HEAD +[v0.1.3]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.2...vorago-peb1-v0.1.3 +[v0.1.2]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.1...vorago-peb1-v0.1.2 +[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.0...vorago-peb1-v0.1.1 +[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/tag/vorago-peb1-v0.1.0 diff --git a/va416xx/vorago-peb1/Cargo.toml b/va416xx/vorago-peb1/Cargo.toml new file mode 100644 index 0000000..ed61e93 --- /dev/null +++ b/va416xx/vorago-peb1/Cargo.toml @@ -0,0 +1,21 @@ +[package] +name = "vorago-peb1" +version = "0.1.3" +authors = ["Robin Mueller "] +edition = "2021" +description = "Board Support Crate for the Vorago PEB1 development board" +homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-peb1" +repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-peb1" +license = "Apache-2.0" +keywords = ["no-std", "peb1", "cortex-m", "vorago", "va416xx"] +categories = ["embedded", "no-std", "hardware-support"] + +[dependencies] +va416xx-hal = { version = "0.6", path = "../va416xx-hal", features = ["va41630"] } +lis2dh12 = { version = "0.7", features = ["out_f32"] } + +[features] + +[package.metadata.docs.rs] +all-features = true +rustdoc-args = ["--generate-link-to-definition"] diff --git a/va416xx/vorago-peb1/LICENSE-APACHE b/va416xx/vorago-peb1/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va416xx/vorago-peb1/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va416xx/vorago-peb1/NOTICE b/va416xx/vorago-peb1/NOTICE new file mode 100644 index 0000000..c95b309 --- /dev/null +++ b/va416xx/vorago-peb1/NOTICE @@ -0,0 +1,3 @@ +Rust Board Support Package (BSP) crate for the Vorago PEB1 development board + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va416xx/vorago-peb1/README.md b/va416xx/vorago-peb1/README.md new file mode 100644 index 0000000..591201c --- /dev/null +++ b/va416xx/vorago-peb1/README.md @@ -0,0 +1,17 @@ +[![Crates.io](https://img.shields.io/crates/v/vorago-peb1)](https://crates.io/crates/vorago-peb1) +[![docs.rs](https://img.shields.io/docsrs/vorago-peb1)](https://docs.rs/vorago-peb1) + +# Rust BSP for the Vorago PEB1 development board + +This is the Rust **B**oard **S**upport **P**ackage crate for the Vorago PEB1 development board. +Its aim is to provide drivers for the board features of the PEB1 board. + +The BSP builds on top of the [HAL crate for VA416xx devices](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-hal). + +## Notes on board revisions + +On RevA, issuing the `monitor reset` command in the GDB application is problematic and will prevent +the flashed binary from working properly. On board revision B, this was not an issue. +For that reason, two different `*.gdb` files were provided in the `jlink` folder for each +board revision. If you are not using these files, make sure to correctly configure your flash +tools depending on which tool or board your are using. diff --git a/va416xx/vorago-peb1/jlink-gdb.sh b/va416xx/vorago-peb1/jlink-gdb.sh new file mode 100755 index 0000000..65e187f --- /dev/null +++ b/va416xx/vorago-peb1/jlink-gdb.sh @@ -0,0 +1,5 @@ +#!/bin/bash +# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary +# to disable ROM protection to allow flashing +JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript diff --git a/va416xx/vorago-peb1/jlink/JLinkSettings.JLinkScript b/va416xx/vorago-peb1/jlink/JLinkSettings.JLinkScript new file mode 100644 index 0000000..59cff80 --- /dev/null +++ b/va416xx/vorago-peb1/jlink/JLinkSettings.JLinkScript @@ -0,0 +1,77 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 1995 - 2018 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +---------------------------------------------------------------------- +File : JLinkSettings.JLinkScript +Purpose : J-Link target setup file for VORAGO VA416xx +---------------------------END-OF-HEADER------------------------------ +*/ + +int DisableRomProt(void) { + JLINK_SYS_Report("VA416XX: Disabling ROM protection"); + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +int DisableWatchdog(void) { + JLINK_MEM_WriteU32(0x400210C0, 0x1ACCE551); // WDOGLOCK = 0x1ACCE551 + JLINK_MEM_WriteU32(0x40021008, 0x0); // WDOGCONTROL = 0x0 (diable) +} + +int SetupTarget (void) { + JLINK_SYS_Report("SetupTarget()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterResetTarget +*/ +int AfterResetTarget (void) { + JLINK_SYS_Report("AfterResetTarget()"); + // disable watchdog and unlock code RAM for write + DisableWatchdog(); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* BeforeTargetDownload +*/ +int BeforeTargetDownload (void) { + JLINK_SYS_Report("BeforeTargetDownload()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterTargetDownload +*/ +int AfterTargetDownload (void) { + JLINK_SYS_Report("AfterTargetDownload()"); + return DisableRomProt(); // ROM_PROT = 0x0 +} + +/********************************************************************* +* +* HandleBeforeFlashProg +*/ +int HandleBeforeFlashProg(void) { + JLINK_SYS_Report("HandleBeforeFlashProg()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* HandleAfterFlashProg +*/ +int HandleAfterFlashProg(void) { + JLINK_SYS_Report("HandleAfterFlashProg()"); + return DisableRomProt(); // ROM_PROT = 0x0 +} \ No newline at end of file diff --git a/va416xx/vorago-peb1/jlink/jlink-reva.gdb b/va416xx/vorago-peb1/jlink/jlink-reva.gdb new file mode 100644 index 0000000..8712a8e --- /dev/null +++ b/va416xx/vorago-peb1/jlink/jlink-reva.gdb @@ -0,0 +1,13 @@ +target remote localhost:2331 + +# For some reason, this is problematic even if the JLinkScript disabled the remote +# write protection. Therefore, don't do it for now +# This is only problematic on board RevA +# monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va416xx/vorago-peb1/jlink/jlink.gdb b/va416xx/vorago-peb1/jlink/jlink.gdb new file mode 100644 index 0000000..615efdc --- /dev/null +++ b/va416xx/vorago-peb1/jlink/jlink.gdb @@ -0,0 +1,11 @@ +target remote localhost:2331 + +# Reset is problematic on RevA, okay for RevB +monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va416xx/vorago-peb1/memory.x b/va416xx/vorago-peb1/memory.x new file mode 100644 index 0000000..b9011d5 --- /dev/null +++ b/va416xx/vorago-peb1/memory.x @@ -0,0 +1,14 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 256K + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/va416xx/vorago-peb1/src/lib.rs b/va416xx/vorago-peb1/src/lib.rs new file mode 100644 index 0000000..7e9f403 --- /dev/null +++ b/va416xx/vorago-peb1/src/lib.rs @@ -0,0 +1,53 @@ +//! Board support crate for the VORAGO PEB1 board. +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] + +pub use lis2dh12; + +/// Support for the LIS2DH12 accelerometer on the GPIO board. +/// +/// # Example +/// +/// - [PEB1 Accelerometer](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/peb1-accelerometer.rs) +pub mod accelerometer { + + use lis2dh12::{self, detect_i2c_addr, AddrDetectionError, Lis2dh12}; + use va416xx_hal::{ + clock::Clocks, + i2c::{self, ClockTooSlowForFastI2cError, I2cMaster, I2cSpeed, MasterConfig}, + pac, + }; + + // Accelerometer located on the GPIO board. + pub type Accelerometer = Lis2dh12; + + #[derive(Debug)] + pub enum ConstructorError { + ClkError(ClockTooSlowForFastI2cError), + AddrDetectionError(AddrDetectionError), + AccelerometerError(lis2dh12::Error), + } + + pub fn new_with_addr_detection( + i2c: pac::I2c0, + clocks: &Clocks, + ) -> Result { + let mut i2c_master = I2cMaster::new( + i2c, + clocks, + MasterConfig::default(), + I2cSpeed::Regular100khz, + ) + .map_err(ConstructorError::ClkError)?; + let slave_addr = + detect_i2c_addr(&mut i2c_master).map_err(ConstructorError::AddrDetectionError)?; + Lis2dh12::new(i2c_master, slave_addr).map_err(ConstructorError::AccelerometerError) + } + + pub fn new_with_i2cm( + i2c: I2cMaster, + addr: lis2dh12::SlaveAddr, + ) -> Result> { + Lis2dh12::new(i2c, addr) + } +} diff --git a/va416xx/vscode/.cortex-debug.peripherals.state.json b/va416xx/vscode/.cortex-debug.peripherals.state.json new file mode 100644 index 0000000..0637a08 --- /dev/null +++ b/va416xx/vscode/.cortex-debug.peripherals.state.json @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/va416xx/vscode/.cortex-debug.registers.state.json b/va416xx/vscode/.cortex-debug.registers.state.json new file mode 100644 index 0000000..0637a08 --- /dev/null +++ b/va416xx/vscode/.cortex-debug.registers.state.json @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/va416xx/vscode/extensions.json b/va416xx/vscode/extensions.json new file mode 100644 index 0000000..d2cfd28 --- /dev/null +++ b/va416xx/vscode/extensions.json @@ -0,0 +1,12 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=827846 to learn about workspace recommendations. + // Extension identifier format: ${publisher}.${name}. Example: vscode.csharp + // List of extensions which should be recommended for users of this workspace. + "recommendations": [ + "rust-lang.rust", + "marus25.cortex-debug" + // "probe-rs.probe-rs-debugger" + ], + // List of extensions recommended by VS Code that should not be recommended for users of this workspace. + "unwantedRecommendations": [] +} \ No newline at end of file diff --git a/va416xx/vscode/launch.json b/va416xx/vscode/launch.json new file mode 100644 index 0000000..3ca187b --- /dev/null +++ b/va416xx/vscode/launch.json @@ -0,0 +1,594 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "preLaunchTask": "blinky-example", + "type": "probe-rs-debug", + "request": "launch", + "name": "probe-rs Debug Blinky", + "flashingConfig": { + "flashingEnabled": true, + "haltAfterReset": true + }, + "chip": "VA416xx", + "coreConfigs": [ + { + "programBinary": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/blinky", + "rttEnabled": true, + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched" + } + ] + }, + { + "preLaunchTask": "rtt-log-example", + "type": "probe-rs-debug", + "request": "launch", + "name": "probe-rs Debug RTT", + "flashingConfig": { + "flashingEnabled": true, + "haltAfterReset": false + }, + "chip": "VA416xx", + "coreConfigs": [ + { + "programBinary": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/rtt-log", + "rttEnabled": true, + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched" + } + ] + }, + { + "preLaunchTask": "rtt-log-example", + "type": "probe-rs-debug", + "request": "attach", + "name": "probe-rs Attach RTT", + "chip": "VA416xx", + "coreConfigs": [ + { + "programBinary": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/rtt-log", + "rttEnabled": true, + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd" + } + ] + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug LED Blinky", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "blinky-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/blinky", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug RTT Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "rtt-log-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/rtt-log", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug UART Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "uart-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/uart", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug WDT Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "wdt-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/wdt", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug SPI Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "spi-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/spi", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug Timer/Ticks Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "timer-ticks-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/timer-ticks", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug DAC/ADC Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "dac-adc-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/dac-adc", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug ADC Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "adc-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/adc", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug PWM Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "pwm-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/pwm", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug DMA Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "dma-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/dma", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "UART Line Terminated Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "uart-echo-with-irq", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/uart-echo-with-irq", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Bootloader", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "bootloader", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/bootloader", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Flashloader", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "flashloader", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/flashloader", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Embassy Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "embassy-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/embassy-example", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "RTIC Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "embassy-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/rtic-example", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Async GPIO Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "async-gpio", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/async-gpio", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Async UART TX Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "async-uart-tx", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/async-uart-tx", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Async UART RX Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "async-uart-rx", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/async-uart-rx", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + "address": "auto", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + ] +} \ No newline at end of file diff --git a/va416xx/vscode/settings.json b/va416xx/vscode/settings.json new file mode 100644 index 0000000..e78c4ec --- /dev/null +++ b/va416xx/vscode/settings.json @@ -0,0 +1,3 @@ +{ + "cortex-debug.gdbPath.linux": "gdb-multiarch" +} diff --git a/va416xx/vscode/tasks.json b/va416xx/vscode/tasks.json new file mode 100644 index 0000000..7e7bc7f --- /dev/null +++ b/va416xx/vscode/tasks.json @@ -0,0 +1,255 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "bootloader", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "bootloader" + ], + "group": { + "kind": "build", + } + }, + { + "label": "flashloader", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "flashloader" + ], + "group": { + "kind": "build", + } + }, + { + "label": "blinky-pac-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "blinky-pac" + ], + "group": { + "kind": "build", + } + }, + { + "label": "rtt-log-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "rtt-log" + ], + "group": { + "kind": "build", + } + }, + { + "label": "timer-ticks-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "timer-ticks" + ], + "group": { + "kind": "build", + } + }, + { + "label": "blinky-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "blinky" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "uart-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "uart" + ], + "group": { + "kind": "build", + } + }, + { + "label": "uart-echo-with-irq", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "uart-echo-with-irq" + ], + "group": { + "kind": "build", + } + }, + { + "label": "pwm-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "pwm" + ], + "group": { + "kind": "build", + } + }, + { + "label": "wdt-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "wdt" + ], + "group": { + "kind": "build", + } + }, + { + "label": "spi-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "spi" + ], + "group": { + "kind": "build", + } + }, + { + "label": "dac-adc-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "dac-adc" + ], + "group": { + "kind": "build", + } + }, + { + "label": "adc-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "adc" + ], + "group": { + "kind": "build", + } + }, + { + "label": "dma-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "dma" + ], + "group": { + "kind": "build", + } + }, + { + "label": "embassy-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "embassy-example" + ], + "group": { + "kind": "build", + } + }, + { + "label": "async-gpio", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "async-gpio" + ], + "group": { + "kind": "build", + } + }, + { + "label": "rtic-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "rtic-example" + ], + "group": { + "kind": "build", + } + }, + { + "label": "async-uart-tx", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "async-uart-tx" + ], + "group": { + "kind": "build", + } + }, + { + "label": "async-uart-rx", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--bin", + "async-uart-rx" + ], + "group": { + "kind": "build", + } + }, + ] +} \ No newline at end of file diff --git a/vorago-shared-hal/.cargo/.gitignore b/vorago-shared-hal/.cargo/.gitignore new file mode 100644 index 0000000..5b6c096 --- /dev/null +++ b/vorago-shared-hal/.cargo/.gitignore @@ -0,0 +1 @@ +config.toml diff --git a/vorago-shared-hal/.cargo/def-config.toml b/vorago-shared-hal/.cargo/def-config.toml new file mode 100644 index 0000000..a075fc5 --- /dev/null +++ b/vorago-shared-hal/.cargo/def-config.toml @@ -0,0 +1,41 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# uncomment ONE of these three option to make `cargo run` start a GDB session +# which option to pick depends on your system +# runner = "arm-none-eabi-gdb -q -x openocd.gdb" +# runner = "gdb-multiarch -q -x openocd.gdb" +# runner = "gdb -q -x openocd.gdb" +# runner = "gdb-multiarch -q -x jlink.gdb" + +runner = "probe-rs run --chip VA108xx_RAM --protocol jtag" +# runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format", "{L} {s}"] + +rustflags = [ + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", + + # LLD (shipped with the Rust toolchain) is used as the default linker + "-C", "link-arg=-Tlink.x", + + # knurling-rs tooling. If you want to use flip-link, ensure it is installed first. + "-C", "linker=flip-link", + # Unfortunately, defmt is clunky to use without probe-rs.. + "-C", "link-arg=-Tdefmt.x", + + # Can be useful for debugging. + # "-Clink-args=-Map=app.map" +] + +[build] +# Pick ONE of these compilation targets +target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ for VA108xx +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) for VA416xx + +[alias] +re = "run --example" +rb = "run --bin" +rrb = "run --release --bin" +ut = "test --target x86_64-unknown-linux-gnu" + +[env] +DEFMT_LOG = "info" diff --git a/vorago-shared-hal/.gitignore b/vorago-shared-hal/.gitignore new file mode 100644 index 0000000..d5a7660 --- /dev/null +++ b/vorago-shared-hal/.gitignore @@ -0,0 +1,22 @@ +# Generated by Cargo +# will have compiled files and executables +/target/ +# Keep config.toml configurable. +.cargo/config.toml + +# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries +# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html +Cargo.lock + +/app.map + +# These are backup files generated by rustfmt +**/*.rs.bk + +/.vscode + +# JetBrains IDEs +/.idea +*.iml + +/Embed.toml diff --git a/vorago-shared-hal/CHANGELOG.md b/vorago-shared-hal/CHANGELOG.md new file mode 100644 index 0000000..432a211 --- /dev/null +++ b/vorago-shared-hal/CHANGELOG.md @@ -0,0 +1,33 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +## [unreleased] + +## [v0.2.0] 2025-09-03 + +Renamed to `vorago-shared-hal` + +### Changed + +- Various renaming to be more in-line with common Embedded Rust naming conventions. + - `PinId` -> `DynPinId` + - `PinIdProvider` -> `PinId` + - `FunSel` -> `FunctionSelect` + - `PinMarker` -> `AnyPin` + - Peripheral traits renamed from `*Marker` to `*Instance` + - `Clk` abbreviation in names changed to `Clock` + - `Cmd` abbreviation in names changed to `Command` + - `Irq` abbreviation in names changed to `Interrupt` + +## [v0.1.0] 2025-09-02 + +Init commit. + +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.2.0...HEAD +[v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.1.0...v0.2.0 +[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/src/tag/v0.1.0 diff --git a/vorago-shared-hal/Cargo.toml b/vorago-shared-hal/Cargo.toml new file mode 100644 index 0000000..360f33d --- /dev/null +++ b/vorago-shared-hal/Cargo.toml @@ -0,0 +1,65 @@ +[package] +name = "vorago-shared-hal" +version = "0.2.0" +description = "Peripheral HAL components shared between Vorago families" +edition = "2024" +homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs" +repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs" +license = "Apache-2.0" + +[dependencies] +cortex-m = { version = "0.7" } +cfg-if = "1" +derive-mmio = "0.6" +bitbybit = "1.3" +arbitrary-int = "2" +static_assertions = "1.1" +nb = "1" +heapless = "0.9" +critical-section = "1" +embedded-hal = "1.0" +embedded-hal-async = "1" +embedded-hal-nb = "1" +embedded-io = "0.6" +embedded-io-async = "0.6" +raw-slicee = "0.1" +thiserror = { version = "2", default-features = false } +paste = "1" +fugit = "0.3" +defmt = { version = "1", optional = true } +va108xx = { version = "0.6", default-features = false, optional = true } +va416xx = { version = ">=0.4, <=0.5", default-features = false, optional = true } +embassy-sync = "0.7" +embassy-time-driver = "0.2" +embassy-time-queue-utils = "0.3" +once_cell = { version = "1", default-features = false, features = [ + "critical-section", +] } + +[target.thumbv6m-none-eabi.dependencies] +portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] } +[target.thumbv7em-none-eabihf.dependencies] +portable-atomic = "1" +[target.'cfg(not(any(target_arch = "arm", target_os = "none")))'.dependencies] +portable-atomic = "1" + +[features] +vor1x = ["_family-selected", "dep:va108xx"] +vor4x = ["_family-selected", "dep:va416xx"] +va41628 = [] +defmt = [ + "dep:defmt", + "arbitrary-int/defmt", + "fugit/defmt", + "embedded-hal/defmt-03", + "va108xx/defmt" +] + +_family-selected = [] + +[package.metadata.cargo-machete] +ignored = ["raw-slicee"] + +[package.metadata.docs.rs] +features = ["vor1x", "defmt"] +rustdoc-args = ["--generate-link-to-definition"] diff --git a/vorago-shared-hal/LICENSE-APACHE b/vorago-shared-hal/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/vorago-shared-hal/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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Instead, use the re-exported modules of the repective +[VA108xx HAL](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/va108xx-hal) and +[VA416xx HAL](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs). + +## Check / Build for VA1XXX family + +```sh +cargo check --features "vor1x, defmt" +``` + +## Check / Build for VA4XXX family + +```sh +cargo check --features "vor4x, defmt" +``` diff --git a/vorago-shared-hal/src/clock.rs b/vorago-shared-hal/src/clock.rs new file mode 100644 index 0000000..c8d5ab9 --- /dev/null +++ b/vorago-shared-hal/src/clock.rs @@ -0,0 +1,62 @@ +use crate::time::Hertz; + +pub const HBO_FREQ: Hertz = Hertz::from_raw(20_000_000); + +/// Frozen clock frequencies +/// +/// The existence of this value indicates that the clock configuration can no longer be changed. +/// The [self] module documentation gives some more information on how to retrieve an instance +/// of this structure. +#[derive(Copy, Clone, PartialEq, Eq, Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct Clocks { + sysclk: Hertz, + apb1: Hertz, + apb2: Hertz, + #[cfg(not(feature = "va41628"))] + adc_clk: Hertz, +} + +impl Clocks { + #[doc(hidden)] + pub fn __new(final_sysclk: Hertz, #[cfg(not(feature = "va41628"))] adc_clk: Hertz) -> Self { + Self { + sysclk: final_sysclk, + apb1: final_sysclk / 2, + apb2: final_sysclk / 4, + #[cfg(not(feature = "va41628"))] + adc_clk, + } + } + + /// Returns the frequency of the HBO clock + pub const fn hbo(&self) -> Hertz { + HBO_FREQ + } + + /// Returns the frequency of the APB0 which is equal to the system clock. + pub const fn apb0(&self) -> Hertz { + self.sysclk() + } + + /// Returns system clock divied by 2. + pub const fn apb1(&self) -> Hertz { + self.apb1 + } + + /// Returns system clock divied by 4. + pub const fn apb2(&self) -> Hertz { + self.apb2 + } + + /// Returns the system (core) frequency + pub const fn sysclk(&self) -> Hertz { + self.sysclk + } + + /// Returns the ADC clock frequency which has a separate divider. + #[cfg(not(feature = "va41628"))] + pub const fn adc_clk(&self) -> Hertz { + self.adc_clk + } +} diff --git a/vorago-shared-hal/src/embassy.rs b/vorago-shared-hal/src/embassy.rs new file mode 100644 index 0000000..d948691 --- /dev/null +++ b/vorago-shared-hal/src/embassy.rs @@ -0,0 +1,340 @@ +use core::cell::{Cell, RefCell}; + +use crate::{ + enable_nvic_interrupt, + timer::{ + TimId, TimInstance, assert_tim_reset_for_cycles, enable_tim_clk, + regs::{EnableControl, MmioTimer}, + }, +}; +use critical_section::{CriticalSection, Mutex}; +use embassy_time_driver::TICK_HZ; +use embassy_time_driver::{Driver, time_driver_impl}; +use embassy_time_queue_utils::Queue; +use once_cell::sync::OnceCell; +use portable_atomic::{AtomicU32, Ordering}; + +#[cfg(feature = "vor1x")] +use crate::time::Hertz; +#[cfg(feature = "vor1x")] +use crate::{PeripheralSelect, enable_peripheral_clock}; + +time_driver_impl!( + static TIME_DRIVER: TimerDriver = TimerDriver { + periods: AtomicU32::new(0), + alarms: Mutex::new(AlarmState::new()), + queue: Mutex::new(RefCell::new(Queue::new())), +}); + +/// Expose the time driver so the user can specify the IRQ handlers themselves. +pub fn time_driver() -> &'static TimerDriver { + &TIME_DRIVER +} + +struct AlarmState { + timestamp: Cell, +} + +impl AlarmState { + const fn new() -> Self { + Self { + timestamp: Cell::new(u64::MAX), + } + } +} + +unsafe impl Send for AlarmState {} + +static SCALE: OnceCell = OnceCell::new(); +static TIMEKEEPER_TIM: OnceCell = OnceCell::new(); +static ALARM_TIM: OnceCell = OnceCell::new(); + +pub struct TimerDriver { + periods: AtomicU32, + /// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled. + alarms: Mutex, + queue: Mutex>, +} + +impl TimerDriver { + #[cfg(feature = "vor1x")] + #[doc(hidden)] + pub fn __init( + &self, + sysclk: Hertz, + _timekeeper_tim: TimekeeperTim, + _alarm_tim: AlarmTim, + timekeeper_irq: va108xx::Interrupt, + alarm_irq: va108xx::Interrupt, + ) { + if ALARM_TIM.get().is_some() || TIMEKEEPER_TIM.get().is_some() { + return; + } + ALARM_TIM.set(AlarmTim::ID).ok(); + TIMEKEEPER_TIM.set(TimekeeperTim::ID).ok(); + enable_peripheral_clock(PeripheralSelect::Irqsel); + enable_tim_clk(TimekeeperTim::ID); + assert_tim_reset_for_cycles(TimekeeperTim::ID, 2); + + let mut timekeeper_reg_block = unsafe { TimekeeperTim::ID.steal_regs() }; + let mut alarm_tim_reg_block = unsafe { AlarmTim::ID.steal_regs() }; + // Initiate scale value here. This is required to convert timer ticks back to a timestamp. + SCALE.set((sysclk.raw() / TICK_HZ as u32) as u64).unwrap(); + timekeeper_reg_block.write_reset_value(u32::MAX); + // Decrementing counter. + timekeeper_reg_block.write_count_value(u32::MAX); + let irqsel = unsafe { va108xx::Irqsel::steal() }; + // Switch on. Timekeeping should always be done. + irqsel + .tim(TimekeeperTim::ID.value() as usize) + .write(|w| unsafe { w.bits(timekeeper_irq as u32) }); + unsafe { + enable_nvic_interrupt(timekeeper_irq); + } + timekeeper_reg_block.modify_control(|mut value| { + value.set_irq_enable(true); + value + }); + timekeeper_reg_block.write_enable_control(EnableControl::new_enable()); + + enable_tim_clk(AlarmTim::ID); + assert_tim_reset_for_cycles(AlarmTim::ID, 2); + + // Explicitely disable alarm timer until needed. + alarm_tim_reg_block.modify_control(|mut value| { + value.set_irq_enable(false); + value.set_enable(false); + value + }); + // Enable general interrupts. The IRQ enable of the peripheral remains cleared. + unsafe { + enable_nvic_interrupt(alarm_irq); + } + irqsel + .tim(AlarmTim::ID.value() as usize) + .write(|w| unsafe { w.bits(alarm_irq as u32) }); + } + + #[cfg(feature = "vor4x")] + #[doc(hidden)] + pub fn __init( + &self, + _timekeeper_tim: TimekeeperTim, + _alarm_tim: AlarmTim, + clocks: &crate::clock::Clocks, + ) { + if ALARM_TIM.get().is_some() || TIMEKEEPER_TIM.get().is_some() { + return; + } + ALARM_TIM.set(AlarmTim::ID).ok(); + TIMEKEEPER_TIM.set(TimekeeperTim::ID).ok(); + let mut timekeeper_regs = unsafe { TimekeeperTim::ID.steal_regs() }; + let mut alarm_regs = unsafe { AlarmTim::ID.steal_regs() }; + + enable_tim_clk(TimekeeperTim::ID); + assert_tim_reset_for_cycles(TimekeeperTim::ID, 2); + + // Initiate scale value here. This is required to convert timer ticks back to a timestamp. + + SCALE + .set((TimekeeperTim::clock(clocks).raw() / TICK_HZ as u32) as u64) + .unwrap(); + timekeeper_regs.write_reset_value(u32::MAX); + // Decrementing counter. + timekeeper_regs.write_count_value(u32::MAX); + // Switch on. Timekeeping should always be done. + unsafe { + enable_nvic_interrupt(TimekeeperTim::IRQ); + } + timekeeper_regs.modify_control(|mut value| { + value.set_irq_enable(true); + value + }); + timekeeper_regs.write_enable_control(EnableControl::new_enable()); + + enable_tim_clk(AlarmTim::ID); + assert_tim_reset_for_cycles(AlarmTim::ID, 2); + // Explicitely disable alarm timer until needed. + alarm_regs.modify_control(|mut value| { + value.set_irq_enable(false); + value.set_enable(false); + value + }); + // Enable general interrupts. The IRQ enable of the peripheral remains cleared. + unsafe { + enable_nvic_interrupt(AlarmTim::IRQ); + } + } + + fn timekeeper_tim() -> MmioTimer<'static> { + TIMEKEEPER_TIM + .get() + .map(|tim| unsafe { tim.steal_regs() }) + .unwrap() + } + fn alarm_tim() -> MmioTimer<'static> { + ALARM_TIM + .get() + .map(|tim| unsafe { tim.steal_regs() }) + .unwrap() + } + + /// Should be called inside the IRQ of the timekeeper timer. + /// + /// # Safety + /// + /// This function has to be called once by the TIM IRQ used for the timekeeping. + pub unsafe fn on_interrupt_timekeeping(&self) { + self.next_period(); + } + + /// Should be called inside the IRQ of the alarm timer. + /// + /// # Safety + /// + ///This function has to be called once by the TIM IRQ used for the timekeeping. + pub unsafe fn on_interrupt_alarm(&self) { + critical_section::with(|cs| { + if self.alarms.borrow(cs).timestamp.get() <= self.now() { + self.trigger_alarm(cs) + } + }) + } + + fn next_period(&self) { + let period = self.periods.fetch_add(1, Ordering::AcqRel) + 1; + let t = (period as u64) << 32; + critical_section::with(|cs| { + let alarm = &self.alarms.borrow(cs); + let at = alarm.timestamp.get(); + if at < t { + self.trigger_alarm(cs); + } else { + let mut alarm_tim = Self::alarm_tim(); + + let remaining_ticks = (at - t).checked_mul(*SCALE.get().unwrap()); + if remaining_ticks.is_some_and(|v| v <= u32::MAX as u64) { + alarm_tim.write_enable_control(EnableControl::new_disable()); + alarm_tim.write_count_value(remaining_ticks.unwrap() as u32); + alarm_tim.modify_control(|mut value| { + value.set_irq_enable(true); + value + }); + alarm_tim.write_enable_control(EnableControl::new_enable()); + } + } + }) + } + + fn trigger_alarm(&self, cs: CriticalSection) { + Self::alarm_tim().modify_control(|mut value| { + value.set_irq_enable(false); + value.set_enable(false); + value + }); + + let alarm = &self.alarms.borrow(cs); + // Setting the maximum value disables the alarm. + alarm.timestamp.set(u64::MAX); + + // Call after clearing alarm, so the callback can set another alarm. + let mut next = self + .queue + .borrow(cs) + .borrow_mut() + .next_expiration(self.now()); + while !self.set_alarm(cs, next) { + next = self + .queue + .borrow(cs) + .borrow_mut() + .next_expiration(self.now()); + } + } + + fn set_alarm(&self, cs: CriticalSection, timestamp: u64) -> bool { + if SCALE.get().is_none() { + return false; + } + let mut alarm_tim = Self::alarm_tim(); + alarm_tim.modify_control(|mut value| { + value.set_irq_enable(false); + value.set_enable(false); + value + }); + + let alarm = self.alarms.borrow(cs); + alarm.timestamp.set(timestamp); + + let t = self.now(); + if timestamp <= t { + alarm.timestamp.set(u64::MAX); + return false; + } + + // If it hasn't triggered yet, setup the relevant reset value, regardless of whether + // the interrupts are enabled or not. When they are enabled at a later point, the + // right value is already set. + + // If the timestamp is in the next few ticks, add a bit of buffer to be sure the alarm + // is not missed. + // + // This means that an alarm can be delayed for up to 2 ticks (from t+1 to t+3), but this is allowed + // by the Alarm trait contract. What's not allowed is triggering alarms *before* their scheduled time, + // and we don't do that here. + let safe_timestamp = timestamp.max(t + 3); + let timer_ticks = (safe_timestamp - t).checked_mul(*SCALE.get().unwrap()); + alarm_tim.write_reset_value(u32::MAX); + if timer_ticks.is_some_and(|v| v <= u32::MAX as u64) { + alarm_tim.write_count_value(timer_ticks.unwrap() as u32); + alarm_tim.modify_control(|mut value| { + value.set_irq_enable(true); + value.set_enable(true); + value + }); + } + // If it's too far in the future, don't enable timer yet. + // It will be enabled later by `next_period`. + + true + } +} + +impl Driver for TimerDriver { + fn now(&self) -> u64 { + if SCALE.get().is_none() { + return 0; + } + let mut period1: u32; + let mut period2: u32; + let mut counter_val: u32; + + loop { + // Acquire ensures that we get the latest value of `periods` and + // no instructions can be reordered before the load. + period1 = self.periods.load(Ordering::Acquire); + + counter_val = u32::MAX - Self::timekeeper_tim().read_count_value(); + + // Double read to protect against race conditions when the counter is overflowing. + period2 = self.periods.load(Ordering::Relaxed); + if period1 == period2 { + let now = (((period1 as u64) << 32) | counter_val as u64) / *SCALE.get().unwrap(); + return now; + } + } + } + + fn schedule_wake(&self, at: u64, waker: &core::task::Waker) { + critical_section::with(|cs| { + let mut queue = self.queue.borrow(cs).borrow_mut(); + + if queue.schedule_wake(at, waker) { + let mut next = queue.next_expiration(self.now()); + while !self.set_alarm(cs, next) { + next = queue.next_expiration(self.now()); + } + } + }) + } +} diff --git a/vorago-shared-hal/src/gpio/asynch.rs b/vorago-shared-hal/src/gpio/asynch.rs new file mode 100644 index 0000000..46e349e --- /dev/null +++ b/vorago-shared-hal/src/gpio/asynch.rs @@ -0,0 +1,333 @@ +//! # Async GPIO functionality for the Vorago GPIO peripherals. +//! +//! This module provides the [InputPinAsync] which implements +//! the [embedded_hal_async::digital::Wait] trait. These types allow for asynchronous waiting +//! on GPIO pins. Please note that this module does not specify/declare the interrupt handlers +//! which must be provided for async support to work. However, it provides the +//! [on_interrupt_for_async_gpio_for_port] generic interrupt handler. This should be called in all +//! IRQ functions which handle any GPIO interrupts with the corresponding [Port] argument. +use core::future::Future; + +use embassy_sync::waitqueue::AtomicWaker; +use embedded_hal_async::digital::Wait; +use portable_atomic::AtomicBool; + +#[cfg(feature = "vor4x")] +use crate::NUM_PORT_DEFAULT; +#[cfg(feature = "vor1x")] +use crate::{InterruptConfig, NUM_PORT_A, NUM_PORT_B}; + +#[cfg(feature = "vor4x")] +use super::ll::PortDoesNotSupportInterrupts; + +#[cfg(feature = "vor1x")] +use va108xx as pac; + +pub use super::ll::InterruptEdge; +use super::{ + Input, Port, + ll::{DynPinId, LowLevelGpio}, +}; + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + static WAKERS_FOR_PORT_A: [AtomicWaker; NUM_PORT_A] = [const { AtomicWaker::new() }; NUM_PORT_A]; + static WAKERS_FOR_PORT_B: [AtomicWaker; NUM_PORT_B] = [const { AtomicWaker::new() }; NUM_PORT_B]; + static EDGE_DETECTION_PORT_A: [AtomicBool; NUM_PORT_A] = + [const { AtomicBool::new(false) }; NUM_PORT_A]; + static EDGE_DETECTION_PORT_B: [AtomicBool; NUM_PORT_B] = + [const { AtomicBool::new(false) }; NUM_PORT_B]; + } else { + static WAKERS_FOR_PORT_A: [AtomicWaker; NUM_PORT_DEFAULT] = + [const { AtomicWaker::new() }; NUM_PORT_DEFAULT]; + static WAKERS_FOR_PORT_B: [AtomicWaker; NUM_PORT_DEFAULT] = + [const { AtomicWaker::new() }; NUM_PORT_DEFAULT]; + static WAKERS_FOR_PORT_C: [AtomicWaker; NUM_PORT_DEFAULT] = + [const { AtomicWaker::new() }; NUM_PORT_DEFAULT]; + static WAKERS_FOR_PORT_D: [AtomicWaker; NUM_PORT_DEFAULT] = + [const { AtomicWaker::new() }; NUM_PORT_DEFAULT]; + static WAKERS_FOR_PORT_E: [AtomicWaker; NUM_PORT_DEFAULT] = + [const { AtomicWaker::new() }; NUM_PORT_DEFAULT]; + static WAKERS_FOR_PORT_F: [AtomicWaker; NUM_PORT_DEFAULT] = + [const { AtomicWaker::new() }; NUM_PORT_DEFAULT]; + + static EDGE_DETECTION_PORT_A: [AtomicBool; NUM_PORT_DEFAULT] = + [const { AtomicBool::new(false) }; NUM_PORT_DEFAULT]; + static EDGE_DETECTION_PORT_B: [AtomicBool; NUM_PORT_DEFAULT] = + [const { AtomicBool::new(false) }; NUM_PORT_DEFAULT]; + static EDGE_DETECTION_PORT_C: [AtomicBool; NUM_PORT_DEFAULT] = + [const { AtomicBool::new(false) }; NUM_PORT_DEFAULT]; + static EDGE_DETECTION_PORT_D: [AtomicBool; NUM_PORT_DEFAULT] = + [const { AtomicBool::new(false) }; NUM_PORT_DEFAULT]; + static EDGE_DETECTION_PORT_E: [AtomicBool; NUM_PORT_DEFAULT] = + [const { AtomicBool::new(false) }; NUM_PORT_DEFAULT]; + static EDGE_DETECTION_PORT_F: [AtomicBool; NUM_PORT_DEFAULT] = + [const { AtomicBool::new(false) }; NUM_PORT_DEFAULT]; + } +} + +#[inline] +fn pin_group_to_waker_and_edge_detection_group( + port: Port, +) -> (&'static [AtomicWaker], &'static [AtomicBool]) { + match port { + Port::A => (WAKERS_FOR_PORT_A.as_ref(), EDGE_DETECTION_PORT_A.as_ref()), + Port::B => (WAKERS_FOR_PORT_B.as_ref(), EDGE_DETECTION_PORT_B.as_ref()), + #[cfg(feature = "vor4x")] + Port::C => (WAKERS_FOR_PORT_C.as_ref(), EDGE_DETECTION_PORT_C.as_ref()), + #[cfg(feature = "vor4x")] + Port::D => (WAKERS_FOR_PORT_D.as_ref(), EDGE_DETECTION_PORT_D.as_ref()), + #[cfg(feature = "vor4x")] + Port::E => (WAKERS_FOR_PORT_E.as_ref(), EDGE_DETECTION_PORT_E.as_ref()), + #[cfg(feature = "vor4x")] + Port::F => (WAKERS_FOR_PORT_F.as_ref(), EDGE_DETECTION_PORT_F.as_ref()), + #[cfg(feature = "vor4x")] + Port::G => unreachable!(), + } +} + +/// Generic interrupt handler for GPIO interrupts on a specific port to support async functionalities +/// +/// This function should be called in all interrupt handlers which handle any GPIO interrupts +/// matching the [Port] argument. +/// The handler will wake the corresponding wakers for the pins that triggered an interrupts +/// as well as update the static edge detection structures. This allows the pin future to complete +/// complete async operations. +#[cfg(feature = "vor1x")] +pub fn on_interrupt_for_async_gpio_for_port(port: Port) { + on_interrupt_for_async_gpio_for_port_generic(port); +} +#[cfg(feature = "vor4x")] +pub fn on_interrupt_for_async_gpio_for_port( + port: Port, +) -> Result<(), PortDoesNotSupportInterrupts> { + if port == Port::G { + return Err(PortDoesNotSupportInterrupts); + } + on_interrupt_for_async_gpio_for_port_generic(port); + Ok(()) +} + +fn on_interrupt_for_async_gpio_for_port_generic(port: Port) { + let gpio = unsafe { port.steal_gpio() }; + + let irq_enb = gpio.read_irq_enable(); + let edge_status = gpio.read_edge_status(); + let (wakers, edge_detection) = pin_group_to_waker_and_edge_detection_group(port); + + on_interrupt_for_port(irq_enb, edge_status, wakers, edge_detection); +} + +#[inline] +fn on_interrupt_for_port( + mut irq_enb: u32, + edge_status: u32, + wakers: &'static [AtomicWaker], + edge_detection: &'static [AtomicBool], +) { + while irq_enb != 0 { + let bit_pos = irq_enb.trailing_zeros() as usize; + let bit_mask = 1 << bit_pos; + + wakers[bit_pos].wake(); + + if edge_status & bit_mask != 0 { + edge_detection[bit_pos].store(true, core::sync::atomic::Ordering::Relaxed); + + // Clear the processed bit + irq_enb &= !bit_mask; + } + } +} + +/// Input pin future which implements the [Future] trait. +/// +/// Generally, you want to use the [InputPinAsync] types instead of this +/// which also implements the [embedded_hal_async::digital::Wait] trait. However, access to this +/// struture is granted to allow writing custom async structures. +pub struct InputPinFuture { + id: DynPinId, + waker_group: &'static [AtomicWaker], + edge_detection_group: &'static [AtomicBool], +} + +impl InputPinFuture { + #[cfg(feature = "vor1x")] + pub fn new_with_input_pin(pin: &mut Input, irq: pac::Interrupt, edge: InterruptEdge) -> Self { + let (waker_group, edge_detection_group) = + pin_group_to_waker_and_edge_detection_group(pin.id().port()); + edge_detection_group[pin.id().offset()].store(false, core::sync::atomic::Ordering::Relaxed); + pin.configure_edge_interrupt(edge); + #[cfg(feature = "vor1x")] + pin.enable_interrupt(InterruptConfig::new(irq, true, true)); + Self { + id: pin.id(), + waker_group, + edge_detection_group, + } + } + #[cfg(feature = "vor4x")] + pub fn new_with_input_pin( + pin: &mut Input, + edge: InterruptEdge, + ) -> Result { + let (waker_group, edge_detection_group) = + pin_group_to_waker_and_edge_detection_group(pin.id().port()); + pin.configure_edge_interrupt(edge); + pin.enable_interrupt(true)?; + Ok(Self { + id: pin.id(), + waker_group, + edge_detection_group, + }) + } +} + +impl Drop for InputPinFuture { + fn drop(&mut self) { + let mut ll = LowLevelGpio::new(self.id); + #[cfg(feature = "vor1x")] + ll.disable_interrupt(false); + #[cfg(feature = "vor4x")] + ll.disable_interrupt(); + } +} + +impl Future for InputPinFuture { + type Output = (); + fn poll( + self: core::pin::Pin<&mut Self>, + cx: &mut core::task::Context<'_>, + ) -> core::task::Poll { + let idx = self.id.offset(); + self.waker_group[idx].register(cx.waker()); + if self.edge_detection_group[idx].swap(false, core::sync::atomic::Ordering::Relaxed) { + return core::task::Poll::Ready(()); + } + core::task::Poll::Pending + } +} + +pub struct InputPinAsync { + pin: Input, + #[cfg(feature = "vor1x")] + irq: va108xx::Interrupt, +} + +impl InputPinAsync { + /// Create a new asynchronous input pin from an [Input] pin. The interrupt ID to be used must be + /// passed as well and is used to route and enable the interrupt. + /// + /// Please note that the interrupt handler itself must be provided by the user and the + /// generic [on_interrupt_for_async_gpio_for_port] function must be called inside that function + /// for the asynchronous functionality to work. + #[cfg(feature = "vor1x")] + pub fn new(pin: Input, irq: va108xx::Interrupt) -> Self { + Self { pin, irq } + } + #[cfg(feature = "vor4x")] + pub fn new(pin: Input) -> Result { + if pin.id().port() == Port::G { + return Err(PortDoesNotSupportInterrupts); + } + Ok(Self { pin }) + } + + /// Asynchronously wait until the pin is high. + /// + /// This returns immediately if the pin is already high. + pub async fn wait_for_high(&mut self) { + // Unwrap okay, checked pin in constructor. + #[cfg(feature = "vor1x")] + let fut = + InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::LowToHigh); + #[cfg(feature = "vor4x")] + let fut = + InputPinFuture::new_with_input_pin(&mut self.pin, InterruptEdge::LowToHigh).unwrap(); + if self.pin.is_high() { + return; + } + fut.await; + } + + /// Asynchronously wait until the pin is low. + /// + /// This returns immediately if the pin is already high. + pub async fn wait_for_low(&mut self) { + // Unwrap okay, checked pin in constructor. + #[cfg(feature = "vor1x")] + let fut = + InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::HighToLow); + #[cfg(feature = "vor4x")] + let fut = + InputPinFuture::new_with_input_pin(&mut self.pin, InterruptEdge::HighToLow).unwrap(); + if self.pin.is_low() { + return; + } + fut.await; + } + + /// Asynchronously wait until the pin sees a falling edge. + pub async fn wait_for_falling_edge(&mut self) { + // Unwrap okay, checked pin in constructor. + #[cfg(feature = "vor1x")] + InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::HighToLow).await; + #[cfg(feature = "vor4x")] + InputPinFuture::new_with_input_pin(&mut self.pin, InterruptEdge::HighToLow) + .unwrap() + .await; + } + + /// Asynchronously wait until the pin sees a rising edge. + pub async fn wait_for_rising_edge(&mut self) { + // Unwrap okay, checked pin in constructor. + #[cfg(feature = "vor1x")] + InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::LowToHigh).await; + } + + /// Asynchronously wait until the pin sees any edge (either rising or falling). + pub async fn wait_for_any_edge(&mut self) { + // Unwrap okay, checked pin in constructor. + #[cfg(feature = "vor1x")] + InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::BothEdges).await; + #[cfg(feature = "vor4x")] + InputPinFuture::new_with_input_pin(&mut self.pin, InterruptEdge::BothEdges) + .unwrap() + .await; + } + + pub fn release(self) -> Input { + self.pin + } +} + +impl embedded_hal::digital::ErrorType for InputPinAsync { + type Error = core::convert::Infallible; +} + +impl Wait for InputPinAsync { + async fn wait_for_high(&mut self) -> Result<(), Self::Error> { + self.wait_for_high().await; + Ok(()) + } + + async fn wait_for_low(&mut self) -> Result<(), Self::Error> { + self.wait_for_low().await; + Ok(()) + } + + async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_rising_edge().await; + Ok(()) + } + + async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_falling_edge().await; + Ok(()) + } + + async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> { + self.wait_for_any_edge().await; + Ok(()) + } +} diff --git a/vorago-shared-hal/src/gpio/ll.rs b/vorago-shared-hal/src/gpio/ll.rs new file mode 100644 index 0000000..0389cb2 --- /dev/null +++ b/vorago-shared-hal/src/gpio/ll.rs @@ -0,0 +1,584 @@ +pub use embedded_hal::digital::PinState; + +use crate::ioconfig::FilterClockSelect; +use crate::ioconfig::FilterType; +#[cfg(feature = "vor1x")] +use crate::{PeripheralSelect, sysconfig::enable_peripheral_clock}; + +pub use crate::InvalidOffsetError; +pub use crate::Port; +pub use crate::ioconfig::regs::Pull; +use crate::ioconfig::regs::{FunctionSelect, IoConfig, MmioIoConfig}; +use crate::pins::PinId; + +use super::Pin; + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum InterruptEdge { + HighToLow, + LowToHigh, + BothEdges, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum InterruptLevel { + Low = 0, + High = 1, +} + +/// Pin identifier for all physical pins exposed by Vorago MCUs. +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct DynPinId { + port: Port, + /// Offset within the port. + offset: u8, +} + +#[derive(Debug, thiserror::Error)] +#[cfg(feature = "vor4x")] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("port G does not support interrupts")] +pub struct PortDoesNotSupportInterrupts; + +impl DynPinId { + /// Unchecked constructor which panics on invalid offsets. + pub const fn new_unchecked(port: Port, offset: usize) -> Self { + if offset >= port.max_offset() { + panic!("Pin ID construction: offset is out of range"); + } + DynPinId { + port, + offset: offset as u8, + } + } + + pub const fn new(port: Port, offset: usize) -> Result { + if offset >= port.max_offset() { + return Err(InvalidOffsetError { offset, port }); + } + Ok(DynPinId { + port, + offset: offset as u8, + }) + } + + pub const fn port(&self) -> Port { + self.port + } + + pub const fn offset(&self) -> usize { + self.offset as usize + } + + /// This function panics if the port is [Port::G]. + #[cfg(feature = "vor4x")] + pub fn irq(&self) -> Result { + if self.port() == Port::G { + return Err(PortDoesNotSupportInterrupts); + } + Ok(self.irq_unchecked()) + } + + /// This function panics if the port is [Port::G]. + #[cfg(feature = "vor4x")] + pub const fn irq_unchecked(&self) -> va416xx::Interrupt { + match self.port() { + Port::A => match self.offset() { + 0 => va416xx::Interrupt::PORTA0, + 1 => va416xx::Interrupt::PORTA1, + 2 => va416xx::Interrupt::PORTA2, + 3 => va416xx::Interrupt::PORTA3, + 4 => va416xx::Interrupt::PORTA4, + 5 => va416xx::Interrupt::PORTA5, + 6 => va416xx::Interrupt::PORTA6, + 7 => va416xx::Interrupt::PORTA7, + 8 => va416xx::Interrupt::PORTA8, + 9 => va416xx::Interrupt::PORTA9, + 10 => va416xx::Interrupt::PORTA10, + 11 => va416xx::Interrupt::PORTA11, + 12 => va416xx::Interrupt::PORTA12, + 13 => va416xx::Interrupt::PORTA13, + 14 => va416xx::Interrupt::PORTA14, + 15 => va416xx::Interrupt::PORTA15, + _ => unreachable!(), + }, + Port::B => match self.offset() { + 0 => va416xx::Interrupt::PORTB0, + 1 => va416xx::Interrupt::PORTB1, + 2 => va416xx::Interrupt::PORTB2, + 3 => va416xx::Interrupt::PORTB3, + 4 => va416xx::Interrupt::PORTB4, + 5 => va416xx::Interrupt::PORTB5, + 6 => va416xx::Interrupt::PORTB6, + 7 => va416xx::Interrupt::PORTB7, + 8 => va416xx::Interrupt::PORTB8, + 9 => va416xx::Interrupt::PORTB9, + 10 => va416xx::Interrupt::PORTB10, + 11 => va416xx::Interrupt::PORTB11, + 12 => va416xx::Interrupt::PORTB12, + 13 => va416xx::Interrupt::PORTB13, + 14 => va416xx::Interrupt::PORTB14, + 15 => va416xx::Interrupt::PORTB15, + _ => unreachable!(), + }, + Port::C => match self.offset() { + 0 => va416xx::Interrupt::PORTC0, + 1 => va416xx::Interrupt::PORTC1, + 2 => va416xx::Interrupt::PORTC2, + 3 => va416xx::Interrupt::PORTC3, + 4 => va416xx::Interrupt::PORTC4, + 5 => va416xx::Interrupt::PORTC5, + 6 => va416xx::Interrupt::PORTC6, + 7 => va416xx::Interrupt::PORTC7, + 8 => va416xx::Interrupt::PORTC8, + 9 => va416xx::Interrupt::PORTC9, + 10 => va416xx::Interrupt::PORTC10, + 11 => va416xx::Interrupt::PORTC11, + 12 => va416xx::Interrupt::PORTC12, + 13 => va416xx::Interrupt::PORTC13, + 14 => va416xx::Interrupt::PORTC14, + 15 => va416xx::Interrupt::PORTC15, + _ => unreachable!(), + }, + Port::D => match self.offset() { + 0 => va416xx::Interrupt::PORTD0, + 1 => va416xx::Interrupt::PORTD1, + 2 => va416xx::Interrupt::PORTD2, + 3 => va416xx::Interrupt::PORTD3, + 4 => va416xx::Interrupt::PORTD4, + 5 => va416xx::Interrupt::PORTD5, + 6 => va416xx::Interrupt::PORTD6, + 7 => va416xx::Interrupt::PORTD7, + 8 => va416xx::Interrupt::PORTD8, + 9 => va416xx::Interrupt::PORTD9, + 10 => va416xx::Interrupt::PORTD10, + 11 => va416xx::Interrupt::PORTD11, + 12 => va416xx::Interrupt::PORTD12, + 13 => va416xx::Interrupt::PORTD13, + 14 => va416xx::Interrupt::PORTD14, + 15 => va416xx::Interrupt::PORTD15, + _ => unreachable!(), + }, + Port::E => match self.offset() { + 0 => va416xx::Interrupt::PORTE0, + 1 => va416xx::Interrupt::PORTE1, + 2 => va416xx::Interrupt::PORTE2, + 3 => va416xx::Interrupt::PORTE3, + 4 => va416xx::Interrupt::PORTE4, + 5 => va416xx::Interrupt::PORTE5, + 6 => va416xx::Interrupt::PORTE6, + 7 => va416xx::Interrupt::PORTE7, + 8 => va416xx::Interrupt::PORTE8, + 9 => va416xx::Interrupt::PORTE9, + 10 => va416xx::Interrupt::PORTE10, + 11 => va416xx::Interrupt::PORTE11, + 12 => va416xx::Interrupt::PORTE12, + 13 => va416xx::Interrupt::PORTE13, + 14 => va416xx::Interrupt::PORTE14, + 15 => va416xx::Interrupt::PORTE15, + _ => unreachable!(), + }, + Port::F => match self.offset() { + 0 => va416xx::Interrupt::PORTF0, + 1 => va416xx::Interrupt::PORTF1, + 2 => va416xx::Interrupt::PORTF2, + 3 => va416xx::Interrupt::PORTF3, + 4 => va416xx::Interrupt::PORTF4, + 5 => va416xx::Interrupt::PORTF5, + 6 => va416xx::Interrupt::PORTF6, + 7 => va416xx::Interrupt::PORTF7, + 8 => va416xx::Interrupt::PORTF8, + 9 => va416xx::Interrupt::PORTF9, + 10 => va416xx::Interrupt::PORTF10, + 11 => va416xx::Interrupt::PORTF11, + 12 => va416xx::Interrupt::PORTF12, + 13 => va416xx::Interrupt::PORTF13, + 14 => va416xx::Interrupt::PORTF14, + 15 => va416xx::Interrupt::PORTF15, + _ => unreachable!(), + }, + Port::G => panic!("port G does not have interrupts"), + } + } +} + +/// Low-level driver structure for GPIO pins. +pub struct LowLevelGpio { + gpio: super::regs::MmioGpio<'static>, + ioconfig: MmioIoConfig<'static>, + id: DynPinId, +} + +impl core::fmt::Debug for LowLevelGpio { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + f.debug_struct("LowLevelGpio") + .field("gpio", &self.gpio.port()) + .field("id", &self.id) + .finish() + } +} + +impl LowLevelGpio { + /// Create a new low-level GPIO pin instance from a given [Pin]. + /// + /// Can be used for performing resource management of the [Pin]s. + pub fn new_with_pin(_pin: Pin) -> Self { + Self::new(I::ID) + } + + /// Create a new low-level GPIO pin instance using only the [PinId]. + pub fn new(id: DynPinId) -> Self { + LowLevelGpio { + gpio: super::regs::Gpio::new_mmio(id.port), + ioconfig: IoConfig::new_mmio(), + id, + } + } + + #[inline] + pub fn id(&self) -> DynPinId { + self.id + } + + #[inline] + pub fn port(&self) -> Port { + self.id.port() + } + + #[inline] + pub fn offset(&self) -> usize { + self.id.offset() + } + + pub fn configure_as_input_floating(&mut self) { + self.ioconfig.modify_pin_config(self.id, |mut config| { + config.set_funsel(FunctionSelect::Sel0); + config.set_io_disable(false); + config.set_invert_input(false); + config.set_open_drain(false); + config.set_pull_enable(false); + config.set_pull_when_output_active(false); + config.set_invert_output(false); + config.set_input_enable_when_output(false); + config + }); + self.gpio.modify_dir(|mut dir| { + dir &= !(1 << self.id.offset()); + dir + }); + } + + pub fn configure_as_input_with_pull(&mut self, pull: Pull) { + self.ioconfig.modify_pin_config(self.id, |mut config| { + config.set_funsel(FunctionSelect::Sel0); + config.set_io_disable(false); + config.set_invert_input(false); + config.set_open_drain(false); + config.set_pull_enable(true); + config.set_pull_dir(pull); + config.set_pull_when_output_active(false); + config.set_invert_output(false); + config.set_input_enable_when_output(false); + config + }); + self.gpio.modify_dir(|mut dir| { + dir &= !(1 << self.id.offset()); + dir + }); + } + + pub fn configure_as_output_push_pull(&mut self, init_level: PinState) { + self.ioconfig.modify_pin_config(self.id, |mut config| { + config.set_funsel(FunctionSelect::Sel0); + config.set_io_disable(false); + config.set_invert_input(false); + config.set_open_drain(false); + config.set_pull_enable(false); + config.set_pull_when_output_active(false); + config.set_invert_output(false); + config.set_input_enable_when_output(true); + config + }); + match init_level { + PinState::Low => self.gpio.write_clr_out(self.mask_32()), + PinState::High => self.gpio.write_set_out(self.mask_32()), + } + self.gpio.modify_dir(|mut dir| { + dir |= 1 << self.id.offset(); + dir + }); + } + + pub fn configure_as_output_open_drain(&mut self, init_level: PinState) { + self.ioconfig.modify_pin_config(self.id, |mut config| { + config.set_funsel(FunctionSelect::Sel0); + config.set_io_disable(false); + config.set_invert_input(false); + config.set_open_drain(true); + config.set_pull_enable(true); + config.set_pull_dir(Pull::Up); + config.set_pull_when_output_active(false); + config.set_invert_output(false); + config.set_input_enable_when_output(true); + config + }); + let mask32 = self.mask_32(); + match init_level { + PinState::Low => self.gpio.write_clr_out(mask32), + PinState::High => self.gpio.write_set_out(mask32), + } + self.gpio.modify_dir(|mut dir| { + dir |= mask32; + dir + }); + } + + pub fn configure_as_peripheral_pin(&mut self, fun_sel: FunctionSelect, pull: Option) { + self.ioconfig.modify_pin_config(self.id, |mut config| { + config.set_funsel(fun_sel); + config.set_io_disable(false); + config.set_invert_input(false); + config.set_open_drain(false); + config.set_pull_enable(pull.is_some()); + config.set_pull_dir(pull.unwrap_or(Pull::Up)); + config.set_invert_output(false); + config + }); + } + + #[inline] + pub fn is_high(&self) -> bool { + (self.gpio.read_data_in() >> self.offset()) & 1 == 1 + } + + #[inline] + pub fn is_low(&self) -> bool { + !self.is_high() + } + + #[inline] + pub fn set_high(&mut self) { + self.gpio.write_set_out(self.mask_32()); + } + + #[inline] + pub fn set_low(&mut self) { + self.gpio.write_clr_out(self.mask_32()); + } + + #[inline] + pub fn is_set_high(&self) -> bool { + (self.gpio.read_data_out() >> self.offset()) & 1 == 1 + } + + #[inline] + pub fn is_set_low(&self) -> bool { + !self.is_set_high() + } + + #[inline] + pub fn toggle(&mut self) { + self.gpio.write_tog_out(self.mask_32()); + } + + #[cfg(feature = "vor1x")] + pub fn enable_interrupt(&mut self, irq_cfg: crate::InterruptConfig) { + if irq_cfg.route { + self.configure_irqsel(irq_cfg.id); + } + if irq_cfg.enable_in_nvic { + unsafe { crate::enable_nvic_interrupt(irq_cfg.id) }; + } + self.gpio.modify_irq_enable(|mut value| { + value |= 1 << self.id.offset; + value + }); + } + + #[cfg(feature = "vor4x")] + pub fn enable_interrupt( + &mut self, + enable_in_nvic: bool, + ) -> Result<(), PortDoesNotSupportInterrupts> { + if enable_in_nvic { + unsafe { crate::enable_nvic_interrupt(self.id().irq_unchecked()) }; + } + self.gpio.modify_irq_enable(|mut value| { + value |= 1 << self.id.offset; + value + }); + Ok(()) + } + + #[cfg(feature = "vor1x")] + pub fn disable_interrupt(&mut self, reset_irqsel: bool) { + if reset_irqsel { + self.reset_irqsel(); + } + // We only manipulate our own bit. + self.gpio.modify_irq_enable(|mut value| { + value &= !(1 << self.id.offset); + value + }); + } + + #[cfg(feature = "vor4x")] + pub fn disable_interrupt(&mut self) { + self.gpio.modify_irq_enable(|mut value| { + value &= !(1 << self.id.offset); + value + }); + } + + /// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure + /// When using edge mode, it is possible to generate interrupts on both edges as well + #[inline] + pub fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) { + let mask32 = self.mask_32(); + self.gpio.modify_irq_sen(|mut value| { + value &= !mask32; + value + }); + match edge_type { + InterruptEdge::HighToLow => { + self.gpio.modify_irq_evt(|mut value| { + value &= !mask32; + value + }); + } + InterruptEdge::LowToHigh => { + self.gpio.modify_irq_evt(|mut value| { + value |= mask32; + value + }); + } + InterruptEdge::BothEdges => { + self.gpio.modify_irq_edge(|mut value| { + value |= mask32; + value + }); + } + } + } + + /// Configure which edge or level type triggers an interrupt + #[inline] + pub fn configure_level_interrupt(&mut self, level: InterruptLevel) { + let mask32 = self.mask_32(); + self.gpio.modify_irq_sen(|mut value| { + value |= mask32; + value + }); + if level == InterruptLevel::Low { + self.gpio.modify_irq_evt(|mut value| { + value &= !mask32; + value + }); + } else { + self.gpio.modify_irq_evt(|mut value| { + value |= mask32; + value + }); + } + } + + /// Only useful for input pins + #[inline] + pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClockSelect) { + self.ioconfig.modify_pin_config(self.id, |mut config| { + config.set_filter_type(filter); + config.set_filter_clk_sel(clksel); + config + }); + } + + /// Only useful for output pins. + #[inline] + pub fn configure_pulse_mode(&mut self, enable: bool, default_state: PinState) { + self.gpio.modify_pulse(|mut value| { + if enable { + value |= 1 << self.id.offset; + } else { + value &= !(1 << self.id.offset); + } + value + }); + self.gpio.modify_pulsebase(|mut value| { + if default_state == PinState::High { + value |= 1 << self.id.offset; + } else { + value &= !(1 << self.id.offset); + } + value + }); + } + + /// Only useful for output pins + #[inline] + pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) { + self.gpio.modify_delay1(|mut value| { + if delay_1 { + value |= 1 << self.id.offset; + } else { + value &= !(1 << self.id.offset); + } + value + }); + self.gpio.modify_delay2(|mut value| { + if delay_2 { + value |= 1 << self.id.offset; + } else { + value &= !(1 << self.id.offset); + } + value + }); + } + + #[cfg(feature = "vor1x")] + /// Configure the IRQSEL peripheral for this particular pin with the given interrupt ID. + pub fn configure_irqsel(&mut self, id: va108xx::Interrupt) { + let irqsel = unsafe { va108xx::Irqsel::steal() }; + enable_peripheral_clock(PeripheralSelect::Irqsel); + match self.id().port() { + // Set the correct interrupt number in the IRQSEL register + super::Port::A => { + irqsel + .porta(self.id().offset()) + .write(|w| unsafe { w.bits(id as u32) }); + } + super::Port::B => { + irqsel + .portb(self.id().offset()) + .write(|w| unsafe { w.bits(id as u32) }); + } + } + } + + #[cfg(feature = "vor1x")] + /// Reset the IRQSEL peripheral value for this particular pin. + pub fn reset_irqsel(&mut self) { + let irqsel = unsafe { va108xx::Irqsel::steal() }; + enable_peripheral_clock(PeripheralSelect::Irqsel); + match self.id().port() { + // Set the correct interrupt number in the IRQSEL register + super::Port::A => { + irqsel + .porta(self.id().offset()) + .write(|w| unsafe { w.bits(u32::MAX) }); + } + super::Port::B => { + irqsel + .portb(self.id().offset()) + .write(|w| unsafe { w.bits(u32::MAX) }); + } + } + } + + #[inline(always)] + pub const fn mask_32(&self) -> u32 { + 1 << self.id.offset() + } +} diff --git a/vorago-shared-hal/src/gpio/mod.rs b/vorago-shared-hal/src/gpio/mod.rs new file mode 100644 index 0000000..498ea92 --- /dev/null +++ b/vorago-shared-hal/src/gpio/mod.rs @@ -0,0 +1,362 @@ +//! GPIO support module. +use core::convert::Infallible; + +pub use crate::ioconfig::{FilterClockSelect, FilterType, regs::FunctionSelect}; +pub use crate::pins::{Pin, PinId}; +pub use embedded_hal::digital::PinState; +pub use ll::{DynPinId, InterruptEdge, InterruptLevel, Port, Pull}; + +pub mod asynch; +pub mod ll; +pub mod regs; + +/// Push-Pull output pin. +#[derive(Debug)] +pub struct Output(ll::LowLevelGpio); + +impl Output { + pub fn new(_pin: Pin, init_level: PinState) -> Self { + let mut ll = ll::LowLevelGpio::new(I::ID); + ll.configure_as_output_push_pull(init_level); + Output(ll) + } + + #[inline] + pub fn port(&self) -> Port { + self.0.port() + } + + #[inline] + pub fn offset(&self) -> usize { + self.0.offset() + } + + #[inline] + pub fn set_high(&mut self) { + self.0.set_high(); + } + + #[inline] + pub fn set_low(&mut self) { + self.0.set_low(); + } + + #[inline] + pub fn is_set_high(&self) -> bool { + self.0.is_set_high() + } + + #[inline] + pub fn is_set_low(&self) -> bool { + self.0.is_set_low() + } + + /// Toggle pin output with dedicated HW feature. + #[inline] + pub fn toggle(&mut self) { + self.0.toggle(); + } + + #[inline] + pub fn configure_pulse_mode(&mut self, enable: bool, default_state: PinState) { + self.0.configure_pulse_mode(enable, default_state); + } + + #[inline] + pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) { + self.0.configure_delay(delay_1, delay_2); + } +} + +impl embedded_hal::digital::ErrorType for Output { + type Error = Infallible; +} + +impl embedded_hal::digital::OutputPin for Output { + fn set_low(&mut self) -> Result<(), Self::Error> { + self.0.set_low(); + Ok(()) + } + + fn set_high(&mut self) -> Result<(), Self::Error> { + self.0.set_high(); + Ok(()) + } +} + +impl embedded_hal::digital::StatefulOutputPin for Output { + fn is_set_high(&mut self) -> Result { + Ok(self.0.is_set_high()) + } + + fn is_set_low(&mut self) -> Result { + Ok(self.0.is_set_low()) + } + + /// Toggle pin output with dedicated HW feature. + fn toggle(&mut self) -> Result<(), Self::Error> { + self.0.toggle(); + Ok(()) + } +} + +/// Input pin. +/// +/// Can be created as a floating input pin or as an input pin with pull-up or pull-down. +#[derive(Debug)] +pub struct Input(ll::LowLevelGpio); + +impl Input { + pub fn new_floating(_pin: Pin) -> Self { + let mut ll = ll::LowLevelGpio::new(I::ID); + ll.configure_as_input_floating(); + Input(ll) + } + + pub fn new_with_pull(_pin: Pin, pull: Pull) -> Self { + let mut ll = ll::LowLevelGpio::new(I::ID); + ll.configure_as_input_with_pull(pull); + Input(ll) + } + + #[inline] + pub fn id(&self) -> DynPinId { + self.0.id() + } + + #[cfg(feature = "vor1x")] + #[inline] + pub fn enable_interrupt(&mut self, irq_cfg: crate::InterruptConfig) { + self.0.enable_interrupt(irq_cfg); + } + + #[cfg(feature = "vor4x")] + #[inline] + pub fn enable_interrupt( + &mut self, + enable_in_nvic: bool, + ) -> Result<(), ll::PortDoesNotSupportInterrupts> { + self.0.enable_interrupt(enable_in_nvic) + } + + #[inline] + pub fn configure_edge_interrupt(&mut self, edge: InterruptEdge) { + self.0.configure_edge_interrupt(edge); + } + + #[inline] + pub fn configure_level_interrupt(&mut self, edge: InterruptLevel) { + self.0.configure_level_interrupt(edge); + } + + #[inline] + pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) { + self.0.configure_delay(delay_1, delay_2); + } + + #[inline] + pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClockSelect) { + self.0.configure_filter_type(filter, clksel); + } + + #[inline] + pub fn is_low(&self) -> bool { + self.0.is_low() + } + + #[inline] + pub fn is_high(&self) -> bool { + self.0.is_high() + } +} + +impl embedded_hal::digital::ErrorType for Input { + type Error = Infallible; +} + +impl embedded_hal::digital::InputPin for Input { + fn is_low(&mut self) -> Result { + Ok(self.0.is_low()) + } + + fn is_high(&mut self) -> Result { + Ok(self.0.is_high()) + } +} + +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum PinMode { + InputFloating, + InputWithPull(Pull), + OutputPushPull, + OutputOpenDrain, +} + +impl PinMode { + pub fn is_input(&self) -> bool { + matches!(self, PinMode::InputFloating | PinMode::InputWithPull(_)) + } + + pub fn is_output(&self) -> bool { + !self.is_input() + } +} + +/// Flex pin abstraction which can be dynamically re-configured. +/// +/// The following functions can be configured at run-time: +/// +/// - Input Floating +/// - Input with Pull-Up +/// - Output Push-Pull +/// - Output Open-Drain. +/// +/// Flex pins are always floating input pins after construction. +#[derive(Debug)] +pub struct Flex { + ll: ll::LowLevelGpio, + mode: PinMode, +} + +impl Flex { + pub fn new(_pin: Pin) -> Self { + let mut ll = ll::LowLevelGpio::new(I::ID); + ll.configure_as_input_floating(); + Flex { + ll, + mode: PinMode::InputFloating, + } + } + + #[inline] + pub fn port(&self) -> Port { + self.ll.port() + } + + #[inline] + pub fn offset(&self) -> usize { + self.ll.offset() + } + + /// Reads the input state of the pin, regardless of configured mode. + #[inline] + pub fn is_low(&self) -> bool { + self.ll.is_low() + } + + /// Reads the input state of the pin, regardless of configured mode. + #[inline] + pub fn is_high(&self) -> bool { + self.ll.is_high() + } + + /// If the pin is configured as an input pin, this function does nothing. + #[inline] + pub fn set_low(&mut self) { + if !self.mode.is_input() { + return; + } + self.ll.set_low(); + } + + /// If the pin is configured as an input pin, this function does nothing. + #[inline] + pub fn set_high(&mut self) { + if !self.mode.is_input() { + return; + } + self.ll.set_high(); + } +} + +impl embedded_hal::digital::ErrorType for Flex { + type Error = Infallible; +} + +impl embedded_hal::digital::InputPin for Flex { + /// Reads the input state of the pin, regardless of configured mode. + fn is_low(&mut self) -> Result { + Ok(self.ll.is_low()) + } + + /// Reads the input state of the pin, regardless of configured mode. + fn is_high(&mut self) -> Result { + Ok(self.ll.is_high()) + } +} + +impl embedded_hal::digital::OutputPin for Flex { + /// If the pin is configured as an input pin, this function does nothing. + fn set_low(&mut self) -> Result<(), Self::Error> { + self.set_low(); + Ok(()) + } + + /// If the pin is configured as an input pin, this function does nothing. + fn set_high(&mut self) -> Result<(), Self::Error> { + self.set_high(); + Ok(()) + } +} + +impl embedded_hal::digital::StatefulOutputPin for Flex { + /// If the pin is not configured as a stateful output pin like Output Push-Pull, the result + /// of this function is undefined. + fn is_set_high(&mut self) -> Result { + Ok(self.ll.is_set_high()) + } + + /// If the pin is not configured as a stateful output pin like Output Push-Pull, the result + /// of this function is undefined. + fn is_set_low(&mut self) -> Result { + Ok(self.ll.is_set_low()) + } + + /// Toggle pin output. + /// + /// If the pin is not configured as a stateful output pin like Output Push-Pull, the result + /// of this function is undefined. + fn toggle(&mut self) -> Result<(), Self::Error> { + self.ll.toggle(); + Ok(()) + } +} + +/// IO peripheral pin structure. +/// +/// Can be used to configure pins as IO peripheral pins. +pub struct IoPeriphPin { + ll: ll::LowLevelGpio, + fun_sel: FunctionSelect, +} + +impl IoPeriphPin { + pub fn new_with_pin( + _pin: Pin, + fun_sel: FunctionSelect, + pull: Option, + ) -> Self { + let mut ll = ll::LowLevelGpio::new(I::ID); + ll.configure_as_peripheral_pin(fun_sel, pull); + IoPeriphPin { ll, fun_sel } + } + + pub fn new(pin_id: DynPinId, fun_sel: FunctionSelect, pull: Option) -> Self { + let mut ll = ll::LowLevelGpio::new(pin_id); + ll.configure_as_peripheral_pin(fun_sel, pull); + IoPeriphPin { ll, fun_sel } + } + + pub fn port(&self) -> Port { + self.ll.port() + } + + pub fn offset(&self) -> usize { + self.ll.offset() + } + + pub fn fun_sel(&self) -> FunctionSelect { + self.fun_sel + } +} diff --git a/vorago-shared-hal/src/gpio/regs.rs b/vorago-shared-hal/src/gpio/regs.rs new file mode 100644 index 0000000..e0ae9db --- /dev/null +++ b/vorago-shared-hal/src/gpio/regs.rs @@ -0,0 +1,126 @@ +use crate::Port; + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + /// PORT A base address. + pub const GPIO_0_BASE: usize = 0x5000_0000; + /// PORT B base address. + pub const GPIO_1_BASE: usize = 0x5000_1000; + } else if #[cfg(feature = "vor4x")] { + /// PORT A base address. + pub const GPIO_0_BASE: usize = 0x4001_2000; + /// PORT B base address. + pub const GPIO_1_BASE: usize = 0x4001_2400; + /// PORT C base address. + pub const GPIO_2_BASE: usize = 0x4001_2800; + /// PORT D base address. + pub const GPIO_3_BASE: usize = 0x4001_2C00; + /// PORT E base address. + pub const GPIO_4_BASE: usize = 0x4001_3000; + /// PORT F base address. + pub const GPIO_5_BASE: usize = 0x4001_3400; + /// PORT G base address. + pub const GPIO_6_BASE: usize = 0x4001_3800; + } +} + +#[derive(derive_mmio::Mmio)] +#[mmio(no_ctors)] +#[repr(C)] +pub struct Gpio { + #[mmio(PureRead)] + data_in: u32, + #[mmio(PureRead)] + data_in_raw: u32, + data_out: u32, + data_out_raw: u32, + #[mmio(Write)] + set_out: u32, + #[mmio(Write)] + clr_out: u32, + #[mmio(Write)] + tog_out: u32, + data_mask: u32, + /// Direction bits. 1 for output, 0 for input. + dir: u32, + pulse: u32, + pulsebase: u32, + delay1: u32, + delay2: u32, + irq_sen: u32, + irq_edge: u32, + irq_evt: u32, + irq_enable: u32, + /// Raw interrupt status. This register is not latched and may not indicated edge sensitive + /// events. + #[mmio(PureRead)] + irq_raw: u32, + /// Read-only register which shows enabled and active interrupts. Called IRQ_end by Vorago. + #[mmio(PureRead)] + irq_status: u32, + #[mmio(PureRead)] + edge_status: u32, + + #[cfg(feature = "vor1x")] + _reserved: [u32; 0x3eb], + #[cfg(feature = "vor4x")] + _reserved: [u32; 0xeb], + + /// Peripheral ID. Vorago 1x reset value: 0x0040_07e1. Vorago 4x reset value: 0x0210_07E9. + perid: u32, +} + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + static_assertions::const_assert_eq!(core::mem::size_of::(), 0x1000); + } else if #[cfg(feature = "vor4x")] { + static_assertions::const_assert_eq!(core::mem::size_of::(), 0x400); + } +} + +impl Gpio { + const fn new_mmio_at(base: usize) -> MmioGpio<'static> { + MmioGpio { + ptr: base as *mut _, + phantom: core::marker::PhantomData, + } + } + + pub const fn new_mmio(port: Port) -> MmioGpio<'static> { + match port { + Port::A => Self::new_mmio_at(GPIO_0_BASE), + Port::B => Self::new_mmio_at(GPIO_1_BASE), + #[cfg(feature = "vor4x")] + Port::C => Self::new_mmio_at(GPIO_2_BASE), + #[cfg(feature = "vor4x")] + Port::D => Self::new_mmio_at(GPIO_3_BASE), + #[cfg(feature = "vor4x")] + Port::E => Self::new_mmio_at(GPIO_4_BASE), + #[cfg(feature = "vor4x")] + Port::F => Self::new_mmio_at(GPIO_5_BASE), + #[cfg(feature = "vor4x")] + Port::G => Self::new_mmio_at(GPIO_6_BASE), + } + } +} + +impl MmioGpio<'_> { + pub fn port(&self) -> Port { + match unsafe { self.ptr() } as usize { + GPIO_0_BASE => Port::A, + GPIO_1_BASE => Port::B, + #[cfg(feature = "vor4x")] + GPIO_2_BASE => Port::C, + #[cfg(feature = "vor4x")] + GPIO_3_BASE => Port::D, + #[cfg(feature = "vor4x")] + GPIO_4_BASE => Port::E, + #[cfg(feature = "vor4x")] + GPIO_5_BASE => Port::F, + #[cfg(feature = "vor4x")] + GPIO_6_BASE => Port::G, + // Constructors were disabled, so this should really not happen. + _ => panic!("unexpected base address of GPIO register block"), + } + } +} diff --git a/vorago-shared-hal/src/i2c/mod.rs b/vorago-shared-hal/src/i2c/mod.rs new file mode 100644 index 0000000..48805a0 --- /dev/null +++ b/vorago-shared-hal/src/i2c/mod.rs @@ -0,0 +1,705 @@ +pub mod regs; + +use crate::{ + PeripheralSelect, enable_peripheral_clock, sealed::Sealed, + sysconfig::reset_peripheral_for_cycles, time::Hertz, +}; +use arbitrary_int::{u4, u10, u11, u20}; +use core::marker::PhantomData; +use embedded_hal::i2c::{self, Operation, SevenBitAddress, TenBitAddress}; +use regs::ClockTimeoutLimit; +pub use regs::{Bank, I2cSpeed, RxFifoFullMode, TxFifoEmptyMode}; + +#[cfg(feature = "vor1x")] +use va108xx as pac; +#[cfg(feature = "vor4x")] +use va416xx as pac; + +//================================================================================================== +// Defintions +//================================================================================================== + +const CLK_100K: Hertz = Hertz::from_raw(100_000); +const CLK_400K: Hertz = Hertz::from_raw(400_000); +const MIN_CLK_400K: Hertz = Hertz::from_raw(8_000_000); + +#[derive(Debug, PartialEq, Eq, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("clock too slow for fast I2C mode")] +pub struct ClockTooSlowForFastI2cError; + +#[derive(Debug, PartialEq, Eq, thiserror::Error)] +#[error("invalid timing parameters")] +pub struct InvalidTimingParamsError; + +#[derive(Debug, PartialEq, Eq, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Error { + #[error("arbitration lost")] + ArbitrationLost, + #[error("nack address")] + NackAddr, + /// Data not acknowledged in write operation + #[error("data not acknowledged in write operation")] + NackData, + /// Not enough data received in read operation + #[error("insufficient data received")] + InsufficientDataReceived, + /// Number of bytes in transfer too large (larger than 0x7fe) + #[error("data too large (larger than 0x7fe)")] + DataTooLarge, + #[error("clock timeout, SCL was low for {0} clock cycles")] + ClockTimeout(u20), +} + +#[derive(Debug, PartialEq, Eq, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum InitError { + /// Wrong address used in constructor + #[error("wrong address mode")] + WrongAddrMode, + /// APB1 clock is too slow for fast I2C mode. + #[error("clock too slow for fast I2C mode: {0}")] + ClockTooSlow(#[from] ClockTooSlowForFastI2cError), +} + +impl embedded_hal::i2c::Error for Error { + fn kind(&self) -> embedded_hal::i2c::ErrorKind { + match self { + Error::ArbitrationLost => embedded_hal::i2c::ErrorKind::ArbitrationLoss, + Error::NackAddr => { + embedded_hal::i2c::ErrorKind::NoAcknowledge(i2c::NoAcknowledgeSource::Address) + } + Error::NackData => { + embedded_hal::i2c::ErrorKind::NoAcknowledge(i2c::NoAcknowledgeSource::Data) + } + Error::DataTooLarge | Error::InsufficientDataReceived | Error::ClockTimeout(_) => { + embedded_hal::i2c::ErrorKind::Other + } + } + } +} + +#[derive(Debug, PartialEq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum I2cCommand { + Start = 0b01, + Stop = 0b10, + StartWithStop = 0b11, + Cancel = 0b100, +} + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum I2cAddress { + Regular(u8), + TenBit(u16), +} + +impl I2cAddress { + pub fn ten_bit_addr(&self) -> bool { + match self { + I2cAddress::Regular(_) => false, + I2cAddress::TenBit(_) => true, + } + } + pub fn raw(&self) -> u16 { + match self { + I2cAddress::Regular(addr) => *addr as u16, + I2cAddress::TenBit(addr) => *addr, + } + } +} + +/// Common trait implemented by all PAC peripheral access structures. The register block +/// format is the same for all SPI blocks. +pub trait I2cInstance: Sealed { + const ID: Bank; + const PERIPH_SEL: PeripheralSelect; +} + +#[cfg(feature = "vor1x")] +pub type I2c0 = pac::I2ca; +#[cfg(feature = "vor4x")] +pub type I2c0 = pac::I2c0; + +impl I2cInstance for I2c0 { + const ID: Bank = Bank::I2c0; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::I2c0; +} +impl Sealed for I2c0 {} + +#[cfg(feature = "vor1x")] +pub type I2c1 = pac::I2cb; +#[cfg(feature = "vor4x")] +pub type I2c1 = pac::I2c1; + +impl I2cInstance for I2c1 { + const ID: Bank = Bank::I2c1; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::I2c1; +} +impl Sealed for I2c1 {} + +//================================================================================================== +// Config +//================================================================================================== + +fn calc_clk_div_generic( + ref_clk: Hertz, + speed_mode: I2cSpeed, +) -> Result { + if speed_mode == I2cSpeed::Regular100khz { + Ok(((ref_clk.raw() / CLK_100K.raw() / 20) - 1) as u8) + } else { + if ref_clk.raw() < MIN_CLK_400K.raw() { + return Err(ClockTooSlowForFastI2cError); + } + Ok(((ref_clk.raw() / CLK_400K.raw() / 25) - 1) as u8) + } +} + +#[cfg(feature = "vor4x")] +fn calc_clk_div( + clks: &crate::clock::Clocks, + speed_mode: I2cSpeed, +) -> Result { + calc_clk_div_generic(clks.apb1(), speed_mode) +} + +#[cfg(feature = "vor1x")] +fn calc_clk_div(sys_clk: Hertz, speed_mode: I2cSpeed) -> Result { + calc_clk_div_generic(sys_clk, speed_mode) +} + +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct TimingConfig { + pub t_rise: u4, + pub t_fall: u4, + pub t_high: u4, + pub t_low: u4, + pub tsu_stop: u4, + pub tsu_start: u4, + pub thd_start: u4, + pub t_buf: u4, +} + +/// Default configuration are the register reset value which are used by default. +impl Default for TimingConfig { + fn default() -> Self { + TimingConfig { + t_rise: u4::new(0b0010), + t_fall: u4::new(0b0001), + t_high: u4::new(0b1000), + t_low: u4::new(0b1001), + tsu_stop: u4::new(0b1000), + tsu_start: u4::new(0b1010), + thd_start: u4::new(0b1000), + t_buf: u4::new(0b1010), + } + } +} + +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct MasterConfig { + pub tx_empty_mode: TxFifoEmptyMode, + pub rx_full_mode: RxFifoFullMode, + /// Enable the analog delay glitch filter + pub alg_filt: bool, + /// Enable the digital glitch filter + pub dlg_filt: bool, + pub timing_config: Option, + /// See [I2cMaster::set_clock_low_timeout] documentation. + pub timeout: Option, + // Loopback mode + // lbm: bool, +} + +impl Default for MasterConfig { + fn default() -> Self { + MasterConfig { + tx_empty_mode: TxFifoEmptyMode::Stall, + rx_full_mode: RxFifoFullMode::Stall, + alg_filt: false, + dlg_filt: false, + timeout: None, + timing_config: None, + } + } +} + +impl Sealed for MasterConfig {} + +#[derive(Debug, PartialEq, Eq)] +enum WriteCompletionCondition { + Idle, + Waiting, +} + +struct TimeoutGuard { + clk_timeout_enabled: bool, + regs: regs::MmioI2c<'static>, +} + +impl TimeoutGuard { + fn new(regs: ®s::MmioI2c<'static>) -> Self { + let clk_timeout_enabled = regs.read_clk_timeout_limit().value().value() > 0; + let mut guard = TimeoutGuard { + clk_timeout_enabled, + regs: unsafe { regs.clone() }, + }; + if clk_timeout_enabled { + // Clear any interrupts which might be pending. + guard.regs.write_irq_clear( + regs::InterruptClear::builder() + .with_clock_timeout(true) + .with_tx_overflow(false) + .with_rx_overflow(false) + .build(), + ); + guard.regs.modify_irq_enb(|mut value| { + value.set_clock_timeout(true); + value + }); + } + guard + } + + fn timeout_enabled(&self) -> bool { + self.clk_timeout_enabled + } +} + +impl Drop for TimeoutGuard { + fn drop(&mut self) { + if self.clk_timeout_enabled { + self.regs.modify_irq_enb(|mut value| { + value.set_clock_timeout(false); + value + }); + } + } +} +//================================================================================================== +// I2C Master +//================================================================================================== + +pub struct I2cMaster { + id: Bank, + regs: regs::MmioI2c<'static>, + addr: PhantomData, +} + +impl I2cMaster { + pub fn new( + _i2c: I2c, + #[cfg(feature = "vor1x")] sysclk: Hertz, + #[cfg(feature = "vor4x")] clks: &crate::clock::Clocks, + cfg: MasterConfig, + speed_mode: I2cSpeed, + ) -> Result { + reset_peripheral_for_cycles(I2c::PERIPH_SEL, 2); + enable_peripheral_clock(I2c::PERIPH_SEL); + let mut regs = regs::I2c::new_mmio(I2c::ID); + #[cfg(feature = "vor1x")] + let clk_div = calc_clk_div(sysclk, speed_mode)?; + #[cfg(feature = "vor4x")] + let clk_div = calc_clk_div(clks, speed_mode)?; + regs.write_clkscale( + regs::ClockScale::builder() + .with_div(clk_div) + .with_fastmode(speed_mode) + .build(), + ); + regs.modify_control(|mut value| { + value.set_tx_fifo_empty_mode(cfg.tx_empty_mode); + value.set_rx_fifo_full_mode(cfg.rx_full_mode); + value.set_analog_filter(cfg.alg_filt); + value.set_digital_filter(cfg.dlg_filt); + value + }); + + if let Some(ref timing_cfg) = cfg.timing_config { + regs.modify_control(|mut value| { + value.set_enable_timing_config(true); + value + }); + regs.write_timing_config( + regs::TimingConfig::builder() + .with_t_rise(timing_cfg.t_rise) + .with_t_fall(timing_cfg.t_fall) + .with_t_high(timing_cfg.t_high) + .with_t_low(timing_cfg.t_low) + .with_tsu_stop(timing_cfg.tsu_stop) + .with_tsu_start(timing_cfg.tsu_start) + .with_thd_start(timing_cfg.thd_start) + .with_t_buf(timing_cfg.t_buf) + .build(), + ); + } + regs.write_fifo_clear( + regs::FifoClear::builder() + .with_tx_fifo(true) + .with_rx_fifo(true) + .build(), + ); + if let Some(timeout) = cfg.timeout { + regs.write_clk_timeout_limit(ClockTimeoutLimit::new(timeout)); + } + let mut i2c_master = I2cMaster { + addr: PhantomData, + id: I2c::ID, + regs, + }; + i2c_master.enable(); + Ok(i2c_master) + } + + pub const fn id(&self) -> Bank { + self.id + } + + #[inline] + pub fn perid(&self) -> u32 { + self.regs.read_perid() + } + + /// Configures the clock scale for a given speed mode setting + pub fn set_clk_scale( + &mut self, + #[cfg(feature = "vor1x")] sys_clk: Hertz, + #[cfg(feature = "vor4x")] clks: &crate::clock::Clocks, + speed_mode: I2cSpeed, + ) -> Result<(), ClockTooSlowForFastI2cError> { + self.disable(); + #[cfg(feature = "vor1x")] + let clk_div = calc_clk_div(sys_clk, speed_mode)?; + #[cfg(feature = "vor4x")] + let clk_div = calc_clk_div(clks, speed_mode)?; + self.regs.write_clkscale( + regs::ClockScale::builder() + .with_div(clk_div) + .with_fastmode(speed_mode) + .build(), + ); + self.enable(); + Ok(()) + } + + #[inline] + pub fn cancel_transfer(&mut self) { + self.regs.write_cmd( + regs::Command::builder() + .with_start(false) + .with_stop(false) + .with_cancel(true) + .build(), + ); + } + + #[inline] + pub fn clear_tx_fifo(&mut self) { + self.regs.write_fifo_clear( + regs::FifoClear::builder() + .with_tx_fifo(true) + .with_rx_fifo(false) + .build(), + ); + } + + #[inline] + pub fn clear_rx_fifo(&mut self) { + self.regs.write_fifo_clear( + regs::FifoClear::builder() + .with_tx_fifo(false) + .with_rx_fifo(true) + .build(), + ); + } + + /// Configure a timeout limit on the amount of time the I2C clock is seen to be low. + /// The timeout is specified as I2C clock cycles. + /// + /// If the timeout is enabled, the blocking transaction handlers provided by the [I2cMaster] + /// will poll the interrupt status register to check for timeouts. This can be used to avoid + /// hang-ups of the I2C bus. + #[inline] + pub fn set_clock_low_timeout(&mut self, clock_cycles: u20) { + self.regs + .write_clk_timeout_limit(ClockTimeoutLimit::new(clock_cycles)); + } + + #[inline] + pub fn disable_clock_low_timeout(&mut self) { + self.regs + .write_clk_timeout_limit(ClockTimeoutLimit::new(u20::new(0))); + } + + #[inline] + pub fn enable(&mut self) { + self.regs.modify_control(|mut value| { + value.set_enable(true); + value + }); + } + + #[inline] + pub fn disable(&mut self) { + self.regs.modify_control(|mut value| { + value.set_enable(false); + value + }); + } + + #[inline(always)] + fn write_fifo_unchecked(&mut self, word: u8) { + self.regs.write_data(regs::Data::new(word)); + } + + #[inline(always)] + fn read_fifo_unchecked(&self) -> u8 { + self.regs.read_data().data() + } + + #[inline] + pub fn read_status(&mut self) -> regs::Status { + self.regs.read_status() + } + + #[inline] + pub fn write_command(&mut self, cmd: I2cCommand) { + self.regs + .write_cmd(regs::Command::new_with_raw_value(cmd as u32)); + } + + #[inline] + pub fn write_address(&mut self, addr: I2cAddress, dir: regs::Direction) { + self.regs.write_address( + regs::Address::builder() + .with_direction(dir) + .with_address(u10::new(addr.raw())) + .with_a10_mode(addr.ten_bit_addr()) + .build(), + ); + } + + fn error_handler_write(&mut self, init_cmd: I2cCommand) { + if init_cmd == I2cCommand::Start { + self.write_command(I2cCommand::Stop); + } + // The other case is start with stop where, so a CANCEL command should not be necessary + // because the hardware takes care of it. + self.clear_tx_fifo(); + } + + /// Blocking write transaction on the I2C bus. + pub fn write_blocking(&mut self, addr: I2cAddress, output: &[u8]) -> Result<(), Error> { + self.write_blocking_generic( + I2cCommand::StartWithStop, + addr, + output, + WriteCompletionCondition::Idle, + ) + } + + /// Blocking read transaction on the I2C bus. + pub fn read_blocking(&mut self, addr: I2cAddress, buffer: &mut [u8]) -> Result<(), Error> { + let len = buffer.len(); + if len > 0x7fe { + return Err(Error::DataTooLarge); + } + // Clear the receive FIFO + self.clear_rx_fifo(); + + let timeout_guard = TimeoutGuard::new(&self.regs); + + // Load number of words + self.regs + .write_words(regs::Words::new(u11::new(len as u16))); + // Load address + self.write_address(addr, regs::Direction::Receive); + + let mut buf_iter = buffer.iter_mut(); + let mut read_bytes = 0; + // Start receive transfer + self.write_command(I2cCommand::StartWithStop); + loop { + let status = self.read_status(); + if status.arb_lost() { + self.clear_rx_fifo(); + return Err(Error::ArbitrationLost); + } + if status.nack_addr() { + self.clear_rx_fifo(); + return Err(Error::NackAddr); + } + if status.idle() { + if read_bytes != len { + return Err(Error::InsufficientDataReceived); + } + return Ok(()); + } + if timeout_guard.timeout_enabled() && self.regs.read_irq_status().clock_timeout() { + return Err(Error::ClockTimeout( + self.regs.read_clk_timeout_limit().value(), + )); + } + if status.rx_not_empty() { + if let Some(next_byte) = buf_iter.next() { + *next_byte = self.read_fifo_unchecked(); + } + read_bytes += 1; + } + } + } + + fn write_blocking_generic( + &mut self, + init_cmd: I2cCommand, + addr: I2cAddress, + output: &[u8], + end_condition: WriteCompletionCondition, + ) -> Result<(), Error> { + let len = output.len(); + if len > 0x7fe { + return Err(Error::DataTooLarge); + } + // Clear the send FIFO + self.clear_tx_fifo(); + + let timeout_guard = TimeoutGuard::new(&self.regs); + + // Load number of words + self.regs + .write_words(regs::Words::new(u11::new(len as u16))); + let mut bytes = output.iter(); + // FIFO has a depth of 16. We load slightly above the trigger level + // but not all of it because the transaction might fail immediately + const FILL_DEPTH: usize = 12; + + let mut current_index = core::cmp::min(FILL_DEPTH, len); + // load the FIFO + for _ in 0..current_index { + self.write_fifo_unchecked(*bytes.next().unwrap()); + } + self.write_address(addr, regs::Direction::Send); + self.write_command(init_cmd); + loop { + let status = self.regs.read_status(); + if status.arb_lost() { + self.error_handler_write(init_cmd); + return Err(Error::ArbitrationLost); + } + if status.nack_addr() { + self.error_handler_write(init_cmd); + return Err(Error::NackAddr); + } + if status.nack_data() { + self.error_handler_write(init_cmd); + return Err(Error::NackData); + } + match end_condition { + WriteCompletionCondition::Idle => { + if status.idle() { + return Ok(()); + } + } + + WriteCompletionCondition::Waiting => { + if status.waiting() { + return Ok(()); + } + } + } + if timeout_guard.timeout_enabled() && self.regs.read_irq_status().clock_timeout() { + return Err(Error::ClockTimeout( + self.regs.read_clk_timeout_limit().value(), + )); + } + if status.tx_not_full() && current_index < len { + self.write_fifo_unchecked(output[current_index]); + current_index += 1; + } + } + } + + /// Blocking write-read transaction on the I2C bus. + pub fn write_read_blocking( + &mut self, + address: I2cAddress, + write: &[u8], + read: &mut [u8], + ) -> Result<(), Error> { + self.write_blocking_generic( + I2cCommand::Start, + address, + write, + WriteCompletionCondition::Waiting, + )?; + self.read_blocking(address, read) + } +} + +//====================================================================================== +// Embedded HAL I2C implementations +//====================================================================================== + +impl embedded_hal::i2c::ErrorType for I2cMaster { + type Error = Error; +} + +impl embedded_hal::i2c::I2c for I2cMaster { + fn transaction( + &mut self, + address: SevenBitAddress, + operations: &mut [Operation<'_>], + ) -> Result<(), Self::Error> { + for operation in operations { + match operation { + Operation::Read(buf) => self.read_blocking(I2cAddress::Regular(address), buf)?, + Operation::Write(buf) => self.write_blocking(I2cAddress::Regular(address), buf)?, + } + } + Ok(()) + } + + fn write_read( + &mut self, + address: u8, + write: &[u8], + read: &mut [u8], + ) -> Result<(), Self::Error> { + let addr = I2cAddress::Regular(address); + self.write_read_blocking(addr, write, read) + } +} + +impl embedded_hal::i2c::ErrorType for I2cMaster { + type Error = Error; +} + +impl embedded_hal::i2c::I2c for I2cMaster { + fn transaction( + &mut self, + address: TenBitAddress, + operations: &mut [Operation<'_>], + ) -> Result<(), Self::Error> { + for operation in operations { + match operation { + Operation::Read(buf) => self.read_blocking(I2cAddress::TenBit(address), buf)?, + Operation::Write(buf) => self.write_blocking(I2cAddress::TenBit(address), buf)?, + } + } + Ok(()) + } + + fn write_read( + &mut self, + address: TenBitAddress, + write: &[u8], + read: &mut [u8], + ) -> Result<(), Self::Error> { + let addr = I2cAddress::TenBit(address); + self.write_read_blocking(addr, write, read) + } +} diff --git a/vorago-shared-hal/src/i2c/regs.rs b/vorago-shared-hal/src/i2c/regs.rs new file mode 100644 index 0000000..93a7412 --- /dev/null +++ b/vorago-shared-hal/src/i2c/regs.rs @@ -0,0 +1,661 @@ +use core::marker::PhantomData; + +use arbitrary_int::{u4, u5, u9, u10, u11, u20}; + +pub use crate::shared::{FifoClear, TriggerLevel}; + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + /// I2C A base address + pub const BASE_ADDR_0: usize = 0x4006_0000; + /// I2C B base address + pub const BASE_ADDR_1: usize = 0x4006_1000; + } else if #[cfg(feature = "vor4x")] { + /// I2C 0 base address + pub const BASE_ADDR_0: usize = 0x4001_6000; + /// I2C 1 base address + pub const BASE_ADDR_1: usize = 0x4001_6400; + /// I2C 2 base address + pub const BASE_ADDR_2: usize = 0x4001_6800; + } +} + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Bank { + I2c0 = 0, + I2c1 = 1, + #[cfg(feature = "vor4x")] + I2c2 = 2, +} + +impl Bank { + /// Unsafely steal the I2C peripheral block for the given port. + /// + /// # Safety + /// + /// Circumvents ownership and safety guarantees by the HAL. + pub unsafe fn steal_regs(&self) -> MmioI2c<'static> { + I2c::new_mmio(*self) + } +} + +#[bitbybit::bitenum(u1, exhaustive = true)] +#[derive(Default, Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum TxFifoEmptyMode { + /// I2C clock is stretched until data is available. + #[default] + Stall = 0, + EndTransaction = 1, +} + +#[bitbybit::bitenum(u1, exhaustive = true)] +#[derive(Default, Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum RxFifoFullMode { + /// I2C clock is stretched until data is available. + #[default] + Stall = 0, + Nack = 1, +} + +#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] +pub struct Control { + #[bit(0, r)] + clk_enabled: bool, + #[bit(1, r)] + enabled: bool, + #[bit(2, rw)] + enable: bool, + #[bit(3, rw)] + tx_fifo_empty_mode: TxFifoEmptyMode, + #[bit(4, rw)] + rx_fifo_full_mode: RxFifoFullMode, + /// Enables the analog delay glitch filter. + #[bit(5, rw)] + analog_filter: bool, + /// Enables the digital glitch filter. + #[bit(6, rw)] + digital_filter: bool, + #[bit(8, rw)] + loopback: bool, + #[bit(9, rw)] + enable_timing_config: bool, +} + +#[derive(Debug, PartialEq, Eq)] +#[bitbybit::bitenum(u1, exhaustive = true)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum I2cSpeed { + Regular100khz = 0, + Fast400khz = 1, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))] +pub struct ClockScale { + /// Clock divide value. Reset value: 0x18. + #[bits(0..=7, rw)] + div: u8, + #[bit(31, rw)] + fastmode: I2cSpeed, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub struct Words(arbitrary_int::UInt); + +impl Words { + pub const fn new(value: u11) -> Self { + Words(arbitrary_int::UInt::::new(value.value() as u32)) + } + pub const fn value(&self) -> u11 { + u11::new(self.0.value() as u16) + } +} + +#[bitbybit::bitenum(u1, exhaustive = true)] +#[derive(Default, Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Direction { + #[default] + Send = 0, + Receive = 1, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))] +pub struct Address { + #[bit(0, rw)] + direction: Direction, + #[bits(1..=10, rw)] + address: u10, + /// Enables 10-bit addressing mode. + #[bit(15, rw)] + a10_mode: bool, +} + +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +pub struct Data(arbitrary_int::UInt); + +impl Data { + pub const fn new(value: u8) -> Self { + Data(arbitrary_int::UInt::::new(value as u32)) + } + + pub const fn data(&self) -> u8 { + self.0.value() as u8 + } +} + +#[bitbybit::bitfield(u32, default = 0x0)] +#[derive(Debug)] +pub struct Command { + #[bit(0, w)] + start: bool, + #[bit(1, w)] + stop: bool, + #[bit(2, w)] + cancel: bool, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct Status { + #[bit(0, r)] + i2c_idle: bool, + #[bit(1, r)] + idle: bool, + #[bit(2, r)] + waiting: bool, + #[bit(3, r)] + stalled: bool, + #[bit(4, r)] + arb_lost: bool, + #[bit(5, r)] + nack_addr: bool, + #[bit(6, r)] + nack_data: bool, + #[bit(8, r)] + rx_not_empty: bool, + #[bit(9, r)] + rx_full: bool, + #[bit(11, r)] + rx_trigger: bool, + #[bit(12, r)] + tx_empty: bool, + #[bit(13, r)] + tx_not_full: bool, + #[bit(15, r)] + tx_trigger: bool, + #[bit(30, r)] + raw_sda: bool, + #[bit(31, r)] + raw_scl: bool, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct State { + #[bits(0..=3, rw)] + state: u4, + #[bits(4..=7, rw)] + step: u4, + #[bits(8..=12, rw)] + rx_fifo: u5, + #[bits(14..=18, rw)] + tx_fifo: u5, + #[bits(20..=28, rw)] + bitstate: u9, +} + +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct DataCount(arbitrary_int::UInt); + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct InterruptControl { + #[bit(0, rw)] + i2c_idle: bool, + #[bit(1, rw)] + idle: bool, + #[bit(2, rw)] + waiting: bool, + #[bit(3, rw)] + stalled: bool, + #[bit(4, rw)] + arb_lost: bool, + #[bit(5, rw)] + nack_addr: bool, + #[bit(6, rw)] + nack_data: bool, + #[bit(7, rw)] + clock_timeout: bool, + #[bit(10, rw)] + tx_overflow: bool, + #[bit(11, rw)] + rx_overflow: bool, + #[bit(12, rw)] + tx_ready: bool, + #[bit(13, rw)] + rx_ready: bool, + #[bit(14, rw)] + tx_empty: bool, + #[bit(15, rw)] + rx_full: bool, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct InterruptStatus { + #[bit(0, r)] + i2c_idle: bool, + #[bit(1, r)] + idle: bool, + #[bit(2, r)] + waiting: bool, + #[bit(3, r)] + stalled: bool, + #[bit(4, r)] + arb_lost: bool, + #[bit(5, r)] + nack_addr: bool, + #[bit(6, r)] + nack_data: bool, + #[bit(7, r)] + clock_timeout: bool, + #[bit(10, r)] + tx_overflow: bool, + #[bit(11, r)] + rx_overflow: bool, + #[bit(12, r)] + tx_ready: bool, + #[bit(13, r)] + rx_ready: bool, + #[bit(14, r)] + tx_empty: bool, + #[bit(15, r)] + rx_full: bool, +} + +#[bitbybit::bitfield(u32, default = 0x0)] +#[derive(Debug)] +pub struct InterruptClear { + #[bit(7, w)] + clock_timeout: bool, + #[bit(10, w)] + tx_overflow: bool, + #[bit(11, w)] + rx_overflow: bool, +} + +#[bitbybit::bitfield(u32)] +#[derive(Debug)] +pub struct TimingConfig { + /// Rise time. + #[bits(0..=3, rw)] + t_rise: u4, + /// Fall time. + #[bits(4..=7, rw)] + t_fall: u4, + /// Duty cycle high time of SCL. + #[bits(8..=11, rw)] + t_high: u4, + /// Duty cycle low time of SCL. + #[bits(12..=15, rw)] + t_low: u4, + /// Setup time for STOP. + #[bits(16..=19, rw)] + tsu_stop: u4, + /// Setup time for START. + #[bits(20..=23, rw)] + tsu_start: u4, + /// Data hold time. + #[bits(24..=27, rw)] + thd_start: u4, + /// TBus free time between STOP and START. + #[bits(28..=31, rw)] + t_buf: u4, +} + +pub struct ClockTimeoutLimit(pub arbitrary_int::UInt); + +impl ClockTimeoutLimit { + pub fn new(value: u20) -> Self { + ClockTimeoutLimit(arbitrary_int::UInt::::new(value.value())) + } + pub fn value(&self) -> u20 { + self.0 + } +} + +pub mod slave { + use super::{Data, DataCount, FifoClear, RxFifoFullMode, TriggerLevel, TxFifoEmptyMode}; + use arbitrary_int::{u3, u4, u5, u10, u11}; + + #[bitbybit::bitfield(u32)] + #[derive(Debug)] + pub struct Control { + #[bit(0, r)] + clk_enabled: bool, + #[bit(1, r)] + enabled: bool, + #[bit(2, rw)] + enable: bool, + #[bit(3, rw)] + tx_fifo_empty_mode: TxFifoEmptyMode, + #[bit(4, rw)] + rx_fifo_full_mode: RxFifoFullMode, + } + + #[bitbybit::bitfield(u32)] + #[derive(Debug)] + pub struct Maxwords { + #[bits(0..=10, rw)] + maxwords: u11, + #[bit(31, rw)] + enable: bool, + } + + #[bitbybit::bitfield(u32)] + #[derive(Debug)] + pub struct Address { + #[bit(0, rw)] + rw: bool, + #[bits(1..=10, rw)] + address: u10, + #[bit(15, rw)] + a10_mode: bool, + } + + #[bitbybit::bitfield(u32)] + #[derive(Debug)] + pub struct AddressMask { + /// Will normally be 0 to match both read and write addresses. + #[bit(0, rw)] + rw_mask: bool, + /// Reset value 0x3FF. + #[bits(1..=10, rw)] + mask: u10, + } + + #[bitbybit::bitenum(u1, exhaustive = true)] + #[derive(Default, Debug, PartialEq, Eq)] + pub enum Direction { + #[default] + MasterSend = 0, + MasterReceive = 1, + } + + #[bitbybit::bitfield(u32)] + #[derive(Debug)] + pub struct LastAddress { + #[bit(0, rw)] + direction: Direction, + #[bits(1..=10, rw)] + address: u10, + } + + #[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] + pub struct Status { + #[bit(0, r)] + completed: bool, + #[bit(1, r)] + idle: bool, + #[bit(2, r)] + waiting: bool, + #[bit(3, r)] + tx_stalled: bool, + #[bit(4, r)] + rx_stalled: bool, + #[bit(5, r)] + address_match: bool, + #[bit(6, r)] + nack_data: bool, + #[bit(7, r)] + rx_data_first: bool, + #[bit(8, r)] + rx_not_empty: bool, + #[bit(9, r)] + rx_full: bool, + #[bit(11, r)] + rx_trigger: bool, + #[bit(12, r)] + tx_empty: bool, + #[bit(13, r)] + tx_not_full: bool, + #[bit(15, r)] + tx_trigger: bool, + #[bit(28, r)] + raw_busy: bool, + #[bit(30, r)] + raw_sda: bool, + #[bit(31, r)] + raw_scl: bool, + } + + #[bitbybit::bitfield(u32)] + #[derive(Debug)] + pub struct State { + #[bits(0..=2, rw)] + state: u3, + #[bits(4..=7, rw)] + step: u4, + #[bits(8..=12, rw)] + rx_fifo: u5, + #[bits(14..=18, rw)] + tx_fifo: u5, + } + + #[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] + pub struct InterruptControl { + #[bit(0, rw)] + completed: bool, + #[bit(1, rw)] + idle: bool, + #[bit(2, rw)] + waiting: bool, + #[bit(3, rw)] + tx_stalled: bool, + #[bit(4, rw)] + rx_stalled: bool, + #[bit(5, rw)] + address_match: bool, + #[bit(6, rw)] + nack_data: bool, + #[bit(7, rw)] + rx_data_first: bool, + + #[bit(8, rw)] + i2c_start: bool, + #[bit(9, rw)] + i2c_stop: bool, + #[bit(10, rw)] + tx_underflow: bool, + #[bit(11, rw)] + rx_underflow: bool, + #[bit(12, rw)] + tx_ready: bool, + #[bit(13, rw)] + rx_ready: bool, + #[bit(14, rw)] + tx_empty: bool, + #[bit(15, rw)] + rx_full: bool, + } + + #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] + pub struct InterruptStatus { + #[bit(0, r)] + completed: bool, + #[bit(1, r)] + idle: bool, + #[bit(2, r)] + waiting: bool, + #[bit(3, r)] + tx_stalled: bool, + #[bit(4, r)] + rx_stalled: bool, + #[bit(5, r)] + address_match: bool, + #[bit(6, r)] + nack_data: bool, + #[bit(7, r)] + rx_data_first: bool, + + #[bit(8, r)] + i2c_start: bool, + #[bit(9, r)] + i2c_stop: bool, + #[bit(10, r)] + tx_underflow: bool, + #[bit(11, r)] + rx_underflow: bool, + #[bit(12, r)] + tx_ready: bool, + #[bit(13, r)] + rx_ready: bool, + #[bit(14, r)] + tx_empty: bool, + #[bit(15, r)] + rx_full: bool, + } + + #[bitbybit::bitfield(u32, default = 0x0)] + #[derive(Debug)] + pub struct InterruptClear { + #[bit(0, w)] + completed: bool, + #[bit(1, w)] + idle: bool, + #[bit(2, w)] + waiting: bool, + #[bit(3, w)] + tx_stalled: bool, + #[bit(4, w)] + rx_stalled: bool, + #[bit(5, w)] + address_match: bool, + #[bit(6, w)] + nack_data: bool, + #[bit(7, w)] + rx_data_first: bool, + + #[bit(8, w)] + i2c_start: bool, + #[bit(9, w)] + i2c_stop: bool, + #[bit(10, w)] + tx_underflow: bool, + #[bit(11, w)] + rx_underflow: bool, + #[bit(12, w)] + tx_ready: bool, + #[bit(13, w)] + rx_ready: bool, + #[bit(14, w)] + tx_empty: bool, + #[bit(15, w)] + rx_full: bool, + } + + #[derive(derive_mmio::Mmio)] + #[repr(C)] + pub struct I2cSlave { + s0_ctrl: Control, + s0_maxwords: Maxwords, + s0_address: Address, + s0_addressmask: AddressMask, + s0_data: Data, + s0_lastaddress: LastAddress, + #[mmio(PureRead)] + s0_status: Status, + #[mmio(PureRead)] + s0_state: State, + #[mmio(PureRead)] + s0_tx_count: DataCount, + #[mmio(PureRead)] + s0_rx_count: DataCount, + s0_irq_enb: InterruptControl, + #[mmio(PureRead)] + s0_irq_raw: InterruptStatus, + #[mmio(PureRead)] + s0_irq_status: InterruptStatus, + #[mmio(Write)] + s0_irq_clear: InterruptClear, + s0_rx_fifo_trigger: TriggerLevel, + s0_tx_fifo_trigger: TriggerLevel, + #[mmio(Write)] + s0_fifo_clear: FifoClear, + s0_address_b: Address, + s0_addressmask_b: AddressMask, + } +} +#[derive(derive_mmio::Mmio)] +#[mmio(no_ctors)] +#[repr(C)] +pub struct I2c { + control: Control, + clkscale: ClockScale, + words: Words, + address: Address, + data: Data, + #[mmio(Write)] + cmd: Command, + #[mmio(PureRead)] + status: Status, + #[mmio(PureRead)] + state: State, + #[mmio(PureRead)] + tx_count: DataCount, + #[mmio(PureRead)] + rx_count: DataCount, + irq_enb: InterruptControl, + #[mmio(PureRead)] + irq_raw: InterruptStatus, + #[mmio(PureRead)] + irq_status: InterruptStatus, + #[mmio(Write)] + irq_clear: InterruptClear, + rx_fifo_trigger: TriggerLevel, + tx_fifo_trigger: TriggerLevel, + #[mmio(Write)] + fifo_clear: FifoClear, + timing_config: TimingConfig, + clk_timeout_limit: ClockTimeoutLimit, + + _reserved_0: [u32; 0x2D], + + #[mmio(Inner)] + slave: slave::I2cSlave, + + #[cfg(feature = "vor1x")] + _reserved_1: [u32; 0x3AC], + #[cfg(feature = "vor4x")] + _reserved_1: [u32; 0xAC], + + /// Vorago 4x: 0x0214_07E9. Vorago 1x: 0x0014_07E1. + #[mmio(PureRead)] + perid: u32, +} + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + static_assertions::const_assert_eq!(core::mem::size_of::(), 0x1000); + } else if #[cfg(feature = "vor4x")] { + static_assertions::const_assert_eq!(core::mem::size_of::(), 0x400); + } +} + +impl I2c { + fn new_mmio_at(base: usize) -> MmioI2c<'static> { + MmioI2c { + ptr: base as *mut _, + phantom: PhantomData, + } + } + + pub fn new_mmio(bank: Bank) -> MmioI2c<'static> { + match bank { + Bank::I2c0 => Self::new_mmio_at(BASE_ADDR_0), + Bank::I2c1 => Self::new_mmio_at(BASE_ADDR_1), + #[cfg(feature = "vor4x")] + Bank::I2c2 => Self::new_mmio_at(BASE_ADDR_2), + } + } +} diff --git a/vorago-shared-hal/src/ioconfig/mod.rs b/vorago-shared-hal/src/ioconfig/mod.rs new file mode 100644 index 0000000..b368ea1 --- /dev/null +++ b/vorago-shared-hal/src/ioconfig/mod.rs @@ -0,0 +1,3 @@ +pub use regs::{FilterClockSelect, FilterType}; + +pub mod regs; diff --git a/vorago-shared-hal/src/ioconfig/regs.rs b/vorago-shared-hal/src/ioconfig/regs.rs new file mode 100644 index 0000000..6798c31 --- /dev/null +++ b/vorago-shared-hal/src/ioconfig/regs.rs @@ -0,0 +1,179 @@ +use core::marker::PhantomData; + +use crate::{NUM_PORT_A, NUM_PORT_B, gpio::DynPinId}; +#[cfg(feature = "vor4x")] +use crate::{NUM_PORT_DEFAULT, NUM_PORT_G}; + +#[cfg(feature = "vor1x")] +pub const BASE_ADDR: usize = 0x4000_2000; +#[cfg(feature = "vor4x")] +pub const BASE_ADDR: usize = 0x4001_1000; + +#[bitbybit::bitenum(u3)] +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilterType { + SysClk = 0, + DirectInput = 1, + FilterOneCycle = 2, + FilterTwoCycles = 3, + FilterThreeCycles = 4, + FilterFourCycles = 5, +} + +#[derive(Debug, PartialEq, Eq)] +#[bitbybit::bitenum(u3, exhaustive = true)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FilterClockSelect { + SysClk = 0, + Clk1 = 1, + Clk2 = 2, + Clk3 = 3, + Clk4 = 4, + Clk5 = 5, + Clk6 = 6, + Clk7 = 7, +} + +#[derive(Debug, PartialEq, Eq)] +#[bitbybit::bitenum(u1, exhaustive = true)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pull { + Up = 0, + Down = 1, +} + +#[derive(Debug, Eq, PartialEq)] +#[bitbybit::bitenum(u2, exhaustive = true)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FunctionSelect { + Sel0 = 0b00, + Sel1 = 0b01, + Sel2 = 0b10, + Sel3 = 0b11, +} + +#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] +pub struct Config { + #[bit(16, rw)] + io_disable: bool, + #[bits(13..=14, rw)] + funsel: FunctionSelect, + #[bit(12, rw)] + pull_when_output_active: bool, + #[bit(11, rw)] + pull_enable: bool, + #[bit(10, rw)] + pull_dir: Pull, + #[bit(9, rw)] + invert_output: bool, + #[bit(8, rw)] + open_drain: bool, + /// IEWO bit. Allows monitoring of output values. + #[bit(7, rw)] + input_enable_when_output: bool, + #[bit(6, rw)] + invert_input: bool, + #[bits(3..=5, rw)] + filter_clk_sel: FilterClockSelect, + #[bits(0..=2, rw)] + filter_type: Option, +} + +#[derive(derive_mmio::Mmio)] +#[mmio(no_ctors)] +#[repr(C)] +pub struct IoConfig { + port_a: [Config; NUM_PORT_A], + port_b: [Config; NUM_PORT_B], + #[cfg(feature = "vor4x")] + port_c: [Config; NUM_PORT_DEFAULT], + #[cfg(feature = "vor4x")] + port_d: [Config; NUM_PORT_DEFAULT], + #[cfg(feature = "vor4x")] + port_e: [Config; NUM_PORT_DEFAULT], + #[cfg(feature = "vor4x")] + port_f: [Config; NUM_PORT_DEFAULT], + #[cfg(feature = "vor4x")] + port_g: [Config; NUM_PORT_G], + #[cfg(feature = "vor4x")] + _reserved0: [u32; 0x8], + #[cfg(feature = "vor4x")] + #[mmio(PureRead)] + clk_div_0: u32, + #[cfg(feature = "vor4x")] + clk_div_1: u32, + #[cfg(feature = "vor4x")] + clk_div_2: u32, + #[cfg(feature = "vor4x")] + clk_div_3: u32, + #[cfg(feature = "vor4x")] + clk_div_4: u32, + #[cfg(feature = "vor4x")] + clk_div_5: u32, + #[cfg(feature = "vor4x")] + clk_div_6: u32, + #[cfg(feature = "vor4x")] + clk_div_7: u32, + #[cfg(feature = "vor4x")] + _reserved1: [u32; 0x387], + #[cfg(feature = "vor1x")] + _reserved1: [u32; 0x3c7], + #[mmio(PureRead)] + /// Reset value: 0x0282_07E9 for Vorago 4x, and 0x0182_07E1 for Vorago 1x + perid: u32, +} + +static_assertions::const_assert_eq!(core::mem::size_of::(), 0x1000); + +impl IoConfig { + pub const fn new_mmio() -> MmioIoConfig<'static> { + MmioIoConfig { + ptr: BASE_ADDR as *mut _, + phantom: PhantomData, + } + } +} + +impl MmioIoConfig<'_> { + pub fn read_pin_config(&self, id: DynPinId) -> Config { + let offset = id.offset(); + match id.port() { + crate::Port::A => unsafe { self.read_port_a_unchecked(offset) }, + crate::Port::B => unsafe { self.read_port_b_unchecked(offset) }, + #[cfg(feature = "vor4x")] + crate::Port::C => unsafe { self.read_port_c_unchecked(offset) }, + #[cfg(feature = "vor4x")] + crate::Port::D => unsafe { self.read_port_d_unchecked(offset) }, + #[cfg(feature = "vor4x")] + crate::Port::E => unsafe { self.read_port_e_unchecked(offset) }, + #[cfg(feature = "vor4x")] + crate::Port::F => unsafe { self.read_port_f_unchecked(offset) }, + #[cfg(feature = "vor4x")] + crate::Port::G => unsafe { self.read_port_g_unchecked(offset) }, + } + } + + pub fn modify_pin_config Config>(&mut self, id: DynPinId, f: F) { + let config = self.read_pin_config(id); + self.write_pin_config(id, f(config)) + } + + pub fn write_pin_config(&mut self, id: DynPinId, config: Config) { + let offset = id.offset(); + match id.port() { + crate::Port::A => unsafe { self.write_port_a_unchecked(offset, config) }, + crate::Port::B => unsafe { self.write_port_b_unchecked(offset, config) }, + #[cfg(feature = "vor4x")] + crate::Port::C => unsafe { self.write_port_c_unchecked(offset, config) }, + #[cfg(feature = "vor4x")] + crate::Port::D => unsafe { self.write_port_d_unchecked(offset, config) }, + #[cfg(feature = "vor4x")] + crate::Port::E => unsafe { self.write_port_e_unchecked(offset, config) }, + #[cfg(feature = "vor4x")] + crate::Port::F => unsafe { self.write_port_f_unchecked(offset, config) }, + #[cfg(feature = "vor4x")] + crate::Port::G => unsafe { self.write_port_g_unchecked(offset, config) }, + } + } +} diff --git a/vorago-shared-hal/src/lib.rs b/vorago-shared-hal/src/lib.rs new file mode 100644 index 0000000..f0ccf26 --- /dev/null +++ b/vorago-shared-hal/src/lib.rs @@ -0,0 +1,228 @@ +//! Shared HAL code for Vorago VA108xx and VA416xx microcontrollers. +#![no_std] +#[cfg(feature = "vor4x")] +pub mod clock; +pub mod embassy; +pub mod gpio; +pub mod i2c; +pub mod ioconfig; +pub mod pins; +pub mod pwm; +pub mod spi; +pub mod sysconfig; +pub mod time; +pub mod timer; +pub mod uart; + +pub use sysconfig::{ + assert_peripheral_reset, deassert_peripheral_reset, disable_peripheral_clock, + enable_peripheral_clock, reset_peripheral_for_cycles, +}; + +#[cfg(not(feature = "_family-selected"))] +compile_error!("no Vorago CPU family was select. Choices: vor1x or vor4x"); + +pub use ioconfig::regs::FunctionSelect; +#[cfg(feature = "vor1x")] +use va108xx as pac; +#[cfg(feature = "vor4x")] +use va416xx as pac; + +#[cfg(feature = "vor1x")] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum PeripheralSelect { + PortA = 0, + PortB = 1, + Spi0 = 4, + Spi1 = 5, + Spi2 = 6, + Uart0 = 8, + Uart1 = 9, + I2c0 = 16, + I2c1 = 17, + Irqsel = 21, + IoConfig = 22, + Utility = 23, + Gpio = 24, +} + +#[cfg(feature = "vor4x")] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum PeripheralSelect { + Spi0 = 0, + Spi1 = 1, + Spi2 = 2, + Spi3 = 3, + Uart0 = 4, + Uart1 = 5, + Uart2 = 6, + I2c0 = 7, + I2c1 = 8, + I2c2 = 9, + Can0 = 10, + Can1 = 11, + Rng = 12, + Adc = 13, + Dac = 14, + Dma = 15, + Ebi = 16, + Eth = 17, + Spw = 18, + Clkgen = 19, + IrqRouter = 20, + IoConfig = 21, + Utility = 22, + Watchdog = 23, + PortA = 24, + PortB = 25, + PortC = 26, + PortD = 27, + PortE = 28, + PortF = 29, + PortG = 30, +} + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + /// Number of GPIO ports and IOCONFIG registers for PORT A + pub const NUM_PORT_A: usize = 32; + /// Number of GPIO ports and IOCONFIG registers for PORT B + pub const NUM_PORT_B: usize = 24; + } else if #[cfg(feature = "vor4x")] { + /// Number of GPIO ports and IOCONFIG registers for PORT C to Port F + pub const NUM_PORT_DEFAULT: usize = 16; + /// Number of GPIO ports and IOCONFIG registers for PORT A + pub const NUM_PORT_A: usize = NUM_PORT_DEFAULT; + /// Number of GPIO ports and IOCONFIG registers for PORT B + pub const NUM_PORT_B: usize = NUM_PORT_DEFAULT; + /// Number of GPIO ports and IOCONFIG registers for PORT G + pub const NUM_PORT_G: usize = 8; + } +} + +/// GPIO port enumeration. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Port { + A = 0, + B = 1, + #[cfg(feature = "vor4x")] + C = 2, + #[cfg(feature = "vor4x")] + D = 3, + #[cfg(feature = "vor4x")] + E = 4, + #[cfg(feature = "vor4x")] + F = 5, + #[cfg(feature = "vor4x")] + G = 6, +} + +impl Port { + pub const fn max_offset(&self) -> usize { + match self { + Port::A => NUM_PORT_A, + Port::B => NUM_PORT_B, + #[cfg(feature = "vor4x")] + Port::C | Port::D | Port::E | Port::F => NUM_PORT_DEFAULT, + #[cfg(feature = "vor4x")] + Port::G => NUM_PORT_G, + } + } + + /// Unsafely steal the GPIO peripheral block for the given port. + /// + /// # Safety + /// + /// Circumvents ownership and safety guarantees by the HAL. + pub unsafe fn steal_gpio(&self) -> gpio::regs::MmioGpio<'static> { + gpio::regs::Gpio::new_mmio(*self) + } +} + +#[derive(Debug, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("invalid GPIO offset {offset} for port {port:?}")] +pub struct InvalidOffsetError { + offset: usize, + port: Port, +} + +/// Generic interrupt config which can be used to specify whether the HAL driver will +/// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the +/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might want to +/// perform those steps themselves. +#[cfg(feature = "vor1x")] +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InterruptConfig { + /// Interrupt target vector. Should always be set, might be required for disabling IRQs + pub id: va108xx::Interrupt, + /// Specfiy whether IRQ should be routed to an IRQ vector using the IRQSEL peripheral. + pub route: bool, + /// Specify whether the IRQ is unmasked in the Cortex-M NVIC. If an interrupt is used for + /// multiple purposes, the user can enable the interrupts themselves. + pub enable_in_nvic: bool, +} + +#[cfg(feature = "vor1x")] +impl InterruptConfig { + pub fn new(id: va108xx::Interrupt, route: bool, enable_in_nvic: bool) -> Self { + InterruptConfig { + id, + route, + enable_in_nvic, + } + } +} + +/// Enable a specific interrupt using the NVIC peripheral. +/// +/// # Safety +/// +/// This function is `unsafe` because it can break mask-based critical sections. +#[inline] +pub unsafe fn enable_nvic_interrupt(irq: pac::Interrupt) { + unsafe { + cortex_m::peripheral::NVIC::unmask(irq); + } +} + +/// Disable a specific interrupt using the NVIC peripheral. +#[inline] +pub fn disable_nvic_interrupt(irq: pac::Interrupt) { + cortex_m::peripheral::NVIC::mask(irq); +} + +#[allow(dead_code)] +pub(crate) mod sealed { + pub trait Sealed {} +} + +pub(crate) mod shared { + use arbitrary_int::u5; + + #[derive(Debug)] + pub struct TriggerLevel(arbitrary_int::UInt); + + impl TriggerLevel { + pub const fn new(value: u5) -> Self { + TriggerLevel(arbitrary_int::UInt::::new(value.value() as u32)) + } + + pub const fn value(&self) -> u5 { + u5::new(self.0.value() as u8) + } + } + + #[bitbybit::bitfield(u32, default = 0x0)] + #[derive(Debug)] + pub struct FifoClear { + #[bit(1, w)] + tx_fifo: bool, + #[bit(0, w)] + rx_fifo: bool, + } +} diff --git a/vorago-shared-hal/src/pins.rs b/vorago-shared-hal/src/pins.rs new file mode 100644 index 0000000..3269348 --- /dev/null +++ b/vorago-shared-hal/src/pins.rs @@ -0,0 +1,751 @@ +use crate::sysconfig::reset_peripheral_for_cycles; + +pub use crate::gpio::{DynPinId, Port}; + +use crate::PeripheralSelect; +use crate::sealed::Sealed; +#[cfg(feature = "vor1x")] +use va108xx as pac; +#[cfg(feature = "vor4x")] +use va416xx as pac; + +/// Trait implemented by data structures associated with pin identification. +pub trait PinId { + const ID: crate::gpio::ll::DynPinId; +} + +pub trait AnyPin: Sealed { + const ID: DynPinId; +} + +/// Primary Pin structure for the physical pins exposed by Vorago MCUs. +/// +/// This pin structure is only used for resource management and does not do anything on its +/// own. +pub struct Pin { + phantom: core::marker::PhantomData, +} + +impl AnyPin for Pin { + const ID: DynPinId = Id::ID; +} + +impl Pin { + #[allow(clippy::new_without_default)] + #[doc(hidden)] + pub const fn __new() -> Self { + Self { + phantom: core::marker::PhantomData, + } + } + + /// Create a new pin instance. + /// + /// # Safety + /// + /// This circumvents ownership rules of the HAL and allows creating multiple instances + /// of the same pin. + pub const unsafe fn steal() -> Self { + Self::__new() + } +} + +macro_rules! pin_id { + ($Id:ident, $Port:path, $num:literal) => { + // Need paste macro to use ident in doc attribute + paste::paste! { + #[doc = "Pin ID representing pin " $Id] + #[derive(Debug)] + pub enum $Id {} + + impl $crate::sealed::Sealed for $Id {} + impl PinId for $Id { + const ID: DynPinId = DynPinId::new_unchecked($Port, $num); + } + } + }; +} + +impl Sealed for Pin {} + +pin_id!(Pa0, Port::A, 0); +pin_id!(Pa1, Port::A, 1); +pin_id!(Pa2, Port::A, 2); +pin_id!(Pa3, Port::A, 3); +pin_id!(Pa4, Port::A, 4); +pin_id!(Pa5, Port::A, 5); +pin_id!(Pa6, Port::A, 6); +pin_id!(Pa7, Port::A, 7); +pin_id!(Pa8, Port::A, 8); +pin_id!(Pa9, Port::A, 9); +pin_id!(Pa10, Port::A, 10); +pin_id!(Pa11, Port::A, 11); +pin_id!(Pa12, Port::A, 12); +pin_id!(Pa13, Port::A, 13); +pin_id!(Pa14, Port::A, 14); +pin_id!(Pa15, Port::A, 15); +#[cfg(feature = "vor1x")] +pin_id!(Pa16, Port::A, 16); +#[cfg(feature = "vor1x")] +pin_id!(Pa17, Port::A, 17); +#[cfg(feature = "vor1x")] +pin_id!(Pa18, Port::A, 18); +#[cfg(feature = "vor1x")] +pin_id!(Pa19, Port::A, 19); +#[cfg(feature = "vor1x")] +pin_id!(Pa20, Port::A, 20); +#[cfg(feature = "vor1x")] +pin_id!(Pa21, Port::A, 21); +#[cfg(feature = "vor1x")] +pin_id!(Pa22, Port::A, 22); +#[cfg(feature = "vor1x")] +pin_id!(Pa23, Port::A, 23); +#[cfg(feature = "vor1x")] +pin_id!(Pa24, Port::A, 24); +#[cfg(feature = "vor1x")] +pin_id!(Pa25, Port::A, 25); +#[cfg(feature = "vor1x")] +pin_id!(Pa26, Port::A, 26); +#[cfg(feature = "vor1x")] +#[cfg(feature = "vor1x")] +pin_id!(Pa27, Port::A, 27); +#[cfg(feature = "vor1x")] +pin_id!(Pa28, Port::A, 28); +#[cfg(feature = "vor1x")] +pin_id!(Pa29, Port::A, 29); +#[cfg(feature = "vor1x")] +pin_id!(Pa30, Port::A, 30); +#[cfg(feature = "vor1x")] +pin_id!(Pa31, Port::A, 31); + +pin_id!(Pb0, Port::B, 0); +pin_id!(Pb1, Port::B, 1); +pin_id!(Pb2, Port::B, 2); +pin_id!(Pb3, Port::B, 3); +pin_id!(Pb4, Port::B, 4); +#[cfg(not(feature = "va41628"))] +pin_id!(Pb5, Port::B, 5); +#[cfg(not(feature = "va41628"))] +pin_id!(Pb6, Port::B, 6); +#[cfg(not(feature = "va41628"))] +pin_id!(Pb7, Port::B, 7); +#[cfg(not(feature = "va41628"))] +pin_id!(Pb8, Port::B, 8); +#[cfg(not(feature = "va41628"))] +pin_id!(Pb9, Port::B, 9); +#[cfg(not(feature = "va41628"))] +pin_id!(Pb10, Port::B, 10); +#[cfg(not(feature = "va41628"))] +pin_id!(Pb11, Port::B, 11); +pin_id!(Pb12, Port::B, 12); +pin_id!(Pb13, Port::B, 13); +pin_id!(Pb14, Port::B, 14); +pin_id!(Pb15, Port::B, 15); +#[cfg(feature = "vor1x")] +pin_id!(Pb16, Port::B, 16); +#[cfg(feature = "vor1x")] +pin_id!(Pb17, Port::B, 17); +#[cfg(feature = "vor1x")] +pin_id!(Pb18, Port::B, 18); +#[cfg(feature = "vor1x")] +pin_id!(Pb19, Port::B, 19); +#[cfg(feature = "vor1x")] +pin_id!(Pb20, Port::B, 20); +#[cfg(feature = "vor1x")] +pin_id!(Pb21, Port::B, 21); +#[cfg(feature = "vor1x")] +pin_id!(Pb22, Port::B, 22); +#[cfg(feature = "vor1x")] +pin_id!(Pb23, Port::B, 23); + +cfg_if::cfg_if! { + if #[cfg(feature = "vor4x")] { + pin_id!(Pc0, Port::C, 0); + pin_id!(Pc1, Port::C, 1); + pin_id!(Pc2, Port::C, 2); + pin_id!(Pc3, Port::C, 3); + pin_id!(Pc4, Port::C, 4); + pin_id!(Pc5, Port::C, 5); + pin_id!(Pc6, Port::C, 6); + pin_id!(Pc7, Port::C, 7); + pin_id!(Pc8, Port::C, 8); + pin_id!(Pc9, Port::C, 9); + pin_id!(Pc10, Port::C, 10); + pin_id!(Pc11, Port::C, 11); + pin_id!(Pc12, Port::C, 12); + #[cfg(not(feature = "va41628"))] + pin_id!(Pc13, Port::C, 13); + pin_id!(Pc14, Port::C, 14); + #[cfg(not(feature = "va41628"))] + pin_id!(Pc15, Port::C, 15); + + #[cfg(not(feature = "va41628"))] + pin_id!(Pd0, Port::D, 0); + #[cfg(not(feature = "va41628"))] + pin_id!(Pd1, Port::D, 1); + #[cfg(not(feature = "va41628"))] + pin_id!(Pd2, Port::D, 2); + #[cfg(not(feature = "va41628"))] + pin_id!(Pd3, Port::D, 3); + #[cfg(not(feature = "va41628"))] + pin_id!(Pd4, Port::D, 4); + #[cfg(not(feature = "va41628"))] + pin_id!(Pd5, Port::D, 5); + #[cfg(not(feature = "va41628"))] + pin_id!(Pd6, Port::D, 6); + #[cfg(not(feature = "va41628"))] + pin_id!(Pd7, Port::D, 7); + #[cfg(not(feature = "va41628"))] + pin_id!(Pd8, Port::D, 8); + #[cfg(not(feature = "va41628"))] + pin_id!(Pd9, Port::D, 9); + pin_id!(Pd10, Port::D, 10); + pin_id!(Pd11, Port::D, 11); + pin_id!(Pd12, Port::D, 12); + pin_id!(Pd13, Port::D, 13); + pin_id!(Pd14, Port::D, 14); + pin_id!(Pd15, Port::D, 15); + + pin_id!(Pe0, Port::E, 0); + pin_id!(Pe1, Port::E, 1); + pin_id!(Pe2, Port::E, 2); + pin_id!(Pe3, Port::E, 3); + pin_id!(Pe4, Port::E, 4); + pin_id!(Pe5, Port::E, 5); + pin_id!(Pe6, Port::E, 6); + pin_id!(Pe7, Port::E, 7); + pin_id!(Pe8, Port::E, 8); + pin_id!(Pe9, Port::E, 9); + #[cfg(not(feature = "va41628"))] + pin_id!(Pe10, Port::E, 10); + #[cfg(not(feature = "va41628"))] + pin_id!(Pe11, Port::E, 11); + pin_id!(Pe12, Port::E, 12); + pin_id!(Pe13, Port::E, 13); + pin_id!(Pe14, Port::E, 14); + pin_id!(Pe15, Port::E, 15); + + pin_id!(Pf0, Port::F, 0); + pin_id!(Pf1, Port::F, 1); + #[cfg(not(feature = "va41628"))] + pin_id!(Pf2, Port::F, 2); + #[cfg(not(feature = "va41628"))] + pin_id!(Pf3, Port::F, 3); + #[cfg(not(feature = "va41628"))] + pin_id!(Pf4, Port::F, 4); + #[cfg(not(feature = "va41628"))] + pin_id!(Pf5, Port::F, 5); + #[cfg(not(feature = "va41628"))] + pin_id!(Pf6, Port::F, 6); + #[cfg(not(feature = "va41628"))] + pin_id!(Pf7, Port::F, 7); + #[cfg(not(feature = "va41628"))] + pin_id!(Pf8, Port::F, 8); + pin_id!(Pf9, Port::F, 9); + #[cfg(not(feature = "va41628"))] + pin_id!(Pf10, Port::F, 10); + pin_id!(Pf11, Port::F, 11); + pin_id!(Pf12, Port::F, 12); + pin_id!(Pf13, Port::F, 13); + pin_id!(Pf14, Port::F, 14); + pin_id!(Pf15, Port::F, 15); + + pin_id!(Pg0, Port::G, 0); + pin_id!(Pg1, Port::G, 1); + pin_id!(Pg2, Port::G, 2); + pin_id!(Pg3, Port::G, 3); + pin_id!(Pg4, Port::G, 4); + pin_id!(Pg5, Port::G, 5); + pin_id!(Pg6, Port::G, 6); + pin_id!(Pg7, Port::G, 7); + } +} + +/// Resource management singleton for GPIO PORT A. +pub struct PinsA { + pub pa0: Pin, + pub pa1: Pin, + pub pa2: Pin, + pub pa3: Pin, + pub pa4: Pin, + pub pa5: Pin, + pub pa6: Pin, + pub pa7: Pin, + pub pa8: Pin, + pub pa9: Pin, + pub pa10: Pin, + pub pa11: Pin, + pub pa12: Pin, + pub pa13: Pin, + pub pa14: Pin, + pub pa15: Pin, + #[cfg(feature = "vor1x")] + pub pa16: Pin, + #[cfg(feature = "vor1x")] + pub pa17: Pin, + #[cfg(feature = "vor1x")] + pub pa18: Pin, + #[cfg(feature = "vor1x")] + pub pa19: Pin, + #[cfg(feature = "vor1x")] + pub pa20: Pin, + #[cfg(feature = "vor1x")] + pub pa21: Pin, + #[cfg(feature = "vor1x")] + pub pa22: Pin, + #[cfg(feature = "vor1x")] + pub pa23: Pin, + #[cfg(feature = "vor1x")] + pub pa24: Pin, + #[cfg(feature = "vor1x")] + pub pa25: Pin, + #[cfg(feature = "vor1x")] + pub pa26: Pin, + #[cfg(feature = "vor1x")] + pub pa27: Pin, + #[cfg(feature = "vor1x")] + pub pa28: Pin, + #[cfg(feature = "vor1x")] + pub pa29: Pin, + #[cfg(feature = "vor1x")] + pub pa30: Pin, + #[cfg(feature = "vor1x")] + pub pa31: Pin, +} + +impl PinsA { + pub fn new(_port_a: pac::Porta) -> Self { + let syscfg = unsafe { pac::Sysconfig::steal() }; + reset_peripheral_for_cycles(PeripheralSelect::PortA, 2); + syscfg.peripheral_clk_enable().modify(|_, w| { + w.porta().set_bit(); + #[cfg(feature = "vor1x")] + w.gpio().set_bit(); + w.ioconfig().set_bit() + }); + Self { + pa0: Pin::__new(), + pa1: Pin::__new(), + pa2: Pin::__new(), + pa3: Pin::__new(), + pa4: Pin::__new(), + pa5: Pin::__new(), + pa6: Pin::__new(), + pa7: Pin::__new(), + pa8: Pin::__new(), + pa9: Pin::__new(), + pa10: Pin::__new(), + pa11: Pin::__new(), + pa12: Pin::__new(), + pa13: Pin::__new(), + pa14: Pin::__new(), + pa15: Pin::__new(), + #[cfg(feature = "vor1x")] + pa16: Pin::__new(), + #[cfg(feature = "vor1x")] + pa17: Pin::__new(), + #[cfg(feature = "vor1x")] + pa18: Pin::__new(), + #[cfg(feature = "vor1x")] + pa19: Pin::__new(), + #[cfg(feature = "vor1x")] + pa20: Pin::__new(), + #[cfg(feature = "vor1x")] + pa21: Pin::__new(), + #[cfg(feature = "vor1x")] + pa22: Pin::__new(), + #[cfg(feature = "vor1x")] + pa23: Pin::__new(), + #[cfg(feature = "vor1x")] + pa24: Pin::__new(), + #[cfg(feature = "vor1x")] + pa25: Pin::__new(), + #[cfg(feature = "vor1x")] + pa26: Pin::__new(), + #[cfg(feature = "vor1x")] + pa27: Pin::__new(), + #[cfg(feature = "vor1x")] + pa28: Pin::__new(), + #[cfg(feature = "vor1x")] + pa29: Pin::__new(), + #[cfg(feature = "vor1x")] + pa30: Pin::__new(), + #[cfg(feature = "vor1x")] + pa31: Pin::__new(), + } + } +} + +/// Resource management singleton for GPIO PORT B. +pub struct PinsB { + pub pb0: Pin, + pub pb1: Pin, + pub pb2: Pin, + pub pb3: Pin, + pub pb4: Pin, + #[cfg(not(feature = "va41628"))] + pub pb5: Pin, + #[cfg(not(feature = "va41628"))] + pub pb6: Pin, + #[cfg(not(feature = "va41628"))] + pub pb7: Pin, + #[cfg(not(feature = "va41628"))] + pub pb8: Pin, + #[cfg(not(feature = "va41628"))] + pub pb9: Pin, + #[cfg(not(feature = "va41628"))] + pub pb10: Pin, + #[cfg(not(feature = "va41628"))] + pub pb11: Pin, + pub pb12: Pin, + pub pb13: Pin, + pub pb14: Pin, + pub pb15: Pin, + #[cfg(feature = "vor1x")] + pub pb16: Pin, + #[cfg(feature = "vor1x")] + pub pb17: Pin, + #[cfg(feature = "vor1x")] + pub pb18: Pin, + #[cfg(feature = "vor1x")] + pub pb19: Pin, + #[cfg(feature = "vor1x")] + pub pb20: Pin, + #[cfg(feature = "vor1x")] + pub pb21: Pin, + #[cfg(feature = "vor1x")] + pub pb22: Pin, + #[cfg(feature = "vor1x")] + pub pb23: Pin, +} + +impl PinsB { + pub fn new(_port_b: pac::Portb) -> Self { + let syscfg = unsafe { pac::Sysconfig::steal() }; + reset_peripheral_for_cycles(PeripheralSelect::PortB, 2); + syscfg.peripheral_clk_enable().modify(|_, w| { + w.portb().set_bit(); + #[cfg(feature = "vor1x")] + w.gpio().set_bit(); + w.ioconfig().set_bit() + }); + Self { + pb0: Pin::__new(), + pb1: Pin::__new(), + pb2: Pin::__new(), + pb3: Pin::__new(), + pb4: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pb5: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pb6: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pb7: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pb8: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pb9: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pb10: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pb11: Pin::__new(), + pb12: Pin::__new(), + pb13: Pin::__new(), + pb14: Pin::__new(), + pb15: Pin::__new(), + #[cfg(feature = "vor1x")] + pb16: Pin::__new(), + #[cfg(feature = "vor1x")] + pb17: Pin::__new(), + #[cfg(feature = "vor1x")] + pb18: Pin::__new(), + #[cfg(feature = "vor1x")] + pb19: Pin::__new(), + #[cfg(feature = "vor1x")] + pb20: Pin::__new(), + #[cfg(feature = "vor1x")] + pb21: Pin::__new(), + #[cfg(feature = "vor1x")] + pb22: Pin::__new(), + #[cfg(feature = "vor1x")] + pb23: Pin::__new(), + } + } +} + +cfg_if::cfg_if! { + if #[cfg(feature = "vor4x")] { + /// Resource management singleton for GPIO PORT C. + pub struct PinsC { + pub pc0: Pin, + pub pc1: Pin, + pub pc2: Pin, + pub pc3: Pin, + pub pc4: Pin, + pub pc5: Pin, + pub pc6: Pin, + pub pc7: Pin, + pub pc8: Pin, + pub pc9: Pin, + pub pc10: Pin, + pub pc11: Pin, + pub pc12: Pin, + #[cfg(not(feature = "va41628"))] + pub pc13: Pin, + pub pc14: Pin, + #[cfg(not(feature = "va41628"))] + pub pc15: Pin, + } + + impl PinsC { + pub fn new(_port_c: pac::Portc) -> Self { + let syscfg = unsafe { pac::Sysconfig::steal() }; + reset_peripheral_for_cycles(PeripheralSelect::PortC, 2); + syscfg.peripheral_clk_enable().modify(|_, w| { + w.portc().set_bit(); + w.ioconfig().set_bit() + }); + Self { + pc0: Pin::__new(), + pc1: Pin::__new(), + pc2: Pin::__new(), + pc3: Pin::__new(), + pc4: Pin::__new(), + pc5: Pin::__new(), + pc6: Pin::__new(), + pc7: Pin::__new(), + pc8: Pin::__new(), + pc9: Pin::__new(), + pc10: Pin::__new(), + pc11: Pin::__new(), + pc12: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pc13: Pin::__new(), + pc14: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pc15: Pin::__new(), + } + } + } + + /// Resource management singleton for GPIO PORT D. + pub struct PinsD { + #[cfg(not(feature = "va41628"))] + pub pd0: Pin, + #[cfg(not(feature = "va41628"))] + pub pd1: Pin, + #[cfg(not(feature = "va41628"))] + pub pd2: Pin, + #[cfg(not(feature = "va41628"))] + pub pd3: Pin, + #[cfg(not(feature = "va41628"))] + pub pd4: Pin, + #[cfg(not(feature = "va41628"))] + pub pd5: Pin, + #[cfg(not(feature = "va41628"))] + pub pd6: Pin, + #[cfg(not(feature = "va41628"))] + pub pd7: Pin, + #[cfg(not(feature = "va41628"))] + pub pd8: Pin, + #[cfg(not(feature = "va41628"))] + pub pd9: Pin, + pub pd10: Pin, + pub pd11: Pin, + pub pd12: Pin, + pub pd13: Pin, + pub pd14: Pin, + pub pd15: Pin, + } + + impl PinsD { + pub fn new(_port_d: pac::Portd) -> Self { + let syscfg = unsafe { pac::Sysconfig::steal() }; + reset_peripheral_for_cycles(PeripheralSelect::PortD, 2); + syscfg.peripheral_clk_enable().modify(|_, w| { + w.portd().set_bit(); + w.ioconfig().set_bit() + }); + Self { + #[cfg(not(feature = "va41628"))] + pd0: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pd1: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pd2: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pd3: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pd4: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pd5: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pd6: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pd7: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pd8: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pd9: Pin::__new(), + pd10: Pin::__new(), + pd11: Pin::__new(), + pd12: Pin::__new(), + pd13: Pin::__new(), + pd14: Pin::__new(), + pd15: Pin::__new(), + } + } + } + + /// Resource management singleton for GPIO PORT E. + pub struct PinsE { + pub pe0: Pin, + pub pe1: Pin, + pub pe2: Pin, + pub pe3: Pin, + pub pe4: Pin, + pub pe5: Pin, + pub pe6: Pin, + pub pe7: Pin, + pub pe8: Pin, + pub pe9: Pin, + #[cfg(not(feature = "va41628"))] + pub pe10: Pin, + #[cfg(not(feature = "va41628"))] + pub pe11: Pin, + pub pe12: Pin, + pub pe13: Pin, + pub pe14: Pin, + pub pe15: Pin, + } + + impl PinsE { + pub fn new(_port_e: pac::Porte) -> Self { + let syscfg = unsafe { pac::Sysconfig::steal() }; + reset_peripheral_for_cycles(PeripheralSelect::PortE, 2); + syscfg.peripheral_clk_enable().modify(|_, w| { + w.porte().set_bit(); + w.ioconfig().set_bit() + }); + Self { + pe0: Pin::__new(), + pe1: Pin::__new(), + pe2: Pin::__new(), + pe3: Pin::__new(), + pe4: Pin::__new(), + pe5: Pin::__new(), + pe6: Pin::__new(), + pe7: Pin::__new(), + pe8: Pin::__new(), + pe9: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pe10: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pe11: Pin::__new(), + pe12: Pin::__new(), + pe13: Pin::__new(), + pe14: Pin::__new(), + pe15: Pin::__new(), + } + } + } + + /// Resource management singleton for GPIO PORT F. + pub struct PinsF { + pub pf0: Pin, + pub pf1: Pin, + #[cfg(not(feature = "va41628"))] + pub pf2: Pin, + #[cfg(not(feature = "va41628"))] + pub pf3: Pin, + #[cfg(not(feature = "va41628"))] + pub pf4: Pin, + #[cfg(not(feature = "va41628"))] + pub pf5: Pin, + #[cfg(not(feature = "va41628"))] + pub pf6: Pin, + #[cfg(not(feature = "va41628"))] + pub pf7: Pin, + #[cfg(not(feature = "va41628"))] + pub pf8: Pin, + pub pf9: Pin, + #[cfg(not(feature = "va41628"))] + pub pf10: Pin, + pub pf11: Pin, + pub pf12: Pin, + pub pf13: Pin, + pub pf14: Pin, + pub pf15: Pin, + } + + impl PinsF { + pub fn new(_port_f: pac::Portf) -> Self { + let syscfg = unsafe { pac::Sysconfig::steal() }; + reset_peripheral_for_cycles(PeripheralSelect::PortF, 2); + syscfg.peripheral_clk_enable().modify(|_, w| { + w.portf().set_bit(); + w.ioconfig().set_bit() + }); + Self { + pf0: Pin::__new(), + pf1: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pf2: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pf3: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pf4: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pf5: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pf6: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pf7: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pf8: Pin::__new(), + pf9: Pin::__new(), + #[cfg(not(feature = "va41628"))] + pf10: Pin::__new(), + pf11: Pin::__new(), + pf12: Pin::__new(), + pf13: Pin::__new(), + pf14: Pin::__new(), + pf15: Pin::__new(), + } + } + } + + /// Resource management singleton for GPIO PORT G. + pub struct PinsG { + pub pg0: Pin, + pub pg1: Pin, + pub pg2: Pin, + pub pg3: Pin, + pub pg4: Pin, + pub pg5: Pin, + pub pg6: Pin, + pub pg7: Pin, + } + + impl PinsG { + pub fn new(_port_g: pac::Portg) -> Self { + let syscfg = unsafe { pac::Sysconfig::steal() }; + reset_peripheral_for_cycles(PeripheralSelect::PortG, 2); + syscfg.peripheral_clk_enable().modify(|_, w| { + w.portg().set_bit(); + w.ioconfig().set_bit() + }); + Self { + pg0: Pin::__new(), + pg1: Pin::__new(), + pg2: Pin::__new(), + pg3: Pin::__new(), + pg4: Pin::__new(), + pg5: Pin::__new(), + pg6: Pin::__new(), + pg7: Pin::__new(), + } + } + } + } +} diff --git a/vorago-shared-hal/src/pwm.rs b/vorago-shared-hal/src/pwm.rs new file mode 100644 index 0000000..9184d73 --- /dev/null +++ b/vorago-shared-hal/src/pwm.rs @@ -0,0 +1,254 @@ +use core::convert::Infallible; +use core::marker::PhantomData; + +use crate::gpio::IoPeriphPin; +use crate::timer::enable_tim_clk; +use crate::timer::regs::{EnableControl, StatusSelect}; +use crate::{PeripheralSelect, enable_peripheral_clock}; + +use crate::time::Hertz; +use crate::timer::{self, TimId, TimInstance, TimPin}; + +const DUTY_MAX: u16 = u16::MAX; + +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum PwmA {} +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum PwmB {} + +#[derive(Debug, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("pin tim ID {pin_tim:?} and timer tim id {tim_id:?} do not match")] +pub struct TimMissmatchError { + pin_tim: TimId, + tim_id: TimId, +} + +//================================================================================================== +// PWM pin +//================================================================================================== + +/// Reduced version where type information is deleted +pub struct PwmPin { + tim_id: TimId, + regs: timer::regs::MmioTimer<'static>, + ref_clk: Hertz, + /// For PWMB, this is the upper limit + current_duty: u16, + /// For PWMA, this value will not be used + current_lower_limit: u16, + current_period: Hertz, + current_rst_val: u32, + mode: PhantomData, +} + +impl PwmPin { + /// Create a new PWM pin + pub fn new( + _pin: Pin, + _tim: Tim, + #[cfg(feature = "vor1x")] sys_clk: Hertz, + #[cfg(feature = "vor4x")] clks: &crate::clock::Clocks, + initial_frequency: Hertz, + ) -> Result { + if Pin::TIM_ID != Tim::ID { + return Err(TimMissmatchError { + pin_tim: Pin::TIM_ID, + tim_id: Tim::ID, + }); + } + IoPeriphPin::new(Pin::PIN_ID, Pin::FUN_SEL, None); + let mut pin = PwmPin { + tim_id: Tim::ID, + regs: timer::regs::Timer::new_mmio(Tim::ID), + current_duty: 0, + current_lower_limit: 0, + current_period: initial_frequency, + current_rst_val: 0, + #[cfg(feature = "vor1x")] + ref_clk: sys_clk, + #[cfg(feature = "vor4x")] + ref_clk: clks.apb1(), + mode: PhantomData, + }; + // For Vorago 4x, the presence of the pin structure ensures that its respective peripheral + // clock was already enabled. + #[cfg(feature = "vor1x")] + enable_peripheral_clock(PeripheralSelect::Gpio); + enable_peripheral_clock(PeripheralSelect::IoConfig); + enable_tim_clk(Tim::ID); + pin.enable_pwm_a(); + pin.set_period(initial_frequency); + Ok(pin) + } + + #[inline] + fn enable_pwm_a(&mut self) { + self.regs.modify_control(|mut value| { + value.set_status_sel(StatusSelect::PwmaOutput); + value + }); + } + + #[inline] + fn enable_pwm_b(&mut self) { + self.regs.modify_control(|mut value| { + value.set_status_sel(StatusSelect::PwmbOutput); + value + }); + } + + #[inline] + pub fn get_period(&self) -> Hertz { + self.current_period + } + + #[inline] + pub fn set_period(&mut self, period: impl Into) { + self.current_period = period.into(); + // Avoid division by 0 + if self.current_period.raw() == 0 { + return; + } + self.current_rst_val = self.ref_clk.raw() / self.current_period.raw(); + self.regs.write_reset_value(self.current_rst_val); + } + + #[inline] + pub fn disable(&mut self) { + self.regs.write_enable_control(EnableControl::new_disable()); + } + + #[inline] + pub fn enable(&mut self) { + self.regs.write_enable_control(EnableControl::new_enable()); + } + + #[inline] + pub fn period(&self) -> Hertz { + self.current_period + } + + #[inline(always)] + pub fn duty(&self) -> u16 { + self.current_duty + } +} + +impl From> for PwmPin { + fn from(other: PwmPin) -> Self { + let mut pwmb = Self { + mode: PhantomData, + regs: other.regs, + tim_id: other.tim_id, + ref_clk: other.ref_clk, + current_duty: other.current_duty, + current_lower_limit: other.current_lower_limit, + current_period: other.current_period, + current_rst_val: other.current_rst_val, + }; + pwmb.enable_pwm_b(); + pwmb + } +} + +impl From> for PwmPin { + fn from(other: PwmPin) -> Self { + let mut pwmb = Self { + mode: PhantomData, + tim_id: other.tim_id, + regs: other.regs, + ref_clk: other.ref_clk, + current_duty: other.current_duty, + current_lower_limit: other.current_lower_limit, + current_period: other.current_period, + current_rst_val: other.current_rst_val, + }; + pwmb.enable_pwm_a(); + pwmb + } +} + +//================================================================================================== +// PWMB implementations +//================================================================================================== + +impl PwmPin { + #[inline(always)] + pub fn pwmb_lower_limit(&self) -> u16 { + self.current_lower_limit + } + + #[inline(always)] + pub fn pwmb_upper_limit(&self) -> u16 { + self.current_duty + } + + /// Set the lower limit for PWMB + /// + /// The PWM signal will be 1 as long as the current RST counter is larger than + /// the lower limit. For example, with a lower limit of 0.5 and and an upper limit + /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high + /// state + #[inline(always)] + pub fn set_pwmb_lower_limit(&mut self, duty: u16) { + self.current_lower_limit = duty; + let pwmb_val: u64 = + (self.current_rst_val as u64 * self.current_lower_limit as u64) / DUTY_MAX as u64; + self.regs.write_pwmb_value(pwmb_val as u32); + } + + /// Set the higher limit for PWMB + /// + /// The PWM signal will be 1 as long as the current RST counter is smaller than + /// the higher limit. For example, with a lower limit of 0.5 and and an upper limit + /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high + /// state + pub fn set_pwmb_upper_limit(&mut self, duty: u16) { + self.current_duty = duty; + let pwma_val: u64 = + (self.current_rst_val as u64 * self.current_duty as u64) / DUTY_MAX as u64; + self.regs.write_pwma_value(pwma_val as u32); + } +} + +//================================================================================================== +// Embedded HAL implementation: PWMA only +//================================================================================================== + +impl embedded_hal::pwm::ErrorType for PwmPin { + type Error = Infallible; +} + +impl embedded_hal::pwm::SetDutyCycle for PwmPin { + #[inline] + fn max_duty_cycle(&self) -> u16 { + DUTY_MAX + } + + #[inline] + fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> { + self.current_duty = duty; + let pwma_val: u64 = (self.current_rst_val as u64 + * (DUTY_MAX as u64 - self.current_duty as u64)) + / DUTY_MAX as u64; + self.regs.write_pwma_value(pwma_val as u32); + Ok(()) + } +} + +/// Get the corresponding u16 duty cycle from a percent value ranging between 0.0 and 1.0. +/// +/// Please note that this might load a lot of floating point code because this processor does not +/// have a FPU +pub fn get_duty_from_percent(percent: f32) -> u16 { + if percent > 1.0 { + DUTY_MAX + } else if percent <= 0.0 { + 0 + } else { + (percent * DUTY_MAX as f32) as u16 + } +} diff --git a/vorago-shared-hal/src/spi/mod.rs b/vorago-shared-hal/src/spi/mod.rs new file mode 100644 index 0000000..e0bdcf2 --- /dev/null +++ b/vorago-shared-hal/src/spi/mod.rs @@ -0,0 +1,957 @@ +use crate::FunctionSelect; +use crate::gpio::{DynPinId, IoPeriphPin}; +use crate::{PeripheralSelect, enable_peripheral_clock, pins::AnyPin, sealed::Sealed, time::Hertz}; +use core::{convert::Infallible, fmt::Debug, marker::PhantomData}; +use embedded_hal::spi::{MODE_0, Mode}; + +use regs::{ClockPrescaler, Data, FifoClear, WordSize}; +#[cfg(feature = "vor1x")] +use va108xx as pac; +#[cfg(feature = "vor4x")] +use va416xx as pac; + +pub use regs::{Bank, HwChipSelectId}; + +pub mod regs; + +pub fn configure_pin_as_hw_cs_pin(_pin: P) -> HwChipSelectId { + IoPeriphPin::new(P::ID, P::FUN_SEL, None); + P::CS_ID +} + +//================================================================================================== +// Pins and traits. +//================================================================================================== + +pub trait PinSck: AnyPin { + const SPI_ID: Bank; + const FUN_SEL: FunctionSelect; +} + +pub trait PinMosi: AnyPin { + const SPI_ID: Bank; + const FUN_SEL: FunctionSelect; +} + +pub trait PinMiso: AnyPin { + const SPI_ID: Bank; + const FUN_SEL: FunctionSelect; +} + +pub trait HwCsProvider { + const PIN_ID: DynPinId; + const SPI_ID: Bank; + const FUN_SEL: FunctionSelect; + const CS_ID: HwChipSelectId; +} + +#[macro_use] +mod macros { + #[cfg(not(feature = "va41628"))] + macro_rules! hw_cs_multi_pin { + ( + // name of the newtype wrapper struct + $name:ident, + // Pb0 + $pin_id:ident, + // SpiId::B + $spi_id:path, + // FunSel::Sel1 + $fun_sel:path, + // HwChipSelectId::Id2 + $cs_id:path + ) => { + #[doc = concat!( + "Newtype wrapper to use [Pin] [`", stringify!($pin_id), "`] as a HW CS pin for [`", stringify!($spi_id), "`] with [`", stringify!($cs_id), "`]." + )] + pub struct $name(Pin<$pin_id>); + + impl $name { + pub fn new(pin: Pin<$pin_id>) -> Self { + Self(pin) + } + } + + impl crate::sealed::Sealed for $name {} + + impl HwCsProvider for $name { + const PIN_ID: DynPinId = <$pin_id as PinId>::ID; + const SPI_ID: Bank = $spi_id; + const FUN_SEL: FunctionSelect = $fun_sel; + const CS_ID: HwChipSelectId = $cs_id; + } + }; + } + + #[macro_export] + macro_rules! hw_cs_pins { + ($SpiId:path, $(($Px:ident, $FunSel:path, $HwCsIdent:path)$(,)?)+) => { + $( + impl HwCsProvider for Pin<$Px> { + const PIN_ID: DynPinId = $Px::ID; + const SPI_ID: Bank = $SpiId; + const FUN_SEL: FunctionSelect = $FunSel; + const CS_ID: HwChipSelectId = $HwCsIdent; + } + )+ + }; + } +} + +#[cfg(feature = "vor1x")] +pub mod pins_vor1x; +#[cfg(feature = "vor4x")] +pub mod pins_vor4x; + +//================================================================================================== +// Defintions +//================================================================================================== + +// FIFO has a depth of 16. +const FILL_DEPTH: usize = 12; + +pub const BMSTART_BMSTOP_MASK: u32 = 1 << 31; +pub const BMSKIPDATA_MASK: u32 = 1 << 30; + +pub const DEFAULT_CLK_DIV: u16 = 2; + +/// Common trait implemented by all PAC peripheral access structures. The register block +/// format is the same for all SPI blocks. +pub trait SpiInstance: Sealed { + const ID: Bank; + const PERIPH_SEL: PeripheralSelect; +} + +#[cfg(feature = "vor1x")] +pub type Spi0 = pac::Spia; +#[cfg(feature = "vor4x")] +pub type Spi0 = pac::Spi0; + +impl SpiInstance for Spi0 { + const ID: Bank = Bank::Spi0; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi0; +} +impl Sealed for Spi0 {} + +#[cfg(feature = "vor1x")] +pub type Spi1 = pac::Spib; +#[cfg(feature = "vor4x")] +pub type Spi1 = pac::Spi1; + +impl SpiInstance for Spi1 { + const ID: Bank = Bank::Spi1; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi1; +} +impl Sealed for Spi1 {} + +#[cfg(feature = "vor1x")] +pub type Spi2 = pac::Spic; +#[cfg(feature = "vor4x")] +pub type Spi2 = pac::Spi2; + +impl SpiInstance for Spi2 { + const ID: Bank = Bank::Spi2; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi2; +} +impl Sealed for Spi2 {} + +#[cfg(feature = "vor4x")] +impl SpiInstance for pac::Spi3 { + const ID: Bank = Bank::Spi3; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi3; +} +#[cfg(feature = "vor4x")] +impl Sealed for pac::Spi3 {} + +//================================================================================================== +// Config +//================================================================================================== + +pub trait TransferConfigProvider { + fn sod(&mut self, sod: bool); + fn blockmode(&mut self, blockmode: bool); + fn mode(&mut self, mode: Mode); + fn clk_cfg(&mut self, clk_cfg: SpiClockConfig); + fn hw_cs_id(&self) -> u8; +} + +/// Type erased variant of the transfer configuration. This is required to avoid generics in +/// the SPI constructor. +#[derive(Copy, Clone, Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct TransferConfig { + pub clk_cfg: Option, + pub mode: Option, + pub sod: bool, + /// If this is enabled, all data in the FIFO is transmitted in a single frame unless + /// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the + /// duration of multiple data words + pub blockmode: bool, + /// Only used when blockmode is used. The SCK will be stalled until an explicit stop bit + /// is set on a written word. + pub bmstall: bool, + pub hw_cs: Option, +} + +impl TransferConfig { + pub fn new_with_hw_cs( + clk_cfg: Option, + mode: Option, + blockmode: bool, + bmstall: bool, + sod: bool, + hw_cs_id: HwChipSelectId, + ) -> Self { + TransferConfig { + clk_cfg, + mode, + sod, + blockmode, + bmstall, + hw_cs: Some(hw_cs_id), + } + } +} + +/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct SpiConfig { + clk: SpiClockConfig, + // SPI mode configuration + pub init_mode: Mode, + /// If this is enabled, all data in the FIFO is transmitted in a single frame unless + /// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the + /// duration of multiple data words. Defaults to true. + pub blockmode: bool, + /// This enables the stalling of the SPI SCK if in blockmode and the FIFO is empty. + /// Currently enabled by default. + pub bmstall: bool, + /// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control + pub slave_output_disable: bool, + /// Loopback mode. If you use this, don't connect MISO to MOSI, they will be tied internally + pub loopback_mode: bool, + /// Enable Master Delayer Capture Mode. See Programmers Guide p.92 for more details + pub master_delayer_capture: bool, +} + +impl Default for SpiConfig { + fn default() -> Self { + Self { + init_mode: MODE_0, + blockmode: true, + bmstall: true, + // Default value is definitely valid. + clk: SpiClockConfig::from_div(DEFAULT_CLK_DIV).unwrap(), + slave_output_disable: Default::default(), + loopback_mode: Default::default(), + master_delayer_capture: Default::default(), + } + } +} + +impl SpiConfig { + pub fn loopback(mut self, enable: bool) -> Self { + self.loopback_mode = enable; + self + } + + pub fn blockmode(mut self, enable: bool) -> Self { + self.blockmode = enable; + self + } + + pub fn bmstall(mut self, enable: bool) -> Self { + self.bmstall = enable; + self + } + + pub fn mode(mut self, mode: Mode) -> Self { + self.init_mode = mode; + self + } + + pub fn clk_cfg(mut self, clk_cfg: SpiClockConfig) -> Self { + self.clk = clk_cfg; + self + } + + pub fn slave_output_disable(mut self, sod: bool) -> Self { + self.slave_output_disable = sod; + self + } +} + +//================================================================================================== +// Word Size +//================================================================================================== + +/// Configuration trait for the Word Size +/// used by the SPI peripheral +pub trait SpiWord: Copy + Default + Into + TryFrom + 'static { + const MASK: u32; + const WORD_SIZE: regs::WordSize; + fn word_reg() -> u8; +} + +impl SpiWord for u8 { + const MASK: u32 = 0xff; + const WORD_SIZE: regs::WordSize = regs::WordSize::EightBits; + fn word_reg() -> u8 { + 0x07 + } +} + +impl SpiWord for u16 { + const MASK: u32 = 0xffff; + const WORD_SIZE: regs::WordSize = regs::WordSize::SixteenBits; + fn word_reg() -> u8 { + 0x0f + } +} + +//================================================================================================== +// Spi +//================================================================================================== + +/// Low level access trait for the SPI peripheral. +pub trait SpiLowLevel { + /// Low level function to write a word to the SPI FIFO but also checks whether + /// there is actually data in the FIFO. + /// + /// Uses the [nb] API to allow usage in blocking and non-blocking contexts. + fn write_fifo(&mut self, data: u32) -> nb::Result<(), Infallible>; + + /// Low level function to write a word to the SPI FIFO without checking whether + /// there FIFO is full. + /// + /// This does not necesarily mean there is a space in the FIFO available. + /// Use [Self::write_fifo] function to write a word into the FIFO reliably. + fn write_fifo_unchecked(&mut self, data: u32); + + /// Low level function to read a word from the SPI FIFO. Must be preceeded by a + /// [Self::write_fifo] call. + /// + /// Uses the [nb] API to allow usage in blocking and non-blocking contexts. + fn read_fifo(&mut self) -> nb::Result; + + /// Low level function to read a word from from the SPI FIFO. + /// + /// This does not necesarily mean there is a word in the FIFO available. + /// Use the [Self::read_fifo] function to read a word from the FIFO reliably using the [nb] + /// API. + /// You might also need to mask the value to ignore the BMSTART/BMSTOP bit. + fn read_fifo_unchecked(&mut self) -> u32; +} + +#[inline(always)] +pub fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) { + match mode { + embedded_hal::spi::MODE_0 => (false, false), + embedded_hal::spi::MODE_1 => (false, true), + embedded_hal::spi::MODE_2 => (true, false), + embedded_hal::spi::MODE_3 => (true, true), + } +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct SpiClockConfig { + prescale_val: u8, + scrdv: u8, +} + +impl SpiClockConfig { + pub fn prescale_val(&self) -> u8 { + self.prescale_val + } + pub fn scrdv(&self) -> u8 { + self.scrdv + } +} + +impl SpiClockConfig { + pub fn new(prescale_val: u8, scrdv: u8) -> Self { + Self { + prescale_val, + scrdv, + } + } + + pub fn from_div(div: u16) -> Result { + spi_clk_config_from_div(div) + } + + #[cfg(feature = "vor1x")] + pub fn from_clk(sys_clk: Hertz, spi_clk: Hertz) -> Option { + clk_div_for_target_clock(sys_clk, spi_clk).map(|div| spi_clk_config_from_div(div).unwrap()) + } + + #[cfg(feature = "vor4x")] + pub fn from_clks(clks: &crate::clock::Clocks, spi_clk: Hertz) -> Option { + Self::from_apb1_clk(clks.apb1(), spi_clk) + } + + #[cfg(feature = "vor4x")] + pub fn from_apb1_clk(apb1_clk: Hertz, spi_clk: Hertz) -> Option { + clk_div_for_target_clock(apb1_clk, spi_clk).map(|div| spi_clk_config_from_div(div).unwrap()) + } +} + +#[derive(Debug, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum SpiClockConfigError { + #[error("division by zero")] + DivIsZero, + #[error("divide value is not even")] + DivideValueNotEven, + #[error("scrdv value is too large")] + ScrdvValueTooLarge, +} + +#[inline] +pub fn spi_clk_config_from_div(mut div: u16) -> Result { + if div == 0 { + return Err(SpiClockConfigError::DivIsZero); + } + if div % 2 != 0 { + return Err(SpiClockConfigError::DivideValueNotEven); + } + let mut prescale_val = 0; + + // find largest (even) prescale value that divides into div + for i in (2..=0xfe).rev().step_by(2) { + if div % i == 0 { + prescale_val = i; + break; + } + } + + if prescale_val == 0 { + return Err(SpiClockConfigError::DivideValueNotEven); + } + + div /= prescale_val; + if div > u8::MAX as u16 + 1 { + return Err(SpiClockConfigError::ScrdvValueTooLarge); + } + Ok(SpiClockConfig { + prescale_val: prescale_val as u8, + scrdv: (div - 1) as u8, + }) +} + +#[inline] +pub fn clk_div_for_target_clock(sys_clk: Hertz, spi_clk: Hertz) -> Option { + if spi_clk > sys_clk { + return None; + } + + // Step 1: Calculate raw divider. + let raw_div = sys_clk.raw() / spi_clk.raw(); + let remainder = sys_clk.raw() % spi_clk.raw(); + + // Step 2: Round up if necessary. + let mut rounded_div = if remainder * 2 >= spi_clk.raw() { + raw_div + 1 + } else { + raw_div + }; + + if rounded_div % 2 != 0 { + // Take slower clock conservatively. + rounded_div += 1; + } + if rounded_div > u16::MAX as u32 { + return None; + } + Some(rounded_div as u16) +} + +#[derive(Debug, thiserror::Error)] +#[error("peripheral or peripheral pin ID is not consistent")] +pub struct SpiIdMissmatchError; + +/// SPI peripheral driver structure. +pub struct Spi { + id: Bank, + regs: regs::MmioSpi<'static>, + cfg: SpiConfig, + /// Fill word for read-only SPI transactions. + fill_word: Word, + blockmode: bool, + bmstall: bool, + word: PhantomData, +} + +impl Spi +where + >::Error: core::fmt::Debug, +{ + /// Create a new SPI struct for using SPI with the fixed ROM SPI pins. + /// + /// ## Arguments + /// + /// * `spi` - SPI bus to use + /// * `spi_cfg` - Configuration specific to the SPI bus + pub fn new_for_rom( + spi: SpiI, + spi_cfg: SpiConfig, + ) -> Result { + #[cfg(feature = "vor1x")] + if SpiI::ID != Bank::Spi2 { + return Err(SpiIdMissmatchError); + } + #[cfg(feature = "vor4x")] + if SpiI::ID != Bank::Spi3 { + return Err(SpiIdMissmatchError); + } + Ok(Self::new_generic(spi, spi_cfg)) + } + + /// Create a new SPI peripheral driver. + /// + /// ## Arguments + /// + /// * `spi` - SPI bus to use + /// * `pins` - Pins to be used for SPI transactions. These pins are consumed + /// to ensure the pins can not be used for other purposes anymore + /// * `spi_cfg` - Configuration specific to the SPI bus + pub fn new( + spi: SpiI, + _pins: (Sck, Miso, Mosi), + spi_cfg: SpiConfig, + ) -> Result { + if SpiI::ID != Sck::SPI_ID || SpiI::ID != Miso::SPI_ID || SpiI::ID != Mosi::SPI_ID { + return Err(SpiIdMissmatchError); + } + IoPeriphPin::new(Sck::ID, Sck::FUN_SEL, None); + IoPeriphPin::new(Miso::ID, Miso::FUN_SEL, None); + IoPeriphPin::new(Mosi::ID, Mosi::FUN_SEL, None); + Ok(Self::new_generic(spi, spi_cfg)) + } + + pub fn new_generic(_spi: SpiI, spi_cfg: SpiConfig) -> Self { + enable_peripheral_clock(SpiI::PERIPH_SEL); + let mut regs = regs::Spi::new_mmio(SpiI::ID); + let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(spi_cfg.init_mode); + regs.write_ctrl0( + regs::Control0::builder() + .with_scrdv(spi_cfg.clk.scrdv) + .with_sph(cph_bit) + .with_spo(cpo_bit) + .with_word_size(Word::WORD_SIZE) + .build(), + ); + regs.write_ctrl1( + regs::Control1::builder() + .with_mtxpause(false) + .with_mdlycap(spi_cfg.master_delayer_capture) + .with_bm_stall(spi_cfg.bmstall) + .with_bm_start(false) + .with_blockmode(spi_cfg.blockmode) + .with_ss(HwChipSelectId::Id0) + .with_sod(spi_cfg.slave_output_disable) + .with_slave_mode(false) + .with_enable(false) + .with_lbm(spi_cfg.loopback_mode) + .build(), + ); + regs.write_clkprescale(ClockPrescaler::new(spi_cfg.clk.prescale_val)); + regs.write_fifo_clear( + FifoClear::builder() + .with_tx_fifo(true) + .with_rx_fifo(true) + .build(), + ); + // Enable the peripheral as the last step as recommended in the + // programmers guide + regs.modify_ctrl1(|mut value| { + value.set_enable(true); + value + }); + Spi { + id: SpiI::ID, + regs: regs::Spi::new_mmio(SpiI::ID), + cfg: spi_cfg, + fill_word: Default::default(), + bmstall: spi_cfg.bmstall, + blockmode: spi_cfg.blockmode, + word: PhantomData, + } + } + + #[inline] + pub fn cfg_clock(&mut self, cfg: SpiClockConfig) { + self.regs.modify_ctrl0(|mut value| { + value.set_scrdv(cfg.scrdv); + value + }); + self.regs + .write_clkprescale(regs::ClockPrescaler::new(cfg.prescale_val)); + } + + pub fn set_fill_word(&mut self, fill_word: Word) { + self.fill_word = fill_word; + } + + #[inline] + pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClockConfigError> { + let val = spi_clk_config_from_div(div)?; + self.cfg_clock(val); + Ok(()) + } + + #[inline] + pub fn cfg_mode(&mut self, mode: Mode) { + let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(mode); + self.regs.modify_ctrl0(|mut value| { + value.set_spo(cpo_bit); + value.set_sph(cph_bit); + value + }); + } + + #[inline] + pub fn fill_word(&self) -> Word { + self.fill_word + } + + #[inline] + pub fn clear_tx_fifo(&mut self) { + self.regs.write_fifo_clear( + regs::FifoClear::builder() + .with_tx_fifo(true) + .with_rx_fifo(false) + .build(), + ); + } + + #[inline] + pub fn clear_rx_fifo(&mut self) { + self.regs.write_fifo_clear( + regs::FifoClear::builder() + .with_tx_fifo(false) + .with_rx_fifo(true) + .build(), + ); + } + + #[inline] + pub fn perid(&self) -> u32 { + self.regs.read_perid() + } + + /// Configure the hardware chip select given a hardware chip select ID. + /// + /// The pin also needs to be configured to be used as a HW CS pin. This can be done + /// by using the [configure_pin_as_hw_cs_pin] function which also returns the + /// corresponding [HwChipSelectId]. + #[inline] + pub fn cfg_hw_cs(&mut self, hw_cs: HwChipSelectId) { + self.regs.modify_ctrl1(|mut value| { + value.set_sod(false); + value.set_ss(hw_cs); + value + }); + } + + /// Disables the hardware chip select functionality. This can be used when performing + /// external chip select handling, for example with GPIO pins. + #[inline] + pub fn cfg_hw_cs_disable(&mut self) { + self.regs.modify_ctrl1(|mut value| { + value.set_sod(true); + value + }); + } + + /// Utility function to configure all relevant transfer parameters in one go. + /// This is useful if multiple devices with different clock and mode configurations + /// are connected to one bus. + pub fn cfg_transfer(&mut self, transfer_cfg: &TransferConfig) { + if let Some(trans_clk_div) = transfer_cfg.clk_cfg { + self.cfg_clock(trans_clk_div); + } + if let Some(mode) = transfer_cfg.mode { + self.cfg_mode(mode); + } + self.blockmode = transfer_cfg.blockmode; + self.regs.modify_ctrl1(|mut value| { + if transfer_cfg.sod { + value.set_sod(transfer_cfg.sod); + } else { + value.set_sod(false); + if let Some(hw_cs) = transfer_cfg.hw_cs { + value.set_ss(hw_cs); + } + } + value.set_blockmode(transfer_cfg.blockmode); + value.set_bm_stall(transfer_cfg.bmstall); + value + }); + } + + fn flush_internal(&mut self) { + let mut status_reg = self.regs.read_status(); + while !status_reg.tx_empty() || status_reg.rx_not_empty() || status_reg.busy() { + if status_reg.rx_not_empty() { + self.read_fifo_unchecked(); + } + status_reg = self.regs.read_status(); + } + } + + fn transfer_preparation(&mut self, words: &[Word]) -> Result<(), Infallible> { + if words.is_empty() { + return Ok(()); + } + self.flush_internal(); + Ok(()) + } + + // The FIFO can hold a guaranteed amount of data, so we can pump it on transfer + // initialization. Returns the amount of written bytes. + fn initial_send_fifo_pumping_with_words(&mut self, words: &[Word]) -> usize { + //let reg_block = self.reg_block(); + if self.blockmode { + self.regs.modify_ctrl1(|mut value| { + value.set_mtxpause(true); + value + }); + } + // Fill the first half of the write FIFO + let mut current_write_idx = 0; + let smaller_idx = core::cmp::min(FILL_DEPTH, words.len()); + for _ in 0..smaller_idx { + if current_write_idx == smaller_idx.saturating_sub(1) && self.bmstall { + self.write_fifo_unchecked(words[current_write_idx].into() | BMSTART_BMSTOP_MASK); + } else { + self.write_fifo_unchecked(words[current_write_idx].into()); + } + current_write_idx += 1; + } + if self.blockmode { + self.regs.modify_ctrl1(|mut value| { + value.set_mtxpause(false); + value + }); + } + current_write_idx + } + + // The FIFO can hold a guaranteed amount of data, so we can pump it on transfer + // initialization. + fn initial_send_fifo_pumping_with_fill_words(&mut self, send_len: usize) -> usize { + if self.blockmode { + self.regs.modify_ctrl1(|mut value| { + value.set_mtxpause(true); + value + }); + } + // Fill the first half of the write FIFO + let mut current_write_idx = 0; + let smaller_idx = core::cmp::min(FILL_DEPTH, send_len); + for _ in 0..smaller_idx { + if current_write_idx == smaller_idx.saturating_sub(1) && self.bmstall { + self.write_fifo_unchecked(self.fill_word.into() | BMSTART_BMSTOP_MASK); + } else { + self.write_fifo_unchecked(self.fill_word.into()); + } + current_write_idx += 1; + } + if self.blockmode { + self.regs.modify_ctrl1(|mut value| { + value.set_mtxpause(false); + value + }); + } + current_write_idx + } +} + +impl SpiLowLevel for Spi +where + >::Error: core::fmt::Debug, +{ + #[inline(always)] + fn write_fifo(&mut self, data: u32) -> nb::Result<(), Infallible> { + if !self.regs.read_status().tx_not_full() { + return Err(nb::Error::WouldBlock); + } + self.write_fifo_unchecked(data); + Ok(()) + } + + #[inline(always)] + fn write_fifo_unchecked(&mut self, data: u32) { + self.regs.write_data(Data::new_with_raw_value(data)); + } + + #[inline(always)] + fn read_fifo(&mut self) -> nb::Result { + if !self.regs.read_status().rx_not_empty() { + return Err(nb::Error::WouldBlock); + } + Ok(self.read_fifo_unchecked()) + } + + #[inline(always)] + fn read_fifo_unchecked(&mut self) -> u32 { + self.regs.read_data().raw_value() + } +} + +impl embedded_hal::spi::ErrorType for Spi { + type Error = Infallible; +} + +impl embedded_hal::spi::SpiBus for Spi +where + >::Error: core::fmt::Debug, +{ + fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> { + self.transfer_preparation(words)?; + let mut current_read_idx = 0; + let mut current_write_idx = self.initial_send_fifo_pumping_with_fill_words(words.len()); + loop { + if current_read_idx < words.len() { + words[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK) + .try_into() + .unwrap(); + current_read_idx += 1; + } + if current_write_idx < words.len() { + if current_write_idx == words.len() - 1 && self.bmstall { + nb::block!(self.write_fifo(self.fill_word.into() | BMSTART_BMSTOP_MASK))?; + } else { + nb::block!(self.write_fifo(self.fill_word.into()))?; + } + current_write_idx += 1; + } + if current_read_idx >= words.len() && current_write_idx >= words.len() { + break; + } + } + Ok(()) + } + + fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> { + self.transfer_preparation(words)?; + let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words); + while current_write_idx < words.len() { + if current_write_idx == words.len() - 1 && self.bmstall { + nb::block!(self.write_fifo(words[current_write_idx].into() | BMSTART_BMSTOP_MASK))?; + } else { + nb::block!(self.write_fifo(words[current_write_idx].into()))?; + } + current_write_idx += 1; + // Ignore received words. + if self.regs.read_status().rx_not_empty() { + self.clear_rx_fifo(); + } + } + Ok(()) + } + + fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> { + self.transfer_preparation(write)?; + let mut current_read_idx = 0; + let mut current_write_idx = self.initial_send_fifo_pumping_with_words(write); + let max_idx = core::cmp::max(read.len(), write.len()); + while current_read_idx < read.len() || current_write_idx < write.len() { + if current_write_idx < max_idx { + if current_write_idx == write.len() - 1 && self.bmstall { + nb::block!( + self.write_fifo(write[current_write_idx].into() | BMSTART_BMSTOP_MASK) + )?; + } else if current_write_idx < write.len() { + nb::block!(self.write_fifo(write[current_write_idx].into()))?; + } else { + nb::block!(self.write_fifo(0))?; + } + current_write_idx += 1; + } + if current_read_idx < max_idx { + if current_read_idx < read.len() { + read[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK) + .try_into() + .unwrap(); + } else { + nb::block!(self.read_fifo()).unwrap(); + } + current_read_idx += 1; + } + } + + Ok(()) + } + + fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> { + self.transfer_preparation(words)?; + let mut current_read_idx = 0; + let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words); + + while current_read_idx < words.len() || current_write_idx < words.len() { + if current_write_idx < words.len() { + if current_write_idx == words.len() - 1 && self.bmstall { + nb::block!( + self.write_fifo(words[current_write_idx].into() | BMSTART_BMSTOP_MASK) + )?; + } else { + nb::block!(self.write_fifo(words[current_write_idx].into()))?; + } + current_write_idx += 1; + } + if current_read_idx < words.len() && current_read_idx < current_write_idx { + words[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK) + .try_into() + .unwrap(); + current_read_idx += 1; + } + } + Ok(()) + } + + fn flush(&mut self) -> Result<(), Self::Error> { + self.flush_internal(); + Ok(()) + } +} + +/// Changing the word size also requires a type conversion +impl From> for Spi { + fn from(mut old_spi: Spi) -> Self { + old_spi.regs.modify_ctrl0(|mut value| { + value.set_word_size(WordSize::SixteenBits); + value + }); + Spi { + id: old_spi.id, + regs: old_spi.regs, + cfg: old_spi.cfg, + blockmode: old_spi.blockmode, + fill_word: Default::default(), + bmstall: old_spi.bmstall, + word: PhantomData, + } + } +} + +impl From> for Spi { + fn from(mut old_spi: Spi) -> Self { + old_spi.regs.modify_ctrl0(|mut value| { + value.set_word_size(WordSize::EightBits); + value + }); + Spi { + id: old_spi.id, + regs: old_spi.regs, + cfg: old_spi.cfg, + blockmode: old_spi.blockmode, + fill_word: Default::default(), + bmstall: old_spi.bmstall, + word: PhantomData, + } + } +} diff --git a/vorago-shared-hal/src/spi/pins_vor1x.rs b/vorago-shared-hal/src/spi/pins_vor1x.rs new file mode 100644 index 0000000..6f564bf --- /dev/null +++ b/vorago-shared-hal/src/spi/pins_vor1x.rs @@ -0,0 +1,303 @@ +use super::{HwCsProvider, PinMiso, PinMosi, PinSck}; +use crate::FunctionSelect; +use crate::gpio::{DynPinId, PinId}; + +use crate::pins::{ + Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, Pa16, Pa17, Pa18, Pa19, Pa20, Pa21, Pa22, Pa23, Pa24, Pa25, + Pa26, Pa27, Pa28, Pa29, Pa30, Pa31, Pb0, Pb1, Pb2, Pb3, Pb4, Pb5, Pb6, Pb7, Pb8, Pb9, Pb10, + Pb11, Pb12, Pb13, Pb14, Pb15, Pb16, Pb17, Pb18, Pb19, Pb22, Pb23, Pin, +}; + +use super::{Bank, HwChipSelectId}; + +// SPIA + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +hw_cs_pins!( + Bank::Spi0, + (Pb0, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pb1, FunctionSelect::Sel2, HwChipSelectId::Id2), + (Pb2, FunctionSelect::Sel2, HwChipSelectId::Id3), + (Pb3, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pb4, FunctionSelect::Sel2, HwChipSelectId::Id5), + (Pb5, FunctionSelect::Sel2, HwChipSelectId::Id6), + (Pb6, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pa24, FunctionSelect::Sel1, HwChipSelectId::Id4), + (Pa25, FunctionSelect::Sel1, HwChipSelectId::Id3), + (Pa26, FunctionSelect::Sel1, HwChipSelectId::Id2), + (Pa27, FunctionSelect::Sel1, HwChipSelectId::Id1), + (Pa28, FunctionSelect::Sel1, HwChipSelectId::Id0), +); + +hw_cs_multi_pin!( + PinPb0SpiaHwCsId1, + Pb0, + Bank::Spi0, + FunctionSelect::Sel2, + HwChipSelectId::Id1 +); +hw_cs_multi_pin!( + PinPb1SpiaHwCsId2, + Pb1, + Bank::Spi0, + FunctionSelect::Sel2, + HwChipSelectId::Id2 +); +hw_cs_multi_pin!( + PinPb2SpiaHwCsId3, + Pb2, + Bank::Spi0, + FunctionSelect::Sel2, + HwChipSelectId::Id3 +); + +hw_cs_multi_pin!( + PinPa21SpiaHwCsId7, + Pa21, + Bank::Spi0, + FunctionSelect::Sel1, + HwChipSelectId::Id7 +); +hw_cs_multi_pin!( + PinPa22SpiaHwCsId6, + Pa22, + Bank::Spi0, + FunctionSelect::Sel1, + HwChipSelectId::Id6 +); +hw_cs_multi_pin!( + PinPa23SpiaHwCsId5, + Pa23, + Bank::Spi0, + FunctionSelect::Sel1, + HwChipSelectId::Id5 +); + +// SPIB + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +pub type SpiBPortASck = Pin; +pub type SpiBPortAMosi = Pin; +pub type SpiBPortAMiso = Pin; + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +// TODO: Need to deal with these duplications.. +hw_cs_pins!( + Bank::Spi1, + (Pb16, FunctionSelect::Sel1, HwChipSelectId::Id0), + (Pb15, FunctionSelect::Sel1, HwChipSelectId::Id1), + (Pb14, FunctionSelect::Sel1, HwChipSelectId::Id2), + (Pb13, FunctionSelect::Sel1, HwChipSelectId::Id3), + (Pa17, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pa16, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pa15, FunctionSelect::Sel2, HwChipSelectId::Id2), + (Pa14, FunctionSelect::Sel2, HwChipSelectId::Id3), + (Pa13, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pa12, FunctionSelect::Sel2, HwChipSelectId::Id5), + (Pa11, FunctionSelect::Sel2, HwChipSelectId::Id6), + (Pa10, FunctionSelect::Sel2, HwChipSelectId::Id7), + (Pa23, FunctionSelect::Sel2, HwChipSelectId::Id5), + (Pa22, FunctionSelect::Sel2, HwChipSelectId::Id6), + (Pa21, FunctionSelect::Sel2, HwChipSelectId::Id7), +); + +hw_cs_multi_pin!( + PinPb0SpibHwCsId2, + Pb0, + Bank::Spi1, + FunctionSelect::Sel1, + HwChipSelectId::Id2 +); +hw_cs_multi_pin!( + PinPb1SpibHwCsId1, + Pb1, + Bank::Spi1, + FunctionSelect::Sel1, + HwChipSelectId::Id1 +); +hw_cs_multi_pin!( + PinPb2SpibHwCsId0, + Pb2, + Bank::Spi1, + FunctionSelect::Sel1, + HwChipSelectId::Id0 +); + +hw_cs_multi_pin!( + PinPb10SpibHwCsId6, + Pb10, + Bank::Spi1, + FunctionSelect::Sel1, + HwChipSelectId::Id6 +); +hw_cs_multi_pin!( + PinPb11SpibHwCsId5, + Pb11, + Bank::Spi1, + FunctionSelect::Sel1, + HwChipSelectId::Id5 +); +hw_cs_multi_pin!( + PinPb12SpibHwCsId4, + Pb12, + Bank::Spi1, + FunctionSelect::Sel1, + HwChipSelectId::Id4 +); + +hw_cs_multi_pin!( + PinPb10SpibHwCsId2, + Pb10, + Bank::Spi1, + FunctionSelect::Sel2, + HwChipSelectId::Id2 +); +hw_cs_multi_pin!( + PinPb11SpibHwCsId1, + Pb11, + Bank::Spi1, + FunctionSelect::Sel2, + HwChipSelectId::Id1 +); +hw_cs_multi_pin!( + PinPb12SpibHwCsId0, + Pb12, + Bank::Spi1, + FunctionSelect::Sel2, + HwChipSelectId::Id0 +); + +hw_cs_multi_pin!( + PinPa21SpibHwCsId7, + Pa21, + Bank::Spi1, + FunctionSelect::Sel2, + HwChipSelectId::Id7 +); +hw_cs_multi_pin!( + PinPa22SpibHwCsId6, + Pa22, + Bank::Spi1, + FunctionSelect::Sel2, + HwChipSelectId::Id6 +); +hw_cs_multi_pin!( + PinPa23SpibHwCsId5, + Pa23, + Bank::Spi1, + FunctionSelect::Sel2, + HwChipSelectId::Id5 +); + +// SPIC + +hw_cs_pins!( + Bank::Spi2, + (Pb9, FunctionSelect::Sel3, HwChipSelectId::Id1), + (Pb8, FunctionSelect::Sel3, HwChipSelectId::Id2), + (Pb7, FunctionSelect::Sel3, HwChipSelectId::Id3), + (Pb23, FunctionSelect::Sel3, HwChipSelectId::Id2), + (Pb22, FunctionSelect::Sel3, HwChipSelectId::Id1), + (Pa20, FunctionSelect::Sel1, HwChipSelectId::Id1), + (Pa19, FunctionSelect::Sel1, HwChipSelectId::Id2), + (Pb18, FunctionSelect::Sel1, HwChipSelectId::Id3), +); + +hw_cs_multi_pin!( + PinPa21SpicHwCsId3, + Pa21, + Bank::Spi2, + FunctionSelect::Sel3, + HwChipSelectId::Id3 +); +hw_cs_multi_pin!( + PinPa22SpicHwCsId2, + Pa22, + Bank::Spi2, + FunctionSelect::Sel3, + HwChipSelectId::Id2 +); +hw_cs_multi_pin!( + PinPa23SpicHwCsId1, + Pa23, + Bank::Spi2, + FunctionSelect::Sel3, + HwChipSelectId::Id1 +); + +hw_cs_multi_pin!( + PinPa20SpicHwCsId1, + Pa20, + Bank::Spi2, + FunctionSelect::Sel1, + HwChipSelectId::Id1 +); +hw_cs_multi_pin!( + PinPa20SpicHwCsId4, + Pa20, + Bank::Spi2, + FunctionSelect::Sel3, + HwChipSelectId::Id4 +); diff --git a/vorago-shared-hal/src/spi/pins_vor4x.rs b/vorago-shared-hal/src/spi/pins_vor4x.rs new file mode 100644 index 0000000..c6323d9 --- /dev/null +++ b/vorago-shared-hal/src/spi/pins_vor4x.rs @@ -0,0 +1,208 @@ +use crate::{ + FunctionSelect, + gpio::{DynPinId, Pin, PinId}, + pins::{ + Pa0, Pa1, Pa2, Pa3, Pa4, Pa5, Pa6, Pa7, Pa8, Pa9, Pb0, Pb1, Pb2, Pb3, Pb4, Pb12, Pb13, + Pb14, Pb15, Pc0, Pc1, Pc7, Pc8, Pc9, Pc10, Pc11, Pe5, Pe6, Pe7, Pe8, Pe9, Pe12, Pe13, Pe14, + Pe15, Pf0, Pf1, Pg2, Pg3, Pg4, + }, +}; + +#[cfg(not(feature = "va41628"))] +use crate::pins::{Pb5, Pb6, Pb7, Pb8, Pb9, Pb10, Pb11, Pe10, Pe11, Pf2, Pf3, Pf4, Pf5, Pf6, Pf7}; + +use super::{Bank, HwChipSelectId, HwCsProvider, PinMiso, PinMosi, PinSck}; + +// SPI0 + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +hw_cs_pins!( + Bank::Spi0, + (Pb14, FunctionSelect::Sel1, HwChipSelectId::Id0), + (Pb13, FunctionSelect::Sel1, HwChipSelectId::Id1), + (Pb12, FunctionSelect::Sel1, HwChipSelectId::Id2), +); + +#[cfg(not(feature = "va41628"))] +hw_cs_pins!( + Bank::Spi0, + (Pb11, FunctionSelect::Sel1, HwChipSelectId::Id3) +); + +// SPI1 + +#[cfg(not(feature = "va41628"))] +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +#[cfg(not(feature = "va41628"))] +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +#[cfg(not(feature = "va41628"))] +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +#[cfg(not(feature = "va41628"))] +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +#[cfg(not(feature = "va41628"))] +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +#[cfg(not(feature = "va41628"))] +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +hw_cs_pins!( + Bank::Spi1, + (Pb4, FunctionSelect::Sel3, HwChipSelectId::Id3), + (Pb3, FunctionSelect::Sel3, HwChipSelectId::Id4), + (Pb2, FunctionSelect::Sel3, HwChipSelectId::Id5), + (Pb1, FunctionSelect::Sel3, HwChipSelectId::Id6), + (Pb0, FunctionSelect::Sel3, HwChipSelectId::Id7), + (Pc8, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pc7, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pe12, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pe9, FunctionSelect::Sel2, HwChipSelectId::Id3), + (Pe8, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pe7, FunctionSelect::Sel3, HwChipSelectId::Id5), + (Pe6, FunctionSelect::Sel3, HwChipSelectId::Id6), + (Pe5, FunctionSelect::Sel3, HwChipSelectId::Id7), + (Pg2, FunctionSelect::Sel2, HwChipSelectId::Id0), +); + +#[cfg(not(feature = "va41628"))] +hw_cs_pins!( + Bank::Spi1, + (Pb7, FunctionSelect::Sel3, HwChipSelectId::Id0), + (Pb6, FunctionSelect::Sel3, HwChipSelectId::Id1), + (Pb5, FunctionSelect::Sel3, HwChipSelectId::Id2), + (Pe11, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pe10, FunctionSelect::Sel2, HwChipSelectId::Id2), +); + +#[cfg(not(feature = "va41628"))] +hw_cs_multi_pin!( + PinPf2Spi1HwCsId0, + Pf2, + Bank::Spi2, + FunctionSelect::Sel1, + HwChipSelectId::Id0 +); + +// SPI2 + +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +#[cfg(not(feature = "va41628"))] +impl PinSck for Pin { + const SPI_ID: Bank = Bank::Spi2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +#[cfg(not(feature = "va41628"))] +impl PinMosi for Pin { + const SPI_ID: Bank = Bank::Spi2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +#[cfg(not(feature = "va41628"))] +impl PinMiso for Pin { + const SPI_ID: Bank = Bank::Spi2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +hw_cs_pins!( + Bank::Spi1, + (Pa4, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pa3, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pa2, FunctionSelect::Sel2, HwChipSelectId::Id2), + (Pa1, FunctionSelect::Sel2, HwChipSelectId::Id3), + (Pa0, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pa8, FunctionSelect::Sel2, HwChipSelectId::Id5), + (Pa9, FunctionSelect::Sel2, HwChipSelectId::Id6), + (Pf0, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pf1, FunctionSelect::Sel2, HwChipSelectId::Id3), +); + +#[cfg(not(feature = "va41628"))] +hw_cs_pins!( + Bank::Spi1, + (Pf3, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pf4, FunctionSelect::Sel2, HwChipSelectId::Id0), +); + +#[cfg(not(feature = "va41628"))] +hw_cs_multi_pin!( + PinPf2Spi2HwCsId2, + Pf2, + Bank::Spi2, + FunctionSelect::Sel2, + HwChipSelectId::Id2 +); diff --git a/vorago-shared-hal/src/spi/regs.rs b/vorago-shared-hal/src/spi/regs.rs new file mode 100644 index 0000000..99d7d50 --- /dev/null +++ b/vorago-shared-hal/src/spi/regs.rs @@ -0,0 +1,273 @@ +use core::marker::PhantomData; + +pub use crate::shared::{FifoClear, TriggerLevel}; + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + /// SPI A base address + pub const BASE_ADDR_0: usize = 0x4005_0000; + /// SPI B base address + pub const BASE_ADDR_1: usize = 0x4005_1000; + /// SPI C base address + pub const BASE_ADDR_2: usize = 0x4005_2000; + } else if #[cfg(feature = "vor4x")] { + /// SPI 0 base address + pub const BASE_ADDR_0: usize = 0x4001_5000; + /// SPI 1 base address + pub const BASE_ADDR_1: usize = 0x4001_5400; + /// SPI 2 base address + pub const BASE_ADDR_2: usize = 0x4001_5800; + /// SPI 3 base address + pub const BASE_ADDR_3: usize = 0x4001_5C00; + } +} + +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Bank { + Spi0, + Spi1, + Spi2, + #[cfg(feature = "vor4x")] + Spi3, +} + +impl Bank { + /// Unsafely steal the SPI peripheral block for the given port. + /// + /// # Safety + /// + /// Circumvents ownership and safety guarantees by the HAL. + pub unsafe fn steal_regs(&self) -> MmioSpi<'static> { + Spi::new_mmio(*self) + } +} + +#[bitbybit::bitenum(u4)] +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum WordSize { + OneBit = 0x00, + FourBits = 0x03, + EightBits = 0x07, + SixteenBits = 0x0f, +} + +#[derive(Debug, PartialEq, Eq)] +#[bitbybit::bitenum(u3, exhaustive = true)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum HwChipSelectId { + Id0 = 0, + Id1 = 1, + Id2 = 2, + Id3 = 3, + Id4 = 4, + Id5 = 5, + Id6 = 6, + Id7 = 7, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))] +pub struct Control0 { + #[bits(8..=15, rw)] + scrdv: u8, + #[bit(7, rw)] + sph: bool, + #[bit(6, rw)] + spo: bool, + #[bits(0..=3, rw)] + word_size: Option, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))] +pub struct Control1 { + #[bit(11, rw)] + mtxpause: bool, + #[bit(10, rw)] + mdlycap: bool, + #[bit(9, rw)] + bm_stall: bool, + #[bit(8, rw)] + bm_start: bool, + #[bit(7, rw)] + blockmode: bool, + #[bits(4..=6, rw)] + ss: HwChipSelectId, + #[bit(3, rw)] + sod: bool, + #[bit(2, rw)] + slave_mode: bool, + #[bit(1, rw)] + enable: bool, + #[bit(0, rw)] + lbm: bool, +} + +#[bitbybit::bitfield(u32)] +#[derive(Debug)] +pub struct Data { + /// Only used for BLOCKMODE. For received data, this bit indicated that the data was the first + /// word after the chip select went active. For transmitted data, setting this bit to 1 + /// will end an SPI frame (deassert CS) after the specified data word. + #[bit(31, rw)] + bm_start_stop: bool, + /// Only used for BLOCKMODE. Setting this bit to 1 along with the BMSTOP bit will end an SPI + /// frame without any additional data to be transmitted. If BMSTOP is not set, this bit is + /// ignored. + #[bit(30, rw)] + bm_skipdata: bool, + #[bits(0..=15, rw)] + data: u16, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct Status { + /// TX FIFO below the trigger level. + #[bit(7, r)] + tx_trigger: bool, + /// RX FIFO above or equals the trigger level. + #[bit(6, r)] + rx_trigger: bool, + #[bit(5, r)] + rx_data_first: bool, + #[bit(4, r)] + busy: bool, + #[bit(3, r)] + rx_full: bool, + #[bit(2, r)] + rx_not_empty: bool, + #[bit(1, r)] + tx_not_full: bool, + #[bit(0, r)] + tx_empty: bool, +} + +/// Clock divisor value. Bit 0 is ignored and always 0. This means that only the even values +/// are used as clock divisor values, and uneven values are truncated to the next even value. +/// A value of 0 acts as a 1 for the divisor value. +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub struct ClockPrescaler(arbitrary_int::UInt); + +impl ClockPrescaler { + pub const fn new(value: u8) -> Self { + ClockPrescaler(arbitrary_int::UInt::::new(value as u32)) + } + pub const fn value(&self) -> u8 { + self.0.value() as u8 + } +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct InterruptControl { + /// TX FIFO count <= TX FIFO trigger level. + #[bit(3, rw)] + tx: bool, + /// RX FIFO count >= RX FIFO trigger level. + #[bit(2, rw)] + rx: bool, + /// Occurs when the RX FIFO has not been read within 32 clock ticks of the SPICLKx2 clock + /// within the RX FIFO not being empty. Clearing the RX interrupt or reading data from the + /// FIFO resets the timeout counter. + #[bit(1, rw)] + rx_timeout: bool, + #[bit(0, rw)] + rx_overrun: bool, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct InterruptStatus { + /// TX FIFO count <= TX FIFO trigger level. + #[bit(3, r)] + tx: bool, + /// RX FIFO count >= RX FIFO trigger level. + #[bit(2, r)] + rx: bool, + /// Occurs when the RX FIFO has not been read within 32 clock ticks of the SPICLKx2 clock + /// within the RX FIFO not being empty. Clearing the RX interrupt or reading data from the + /// FIFO resets the timeout counter. + #[bit(1, r)] + rx_timeout: bool, + #[bit(0, r)] + rx_overrun: bool, +} + +#[bitbybit::bitfield(u32)] +#[derive(Debug)] +pub struct InterruptClear { + /// Clearing the RX interrupt or reading data from the FIFO resets the timeout counter. + #[bit(1, w)] + rx_timeout: bool, + #[bit(0, w)] + rx_overrun: bool, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct State { + #[bits(0..=7, r)] + rx_state: u8, + #[bits(8..=15, r)] + rx_fifo: u8, + #[bits(24..=31, r)] + tx_fifo: u8, +} + +#[derive(derive_mmio::Mmio)] +#[mmio(no_ctors)] +#[repr(C)] +pub struct Spi { + ctrl0: Control0, + ctrl1: Control1, + data: Data, + #[mmio(PureRead)] + status: Status, + clkprescale: ClockPrescaler, + irq_enb: InterruptControl, + /// Raw interrupt status. + #[mmio(PureRead)] + irq_raw: InterruptStatus, + /// Enabled interrupt status. + #[mmio(PureRead)] + irq_status: InterruptStatus, + #[mmio(Write)] + irq_clear: InterruptClear, + rx_fifo_trigger: TriggerLevel, + tx_fifo_trigger: TriggerLevel, + #[mmio(Write)] + fifo_clear: FifoClear, + #[mmio(PureRead)] + state: u32, + #[cfg(feature = "vor1x")] + _reserved: [u32; 0x3F2], + #[cfg(feature = "vor4x")] + _reserved: [u32; 0xF2], + /// Vorago 1x: 0x0113_07E1. Vorago 4x: 0x0213_07E9. + #[mmio(PureRead)] + perid: u32, +} + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + static_assertions::const_assert_eq!(core::mem::size_of::(), 0x1000); + } else if #[cfg(feature = "vor4x")] { + static_assertions::const_assert_eq!(core::mem::size_of::(), 0x400); + } +} + +impl Spi { + fn new_mmio_at(base: usize) -> MmioSpi<'static> { + MmioSpi { + ptr: base as *mut _, + phantom: PhantomData, + } + } + + pub fn new_mmio(bank: Bank) -> MmioSpi<'static> { + match bank { + Bank::Spi0 => Self::new_mmio_at(BASE_ADDR_0), + Bank::Spi1 => Self::new_mmio_at(BASE_ADDR_1), + Bank::Spi2 => Self::new_mmio_at(BASE_ADDR_2), + #[cfg(feature = "vor4x")] + Bank::Spi3 => Self::new_mmio_at(BASE_ADDR_2), + } + } +} diff --git a/vorago-shared-hal/src/sysconfig.rs b/vorago-shared-hal/src/sysconfig.rs new file mode 100644 index 0000000..5548419 --- /dev/null +++ b/vorago-shared-hal/src/sysconfig.rs @@ -0,0 +1,43 @@ +#[cfg(feature = "vor1x")] +use va108xx as pac; +#[cfg(feature = "vor4x")] +use va416xx as pac; + +#[inline] +pub fn enable_peripheral_clock(clock: crate::PeripheralSelect) { + let syscfg = unsafe { pac::Sysconfig::steal() }; + syscfg + .peripheral_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) }); +} + +#[inline] +pub fn disable_peripheral_clock(clock: crate::PeripheralSelect) { + let syscfg = unsafe { pac::Sysconfig::steal() }; + syscfg + .peripheral_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) }); +} + +#[inline] +pub fn assert_peripheral_reset(periph_sel: crate::PeripheralSelect) { + let syscfg = unsafe { pac::Sysconfig::steal() }; + syscfg + .peripheral_reset() + .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph_sel as u8)) }); +} + +#[inline] +pub fn deassert_peripheral_reset(periph_sel: crate::PeripheralSelect) { + let syscfg = unsafe { pac::Sysconfig::steal() }; + syscfg + .peripheral_reset() + .modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) }); +} + +#[inline] +pub fn reset_peripheral_for_cycles(periph_sel: crate::PeripheralSelect, cycles: usize) { + assert_peripheral_reset(periph_sel); + cortex_m::asm::delay(cycles as u32); + deassert_peripheral_reset(periph_sel); +} diff --git a/vorago-shared-hal/src/time.rs b/vorago-shared-hal/src/time.rs new file mode 100644 index 0000000..9808028 --- /dev/null +++ b/vorago-shared-hal/src/time.rs @@ -0,0 +1,26 @@ +//! Time units + +// Frequency based + +/// Hertz +pub type Hertz = fugit::HertzU32; + +/// KiloHertz +pub type KiloHertz = fugit::KilohertzU32; + +/// MegaHertz +pub type MegaHertz = fugit::MegahertzU32; + +// Period based + +/// Seconds +pub type Seconds = fugit::SecsDurationU32; + +/// Milliseconds +pub type Milliseconds = fugit::MillisDurationU32; + +/// Microseconds +pub type Microseconds = fugit::MicrosDurationU32; + +/// Nanoseconds +pub type Nanoseconds = fugit::NanosDurationU32; diff --git a/vorago-shared-hal/src/timer/mod.rs b/vorago-shared-hal/src/timer/mod.rs new file mode 100644 index 0000000..31fe0a1 --- /dev/null +++ b/vorago-shared-hal/src/timer/mod.rs @@ -0,0 +1,504 @@ +pub mod regs; + +use core::convert::Infallible; + +#[cfg(feature = "vor1x")] +pub use crate::InterruptConfig; +#[cfg(feature = "vor1x")] +use crate::sysconfig::enable_peripheral_clock; +pub use regs::{CascadeSource, InvalidTimerIndex, TimId}; + +use crate::{enable_nvic_interrupt, sealed::Sealed, time::Hertz}; +use crate::{gpio::DynPinId, ioconfig::regs::FunctionSelect, pins::AnyPin}; +use fugit::RateExtU32; + +#[cfg(feature = "vor1x")] +use crate::PeripheralSelect; + +#[cfg(feature = "vor1x")] +use va108xx as pac; +#[cfg(feature = "vor4x")] +use va416xx as pac; + +#[cfg(feature = "vor4x")] +pub const TIM_IRQ_OFFSET: usize = 48; + +//================================================================================================== +// Defintions +//================================================================================================== + +#[derive(Default, Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct CascadeControl { + /// Enable Cascade 0 signal active as a requirement for counting + pub enable_src_0: bool, + /// Invert Cascade 0, making it active low + pub inv_src_0: regs::CascadeInvert, + /// Enable Cascade 1 signal active as a requirement for counting + pub enable_src_1: bool, + /// Invert Cascade 1, making it active low + pub inv_src_1: regs::CascadeInvert, + /// Specify required operation if both Cascade 0 and Cascade 1 are active. + /// 0 is a logical AND of both cascade signals, 1 is a logical OR + pub dual_operation: regs::DualCascadeOp, + /// Enable trigger mode for Cascade 0. In trigger mode, couting will start with the selected + /// cascade signal active, but once the counter is active, cascade control will be ignored + pub trigger_mode_0: bool, + /// Trigger mode, identical to [Self::trigger_mode_0] but for Cascade 1 + pub trigger_mode_1: bool, + /// Enable Cascade 2 signal active as a requirement to stop counting. This mode is similar + /// to the REQ_STOP control bit, but signalled by a Cascade source + pub enable_stop_src_2: bool, + /// Invert Cascade 2, making it active low + pub inv_src_2: regs::CascadeInvert, + /// The counter is automatically disabled if the corresponding Cascade 2 level-sensitive input + /// souce is active when the count reaches 0. If the counter is not 0, the cascade control is + /// ignored + pub trigger_mode_2: bool, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum CascadeSelect { + Csd0 = 0, + Csd1 = 1, + Csd2 = 2, +} + +//================================================================================================== +// Valid TIM and PIN combinations +//================================================================================================== + +pub trait TimPin: AnyPin { + const PIN_ID: DynPinId; + const FUN_SEL: FunctionSelect; + const TIM_ID: TimId; +} + +pub trait TimInstance: Sealed { + // TIM ID ranging from 0 to 23 for 24 TIM peripherals + const ID: TimId; + #[cfg(feature = "vor4x")] + const IRQ: va416xx::Interrupt; + + #[cfg(feature = "vor4x")] + fn clock(clocks: &crate::clock::Clocks) -> Hertz { + if Self::ID.value() <= 15 { + clocks.apb1() + } else { + clocks.apb2() + } + } +} + +macro_rules! tim_marker { + ($TIMX:path, $ID:expr) => { + impl TimInstance for $TIMX { + const ID: TimId = TimId::new_unchecked($ID); + } + + impl Sealed for $TIMX {} + }; + ($TIMX:path, $ID:expr, $IrqId:ident) => { + impl TimInstance for $TIMX { + const ID: TimId = TimId::new_unchecked($ID); + const IRQ: va416xx::Interrupt = va416xx::Interrupt::$IrqId; + } + + impl Sealed for $TIMX {} + }; +} + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + tim_marker!(pac::Tim0, 0); + tim_marker!(pac::Tim1, 1); + tim_marker!(pac::Tim2, 2); + tim_marker!(pac::Tim3, 3); + tim_marker!(pac::Tim4, 4); + tim_marker!(pac::Tim5, 5); + tim_marker!(pac::Tim6, 6); + tim_marker!(pac::Tim7, 7); + tim_marker!(pac::Tim8, 8); + tim_marker!(pac::Tim9, 9); + tim_marker!(pac::Tim10, 10); + tim_marker!(pac::Tim11, 11); + tim_marker!(pac::Tim12, 12); + tim_marker!(pac::Tim13, 13); + tim_marker!(pac::Tim14, 14); + tim_marker!(pac::Tim15, 15); + tim_marker!(pac::Tim16, 16); + tim_marker!(pac::Tim17, 17); + tim_marker!(pac::Tim18, 18); + tim_marker!(pac::Tim19, 19); + tim_marker!(pac::Tim20, 20); + tim_marker!(pac::Tim21, 21); + tim_marker!(pac::Tim22, 22); + tim_marker!(pac::Tim23, 23); + } else if #[cfg(feature = "vor4x")] { + tim_marker!(pac::Tim0, 0, TIM0); + tim_marker!(pac::Tim1, 1, TIM1); + tim_marker!(pac::Tim2, 2, TIM2); + tim_marker!(pac::Tim3, 3, TIM3); + tim_marker!(pac::Tim4, 4, TIM4); + tim_marker!(pac::Tim5, 5, TIM5); + tim_marker!(pac::Tim6, 6, TIM6); + tim_marker!(pac::Tim7, 7, TIM7); + tim_marker!(pac::Tim8, 8, TIM8); + tim_marker!(pac::Tim9, 9, TIM9); + tim_marker!(pac::Tim10, 10, TIM10); + tim_marker!(pac::Tim11, 11, TIM11); + tim_marker!(pac::Tim12, 12, TIM12); + tim_marker!(pac::Tim13, 13, TIM13); + tim_marker!(pac::Tim14, 14, TIM14); + tim_marker!(pac::Tim15, 15, TIM15); + tim_marker!(pac::Tim16, 16, TIM16); + tim_marker!(pac::Tim17, 17, TIM17); + tim_marker!(pac::Tim18, 18, TIM18); + tim_marker!(pac::Tim19, 19, TIM19); + tim_marker!(pac::Tim20, 20, TIM20); + tim_marker!(pac::Tim21, 21, TIM21); + tim_marker!(pac::Tim22, 22, TIM22); + tim_marker!(pac::Tim23, 23, TIM23); + } +} + +pub trait ValidTimAndPin: Sealed {} + +#[macro_use] +mod macros { + macro_rules! pin_and_tim { + ($Px:ident, $FunSel:path, $ID:expr) => { + impl TimPin for Pin<$Px> + where + $Px: PinId, + { + const PIN_ID: DynPinId = $Px::ID; + const FUN_SEL: FunctionSelect = $FunSel; + const TIM_ID: TimId = TimId::new_unchecked($ID); + } + }; + } +} + +#[cfg(feature = "vor1x")] +pub mod pins_vor1x; +#[cfg(feature = "vor4x")] +pub mod pins_vor4x; + +//================================================================================================== +// Timers +//================================================================================================== + +/// Hardware timers +pub struct CountdownTimer { + id: TimId, + regs: regs::MmioTimer<'static>, + curr_freq: Hertz, + ref_clk: Hertz, + rst_val: u32, + last_cnt: u32, +} + +impl CountdownTimer { + /// Create a countdown timer structure for a given TIM peripheral. + /// + /// This does not enable the timer. You can use the [Self::load], [Self::start], + /// [Self::enable_interrupt] and [Self::enable] API to set up and configure the countdown + /// timer. + #[cfg(feature = "vor1x")] + pub fn new(_tim: Tim, sys_clk: Hertz) -> Self { + enable_tim_clk(Tim::ID); + assert_tim_reset_for_cycles(Tim::ID, 2); + CountdownTimer { + id: Tim::ID, + regs: regs::Timer::new_mmio(Tim::ID), + ref_clk: sys_clk, + rst_val: 0, + curr_freq: 0.Hz(), + last_cnt: 0, + } + } + + /// Create a countdown timer structure for a given TIM peripheral. + /// + /// This does not enable the timer. You can use the [Self::load], [Self::start], + /// [Self::enable_interrupt] and [Self::enable] API to set up and configure the countdown + /// timer. + #[cfg(feature = "vor4x")] + pub fn new(_tim: Tim, clks: &crate::clock::Clocks) -> Self { + enable_tim_clk(Tim::ID); + assert_tim_reset_for_cycles(Tim::ID, 2); + CountdownTimer { + id: Tim::ID, + regs: regs::Timer::new_mmio(Tim::ID), + ref_clk: clks.apb1(), + rst_val: 0, + curr_freq: 0.Hz(), + last_cnt: 0, + } + } + + #[inline] + pub fn perid(&self) -> u32 { + self.regs.read_perid() + } + + #[inline(always)] + pub fn enable(&mut self) { + self.regs + .write_enable_control(regs::EnableControl::new_enable()); + } + #[inline(always)] + pub fn disable(&mut self) { + self.regs + .write_enable_control(regs::EnableControl::new_disable()); + } + + #[cfg(feature = "vor1x")] + pub fn enable_interrupt(&mut self, irq_cfg: InterruptConfig) { + if irq_cfg.route { + let irqsel = unsafe { pac::Irqsel::steal() }; + enable_peripheral_clock(PeripheralSelect::Irqsel); + irqsel + .tim(self.id.value() as usize) + .write(|w| unsafe { w.bits(irq_cfg.id as u32) }); + } + if irq_cfg.enable_in_nvic { + unsafe { enable_nvic_interrupt(irq_cfg.id) }; + } + self.regs.modify_control(|mut value| { + value.set_irq_enable(true); + value + }); + } + + #[cfg(feature = "vor4x")] + #[inline(always)] + pub fn enable_interrupt(&mut self, enable_in_nvic: bool) { + if enable_in_nvic { + unsafe { enable_nvic_interrupt(self.id.interrupt_id()) }; + } + self.regs.modify_control(|mut value| { + value.set_irq_enable(true); + value + }); + } + + /// This function only clears the interrupt enable bit. + /// + /// It does not mask the interrupt in the NVIC or un-route the IRQ. + #[inline(always)] + pub fn disable_interrupt(&mut self) { + self.regs.modify_control(|mut value| { + value.set_irq_enable(false); + value + }); + } + + /// Calls [Self::load] to configure the specified frequency and then calls [Self::enable]. + pub fn start(&mut self, frequency: impl Into) { + self.load(frequency); + self.enable(); + } + + /// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the + /// flag and restart the time if configured correctly + pub fn wait(&mut self) -> nb::Result<(), Infallible> { + let cnt = self.counter(); + if (cnt > self.last_cnt) || cnt == 0 { + self.last_cnt = self.rst_val; + Ok(()) + } else { + self.last_cnt = cnt; + Err(nb::Error::WouldBlock) + } + } + + /// Load the count down timer with a timeout but do not start it. + pub fn load(&mut self, timeout: impl Into) { + self.disable(); + self.curr_freq = timeout.into(); + self.rst_val = self.ref_clk.raw() / self.curr_freq.raw(); + self.set_reload(self.rst_val); + self.set_count(self.rst_val); + } + + #[inline(always)] + pub fn set_reload(&mut self, val: u32) { + self.regs.write_reset_value(val); + } + + #[inline(always)] + pub fn set_count(&mut self, val: u32) { + self.regs.write_count_value(val); + } + + #[inline(always)] + pub fn counter(&self) -> u32 { + self.regs.read_count_value() + } + + /// Disable the counter, setting both enable and active bit to 0 + #[inline] + pub fn auto_disable(&mut self, enable: bool) { + self.regs.modify_control(|mut value| { + value.set_auto_disable(enable); + value + }); + } + + /// This option only applies when the Auto-Disable functionality is 0. + /// + /// The active bit is changed to 0 when count reaches 0, but the counter stays + /// enabled. When Auto-Disable is 1, Auto-Deactivate is implied + #[inline] + pub fn auto_deactivate(&mut self, enable: bool) { + self.regs.modify_control(|mut value| { + value.set_auto_deactivate(enable); + value + }); + } + + /// Configure the cascade parameters + pub fn cascade_control(&mut self, ctrl: CascadeControl) { + self.regs.write_cascade_control( + regs::CascadeControl::builder() + .with_trigger2(ctrl.trigger_mode_2) + .with_inv2(ctrl.inv_src_2) + .with_en2(ctrl.enable_stop_src_2) + .with_trigger1(ctrl.trigger_mode_1) + .with_trigger0(ctrl.trigger_mode_0) + .with_dual_cascade_op(ctrl.dual_operation) + .with_inv1(ctrl.inv_src_1) + .with_en1(ctrl.enable_src_1) + .with_inv0(ctrl.inv_src_0) + .with_en0(ctrl.enable_src_0) + .build(), + ); + } + + pub fn cascade_source( + &mut self, + cascade_index: CascadeSelect, + src: regs::CascadeSource, + ) -> Result<(), regs::InvalidCascadeSourceId> { + // Safety: Index range safe by enum values. + unsafe { + self.regs + .write_cascade_unchecked(cascade_index as usize, regs::CascadeSourceReg::new(src)?); + } + Ok(()) + } + + pub fn curr_freq(&self) -> Hertz { + self.curr_freq + } + + /// Disables the TIM and the dedicated TIM clock. + pub fn stop_with_clock_disable(mut self) { + self.disable(); + unsafe { pac::Sysconfig::steal() } + .tim_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.id.value())) }); + } +} + +//================================================================================================== +// Delay implementations +//================================================================================================== +// +impl embedded_hal::delay::DelayNs for CountdownTimer { + fn delay_ns(&mut self, ns: u32) { + let ticks = (u64::from(ns)) * (u64::from(self.ref_clk.raw())) / 1_000_000_000; + + let full_cycles = ticks >> 32; + let mut last_count; + let mut new_count; + if full_cycles > 0 { + self.set_reload(u32::MAX); + self.set_count(u32::MAX); + self.enable(); + + for _ in 0..full_cycles { + // Always ensure that both values are the same at the start. + new_count = self.counter(); + last_count = new_count; + loop { + new_count = self.counter(); + if new_count == 0 { + // Wait till timer has wrapped. + while self.counter() == 0 { + cortex_m::asm::nop() + } + break; + } + // Timer has definitely wrapped. + if new_count > last_count { + break; + } + last_count = new_count; + } + } + } + let ticks = (ticks & u32::MAX as u64) as u32; + self.disable(); + if ticks > 1 { + self.set_reload(ticks); + self.set_count(ticks); + self.enable(); + last_count = ticks; + + loop { + new_count = self.counter(); + if new_count == 0 || (new_count > last_count) { + break; + } + last_count = new_count; + } + } + + self.disable(); + } +} + +#[inline(always)] +pub fn enable_tim_clk(id: TimId) { + unsafe { pac::Sysconfig::steal() } + .tim_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() | (1 << id.value())) }); +} + +#[inline(always)] +pub fn disable_tim_clk(id: TimId) { + unsafe { pac::Sysconfig::steal() } + .tim_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << (id.value()))) }); +} + +/// Clear the reset bit of the TIM, holding it in reset +/// +/// # Safety +/// +/// Only the bit related to the corresponding TIM peripheral is modified +#[inline] +pub fn assert_tim_reset(id: TimId) { + unsafe { pac::Peripherals::steal() } + .sysconfig + .tim_reset() + .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << id.value())) }); +} + +#[inline] +pub fn deassert_tim_reset(tim: TimId) { + unsafe { pac::Peripherals::steal() } + .sysconfig + .tim_reset() + .modify(|r, w| unsafe { w.bits(r.bits() | (1 << tim.value())) }); +} + +pub fn assert_tim_reset_for_cycles(tim: TimId, cycles: u32) { + assert_tim_reset(tim); + cortex_m::asm::delay(cycles); + deassert_tim_reset(tim); +} diff --git a/vorago-shared-hal/src/timer/pins_vor1x.rs b/vorago-shared-hal/src/timer/pins_vor1x.rs new file mode 100644 index 0000000..abd22b3 --- /dev/null +++ b/vorago-shared-hal/src/timer/pins_vor1x.rs @@ -0,0 +1,56 @@ +use super::{TimId, TimPin}; +use crate::FunctionSelect; +use crate::pins::{ + DynPinId, Pa0, Pa1, Pa2, Pa3, Pa4, Pa5, Pa6, Pa7, Pa8, Pa9, Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, + Pa24, Pa25, Pa26, Pa27, Pa28, Pa29, Pa30, Pa31, Pb0, Pb1, Pb2, Pb3, Pb4, Pb5, Pb6, Pb10, Pb11, + Pb12, Pb13, Pb14, Pb15, Pb16, Pb17, Pb18, Pb19, Pb20, Pb21, Pb22, Pb23, Pin, PinId, +}; + +pin_and_tim!(Pa0, FunctionSelect::Sel1, 0); +pin_and_tim!(Pa1, FunctionSelect::Sel1, 1); +pin_and_tim!(Pa2, FunctionSelect::Sel1, 2); +pin_and_tim!(Pa3, FunctionSelect::Sel1, 3); +pin_and_tim!(Pa4, FunctionSelect::Sel1, 4); +pin_and_tim!(Pa5, FunctionSelect::Sel1, 5); +pin_and_tim!(Pa6, FunctionSelect::Sel1, 6); +pin_and_tim!(Pa7, FunctionSelect::Sel1, 7); +pin_and_tim!(Pa8, FunctionSelect::Sel1, 8); +pin_and_tim!(Pa9, FunctionSelect::Sel1, 9); +pin_and_tim!(Pa10, FunctionSelect::Sel1, 10); +pin_and_tim!(Pa11, FunctionSelect::Sel1, 11); +pin_and_tim!(Pa12, FunctionSelect::Sel1, 12); +pin_and_tim!(Pa13, FunctionSelect::Sel1, 13); +pin_and_tim!(Pa14, FunctionSelect::Sel1, 14); +pin_and_tim!(Pa15, FunctionSelect::Sel1, 15); + +pin_and_tim!(Pa24, FunctionSelect::Sel2, 16); +pin_and_tim!(Pa25, FunctionSelect::Sel2, 17); +pin_and_tim!(Pa26, FunctionSelect::Sel2, 18); +pin_and_tim!(Pa27, FunctionSelect::Sel2, 19); +pin_and_tim!(Pa28, FunctionSelect::Sel2, 20); +pin_and_tim!(Pa29, FunctionSelect::Sel2, 21); +pin_and_tim!(Pa30, FunctionSelect::Sel2, 22); +pin_and_tim!(Pa31, FunctionSelect::Sel2, 23); + +pin_and_tim!(Pb0, FunctionSelect::Sel3, 0); +pin_and_tim!(Pb1, FunctionSelect::Sel3, 1); +pin_and_tim!(Pb2, FunctionSelect::Sel3, 2); +pin_and_tim!(Pb3, FunctionSelect::Sel3, 3); +pin_and_tim!(Pb4, FunctionSelect::Sel3, 4); +pin_and_tim!(Pb5, FunctionSelect::Sel3, 5); +pin_and_tim!(Pb6, FunctionSelect::Sel3, 6); + +pin_and_tim!(Pb10, FunctionSelect::Sel3, 10); +pin_and_tim!(Pb11, FunctionSelect::Sel3, 11); +pin_and_tim!(Pb12, FunctionSelect::Sel3, 12); +pin_and_tim!(Pb13, FunctionSelect::Sel3, 13); +pin_and_tim!(Pb14, FunctionSelect::Sel3, 14); +pin_and_tim!(Pb15, FunctionSelect::Sel3, 15); +pin_and_tim!(Pb16, FunctionSelect::Sel3, 16); +pin_and_tim!(Pb17, FunctionSelect::Sel3, 17); +pin_and_tim!(Pb18, FunctionSelect::Sel3, 18); +pin_and_tim!(Pb19, FunctionSelect::Sel3, 19); +pin_and_tim!(Pb20, FunctionSelect::Sel3, 20); +pin_and_tim!(Pb21, FunctionSelect::Sel3, 21); +pin_and_tim!(Pb22, FunctionSelect::Sel3, 22); +pin_and_tim!(Pb23, FunctionSelect::Sel3, 23); diff --git a/vorago-shared-hal/src/timer/pins_vor4x.rs b/vorago-shared-hal/src/timer/pins_vor4x.rs new file mode 100644 index 0000000..7ac72bf --- /dev/null +++ b/vorago-shared-hal/src/timer/pins_vor4x.rs @@ -0,0 +1,132 @@ +use super::{FunctionSelect, TimId, TimPin}; +use crate::pins::{ + DynPinId, Pa0, Pa1, Pa2, Pa3, Pa4, Pa5, Pa6, Pa7, Pa8, Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, Pb0, + Pb1, Pb2, Pb3, Pb4, Pb12, Pb13, Pb14, Pb15, Pc0, Pc1, Pd10, Pd11, Pd12, Pd13, Pd14, Pd15, Pe0, + Pe1, Pe2, Pe3, Pe4, Pe5, Pe6, Pe7, Pe8, Pe9, Pe12, Pe13, Pe14, Pe15, Pf0, Pf1, Pf9, Pf11, Pf12, + Pf13, Pf14, Pf15, Pg0, Pg1, Pg2, Pg3, Pg6, Pin, PinId, +}; +#[cfg(not(feature = "va41628"))] +use crate::pins::{ + Pb5, Pb6, Pb7, Pb8, Pb9, Pb10, Pb11, Pd0, Pd1, Pd2, Pd3, Pd4, Pd5, Pd6, Pd7, Pd8, Pd9, Pe10, + Pe11, Pf2, Pf3, Pf4, Pf5, Pf6, Pf7, Pf8, Pf10, +}; + +pin_and_tim!(Pa0, FunctionSelect::Sel1, 0); +pin_and_tim!(Pa1, FunctionSelect::Sel1, 1); +pin_and_tim!(Pa2, FunctionSelect::Sel1, 2); +pin_and_tim!(Pa3, FunctionSelect::Sel1, 3); +pin_and_tim!(Pa4, FunctionSelect::Sel1, 4); +pin_and_tim!(Pa5, FunctionSelect::Sel1, 5); +pin_and_tim!(Pa6, FunctionSelect::Sel1, 6); +pin_and_tim!(Pa7, FunctionSelect::Sel1, 7); +pin_and_tim!(Pa8, FunctionSelect::Sel3, 8); +pin_and_tim!(Pa10, FunctionSelect::Sel2, 23); +pin_and_tim!(Pa11, FunctionSelect::Sel2, 22); +pin_and_tim!(Pa12, FunctionSelect::Sel2, 21); +pin_and_tim!(Pa13, FunctionSelect::Sel2, 20); +pin_and_tim!(Pa14, FunctionSelect::Sel2, 19); +pin_and_tim!(Pa15, FunctionSelect::Sel2, 18); + +pin_and_tim!(Pb0, FunctionSelect::Sel2, 17); +pin_and_tim!(Pb1, FunctionSelect::Sel2, 16); +pin_and_tim!(Pb2, FunctionSelect::Sel2, 15); +pin_and_tim!(Pb3, FunctionSelect::Sel2, 14); +pin_and_tim!(Pb4, FunctionSelect::Sel2, 13); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pb5, FunctionSelect::Sel2, 12); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pb6, FunctionSelect::Sel2, 11); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pb7, FunctionSelect::Sel2, 10); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pb8, FunctionSelect::Sel2, 9); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pb9, FunctionSelect::Sel2, 8); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pb10, FunctionSelect::Sel2, 7); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pb11, FunctionSelect::Sel2, 6); +pin_and_tim!(Pb12, FunctionSelect::Sel2, 5); +pin_and_tim!(Pb13, FunctionSelect::Sel2, 4); +pin_and_tim!(Pb14, FunctionSelect::Sel2, 3); +pin_and_tim!(Pb15, FunctionSelect::Sel2, 2); + +pin_and_tim!(Pc0, FunctionSelect::Sel2, 1); +pin_and_tim!(Pc1, FunctionSelect::Sel2, 0); + +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd0, FunctionSelect::Sel2, 0); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd1, FunctionSelect::Sel2, 1); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd2, FunctionSelect::Sel2, 2); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd3, FunctionSelect::Sel2, 3); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd4, FunctionSelect::Sel2, 4); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd5, FunctionSelect::Sel2, 5); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd6, FunctionSelect::Sel2, 6); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd7, FunctionSelect::Sel2, 7); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd8, FunctionSelect::Sel2, 8); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pd9, FunctionSelect::Sel2, 9); +pin_and_tim!(Pd10, FunctionSelect::Sel2, 10); +pin_and_tim!(Pd11, FunctionSelect::Sel2, 11); +pin_and_tim!(Pd12, FunctionSelect::Sel2, 12); +pin_and_tim!(Pd13, FunctionSelect::Sel2, 13); +pin_and_tim!(Pd14, FunctionSelect::Sel2, 14); +pin_and_tim!(Pd15, FunctionSelect::Sel2, 15); + +pin_and_tim!(Pe0, FunctionSelect::Sel2, 16); +pin_and_tim!(Pe1, FunctionSelect::Sel2, 17); +pin_and_tim!(Pe2, FunctionSelect::Sel2, 18); +pin_and_tim!(Pe3, FunctionSelect::Sel2, 19); +pin_and_tim!(Pe4, FunctionSelect::Sel2, 20); +pin_and_tim!(Pe5, FunctionSelect::Sel2, 21); +pin_and_tim!(Pe6, FunctionSelect::Sel2, 22); +pin_and_tim!(Pe7, FunctionSelect::Sel2, 23); +pin_and_tim!(Pe8, FunctionSelect::Sel3, 16); +pin_and_tim!(Pe9, FunctionSelect::Sel3, 17); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pe10, FunctionSelect::Sel3, 18); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pe11, FunctionSelect::Sel3, 19); +pin_and_tim!(Pe12, FunctionSelect::Sel3, 20); +pin_and_tim!(Pe13, FunctionSelect::Sel3, 21); +pin_and_tim!(Pe14, FunctionSelect::Sel3, 22); +pin_and_tim!(Pe15, FunctionSelect::Sel3, 23); + +pin_and_tim!(Pf0, FunctionSelect::Sel3, 0); +pin_and_tim!(Pf1, FunctionSelect::Sel3, 1); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pf2, FunctionSelect::Sel3, 2); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pf3, FunctionSelect::Sel3, 3); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pf4, FunctionSelect::Sel3, 4); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pf5, FunctionSelect::Sel3, 5); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pf6, FunctionSelect::Sel3, 6); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pf7, FunctionSelect::Sel3, 7); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pf8, FunctionSelect::Sel3, 8); +pin_and_tim!(Pf9, FunctionSelect::Sel3, 9); +#[cfg(not(feature = "va41628"))] +pin_and_tim!(Pf10, FunctionSelect::Sel3, 10); +pin_and_tim!(Pf11, FunctionSelect::Sel3, 11); +pin_and_tim!(Pf12, FunctionSelect::Sel3, 12); +pin_and_tim!(Pf13, FunctionSelect::Sel2, 19); +pin_and_tim!(Pf14, FunctionSelect::Sel2, 20); +pin_and_tim!(Pf15, FunctionSelect::Sel2, 21); + +pin_and_tim!(Pg0, FunctionSelect::Sel2, 22); +pin_and_tim!(Pg1, FunctionSelect::Sel2, 23); +pin_and_tim!(Pg2, FunctionSelect::Sel1, 9); +pin_and_tim!(Pg3, FunctionSelect::Sel1, 10); +pin_and_tim!(Pg6, FunctionSelect::Sel1, 12); diff --git a/vorago-shared-hal/src/timer/regs.rs b/vorago-shared-hal/src/timer/regs.rs new file mode 100644 index 0000000..fdc691f --- /dev/null +++ b/vorago-shared-hal/src/timer/regs.rs @@ -0,0 +1,431 @@ +use core::marker::PhantomData; + +use arbitrary_int::{prelude::*, u7}; + +#[cfg(feature = "vor1x")] +const BASE_ADDR: usize = 0x4002_0000; +#[cfg(feature = "vor4x")] +const BASE_ADDR: usize = 0x4001_8000; + +#[bitbybit::bitenum(u3)] +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum StatusSelect { + /// Pulse when timer reaches 0. + OneCyclePulse = 0b000, + OutputActiveBit = 0b001, + /// Creates a divide by two output clock of the timer. + ToggleOnEachCycle = 0b010, + /// 1 when count value >= PWM A value, 0 otherwise + PwmaOutput = 0b011, + /// 1 when count value < PWM A value and >= PWM B, 0 when counter value >= PWM A value or < PWM + /// B value + PwmbOutput = 0b100, + EnabledBit = 0b101, + /// 1 when counter value <= PWM A value and 0 otherwise. + PwmaActiveBit = 0b110, +} + +#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))] +pub struct Control { + /// The counter is requested to stop on the next normal count cycle. + #[bit(9, rw)] + request_stop: bool, + #[bit(8, rw)] + status_invert: bool, + #[bits(5..=7, rw)] + status_sel: Option, + #[bit(4, rw)] + irq_enable: bool, + /// Only applies if the Auto-Disable bit is 0. The ACTIVE bit goes to 0 when the count reaches + /// 0, but the timer remains enabled. + #[bit(3, rw)] + auto_deactivate: bool, + /// Counter is fully disabled when count reaches 0, which means that both the ENABLE + /// and ACTIVE bits go to 0. + #[bit(2, rw)] + auto_disable: bool, + #[bit(1, r)] + active: bool, + #[bit(0, rw)] + enable: bool, +} + +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct EnableControl(arbitrary_int::UInt); + +impl EnableControl { + pub fn new_disable() -> Self { + EnableControl(arbitrary_int::UInt::::from_u32(0)) + } + + pub fn new_enable() -> Self { + EnableControl(arbitrary_int::UInt::::from_u32(1)) + } + + pub fn enabled(&self) -> bool { + self.0.value() != 0 + } +} + +#[bitbybit::bitenum(u1, exhaustive = true)] +#[derive(Default, Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum CascadeInvert { + #[default] + ActiveHigh = 0, + ActiveLow = 1, +} + +/// When two cascade sources are selected, configure the required operation. +#[bitbybit::bitenum(u1, exhaustive = true)] +#[derive(Default, Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum DualCascadeOp { + #[default] + LogicalAnd = 0, + LogicalOr = 1, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))] +pub struct CascadeControl { + /// The counter is automatically disabled if the corresponding Cascade 2 level-sensitive input + /// souce is active when the count reaches 0. If the counter is not 0, the cascade control is + /// ignored. + #[bit(10, rw)] + trigger2: bool, + #[bit(9, rw)] + inv2: CascadeInvert, + /// Enable Cascade 2 signal active as a requirement to stop counting. This mode is similar + /// to the REQ_STOP control bit, but signalled by a Cascade source. + #[bit(8, rw)] + en2: bool, + /// Same as the trigger field for Cascade 0. + #[bit(7, rw)] + trigger1: bool, + /// Enable trigger mode for Cascade 0. In trigger mode, couting will start with the selected + /// cascade signal active, but once the counter is active, cascade control will be ignored. + #[bit(6, rw)] + trigger0: bool, + /// Specify required operation if both Cascade 0 and Cascade 1 are active. + /// 0 is a logical AND of both cascade signals, 1 is a logical OR. + #[bit(4, rw)] + dual_cascade_op: DualCascadeOp, + /// Inversion bit for Cascade 1 + #[bit(3, rw)] + inv1: CascadeInvert, + /// Enable Cascade 1 signal active as a requirement for counting. + #[bit(2, rw)] + en1: bool, + /// Inversion bit for Cascade 0. + #[bit(1, rw)] + inv0: CascadeInvert, + /// Enable Cascade 0 signal active as a requirement for counting. + #[bit(0, rw)] + en0: bool, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InvalidCascadeSourceId; + +#[cfg(feature = "vor1x")] +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[repr(u8)] +pub enum CascadeSource { + PortA(u8), + PortB(u8), + Tim(u8), + RamSbe = 96, + RamMbe = 97, + RomSbe = 98, + RomMbe = 99, + Txev = 100, + ClockDivider(u8), +} + +#[cfg(feature = "vor4x")] +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[repr(u8)] +pub enum CascadeSource { + PortA(u8), + PortB(u8), + PortC(u8), + PortD(u8), + PortE(u8), + Tim(u8), + TxEv, + AdcIrq, + RomSbe, + RomMbe, + Ram0Sbe, + Ram0Mbe, + Ram1Sbe, + Ram1Mbe, + WdogIrq, +} + +impl CascadeSource { + #[cfg(feature = "vor1x")] + pub fn id(&self) -> Result { + let port_check = |base: u8, id: u8, len: u8| -> Result { + if id > len - 1 { + return Err(InvalidCascadeSourceId); + } + Ok(u7::new(base + id)) + }; + match self { + CascadeSource::PortA(id) => port_check(0, *id, 32), + CascadeSource::PortB(id) => port_check(32, *id, 32), + CascadeSource::Tim(id) => port_check(64, *id, 24), + CascadeSource::RamSbe => Ok(u7::new(96)), + CascadeSource::RamMbe => Ok(u7::new(97)), + CascadeSource::RomSbe => Ok(u7::new(98)), + CascadeSource::RomMbe => Ok(u7::new(99)), + CascadeSource::Txev => Ok(u7::new(100)), + CascadeSource::ClockDivider(id) => port_check(120, *id, 8), + } + } + + #[cfg(feature = "vor4x")] + fn id(&self) -> Result { + let port_check = |base: u8, id: u8| -> Result { + if id > 15 { + return Err(InvalidCascadeSourceId); + } + Ok(u7::new(base + id)) + }; + match self { + CascadeSource::PortA(id) => port_check(0, *id), + CascadeSource::PortB(id) => port_check(16, *id), + CascadeSource::PortC(id) => port_check(32, *id), + CascadeSource::PortD(id) => port_check(48, *id), + CascadeSource::PortE(id) => port_check(64, *id), + CascadeSource::Tim(id) => { + if *id > 23 { + return Err(InvalidCascadeSourceId); + } + Ok(u7::new(80 + id)) + } + CascadeSource::TxEv => Ok(u7::new(104)), + CascadeSource::AdcIrq => Ok(u7::new(105)), + CascadeSource::RomSbe => Ok(u7::new(106)), + CascadeSource::RomMbe => Ok(u7::new(106)), + CascadeSource::Ram0Sbe => Ok(u7::new(108)), + CascadeSource::Ram0Mbe => Ok(u7::new(109)), + CascadeSource::Ram1Sbe => Ok(u7::new(110)), + CascadeSource::Ram1Mbe => Ok(u7::new(111)), + CascadeSource::WdogIrq => Ok(u7::new(112)), + } + } + + #[cfg(feature = "vor1x")] + pub fn from_raw(raw: u32) -> Result { + let id = u7::new((raw & 0x7F) as u8); + if id.value() > 127 { + return Err(InvalidCascadeSourceId); + } + let id = id.as_u8(); + if id < 32 { + return Ok(CascadeSource::PortA(id)); + } else if (32..56).contains(&id) { + return Ok(CascadeSource::PortB(id - 32)); + } else if (64..88).contains(&id) { + return Ok(CascadeSource::Tim(id - 64)); + } else if id > 120 { + return Ok(CascadeSource::ClockDivider(id - 120)); + } + match id { + 96 => Ok(CascadeSource::RamSbe), + 97 => Ok(CascadeSource::RamMbe), + 98 => Ok(CascadeSource::RomSbe), + 99 => Ok(CascadeSource::RomMbe), + 100 => Ok(CascadeSource::Txev), + _ => Err(InvalidCascadeSourceId), + } + } + #[cfg(feature = "vor4x")] + pub fn from_raw(raw: u32) -> Result { + use crate::NUM_PORT_DEFAULT; + + let id = u7::new((raw & 0x7F) as u8); + if id.value() > 127 { + return Err(InvalidCascadeSourceId); + } + let id = id.as_u8(); + if id < 16 { + return Ok(CascadeSource::PortA(id)); + } else if (16..16 + NUM_PORT_DEFAULT as u8).contains(&id) { + return Ok(CascadeSource::PortB(id - 16)); + } else if (32..32 + NUM_PORT_DEFAULT as u8).contains(&id) { + return Ok(CascadeSource::PortC(id - 32)); + } else if (48..48 + NUM_PORT_DEFAULT as u8).contains(&id) { + return Ok(CascadeSource::PortD(id - 48)); + } else if (64..64 + NUM_PORT_DEFAULT as u8).contains(&id) { + return Ok(CascadeSource::PortE(id - 64)); + } else if (80..104).contains(&id) { + return Ok(CascadeSource::Tim(id - 80)); + } + match id { + 104 => Ok(CascadeSource::TxEv), + 105 => Ok(CascadeSource::AdcIrq), + 106 => Ok(CascadeSource::RomSbe), + 107 => Ok(CascadeSource::RomMbe), + 108 => Ok(CascadeSource::Ram0Sbe), + 109 => Ok(CascadeSource::Ram0Mbe), + 110 => Ok(CascadeSource::Ram1Sbe), + 111 => Ok(CascadeSource::Ram1Mbe), + 112 => Ok(CascadeSource::WdogIrq), + _ => Err(InvalidCascadeSourceId), + } + } +} + +#[bitbybit::bitfield(u32)] +pub struct CascadeSourceReg { + #[bits(0..=6, rw)] + raw: u7, +} + +impl CascadeSourceReg { + pub fn new(source: CascadeSource) -> Result { + let id = source.id()?; + Ok(Self::new_with_raw_value(id.as_u32())) + } + + pub fn as_cascade_source(&self) -> Result { + CascadeSource::from_raw(self.raw().as_u32()) + } +} + +#[derive(derive_mmio::Mmio)] +#[mmio(no_ctors)] +#[repr(C)] +pub struct Timer { + control: Control, + reset_value: u32, + count_value: u32, + enable_control: EnableControl, + cascade_control: CascadeControl, + /// CASCADE0 and CASCADE1 are used to control the counting and activation of the counter. + /// CASCADE2 is used to request stopping of the timer. + cascade: [CascadeSourceReg; 3], + /// PWM A compare value. + pwma_value: u32, + /// PWM B compare value. + pwmb_value: u32, + #[cfg(feature = "vor1x")] + _reserved: [u32; 0x3f5], + #[cfg(feature = "vor4x")] + _reserved: [u32; 0xf5], + /// Vorago 1x: 0x0111_07E1. Vorago 4x: 0x0211_07E9 + perid: u32, +} + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + static_assertions::const_assert_eq!(core::mem::size_of::(), 0x1000); + } else if #[cfg(feature = "vor4x")] { + static_assertions::const_assert_eq!(core::mem::size_of::(), 0x400); + } +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InvalidTimerIndex(pub usize); + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct TimId(u8); + +impl TimId { + pub const fn new(index: usize) -> Result { + if index > 23 { + return Err(InvalidTimerIndex(index)); + } + Ok(TimId(index as u8)) + } + + pub const fn new_unchecked(index: usize) -> Self { + if index > 23 { + panic!("invalid timer index"); + } + TimId(index as u8) + } + + /// Unsafely steal the TIM peripheral block for the TIM ID. + /// + /// # Safety + /// + /// Circumvents ownership and safety guarantees by the HAL. + pub const unsafe fn steal_regs(&self) -> MmioTimer<'static> { + Timer::new_mmio(*self) + } + + pub const fn value(&self) -> u8 { + self.0 + } + + #[cfg(feature = "vor4x")] + pub const fn interrupt_id(&self) -> va416xx::Interrupt { + match self.value() { + 0 => va416xx::Interrupt::TIM0, + 1 => va416xx::Interrupt::TIM1, + 2 => va416xx::Interrupt::TIM2, + 3 => va416xx::Interrupt::TIM3, + 4 => va416xx::Interrupt::TIM4, + 5 => va416xx::Interrupt::TIM5, + 6 => va416xx::Interrupt::TIM6, + 7 => va416xx::Interrupt::TIM7, + 8 => va416xx::Interrupt::TIM8, + 9 => va416xx::Interrupt::TIM9, + 10 => va416xx::Interrupt::TIM10, + 11 => va416xx::Interrupt::TIM11, + 12 => va416xx::Interrupt::TIM12, + 13 => va416xx::Interrupt::TIM13, + 14 => va416xx::Interrupt::TIM14, + 15 => va416xx::Interrupt::TIM15, + 16 => va416xx::Interrupt::TIM16, + 17 => va416xx::Interrupt::TIM17, + 18 => va416xx::Interrupt::TIM18, + 19 => va416xx::Interrupt::TIM19, + 20 => va416xx::Interrupt::TIM20, + 21 => va416xx::Interrupt::TIM21, + 22 => va416xx::Interrupt::TIM22, + 23 => va416xx::Interrupt::TIM23, + _ => unreachable!(), + } + } +} + +impl Timer { + const fn new_mmio_at(base: usize) -> MmioTimer<'static> { + MmioTimer { + ptr: base as *mut _, + phantom: PhantomData, + } + } + + pub const fn new_mmio(id: TimId) -> MmioTimer<'static> { + if cfg!(feature = "vor1x") { + Timer::new_mmio_at(BASE_ADDR + 0x1000 * id.value() as usize) + } else { + Timer::new_mmio_at(BASE_ADDR + 0x400 * id.value() as usize) + } + } + pub fn new_mmio_with_raw_index( + timer_index: usize, + ) -> Result, InvalidTimerIndex> { + if timer_index > 23 { + return Err(InvalidTimerIndex(timer_index)); + } + if cfg!(feature = "vor1x") { + Ok(Timer::new_mmio_at(BASE_ADDR + 0x1000 * timer_index)) + } else { + Ok(Timer::new_mmio_at(BASE_ADDR + 0x400 * timer_index)) + } + } +} diff --git a/vorago-shared-hal/src/uart/mod.rs b/vorago-shared-hal/src/uart/mod.rs new file mode 100644 index 0000000..2c606a3 --- /dev/null +++ b/vorago-shared-hal/src/uart/mod.rs @@ -0,0 +1,1306 @@ +//! # API for the UART peripheral +//! +//! The core of this API are the [Uart], [Rx] and [Tx] structures. +//! The RX structure also has a dedicated [RxWithInterrupt] variant which allows reading the receiver +//! using interrupts. +//! +//! The [rx_asynch] and [tx_asynch] modules provide an asynchronous non-blocking API for the UART +//! peripheral. +//! +//! ## Examples +//! +//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/uart.rs) +//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs) +//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader) +use core::convert::Infallible; +pub mod regs; +#[cfg(feature = "vor1x")] +use crate::InterruptConfig; +use crate::{FunctionSelect, gpio::IoPeriphPin, pins::AnyPin, sealed::Sealed}; +use arbitrary_int::{prelude::*, u6, u18}; +use fugit::RateExtU32; +use regs::{ClockScale, Control, Data, Enable, FifoClear, InterruptClear, MmioUart}; + +use crate::{PeripheralSelect, enable_nvic_interrupt, enable_peripheral_clock, time::Hertz}; +use embedded_hal_nb::serial::Read; +pub use regs::{Bank, Stopbits, WordSize}; + +#[cfg(feature = "vor1x")] +mod pins_vor1x; +#[cfg(feature = "vor4x")] +mod pins_vor4x; + +#[cfg(feature = "vor4x")] +use crate::clock::Clocks; +#[cfg(feature = "vor1x")] +use va108xx as pac; +#[cfg(feature = "vor4x")] +use va416xx as pac; + +pub mod tx_asynch; +pub use tx_asynch::*; + +pub mod rx_asynch; +pub use rx_asynch::*; + +//================================================================================================== +// Type-Level support +//================================================================================================== + +pub trait TxPin: AnyPin { + const BANK: Bank; + const FUN_SEL: FunctionSelect; +} +pub trait RxPin: AnyPin { + const BANK: Bank; + const FUN_SEL: FunctionSelect; +} + +//================================================================================================== +// Regular Definitions +//================================================================================================== + +#[derive(Debug, PartialEq, Eq, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("no interrupt ID was set")] +pub struct NoInterruptIdWasSet; + +#[derive(Debug, PartialEq, Eq, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("transer is pending")] +pub struct TransferPendingError; + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Event { + // Receiver FIFO interrupt enable. Generates interrupt + // when FIFO is at least half full. Half full is defined as FIFO + // count >= RXFIFOIRQTRG + RxFifoHalfFull, + // Framing error, Overrun error, Parity Error and Break error + RxError, + // Event for timeout condition: Data in the FIFO and no receiver + // FIFO activity for 4 character times + RxTimeout, + + // Transmitter FIFO interrupt enable. Generates interrupt + // when FIFO is at least half full. Half full is defined as FIFO + // count >= TXFIFOIRQTRG + TxFifoHalfFull, + // FIFO overflow error + TxError, + // Generate interrupt when transmit FIFO is empty and TXBUSY is 0 + TxEmpty, + // Interrupt when CTSn changes value + TxCts, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Parity { + None, + Odd, + Even, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct Config { + pub baudrate: Hertz, + pub parity: Parity, + pub stopbits: Stopbits, + // When false, use standard 16x baud clock, other 8x baud clock + pub baud8: bool, + pub wordsize: WordSize, + pub enable_tx: bool, + pub enable_rx: bool, +} + +impl Config { + pub fn baudrate(mut self, baudrate: Hertz) -> Self { + self.baudrate = baudrate; + self + } + + pub fn parity_none(mut self) -> Self { + self.parity = Parity::None; + self + } + + pub fn parity_even(mut self) -> Self { + self.parity = Parity::Even; + self + } + + pub fn parity_odd(mut self) -> Self { + self.parity = Parity::Odd; + self + } + + pub fn stopbits(mut self, stopbits: Stopbits) -> Self { + self.stopbits = stopbits; + self + } + + pub fn wordsize(mut self, wordsize: WordSize) -> Self { + self.wordsize = wordsize; + self + } + + pub fn baud8(mut self, baud: bool) -> Self { + self.baud8 = baud; + self + } +} + +impl Default for Config { + fn default() -> Config { + let baudrate = 115_200_u32.Hz(); + Config { + baudrate, + parity: Parity::None, + stopbits: Stopbits::One, + baud8: false, + wordsize: WordSize::Eight, + enable_tx: true, + enable_rx: true, + } + } +} + +impl From for Config { + fn from(baud: Hertz) -> Self { + Config::default().baudrate(baud) + } +} + +//================================================================================================== +// IRQ Definitions +//================================================================================================== + +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InterruptContextTimeoutOrMaxSize { + rx_idx: usize, + mode: InterruptReceptionMode, + pub max_len: usize, +} + +impl InterruptContextTimeoutOrMaxSize { + pub fn new(max_len: usize) -> Self { + InterruptContextTimeoutOrMaxSize { + rx_idx: 0, + max_len, + mode: InterruptReceptionMode::Idle, + } + } +} + +impl InterruptContextTimeoutOrMaxSize { + pub fn reset(&mut self) { + self.rx_idx = 0; + self.mode = InterruptReceptionMode::Idle; + } +} + +/// This struct is used to return the default IRQ handler result to the user +#[derive(Debug, Default)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InterruptResult { + pub bytes_read: usize, + pub errors: Option, +} + +/// This struct is used to return the default IRQ handler result to the user +#[derive(Debug, Default)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InterruptResultMaxSizeOrTimeout { + complete: bool, + timeout: bool, + pub errors: Option, + pub bytes_read: usize, +} + +impl InterruptResultMaxSizeOrTimeout { + pub fn new() -> Self { + InterruptResultMaxSizeOrTimeout { + complete: false, + timeout: false, + errors: None, + bytes_read: 0, + } + } +} +impl InterruptResultMaxSizeOrTimeout { + #[inline] + pub fn has_errors(&self) -> bool { + self.errors.is_some() + } + + #[inline] + pub fn overflow_error(&self) -> bool { + self.errors.is_some_and(|e| e.overflow) + } + + #[inline] + pub fn framing_error(&self) -> bool { + self.errors.is_some_and(|e| e.framing) + } + + #[inline] + pub fn parity_error(&self) -> bool { + self.errors.is_some_and(|e| e.parity) + } + + #[inline] + pub fn timeout(&self) -> bool { + self.timeout + } + + #[inline] + pub fn complete(&self) -> bool { + self.complete + } +} + +#[derive(Debug, PartialEq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +enum InterruptReceptionMode { + Idle, + Pending, +} + +#[derive(Default, Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct UartErrors { + overflow: bool, + framing: bool, + parity: bool, + other: bool, +} + +impl UartErrors { + #[inline(always)] + pub fn overflow(&self) -> bool { + self.overflow + } + + #[inline(always)] + pub fn framing(&self) -> bool { + self.framing + } + + #[inline(always)] + pub fn parity(&self) -> bool { + self.parity + } + + #[inline(always)] + pub fn other(&self) -> bool { + self.other + } +} + +impl UartErrors { + #[inline(always)] + pub fn error(&self) -> bool { + self.overflow || self.framing || self.parity || self.other + } +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct BufferTooShortError { + found: usize, + expected: usize, +} + +//================================================================================================== +// UART peripheral wrapper +//================================================================================================== + +pub trait UartInstance: Sealed { + const ID: Bank; + const PERIPH_SEL: PeripheralSelect; +} + +#[cfg(feature = "vor1x")] +pub type Uart0 = pac::Uarta; +#[cfg(feature = "vor4x")] +pub type Uart0 = pac::Uart0; + +impl UartInstance for Uart0 { + const ID: Bank = Bank::Uart0; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart0; +} +impl Sealed for Uart0 {} + +#[cfg(feature = "vor1x")] +pub type Uart1 = pac::Uartb; +#[cfg(feature = "vor4x")] +pub type Uart1 = pac::Uart1; + +impl UartInstance for Uart1 { + const ID: Bank = Bank::Uart1; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart1; +} +impl Sealed for Uart1 {} + +#[cfg(feature = "vor4x")] +impl UartInstance for pac::Uart2 { + const ID: Bank = Bank::Uart2; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart2; +} +#[cfg(feature = "vor4x")] +impl Sealed for pac::Uart2 {} + +#[derive(Debug, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("UART ID missmatch between peripheral and pins.")] +pub struct UartIdMissmatchError; + +//================================================================================================== +// UART implementation +//================================================================================================== + +/// UART driver structure. +pub struct Uart { + tx: Tx, + rx: Rx, +} + +impl Uart { + cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + /// Calls [Self::new] with the interrupt configuration to some valid value. + pub fn new_with_interrupt( + uart: UartPeriph, + tx_pin: Tx, + rx_pin: Rx, + sys_clk: Hertz, + config: Config, + irq_cfg: InterruptConfig, + ) -> Result { + Self::new(uart, tx_pin, rx_pin, sys_clk, config, Some(irq_cfg)) + } + + /// Calls [Self::new] with the interrupt configuration to [None]. + pub fn new_without_interrupt( + uart: UartPeriph, + tx_pin: Tx, + rx_pin: Rx, + sys_clk: Hertz, + config: Config, + ) -> Result { + Self::new(uart, tx_pin, rx_pin, sys_clk, config, None) + } + + /// Create a new UART peripheral driver with an interrupt configuration. + /// + /// # Arguments + /// + /// - `syscfg`: The system configuration register block + /// - `sys_clk`: The system clock frequency + /// - `uart`: The concrete UART peripheral instance. + /// - `pins`: UART TX and RX pin tuple. + /// - `config`: UART specific configuration parameters like baudrate. + /// - `irq_cfg`: Optional interrupt configuration. This should be a valid value if the plan + /// is to use TX or RX functionality relying on interrupts. If only the blocking API without + /// any interrupt support is used, this can be [None]. + pub fn new( + uart: UartPeriph, + tx_pin: Tx, + rx_pin: Rx, + sys_clk: Hertz, + config: Config, + opt_irq_cfg: Option, + ) -> Result { + Self::new_internal(uart, (tx_pin, rx_pin), sys_clk, config, opt_irq_cfg) + } + } else if #[cfg(feature = "vor4x")] { + /// Create a new UART peripheral driver. + /// + /// # Arguments + /// + /// - `clks`: Frozen system clock configuration. + /// - `uart`: The concrete UART peripheral instance. + /// - `pins`: UART TX and RX pin tuple. + /// - `config`: UART specific configuration parameters like baudrate. + pub fn new( + uart: UartI, + tx_pin: Tx, + rx_pin: Rx, + clks: &Clocks, + config: Config, + ) -> Result { + if UartI::ID == Bank::Uart2 { + Self::new_internal(uart, (tx_pin, rx_pin), clks.apb1(), config) + } else { + Self::new_internal(uart, (tx_pin, rx_pin), clks.apb2(), config) + } + } + + /// Create a new UART peripheral driver given a reference clock. + /// + /// # Arguments + /// + /// - `ref_clk`: APB1 clock for UART2, APB2 clock otherwise. + /// - `uart`: The concrete UART peripheral instance. + /// - `pins`: UART TX and RX pin tuple. + /// - `config`: UART specific configuration parameters like baudrate. + pub fn new_with_ref_clk( + uart: Uart, + tx_pin: Tx, + rx_pin: Rx, + ref_clk: Hertz, + config: Config, + ) -> Result { + Self::new_internal(uart,(tx_pin, rx_pin),ref_clk, config) + } + } + } + + fn new_internal( + _uart: UartI, + _pins: (TxPinI, RxPinI), + ref_clk: Hertz, + config: Config, + #[cfg(feature = "vor1x")] opt_irq_cfg: Option, + ) -> Result { + if UartI::ID != TxPinI::BANK || UartI::ID != RxPinI::BANK { + return Err(UartIdMissmatchError); + } + IoPeriphPin::new(TxPinI::ID, TxPinI::FUN_SEL, None); + IoPeriphPin::new(RxPinI::ID, TxPinI::FUN_SEL, None); + enable_peripheral_clock(UartI::PERIPH_SEL); + + let mut reg_block = regs::Uart::new_mmio(UartI::ID); + let baud_multiplier = match config.baud8 { + false => 16, + true => 8, + }; + + // This is the calculation: (64.0 * (x - integer_part as f32) + 0.5) as u32 without floating + // point calculations. + let frac = ((ref_clk.raw() % (config.baudrate.raw() * 16)) * 64 + + (config.baudrate.raw() * 8)) + / (config.baudrate.raw() * 16); + // Calculations here are derived from chapter 4.8.5 (p.79) of the datasheet. + let x = ref_clk.raw() as f32 / (config.baudrate.raw() * baud_multiplier) as f32; + let integer_part = x as u32; + reg_block.write_clkscale( + ClockScale::builder() + .with_int(u18::new(integer_part)) + .with_frac(u6::new(frac as u8)) + .build(), + ); + + let (paren, pareven) = match config.parity { + Parity::None => (false, false), + Parity::Odd => (true, false), + Parity::Even => (true, true), + }; + reg_block.write_ctrl( + Control::builder() + .with_baud8(config.baud8) + .with_auto_rts(false) + .with_def_rts(false) + .with_auto_cts(false) + .with_loopback_block(false) + .with_loopback(false) + .with_wordsize(config.wordsize) + .with_stopbits(config.stopbits) + .with_parity_manual(false) + .with_parity_even(pareven) + .with_parity_enable(paren) + .build(), + ); + // Clear the FIFO + reg_block.write_fifo_clr(FifoClear::builder().with_tx(true).with_rx(true).build()); + reg_block.write_enable( + Enable::builder() + .with_tx(config.enable_tx) + .with_rx(config.enable_rx) + .build(), + ); + + #[cfg(feature = "vor1x")] + if let Some(irq_cfg) = opt_irq_cfg { + if irq_cfg.route { + enable_peripheral_clock(PeripheralSelect::Irqsel); + unsafe { va108xx::Irqsel::steal() } + .uart(UartI::ID as usize) + .write(|w| unsafe { w.bits(irq_cfg.id as u32) }); + } + if irq_cfg.enable_in_nvic { + // Safety: User has specifically configured this. + unsafe { enable_nvic_interrupt(irq_cfg.id) }; + } + } + + Ok(Uart { + tx: Tx::new(UartI::ID), + rx: Rx::new(UartI::ID), + }) + } + + #[inline] + pub fn peripheral_id(&self) -> u32 { + self.tx.perid() + } + + #[inline] + pub fn enable_rx(&mut self) { + self.rx.enable(); + } + + #[inline] + pub fn disable_rx(&mut self) { + self.rx.disable(); + } + + #[inline] + pub fn enable_tx(&mut self) { + self.tx.enable(); + } + + #[inline] + pub fn disable_tx(&mut self) { + self.tx.disable(); + } + + /// This also clears status conditons for the RX FIFO. + #[inline] + pub fn clear_rx_fifo(&mut self) { + self.rx.clear_fifo(); + } + + /// This also clears status conditons for the TX FIFO. + #[inline] + pub fn clear_tx_fifo(&mut self) { + self.tx.clear_fifo(); + } + + pub fn listen(&mut self, event: Event) { + self.tx.regs.modify_irq_enabled(|mut value| { + match event { + Event::RxError => value.set_rx_status(true), + Event::RxFifoHalfFull => value.set_rx(true), + Event::RxTimeout => value.set_rx_timeout(true), + Event::TxEmpty => value.set_tx_empty(true), + Event::TxError => value.set_tx_status(true), + Event::TxFifoHalfFull => value.set_tx(true), + Event::TxCts => value.set_tx_cts(true), + } + value + }); + } + + pub fn unlisten(&mut self, event: Event) { + self.tx.regs.modify_irq_enabled(|mut value| { + match event { + Event::RxError => value.set_rx_status(false), + Event::RxFifoHalfFull => value.set_rx(false), + Event::RxTimeout => value.set_rx_timeout(false), + Event::TxEmpty => value.set_tx_empty(false), + Event::TxError => value.set_tx_status(false), + Event::TxFifoHalfFull => value.set_tx(false), + Event::TxCts => value.set_tx_cts(false), + } + value + }); + } + + /// Poll receiver errors. + pub fn poll_rx_errors(&self) -> Option { + self.rx.poll_errors() + } + + pub fn split(self) -> (Tx, Rx) { + (self.tx, self.rx) + } +} + +impl embedded_io::ErrorType for Uart { + type Error = Infallible; +} + +impl embedded_hal_nb::serial::ErrorType for Uart { + type Error = Infallible; +} + +impl embedded_hal_nb::serial::Read for Uart { + fn read(&mut self) -> nb::Result { + self.rx.read() + } +} + +impl embedded_hal_nb::serial::Write for Uart { + fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { + self.tx.write(word).map_err(|e| { + if let nb::Error::Other(_) = e { + unreachable!() + } + nb::Error::WouldBlock + }) + } + + fn flush(&mut self) -> nb::Result<(), Self::Error> { + self.tx.flush().map_err(|e| { + if let nb::Error::Other(_) = e { + unreachable!() + } + nb::Error::WouldBlock + }) + } +} + +#[inline(always)] +pub fn enable_rx(uart: &mut MmioUart<'static>) { + uart.modify_enable(|mut value| { + value.set_rx(true); + value + }); +} + +#[inline(always)] +pub fn disable_rx(uart: &mut MmioUart<'static>) { + uart.modify_enable(|mut value| { + value.set_rx(false); + value + }); +} + +#[inline(always)] +pub fn enable_rx_interrupts(uart: &mut MmioUart<'static>, timeout: bool) { + uart.modify_irq_enabled(|mut value| { + value.set_rx_status(true); + value.set_rx(true); + if timeout { + value.set_rx_timeout(true); + } + value + }); +} + +#[inline(always)] +pub fn disable_rx_interrupts(uart: &mut MmioUart<'static>) { + uart.modify_irq_enabled(|mut value| { + value.set_rx_status(false); + value.set_rx(false); + value.set_rx_timeout(false); + value + }); +} + +/// Serial receiver. +/// +/// Can be created by using the [Uart::split] API. +pub struct Rx { + id: Bank, + regs: regs::MmioUart<'static>, +} + +impl Rx { + /// Retrieve a TX pin without expecting an explicit UART structure + /// + /// # Safety + /// + /// Circumvents the HAL safety guarantees. + #[inline(always)] + pub unsafe fn steal(id: Bank) -> Self { + Self::new(id) + } + + #[inline(always)] + fn new(id: Bank) -> Self { + Self { + id, + regs: regs::Uart::new_mmio(id), + } + } + + pub fn poll_errors(&self) -> Option { + let mut errors = UartErrors::default(); + + let status = self.regs.read_rx_status(); + if status.overrun_error() { + errors.overflow = true; + } else if status.framing_error() { + errors.framing = true; + } else if status.parity_error() { + errors.parity = true; + } else { + return None; + }; + Some(errors) + } + + #[inline] + pub fn perid(&self) -> u32 { + self.regs.read_perid() + } + + #[inline] + pub fn clear_fifo(&mut self) { + self.regs + .write_fifo_clr(FifoClear::builder().with_tx(false).with_rx(true).build()); + } + + #[inline] + pub fn disable_interrupts(&mut self) { + disable_rx_interrupts(&mut self.regs); + } + + #[inline] + pub fn enable_interrupts( + &mut self, + #[cfg(feature = "vor4x")] enable_in_nvic: bool, + timeout: bool, + ) { + #[cfg(feature = "vor4x")] + if enable_in_nvic { + unsafe { + enable_nvic_interrupt(self.id.interrupt_id_rx()); + } + } + enable_rx_interrupts(&mut self.regs, timeout); + } + + #[inline] + pub fn enable(&mut self) { + enable_rx(&mut self.regs); + } + + #[inline] + pub fn disable(&mut self) { + disable_rx(&mut self.regs); + } + + /// Low level function to read a word from the UART FIFO. + /// + /// Uses the [nb] API to allow usage in blocking and non-blocking contexts. + /// + /// Please note that you might have to mask the returned value with 0xff to retrieve the actual + /// value if you use the manual parity mode. See chapter 4.6.2 for more information. + #[inline(always)] + pub fn read_fifo(&mut self) -> nb::Result { + if !self.regs.read_rx_status().data_available() { + return Err(nb::Error::WouldBlock); + } + Ok(self.read_fifo_unchecked()) + } + + /// Low level function to read a word from from the UART FIFO. + /// + /// This does not necesarily mean there is a word in the FIFO available. + /// Use the [Self::read_fifo] function to read a word from the FIFO reliably using the [nb] + /// API. + /// + /// Please note that you might have to mask the returned value with 0xff to retrieve the actual + /// value if you use the manual parity mode. See chapter 4.6.2 for more information. + #[inline(always)] + pub fn read_fifo_unchecked(&mut self) -> u32 { + self.regs.read_data().raw_value() + } + + pub fn into_rx_with_irq(self) -> RxWithInterrupt { + RxWithInterrupt::new(self) + } +} + +impl embedded_io::ErrorType for Rx { + type Error = Infallible; +} + +impl embedded_hal_nb::serial::ErrorType for Rx { + type Error = Infallible; +} + +impl embedded_hal_nb::serial::Read for Rx { + fn read(&mut self) -> nb::Result { + self.read_fifo().map(|val| (val & 0xff) as u8).map_err(|e| { + if let nb::Error::Other(_) = e { + unreachable!() + } + nb::Error::WouldBlock + }) + } +} + +impl embedded_io::Read for Rx { + fn read(&mut self, buf: &mut [u8]) -> Result { + if buf.is_empty() { + return Ok(0); + } + let mut read = 0; + loop { + if self.regs.read_rx_status().data_available() { + break; + } + } + for byte in buf.iter_mut() { + match >::read(self) { + Ok(w) => { + *byte = w; + read += 1; + } + Err(nb::Error::WouldBlock) => break, + } + } + + Ok(read) + } +} + +#[inline(always)] +pub fn enable_tx(uart: &mut MmioUart<'static>) { + uart.modify_enable(|mut value| { + value.set_tx(true); + value + }); +} + +#[inline(always)] +pub fn disable_tx(uart: &mut MmioUart<'static>) { + uart.modify_enable(|mut value| { + value.set_tx(false); + value + }); +} + +#[inline(always)] +pub fn enable_tx_interrupts(uart: &mut MmioUart<'static>) { + uart.modify_irq_enabled(|mut value| { + value.set_tx(true); + value.set_tx_empty(true); + value.set_tx_status(true); + value + }); +} + +#[inline(always)] +pub fn disable_tx_interrupts(uart: &mut MmioUart<'static>) { + uart.modify_irq_enabled(|mut value| { + value.set_tx(false); + value.set_tx_empty(false); + value.set_tx_status(false); + value + }); +} + +/// Serial transmitter +/// +/// Can be created by using the [Uart::split] API. +pub struct Tx { + id: Bank, + regs: regs::MmioUart<'static>, +} + +impl Tx { + /// Retrieve a TX pin without expecting an explicit UART structure + /// + /// # Safety + /// + /// Circumvents the HAL safety guarantees. + #[inline(always)] + pub unsafe fn steal(id: Bank) -> Self { + Self::new(id) + } + + #[inline(always)] + fn new(id: Bank) -> Self { + Self { + id, + regs: regs::Uart::new_mmio(id), + } + } + + #[inline] + pub fn perid(&self) -> u32 { + self.regs.read_perid() + } + + #[inline] + pub fn clear_fifo(&mut self) { + self.regs + .write_fifo_clr(FifoClear::builder().with_tx(true).with_rx(false).build()); + } + + #[inline] + pub fn enable(&mut self) { + self.regs.modify_enable(|mut value| { + value.set_tx(true); + value + }); + } + + #[inline] + pub fn disable(&mut self) { + self.regs.modify_enable(|mut value| { + value.set_tx(false); + value + }); + } + + /// Enables the IRQ_TX, IRQ_TX_STATUS and IRQ_TX_EMPTY interrupts. + /// + /// - The IRQ_TX interrupt is generated when the TX FIFO is at least half empty. + /// - The IRQ_TX_STATUS interrupt is generated when write data is lost due to a FIFO overflow + /// - The IRQ_TX_EMPTY interrupt is generated when the TX FIFO is empty and the TXBUSY signal + /// is 0 + #[inline] + pub fn enable_interrupts(&mut self, #[cfg(feature = "vor4x")] enable_in_nvic: bool) { + #[cfg(feature = "vor4x")] + if enable_in_nvic { + unsafe { enable_nvic_interrupt(self.id.interrupt_id_tx()) }; + } + // Safety: We own the UART structure + enable_tx_interrupts(&mut self.regs); + } + + /// Disables the IRQ_TX, IRQ_TX_STATUS and IRQ_TX_EMPTY interrupts. + /// + /// [Self::enable_interrupts] documents the interrupts. + #[inline] + pub fn disable_interrupts(&mut self) { + // Safety: We own the UART structure + disable_tx_interrupts(&mut self.regs); + } + + /// Low level function to write a word to the UART FIFO. + /// + /// Uses the [nb] API to allow usage in blocking and non-blocking contexts. + /// + /// Please note that you might have to mask the returned value with 0xff to retrieve the actual + /// value if you use the manual parity mode. See chapter 11.4.1 for more information. + #[inline(always)] + pub fn write_fifo(&mut self, data: u32) -> nb::Result<(), Infallible> { + if !self.regs.read_tx_status().ready() { + return Err(nb::Error::WouldBlock); + } + self.write_fifo_unchecked(data); + Ok(()) + } + + /// Low level function to write a word to the UART FIFO. + /// + /// This does not necesarily mean that the FIFO can process another word because it might be + /// full. + /// Use the [Self::write_fifo] function to write a word to the FIFO reliably using the [nb] + /// API. + #[inline(always)] + pub fn write_fifo_unchecked(&mut self, data: u32) { + self.regs.write_data(Data::new_with_raw_value(data)); + } + + pub fn into_async(self) -> TxAsync { + TxAsync::new(self) + } +} + +impl embedded_io::ErrorType for Tx { + type Error = Infallible; +} + +impl embedded_hal_nb::serial::ErrorType for Tx { + type Error = Infallible; +} + +impl embedded_hal_nb::serial::Write for Tx { + fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { + self.write_fifo(word as u32) + } + + fn flush(&mut self) -> nb::Result<(), Self::Error> { + // SAFETY: Only TX related registers are used. + if self.regs.read_tx_status().write_busy() { + return Err(nb::Error::WouldBlock); + } + Ok(()) + } +} + +impl embedded_io::Write for Tx { + fn write(&mut self, buf: &[u8]) -> Result { + if buf.is_empty() { + return Ok(0); + } + loop { + if self.regs.read_tx_status().ready() { + break; + } + } + let mut written = 0; + for byte in buf.iter() { + match >::write(self, *byte) { + Ok(_) => written += 1, + Err(nb::Error::WouldBlock) => return Ok(written), + } + } + + Ok(written) + } + + fn flush(&mut self) -> Result<(), Self::Error> { + nb::block!(>::flush(self)) + } +} + +/// Serial receiver, using interrupts to offload reading to the hardware. +/// +/// You can use [Rx::into_rx_with_irq] to convert a normal [Rx] structure into this structure. +/// This structure provides two distinct ways to read the UART RX using interrupts. It should +/// be noted that the interrupt service routine (ISR) still has to be provided by the user. However, +/// this structure provides API calls which can be used inside the ISRs to simplify the reading +/// of the UART. +/// +/// 1. The first way simply empties the FIFO on an interrupt into a user provided buffer. You +/// can simply use [Self::start] to prepare the peripheral and then call the +/// [Self::on_interrupt] in the interrupt service routine. +/// 2. The second way reads packets bounded by a maximum size or a baudtick based timeout. You +/// can use [Self::read_fixed_len_or_timeout_based_using_irq] to prepare the peripheral and +/// then call the [Self::on_interrupt_max_size_or_timeout_based] in the interrupt service +/// routine. You have to call [Self::read_fixed_len_or_timeout_based_using_irq] in the ISR to +/// start reading the next packet. +pub struct RxWithInterrupt(Rx); + +impl RxWithInterrupt { + pub fn new(rx: Rx) -> Self { + Self(rx) + } + + /// This function should be called once at initialization time if the regular + /// [Self::on_interrupt] is used to read the UART receiver to enable and start the receiver. + pub fn start(&mut self) { + #[cfg(feature = "vor4x")] + self.enable_interrupts(true, true); + #[cfg(feature = "vor1x")] + self.enable_interrupts(true); + self.0.enable(); + } + + #[inline(always)] + pub fn rx(&self) -> &Rx { + &self.0 + } + + /// This function is used together with the [Self::on_interrupt_max_size_or_timeout_based] + /// function to read packets with a maximum size or variable sized packets by using the + /// receive timeout of the hardware. + /// + /// This function should be called once at initialization to initiate the context state + /// and to [Self::start] the receiver. After that, it should be called after each + /// completed [Self::on_interrupt_max_size_or_timeout_based] call to restart the reception + /// of a packet. + pub fn read_fixed_len_or_timeout_based_using_irq( + &mut self, + context: &mut InterruptContextTimeoutOrMaxSize, + ) -> Result<(), TransferPendingError> { + if context.mode != InterruptReceptionMode::Idle { + return Err(TransferPendingError); + } + context.mode = InterruptReceptionMode::Pending; + context.rx_idx = 0; + self.start(); + Ok(()) + } + + #[inline] + fn enable_interrupts(&mut self, #[cfg(feature = "vor4x")] enable_in_nvic: bool, timeout: bool) { + #[cfg(feature = "vor4x")] + self.0.enable_interrupts(enable_in_nvic, timeout); + #[cfg(feature = "vor1x")] + self.0.enable_interrupts(timeout); + } + + #[inline] + fn disable_interrupts(&mut self) { + self.0.disable_interrupts(); + } + + pub fn cancel_transfer(&mut self) { + self.disable_interrupts(); + self.0.clear_fifo(); + } + + /// This function should be called in the user provided UART interrupt handler. + /// + /// It simply empties any bytes in the FIFO into the user provided buffer and returns the + /// result of the operation. + /// + /// This function will not disable the RX interrupts, so you don't need to call any other + /// API after calling this function to continue emptying the FIFO. RX errors are handled + /// as partial errors and are returned as part of the [InterruptResult]. + pub fn on_interrupt(&mut self, buf: &mut [u8; 16]) -> InterruptResult { + let mut result = InterruptResult::default(); + + let irq_status = self.0.regs.read_irq_status(); + let irq_enabled = self.0.regs.read_irq_enabled(); + let rx_enabled = irq_enabled.rx(); + + // Half-Full interrupt. We have a guaranteed amount of data we can read. + if irq_status.rx() { + let available_bytes = self.0.regs.read_rx_fifo_trigger().level().as_usize(); + + // If this interrupt bit is set, the trigger level is available at the very least. + // Read everything as fast as possible + for _ in 0..available_bytes { + buf[result.bytes_read] = (self.0.read_fifo_unchecked() & 0xff) as u8; + result.bytes_read += 1; + } + } + + // Timeout, empty the FIFO completely. + if irq_status.rx_timeout() { + // While there is data in the FIFO, write it into the reception buffer + while let Ok(byte) = self.0.read_fifo() { + buf[result.bytes_read] = byte as u8; + result.bytes_read += 1; + } + } + + // RX transfer not complete, check for RX errors + if rx_enabled { + self.check_for_errors(&mut result.errors); + } + + // Clear the interrupt status bits + self.0.regs.write_irq_clr( + InterruptClear::builder() + .with_rx_overrun(true) + .with_tx_overrun(false) + .build(), + ); + result + } + + /// This function should be called in the user provided UART interrupt handler. + /// + /// This function is used to read packets which either have a maximum size or variable sized + /// packet which are bounded by sufficient delays between them, triggering a hardware timeout. + /// + /// If either the maximum number of packets have been read or a timeout occured, the transfer + /// will be deemed completed. The state information of the transfer is tracked in the + /// [InterruptContextTimeoutOrMaxSize] structure. + /// + /// If passed buffer is equal to or larger than the specified maximum length, an + /// [BufferTooShortError] will be returned. Other RX errors are treated as partial errors + /// and returned inside the [InterruptResultMaxSizeOrTimeout] structure. + pub fn on_interrupt_max_size_or_timeout_based( + &mut self, + context: &mut InterruptContextTimeoutOrMaxSize, + buf: &mut [u8], + ) -> Result { + if buf.len() < context.max_len { + return Err(BufferTooShortError { + found: buf.len(), + expected: context.max_len, + }); + } + let mut result = InterruptResultMaxSizeOrTimeout::default(); + + let irq_status = self.0.regs.read_irq_status(); + let rx_enabled = self.0.regs.read_enable().rx(); + + // Half-Full interrupt. We have a guaranteed amount of data we can read. + if irq_status.rx() { + // Determine the number of bytes to read, ensuring we leave 1 byte in the FIFO. + // We use this trick/hack because the timeout feature of the peripheral relies on data + // being in the RX FIFO. If data continues arriving, another half-full IRQ will fire. + // If not, the last byte(s) is/are emptied by the timeout interrupt. + let available_bytes = self.0.regs.read_rx_fifo_trigger().level().as_usize(); + + let bytes_to_read = core::cmp::min( + available_bytes.saturating_sub(1), + context.max_len - context.rx_idx, + ); + + // If this interrupt bit is set, the trigger level is available at the very least. + // Read everything as fast as possible + for _ in 0..bytes_to_read { + buf[context.rx_idx] = (self.0.read_fifo_unchecked() & 0xff) as u8; + context.rx_idx += 1; + } + + // On high-baudrates, data might be available immediately, and we possible have to + // read continuosly? Then again, the CPU should always be faster than that. I'd rather + // rely on the hardware firing another IRQ. I have not tried baudrates higher than + // 115200 so far. + } + // Timeout, empty the FIFO completely. + if irq_status.rx_timeout() { + // While there is data in the FIFO, write it into the reception buffer + loop { + if context.rx_idx == context.max_len { + break; + } + // While there is data in the FIFO, write it into the reception buffer + match self.0.read() { + Ok(byte) => { + buf[context.rx_idx] = byte; + context.rx_idx += 1; + } + Err(_) => break, + } + } + self.irq_completion_handler_max_size_timeout(&mut result, context); + return Ok(result); + } + + // RX transfer not complete, check for RX errors + if (context.rx_idx < context.max_len) && rx_enabled { + self.check_for_errors(&mut result.errors); + } + + // Clear the interrupt status bits + self.0.regs.write_irq_clr( + InterruptClear::builder() + .with_rx_overrun(true) + .with_tx_overrun(false) + .build(), + ); + Ok(result) + } + + fn check_for_errors(&self, errors: &mut Option) { + let rx_status = self.0.regs.read_rx_status(); + + if rx_status.overrun_error() || rx_status.framing_error() || rx_status.parity_error() { + let err = errors.get_or_insert(UartErrors::default()); + + if rx_status.overrun_error() { + err.overflow = true; + } + if rx_status.framing_error() { + err.framing = true; + } + if rx_status.parity_error() { + err.parity = true; + } + } + } + + fn irq_completion_handler_max_size_timeout( + &mut self, + res: &mut InterruptResultMaxSizeOrTimeout, + context: &mut InterruptContextTimeoutOrMaxSize, + ) { + self.disable_interrupts(); + self.0.disable(); + res.bytes_read = context.rx_idx; + res.complete = true; + context.mode = InterruptReceptionMode::Idle; + context.rx_idx = 0; + } + + /// # Safety + /// + /// This API allows creating multiple UART instances when releasing the TX structure as well. + /// The user must ensure that these instances are not used to create multiple overlapping + /// UART drivers. + pub unsafe fn release(mut self) -> Rx { + self.disable_interrupts(); + self.0 + } +} diff --git a/vorago-shared-hal/src/uart/pins_vor1x.rs b/vorago-shared-hal/src/uart/pins_vor1x.rs new file mode 100644 index 0000000..bd165b6 --- /dev/null +++ b/vorago-shared-hal/src/uart/pins_vor1x.rs @@ -0,0 +1,112 @@ +// UART A pins + +use crate::{ + FunctionSelect, + pins::{ + Pa2, Pa3, Pa8, Pa9, Pa16, Pa17, Pa18, Pa19, Pa26, Pa27, Pa30, Pa31, Pb6, Pb7, Pb8, Pb9, + Pb18, Pb19, Pb20, Pb21, Pb22, Pb23, Pin, + }, +}; + +use super::{Bank, RxPin, TxPin}; + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +// UART B pins + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} diff --git a/vorago-shared-hal/src/uart/pins_vor4x.rs b/vorago-shared-hal/src/uart/pins_vor4x.rs new file mode 100644 index 0000000..a72e6c9 --- /dev/null +++ b/vorago-shared-hal/src/uart/pins_vor4x.rs @@ -0,0 +1,98 @@ +#[cfg(not(feature = "va41628"))] +use crate::pins::{Pc15, Pf8}; +use crate::{ + FunctionSelect, + gpio::Pin, + pins::{Pa2, Pa3, Pb14, Pb15, Pc4, Pc5, Pc14, Pd11, Pd12, Pe2, Pe3, Pf9, Pf12, Pf13, Pg0, Pg1}, +}; + +use super::{Bank, RxPin, TxPin}; + +// UART 0 pins + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart0; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +// UART 1 pins + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; +} + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} + +// UART 2 pins + +impl TxPin for Pin { + const BANK: Bank = Bank::Uart2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} +#[cfg(not(feature = "va41628"))] +impl RxPin for Pin { + const BANK: Bank = Bank::Uart2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; +} + +#[cfg(not(feature = "va41628"))] +impl TxPin for Pin { + const BANK: Bank = Bank::Uart2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} +impl RxPin for Pin { + const BANK: Bank = Bank::Uart2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; +} diff --git a/vorago-shared-hal/src/uart/regs.rs b/vorago-shared-hal/src/uart/regs.rs new file mode 100644 index 0000000..06fc903 --- /dev/null +++ b/vorago-shared-hal/src/uart/regs.rs @@ -0,0 +1,313 @@ +use core::marker::PhantomData; + +use arbitrary_int::{u5, u6, u18}; + +cfg_if::cfg_if! { + if #[cfg(feature = "vor1x")] { + /// UART A base address + pub const BASE_ADDR_0: usize = 0x4004_0000; + /// UART B base address + pub const BASE_ADDR_1: usize = 0x4004_1000; + } else if #[cfg(feature = "vor4x")] { + /// UART 0 base address + pub const BASE_ADDR_0: usize = 0x4002_4000; + /// UART 1 base address + pub const BASE_ADDR_1: usize = 0x4002_5000; + /// UART 2 base address + pub const BASE_ADDR_2: usize = 0x4001_7000; + } +} + +#[derive(Debug, PartialEq, Eq, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Bank { + Uart0 = 0, + Uart1 = 1, + #[cfg(feature = "vor4x")] + Uart2 = 2, +} + +impl Bank { + /// Unsafely steal the GPIO peripheral block for the given port. + /// + /// # Safety + /// + /// Circumvents ownership and safety guarantees by the HAL. + pub unsafe fn steal_regs(&self) -> MmioUart<'static> { + Uart::new_mmio(*self) + } + + #[cfg(feature = "vor4x")] + pub const fn interrupt_id_tx(&self) -> va416xx::Interrupt { + match self { + Bank::Uart0 => va416xx::Interrupt::UART0_TX, + Bank::Uart1 => va416xx::Interrupt::UART1_TX, + Bank::Uart2 => va416xx::Interrupt::UART2_TX, + } + } + + #[cfg(feature = "vor4x")] + pub const fn interrupt_id_rx(&self) -> va416xx::Interrupt { + match self { + Bank::Uart0 => va416xx::Interrupt::UART0_RX, + Bank::Uart1 => va416xx::Interrupt::UART1_RX, + Bank::Uart2 => va416xx::Interrupt::UART2_RX, + } + } +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct Data { + #[bit(15, rw)] + dparity: bool, + #[bits(0..=7, rw)] + value: u8, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))] +pub struct Enable { + #[bit(1, rw)] + tx: bool, + #[bit(0, rw)] + rx: bool, +} + +#[bitbybit::bitenum(u1, exhaustive = true)] +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Stopbits { + One = 0, + Two = 1, +} + +#[bitbybit::bitenum(u2, exhaustive = true)] +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum WordSize { + Five = 0b00, + Six = 0b01, + Seven = 0b10, + Eight = 0b11, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))] +pub struct Control { + #[bit(11, rw)] + baud8: bool, + #[bit(10, rw)] + auto_rts: bool, + #[bit(9, rw)] + def_rts: bool, + #[bit(8, rw)] + auto_cts: bool, + #[bit(7, rw)] + loopback_block: bool, + #[bit(6, rw)] + loopback: bool, + #[bits(4..=5, rw)] + wordsize: WordSize, + #[bit(3, rw)] + stopbits: Stopbits, + #[bit(2, rw)] + parity_manual: bool, + #[bit(1, rw)] + parity_even: bool, + #[bit(0, rw)] + parity_enable: bool, +} + +#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))] +pub struct ClockScale { + #[bits(6..=23, rw)] + int: u18, + #[bits(0..=5, rw)] + frac: u6, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct RxStatus { + #[bit(15, r)] + rx_rtsn: bool, + #[bit(9, r)] + rx_addr9: bool, + #[bit(8, r)] + busy_break: bool, + #[bit(7, r)] + break_error: bool, + #[bit(6, r)] + parity_error: bool, + #[bit(5, r)] + framing_error: bool, + #[bit(4, r)] + overrun_error: bool, + #[bit(3, r)] + timeout: bool, + #[bit(2, r)] + busy: bool, + #[bit(1, r)] + not_full: bool, + #[bit(0, r)] + data_available: bool, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct TxStatus { + #[bit(15, r)] + tx_ctsn: bool, + #[bit(3, r)] + wr_lost: bool, + #[bit(2, r)] + tx_busy: bool, + #[bit(1, r)] + write_busy: bool, + /// There is space in the FIFO to write data. + #[bit(0, r)] + ready: bool, +} + +#[bitbybit::bitfield(u32, default = 0x0)] +#[derive(Debug)] +pub struct FifoClear { + #[bit(1, w)] + tx: bool, + #[bit(0, w)] + rx: bool, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct InterruptControl { + /// Generate an interrrupt when the RX FIFO is at least half-full (FIFO count >= trigger level) + #[bit(0, rw)] + rx: bool, + /// Interrupts for status conditions (overrun, framing, parity and break) + #[bit(1, rw)] + rx_status: bool, + /// Interrupt on timeout conditions. + #[bit(2, rw)] + rx_timeout: bool, + + /// Generates an interrupt when the TX FIFO is at least half-empty (FIFO count < trigger level) + #[bit(4, rw)] + tx: bool, + /// Generates an interrupt on TX FIFO overflow. + #[bit(5, rw)] + tx_status: bool, + /// Generates an interrupt when the transmit FIFO is empty and TXBUSY is 0. + #[bit(6, rw)] + tx_empty: bool, + #[bit(7, rw)] + tx_cts: bool, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct InterruptStatus { + /// Generate an interrrupt when the RX FIFO is at least half-full (FIFO count >= trigger level) + #[bit(0, r)] + rx: bool, + /// Interrupts for status conditions (overrun, framing, parity and break) + #[bit(1, r)] + rx_status: bool, + /// Interrupt on timeout conditions. + #[bit(2, r)] + rx_timeout: bool, + + /// Generates an interrupt when the TX FIFO is at least half-empty (FIFO count < trigger level) + #[bit(4, r)] + tx: bool, + /// Generates an interrupt on TX FIFO overflow. + #[bit(5, r)] + tx_status: bool, + /// Generates an interrupt when the transmit FIFO is empty and TXBUSY is 0. + #[bit(6, r)] + tx_empty: bool, + #[bit(7, r)] + tx_cts: bool, +} + +/// As specified in the VA416x0 Programmers Guide, only the RX overflow bit can be cleared. +#[bitbybit::bitfield(u32, default = 0x0)] +#[derive(Debug)] +pub struct InterruptClear { + #[bit(1, w)] + rx_overrun: bool, + /// Not sure if this does anything, the programmer guides are not consistent on this.. + #[bit(5, w)] + tx_overrun: bool, +} + +#[bitbybit::bitfield(u32)] +#[derive(Debug)] +pub struct FifoTrigger { + #[bits(0..=4, rw)] + level: u5, +} + +#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))] +pub struct State { + #[bits(0..=7, r)] + rx_state: u8, + /// Data count. + #[bits(8..=12, r)] + rx_fifo: u5, + #[bits(16..=23, r)] + tx_state: u8, + /// Data count. + #[bits(24..=28, r)] + tx_fifo: u5, +} + +#[derive(derive_mmio::Mmio)] +#[mmio(no_ctors)] +#[repr(C)] +pub struct Uart { + data: Data, + enable: Enable, + ctrl: Control, + clkscale: ClockScale, + #[mmio(PureRead)] + rx_status: RxStatus, + #[mmio(PureRead)] + tx_status: TxStatus, + #[mmio(Write)] + fifo_clr: FifoClear, + #[mmio(Write)] + txbreak: u32, + addr9: u32, + addr9mask: u32, + irq_enabled: InterruptControl, + #[mmio(PureRead)] + irq_raw: InterruptStatus, + #[mmio(PureRead)] + irq_status: InterruptStatus, + #[mmio(Write)] + irq_clr: InterruptClear, + rx_fifo_trigger: FifoTrigger, + tx_fifo_trigger: FifoTrigger, + rx_fifo_rts_trigger: u32, + #[mmio(PureRead)] + state: State, + _reserved: [u32; 0x3ED], + /// Vorago 1x value: 0x0112_07E1. Vorago 4x value: 0x0212_07E9 + #[mmio(PureRead)] + perid: u32, +} + +static_assertions::const_assert_eq!(core::mem::size_of::(), 0x1000); + +impl Uart { + fn new_mmio_at(base: usize) -> MmioUart<'static> { + MmioUart { + ptr: base as *mut _, + phantom: PhantomData, + } + } + + pub fn new_mmio(bank: Bank) -> MmioUart<'static> { + match bank { + Bank::Uart0 => Self::new_mmio_at(BASE_ADDR_0), + Bank::Uart1 => Self::new_mmio_at(BASE_ADDR_1), + #[cfg(feature = "vor4x")] + Bank::Uart2 => Self::new_mmio_at(BASE_ADDR_2), + } + } +} diff --git a/vorago-shared-hal/src/uart/rx_asynch.rs b/vorago-shared-hal/src/uart/rx_asynch.rs new file mode 100644 index 0000000..b5756ff --- /dev/null +++ b/vorago-shared-hal/src/uart/rx_asynch.rs @@ -0,0 +1,443 @@ +//! # Async UART reception functionality. +//! +//! This module provides the [RxAsync] and [RxAsyncOverwriting] struct which both implement the +//! [embedded_io_async::Read] trait. +//! This trait allows for asynchronous reception of data streams. Please note that this module does +//! not specify/declare the interrupt handlers which must be provided for async support to work. +//! However, it provides two interrupt handlers: +//! +//! - [on_interrupt_rx] +//! - [on_interrupt_rx_overwriting] +//! +//! The first two are used for the [RxAsync] struct, while the latter two are used with the +//! [RxAsyncOverwriting] struct. The later two will overwrite old values in the used ring buffer. +//! +//! Error handling is performed in the user interrupt handler by checking the [AsyncUartErrors] +//! structure returned by the interrupt handlers. +use core::{cell::RefCell, convert::Infallible, future::Future, sync::atomic::Ordering}; + +use arbitrary_int::prelude::*; +use critical_section::Mutex; +use embassy_sync::waitqueue::AtomicWaker; +use embedded_io::ErrorType; +use portable_atomic::AtomicBool; + +use super::{ + Bank, Rx, UartErrors, + regs::{InterruptClear, MmioUart}, +}; + +static UART_RX_WAKERS: [AtomicWaker; 2] = [const { AtomicWaker::new() }; 2]; +static RX_READ_ACTIVE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2]; +static RX_HAS_DATA: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2]; + +struct RxFuture { + id: Bank, +} + +impl RxFuture { + pub fn new(rx: &mut Rx) -> Self { + RX_READ_ACTIVE[rx.id as usize].store(true, Ordering::Relaxed); + Self { id: rx.id } + } +} + +impl Future for RxFuture { + type Output = Result<(), Infallible>; + + fn poll( + self: core::pin::Pin<&mut Self>, + cx: &mut core::task::Context<'_>, + ) -> core::task::Poll { + UART_RX_WAKERS[self.id as usize].register(cx.waker()); + if RX_HAS_DATA[self.id as usize].load(Ordering::Relaxed) { + return core::task::Poll::Ready(Ok(())); + } + core::task::Poll::Pending + } +} + +#[derive(Debug, Clone, Copy)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct AsyncUartErrors { + /// Queue has overflowed, data might have been lost. + pub queue_overflow: bool, + /// UART errors. + pub uart_errors: UartErrors, +} + +fn on_interrupt_handle_rx_errors(uart: &mut MmioUart<'static>) -> Option { + let rx_status = uart.read_rx_status(); + if rx_status.overrun_error() || rx_status.framing_error() || rx_status.parity_error() { + let mut errors_val = UartErrors::default(); + + if rx_status.overrun_error() { + errors_val.overflow = true; + } + if rx_status.framing_error() { + errors_val.framing = true; + } + if rx_status.parity_error() { + errors_val.parity = true; + } + return Some(errors_val); + } + None +} + +fn on_interrupt_rx_common_post_processing( + id: Bank, + rx_enabled: bool, + read_some_data: bool, +) -> Option { + let idx = id as usize; + if read_some_data { + RX_HAS_DATA[idx].store(true, Ordering::Relaxed); + if RX_READ_ACTIVE[idx].load(Ordering::Relaxed) { + UART_RX_WAKERS[idx].wake(); + } + } + + let mut errors = None; + let mut uart_regs = unsafe { id.steal_regs() }; + // Check for RX errors + if rx_enabled { + errors = on_interrupt_handle_rx_errors(&mut uart_regs); + } + + // Clear the interrupt status bits + uart_regs.write_irq_clr( + InterruptClear::builder() + .with_rx_overrun(true) + .with_tx_overrun(false) + .build(), + ); + errors +} + +/// Interrupt handler with overwriting behaviour when the ring buffer is full. +/// +/// Should be called in the user interrupt handler to enable +/// asynchronous reception. This variant will overwrite old data in the ring buffer in case +/// the ring buffer is full. +pub fn on_interrupt_rx_overwriting( + bank: Bank, + prod: &mut heapless::spsc::Producer, + shared_consumer: &Mutex>>>, +) -> Result<(), AsyncUartErrors> { + on_interrupt_rx_async_heapless_queue_overwriting(bank, prod, shared_consumer) +} + +pub fn on_interrupt_rx_async_heapless_queue_overwriting( + bank: Bank, + prod: &mut heapless::spsc::Producer, + shared_consumer: &Mutex>>>, +) -> Result<(), AsyncUartErrors> { + let uart_regs = unsafe { bank.steal_regs() }; + let irq_status = uart_regs.read_irq_status(); + let irq_enabled = uart_regs.read_irq_enabled(); + let rx_enabled = irq_enabled.rx(); + let mut read_some_data = false; + let mut queue_overflow = false; + + // Half-Full interrupt. We have a guaranteed amount of data we can read. + if irq_status.rx() { + let available_bytes = uart_regs.read_rx_fifo_trigger().level().as_usize(); + + // If this interrupt bit is set, the trigger level is available at the very least. + // Read everything as fast as possible + for _ in 0..available_bytes { + let byte = uart_regs.read_data().value(); + if !prod.ready() { + queue_overflow = true; + critical_section::with(|cs| { + let mut cons_ref = shared_consumer.borrow(cs).borrow_mut(); + cons_ref.as_mut().unwrap().dequeue(); + }); + } + prod.enqueue(byte).ok(); + } + read_some_data = true; + } + + // Timeout, empty the FIFO completely. + if irq_status.rx_timeout() { + while uart_regs.read_rx_status().data_available() { + // While there is data in the FIFO, write it into the reception buffer + let byte = uart_regs.read_data().value(); + if !prod.ready() { + queue_overflow = true; + critical_section::with(|cs| { + let mut cons_ref = shared_consumer.borrow(cs).borrow_mut(); + cons_ref.as_mut().unwrap().dequeue(); + }); + } + prod.enqueue(byte).ok(); + } + read_some_data = true; + } + + let uart_errors = on_interrupt_rx_common_post_processing(bank, rx_enabled, read_some_data); + if uart_errors.is_some() || queue_overflow { + return Err(AsyncUartErrors { + queue_overflow, + uart_errors: uart_errors.unwrap_or_default(), + }); + } + Ok(()) +} + +/// Interrupt handler for asynchronous RX operations. +/// +/// Should be called in the user interrupt handler to enable asynchronous reception. +pub fn on_interrupt_rx( + bank: Bank, + prod: &mut heapless::spsc::Producer<'_, u8>, +) -> Result<(), AsyncUartErrors> { + on_interrupt_rx_async_heapless_queue(bank, prod) +} + +pub fn on_interrupt_rx_async_heapless_queue( + bank: Bank, + prod: &mut heapless::spsc::Producer<'_, u8>, +) -> Result<(), AsyncUartErrors> { + let uart_regs = unsafe { bank.steal_regs() }; + let irq_status = uart_regs.read_irq_status(); + let irq_enabled = uart_regs.read_irq_enabled(); + let rx_enabled = irq_enabled.rx(); + let mut read_some_data = false; + let mut queue_overflow = false; + + // Half-Full interrupt. We have a guaranteed amount of data we can read. + if irq_status.rx() { + let available_bytes = uart_regs.read_rx_fifo_trigger().level().as_usize(); + + // If this interrupt bit is set, the trigger level is available at the very least. + // Read everything as fast as possible + for _ in 0..available_bytes { + let byte = uart_regs.read_data().value(); + if !prod.ready() { + queue_overflow = true; + } + prod.enqueue(byte).ok(); + } + read_some_data = true; + } + + // Timeout, empty the FIFO completely. + if irq_status.rx_timeout() { + while uart_regs.read_rx_status().data_available() { + // While there is data in the FIFO, write it into the reception buffer + let byte = uart_regs.read_data().value(); + if !prod.ready() { + queue_overflow = true; + } + prod.enqueue(byte).ok(); + } + read_some_data = true; + } + + let uart_errors = on_interrupt_rx_common_post_processing(bank, rx_enabled, read_some_data); + if uart_errors.is_some() || queue_overflow { + return Err(AsyncUartErrors { + queue_overflow, + uart_errors: uart_errors.unwrap_or_default(), + }); + } + Ok(()) +} + +struct ActiveReadGuard(usize); + +impl Drop for ActiveReadGuard { + fn drop(&mut self) { + RX_READ_ACTIVE[self.0].store(false, Ordering::Relaxed); + } +} + +struct RxAsyncInner { + rx: Rx, + pub queue: heapless::spsc::Consumer<'static, u8>, +} + +/// Core data structure to allow asynchronous UART reception. +/// +/// If the ring buffer becomes full, data will be lost. +pub struct RxAsync(Option); + +impl ErrorType for RxAsync { + /// Error reporting is done using the result of the interrupt functions. + type Error = Infallible; +} + +fn stop_async_rx(rx: &mut Rx) { + rx.disable_interrupts(); + rx.disable(); + rx.clear_fifo(); +} + +impl RxAsync { + /// Create a new asynchronous receiver. + /// + /// The passed [heapless::spsc::Consumer] will be used to asynchronously receive data which + /// is filled by the interrupt handler [on_interrupt_rx]. + pub fn new(mut rx: Rx, queue: heapless::spsc::Consumer<'static, u8>) -> Self { + rx.disable_interrupts(); + rx.disable(); + rx.clear_fifo(); + // Enable those together. + critical_section::with(|_| { + #[cfg(feature = "vor1x")] + rx.enable_interrupts(true); + #[cfg(feature = "vor4x")] + rx.enable_interrupts(true, true); + rx.enable(); + }); + Self(Some(RxAsyncInner { rx, queue })) + } + + pub fn stop(&mut self) { + stop_async_rx(&mut self.0.as_mut().unwrap().rx); + } + + pub fn release(mut self) -> (Rx, heapless::spsc::Consumer<'static, u8>) { + self.stop(); + let inner = self.0.take().unwrap(); + (inner.rx, inner.queue) + } +} + +impl Drop for RxAsync { + fn drop(&mut self) { + self.stop(); + } +} + +impl embedded_io_async::Read for RxAsync { + async fn read(&mut self, buf: &mut [u8]) -> Result { + let inner = self.0.as_ref().unwrap(); + // Need to wait for the IRQ to read data and set this flag. If the queue is not + // empty, we can read data immediately. + if inner.queue.is_empty() { + RX_HAS_DATA[inner.rx.id as usize].store(false, Ordering::Relaxed); + } + let _guard = ActiveReadGuard(inner.rx.id as usize); + let mut handle_data_in_queue = |consumer: &mut heapless::spsc::Consumer<'static, u8>| { + let data_to_read = consumer.len().min(buf.len()); + for byte in buf.iter_mut().take(data_to_read) { + // We own the consumer and we checked that the amount of data is guaranteed to be available. + *byte = unsafe { consumer.dequeue_unchecked() }; + } + data_to_read + }; + let mut_ref = self.0.as_mut().unwrap(); + let fut = RxFuture::new(&mut mut_ref.rx); + // Data is available, so read that data immediately. + let read_data = handle_data_in_queue(&mut mut_ref.queue); + if read_data > 0 { + return Ok(read_data); + } + // Await data. + let _ = fut.await; + Ok(handle_data_in_queue(&mut mut_ref.queue)) + } +} + +struct RxAsyncOverwritingInner { + rx: Rx, + pub shared_consumer: &'static Mutex>>>, +} + +/// Core data structure to allow asynchronous UART reception. +/// +/// If the ring buffer becomes full, the oldest data will be overwritten when using the +/// [on_interrupt_rx_overwriting] interrupt handlers. +pub struct RxAsyncOverwriting(Option); + +impl ErrorType for RxAsyncOverwriting { + /// Error reporting is done using the result of the interrupt functions. + type Error = Infallible; +} + +impl RxAsyncOverwriting { + /// Create a new asynchronous receiver. + /// + /// The passed shared [heapless::spsc::Consumer] will be used to asynchronously receive data + /// which is filled by the interrupt handler. The shared property allows using it in the + /// interrupt handler to overwrite old data. + pub fn new( + mut rx: Rx, + shared_consumer: &'static Mutex>>>, + ) -> Self { + rx.disable_interrupts(); + rx.disable(); + rx.clear_fifo(); + // Enable those together. + critical_section::with(|_| { + #[cfg(feature = "vor4x")] + rx.enable_interrupts(true, true); + #[cfg(feature = "vor1x")] + rx.enable_interrupts(true); + rx.enable(); + }); + Self(Some(RxAsyncOverwritingInner { + rx, + shared_consumer, + })) + } + + pub fn stop(&mut self) { + stop_async_rx(&mut self.0.as_mut().unwrap().rx); + } + + pub fn release(mut self) -> Rx { + self.stop(); + let inner = self.0.take().unwrap(); + inner.rx + } +} + +impl Drop for RxAsyncOverwriting { + fn drop(&mut self) { + self.stop(); + } +} + +impl embedded_io_async::Read for RxAsyncOverwriting { + async fn read(&mut self, buf: &mut [u8]) -> Result { + let inner = self.0.as_ref().unwrap(); + let id = inner.rx.id as usize; + // Need to wait for the IRQ to read data and set this flag. If the queue is not + // empty, we can read data immediately. + + critical_section::with(|cs| { + let queue = inner.shared_consumer.borrow(cs); + if queue.borrow().as_ref().unwrap().is_empty() { + RX_HAS_DATA[id].store(false, Ordering::Relaxed); + } + }); + let _guard = ActiveReadGuard(id); + let mut handle_data_in_queue = |inner: &mut RxAsyncOverwritingInner| { + critical_section::with(|cs| { + let mut consumer_ref = inner.shared_consumer.borrow(cs).borrow_mut(); + let consumer = consumer_ref.as_mut().unwrap(); + let data_to_read = consumer.len().min(buf.len()); + for byte in buf.iter_mut().take(data_to_read) { + // We own the consumer and we checked that the amount of data is guaranteed to be available. + *byte = unsafe { consumer.dequeue_unchecked() }; + } + data_to_read + }) + }; + let fut = RxFuture::new(&mut self.0.as_mut().unwrap().rx); + // Data is available, so read that data immediately. + let read_data = handle_data_in_queue(self.0.as_mut().unwrap()); + if read_data > 0 { + return Ok(read_data); + } + // Await data. + let _ = fut.await; + let read_data = handle_data_in_queue(self.0.as_mut().unwrap()); + Ok(read_data) + } +} diff --git a/vorago-shared-hal/src/uart/tx_asynch.rs b/vorago-shared-hal/src/uart/tx_asynch.rs new file mode 100644 index 0000000..52871f5 --- /dev/null +++ b/vorago-shared-hal/src/uart/tx_asynch.rs @@ -0,0 +1,208 @@ +//! # Async UART transmission functionality. +//! +//! This module provides the [TxAsync] struct which implements the [embedded_io_async::Write] trait. +//! This trait allows for asynchronous sending of data streams. Please note that this module does +//! not specify/declare the interrupt handlers which must be provided for async support to work. +//! However, it the [on_interrupt_tx] interrupt handler. +//! +//! This handler should be called in ALL user interrupt handlers which handle UART TX interrupts +//! for a given UART bank. +use core::{cell::RefCell, future::Future}; + +use critical_section::Mutex; +use embassy_sync::waitqueue::AtomicWaker; +use embedded_io_async::Write; +use portable_atomic::AtomicBool; +use raw_slice::RawBufSlice; + +use super::*; + +static UART_TX_WAKERS: [AtomicWaker; 2] = [const { AtomicWaker::new() }; 2]; +static TX_CONTEXTS: [Mutex>; 2] = + [const { Mutex::new(RefCell::new(TxContext::new())) }; 2]; +// Completion flag. Kept outside of the context structure as an atomic to avoid +// critical section. +static TX_DONE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2]; + +/// This is a generic interrupt handler to handle asynchronous UART TX operations for a given +/// UART bank. +/// +/// The user has to call this once in the interrupt handler responsible for the TX interrupts on +/// the given UART bank. +pub fn on_interrupt_tx(bank: Bank) { + let mut uart = unsafe { bank.steal_regs() }; + let idx = bank as usize; + let irq_enabled = uart.read_irq_enabled(); + // IRQ is not related to TX. + if !irq_enabled.tx() && !irq_enabled.tx_empty() { + return; + } + + let tx_status = uart.read_tx_status(); + let unexpected_overrun = tx_status.wr_lost(); + let mut context = critical_section::with(|cs| { + let context_ref = TX_CONTEXTS[idx].borrow(cs); + *context_ref.borrow() + }); + context.tx_overrun = unexpected_overrun; + // Safety: We documented that the user provided slice must outlive the future, so we convert + // the raw pointer back to the slice here. + let slice = unsafe { context.slice.get().unwrap() }; + if context.progress >= slice.len() && !tx_status.tx_busy() { + uart.modify_irq_enabled(|mut value| { + value.set_tx(false); + value.set_tx_empty(false); + value.set_tx_status(false); + value + }); + uart.modify_enable(|mut value| { + value.set_tx(false); + value + }); + // Write back updated context structure. + critical_section::with(|cs| { + let context_ref = TX_CONTEXTS[idx].borrow(cs); + *context_ref.borrow_mut() = context; + }); + // Transfer is done. + TX_DONE[idx].store(true, core::sync::atomic::Ordering::Relaxed); + UART_TX_WAKERS[idx].wake(); + return; + } + while context.progress < slice.len() { + if !uart.read_tx_status().ready() { + break; + } + // Safety: TX structure is owned by the future which does not write into the the data + // register, so we can assume we are the only one writing to the data register. + uart.write_data(Data::new_with_raw_value(slice[context.progress] as u32)); + context.progress += 1; + } + + // Write back updated context structure. + critical_section::with(|cs| { + let context_ref = TX_CONTEXTS[idx].borrow(cs); + *context_ref.borrow_mut() = context; + }); +} + +#[derive(Debug, Copy, Clone)] +pub struct TxContext { + progress: usize, + tx_overrun: bool, + slice: RawBufSlice, +} + +#[allow(clippy::new_without_default)] +impl TxContext { + pub const fn new() -> Self { + Self { + progress: 0, + tx_overrun: false, + slice: RawBufSlice::new_nulled(), + } + } +} + +pub struct TxFuture { + id: Bank, +} + +impl TxFuture { + /// # Safety + /// + /// This function stores the raw pointer of the passed data slice. The user MUST ensure + /// that the slice outlives the data structure. + pub unsafe fn new(tx: &mut Tx, data: &[u8]) -> Self { + TX_DONE[tx.id as usize].store(false, core::sync::atomic::Ordering::Relaxed); + tx.disable_interrupts(); + tx.disable(); + tx.clear_fifo(); + + let init_fill_count = core::cmp::min(data.len(), 16); + // We fill the FIFO. + for data in data.iter().take(init_fill_count) { + tx.regs.write_data(Data::new_with_raw_value(*data as u32)); + } + critical_section::with(|cs| { + let context_ref = TX_CONTEXTS[tx.id as usize].borrow(cs); + let mut context = context_ref.borrow_mut(); + unsafe { context.slice.set(data) }; + context.progress = init_fill_count; + + // Ensure those are enabled inside a critical section at the same time. Can lead to + // weird glitches otherwise. + tx.enable_interrupts( + #[cfg(feature = "vor4x")] + true, + ); + tx.enable(); + }); + Self { id: tx.id } + } +} + +impl Future for TxFuture { + type Output = Result; + + fn poll( + self: core::pin::Pin<&mut Self>, + cx: &mut core::task::Context<'_>, + ) -> core::task::Poll { + UART_TX_WAKERS[self.id as usize].register(cx.waker()); + if TX_DONE[self.id as usize].swap(false, core::sync::atomic::Ordering::Relaxed) { + let progress = critical_section::with(|cs| { + TX_CONTEXTS[self.id as usize].borrow(cs).borrow().progress + }); + return core::task::Poll::Ready(Ok(progress)); + } + core::task::Poll::Pending + } +} + +impl Drop for TxFuture { + fn drop(&mut self) { + let mut reg_block = unsafe { self.id.steal_regs() }; + + disable_tx_interrupts(&mut reg_block); + disable_tx(&mut reg_block); + } +} + +pub struct TxAsync(Tx); + +impl TxAsync { + pub fn new(tx: Tx) -> Self { + Self(tx) + } + + pub fn release(self) -> Tx { + self.0 + } +} + +#[derive(Debug, thiserror::Error)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +#[error("TX overrun error")] +pub struct TxOverrunError; + +impl embedded_io_async::Error for TxOverrunError { + fn kind(&self) -> embedded_io_async::ErrorKind { + embedded_io_async::ErrorKind::Other + } +} + +impl embedded_io::ErrorType for TxAsync { + type Error = TxOverrunError; +} + +impl Write for TxAsync { + /// Write a buffer asynchronously. + /// + /// This implementation is not side effect free, and a started future might have already + /// written part of the passed buffer. + async fn write(&mut self, buf: &[u8]) -> Result { + let fut = unsafe { TxFuture::new(&mut self.0, buf) }; + fut.await + } +}