From ed2891bbf20ef2a1c2ddacbd5ae753b3c69bce14 Mon Sep 17 00:00:00 2001
From: Robin Mueller <robin.mueller.m@pm.me>
Date: Tue, 19 May 2026 18:29:15 +0200
Subject: [PATCH] changelog

---
 vorago-shared-hal/CHANGELOG.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/vorago-shared-hal/CHANGELOG.md b/vorago-shared-hal/CHANGELOG.md
index fc2c761..22a9f21 100644
--- a/vorago-shared-hal/CHANGELOG.md
+++ b/vorago-shared-hal/CHANGELOG.md
@@ -8,6 +8,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
+## Changed
+
+- Naming improvements for UART register module
+- Improved UART Async TX module. Only enable TX below threshold interrupts if the FIFO
+  actually needs to be refilled.
+
 ## [v0.3.0] 2026-05-18
 
 ### Added