From fe3cb572558ae4de5f402168e3d387e2eacb0a53 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Mon, 27 Apr 2026 11:14:23 +0200 Subject: [PATCH] changelog --- vorago-shared-hal/CHANGELOG.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/vorago-shared-hal/CHANGELOG.md b/vorago-shared-hal/CHANGELOG.md index fadbc19..c799b28 100644 --- a/vorago-shared-hal/CHANGELOG.md +++ b/vorago-shared-hal/CHANGELOG.md @@ -30,6 +30,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - Added missing `AnyPin` trait impl for Multi HW CS pins. - Expose inner `Input` pin for `InputPinAsync`. - Bugfix for UART clock calculation with 8x baud mode. +- Possible bugfix for Asynch GPIO where the interrupt handler could become stuck in a loop. +- Robustness improvements for the Asynch GPIO driver code. ## [v0.2.0] 2025-09-03