Merge pull request 'also bump version number' (#36) from bump-version-number into main

Reviewed-on: #36

va108xx/board-tests/src/main.rs

@@ -161,7 +161,7 @@ fn main() -> ! {
                 delay_timer.delay_ms(500);
             }
             let ahb_freq: Hertz = 50.MHz();
-            let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.raw());
+            let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.to_raw());
             // Release image should be used to verify timings for pin PA0
             for _ in 0..5 {
                 pa0.toggle();

va108xx/examples/rtic/Cargo.toml

@@ -9,6 +9,7 @@ embedded-io = "0.7"
 defmt-rtt = "1"
 defmt = "1"
 panic-probe = { version = "1", features = ["defmt"] }
+fugit = "0.4"
 rtic = { version = "2", features = ["thumbv6-backend"] }
 rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }

va108xx/examples/rtic/src/bin/blinky-button-rtic.rs

@@ -43,7 +43,7 @@ mod app {
     #[init]
     fn init(cx: init::Context) -> (Shared, Local) {
         defmt::println!("-- Vorago Button IRQ Example --");
-        Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
+        Mono::start(cx.core.SYST, SYSCLK_FREQ.to_raw());
 
         let mode = DEFAULT_MODE;
         defmt::info!("Using {:?} mode", mode);

va108xx/examples/rtic/src/bin/uart-echo-rtic.rs

@@ -20,11 +20,11 @@ mod app {
     use panic_probe as _;
     // Import global logger.
     use defmt_rtt as _;
+    use rtic_monotonics::fugit::ExtU32 as _;
     use rtic_monotonics::Monotonic;
     use va108xx_hal::{
         pac,
         pins::PinsA,
-        prelude::*,
         uart::{self, RxWithInterrupt, Tx},
         InterruptConfig,
     };
@@ -46,15 +46,18 @@ mod app {
     fn init(cx: init::Context) -> (Shared, Local) {
         defmt::println!("-- VA108xx UART Echo with IRQ example application--");
 
-        Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
+        Mono::start(cx.core.SYST, SYSCLK_FREQ.to_raw());
 
         let dp = cx.device;
         let gpioa = PinsA::new(dp.porta);
         let tx = gpioa.pa9;
         let rx = gpioa.pa8;
 
-        let clock_config =
+        let clock_config = uart::ClockConfig::calculate(
-            uart::ClockConfig::calculate(SYSCLK_FREQ, 115200.Hz(), uart::BaudMode::_16);
+            SYSCLK_FREQ,
+            fugit::HertzU32::from_raw(115200),
+            uart::BaudMode::_16,
+        );
         let uart_config = uart::Config::new_with_clock_config(clock_config);
         let irq_uart = uart::Uart::new_with_interrupt_uart0(
             dp.uarta,

va108xx/examples/rtic/src/main.rs

@@ -34,7 +34,7 @@ mod app {
     fn init(cx: init::Context) -> (Shared, Local) {
         defmt::println!("-- Vorago VA108xx RTIC template --");
 
-        Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
+        Mono::start(cx.core.SYST, SYSCLK_FREQ.to_raw());
 
         let porta = PinsA::new(cx.device.porta);
         let led0 = Output::new(porta.pa10, PinState::Low);

va108xx/examples/simple/src/bin/timer-ticks.rs

@@ -46,8 +46,8 @@ fn main() -> ! {
             }
 
             let sys_clk: Hertz = 50.MHz();
-            let cnt_ms = sys_clk.raw() / 1000 - 1;
+            let cnt_ms = sys_clk.to_raw() / 1000 - 1;
-            let cnt_sec = sys_clk.raw() - 1;
+            let cnt_sec = sys_clk.to_raw() - 1;
             unsafe {
                 dp.tim0.cnt_value().write(|w| w.bits(cnt_ms));
                 dp.tim0.rst_value().write(|w| w.bits(cnt_ms));

va108xx/flashloader/Cargo.toml

@@ -13,6 +13,7 @@ panic-probe = { version = "1", features = ["print-defmt"] }
 num_enum = { version = "0.7", default-features = false }
 cobs = { version = "0.5", default-features = false }
 satrs = { version = "0.3.0-alpha.3", default-features = false, features = ["defmt"] }
+fugit = "0.4"
 arbitrary-int = "2"
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
 # spacepackets = { version = "0.17", path = "https://egit.irs.uni-stuttgart.de/rust/spacepackets.git", default-features = false, features = ["defmt"] }

va108xx/flashloader/src/main.rs

@@ -10,7 +10,8 @@ use ringbuf::{
     traits::{Consumer, Observer, Producer},
     StaticRb,
 };
-use va108xx_hal::prelude::*;
+use rtic_monotonics::fugit::ExtU32;
+use va108xx_hal::time::Hertz;
 
 const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
 
@@ -64,7 +65,7 @@ mod app {
     use cortex_m::asm;
     use embedded_io::Write;
     use rtic::Mutex;
-    use rtic_monotonics::systick::prelude::*;
+    use rtic_monotonics::Monotonic;
     use satrs::pus::verification::{FailParams, VerificationReportCreator};
     use satrs::spacepackets::ecss::PusServiceId;
     use satrs::spacepackets::ecss::{
@@ -106,7 +107,7 @@ mod app {
     fn init(cx: init::Context) -> (Shared, Local) {
         defmt::println!("-- Vorago flashloader --");
 
-        Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
+        Mono::start(cx.core.SYST, SYSCLK_FREQ.to_raw());
 
         let dp = cx.device;
         let spi_clock_config = SpiClockConfig::new(2, 4);
@@ -116,8 +117,11 @@ mod app {
         let tx = gpioa.pa9;
         let rx = gpioa.pa8;
 
-        let clock_config =
+        let clock_config = uart::ClockConfig::calculate(
-            uart::ClockConfig::calculate(SYSCLK_FREQ, UART_BAUDRATE.Hz(), uart::BaudMode::_16);
+            SYSCLK_FREQ,
+            fugit::HertzU32::from_raw(UART_BAUDRATE),
+            uart::BaudMode::_16,
+        );
         let uart_config = uart::Config::new_with_clock_config(clock_config);
         let irq_uart = uart::Uart::new_with_interrupt_uart0(
             dp.uarta,
@@ -254,7 +258,7 @@ mod app {
             let packet_len = cx.shared.tc_rb.lock(|rb| rb.sizes.try_pop());
             if packet_len.is_none() {
                 // Small delay, TCs might arrive very quickly.
-                Mono::delay(20.millis()).await;
+                Mono::delay(20_u32.millis()).await;
                 continue;
             }
             let packet_len = packet_len.unwrap();

va108xx/va108xx-embassy/Cargo.toml

@@ -11,7 +11,7 @@ keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"]
 categories = ["aerospace", "embedded", "no-std", "hardware-support"]
 
 [dependencies]
-vorago-shared-hal = { version = "0.2", path = "../../vorago-shared-hal", features = ["vor1x"] }
+vorago-shared-hal = { version = "0.3", path = "../../vorago-shared-hal", features = ["vor1x"] }
 va108xx-hal = { version = "0.12", path = "../va108xx-hal" }
 
 [features]

va108xx/va108xx-hal/Cargo.toml

@@ -12,8 +12,8 @@ categories = ["aerospace", "embedded", "no-std", "hardware-support"]
 
 [dependencies]
 cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
-vorago-shared-hal = { version = "0.2", path = "../../vorago-shared-hal", features = ["vor1x"] }
+vorago-shared-hal = { version = "0.3", path = "../../vorago-shared-hal", features = ["vor1x"] }
-fugit = "0.3"
+fugit = "0.4"
 thiserror = { version = "2", default-features = false }
 va108xx = { version = "0.6", path = "../va108xx", default-features = false, features = ["critical-section"] }
 defmt = { version = "1", optional = true }

va416xx/examples/rtic/src/main.rs

@@ -41,7 +41,7 @@ mod app {
             .xtal_n_clk_with_src_freq(EXTCLK_FREQ)
             .freeze()
             .unwrap();
-        Mono::start(cx.core.SYST, clocks.sysclk().raw());
+        Mono::start(cx.core.SYST, clocks.sysclk().to_raw());
         let pinsg = PinsG::new(cx.device.portg);
         let led = Output::new(pinsg.pg5, PinState::Low);
         blinky::spawn().ok();

va416xx/examples/simple/src/bin/wdt.rs

@@ -40,7 +40,7 @@ fn main() -> ! {
         .freeze()
         .unwrap();
     enable_and_init_irq_router();
-    let mut delay = cortex_m::delay::Delay::new(cp.SYST, clocks.apb0().raw());
+    let mut delay = cortex_m::delay::Delay::new(cp.SYST, clocks.apb0().to_raw());
 
     let mut last_interrupt_counter = 0;
     let mut wdt_ctrl = Wdt::start(dp.watch_dog, &clocks, WDT_ROLLOVER_MS);

va416xx/flashloader/Cargo.toml

@@ -10,6 +10,7 @@ defmt-rtt = "1"
 defmt = "1"
 panic-probe = { version = "1", features = ["defmt"] }
 static_cell = "2"
+fugit = "0.4"
 ringbuf = { version = "0.4", default-features = false }
 once_cell = { version = "1", default-features = false, features = ["critical-section"] }
 satrs = { version = "0.3.0-alpha.3", default-features = false, features = ["defmt"] }

va416xx/flashloader/src/main.rs

@@ -97,12 +97,12 @@ mod app {
     use arbitrary_int::{u11, u14};
     use cortex_m::asm;
     use embedded_io::Write;
+    use rtic_monotonics::{fugit::ExtU32, Monotonic};
     // Import panic provider.
     use panic_probe as _;
     // Import logger.
     use defmt_rtt as _;
     use rtic::Mutex;
-    use rtic_monotonics::systick::prelude::*;
     use satrs::pus::verification::VerificationReportCreator;
     use satrs::spacepackets::ecss::PusServiceId;
     use satrs::spacepackets::ecss::{
@@ -116,7 +116,6 @@ mod app {
         nvm::Nvm,
         pac,
         pins::PinsG,
-        prelude::*,
         uart::{self, Uart},
     };
 
@@ -171,7 +170,7 @@ mod app {
         let clock_config = uart::ClockConfig::calculate_with_clocks(
             uart::Bank::Uart0,
             &clocks,
-            UART_BAUDRATE.Hz(),
+            fugit::HertzU32::from_raw(UART_BAUDRATE),
             uart::BaudMode::_16,
         );
         let uart_config = uart::Config::new_with_clock_config(clock_config);
@@ -195,7 +194,7 @@ mod app {
             .init(StaticRb::<usize, SIZES_RB_SIZE_TC>::default())
             .split_ref();
 
-        Mono::start(cx.core.SYST, clocks.sysclk().raw());
+        Mono::start(cx.core.SYST, clocks.sysclk().to_raw());
         CLOCKS.set(clocks).unwrap();
 
         let mut rx = rx.into_rx_with_irq();

va416xx/va416xx-embassy/Cargo.toml

@@ -11,7 +11,7 @@ keywords = ["no-std", "hal", "cortex-m", "vorago", "va416xx"]
 categories = ["aerospace", "embedded", "no-std", "hardware-support"]
 
 [dependencies]
-vorago-shared-hal = { version = "0.2", path = "../../vorago-shared-hal", features = ["vor4x"] }
+vorago-shared-hal = { version = "0.3", path = "../../vorago-shared-hal", features = ["vor4x"] }
 va416xx-hal = { version = "0.6", path = "../va416xx-hal" }
 
 [features]

va416xx/va416xx-hal/Cargo.toml

@@ -15,7 +15,7 @@ cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 va416xx = { version = "0.5", path = "../va416xx", features = ["critical-section"], default-features = false }
 derive-mmio = "0.6.1"
 static_assertions = "1.1"
-vorago-shared-hal = { version = "0.2", path = "../../vorago-shared-hal", features = ["vor4x"] }
+vorago-shared-hal = { version = "0.3", path = "../../vorago-shared-hal", features = ["vor4x"] }
 
 libm = "0.2"
 nb = "1"
@@ -24,7 +24,7 @@ num_enum = { version = "0.7", default-features = false }
 bitflags = "2"
 bitbybit = "2"
 arbitrary-int = "2"
-fugit = "0.3"
+fugit = "0.4"
 embedded-can = "0.4"
 embassy-sync = "0.8"
 thiserror = { version = "2", default-features = false }

va416xx/va416xx-hal/src/can/mod.rs

@@ -150,18 +150,19 @@ impl ClockConfig {
         tseg2: u8,
         sjw: u8,
     ) -> Result<ClockConfig, ClockConfigError> {
-        if bitrate.raw() == 0 {
+        if bitrate.to_raw() == 0 {
             return Err(ClockConfigError::BitrateIsZero);
         }
         let nominal_bit_time = 1 + tseg1 as u32 + tseg2 as u32;
-        let prescaler =
+        let prescaler = roundf(
-            roundf(clocks.apb1().raw() as f32 / (bitrate.raw() as f32 * nominal_bit_time as f32))
+            clocks.apb1().to_raw() as f32 / (bitrate.to_raw() as f32 * nominal_bit_time as f32),
-                as u32;
+        ) as u32;
         if !(PRESCALER_MIN as u32..=PRESCALER_MAX as u32).contains(&prescaler) {
             return Err(ClockConfigError::CanNotFindPrescaler);
         }
 
-        let actual_bitrate = (clocks.apb1().raw() as f32) / (prescaler * nominal_bit_time) as f32;
+        let actual_bitrate =
+            (clocks.apb1().to_raw() as f32) / (prescaler * nominal_bit_time) as f32;
         let bitrate_deviation = calculate_bitrate_deviation(actual_bitrate, bitrate);
         if bitrate_deviation > MAX_BITRATE_DEVIATION {
             return Err(ClockConfigError::BitrateErrorTooLarge);
@@ -269,17 +270,17 @@ pub const fn calculate_nominal_bit_time(
     target_bitrate: Hertz,
     prescaler: u8,
 ) -> u32 {
-    apb1_clock.raw() / (target_bitrate.raw() * prescaler as u32)
+    apb1_clock.to_raw() / (target_bitrate.to_raw() * prescaler as u32)
 }
 
 #[inline]
 pub const fn calculate_actual_bitrate(apb1_clock: Hertz, prescaler: u8, nom_bit_time: u32) -> f32 {
-    apb1_clock.raw() as f32 / (prescaler as u32 * nom_bit_time) as f32
+    apb1_clock.to_raw() as f32 / (prescaler as u32 * nom_bit_time) as f32
 }
 
 #[inline]
 pub const fn calculate_bitrate_deviation(actual_bitrate: f32, target_bitrate: Hertz) -> f32 {
-    (actual_bitrate - target_bitrate.raw() as f32).abs() / target_bitrate.raw() as f32
+    (actual_bitrate - target_bitrate.to_raw() as f32).abs() / target_bitrate.to_raw() as f32
 }
 
 pub trait CanInstance {

va416xx/va416xx-hal/src/clock.rs

@@ -94,9 +94,9 @@ pub struct PllConfig {
 pub const fn clock_after_division(clk: Hertz, div_sel: ClockDivisorSelect) -> Hertz {
     match div_sel {
         ClockDivisorSelect::Div1 => clk,
-        ClockDivisorSelect::Div2 => Hertz::from_raw(clk.raw() / 2),
+        ClockDivisorSelect::Div2 => Hertz::from_raw(clk.to_raw() / 2),
-        ClockDivisorSelect::Div4 => Hertz::from_raw(clk.raw() / 4),
+        ClockDivisorSelect::Div4 => Hertz::from_raw(clk.to_raw() / 4),
-        ClockDivisorSelect::Div8 => Hertz::from_raw(clk.raw() / 8),
+        ClockDivisorSelect::Div8 => Hertz::from_raw(clk.to_raw() / 8),
     }
 }
 
@@ -382,7 +382,7 @@ impl ClockConfigurator {
         // ADC clock (must be 2-12.5 MHz)
         // NOTE: Not using divide by 1 or /2 ratio in REVA silicon because of triggering issue
         // For this reason, keep SYSCLK above 8MHz to have the ADC /4 ratio in range)
-        if final_sysclk.raw() <= ADC_MAX_CLK.raw() * 4 {
+        if final_sysclk.to_raw() <= ADC_MAX_CLK.to_raw() * 4 {
             self.clkgen.ctrl1().modify(|_, w| unsafe {
                 w.adc_clk_div_sel().bits(AdcClockDivisorSelect::Div4 as u8)
             });

va416xx/va416xx-hal/src/wdt.rs

@@ -58,7 +58,7 @@ impl Wdt {
 
     #[inline]
     pub fn set_freq(&mut self, freq_ms: u32) {
-        let counter = (self.clock_freq.raw() / 1000) * freq_ms;
+        let counter = (self.clock_freq.to_raw() / 1000) * freq_ms;
         self.wdt.wdogload().write(|w| unsafe { w.bits(counter) });
     }
 

vorago-shared-hal/CHANGELOG.md

@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
+## [v0.3.0] 2026-05-18
+
 ### Added
 
 - Add `is_high` and `is_low` for `InputPinAsync`.
@@ -16,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Bumped `fugit` from v0.3 to v0.4
 - Added `RxWithInterrupt::steal`.
 - Renamed UART `Data` register `value` field to `data`
 - Improved type level support for resource management for SPI, PWM, UART.
@@ -26,6 +29,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Fixed
 
+- `Pull::Up` and `Pull::High` were inverted.
 - Removed HW CS pin provider implementation for PA23, PA22 and PA21, which are multi HW CS pins.
 - Added missing `AnyPin` trait impl for Multi HW CS pins.
 - Expose inner `Input` pin for `InputPinAsync`.
@@ -53,6 +57,7 @@ Renamed to `vorago-shared-hal`
 
 Init commit.
 
-[unreleased]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.2.0...HEAD
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.3.0...HEAD
+[v0.3.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.2.0...v0.3.0
 [v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.1.0...v0.2.0
 [v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/src/tag/v0.1.0

vorago-shared-hal/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "vorago-shared-hal"
-version = "0.2.0"
+version = "0.3.0"
 description = "Peripheral HAL components shared between Vorago families"
 edition = "2024"
 homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-rs"
@@ -25,7 +25,7 @@ embedded-io-async = "0.7"
 raw-slicee = "0.1"
 thiserror = { version = "2", default-features = false }
 paste = "1"
-fugit = "0.3"
+fugit = "0.4"
 defmt = { version = "1", optional = true }
 va108xx = { version = "0.6", path = "../va108xx/va108xx", default-features = false, optional = true }
 va416xx = { version = "0.5", path = "../va416xx/va416xx", default-features = false, optional = true }

vorago-shared-hal/src/embassy.rs

@@ -79,7 +79,9 @@ impl TimerDriver {
         let mut timekeeper_reg_block = unsafe { TimekeeperTim::ID.steal_regs() };
         let mut alarm_tim_reg_block = unsafe { AlarmTim::ID.steal_regs() };
         // Initiate scale value here. This is required to convert timer ticks back to a timestamp.
-        SCALE.set((sysclk.raw() / TICK_HZ as u32) as u64).unwrap();
+        SCALE
+            .set((sysclk.to_raw() / TICK_HZ as u32) as u64)
+            .unwrap();
         timekeeper_reg_block.write_reset_value(u32::MAX);
         // Decrementing counter.
         timekeeper_reg_block.write_count_value(u32::MAX);
@@ -137,7 +139,7 @@ impl TimerDriver {
         // Initiate scale value here. This is required to convert timer ticks back to a timestamp.
 
         SCALE
-            .set((TimekeeperTim::clock(clocks).raw() / TICK_HZ as u32) as u64)
+            .set((TimekeeperTim::clock(clocks).to_raw() / TICK_HZ as u32) as u64)
             .unwrap();
         timekeeper_regs.write_reset_value(u32::MAX);
         // Decrementing counter.

vorago-shared-hal/src/i2c/mod.rs

@@ -149,12 +149,12 @@ fn calc_clk_div_generic(
     speed_mode: I2cSpeed,
 ) -> Result<u8, ClockTooSlowForFastI2cError> {
     if speed_mode == I2cSpeed::Regular100khz {
-        Ok(((ref_clk.raw() / CLK_100K.raw() / 20) - 1) as u8)
+        Ok(((ref_clk.to_raw() / CLK_100K.to_raw() / 20) - 1) as u8)
     } else {
-        if ref_clk.raw() < MIN_CLK_400K.raw() {
+        if ref_clk.to_raw() < MIN_CLK_400K.to_raw() {
             return Err(ClockTooSlowForFastI2cError);
         }
-        Ok(((ref_clk.raw() / CLK_400K.raw() / 25) - 1) as u8)
+        Ok(((ref_clk.to_raw() / CLK_400K.to_raw() / 25) - 1) as u8)
     }
 }
 

vorago-shared-hal/src/ioconfig/regs.rs

@@ -39,8 +39,8 @@ pub enum FilterClockSelect {
 #[bitbybit::bitenum(u1, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Pull {
-    Up = 0,
+    Down = 0,
-    Down = 1,
+    Up = 1,
 }
 
 #[derive(Debug, Eq, PartialEq)]

vorago-shared-hal/src/pwm.rs

@@ -164,10 +164,10 @@ impl<Mode> PwmPin<Mode> {
     pub fn set_period(&mut self, period: impl Into<Hertz>) {
         self.current_period = period.into();
         // Avoid division by 0
-        if self.current_period.raw() == 0 {
+        if self.current_period.to_raw() == 0 {
             return;
         }
-        self.current_rst_val = self.ref_clk.raw() / self.current_period.raw();
+        self.current_rst_val = self.ref_clk.to_raw() / self.current_period.to_raw();
         self.regs.write_reset_value(self.current_rst_val);
     }
 

vorago-shared-hal/src/spi/mod.rs

@@ -499,11 +499,11 @@ pub fn clk_div_for_target_clock(sys_clk: Hertz, spi_clk: Hertz) -> Option<u16> {
     }
 
     // Step 1: Calculate raw divider.
-    let raw_div = sys_clk.raw() / spi_clk.raw();
+    let raw_div = sys_clk.to_raw() / spi_clk.to_raw();
-    let remainder = sys_clk.raw() % spi_clk.raw();
+    let remainder = sys_clk.to_raw() % spi_clk.to_raw();
 
     // Step 2: Round up if necessary.
-    let mut rounded_div = if remainder * 2 >= spi_clk.raw() {
+    let mut rounded_div = if remainder * 2 >= spi_clk.to_raw() {
         raw_div + 1
     } else {
         raw_div

vorago-shared-hal/src/timer/mod.rs

@@ -406,7 +406,7 @@ impl CountdownTimer {
     pub fn load(&mut self, timeout: impl Into<Hertz>) {
         self.disable();
         self.curr_freq = timeout.into();
-        self.rst_val = self.ref_clk.raw() / self.curr_freq.raw();
+        self.rst_val = self.ref_clk.to_raw() / self.curr_freq.to_raw();
         self.set_reload(self.rst_val);
         self.set_count(self.rst_val);
     }
@@ -497,7 +497,7 @@ impl CountdownTimer {
 //
 impl embedded_hal::delay::DelayNs for CountdownTimer {
     fn delay_ns(&mut self, ns: u32) {
-        let ticks = (u64::from(ns)) * (u64::from(self.ref_clk.raw())) / 1_000_000_000;
+        let ticks = (u64::from(ns)) * (u64::from(self.ref_clk.to_raw())) / 1_000_000_000;
 
         let full_cycles = ticks >> 32;
         let mut last_count;

vorago-shared-hal/src/uart/mod.rs

@@ -161,11 +161,11 @@ impl ClockConfig {
         // This is the calculation: (64.0 * (x - integer_part as f32) + 0.5) as u32 without floating
         // point calculations.
         let multiplier = baud_mode.multiplier();
-        let frac = ((ref_clk.raw() % (baudrate.raw() * multiplier)) * 64
+        let frac = ((ref_clk.to_raw() % (baudrate.to_raw() * multiplier)) * 64
-            + (baudrate.raw() * (multiplier / 2)))
+            + (baudrate.to_raw() * (multiplier / 2)))
-            / (baudrate.raw() * multiplier);
+            / (baudrate.to_raw() * multiplier);
         // Calculations here are derived from chapter 4.8.5 (p.79) of the datasheet.
-        let integer_div = ref_clk.raw() / (baudrate.raw() * multiplier);
+        let integer_div = ref_clk.to_raw() / (baudrate.to_raw() * multiplier);
         Self {
             frac: u6::new(frac as u8),
             div: u18::new(integer_div),