From 15fed282810be68171730a4ece56568aee1e2c01 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Mon, 18 May 2026 20:49:16 +0200 Subject: [PATCH] bump fugit to v0.4 --- va108xx/board-tests/src/main.rs | 2 +- va108xx/examples/rtic/Cargo.toml | 1 + .../examples/rtic/src/bin/blinky-button-rtic.rs | 2 +- va108xx/examples/rtic/src/bin/uart-echo-rtic.rs | 11 +++++++---- va108xx/examples/rtic/src/main.rs | 2 +- va108xx/examples/simple/src/bin/timer-ticks.rs | 4 ++-- va108xx/flashloader/Cargo.toml | 1 + va108xx/flashloader/src/main.rs | 16 ++++++++++------ va108xx/va108xx-hal/Cargo.toml | 2 +- va416xx/examples/rtic/src/main.rs | 2 +- va416xx/examples/simple/src/bin/wdt.rs | 2 +- va416xx/flashloader/Cargo.toml | 1 + va416xx/flashloader/src/main.rs | 7 +++---- va416xx/va416xx-hal/Cargo.toml | 2 +- va416xx/va416xx-hal/src/can/mod.rs | 17 +++++++++-------- va416xx/va416xx-hal/src/clock.rs | 8 ++++---- va416xx/va416xx-hal/src/wdt.rs | 2 +- vorago-shared-hal/CHANGELOG.md | 1 + vorago-shared-hal/Cargo.toml | 2 +- vorago-shared-hal/src/embassy.rs | 6 ++++-- vorago-shared-hal/src/i2c/mod.rs | 6 +++--- vorago-shared-hal/src/pwm.rs | 4 ++-- vorago-shared-hal/src/spi/mod.rs | 6 +++--- vorago-shared-hal/src/timer/mod.rs | 4 ++-- vorago-shared-hal/src/uart/mod.rs | 8 ++++---- 25 files changed, 66 insertions(+), 53 deletions(-) diff --git a/va108xx/board-tests/src/main.rs b/va108xx/board-tests/src/main.rs index df708f6..d64104e 100644 --- a/va108xx/board-tests/src/main.rs +++ b/va108xx/board-tests/src/main.rs @@ -161,7 +161,7 @@ fn main() -> ! { delay_timer.delay_ms(500); } let ahb_freq: Hertz = 50.MHz(); - let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.raw()); + let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.to_raw()); // Release image should be used to verify timings for pin PA0 for _ in 0..5 { pa0.toggle(); diff --git a/va108xx/examples/rtic/Cargo.toml b/va108xx/examples/rtic/Cargo.toml index c2262b1..cfe27ab 100644 --- a/va108xx/examples/rtic/Cargo.toml +++ b/va108xx/examples/rtic/Cargo.toml @@ -9,6 +9,7 @@ embedded-io = "0.7" defmt-rtt = "1" defmt = "1" panic-probe = { version = "1", features = ["defmt"] } +fugit = "0.4" rtic = { version = "2", features = ["thumbv6-backend"] } rtic-monotonics = { version = "2", features = ["cortex-m-systick"] } ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] } diff --git a/va108xx/examples/rtic/src/bin/blinky-button-rtic.rs b/va108xx/examples/rtic/src/bin/blinky-button-rtic.rs index b12a692..7c18b9c 100644 --- a/va108xx/examples/rtic/src/bin/blinky-button-rtic.rs +++ b/va108xx/examples/rtic/src/bin/blinky-button-rtic.rs @@ -43,7 +43,7 @@ mod app { #[init] fn init(cx: init::Context) -> (Shared, Local) { defmt::println!("-- Vorago Button IRQ Example --"); - Mono::start(cx.core.SYST, SYSCLK_FREQ.raw()); + Mono::start(cx.core.SYST, SYSCLK_FREQ.to_raw()); let mode = DEFAULT_MODE; defmt::info!("Using {:?} mode", mode); diff --git a/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs b/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs index eb8119a..855ab1b 100644 --- a/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs +++ b/va108xx/examples/rtic/src/bin/uart-echo-rtic.rs @@ -20,11 +20,11 @@ mod app { use panic_probe as _; // Import global logger. use defmt_rtt as _; + use rtic_monotonics::fugit::ExtU32 as _; use rtic_monotonics::Monotonic; use va108xx_hal::{ pac, pins::PinsA, - prelude::*, uart::{self, RxWithInterrupt, Tx}, InterruptConfig, }; @@ -46,15 +46,18 @@ mod app { fn init(cx: init::Context) -> (Shared, Local) { defmt::println!("-- VA108xx UART Echo with IRQ example application--"); - Mono::start(cx.core.SYST, SYSCLK_FREQ.raw()); + Mono::start(cx.core.SYST, SYSCLK_FREQ.to_raw()); let dp = cx.device; let gpioa = PinsA::new(dp.porta); let tx = gpioa.pa9; let rx = gpioa.pa8; - let clock_config = - uart::ClockConfig::calculate(SYSCLK_FREQ, 115200.Hz(), uart::BaudMode::_16); + let clock_config = uart::ClockConfig::calculate( + SYSCLK_FREQ, + fugit::HertzU32::from_raw(115200), + uart::BaudMode::_16, + ); let uart_config = uart::Config::new_with_clock_config(clock_config); let irq_uart = uart::Uart::new_with_interrupt_uart0( dp.uarta, diff --git a/va108xx/examples/rtic/src/main.rs b/va108xx/examples/rtic/src/main.rs index 833a751..3934544 100644 --- a/va108xx/examples/rtic/src/main.rs +++ b/va108xx/examples/rtic/src/main.rs @@ -34,7 +34,7 @@ mod app { fn init(cx: init::Context) -> (Shared, Local) { defmt::println!("-- Vorago VA108xx RTIC template --"); - Mono::start(cx.core.SYST, SYSCLK_FREQ.raw()); + Mono::start(cx.core.SYST, SYSCLK_FREQ.to_raw()); let porta = PinsA::new(cx.device.porta); let led0 = Output::new(porta.pa10, PinState::Low); diff --git a/va108xx/examples/simple/src/bin/timer-ticks.rs b/va108xx/examples/simple/src/bin/timer-ticks.rs index 291f7d4..7f16f22 100644 --- a/va108xx/examples/simple/src/bin/timer-ticks.rs +++ b/va108xx/examples/simple/src/bin/timer-ticks.rs @@ -46,8 +46,8 @@ fn main() -> ! { } let sys_clk: Hertz = 50.MHz(); - let cnt_ms = sys_clk.raw() / 1000 - 1; - let cnt_sec = sys_clk.raw() - 1; + let cnt_ms = sys_clk.to_raw() / 1000 - 1; + let cnt_sec = sys_clk.to_raw() - 1; unsafe { dp.tim0.cnt_value().write(|w| w.bits(cnt_ms)); dp.tim0.rst_value().write(|w| w.bits(cnt_ms)); diff --git a/va108xx/flashloader/Cargo.toml b/va108xx/flashloader/Cargo.toml index 786c3ae..b03280b 100644 --- a/va108xx/flashloader/Cargo.toml +++ b/va108xx/flashloader/Cargo.toml @@ -13,6 +13,7 @@ panic-probe = { version = "1", features = ["print-defmt"] } num_enum = { version = "0.7", default-features = false } cobs = { version = "0.5", default-features = false } satrs = { version = "0.3.0-alpha.3", default-features = false, features = ["defmt"] } +fugit = "0.4" arbitrary-int = "2" ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] } # spacepackets = { version = "0.17", path = "https://egit.irs.uni-stuttgart.de/rust/spacepackets.git", default-features = false, features = ["defmt"] } diff --git a/va108xx/flashloader/src/main.rs b/va108xx/flashloader/src/main.rs index d087a1b..5776257 100644 --- a/va108xx/flashloader/src/main.rs +++ b/va108xx/flashloader/src/main.rs @@ -10,7 +10,8 @@ use ringbuf::{ traits::{Consumer, Observer, Producer}, StaticRb, }; -use va108xx_hal::prelude::*; +use rtic_monotonics::fugit::ExtU32; +use va108xx_hal::time::Hertz; const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000); @@ -64,7 +65,7 @@ mod app { use cortex_m::asm; use embedded_io::Write; use rtic::Mutex; - use rtic_monotonics::systick::prelude::*; + use rtic_monotonics::Monotonic; use satrs::pus::verification::{FailParams, VerificationReportCreator}; use satrs::spacepackets::ecss::PusServiceId; use satrs::spacepackets::ecss::{ @@ -106,7 +107,7 @@ mod app { fn init(cx: init::Context) -> (Shared, Local) { defmt::println!("-- Vorago flashloader --"); - Mono::start(cx.core.SYST, SYSCLK_FREQ.raw()); + Mono::start(cx.core.SYST, SYSCLK_FREQ.to_raw()); let dp = cx.device; let spi_clock_config = SpiClockConfig::new(2, 4); @@ -116,8 +117,11 @@ mod app { let tx = gpioa.pa9; let rx = gpioa.pa8; - let clock_config = - uart::ClockConfig::calculate(SYSCLK_FREQ, UART_BAUDRATE.Hz(), uart::BaudMode::_16); + let clock_config = uart::ClockConfig::calculate( + SYSCLK_FREQ, + fugit::HertzU32::from_raw(UART_BAUDRATE), + uart::BaudMode::_16, + ); let uart_config = uart::Config::new_with_clock_config(clock_config); let irq_uart = uart::Uart::new_with_interrupt_uart0( dp.uarta, @@ -254,7 +258,7 @@ mod app { let packet_len = cx.shared.tc_rb.lock(|rb| rb.sizes.try_pop()); if packet_len.is_none() { // Small delay, TCs might arrive very quickly. - Mono::delay(20.millis()).await; + Mono::delay(20_u32.millis()).await; continue; } let packet_len = packet_len.unwrap(); diff --git a/va108xx/va108xx-hal/Cargo.toml b/va108xx/va108xx-hal/Cargo.toml index 2ebd64d..1ab5d50 100644 --- a/va108xx/va108xx-hal/Cargo.toml +++ b/va108xx/va108xx-hal/Cargo.toml @@ -13,7 +13,7 @@ categories = ["aerospace", "embedded", "no-std", "hardware-support"] [dependencies] cortex-m = { version = "0.7", features = ["critical-section-single-core"]} vorago-shared-hal = { version = "0.2", path = "../../vorago-shared-hal", features = ["vor1x"] } -fugit = "0.3" +fugit = "0.4" thiserror = { version = "2", default-features = false } va108xx = { version = "0.6", path = "../va108xx", default-features = false, features = ["critical-section"] } defmt = { version = "1", optional = true } diff --git a/va416xx/examples/rtic/src/main.rs b/va416xx/examples/rtic/src/main.rs index 5e2e9d7..075155f 100644 --- a/va416xx/examples/rtic/src/main.rs +++ b/va416xx/examples/rtic/src/main.rs @@ -41,7 +41,7 @@ mod app { .xtal_n_clk_with_src_freq(EXTCLK_FREQ) .freeze() .unwrap(); - Mono::start(cx.core.SYST, clocks.sysclk().raw()); + Mono::start(cx.core.SYST, clocks.sysclk().to_raw()); let pinsg = PinsG::new(cx.device.portg); let led = Output::new(pinsg.pg5, PinState::Low); blinky::spawn().ok(); diff --git a/va416xx/examples/simple/src/bin/wdt.rs b/va416xx/examples/simple/src/bin/wdt.rs index 14bff07..e34e9c0 100644 --- a/va416xx/examples/simple/src/bin/wdt.rs +++ b/va416xx/examples/simple/src/bin/wdt.rs @@ -40,7 +40,7 @@ fn main() -> ! { .freeze() .unwrap(); enable_and_init_irq_router(); - let mut delay = cortex_m::delay::Delay::new(cp.SYST, clocks.apb0().raw()); + let mut delay = cortex_m::delay::Delay::new(cp.SYST, clocks.apb0().to_raw()); let mut last_interrupt_counter = 0; let mut wdt_ctrl = Wdt::start(dp.watch_dog, &clocks, WDT_ROLLOVER_MS); diff --git a/va416xx/flashloader/Cargo.toml b/va416xx/flashloader/Cargo.toml index d7a369e..d950009 100644 --- a/va416xx/flashloader/Cargo.toml +++ b/va416xx/flashloader/Cargo.toml @@ -10,6 +10,7 @@ defmt-rtt = "1" defmt = "1" panic-probe = { version = "1", features = ["defmt"] } static_cell = "2" +fugit = "0.4" ringbuf = { version = "0.4", default-features = false } once_cell = { version = "1", default-features = false, features = ["critical-section"] } satrs = { version = "0.3.0-alpha.3", default-features = false, features = ["defmt"] } diff --git a/va416xx/flashloader/src/main.rs b/va416xx/flashloader/src/main.rs index 4486fd7..191f847 100644 --- a/va416xx/flashloader/src/main.rs +++ b/va416xx/flashloader/src/main.rs @@ -97,12 +97,12 @@ mod app { use arbitrary_int::{u11, u14}; use cortex_m::asm; use embedded_io::Write; + use rtic_monotonics::{fugit::ExtU32, Monotonic}; // Import panic provider. use panic_probe as _; // Import logger. use defmt_rtt as _; use rtic::Mutex; - use rtic_monotonics::systick::prelude::*; use satrs::pus::verification::VerificationReportCreator; use satrs::spacepackets::ecss::PusServiceId; use satrs::spacepackets::ecss::{ @@ -116,7 +116,6 @@ mod app { nvm::Nvm, pac, pins::PinsG, - prelude::*, uart::{self, Uart}, }; @@ -171,7 +170,7 @@ mod app { let clock_config = uart::ClockConfig::calculate_with_clocks( uart::Bank::Uart0, &clocks, - UART_BAUDRATE.Hz(), + fugit::HertzU32::from_raw(UART_BAUDRATE), uart::BaudMode::_16, ); let uart_config = uart::Config::new_with_clock_config(clock_config); @@ -195,7 +194,7 @@ mod app { .init(StaticRb::::default()) .split_ref(); - Mono::start(cx.core.SYST, clocks.sysclk().raw()); + Mono::start(cx.core.SYST, clocks.sysclk().to_raw()); CLOCKS.set(clocks).unwrap(); let mut rx = rx.into_rx_with_irq(); diff --git a/va416xx/va416xx-hal/Cargo.toml b/va416xx/va416xx-hal/Cargo.toml index fc8179a..9e025bf 100644 --- a/va416xx/va416xx-hal/Cargo.toml +++ b/va416xx/va416xx-hal/Cargo.toml @@ -24,7 +24,7 @@ num_enum = { version = "0.7", default-features = false } bitflags = "2" bitbybit = "2" arbitrary-int = "2" -fugit = "0.3" +fugit = "0.4" embedded-can = "0.4" embassy-sync = "0.8" thiserror = { version = "2", default-features = false } diff --git a/va416xx/va416xx-hal/src/can/mod.rs b/va416xx/va416xx-hal/src/can/mod.rs index 1dcc0c7..065eba4 100644 --- a/va416xx/va416xx-hal/src/can/mod.rs +++ b/va416xx/va416xx-hal/src/can/mod.rs @@ -150,18 +150,19 @@ impl ClockConfig { tseg2: u8, sjw: u8, ) -> Result { - if bitrate.raw() == 0 { + if bitrate.to_raw() == 0 { return Err(ClockConfigError::BitrateIsZero); } let nominal_bit_time = 1 + tseg1 as u32 + tseg2 as u32; - let prescaler = - roundf(clocks.apb1().raw() as f32 / (bitrate.raw() as f32 * nominal_bit_time as f32)) - as u32; + let prescaler = roundf( + clocks.apb1().to_raw() as f32 / (bitrate.to_raw() as f32 * nominal_bit_time as f32), + ) as u32; if !(PRESCALER_MIN as u32..=PRESCALER_MAX as u32).contains(&prescaler) { return Err(ClockConfigError::CanNotFindPrescaler); } - let actual_bitrate = (clocks.apb1().raw() as f32) / (prescaler * nominal_bit_time) as f32; + let actual_bitrate = + (clocks.apb1().to_raw() as f32) / (prescaler * nominal_bit_time) as f32; let bitrate_deviation = calculate_bitrate_deviation(actual_bitrate, bitrate); if bitrate_deviation > MAX_BITRATE_DEVIATION { return Err(ClockConfigError::BitrateErrorTooLarge); @@ -269,17 +270,17 @@ pub const fn calculate_nominal_bit_time( target_bitrate: Hertz, prescaler: u8, ) -> u32 { - apb1_clock.raw() / (target_bitrate.raw() * prescaler as u32) + apb1_clock.to_raw() / (target_bitrate.to_raw() * prescaler as u32) } #[inline] pub const fn calculate_actual_bitrate(apb1_clock: Hertz, prescaler: u8, nom_bit_time: u32) -> f32 { - apb1_clock.raw() as f32 / (prescaler as u32 * nom_bit_time) as f32 + apb1_clock.to_raw() as f32 / (prescaler as u32 * nom_bit_time) as f32 } #[inline] pub const fn calculate_bitrate_deviation(actual_bitrate: f32, target_bitrate: Hertz) -> f32 { - (actual_bitrate - target_bitrate.raw() as f32).abs() / target_bitrate.raw() as f32 + (actual_bitrate - target_bitrate.to_raw() as f32).abs() / target_bitrate.to_raw() as f32 } pub trait CanInstance { diff --git a/va416xx/va416xx-hal/src/clock.rs b/va416xx/va416xx-hal/src/clock.rs index 5b1b6a6..8e37e04 100644 --- a/va416xx/va416xx-hal/src/clock.rs +++ b/va416xx/va416xx-hal/src/clock.rs @@ -94,9 +94,9 @@ pub struct PllConfig { pub const fn clock_after_division(clk: Hertz, div_sel: ClockDivisorSelect) -> Hertz { match div_sel { ClockDivisorSelect::Div1 => clk, - ClockDivisorSelect::Div2 => Hertz::from_raw(clk.raw() / 2), - ClockDivisorSelect::Div4 => Hertz::from_raw(clk.raw() / 4), - ClockDivisorSelect::Div8 => Hertz::from_raw(clk.raw() / 8), + ClockDivisorSelect::Div2 => Hertz::from_raw(clk.to_raw() / 2), + ClockDivisorSelect::Div4 => Hertz::from_raw(clk.to_raw() / 4), + ClockDivisorSelect::Div8 => Hertz::from_raw(clk.to_raw() / 8), } } @@ -382,7 +382,7 @@ impl ClockConfigurator { // ADC clock (must be 2-12.5 MHz) // NOTE: Not using divide by 1 or /2 ratio in REVA silicon because of triggering issue // For this reason, keep SYSCLK above 8MHz to have the ADC /4 ratio in range) - if final_sysclk.raw() <= ADC_MAX_CLK.raw() * 4 { + if final_sysclk.to_raw() <= ADC_MAX_CLK.to_raw() * 4 { self.clkgen.ctrl1().modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClockDivisorSelect::Div4 as u8) }); diff --git a/va416xx/va416xx-hal/src/wdt.rs b/va416xx/va416xx-hal/src/wdt.rs index 440c611..3fca8d6 100644 --- a/va416xx/va416xx-hal/src/wdt.rs +++ b/va416xx/va416xx-hal/src/wdt.rs @@ -58,7 +58,7 @@ impl Wdt { #[inline] pub fn set_freq(&mut self, freq_ms: u32) { - let counter = (self.clock_freq.raw() / 1000) * freq_ms; + let counter = (self.clock_freq.to_raw() / 1000) * freq_ms; self.wdt.wdogload().write(|w| unsafe { w.bits(counter) }); } diff --git a/vorago-shared-hal/CHANGELOG.md b/vorago-shared-hal/CHANGELOG.md index d03dfd6..5793d22 100644 --- a/vorago-shared-hal/CHANGELOG.md +++ b/vorago-shared-hal/CHANGELOG.md @@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Changed +- Bumped `fugit` from v0.3 to v0.4 - Added `RxWithInterrupt::steal`. - Renamed UART `Data` register `value` field to `data` - Improved type level support for resource management for SPI, PWM, UART. diff --git a/vorago-shared-hal/Cargo.toml b/vorago-shared-hal/Cargo.toml index fc37222..e377242 100644 --- a/vorago-shared-hal/Cargo.toml +++ b/vorago-shared-hal/Cargo.toml @@ -25,7 +25,7 @@ embedded-io-async = "0.7" raw-slicee = "0.1" thiserror = { version = "2", default-features = false } paste = "1" -fugit = "0.3" +fugit = "0.4" defmt = { version = "1", optional = true } va108xx = { version = "0.6", path = "../va108xx/va108xx", default-features = false, optional = true } va416xx = { version = "0.5", path = "../va416xx/va416xx", default-features = false, optional = true } diff --git a/vorago-shared-hal/src/embassy.rs b/vorago-shared-hal/src/embassy.rs index d948691..ca7af6d 100644 --- a/vorago-shared-hal/src/embassy.rs +++ b/vorago-shared-hal/src/embassy.rs @@ -79,7 +79,9 @@ impl TimerDriver { let mut timekeeper_reg_block = unsafe { TimekeeperTim::ID.steal_regs() }; let mut alarm_tim_reg_block = unsafe { AlarmTim::ID.steal_regs() }; // Initiate scale value here. This is required to convert timer ticks back to a timestamp. - SCALE.set((sysclk.raw() / TICK_HZ as u32) as u64).unwrap(); + SCALE + .set((sysclk.to_raw() / TICK_HZ as u32) as u64) + .unwrap(); timekeeper_reg_block.write_reset_value(u32::MAX); // Decrementing counter. timekeeper_reg_block.write_count_value(u32::MAX); @@ -137,7 +139,7 @@ impl TimerDriver { // Initiate scale value here. This is required to convert timer ticks back to a timestamp. SCALE - .set((TimekeeperTim::clock(clocks).raw() / TICK_HZ as u32) as u64) + .set((TimekeeperTim::clock(clocks).to_raw() / TICK_HZ as u32) as u64) .unwrap(); timekeeper_regs.write_reset_value(u32::MAX); // Decrementing counter. diff --git a/vorago-shared-hal/src/i2c/mod.rs b/vorago-shared-hal/src/i2c/mod.rs index 48805a0..f3a4c62 100644 --- a/vorago-shared-hal/src/i2c/mod.rs +++ b/vorago-shared-hal/src/i2c/mod.rs @@ -149,12 +149,12 @@ fn calc_clk_div_generic( speed_mode: I2cSpeed, ) -> Result { if speed_mode == I2cSpeed::Regular100khz { - Ok(((ref_clk.raw() / CLK_100K.raw() / 20) - 1) as u8) + Ok(((ref_clk.to_raw() / CLK_100K.to_raw() / 20) - 1) as u8) } else { - if ref_clk.raw() < MIN_CLK_400K.raw() { + if ref_clk.to_raw() < MIN_CLK_400K.to_raw() { return Err(ClockTooSlowForFastI2cError); } - Ok(((ref_clk.raw() / CLK_400K.raw() / 25) - 1) as u8) + Ok(((ref_clk.to_raw() / CLK_400K.to_raw() / 25) - 1) as u8) } } diff --git a/vorago-shared-hal/src/pwm.rs b/vorago-shared-hal/src/pwm.rs index c1ede12..01cb49c 100644 --- a/vorago-shared-hal/src/pwm.rs +++ b/vorago-shared-hal/src/pwm.rs @@ -164,10 +164,10 @@ impl PwmPin { pub fn set_period(&mut self, period: impl Into) { self.current_period = period.into(); // Avoid division by 0 - if self.current_period.raw() == 0 { + if self.current_period.to_raw() == 0 { return; } - self.current_rst_val = self.ref_clk.raw() / self.current_period.raw(); + self.current_rst_val = self.ref_clk.to_raw() / self.current_period.to_raw(); self.regs.write_reset_value(self.current_rst_val); } diff --git a/vorago-shared-hal/src/spi/mod.rs b/vorago-shared-hal/src/spi/mod.rs index 58ef440..cd76aca 100644 --- a/vorago-shared-hal/src/spi/mod.rs +++ b/vorago-shared-hal/src/spi/mod.rs @@ -499,11 +499,11 @@ pub fn clk_div_for_target_clock(sys_clk: Hertz, spi_clk: Hertz) -> Option { } // Step 1: Calculate raw divider. - let raw_div = sys_clk.raw() / spi_clk.raw(); - let remainder = sys_clk.raw() % spi_clk.raw(); + let raw_div = sys_clk.to_raw() / spi_clk.to_raw(); + let remainder = sys_clk.to_raw() % spi_clk.to_raw(); // Step 2: Round up if necessary. - let mut rounded_div = if remainder * 2 >= spi_clk.raw() { + let mut rounded_div = if remainder * 2 >= spi_clk.to_raw() { raw_div + 1 } else { raw_div diff --git a/vorago-shared-hal/src/timer/mod.rs b/vorago-shared-hal/src/timer/mod.rs index 7d0bb68..fe69582 100644 --- a/vorago-shared-hal/src/timer/mod.rs +++ b/vorago-shared-hal/src/timer/mod.rs @@ -406,7 +406,7 @@ impl CountdownTimer { pub fn load(&mut self, timeout: impl Into) { self.disable(); self.curr_freq = timeout.into(); - self.rst_val = self.ref_clk.raw() / self.curr_freq.raw(); + self.rst_val = self.ref_clk.to_raw() / self.curr_freq.to_raw(); self.set_reload(self.rst_val); self.set_count(self.rst_val); } @@ -497,7 +497,7 @@ impl CountdownTimer { // impl embedded_hal::delay::DelayNs for CountdownTimer { fn delay_ns(&mut self, ns: u32) { - let ticks = (u64::from(ns)) * (u64::from(self.ref_clk.raw())) / 1_000_000_000; + let ticks = (u64::from(ns)) * (u64::from(self.ref_clk.to_raw())) / 1_000_000_000; let full_cycles = ticks >> 32; let mut last_count; diff --git a/vorago-shared-hal/src/uart/mod.rs b/vorago-shared-hal/src/uart/mod.rs index 0fd6803..e6f1bd0 100644 --- a/vorago-shared-hal/src/uart/mod.rs +++ b/vorago-shared-hal/src/uart/mod.rs @@ -161,11 +161,11 @@ impl ClockConfig { // This is the calculation: (64.0 * (x - integer_part as f32) + 0.5) as u32 without floating // point calculations. let multiplier = baud_mode.multiplier(); - let frac = ((ref_clk.raw() % (baudrate.raw() * multiplier)) * 64 - + (baudrate.raw() * (multiplier / 2))) - / (baudrate.raw() * multiplier); + let frac = ((ref_clk.to_raw() % (baudrate.to_raw() * multiplier)) * 64 + + (baudrate.to_raw() * (multiplier / 2))) + / (baudrate.to_raw() * multiplier); // Calculations here are derived from chapter 4.8.5 (p.79) of the datasheet. - let integer_div = ref_clk.raw() / (baudrate.raw() * multiplier); + let integer_div = ref_clk.to_raw() / (baudrate.to_raw() * multiplier); Self { frac: u6::new(frac as u8), div: u18::new(integer_div), -- 2.43.0