vorago-rs/vorago-shared-hal/CHANGELOG.md

Change Log

All notable changes to this project will be documented in this file.

The format is based on Keep a Changelog and this project adheres to Semantic Versioning.

unreleased

Added

• Add is_high and is_low for InputPinAsync.
• Add InputPin impl for InputPinAsync.
• HwCsPin in SPI module for easer usage of HW CS pins as Output CS pins

Changed

• Added RxWithInterrupt::steal.
• Renamed UART Data register value field to data
• Improved type level support for resource management for SPI, PWM, UART.
• Renamed tx_asynch and rx_asynch module name to *_async
• Naming improvements in SPI module: replaced cfg by config*
• UART configuration now expects an explicit clock configuration structure and does not calculate it itself anymore.

Fixed

• Removed HW CS pin provider implementation for PA23, PA22 and PA21, which are multi HW CS pins.
• Added missing AnyPin trait impl for Multi HW CS pins.
• Expose inner Input pin for InputPinAsync.
• Bugfix for UART clock calculation with 8x baud mode.
• Possible bugfix for Asynch GPIO where the interrupt handler could become stuck in a loop.
• Robustness improvements for the Asynch GPIO driver code.

v0.2.0 2025-09-03

Renamed to vorago-shared-hal

Changed

• Various renaming to be more in-line with common Embedded Rust naming conventions.
  • PinId -> DynPinId
  • PinIdProvider -> PinId
  • FunSel -> FunctionSelect
  • PinMarker -> AnyPin
  • Peripheral traits renamed from *Marker to *Instance
  • Clk abbreviation in names changed to Clock
  • Cmd abbreviation in names changed to Command
  • Irq abbreviation in names changed to Interrupt

v0.1.0 2025-09-02

Init commit.