Robin Mueller
15fed28281
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592 lines
20 KiB
Rust
592 lines
20 KiB
Rust
pub mod regs;
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use core::convert::Infallible;
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#[cfg(feature = "vor1x")]
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pub use crate::InterruptConfig;
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#[cfg(feature = "vor1x")]
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use crate::sysconfig::enable_peripheral_clock;
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pub use regs::{CascadeSource, InvalidTimerIndex, TimId};
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use crate::{enable_nvic_interrupt, sealed::Sealed, time::Hertz};
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use crate::{gpio::DynPinId, ioconfig::regs::FunctionSelect, pins::AnyPin};
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use fugit::RateExtU32;
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#[cfg(feature = "vor1x")]
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use crate::PeripheralSelect;
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#[cfg(feature = "vor1x")]
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use va108xx as pac;
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#[cfg(feature = "vor4x")]
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use va416xx as pac;
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#[cfg(feature = "vor4x")]
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pub const TIM_IRQ_OFFSET: usize = 48;
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//==================================================================================================
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// Defintions
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//==================================================================================================
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#[derive(Default, Debug, PartialEq, Eq, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct CascadeControl {
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/// Enable Cascade 0 signal active as a requirement for counting
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pub enable_src_0: bool,
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/// Invert Cascade 0, making it active low
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pub inv_src_0: regs::CascadeInvert,
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/// Enable Cascade 1 signal active as a requirement for counting
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pub enable_src_1: bool,
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/// Invert Cascade 1, making it active low
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pub inv_src_1: regs::CascadeInvert,
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/// Specify required operation if both Cascade 0 and Cascade 1 are active.
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/// 0 is a logical AND of both cascade signals, 1 is a logical OR
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pub dual_operation: regs::DualCascadeOp,
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/// Enable trigger mode for Cascade 0. In trigger mode, couting will start with the selected
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/// cascade signal active, but once the counter is active, cascade control will be ignored
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pub trigger_mode_0: bool,
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/// Trigger mode, identical to [Self::trigger_mode_0] but for Cascade 1
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pub trigger_mode_1: bool,
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/// Enable Cascade 2 signal active as a requirement to stop counting. This mode is similar
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/// to the REQ_STOP control bit, but signalled by a Cascade source
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pub enable_stop_src_2: bool,
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/// Invert Cascade 2, making it active low
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pub inv_src_2: regs::CascadeInvert,
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/// The counter is automatically disabled if the corresponding Cascade 2 level-sensitive input
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/// souce is active when the count reaches 0. If the counter is not 0, the cascade control is
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/// ignored
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pub trigger_mode_2: bool,
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}
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum CascadeSelect {
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Csd0 = 0,
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Csd1 = 1,
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Csd2 = 2,
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}
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//==================================================================================================
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// Valid TIM and PIN combinations
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//==================================================================================================
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macro_rules! define_tim_pin_traits {
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([$(($tim_name:ident, $index:expr)),* $(,)?]) => {
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$(
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pub trait $tim_name: AnyPin {
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const PIN_ID: DynPinId;
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const FUNC_SEL: FunctionSelect;
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const TIM_ID: TimId = TimId::new_unchecked($index);
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}
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)*
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};
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}
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define_tim_pin_traits!([
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(Tim0Pin, 0),
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(Tim1Pin, 1),
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(Tim2Pin, 2),
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(Tim3Pin, 3),
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(Tim4Pin, 4),
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(Tim5Pin, 5),
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(Tim6Pin, 6),
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(Tim7Pin, 7),
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(Tim8Pin, 8),
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(Tim9Pin, 9),
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(Tim10Pin, 10),
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(Tim11Pin, 11),
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(Tim12Pin, 12),
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(Tim13Pin, 13),
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(Tim14Pin, 14),
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(Tim15Pin, 15),
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(Tim16Pin, 16),
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(Tim17Pin, 17),
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(Tim18Pin, 18),
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(Tim19Pin, 19),
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(Tim20Pin, 20),
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(Tim21Pin, 21),
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(Tim22Pin, 22),
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(Tim23Pin, 23),
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]);
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pub trait TimInstance: Sealed {
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const ID: TimId;
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#[cfg(feature = "vor4x")]
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const IRQ: va416xx::Interrupt;
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#[cfg(feature = "vor4x")]
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fn clock(clocks: &crate::clock::Clocks) -> Hertz {
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if Self::ID.value() < 16 {
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clocks.apb1()
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} else {
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clocks.apb2()
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}
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}
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}
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pub trait Tim0Instance: TimInstance {}
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pub trait Tim1Instance: TimInstance {}
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pub trait Tim2Instance: TimInstance {}
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pub trait Tim3Instance: TimInstance {}
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pub trait Tim4Instance: TimInstance {}
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pub trait Tim5Instance: TimInstance {}
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pub trait Tim6Instance: TimInstance {}
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pub trait Tim7Instance: TimInstance {}
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pub trait Tim8Instance: TimInstance {}
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pub trait Tim9Instance: TimInstance {}
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pub trait Tim10Instance: TimInstance {}
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pub trait Tim11Instance: TimInstance {}
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pub trait Tim12Instance: TimInstance {}
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pub trait Tim13Instance: TimInstance {}
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pub trait Tim14Instance: TimInstance {}
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pub trait Tim15Instance: TimInstance {}
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pub trait Tim16Instance: TimInstance {}
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pub trait Tim17Instance: TimInstance {}
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pub trait Tim18Instance: TimInstance {}
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pub trait Tim19Instance: TimInstance {}
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pub trait Tim20Instance: TimInstance {}
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pub trait Tim21Instance: TimInstance {}
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pub trait Tim22Instance: TimInstance {}
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pub trait Tim23Instance: TimInstance {}
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macro_rules! tim_marker {
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($TIMX:path, $Trait:ident, $ID:expr) => {
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impl Sealed for $TIMX {}
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impl TimInstance for $TIMX {
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const ID: TimId = TimId::new_unchecked($ID);
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}
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impl $Trait for $TIMX {}
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};
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($TIMX:path, $Trait:ident, $ID:expr, $IrqId:ident) => {
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impl Sealed for $TIMX {}
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impl TimInstance for $TIMX {
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const ID: TimId = TimId::new_unchecked($ID);
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const IRQ: va416xx::Interrupt = va416xx::Interrupt::$IrqId;
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}
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impl $Trait for $TIMX {}
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};
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}
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cfg_if::cfg_if! {
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if #[cfg(feature = "vor1x")] {
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tim_marker!(pac::Tim0, Tim0Instance, 0);
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tim_marker!(pac::Tim1, Tim1Instance, 1);
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tim_marker!(pac::Tim2, Tim2Instance, 2);
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tim_marker!(pac::Tim3, Tim3Instance, 3);
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tim_marker!(pac::Tim4, Tim4Instance, 4);
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tim_marker!(pac::Tim5, Tim5Instance, 5);
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tim_marker!(pac::Tim6, Tim6Instance, 6);
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tim_marker!(pac::Tim7, Tim7Instance, 7);
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tim_marker!(pac::Tim8, Tim8Instance, 8);
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tim_marker!(pac::Tim9, Tim9Instance, 9);
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tim_marker!(pac::Tim10, Tim10Instance, 10);
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tim_marker!(pac::Tim11, Tim11Instance, 11);
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tim_marker!(pac::Tim12, Tim12Instance, 12);
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tim_marker!(pac::Tim13, Tim13Instance, 13);
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tim_marker!(pac::Tim14, Tim14Instance, 14);
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tim_marker!(pac::Tim15, Tim15Instance, 15);
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tim_marker!(pac::Tim16, Tim16Instance, 16);
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tim_marker!(pac::Tim17, Tim17Instance, 17);
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tim_marker!(pac::Tim18, Tim18Instance, 18);
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tim_marker!(pac::Tim19, Tim19Instance, 19);
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tim_marker!(pac::Tim20, Tim20Instance, 20);
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tim_marker!(pac::Tim21, Tim21Instance, 21);
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tim_marker!(pac::Tim22, Tim22Instance, 22);
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tim_marker!(pac::Tim23, Tim23Instance, 23);
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} else if #[cfg(feature = "vor4x")] {
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tim_marker!(pac::Tim0, Tim0Instance, 0, TIM0);
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tim_marker!(pac::Tim1, Tim1Instance, 1, TIM1);
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tim_marker!(pac::Tim2, Tim2Instance, 2, TIM2);
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tim_marker!(pac::Tim3, Tim3Instance, 3, TIM3);
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tim_marker!(pac::Tim4, Tim4Instance, 4, TIM4);
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tim_marker!(pac::Tim5, Tim5Instance, 5, TIM5);
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tim_marker!(pac::Tim6, Tim6Instance, 6, TIM6);
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tim_marker!(pac::Tim7, Tim7Instance, 7, TIM7);
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tim_marker!(pac::Tim8, Tim8Instance, 8, TIM8);
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tim_marker!(pac::Tim9, Tim9Instance, 9, TIM9);
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tim_marker!(pac::Tim10, Tim10Instance, 10, TIM10);
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tim_marker!(pac::Tim11, Tim11Instance, 11, TIM11);
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tim_marker!(pac::Tim12, Tim12Instance, 12, TIM12);
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tim_marker!(pac::Tim13, Tim13Instance, 13, TIM13);
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tim_marker!(pac::Tim14, Tim14Instance, 14, TIM14);
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tim_marker!(pac::Tim15, Tim15Instance, 15, TIM15);
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tim_marker!(pac::Tim16, Tim16Instance, 16, TIM16);
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tim_marker!(pac::Tim17, Tim17Instance, 17, TIM17);
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tim_marker!(pac::Tim18, Tim18Instance, 18, TIM18);
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tim_marker!(pac::Tim19, Tim19Instance, 19, TIM19);
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tim_marker!(pac::Tim20, Tim20Instance, 20, TIM20);
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tim_marker!(pac::Tim21, Tim21Instance, 21, TIM21);
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tim_marker!(pac::Tim22, Tim22Instance, 22, TIM22);
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tim_marker!(pac::Tim23, Tim23Instance, 23, TIM23);
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}
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}
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pub trait ValidTimAndPin0<Pin: Tim0Pin, Tim: Tim0Instance>: Sealed {}
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pub trait ValidTimAndPin1<Pin: Tim1Pin, Tim: Tim1Instance>: Sealed {}
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pub trait ValidTimAndPin2<Pin: Tim2Pin, Tim: Tim2Instance>: Sealed {}
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pub trait ValidTimAndPin3<Pin: Tim3Pin, Tim: Tim3Instance>: Sealed {}
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pub trait ValidTimAndPin4<Pin: Tim4Pin, Tim: Tim4Instance>: Sealed {}
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pub trait ValidTimAndPin5<Pin: Tim5Pin, Tim: Tim5Instance>: Sealed {}
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pub trait ValidTimAndPin6<Pin: Tim6Pin, Tim: Tim6Instance>: Sealed {}
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pub trait ValidTimAndPin7<Pin: Tim7Pin, Tim: Tim7Instance>: Sealed {}
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pub trait ValidTimAndPin8<Pin: Tim8Pin, Tim: Tim8Instance>: Sealed {}
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pub trait ValidTimAndPin9<Pin: Tim9Pin, Tim: Tim9Instance>: Sealed {}
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pub trait ValidTimAndPin10<Pin: Tim10Pin, Tim: Tim10Instance>: Sealed {}
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pub trait ValidTimAndPin11<Pin: Tim11Pin, Tim: Tim11Instance>: Sealed {}
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pub trait ValidTimAndPin12<Pin: Tim12Pin, Tim: Tim12Instance>: Sealed {}
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pub trait ValidTimAndPin13<Pin: Tim13Pin, Tim: Tim13Instance>: Sealed {}
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pub trait ValidTimAndPin14<Pin: Tim14Pin, Tim: Tim14Instance>: Sealed {}
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pub trait ValidTimAndPin15<Pin: Tim15Pin, Tim: Tim15Instance>: Sealed {}
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pub trait ValidTimAndPin16<Pin: Tim16Pin, Tim: Tim16Instance>: Sealed {}
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pub trait ValidTimAndPin17<Pin: Tim17Pin, Tim: Tim17Instance>: Sealed {}
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pub trait ValidTimAndPin18<Pin: Tim18Pin, Tim: Tim18Instance>: Sealed {}
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pub trait ValidTimAndPin19<Pin: Tim19Pin, Tim: Tim19Instance>: Sealed {}
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pub trait ValidTimAndPin20<Pin: Tim20Pin, Tim: Tim20Instance>: Sealed {}
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pub trait ValidTimAndPin21<Pin: Tim21Pin, Tim: Tim21Instance>: Sealed {}
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pub trait ValidTimAndPin22<Pin: Tim22Pin, Tim: Tim22Instance>: Sealed {}
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pub trait ValidTimAndPin23<Pin: Tim23Pin, Tim: Tim23Instance>: Sealed {}
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#[macro_use]
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mod macros {
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macro_rules! pin_and_tim {
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($Px:ident, $FunSel:path, $ID:expr) => {
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paste::paste! {
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impl [<Tim $ID Pin>] for crate::pins::Pin<$Px>
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where
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$Px: crate::pins::PinId,
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{
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const PIN_ID: crate::pins::DynPinId = $Px::ID;
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const FUNC_SEL: crate::FunctionSelect = $FunSel;
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const TIM_ID: crate::timer::TimId = crate::timer::TimId::new_unchecked($ID);
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}
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}
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};
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}
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}
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#[cfg(feature = "vor1x")]
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pub mod pins_vor1x;
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#[cfg(feature = "vor4x")]
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pub mod pins_vor4x;
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//==================================================================================================
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// Timers
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//==================================================================================================
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/// Hardware timers
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pub struct CountdownTimer {
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id: TimId,
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regs: regs::MmioTimer<'static>,
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curr_freq: Hertz,
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ref_clk: Hertz,
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rst_val: u32,
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last_cnt: u32,
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}
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impl CountdownTimer {
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/// Create a countdown timer structure for a given TIM peripheral.
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///
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/// This does not enable the timer. You can use the [Self::load], [Self::start],
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/// [Self::enable_interrupt] and [Self::enable] API to set up and configure the countdown
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/// timer.
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#[cfg(feature = "vor1x")]
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pub fn new<Tim: TimInstance>(_tim: Tim, sys_clk: Hertz) -> Self {
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enable_tim_clk(Tim::ID);
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assert_tim_reset_for_cycles(Tim::ID, 2);
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CountdownTimer {
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id: Tim::ID,
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regs: regs::Timer::new_mmio(Tim::ID),
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ref_clk: sys_clk,
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rst_val: 0,
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curr_freq: 0.Hz(),
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last_cnt: 0,
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}
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}
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/// Create a countdown timer structure for a given TIM peripheral.
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///
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/// This does not enable the timer. You can use the [Self::load], [Self::start],
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/// [Self::enable_interrupt] and [Self::enable] API to set up and configure the countdown
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/// timer.
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#[cfg(feature = "vor4x")]
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pub fn new<Tim: TimInstance>(_tim: Tim, clks: &crate::clock::Clocks) -> Self {
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enable_tim_clk(Tim::ID);
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assert_tim_reset_for_cycles(Tim::ID, 2);
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CountdownTimer {
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id: Tim::ID,
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regs: regs::Timer::new_mmio(Tim::ID),
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ref_clk: clks.apb1(),
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rst_val: 0,
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curr_freq: 0.Hz(),
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last_cnt: 0,
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}
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}
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#[inline]
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pub fn perid(&self) -> u32 {
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self.regs.read_perid()
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}
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#[inline(always)]
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pub fn enable(&mut self) {
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self.regs
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.write_enable_control(regs::EnableControl::new_enable());
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}
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#[inline(always)]
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pub fn disable(&mut self) {
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self.regs
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.write_enable_control(regs::EnableControl::new_disable());
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}
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#[cfg(feature = "vor1x")]
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pub fn enable_interrupt(&mut self, irq_cfg: InterruptConfig) {
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if irq_cfg.route {
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let irqsel = unsafe { pac::Irqsel::steal() };
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enable_peripheral_clock(PeripheralSelect::Irqsel);
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irqsel
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.tim(self.id.value() as usize)
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.write(|w| unsafe { w.bits(irq_cfg.id as u32) });
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}
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if irq_cfg.enable_in_nvic {
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unsafe { enable_nvic_interrupt(irq_cfg.id) };
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}
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self.regs.modify_control(|mut value| {
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value.set_irq_enable(true);
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value
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});
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}
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#[cfg(feature = "vor4x")]
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#[inline(always)]
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pub fn enable_interrupt(&mut self, enable_in_nvic: bool) {
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if enable_in_nvic {
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unsafe { enable_nvic_interrupt(self.id.interrupt_id()) };
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}
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self.regs.modify_control(|mut value| {
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value.set_irq_enable(true);
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value
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});
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}
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/// This function only clears the interrupt enable bit.
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///
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/// It does not mask the interrupt in the NVIC or un-route the IRQ.
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#[inline(always)]
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pub fn disable_interrupt(&mut self) {
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self.regs.modify_control(|mut value| {
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value.set_irq_enable(false);
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value
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});
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}
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/// Calls [Self::load] to configure the specified frequency and then calls [Self::enable].
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pub fn start(&mut self, frequency: impl Into<Hertz>) {
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self.load(frequency);
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self.enable();
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}
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/// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the
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/// flag and restart the time if configured correctly
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pub fn wait(&mut self) -> nb::Result<(), Infallible> {
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let cnt = self.counter();
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if (cnt > self.last_cnt) || cnt == 0 {
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self.last_cnt = self.rst_val;
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Ok(())
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} else {
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self.last_cnt = cnt;
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Err(nb::Error::WouldBlock)
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}
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}
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/// Load the count down timer with a timeout but do not start it.
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pub fn load(&mut self, timeout: impl Into<Hertz>) {
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self.disable();
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self.curr_freq = timeout.into();
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self.rst_val = self.ref_clk.to_raw() / self.curr_freq.to_raw();
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self.set_reload(self.rst_val);
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self.set_count(self.rst_val);
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}
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#[inline(always)]
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pub fn set_reload(&mut self, val: u32) {
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self.regs.write_reset_value(val);
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}
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#[inline(always)]
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pub fn set_count(&mut self, val: u32) {
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self.regs.write_count_value(val);
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}
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#[inline(always)]
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pub fn counter(&self) -> u32 {
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self.regs.read_count_value()
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}
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/// Disable the counter, setting both enable and active bit to 0
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#[inline]
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pub fn auto_disable(&mut self, enable: bool) {
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self.regs.modify_control(|mut value| {
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value.set_auto_disable(enable);
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value
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});
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}
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|
|
/// This option only applies when the Auto-Disable functionality is 0.
|
|
///
|
|
/// The active bit is changed to 0 when count reaches 0, but the counter stays
|
|
/// enabled. When Auto-Disable is 1, Auto-Deactivate is implied
|
|
#[inline]
|
|
pub fn auto_deactivate(&mut self, enable: bool) {
|
|
self.regs.modify_control(|mut value| {
|
|
value.set_auto_deactivate(enable);
|
|
value
|
|
});
|
|
}
|
|
|
|
/// Configure the cascade parameters
|
|
pub fn cascade_control(&mut self, ctrl: CascadeControl) {
|
|
self.regs.write_cascade_control(
|
|
regs::CascadeControl::builder()
|
|
.with_trigger2(ctrl.trigger_mode_2)
|
|
.with_inv2(ctrl.inv_src_2)
|
|
.with_en2(ctrl.enable_stop_src_2)
|
|
.with_trigger1(ctrl.trigger_mode_1)
|
|
.with_trigger0(ctrl.trigger_mode_0)
|
|
.with_dual_cascade_op(ctrl.dual_operation)
|
|
.with_inv1(ctrl.inv_src_1)
|
|
.with_en1(ctrl.enable_src_1)
|
|
.with_inv0(ctrl.inv_src_0)
|
|
.with_en0(ctrl.enable_src_0)
|
|
.build(),
|
|
);
|
|
}
|
|
|
|
pub fn cascade_source(
|
|
&mut self,
|
|
cascade_index: CascadeSelect,
|
|
src: regs::CascadeSource,
|
|
) -> Result<(), regs::InvalidCascadeSourceId> {
|
|
// Safety: Index range safe by enum values.
|
|
unsafe {
|
|
self.regs
|
|
.write_cascade_unchecked(cascade_index as usize, regs::CascadeSourceReg::new(src)?);
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
pub fn curr_freq(&self) -> Hertz {
|
|
self.curr_freq
|
|
}
|
|
|
|
/// Disables the TIM and the dedicated TIM clock.
|
|
pub fn stop_with_clock_disable(mut self) {
|
|
self.disable();
|
|
unsafe { pac::Sysconfig::steal() }
|
|
.tim_clk_enable()
|
|
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.id.value())) });
|
|
}
|
|
}
|
|
|
|
//==================================================================================================
|
|
// Delay implementations
|
|
//==================================================================================================
|
|
//
|
|
impl embedded_hal::delay::DelayNs for CountdownTimer {
|
|
fn delay_ns(&mut self, ns: u32) {
|
|
let ticks = (u64::from(ns)) * (u64::from(self.ref_clk.to_raw())) / 1_000_000_000;
|
|
|
|
let full_cycles = ticks >> 32;
|
|
let mut last_count;
|
|
let mut new_count;
|
|
if full_cycles > 0 {
|
|
self.set_reload(u32::MAX);
|
|
self.set_count(u32::MAX);
|
|
self.enable();
|
|
|
|
for _ in 0..full_cycles {
|
|
// Always ensure that both values are the same at the start.
|
|
new_count = self.counter();
|
|
last_count = new_count;
|
|
loop {
|
|
new_count = self.counter();
|
|
if new_count == 0 {
|
|
// Wait till timer has wrapped.
|
|
while self.counter() == 0 {
|
|
cortex_m::asm::nop()
|
|
}
|
|
break;
|
|
}
|
|
// Timer has definitely wrapped.
|
|
if new_count > last_count {
|
|
break;
|
|
}
|
|
last_count = new_count;
|
|
}
|
|
}
|
|
}
|
|
let ticks = (ticks & u32::MAX as u64) as u32;
|
|
self.disable();
|
|
if ticks > 1 {
|
|
self.set_reload(ticks);
|
|
self.set_count(ticks);
|
|
self.enable();
|
|
last_count = ticks;
|
|
|
|
loop {
|
|
new_count = self.counter();
|
|
if new_count == 0 || (new_count > last_count) {
|
|
break;
|
|
}
|
|
last_count = new_count;
|
|
}
|
|
}
|
|
|
|
self.disable();
|
|
}
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn enable_tim_clk(id: TimId) {
|
|
unsafe { pac::Sysconfig::steal() }
|
|
.tim_clk_enable()
|
|
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << id.value())) });
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn disable_tim_clk(id: TimId) {
|
|
unsafe { pac::Sysconfig::steal() }
|
|
.tim_clk_enable()
|
|
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << (id.value()))) });
|
|
}
|
|
|
|
/// Clear the reset bit of the TIM, holding it in reset
|
|
///
|
|
/// # Safety
|
|
///
|
|
/// Only the bit related to the corresponding TIM peripheral is modified
|
|
#[inline]
|
|
pub fn assert_tim_reset(id: TimId) {
|
|
unsafe { pac::Peripherals::steal() }
|
|
.sysconfig
|
|
.tim_reset()
|
|
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << id.value())) });
|
|
}
|
|
|
|
#[inline]
|
|
pub fn deassert_tim_reset(tim: TimId) {
|
|
unsafe { pac::Peripherals::steal() }
|
|
.sysconfig
|
|
.tim_reset()
|
|
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << tim.value())) });
|
|
}
|
|
|
|
pub fn assert_tim_reset_for_cycles(tim: TimId, cycles: u32) {
|
|
assert_tim_reset(tim);
|
|
cortex_m::asm::delay(cycles);
|
|
deassert_tim_reset(tim);
|
|
}
|