diff --git a/Cargo.toml b/Cargo.toml
index 9c816f4..40eeb0c 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -27,8 +27,8 @@ thiserror = { version = "2", default-features = false }
 paste = "1"
 fugit = "0.3"
 defmt = { version = "1", optional = true }
-va108xx = { version = "0.5", default-features = false, optional = true }
-va416xx = { version = "0.4", default-features = false, optional = true }
+va108xx = { version = "0.6", default-features = false, optional = true }
+va416xx = { version = ">=0.4, <=0.5", default-features = false, optional = true }
 embassy-sync = "0.7"
 embassy-time-driver = "0.2"
 embassy-time-queue-utils = "0.3"
diff --git a/src/embassy.rs b/src/embassy.rs
index a93a810..d948691 100644
--- a/src/embassy.rs
+++ b/src/embassy.rs
@@ -86,7 +86,7 @@ impl TimerDriver {
         let irqsel = unsafe { va108xx::Irqsel::steal() };
         // Switch on. Timekeeping should always be done.
         irqsel
-            .tim0(TimekeeperTim::ID.value() as usize)
+            .tim(TimekeeperTim::ID.value() as usize)
             .write(|w| unsafe { w.bits(timekeeper_irq as u32) });
         unsafe {
             enable_nvic_interrupt(timekeeper_irq);
@@ -111,7 +111,7 @@ impl TimerDriver {
             enable_nvic_interrupt(alarm_irq);
         }
         irqsel
-            .tim0(AlarmTim::ID.value() as usize)
+            .tim(AlarmTim::ID.value() as usize)
             .write(|w| unsafe { w.bits(alarm_irq as u32) });
     }
 
diff --git a/src/gpio/ll.rs b/src/gpio/ll.rs
index 810d787..0389cb2 100644
--- a/src/gpio/ll.rs
+++ b/src/gpio/ll.rs
@@ -546,12 +546,12 @@ impl LowLevelGpio {
             // Set the correct interrupt number in the IRQSEL register
             super::Port::A => {
                 irqsel
-                    .porta0(self.id().offset())
+                    .porta(self.id().offset())
                     .write(|w| unsafe { w.bits(id as u32) });
             }
             super::Port::B => {
                 irqsel
-                    .portb0(self.id().offset())
+                    .portb(self.id().offset())
                     .write(|w| unsafe { w.bits(id as u32) });
             }
         }
@@ -566,12 +566,12 @@ impl LowLevelGpio {
             // Set the correct interrupt number in the IRQSEL register
             super::Port::A => {
                 irqsel
-                    .porta0(self.id().offset())
+                    .porta(self.id().offset())
                     .write(|w| unsafe { w.bits(u32::MAX) });
             }
             super::Port::B => {
                 irqsel
-                    .portb0(self.id().offset())
+                    .portb(self.id().offset())
                     .write(|w| unsafe { w.bits(u32::MAX) });
             }
         }
diff --git a/src/timer/mod.rs b/src/timer/mod.rs
index d378b8c..31fe0a1 100644
--- a/src/timer/mod.rs
+++ b/src/timer/mod.rs
@@ -261,7 +261,7 @@ impl CountdownTimer {
             let irqsel = unsafe { pac::Irqsel::steal() };
             enable_peripheral_clock(PeripheralSelect::Irqsel);
             irqsel
-                .tim0(self.id.value() as usize)
+                .tim(self.id.value() as usize)
                 .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
         }
         if irq_cfg.enable_in_nvic {
diff --git a/src/uart/mod.rs b/src/uart/mod.rs
index 1a03761..2c606a3 100644
--- a/src/uart/mod.rs
+++ b/src/uart/mod.rs
@@ -529,7 +529,7 @@ impl Uart {
             if irq_cfg.route {
                 enable_peripheral_clock(PeripheralSelect::Irqsel);
                 unsafe { va108xx::Irqsel::steal() }
-                    .uart0(UartI::ID as usize)
+                    .uart(UartI::ID as usize)
                     .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
             }
             if irq_cfg.enable_in_nvic {