prepare first release

2025-09-02 20:22:39 +02:00
parent c972f17256
commit 5f11e94e24
8 changed files with 53 additions and 65 deletions
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -10,8 +10,8 @@ jobs:
      - uses: dtolnay/rust-toolchain@stable
        with:
          targets: "thumbv7em-none-eabihf, thumbv6m-none-eabi"
-      - run: cargo check --target thumbv7em-none-eabihf --features vor4x
-      - run: cargo check --target thumbv6m-none-eabi --features vor1x
+      - run: cargo check --target thumbv7em-none-eabihf --features "vor4x, defmt"
+      - run: cargo check --target thumbv6m-none-eabi --features "vor1x, defmt"

  fmt:
    name: Check formatting
@@ -29,8 +29,8 @@ jobs:
      - uses: dtolnay/rust-toolchain@nightly
        with:
          targets: "thumbv7em-none-eabihf, thumbv6m-none-eabi"
-      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --target thumbv7em-none-eabihf --features vor4x
-      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --target thumbv6m-none-eabi --features vor1x
+      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --target thumbv7em-none-eabihf --features "vor4x, defmt"
+      - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --target thumbv6m-none-eabi --features "vor1x, defmt"

  clippy:
    name: Clippy
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -8,11 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

 ## [unreleased]

-### Changed
-
- SPI `transfer` implemenation update to handle size missmatch between read and write.
-
-## [v0.1.0]
+## [v0.1.0] 2025-09-02

 Init commit.

--- a/Cargo.toml
+++ b/Cargo.toml
@@ -10,7 +10,7 @@ license = "Apache-2.0"
 [dependencies]
 cortex-m = { version = "0.7" }
 cfg-if = "1"
-derive-mmio = { git = "https://github.com/knurling-rs/derive-mmio.git",  version = "0.6" }
+derive-mmio = "0.6"
 bitbybit = "1.3"
 arbitrary-int = "2"
 static_assertions = "1.1"
@@ -32,7 +32,9 @@ va416xx = { version = "0.4", default-features = false, optional = true }
 embassy-sync = "0.7"
 embassy-time-driver = "0.2"
 embassy-time-queue-utils = "0.3"
-once_cell = { version = "1", default-features = false, features = ["critical-section"] }
+once_cell = { version = "1", default-features = false, features = [
+  "critical-section",
+] }

 [target.thumbv6m-none-eabi.dependencies]
 portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
@@ -45,9 +47,19 @@ portable-atomic = "1"
 vor1x = ["_family-selected", "dep:va108xx"]
 vor4x = ["_family-selected", "dep:va416xx"]
 va41628 = []
-defmt = ["dep:defmt", "arbitrary-int/defmt", "fugit/defmt", "embedded-hal/defmt-03"]
+defmt = [
+  "dep:defmt",
+  "arbitrary-int/defmt",
+  "fugit/defmt",
+  "embedded-hal/defmt-03",
+  "va108xx/defmt"
+]

 _family-selected = []

 [package.metadata.cargo-machete]
 ignored = ["raw-slicee"]
+
+[package.metadata.docs.rs]
+features = ["vor1x", "defmt"]
+rustdoc-args = ["--generate-link-to-definition"]
--- a/src/i2c/regs.rs
+++ b/src/i2c/regs.rs
@@ -60,8 +60,7 @@ pub enum RxFifoFullMode {
    Nack = 1,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
 pub struct Control {
    #[bit(0, r)]
    clk_enabled: bool,
@@ -93,8 +92,7 @@ pub enum I2cSpeed {
    Fast400khz = 1,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))]
 pub struct ClkScale {
    /// Clock divide value. Reset value: 0x18.
    #[bits(0..=7, rw)]
@@ -124,8 +122,7 @@ pub enum Direction {
    Receive = 1,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))]
 pub struct Address {
    #[bit(0, rw)]
    direction: Direction,
@@ -160,8 +157,7 @@ pub struct Command {
    cancel: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct Status {
    #[bit(0, r)]
    i2c_idle: bool,
@@ -195,8 +191,7 @@ pub struct Status {
    raw_scl: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct State {
    #[bits(0..=3, rw)]
    state: u4,
@@ -214,8 +209,7 @@ pub struct State {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct DataCount(arbitrary_int::UInt<u32, 11>);

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct InterruptControl {
    #[bit(0, rw)]
    i2c_idle: bool,
@@ -247,8 +241,7 @@ pub struct InterruptControl {
    rx_full: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct InterruptStatus {
    #[bit(0, r)]
    i2c_idle: bool,
@@ -398,8 +391,7 @@ pub mod slave {
        address: u10,
    }

-    #[bitbybit::bitfield(u32)]
-    #[derive(Debug)]
+    #[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
    pub struct Status {
        #[bit(0, r)]
        completed: bool,
@@ -450,8 +442,7 @@ pub mod slave {
        tx_fifo: u5,
    }

-    #[bitbybit::bitfield(u32)]
-    #[derive(Debug)]
+    #[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
    pub struct InterruptControl {
        #[bit(0, rw)]
        completed: bool,
@@ -488,8 +479,7 @@ pub mod slave {
        rx_full: bool,
    }

-    #[bitbybit::bitfield(u32)]
-    #[derive(Debug)]
+    #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
    pub struct InterruptStatus {
        #[bit(0, r)]
        completed: bool,
--- a/src/ioconfig/regs.rs
+++ b/src/ioconfig/regs.rs
@@ -10,6 +10,8 @@ pub const BASE_ADDR: usize = 0x4000_2000;
 pub const BASE_ADDR: usize = 0x4001_1000;

 #[bitbybit::bitenum(u3)]
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum FilterType {
    SysClk = 0,
    DirectInput = 1,
@@ -51,7 +53,7 @@ pub enum FunSel {
    Sel3 = 0b11,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
 pub struct Config {
    #[bit(16, rw)]
    io_disable: bool,
--- a/src/spi/regs.rs
+++ b/src/spi/regs.rs
@@ -67,8 +67,7 @@ pub enum HwChipSelectId {
    Id7 = 7,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))]
 pub struct Control0 {
    #[bits(8..=15, rw)]
    scrdv: u8,
@@ -80,8 +79,7 @@ pub struct Control0 {
    word_size: Option<WordSize>,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))]
 pub struct Control1 {
    #[bit(11, rw)]
    mtxpause: bool,
@@ -122,8 +120,7 @@ pub struct Data {
    data: u16,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct Status {
    /// TX FIFO below the trigger level.
    #[bit(7, r)]
@@ -160,8 +157,7 @@ impl ClkPrescaler {
    }
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct InterruptControl {
    /// TX FIFO count <= TX FIFO trigger level.
    #[bit(3, rw)]
@@ -178,8 +174,7 @@ pub struct InterruptControl {
    rx_overrun: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct InterruptStatus {
    /// TX FIFO count <= TX FIFO trigger level.
    #[bit(3, r)]
@@ -206,8 +201,7 @@ pub struct InterruptClear {
    rx_overrun: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct State {
    #[bits(0..=7, r)]
    rx_state: u8,
--- a/src/timer/regs.rs
+++ b/src/timer/regs.rs
@@ -9,6 +9,7 @@ const BASE_ADDR: usize = 0x4001_8000;

 #[bitbybit::bitenum(u3)]
 #[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum StatusSelect {
    /// Pulse when timer reaches 0.
    OneCyclePulse = 0b000,
@@ -25,7 +26,7 @@ pub enum StatusSelect {
    PwmaActiveBit = 0b110,
 }

-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
 pub struct Control {
    /// The counter is requested to stop on the next normal count cycle.
    #[bit(9, rw)]
@@ -50,6 +51,8 @@ pub struct Control {
    enable: bool,
 }

+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct EnableControl(arbitrary_int::UInt<u32, 1>);

 impl EnableControl {
@@ -85,7 +88,7 @@ pub enum DualCascadeOp {
    LogicalOr = 1,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))]
 pub struct CascadeControl {
    /// The counter is automatically disabled if the corresponding Cascade 2 level-sensitive input
    /// souce is active when the count reaches 0. If the counter is not 0, the cascade control is
--- a/src/uart/regs.rs
+++ b/src/uart/regs.rs
@@ -56,8 +56,7 @@ impl Bank {
    }
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct Data {
    #[bit(15, rw)]
    dparity: bool,
@@ -65,8 +64,7 @@ pub struct Data {
    value: u8,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))]
 pub struct Enable {
    #[bit(1, rw)]
    tx: bool,
@@ -92,8 +90,7 @@ pub enum WordSize {
    Eight = 0b11,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))]
 pub struct Control {
    #[bit(11, rw)]
    baud8: bool,
@@ -119,8 +116,7 @@ pub struct Control {
    parity_enable: bool,
 }

-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))]
 pub struct ClkScale {
    #[bits(6..=23, rw)]
    int: u18,
@@ -128,8 +124,7 @@ pub struct ClkScale {
    frac: u6,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct RxStatus {
    #[bit(15, r)]
    rx_rtsn: bool,
@@ -155,8 +150,7 @@ pub struct RxStatus {
    data_available: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct TxStatus {
    #[bit(15, r)]
    tx_ctsn: bool,
@@ -180,8 +174,7 @@ pub struct FifoClear {
    rx: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct InterruptControl {
    /// Generate an interrrupt when the RX FIFO is at least half-full (FIFO count >= trigger level)
    #[bit(0, rw)]
@@ -206,8 +199,7 @@ pub struct InterruptControl {
    tx_cts: bool,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct InterruptStatus {
    /// Generate an interrrupt when the RX FIFO is at least half-full (FIFO count >= trigger level)
    #[bit(0, r)]
@@ -250,8 +242,7 @@ pub struct FifoTrigger {
    level: u5,
 }

-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 pub struct State {
    #[bits(0..=7, r)]
    rx_state: u8,