init commit

src/spi/mod.rs

@@ -0,0 +1,952 @@
+use crate::FunSel;
+use crate::gpio::{IoPeriphPin, PinId};
+use crate::{
+    PeripheralSelect, enable_peripheral_clock, pins::PinMarker, sealed::Sealed, time::Hertz,
+};
+use core::{convert::Infallible, fmt::Debug, marker::PhantomData};
+use embedded_hal::spi::{MODE_0, Mode};
+
+use regs::{ClkPrescaler, Data, FifoClear, WordSize};
+#[cfg(feature = "vor1x")]
+use va108xx as pac;
+#[cfg(feature = "vor4x")]
+use va416xx as pac;
+
+pub use regs::{Bank, HwChipSelectId};
+
+pub mod regs;
+
+pub fn configure_pin_as_hw_cs_pin<P: PinMarker + HwCsProvider>(_pin: P) -> HwChipSelectId {
+    IoPeriphPin::new(P::ID, P::FUN_SEL, None);
+    P::CS_ID
+}
+
+//==================================================================================================
+// Pins and traits.
+//==================================================================================================
+
+pub trait PinSck: PinMarker {
+    const SPI_ID: Bank;
+    const FUN_SEL: FunSel;
+}
+
+pub trait PinMosi: PinMarker {
+    const SPI_ID: Bank;
+    const FUN_SEL: FunSel;
+}
+
+pub trait PinMiso: PinMarker {
+    const SPI_ID: Bank;
+    const FUN_SEL: FunSel;
+}
+
+pub trait HwCsProvider {
+    const PIN_ID: PinId;
+    const SPI_ID: Bank;
+    const FUN_SEL: FunSel;
+    const CS_ID: HwChipSelectId;
+}
+
+#[macro_use]
+mod macros {
+    #[cfg(not(feature = "va41628"))]
+    macro_rules! hw_cs_multi_pin {
+    (
+        // name of the newtype wrapper struct
+        $name:ident,
+        // Pb0
+        $pin_id:ident,
+        // SpiId::B
+        $spi_id:path,
+        // FunSel::Sel1
+        $fun_sel:path,
+        // HwChipSelectId::Id2
+        $cs_id:path
+    ) => {
+            #[doc = concat!(
+                "Newtype wrapper to use [Pin] [`", stringify!($pin_id), "`] as a HW CS pin for [`", stringify!($spi_id), "`] with [`", stringify!($cs_id), "`]."
+            )]
+            pub struct $name(Pin<$pin_id>);
+
+            impl $name {
+                pub fn new(pin: Pin<$pin_id>) -> Self {
+                    Self(pin)
+                }
+            }
+
+            impl crate::sealed::Sealed for $name {}
+
+            impl HwCsProvider for $name {
+                const PIN_ID: PinId = <$pin_id as PinIdProvider>::ID;
+                const SPI_ID: Bank = $spi_id;
+                const FUN_SEL: FunSel = $fun_sel;
+                const CS_ID: HwChipSelectId = $cs_id;
+            }
+        };
+    }
+
+    #[macro_export]
+    macro_rules! hw_cs_pins {
+        ($SpiId:path, $(($Px:ident, $FunSel:path, $HwCsIdent:path)$(,)?)+) => {
+            $(
+                impl HwCsProvider for Pin<$Px> {
+                    const PIN_ID: PinId = $Px::ID;
+                    const SPI_ID: Bank = $SpiId;
+                    const FUN_SEL: FunSel = $FunSel;
+                    const CS_ID: HwChipSelectId = $HwCsIdent;
+                }
+            )+
+        };
+    }
+}
+
+#[cfg(feature = "vor1x")]
+pub mod pins_vor1x;
+#[cfg(feature = "vor4x")]
+pub mod pins_vor4x;
+
+//==================================================================================================
+// Defintions
+//==================================================================================================
+
+// FIFO has a depth of 16.
+const FILL_DEPTH: usize = 12;
+
+pub const BMSTART_BMSTOP_MASK: u32 = 1 << 31;
+pub const BMSKIPDATA_MASK: u32 = 1 << 30;
+
+pub const DEFAULT_CLK_DIV: u16 = 2;
+
+/// Common trait implemented by all PAC peripheral access structures. The register block
+/// format is the same for all SPI blocks.
+pub trait SpiMarker: Sealed {
+    const ID: Bank;
+    const PERIPH_SEL: PeripheralSelect;
+}
+
+#[cfg(feature = "vor1x")]
+pub type Spi0 = pac::Spia;
+#[cfg(feature = "vor4x")]
+pub type Spi0 = pac::Spi0;
+
+impl SpiMarker for Spi0 {
+    const ID: Bank = Bank::Spi0;
+    const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi0;
+}
+impl Sealed for Spi0 {}
+
+#[cfg(feature = "vor1x")]
+pub type Spi1 = pac::Spib;
+#[cfg(feature = "vor4x")]
+pub type Spi1 = pac::Spi1;
+
+impl SpiMarker for Spi1 {
+    const ID: Bank = Bank::Spi1;
+    const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi1;
+}
+impl Sealed for Spi1 {}
+
+#[cfg(feature = "vor1x")]
+pub type Spi2 = pac::Spic;
+#[cfg(feature = "vor4x")]
+pub type Spi2 = pac::Spi2;
+
+impl SpiMarker for Spi2 {
+    const ID: Bank = Bank::Spi2;
+    const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi2;
+}
+impl Sealed for Spi2 {}
+
+#[cfg(feature = "vor4x")]
+impl SpiMarker for pac::Spi3 {
+    const ID: Bank = Bank::Spi3;
+    const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi3;
+}
+#[cfg(feature = "vor4x")]
+impl Sealed for pac::Spi3 {}
+
+//==================================================================================================
+// Config
+//==================================================================================================
+
+pub trait TransferConfigProvider {
+    fn sod(&mut self, sod: bool);
+    fn blockmode(&mut self, blockmode: bool);
+    fn mode(&mut self, mode: Mode);
+    fn clk_cfg(&mut self, clk_cfg: SpiClkConfig);
+    fn hw_cs_id(&self) -> u8;
+}
+
+/// Type erased variant of the transfer configuration. This is required to avoid generics in
+/// the SPI constructor.
+#[derive(Copy, Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct TransferConfig {
+    pub clk_cfg: Option<SpiClkConfig>,
+    pub mode: Option<Mode>,
+    pub sod: bool,
+    /// If this is enabled, all data in the FIFO is transmitted in a single frame unless
+    /// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
+    /// duration of multiple data words
+    pub blockmode: bool,
+    /// Only used when blockmode is used. The SCK will be stalled until an explicit stop bit
+    /// is set on a written word.
+    pub bmstall: bool,
+    pub hw_cs: Option<HwChipSelectId>,
+}
+
+impl TransferConfig {
+    pub fn new_with_hw_cs(
+        clk_cfg: Option<SpiClkConfig>,
+        mode: Option<Mode>,
+        blockmode: bool,
+        bmstall: bool,
+        sod: bool,
+        hw_cs_id: HwChipSelectId,
+    ) -> Self {
+        TransferConfig {
+            clk_cfg,
+            mode,
+            sod,
+            blockmode,
+            bmstall,
+            hw_cs: Some(hw_cs_id),
+        }
+    }
+}
+
+/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct SpiConfig {
+    clk: SpiClkConfig,
+    // SPI mode configuration
+    pub init_mode: Mode,
+    /// If this is enabled, all data in the FIFO is transmitted in a single frame unless
+    /// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
+    /// duration of multiple data words. Defaults to true.
+    pub blockmode: bool,
+    /// This enables the stalling of the SPI SCK if in blockmode and the FIFO is empty.
+    /// Currently enabled by default.
+    pub bmstall: bool,
+    /// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control
+    pub slave_output_disable: bool,
+    /// Loopback mode. If you use this, don't connect MISO to MOSI, they will be tied internally
+    pub loopback_mode: bool,
+    /// Enable Master Delayer Capture Mode. See Programmers Guide p.92 for more details
+    pub master_delayer_capture: bool,
+}
+
+impl Default for SpiConfig {
+    fn default() -> Self {
+        Self {
+            init_mode: MODE_0,
+            blockmode: true,
+            bmstall: true,
+            // Default value is definitely valid.
+            clk: SpiClkConfig::from_div(DEFAULT_CLK_DIV).unwrap(),
+            slave_output_disable: Default::default(),
+            loopback_mode: Default::default(),
+            master_delayer_capture: Default::default(),
+        }
+    }
+}
+
+impl SpiConfig {
+    pub fn loopback(mut self, enable: bool) -> Self {
+        self.loopback_mode = enable;
+        self
+    }
+
+    pub fn blockmode(mut self, enable: bool) -> Self {
+        self.blockmode = enable;
+        self
+    }
+
+    pub fn bmstall(mut self, enable: bool) -> Self {
+        self.bmstall = enable;
+        self
+    }
+
+    pub fn mode(mut self, mode: Mode) -> Self {
+        self.init_mode = mode;
+        self
+    }
+
+    pub fn clk_cfg(mut self, clk_cfg: SpiClkConfig) -> Self {
+        self.clk = clk_cfg;
+        self
+    }
+
+    pub fn slave_output_disable(mut self, sod: bool) -> Self {
+        self.slave_output_disable = sod;
+        self
+    }
+}
+
+//==================================================================================================
+// Word Size
+//==================================================================================================
+
+/// Configuration trait for the Word Size
+/// used by the SPI peripheral
+pub trait WordProvider: Copy + Default + Into<u32> + TryFrom<u32> + 'static {
+    const MASK: u32;
+    const WORD_SIZE: regs::WordSize;
+    fn word_reg() -> u8;
+}
+
+impl WordProvider for u8 {
+    const MASK: u32 = 0xff;
+    const WORD_SIZE: regs::WordSize = regs::WordSize::EightBits;
+    fn word_reg() -> u8 {
+        0x07
+    }
+}
+
+impl WordProvider for u16 {
+    const MASK: u32 = 0xffff;
+    const WORD_SIZE: regs::WordSize = regs::WordSize::SixteenBits;
+    fn word_reg() -> u8 {
+        0x0f
+    }
+}
+
+//==================================================================================================
+// Spi
+//==================================================================================================
+
+/// Low level access trait for the SPI peripheral.
+pub trait SpiLowLevel {
+    /// Low level function to write a word to the SPI FIFO but also checks whether
+    /// there is actually data in the FIFO.
+    ///
+    /// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
+    fn write_fifo(&mut self, data: u32) -> nb::Result<(), Infallible>;
+
+    /// Low level function to write a word to the SPI FIFO without checking whether
+    /// there FIFO is full.
+    ///
+    /// This does not necesarily mean there is a space in the FIFO available.
+    /// Use [Self::write_fifo] function to write a word into the FIFO reliably.
+    fn write_fifo_unchecked(&mut self, data: u32);
+
+    /// Low level function to read a word from the SPI FIFO. Must be preceeded by a
+    /// [Self::write_fifo] call.
+    ///
+    /// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
+    fn read_fifo(&mut self) -> nb::Result<u32, Infallible>;
+
+    /// Low level function to read a word from from the SPI FIFO.
+    ///
+    /// This does not necesarily mean there is a word in the FIFO available.
+    /// Use the [Self::read_fifo] function to read a word from the FIFO reliably using the [nb]
+    /// API.
+    /// You might also need to mask the value to ignore the BMSTART/BMSTOP bit.
+    fn read_fifo_unchecked(&mut self) -> u32;
+}
+
+#[inline(always)]
+pub fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) {
+    match mode {
+        embedded_hal::spi::MODE_0 => (false, false),
+        embedded_hal::spi::MODE_1 => (false, true),
+        embedded_hal::spi::MODE_2 => (true, false),
+        embedded_hal::spi::MODE_3 => (true, true),
+    }
+}
+
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct SpiClkConfig {
+    prescale_val: u8,
+    scrdv: u8,
+}
+
+impl SpiClkConfig {
+    pub fn prescale_val(&self) -> u8 {
+        self.prescale_val
+    }
+    pub fn scrdv(&self) -> u8 {
+        self.scrdv
+    }
+}
+
+impl SpiClkConfig {
+    pub fn new(prescale_val: u8, scrdv: u8) -> Self {
+        Self {
+            prescale_val,
+            scrdv,
+        }
+    }
+
+    pub fn from_div(div: u16) -> Result<Self, SpiClkConfigError> {
+        spi_clk_config_from_div(div)
+    }
+
+    #[cfg(feature = "vor1x")]
+    pub fn from_clk(sys_clk: Hertz, spi_clk: Hertz) -> Option<Self> {
+        clk_div_for_target_clock(sys_clk, spi_clk).map(|div| spi_clk_config_from_div(div).unwrap())
+    }
+
+    #[cfg(feature = "vor4x")]
+    pub fn from_clks(clks: &crate::clock::Clocks, spi_clk: Hertz) -> Option<Self> {
+        Self::from_apb1_clk(clks.apb1(), spi_clk)
+    }
+
+    #[cfg(feature = "vor4x")]
+    pub fn from_apb1_clk(apb1_clk: Hertz, spi_clk: Hertz) -> Option<Self> {
+        clk_div_for_target_clock(apb1_clk, spi_clk).map(|div| spi_clk_config_from_div(div).unwrap())
+    }
+}
+
+#[derive(Debug, thiserror::Error)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum SpiClkConfigError {
+    #[error("division by zero")]
+    DivIsZero,
+    #[error("divide value is not even")]
+    DivideValueNotEven,
+    #[error("scrdv value is too large")]
+    ScrdvValueTooLarge,
+}
+
+#[inline]
+pub fn spi_clk_config_from_div(mut div: u16) -> Result<SpiClkConfig, SpiClkConfigError> {
+    if div == 0 {
+        return Err(SpiClkConfigError::DivIsZero);
+    }
+    if div % 2 != 0 {
+        return Err(SpiClkConfigError::DivideValueNotEven);
+    }
+    let mut prescale_val = 0;
+
+    // find largest (even) prescale value that divides into div
+    for i in (2..=0xfe).rev().step_by(2) {
+        if div % i == 0 {
+            prescale_val = i;
+            break;
+        }
+    }
+
+    if prescale_val == 0 {
+        return Err(SpiClkConfigError::DivideValueNotEven);
+    }
+
+    div /= prescale_val;
+    if div > u8::MAX as u16 + 1 {
+        return Err(SpiClkConfigError::ScrdvValueTooLarge);
+    }
+    Ok(SpiClkConfig {
+        prescale_val: prescale_val as u8,
+        scrdv: (div - 1) as u8,
+    })
+}
+
+#[inline]
+pub fn clk_div_for_target_clock(sys_clk: Hertz, spi_clk: Hertz) -> Option<u16> {
+    if spi_clk > sys_clk {
+        return None;
+    }
+
+    // Step 1: Calculate raw divider.
+    let raw_div = sys_clk.raw() / spi_clk.raw();
+    let remainder = sys_clk.raw() % spi_clk.raw();
+
+    // Step 2: Round up if necessary.
+    let mut rounded_div = if remainder * 2 >= spi_clk.raw() {
+        raw_div + 1
+    } else {
+        raw_div
+    };
+
+    if rounded_div % 2 != 0 {
+        // Take slower clock conservatively.
+        rounded_div += 1;
+    }
+    if rounded_div > u16::MAX as u32 {
+        return None;
+    }
+    Some(rounded_div as u16)
+}
+
+#[derive(Debug, thiserror::Error)]
+#[error("peripheral or peripheral pin ID is not consistent")]
+pub struct SpiIdMissmatchError;
+
+/// SPI peripheral driver structure.
+pub struct Spi<Word = u8> {
+    id: Bank,
+    regs: regs::MmioSpi<'static>,
+    cfg: SpiConfig,
+    /// Fill word for read-only SPI transactions.
+    fill_word: Word,
+    blockmode: bool,
+    bmstall: bool,
+    word: PhantomData<Word>,
+}
+
+impl<Word: WordProvider> Spi<Word>
+where
+    <Word as TryFrom<u32>>::Error: core::fmt::Debug,
+{
+    /// Create a new SPI struct for using SPI with the fixed ROM SPI pins.
+    ///
+    /// ## Arguments
+    ///
+    /// * `spi` - SPI bus to use
+    /// * `spi_cfg` - Configuration specific to the SPI bus
+    pub fn new_for_rom<SpiI: SpiMarker>(
+        spi: SpiI,
+        spi_cfg: SpiConfig,
+    ) -> Result<Self, SpiIdMissmatchError> {
+        #[cfg(feature = "vor1x")]
+        if SpiI::ID != Bank::Spi2 {
+            return Err(SpiIdMissmatchError);
+        }
+        #[cfg(feature = "vor4x")]
+        if SpiI::ID != Bank::Spi3 {
+            return Err(SpiIdMissmatchError);
+        }
+        Ok(Self::new_generic(spi, spi_cfg))
+    }
+
+    /// Create a new SPI peripheral driver.
+    ///
+    /// ## Arguments
+    ///
+    /// * `spi` - SPI bus to use
+    /// * `pins` - Pins to be used for SPI transactions. These pins are consumed
+    ///   to ensure the pins can not be used for other purposes anymore
+    /// * `spi_cfg` - Configuration specific to the SPI bus
+    pub fn new<SpiI: SpiMarker, Sck: PinSck, Miso: PinMiso, Mosi: PinMosi>(
+        spi: SpiI,
+        _pins: (Sck, Miso, Mosi),
+        spi_cfg: SpiConfig,
+    ) -> Result<Self, SpiIdMissmatchError> {
+        if SpiI::ID != Sck::SPI_ID || SpiI::ID != Miso::SPI_ID || SpiI::ID != Mosi::SPI_ID {
+            return Err(SpiIdMissmatchError);
+        }
+        IoPeriphPin::new(Sck::ID, Sck::FUN_SEL, None);
+        IoPeriphPin::new(Miso::ID, Miso::FUN_SEL, None);
+        IoPeriphPin::new(Mosi::ID, Mosi::FUN_SEL, None);
+        Ok(Self::new_generic(spi, spi_cfg))
+    }
+
+    pub fn new_generic<SpiI: SpiMarker>(_spi: SpiI, spi_cfg: SpiConfig) -> Self {
+        enable_peripheral_clock(SpiI::PERIPH_SEL);
+        let mut regs = regs::Spi::new_mmio(SpiI::ID);
+        let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(spi_cfg.init_mode);
+        regs.write_ctrl0(
+            regs::Control0::builder()
+                .with_scrdv(spi_cfg.clk.scrdv)
+                .with_sph(cph_bit)
+                .with_spo(cpo_bit)
+                .with_word_size(Word::WORD_SIZE)
+                .build(),
+        );
+        regs.write_ctrl1(
+            regs::Control1::builder()
+                .with_mtxpause(false)
+                .with_mdlycap(spi_cfg.master_delayer_capture)
+                .with_bm_stall(spi_cfg.bmstall)
+                .with_bm_start(false)
+                .with_blockmode(spi_cfg.blockmode)
+                .with_ss(HwChipSelectId::Id0)
+                .with_sod(spi_cfg.slave_output_disable)
+                .with_slave_mode(false)
+                .with_enable(false)
+                .with_lbm(spi_cfg.loopback_mode)
+                .build(),
+        );
+        regs.write_clkprescale(ClkPrescaler::new(spi_cfg.clk.prescale_val));
+        regs.write_fifo_clear(
+            FifoClear::builder()
+                .with_tx_fifo(true)
+                .with_rx_fifo(true)
+                .build(),
+        );
+        // Enable the peripheral as the last step as recommended in the
+        // programmers guide
+        regs.modify_ctrl1(|mut value| {
+            value.set_enable(true);
+            value
+        });
+        Spi {
+            id: SpiI::ID,
+            regs: regs::Spi::new_mmio(SpiI::ID),
+            cfg: spi_cfg,
+            fill_word: Default::default(),
+            bmstall: spi_cfg.bmstall,
+            blockmode: spi_cfg.blockmode,
+            word: PhantomData,
+        }
+    }
+
+    #[inline]
+    pub fn cfg_clock(&mut self, cfg: SpiClkConfig) {
+        self.regs.modify_ctrl0(|mut value| {
+            value.set_scrdv(cfg.scrdv);
+            value
+        });
+        self.regs
+            .write_clkprescale(regs::ClkPrescaler::new(cfg.prescale_val));
+    }
+
+    pub fn set_fill_word(&mut self, fill_word: Word) {
+        self.fill_word = fill_word;
+    }
+
+    #[inline]
+    pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError> {
+        let val = spi_clk_config_from_div(div)?;
+        self.cfg_clock(val);
+        Ok(())
+    }
+
+    #[inline]
+    pub fn cfg_mode(&mut self, mode: Mode) {
+        let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(mode);
+        self.regs.modify_ctrl0(|mut value| {
+            value.set_spo(cpo_bit);
+            value.set_sph(cph_bit);
+            value
+        });
+    }
+
+    #[inline]
+    pub fn fill_word(&self) -> Word {
+        self.fill_word
+    }
+
+    #[inline]
+    pub fn clear_tx_fifo(&mut self) {
+        self.regs.write_fifo_clear(
+            regs::FifoClear::builder()
+                .with_tx_fifo(true)
+                .with_rx_fifo(false)
+                .build(),
+        );
+    }
+
+    #[inline]
+    pub fn clear_rx_fifo(&mut self) {
+        self.regs.write_fifo_clear(
+            regs::FifoClear::builder()
+                .with_tx_fifo(false)
+                .with_rx_fifo(true)
+                .build(),
+        );
+    }
+
+    #[inline]
+    pub fn perid(&self) -> u32 {
+        self.regs.read_perid()
+    }
+
+    /// Configure the hardware chip select given a hardware chip select ID.
+    ///
+    /// The pin also needs to be configured to be used as a HW CS pin. This can be done
+    /// by using the [configure_pin_as_hw_cs_pin] function which also returns the
+    /// corresponding [HwChipSelectId].
+    #[inline]
+    pub fn cfg_hw_cs(&mut self, hw_cs: HwChipSelectId) {
+        self.regs.modify_ctrl1(|mut value| {
+            value.set_sod(false);
+            value.set_ss(hw_cs);
+            value
+        });
+    }
+
+    /// Disables the hardware chip select functionality. This can be used when performing
+    /// external chip select handling, for example with GPIO pins.
+    #[inline]
+    pub fn cfg_hw_cs_disable(&mut self) {
+        self.regs.modify_ctrl1(|mut value| {
+            value.set_sod(true);
+            value
+        });
+    }
+
+    /// Utility function to configure all relevant transfer parameters in one go.
+    /// This is useful if multiple devices with different clock and mode configurations
+    /// are connected to one bus.
+    pub fn cfg_transfer(&mut self, transfer_cfg: &TransferConfig) {
+        if let Some(trans_clk_div) = transfer_cfg.clk_cfg {
+            self.cfg_clock(trans_clk_div);
+        }
+        if let Some(mode) = transfer_cfg.mode {
+            self.cfg_mode(mode);
+        }
+        self.blockmode = transfer_cfg.blockmode;
+        self.regs.modify_ctrl1(|mut value| {
+            if transfer_cfg.sod {
+                value.set_sod(transfer_cfg.sod);
+            } else {
+                value.set_sod(false);
+                if let Some(hw_cs) = transfer_cfg.hw_cs {
+                    value.set_ss(hw_cs);
+                }
+            }
+            value.set_blockmode(transfer_cfg.blockmode);
+            value.set_bm_stall(transfer_cfg.bmstall);
+            value
+        });
+    }
+
+    fn flush_internal(&mut self) {
+        let mut status_reg = self.regs.read_status();
+        while !status_reg.tx_empty() || status_reg.rx_not_empty() || status_reg.busy() {
+            if status_reg.rx_not_empty() {
+                self.read_fifo_unchecked();
+            }
+            status_reg = self.regs.read_status();
+        }
+    }
+
+    fn transfer_preparation(&mut self, words: &[Word]) -> Result<(), Infallible> {
+        if words.is_empty() {
+            return Ok(());
+        }
+        self.flush_internal();
+        Ok(())
+    }
+
+    // The FIFO can hold a guaranteed amount of data, so we can pump it on transfer
+    // initialization. Returns the amount of written bytes.
+    fn initial_send_fifo_pumping_with_words(&mut self, words: &[Word]) -> usize {
+        //let reg_block = self.reg_block();
+        if self.blockmode {
+            self.regs.modify_ctrl1(|mut value| {
+                value.set_mtxpause(true);
+                value
+            });
+        }
+        // Fill the first half of the write FIFO
+        let mut current_write_idx = 0;
+        let smaller_idx = core::cmp::min(FILL_DEPTH, words.len());
+        for _ in 0..smaller_idx {
+            if current_write_idx == smaller_idx.saturating_sub(1) && self.bmstall {
+                self.write_fifo_unchecked(words[current_write_idx].into() | BMSTART_BMSTOP_MASK);
+            } else {
+                self.write_fifo_unchecked(words[current_write_idx].into());
+            }
+            current_write_idx += 1;
+        }
+        if self.blockmode {
+            self.regs.modify_ctrl1(|mut value| {
+                value.set_mtxpause(false);
+                value
+            });
+        }
+        current_write_idx
+    }
+
+    // The FIFO can hold a guaranteed amount of data, so we can pump it on transfer
+    // initialization.
+    fn initial_send_fifo_pumping_with_fill_words(&mut self, send_len: usize) -> usize {
+        if self.blockmode {
+            self.regs.modify_ctrl1(|mut value| {
+                value.set_mtxpause(true);
+                value
+            });
+        }
+        // Fill the first half of the write FIFO
+        let mut current_write_idx = 0;
+        let smaller_idx = core::cmp::min(FILL_DEPTH, send_len);
+        for _ in 0..smaller_idx {
+            if current_write_idx == smaller_idx.saturating_sub(1) && self.bmstall {
+                self.write_fifo_unchecked(self.fill_word.into() | BMSTART_BMSTOP_MASK);
+            } else {
+                self.write_fifo_unchecked(self.fill_word.into());
+            }
+            current_write_idx += 1;
+        }
+        if self.blockmode {
+            self.regs.modify_ctrl1(|mut value| {
+                value.set_mtxpause(false);
+                value
+            });
+        }
+        current_write_idx
+    }
+}
+
+impl<Word: WordProvider> SpiLowLevel for Spi<Word>
+where
+    <Word as TryFrom<u32>>::Error: core::fmt::Debug,
+{
+    #[inline(always)]
+    fn write_fifo(&mut self, data: u32) -> nb::Result<(), Infallible> {
+        if !self.regs.read_status().tx_not_full() {
+            return Err(nb::Error::WouldBlock);
+        }
+        self.write_fifo_unchecked(data);
+        Ok(())
+    }
+
+    #[inline(always)]
+    fn write_fifo_unchecked(&mut self, data: u32) {
+        self.regs.write_data(Data::new_with_raw_value(data));
+    }
+
+    #[inline(always)]
+    fn read_fifo(&mut self) -> nb::Result<u32, Infallible> {
+        if !self.regs.read_status().rx_not_empty() {
+            return Err(nb::Error::WouldBlock);
+        }
+        Ok(self.read_fifo_unchecked())
+    }
+
+    #[inline(always)]
+    fn read_fifo_unchecked(&mut self) -> u32 {
+        self.regs.read_data().raw_value()
+    }
+}
+
+impl<Word: WordProvider> embedded_hal::spi::ErrorType for Spi<Word> {
+    type Error = Infallible;
+}
+
+impl<Word: WordProvider> embedded_hal::spi::SpiBus<Word> for Spi<Word>
+where
+    <Word as TryFrom<u32>>::Error: core::fmt::Debug,
+{
+    fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
+        self.transfer_preparation(words)?;
+        let mut current_read_idx = 0;
+        let mut current_write_idx = self.initial_send_fifo_pumping_with_fill_words(words.len());
+        loop {
+            if current_read_idx < words.len() {
+                words[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK)
+                    .try_into()
+                    .unwrap();
+                current_read_idx += 1;
+            }
+            if current_write_idx < words.len() {
+                if current_write_idx == words.len() - 1 && self.bmstall {
+                    nb::block!(self.write_fifo(self.fill_word.into() | BMSTART_BMSTOP_MASK))?;
+                } else {
+                    nb::block!(self.write_fifo(self.fill_word.into()))?;
+                }
+                current_write_idx += 1;
+            }
+            if current_read_idx >= words.len() && current_write_idx >= words.len() {
+                break;
+            }
+        }
+        Ok(())
+    }
+
+    fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
+        self.transfer_preparation(words)?;
+        let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
+        while current_write_idx < words.len() {
+            if current_write_idx == words.len() - 1 && self.bmstall {
+                nb::block!(self.write_fifo(words[current_write_idx].into() | BMSTART_BMSTOP_MASK))?;
+            } else {
+                nb::block!(self.write_fifo(words[current_write_idx].into()))?;
+            }
+            current_write_idx += 1;
+            // Ignore received words.
+            if self.regs.read_status().rx_not_empty() {
+                self.clear_rx_fifo();
+            }
+        }
+        Ok(())
+    }
+
+    fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
+        self.transfer_preparation(write)?;
+        let mut current_read_idx = 0;
+        let mut current_write_idx = self.initial_send_fifo_pumping_with_words(write);
+        while current_read_idx < read.len() || current_write_idx < write.len() {
+            if current_write_idx < write.len() {
+                if current_write_idx == write.len() - 1 && self.bmstall {
+                    nb::block!(
+                        self.write_fifo(write[current_write_idx].into() | BMSTART_BMSTOP_MASK)
+                    )?;
+                } else {
+                    nb::block!(self.write_fifo(write[current_write_idx].into()))?;
+                }
+                current_write_idx += 1;
+            }
+            if current_read_idx < read.len() {
+                read[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK)
+                    .try_into()
+                    .unwrap();
+                current_read_idx += 1;
+            }
+        }
+
+        Ok(())
+    }
+
+    fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
+        self.transfer_preparation(words)?;
+        let mut current_read_idx = 0;
+        let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
+
+        while current_read_idx < words.len() || current_write_idx < words.len() {
+            if current_write_idx < words.len() {
+                if current_write_idx == words.len() - 1 && self.bmstall {
+                    nb::block!(
+                        self.write_fifo(words[current_write_idx].into() | BMSTART_BMSTOP_MASK)
+                    )?;
+                } else {
+                    nb::block!(self.write_fifo(words[current_write_idx].into()))?;
+                }
+                current_write_idx += 1;
+            }
+            if current_read_idx < words.len() && current_read_idx < current_write_idx {
+                words[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK)
+                    .try_into()
+                    .unwrap();
+                current_read_idx += 1;
+            }
+        }
+        Ok(())
+    }
+
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        self.flush_internal();
+        Ok(())
+    }
+}
+
+/// Changing the word size also requires a type conversion
+impl From<Spi<u8>> for Spi<u16> {
+    fn from(mut old_spi: Spi<u8>) -> Self {
+        old_spi.regs.modify_ctrl0(|mut value| {
+            value.set_word_size(WordSize::SixteenBits);
+            value
+        });
+        Spi {
+            id: old_spi.id,
+            regs: old_spi.regs,
+            cfg: old_spi.cfg,
+            blockmode: old_spi.blockmode,
+            fill_word: Default::default(),
+            bmstall: old_spi.bmstall,
+            word: PhantomData,
+        }
+    }
+}
+
+impl From<Spi<u16>> for Spi<u8> {
+    fn from(mut old_spi: Spi<u16>) -> Self {
+        old_spi.regs.modify_ctrl0(|mut value| {
+            value.set_word_size(WordSize::EightBits);
+            value
+        });
+        Spi {
+            id: old_spi.id,
+            regs: old_spi.regs,
+            cfg: old_spi.cfg,
+            blockmode: old_spi.blockmode,
+            fill_word: Default::default(),
+            bmstall: old_spi.bmstall,
+            word: PhantomData,
+        }
+    }
+}

src/spi/pins_vor1x.rs

@@ -0,0 +1,303 @@
+use super::{HwCsProvider, PinMiso, PinMosi, PinSck};
+use crate::FunSel;
+use crate::gpio::{PinId, PinIdProvider};
+
+use crate::pins::{
+    Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, Pa16, Pa17, Pa18, Pa19, Pa20, Pa21, Pa22, Pa23, Pa24, Pa25,
+    Pa26, Pa27, Pa28, Pa29, Pa30, Pa31, Pb0, Pb1, Pb2, Pb3, Pb4, Pb5, Pb6, Pb7, Pb8, Pb9, Pb10,
+    Pb11, Pb12, Pb13, Pb14, Pb15, Pb16, Pb17, Pb18, Pb19, Pb22, Pb23, Pin,
+};
+
+use super::{Bank, HwChipSelectId};
+
+// SPIA
+
+impl PinSck for Pin<Pa31> {
+    const SPI_ID: Bank = Bank::Spi0;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+impl PinMosi for Pin<Pa30> {
+    const SPI_ID: Bank = Bank::Spi0;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+impl PinMiso for Pin<Pa29> {
+    const SPI_ID: Bank = Bank::Spi0;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+
+impl PinSck for Pin<Pb9> {
+    const SPI_ID: Bank = Bank::Spi0;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMosi for Pin<Pb8> {
+    const SPI_ID: Bank = Bank::Spi0;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMiso for Pin<Pb7> {
+    const SPI_ID: Bank = Bank::Spi0;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+
+hw_cs_pins!(
+    Bank::Spi0,
+    (Pb0, FunSel::Sel2, HwChipSelectId::Id1),
+    (Pb1, FunSel::Sel2, HwChipSelectId::Id2),
+    (Pb2, FunSel::Sel2, HwChipSelectId::Id3),
+    (Pb3, FunSel::Sel2, HwChipSelectId::Id4),
+    (Pb4, FunSel::Sel2, HwChipSelectId::Id5),
+    (Pb5, FunSel::Sel2, HwChipSelectId::Id6),
+    (Pb6, FunSel::Sel2, HwChipSelectId::Id0),
+    (Pa24, FunSel::Sel1, HwChipSelectId::Id4),
+    (Pa25, FunSel::Sel1, HwChipSelectId::Id3),
+    (Pa26, FunSel::Sel1, HwChipSelectId::Id2),
+    (Pa27, FunSel::Sel1, HwChipSelectId::Id1),
+    (Pa28, FunSel::Sel1, HwChipSelectId::Id0),
+);
+
+hw_cs_multi_pin!(
+    PinPb0SpiaHwCsId1,
+    Pb0,
+    Bank::Spi0,
+    FunSel::Sel2,
+    HwChipSelectId::Id1
+);
+hw_cs_multi_pin!(
+    PinPb1SpiaHwCsId2,
+    Pb1,
+    Bank::Spi0,
+    FunSel::Sel2,
+    HwChipSelectId::Id2
+);
+hw_cs_multi_pin!(
+    PinPb2SpiaHwCsId3,
+    Pb2,
+    Bank::Spi0,
+    FunSel::Sel2,
+    HwChipSelectId::Id3
+);
+
+hw_cs_multi_pin!(
+    PinPa21SpiaHwCsId7,
+    Pa21,
+    Bank::Spi0,
+    FunSel::Sel1,
+    HwChipSelectId::Id7
+);
+hw_cs_multi_pin!(
+    PinPa22SpiaHwCsId6,
+    Pa22,
+    Bank::Spi0,
+    FunSel::Sel1,
+    HwChipSelectId::Id6
+);
+hw_cs_multi_pin!(
+    PinPa23SpiaHwCsId5,
+    Pa23,
+    Bank::Spi0,
+    FunSel::Sel1,
+    HwChipSelectId::Id5
+);
+
+// SPIB
+
+impl PinSck for Pin<Pa20> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMosi for Pin<Pa19> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMiso for Pin<Pa18> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+
+pub type SpiBPortASck = Pin<Pa20>;
+pub type SpiBPortAMosi = Pin<Pa19>;
+pub type SpiBPortAMiso = Pin<Pa18>;
+
+impl PinSck for Pin<Pb19> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+impl PinMosi for Pin<Pb18> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+impl PinMiso for Pin<Pb17> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+
+impl PinSck for Pin<Pb5> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+impl PinMosi for Pin<Pb4> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+impl PinMiso for Pin<Pb3> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+
+// TODO: Need to deal with these duplications..
+hw_cs_pins!(
+    Bank::Spi1,
+    (Pb16, FunSel::Sel1, HwChipSelectId::Id0),
+    (Pb15, FunSel::Sel1, HwChipSelectId::Id1),
+    (Pb14, FunSel::Sel1, HwChipSelectId::Id2),
+    (Pb13, FunSel::Sel1, HwChipSelectId::Id3),
+    (Pa17, FunSel::Sel2, HwChipSelectId::Id0),
+    (Pa16, FunSel::Sel2, HwChipSelectId::Id1),
+    (Pa15, FunSel::Sel2, HwChipSelectId::Id2),
+    (Pa14, FunSel::Sel2, HwChipSelectId::Id3),
+    (Pa13, FunSel::Sel2, HwChipSelectId::Id4),
+    (Pa12, FunSel::Sel2, HwChipSelectId::Id5),
+    (Pa11, FunSel::Sel2, HwChipSelectId::Id6),
+    (Pa10, FunSel::Sel2, HwChipSelectId::Id7),
+    (Pa23, FunSel::Sel2, HwChipSelectId::Id5),
+    (Pa22, FunSel::Sel2, HwChipSelectId::Id6),
+    (Pa21, FunSel::Sel2, HwChipSelectId::Id7),
+);
+
+hw_cs_multi_pin!(
+    PinPb0SpibHwCsId2,
+    Pb0,
+    Bank::Spi1,
+    FunSel::Sel1,
+    HwChipSelectId::Id2
+);
+hw_cs_multi_pin!(
+    PinPb1SpibHwCsId1,
+    Pb1,
+    Bank::Spi1,
+    FunSel::Sel1,
+    HwChipSelectId::Id1
+);
+hw_cs_multi_pin!(
+    PinPb2SpibHwCsId0,
+    Pb2,
+    Bank::Spi1,
+    FunSel::Sel1,
+    HwChipSelectId::Id0
+);
+
+hw_cs_multi_pin!(
+    PinPb10SpibHwCsId6,
+    Pb10,
+    Bank::Spi1,
+    FunSel::Sel1,
+    HwChipSelectId::Id6
+);
+hw_cs_multi_pin!(
+    PinPb11SpibHwCsId5,
+    Pb11,
+    Bank::Spi1,
+    FunSel::Sel1,
+    HwChipSelectId::Id5
+);
+hw_cs_multi_pin!(
+    PinPb12SpibHwCsId4,
+    Pb12,
+    Bank::Spi1,
+    FunSel::Sel1,
+    HwChipSelectId::Id4
+);
+
+hw_cs_multi_pin!(
+    PinPb10SpibHwCsId2,
+    Pb10,
+    Bank::Spi1,
+    FunSel::Sel2,
+    HwChipSelectId::Id2
+);
+hw_cs_multi_pin!(
+    PinPb11SpibHwCsId1,
+    Pb11,
+    Bank::Spi1,
+    FunSel::Sel2,
+    HwChipSelectId::Id1
+);
+hw_cs_multi_pin!(
+    PinPb12SpibHwCsId0,
+    Pb12,
+    Bank::Spi1,
+    FunSel::Sel2,
+    HwChipSelectId::Id0
+);
+
+hw_cs_multi_pin!(
+    PinPa21SpibHwCsId7,
+    Pa21,
+    Bank::Spi1,
+    FunSel::Sel2,
+    HwChipSelectId::Id7
+);
+hw_cs_multi_pin!(
+    PinPa22SpibHwCsId6,
+    Pa22,
+    Bank::Spi1,
+    FunSel::Sel2,
+    HwChipSelectId::Id6
+);
+hw_cs_multi_pin!(
+    PinPa23SpibHwCsId5,
+    Pa23,
+    Bank::Spi1,
+    FunSel::Sel2,
+    HwChipSelectId::Id5
+);
+
+// SPIC
+
+hw_cs_pins!(
+    Bank::Spi2,
+    (Pb9, FunSel::Sel3, HwChipSelectId::Id1),
+    (Pb8, FunSel::Sel3, HwChipSelectId::Id2),
+    (Pb7, FunSel::Sel3, HwChipSelectId::Id3),
+    (Pb23, FunSel::Sel3, HwChipSelectId::Id2),
+    (Pb22, FunSel::Sel3, HwChipSelectId::Id1),
+    (Pa20, FunSel::Sel1, HwChipSelectId::Id1),
+    (Pa19, FunSel::Sel1, HwChipSelectId::Id2),
+    (Pb18, FunSel::Sel1, HwChipSelectId::Id3),
+);
+
+hw_cs_multi_pin!(
+    PinPa21SpicHwCsId3,
+    Pa21,
+    Bank::Spi2,
+    FunSel::Sel3,
+    HwChipSelectId::Id3
+);
+hw_cs_multi_pin!(
+    PinPa22SpicHwCsId2,
+    Pa22,
+    Bank::Spi2,
+    FunSel::Sel3,
+    HwChipSelectId::Id2
+);
+hw_cs_multi_pin!(
+    PinPa23SpicHwCsId1,
+    Pa23,
+    Bank::Spi2,
+    FunSel::Sel3,
+    HwChipSelectId::Id1
+);
+
+hw_cs_multi_pin!(
+    PinPa20SpicHwCsId1,
+    Pa20,
+    Bank::Spi2,
+    FunSel::Sel1,
+    HwChipSelectId::Id1
+);
+hw_cs_multi_pin!(
+    PinPa20SpicHwCsId4,
+    Pa20,
+    Bank::Spi2,
+    FunSel::Sel3,
+    HwChipSelectId::Id4
+);

src/spi/pins_vor4x.rs

@@ -0,0 +1,205 @@
+use crate::{
+    FunSel,
+    gpio::{Pin, PinId, PinIdProvider},
+    pins::{
+        Pa0, Pa1, Pa2, Pa3, Pa4, Pa5, Pa6, Pa7, Pa8, Pa9, Pb0, Pb1, Pb2, Pb3, Pb4, Pb12, Pb13,
+        Pb14, Pb15, Pc0, Pc1, Pc7, Pc8, Pc9, Pc10, Pc11, Pe5, Pe6, Pe7, Pe8, Pe9, Pe12, Pe13, Pe14,
+        Pe15, Pf0, Pf1, Pg2, Pg3, Pg4,
+    },
+};
+
+#[cfg(not(feature = "va41628"))]
+use crate::pins::{Pb5, Pb6, Pb7, Pb8, Pb9, Pb10, Pb11, Pe10, Pe11, Pf2, Pf3, Pf4, Pf5, Pf6, Pf7};
+
+use super::{Bank, HwChipSelectId, HwCsProvider, PinMiso, PinMosi, PinSck};
+
+// SPI0
+
+impl PinSck for Pin<Pb15> {
+    const SPI_ID: Bank = Bank::Spi0;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+impl PinMosi for Pin<Pc1> {
+    const SPI_ID: Bank = Bank::Spi0;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+impl PinMiso for Pin<Pc0> {
+    const SPI_ID: Bank = Bank::Spi0;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+
+hw_cs_pins!(
+    Bank::Spi0,
+    (Pb14, FunSel::Sel1, HwChipSelectId::Id0),
+    (Pb13, FunSel::Sel1, HwChipSelectId::Id1),
+    (Pb12, FunSel::Sel1, HwChipSelectId::Id2),
+);
+
+#[cfg(not(feature = "va41628"))]
+hw_cs_pins!(Bank::Spi0, (Pb11, FunSel::Sel1, HwChipSelectId::Id3));
+
+// SPI1
+
+#[cfg(not(feature = "va41628"))]
+impl PinSck for Pin<Pb8> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel3;
+}
+#[cfg(not(feature = "va41628"))]
+impl PinMosi for Pin<Pb10> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel3;
+}
+#[cfg(not(feature = "va41628"))]
+impl PinMiso for Pin<Pb9> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel3;
+}
+
+impl PinSck for Pin<Pc9> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMosi for Pin<Pc11> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMiso for Pin<Pc10> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+
+impl PinSck for Pin<Pe13> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMosi for Pin<Pe15> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMiso for Pin<Pe14> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+
+#[cfg(not(feature = "va41628"))]
+impl PinSck for Pin<Pf3> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+#[cfg(not(feature = "va41628"))]
+impl PinMosi for Pin<Pf5> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+#[cfg(not(feature = "va41628"))]
+impl PinMiso for Pin<Pf4> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel1;
+}
+
+impl PinSck for Pin<Pg3> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMiso for Pin<Pg4> {
+    const SPI_ID: Bank = Bank::Spi1;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+
+hw_cs_pins!(
+    Bank::Spi1,
+    (Pb4, FunSel::Sel3, HwChipSelectId::Id3),
+    (Pb3, FunSel::Sel3, HwChipSelectId::Id4),
+    (Pb2, FunSel::Sel3, HwChipSelectId::Id5),
+    (Pb1, FunSel::Sel3, HwChipSelectId::Id6),
+    (Pb0, FunSel::Sel3, HwChipSelectId::Id7),
+    (Pc8, FunSel::Sel2, HwChipSelectId::Id0),
+    (Pc7, FunSel::Sel2, HwChipSelectId::Id1),
+    (Pe12, FunSel::Sel2, HwChipSelectId::Id0),
+    (Pe9, FunSel::Sel2, HwChipSelectId::Id3),
+    (Pe8, FunSel::Sel2, HwChipSelectId::Id4),
+    (Pe7, FunSel::Sel3, HwChipSelectId::Id5),
+    (Pe6, FunSel::Sel3, HwChipSelectId::Id6),
+    (Pe5, FunSel::Sel3, HwChipSelectId::Id7),
+    (Pg2, FunSel::Sel2, HwChipSelectId::Id0),
+);
+
+#[cfg(not(feature = "va41628"))]
+hw_cs_pins!(
+    Bank::Spi1,
+    (Pb7, FunSel::Sel3, HwChipSelectId::Id0),
+    (Pb6, FunSel::Sel3, HwChipSelectId::Id1),
+    (Pb5, FunSel::Sel3, HwChipSelectId::Id2),
+    (Pe11, FunSel::Sel2, HwChipSelectId::Id1),
+    (Pe10, FunSel::Sel2, HwChipSelectId::Id2),
+);
+
+#[cfg(not(feature = "va41628"))]
+hw_cs_multi_pin!(
+    PinPf2Spi1HwCsId0,
+    Pf2,
+    Bank::Spi2,
+    FunSel::Sel1,
+    HwChipSelectId::Id0
+);
+
+// SPI2
+
+impl PinSck for Pin<Pa5> {
+    const SPI_ID: Bank = Bank::Spi2;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMosi for Pin<Pa7> {
+    const SPI_ID: Bank = Bank::Spi2;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+impl PinMiso for Pin<Pa6> {
+    const SPI_ID: Bank = Bank::Spi2;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+
+#[cfg(not(feature = "va41628"))]
+impl PinSck for Pin<Pf5> {
+    const SPI_ID: Bank = Bank::Spi2;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+#[cfg(not(feature = "va41628"))]
+impl PinMosi for Pin<Pf7> {
+    const SPI_ID: Bank = Bank::Spi2;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+#[cfg(not(feature = "va41628"))]
+impl PinMiso for Pin<Pf6> {
+    const SPI_ID: Bank = Bank::Spi2;
+    const FUN_SEL: FunSel = FunSel::Sel2;
+}
+
+hw_cs_pins!(
+    Bank::Spi1,
+    (Pa4, FunSel::Sel2, HwChipSelectId::Id0),
+    (Pa3, FunSel::Sel2, HwChipSelectId::Id1),
+    (Pa2, FunSel::Sel2, HwChipSelectId::Id2),
+    (Pa1, FunSel::Sel2, HwChipSelectId::Id3),
+    (Pa0, FunSel::Sel2, HwChipSelectId::Id4),
+    (Pa8, FunSel::Sel2, HwChipSelectId::Id5),
+    (Pa9, FunSel::Sel2, HwChipSelectId::Id6),
+    (Pf0, FunSel::Sel2, HwChipSelectId::Id4),
+    (Pf1, FunSel::Sel2, HwChipSelectId::Id3),
+);
+
+#[cfg(not(feature = "va41628"))]
+hw_cs_pins!(
+    Bank::Spi1,
+    (Pf3, FunSel::Sel2, HwChipSelectId::Id1),
+    (Pf4, FunSel::Sel2, HwChipSelectId::Id0),
+);
+
+#[cfg(not(feature = "va41628"))]
+hw_cs_multi_pin!(
+    PinPf2Spi2HwCsId2,
+    Pf2,
+    Bank::Spi2,
+    FunSel::Sel2,
+    HwChipSelectId::Id2
+);

src/spi/regs.rs

@@ -0,0 +1,279 @@
+use core::marker::PhantomData;
+
+pub use crate::shared::{FifoClear, TriggerLevel};
+
+cfg_if::cfg_if! {
+    if #[cfg(feature = "vor1x")] {
+        /// SPI A base address
+        pub const BASE_ADDR_0: usize = 0x4005_0000;
+        /// SPI B base address
+        pub const BASE_ADDR_1: usize = 0x4005_1000;
+        /// SPI C base address
+        pub const BASE_ADDR_2: usize = 0x4005_2000;
+    } else if #[cfg(feature = "vor4x")] {
+        /// SPI 0 base address
+        pub const BASE_ADDR_0: usize = 0x4001_5000;
+        /// SPI 1 base address
+        pub const BASE_ADDR_1: usize = 0x4001_5400;
+        /// SPI 2 base address
+        pub const BASE_ADDR_2: usize = 0x4001_5800;
+        /// SPI 3 base address
+        pub const BASE_ADDR_3: usize = 0x4001_5C00;
+    }
+}
+
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Bank {
+    Spi0,
+    Spi1,
+    Spi2,
+    #[cfg(feature = "vor4x")]
+    Spi3,
+}
+
+impl Bank {
+    /// Unsafely steal the SPI peripheral block for the given port.
+    ///
+    /// # Safety
+    ///
+    /// Circumvents ownership and safety guarantees by the HAL.
+    pub unsafe fn steal_regs(&self) -> MmioSpi<'static> {
+        Spi::new_mmio(*self)
+    }
+}
+
+#[bitbybit::bitenum(u4)]
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum WordSize {
+    OneBit = 0x00,
+    FourBits = 0x03,
+    EightBits = 0x07,
+    SixteenBits = 0x0f,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+#[bitbybit::bitenum(u3, exhaustive = true)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum HwChipSelectId {
+    Id0 = 0,
+    Id1 = 1,
+    Id2 = 2,
+    Id3 = 3,
+    Id4 = 4,
+    Id5 = 5,
+    Id6 = 6,
+    Id7 = 7,
+}
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug)]
+pub struct Control0 {
+    #[bits(8..=15, rw)]
+    scrdv: u8,
+    #[bit(7, rw)]
+    sph: bool,
+    #[bit(6, rw)]
+    spo: bool,
+    #[bits(0..=3, rw)]
+    word_size: Option<WordSize>,
+}
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug)]
+pub struct Control1 {
+    #[bit(11, rw)]
+    mtxpause: bool,
+    #[bit(10, rw)]
+    mdlycap: bool,
+    #[bit(9, rw)]
+    bm_stall: bool,
+    #[bit(8, rw)]
+    bm_start: bool,
+    #[bit(7, rw)]
+    blockmode: bool,
+    #[bits(4..=6, rw)]
+    ss: HwChipSelectId,
+    #[bit(3, rw)]
+    sod: bool,
+    #[bit(2, rw)]
+    slave_mode: bool,
+    #[bit(1, rw)]
+    enable: bool,
+    #[bit(0, rw)]
+    lbm: bool,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct Data {
+    /// Only used for BLOCKMODE. For received data, this bit indicated that the data was the first
+    /// word after the chip select went active. For transmitted data, setting this bit to 1
+    /// will end an SPI frame (deassert CS) after the specified data word.
+    #[bit(31, rw)]
+    bm_start_stop: bool,
+    /// Only used for BLOCKMODE. Setting this bit to 1 along with the BMSTOP bit will end an SPI
+    /// frame without any additional data to be transmitted. If BMSTOP is not set, this bit is
+    /// ignored.
+    #[bit(30, rw)]
+    bm_skipdata: bool,
+    #[bits(0..=15, rw)]
+    data: u16,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct Status {
+    /// TX FIFO below the trigger level.
+    #[bit(7, r)]
+    tx_trigger: bool,
+    /// RX FIFO above or equals the trigger level.
+    #[bit(6, r)]
+    rx_trigger: bool,
+    #[bit(5, r)]
+    rx_data_first: bool,
+    #[bit(4, r)]
+    busy: bool,
+    #[bit(3, r)]
+    rx_full: bool,
+    #[bit(2, r)]
+    rx_not_empty: bool,
+    #[bit(1, r)]
+    tx_not_full: bool,
+    #[bit(0, r)]
+    tx_empty: bool,
+}
+
+/// Clock divisor value. Bit 0 is ignored and always 0. This means that only the even values
+/// are used as clock divisor values, and uneven values are truncated to the next even value.
+/// A value of 0 acts as a 1 for the divisor value.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+pub struct ClkPrescaler(arbitrary_int::UInt<u32, 8>);
+
+impl ClkPrescaler {
+    pub const fn new(value: u8) -> Self {
+        ClkPrescaler(arbitrary_int::UInt::<u32, 8>::new(value as u32))
+    }
+    pub const fn value(&self) -> u8 {
+        self.0.value() as u8
+    }
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct InterruptControl {
+    /// TX FIFO count <= TX FIFO trigger level.
+    #[bit(3, rw)]
+    tx: bool,
+    /// RX FIFO count >= RX FIFO trigger level.
+    #[bit(2, rw)]
+    rx: bool,
+    /// Occurs when the RX FIFO has not been read within 32 clock ticks of the SPICLKx2 clock
+    /// within the RX FIFO not being empty. Clearing the RX interrupt or reading data from the
+    /// FIFO resets the timeout counter.
+    #[bit(1, rw)]
+    rx_timeout: bool,
+    #[bit(0, rw)]
+    rx_overrun: bool,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct InterruptStatus {
+    /// TX FIFO count <= TX FIFO trigger level.
+    #[bit(3, r)]
+    tx: bool,
+    /// RX FIFO count >= RX FIFO trigger level.
+    #[bit(2, r)]
+    rx: bool,
+    /// Occurs when the RX FIFO has not been read within 32 clock ticks of the SPICLKx2 clock
+    /// within the RX FIFO not being empty. Clearing the RX interrupt or reading data from the
+    /// FIFO resets the timeout counter.
+    #[bit(1, r)]
+    rx_timeout: bool,
+    #[bit(0, r)]
+    rx_overrun: bool,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct InterruptClear {
+    /// Clearing the RX interrupt or reading data from the FIFO resets the timeout counter.
+    #[bit(1, w)]
+    rx_timeout: bool,
+    #[bit(0, w)]
+    rx_overrun: bool,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct State {
+    #[bits(0..=7, r)]
+    rx_state: u8,
+    #[bits(8..=15, r)]
+    rx_fifo: u8,
+    #[bits(24..=31, r)]
+    tx_fifo: u8,
+}
+
+#[derive(derive_mmio::Mmio)]
+#[mmio(no_ctors)]
+#[repr(C)]
+pub struct Spi {
+    ctrl0: Control0,
+    ctrl1: Control1,
+    data: Data,
+    #[mmio(PureRead)]
+    status: Status,
+    clkprescale: ClkPrescaler,
+    irq_enb: InterruptControl,
+    /// Raw interrupt status.
+    #[mmio(PureRead)]
+    irq_raw: InterruptStatus,
+    /// Enabled interrupt status.
+    #[mmio(PureRead)]
+    irq_status: InterruptStatus,
+    #[mmio(Write)]
+    irq_clear: InterruptClear,
+    rx_fifo_trigger: TriggerLevel,
+    tx_fifo_trigger: TriggerLevel,
+    #[mmio(Write)]
+    fifo_clear: FifoClear,
+    #[mmio(PureRead)]
+    state: u32,
+    #[cfg(feature = "vor1x")]
+    _reserved: [u32; 0x3F2],
+    #[cfg(feature = "vor4x")]
+    _reserved: [u32; 0xF2],
+    /// Vorago 1x: 0x0113_07E1. Vorago 4x: 0x0213_07E9.
+    #[mmio(PureRead)]
+    perid: u32,
+}
+
+cfg_if::cfg_if! {
+    if #[cfg(feature = "vor1x")] {
+        static_assertions::const_assert_eq!(core::mem::size_of::<Spi>(), 0x1000);
+    } else if #[cfg(feature = "vor4x")] {
+        static_assertions::const_assert_eq!(core::mem::size_of::<Spi>(), 0x400);
+    }
+}
+
+impl Spi {
+    fn new_mmio_at(base: usize) -> MmioSpi<'static> {
+        MmioSpi {
+            ptr: base as *mut _,
+            phantom: PhantomData,
+        }
+    }
+
+    pub fn new_mmio(bank: Bank) -> MmioSpi<'static> {
+        match bank {
+            Bank::Spi0 => Self::new_mmio_at(BASE_ADDR_0),
+            Bank::Spi1 => Self::new_mmio_at(BASE_ADDR_1),
+            Bank::Spi2 => Self::new_mmio_at(BASE_ADDR_2),
+            #[cfg(feature = "vor4x")]
+            Bank::Spi3 => Self::new_mmio_at(BASE_ADDR_2),
+        }
+    }
+}