From f216b39f0af99e28489767d57fd0a9a27b6cb0ad Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Wed, 3 Sep 2025 09:41:34 +0200 Subject: [PATCH] better naming --- CHANGELOG.md | 19 ++++- Cargo.toml | 4 +- src/embassy.rs | 6 +- src/gpio/asynch.rs | 4 +- src/gpio/ll.rs | 34 ++++---- src/gpio/mod.rs | 60 ++++--------- src/i2c/mod.rs | 40 ++++----- src/i2c/regs.rs | 12 +-- src/ioconfig/mod.rs | 2 +- src/ioconfig/regs.rs | 16 ++-- src/lib.rs | 3 +- src/pins.rs | 53 +++++++++--- src/pwm.rs | 4 +- src/spi/mod.rs | 110 ++++++++++++------------ src/spi/pins_vor1x.rs | 150 ++++++++++++++++----------------- src/spi/pins_vor4x.rs | 125 +++++++++++++-------------- src/spi/regs.rs | 8 +- src/timer/mod.rs | 26 +++--- src/timer/pins_vor1x.rs | 98 +++++++++++----------- src/timer/pins_vor4x.rs | 182 ++++++++++++++++++++-------------------- src/uart/mod.rs | 120 +++++++++++++------------- src/uart/pins_vor1x.rs | 46 +++++----- src/uart/pins_vor4x.rs | 38 ++++----- src/uart/regs.rs | 4 +- 24 files changed, 592 insertions(+), 572 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index f3c972a..1b5d959 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,9 +8,26 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [unreleased] +## [v0.2.0] + +Renamed to `vorago-shared-hal` + +### Changed + +- Various renaming to be more in-line with common Embedded Rust naming conventions. + - `PinId` -> `DynPinId` + - `PinIdProvider` -> `PinId` + - `FunSel` -> `FunctionSelect` + - `PinMarker` -> `AnyPin` + - Peripheral traits renamed from `*Marker` to `*Instance` + - `Clk` abbreviation in names changed to `Clock` + - `Cmd` abbreviation in names changed to `Command` + - `Irq` abbreviation in names changed to `Interrupt` + ## [v0.1.0] 2025-09-02 Init commit. -[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/v0.1.0...HEAD +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs/compare/v0.1.0...HEAD +[unreleased]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs/compare/v0.1.0...v0.2.0 [v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs/src/tag/v0.1.0 diff --git a/Cargo.toml b/Cargo.toml index adf31b8..9c816f4 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,7 +1,7 @@ [package] -name = "vorago-shared-periphs" +name = "vorago-shared-hal" version = "0.1.0" -description = "Peripheral drivers shared between Vorago families" +description = "Peripheral HAL components shared between Vorago families" edition = "2024" homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs" repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs" diff --git a/src/embassy.rs b/src/embassy.rs index 72b7e91..a93a810 100644 --- a/src/embassy.rs +++ b/src/embassy.rs @@ -3,7 +3,7 @@ use core::cell::{Cell, RefCell}; use crate::{ enable_nvic_interrupt, timer::{ - TimId, TimMarker, assert_tim_reset_for_cycles, enable_tim_clk, + TimId, TimInstance, assert_tim_reset_for_cycles, enable_tim_clk, regs::{EnableControl, MmioTimer}, }, }; @@ -59,7 +59,7 @@ pub struct TimerDriver { impl TimerDriver { #[cfg(feature = "vor1x")] #[doc(hidden)] - pub fn __init( + pub fn __init( &self, sysclk: Hertz, _timekeeper_tim: TimekeeperTim, @@ -117,7 +117,7 @@ impl TimerDriver { #[cfg(feature = "vor4x")] #[doc(hidden)] - pub fn __init( + pub fn __init( &self, _timekeeper_tim: TimekeeperTim, _alarm_tim: AlarmTim, diff --git a/src/gpio/asynch.rs b/src/gpio/asynch.rs index 36f3632..46e349e 100644 --- a/src/gpio/asynch.rs +++ b/src/gpio/asynch.rs @@ -26,7 +26,7 @@ use va108xx as pac; pub use super::ll::InterruptEdge; use super::{ Input, Port, - ll::{LowLevelGpio, PinId}, + ll::{DynPinId, LowLevelGpio}, }; cfg_if::cfg_if! { @@ -146,7 +146,7 @@ fn on_interrupt_for_port( /// which also implements the [embedded_hal_async::digital::Wait] trait. However, access to this /// struture is granted to allow writing custom async structures. pub struct InputPinFuture { - id: PinId, + id: DynPinId, waker_group: &'static [AtomicWaker], edge_detection_group: &'static [AtomicBool], } diff --git a/src/gpio/ll.rs b/src/gpio/ll.rs index ba8e193..810d787 100644 --- a/src/gpio/ll.rs +++ b/src/gpio/ll.rs @@ -1,6 +1,6 @@ pub use embedded_hal::digital::PinState; -use crate::ioconfig::FilterClkSel; +use crate::ioconfig::FilterClockSelect; use crate::ioconfig::FilterType; #[cfg(feature = "vor1x")] use crate::{PeripheralSelect, sysconfig::enable_peripheral_clock}; @@ -8,10 +8,10 @@ use crate::{PeripheralSelect, sysconfig::enable_peripheral_clock}; pub use crate::InvalidOffsetError; pub use crate::Port; pub use crate::ioconfig::regs::Pull; -use crate::ioconfig::regs::{FunSel, IoConfig, MmioIoConfig}; +use crate::ioconfig::regs::{FunctionSelect, IoConfig, MmioIoConfig}; +use crate::pins::PinId; use super::Pin; -use super::PinIdProvider; #[derive(Debug, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -31,7 +31,7 @@ pub enum InterruptLevel { /// Pin identifier for all physical pins exposed by Vorago MCUs. #[derive(Debug, PartialEq, Eq, Clone, Copy)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub struct PinId { +pub struct DynPinId { port: Port, /// Offset within the port. offset: u8, @@ -43,13 +43,13 @@ pub struct PinId { #[error("port G does not support interrupts")] pub struct PortDoesNotSupportInterrupts; -impl PinId { +impl DynPinId { /// Unchecked constructor which panics on invalid offsets. pub const fn new_unchecked(port: Port, offset: usize) -> Self { if offset >= port.max_offset() { panic!("Pin ID construction: offset is out of range"); } - PinId { + DynPinId { port, offset: offset as u8, } @@ -59,7 +59,7 @@ impl PinId { if offset >= port.max_offset() { return Err(InvalidOffsetError { offset, port }); } - Ok(PinId { + Ok(DynPinId { port, offset: offset as u8, }) @@ -209,7 +209,7 @@ impl PinId { pub struct LowLevelGpio { gpio: super::regs::MmioGpio<'static>, ioconfig: MmioIoConfig<'static>, - id: PinId, + id: DynPinId, } impl core::fmt::Debug for LowLevelGpio { @@ -225,12 +225,12 @@ impl LowLevelGpio { /// Create a new low-level GPIO pin instance from a given [Pin]. /// /// Can be used for performing resource management of the [Pin]s. - pub fn new_with_pin(_pin: Pin) -> Self { + pub fn new_with_pin(_pin: Pin) -> Self { Self::new(I::ID) } /// Create a new low-level GPIO pin instance using only the [PinId]. - pub fn new(id: PinId) -> Self { + pub fn new(id: DynPinId) -> Self { LowLevelGpio { gpio: super::regs::Gpio::new_mmio(id.port), ioconfig: IoConfig::new_mmio(), @@ -239,7 +239,7 @@ impl LowLevelGpio { } #[inline] - pub fn id(&self) -> PinId { + pub fn id(&self) -> DynPinId { self.id } @@ -255,7 +255,7 @@ impl LowLevelGpio { pub fn configure_as_input_floating(&mut self) { self.ioconfig.modify_pin_config(self.id, |mut config| { - config.set_funsel(FunSel::Sel0); + config.set_funsel(FunctionSelect::Sel0); config.set_io_disable(false); config.set_invert_input(false); config.set_open_drain(false); @@ -273,7 +273,7 @@ impl LowLevelGpio { pub fn configure_as_input_with_pull(&mut self, pull: Pull) { self.ioconfig.modify_pin_config(self.id, |mut config| { - config.set_funsel(FunSel::Sel0); + config.set_funsel(FunctionSelect::Sel0); config.set_io_disable(false); config.set_invert_input(false); config.set_open_drain(false); @@ -292,7 +292,7 @@ impl LowLevelGpio { pub fn configure_as_output_push_pull(&mut self, init_level: PinState) { self.ioconfig.modify_pin_config(self.id, |mut config| { - config.set_funsel(FunSel::Sel0); + config.set_funsel(FunctionSelect::Sel0); config.set_io_disable(false); config.set_invert_input(false); config.set_open_drain(false); @@ -314,7 +314,7 @@ impl LowLevelGpio { pub fn configure_as_output_open_drain(&mut self, init_level: PinState) { self.ioconfig.modify_pin_config(self.id, |mut config| { - config.set_funsel(FunSel::Sel0); + config.set_funsel(FunctionSelect::Sel0); config.set_io_disable(false); config.set_invert_input(false); config.set_open_drain(true); @@ -336,7 +336,7 @@ impl LowLevelGpio { }); } - pub fn configure_as_peripheral_pin(&mut self, fun_sel: FunSel, pull: Option) { + pub fn configure_as_peripheral_pin(&mut self, fun_sel: FunctionSelect, pull: Option) { self.ioconfig.modify_pin_config(self.id, |mut config| { config.set_funsel(fun_sel); config.set_io_disable(false); @@ -487,7 +487,7 @@ impl LowLevelGpio { /// Only useful for input pins #[inline] - pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) { + pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClockSelect) { self.ioconfig.modify_pin_config(self.id, |mut config| { config.set_filter_type(filter); config.set_filter_clk_sel(clksel); diff --git a/src/gpio/mod.rs b/src/gpio/mod.rs index 3a3c051..498ea92 100644 --- a/src/gpio/mod.rs +++ b/src/gpio/mod.rs @@ -1,53 +1,21 @@ //! GPIO support module. use core::convert::Infallible; -pub use crate::ioconfig::{FilterClkSel, FilterType, regs::FunSel}; +pub use crate::ioconfig::{FilterClockSelect, FilterType, regs::FunctionSelect}; +pub use crate::pins::{Pin, PinId}; pub use embedded_hal::digital::PinState; -pub use ll::{InterruptEdge, InterruptLevel, PinId, Port, Pull}; +pub use ll::{DynPinId, InterruptEdge, InterruptLevel, Port, Pull}; pub mod asynch; pub mod ll; pub mod regs; -/// Trait implemented by data structures assocaited with pin identifiacation. -pub trait PinIdProvider { - const ID: ll::PinId; -} - -/// Primary Pin structure for the physical pins exposed by Vorago MCUs. -/// -/// This pin structure is only used for resource management and does not do anything on its -/// own. -pub struct Pin { - phantom: core::marker::PhantomData, -} - -impl Pin { - #[allow(clippy::new_without_default)] - #[doc(hidden)] - pub const fn __new() -> Self { - Self { - phantom: core::marker::PhantomData, - } - } - - /// Create a new pin instance. - /// - /// # Safety - /// - /// This circumvents ownership rules of the HAL and allows creating multiple instances - /// of the same pin. - pub const unsafe fn steal() -> Self { - Self::__new() - } -} - /// Push-Pull output pin. #[derive(Debug)] pub struct Output(ll::LowLevelGpio); impl Output { - pub fn new(_pin: Pin, init_level: PinState) -> Self { + pub fn new(_pin: Pin, init_level: PinState) -> Self { let mut ll = ll::LowLevelGpio::new(I::ID); ll.configure_as_output_push_pull(init_level); Output(ll) @@ -139,20 +107,20 @@ impl embedded_hal::digital::StatefulOutputPin for Output { pub struct Input(ll::LowLevelGpio); impl Input { - pub fn new_floating(_pin: Pin) -> Self { + pub fn new_floating(_pin: Pin) -> Self { let mut ll = ll::LowLevelGpio::new(I::ID); ll.configure_as_input_floating(); Input(ll) } - pub fn new_with_pull(_pin: Pin, pull: Pull) -> Self { + pub fn new_with_pull(_pin: Pin, pull: Pull) -> Self { let mut ll = ll::LowLevelGpio::new(I::ID); ll.configure_as_input_with_pull(pull); Input(ll) } #[inline] - pub fn id(&self) -> PinId { + pub fn id(&self) -> DynPinId { self.0.id() } @@ -187,7 +155,7 @@ impl Input { } #[inline] - pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) { + pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClockSelect) { self.0.configure_filter_type(filter, clksel); } @@ -252,7 +220,7 @@ pub struct Flex { } impl Flex { - pub fn new(_pin: Pin) -> Self { + pub fn new(_pin: Pin) -> Self { let mut ll = ll::LowLevelGpio::new(I::ID); ll.configure_as_input_floating(); Flex { @@ -360,13 +328,13 @@ impl embedded_hal::digital::StatefulOutputPin for Flex { /// Can be used to configure pins as IO peripheral pins. pub struct IoPeriphPin { ll: ll::LowLevelGpio, - fun_sel: FunSel, + fun_sel: FunctionSelect, } impl IoPeriphPin { - pub fn new_with_pin( + pub fn new_with_pin( _pin: Pin, - fun_sel: FunSel, + fun_sel: FunctionSelect, pull: Option, ) -> Self { let mut ll = ll::LowLevelGpio::new(I::ID); @@ -374,7 +342,7 @@ impl IoPeriphPin { IoPeriphPin { ll, fun_sel } } - pub fn new(pin_id: PinId, fun_sel: FunSel, pull: Option) -> Self { + pub fn new(pin_id: DynPinId, fun_sel: FunctionSelect, pull: Option) -> Self { let mut ll = ll::LowLevelGpio::new(pin_id); ll.configure_as_peripheral_pin(fun_sel, pull); IoPeriphPin { ll, fun_sel } @@ -388,7 +356,7 @@ impl IoPeriphPin { self.ll.offset() } - pub fn fun_sel(&self) -> FunSel { + pub fn fun_sel(&self) -> FunctionSelect { self.fun_sel } } diff --git a/src/i2c/mod.rs b/src/i2c/mod.rs index 39bd3b7..48805a0 100644 --- a/src/i2c/mod.rs +++ b/src/i2c/mod.rs @@ -7,7 +7,7 @@ use crate::{ use arbitrary_int::{u4, u10, u11, u20}; use core::marker::PhantomData; use embedded_hal::i2c::{self, Operation, SevenBitAddress, TenBitAddress}; -use regs::ClkTimeoutLimit; +use regs::ClockTimeoutLimit; pub use regs::{Bank, I2cSpeed, RxFifoFullMode, TxFifoEmptyMode}; #[cfg(feature = "vor1x")] @@ -60,7 +60,7 @@ pub enum InitError { WrongAddrMode, /// APB1 clock is too slow for fast I2C mode. #[error("clock too slow for fast I2C mode: {0}")] - ClkTooSlow(#[from] ClockTooSlowForFastI2cError), + ClockTooSlow(#[from] ClockTooSlowForFastI2cError), } impl embedded_hal::i2c::Error for Error { @@ -82,7 +82,7 @@ impl embedded_hal::i2c::Error for Error { #[derive(Debug, PartialEq, Copy, Clone)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum I2cCmd { +pub enum I2cCommand { Start = 0b01, Stop = 0b10, StartWithStop = 0b11, @@ -113,7 +113,7 @@ impl I2cAddress { /// Common trait implemented by all PAC peripheral access structures. The register block /// format is the same for all SPI blocks. -pub trait I2cMarker: Sealed { +pub trait I2cInstance: Sealed { const ID: Bank; const PERIPH_SEL: PeripheralSelect; } @@ -123,7 +123,7 @@ pub type I2c0 = pac::I2ca; #[cfg(feature = "vor4x")] pub type I2c0 = pac::I2c0; -impl I2cMarker for I2c0 { +impl I2cInstance for I2c0 { const ID: Bank = Bank::I2c0; const PERIPH_SEL: PeripheralSelect = PeripheralSelect::I2c0; } @@ -134,7 +134,7 @@ pub type I2c1 = pac::I2cb; #[cfg(feature = "vor4x")] pub type I2c1 = pac::I2c1; -impl I2cMarker for I2c1 { +impl I2cInstance for I2c1 { const ID: Bank = Bank::I2c1; const PERIPH_SEL: PeripheralSelect = PeripheralSelect::I2c1; } @@ -291,7 +291,7 @@ pub struct I2cMaster { } impl I2cMaster { - pub fn new( + pub fn new( _i2c: I2c, #[cfg(feature = "vor1x")] sysclk: Hertz, #[cfg(feature = "vor4x")] clks: &crate::clock::Clocks, @@ -306,7 +306,7 @@ impl I2cMaster { #[cfg(feature = "vor4x")] let clk_div = calc_clk_div(clks, speed_mode)?; regs.write_clkscale( - regs::ClkScale::builder() + regs::ClockScale::builder() .with_div(clk_div) .with_fastmode(speed_mode) .build(), @@ -344,7 +344,7 @@ impl I2cMaster { .build(), ); if let Some(timeout) = cfg.timeout { - regs.write_clk_timeout_limit(ClkTimeoutLimit::new(timeout)); + regs.write_clk_timeout_limit(ClockTimeoutLimit::new(timeout)); } let mut i2c_master = I2cMaster { addr: PhantomData, @@ -377,7 +377,7 @@ impl I2cMaster { #[cfg(feature = "vor4x")] let clk_div = calc_clk_div(clks, speed_mode)?; self.regs.write_clkscale( - regs::ClkScale::builder() + regs::ClockScale::builder() .with_div(clk_div) .with_fastmode(speed_mode) .build(), @@ -426,13 +426,13 @@ impl I2cMaster { #[inline] pub fn set_clock_low_timeout(&mut self, clock_cycles: u20) { self.regs - .write_clk_timeout_limit(ClkTimeoutLimit::new(clock_cycles)); + .write_clk_timeout_limit(ClockTimeoutLimit::new(clock_cycles)); } #[inline] pub fn disable_clock_low_timeout(&mut self) { self.regs - .write_clk_timeout_limit(ClkTimeoutLimit::new(u20::new(0))); + .write_clk_timeout_limit(ClockTimeoutLimit::new(u20::new(0))); } #[inline] @@ -467,7 +467,7 @@ impl I2cMaster { } #[inline] - pub fn write_command(&mut self, cmd: I2cCmd) { + pub fn write_command(&mut self, cmd: I2cCommand) { self.regs .write_cmd(regs::Command::new_with_raw_value(cmd as u32)); } @@ -483,9 +483,9 @@ impl I2cMaster { ); } - fn error_handler_write(&mut self, init_cmd: I2cCmd) { - if init_cmd == I2cCmd::Start { - self.write_command(I2cCmd::Stop); + fn error_handler_write(&mut self, init_cmd: I2cCommand) { + if init_cmd == I2cCommand::Start { + self.write_command(I2cCommand::Stop); } // The other case is start with stop where, so a CANCEL command should not be necessary // because the hardware takes care of it. @@ -495,7 +495,7 @@ impl I2cMaster { /// Blocking write transaction on the I2C bus. pub fn write_blocking(&mut self, addr: I2cAddress, output: &[u8]) -> Result<(), Error> { self.write_blocking_generic( - I2cCmd::StartWithStop, + I2cCommand::StartWithStop, addr, output, WriteCompletionCondition::Idle, @@ -522,7 +522,7 @@ impl I2cMaster { let mut buf_iter = buffer.iter_mut(); let mut read_bytes = 0; // Start receive transfer - self.write_command(I2cCmd::StartWithStop); + self.write_command(I2cCommand::StartWithStop); loop { let status = self.read_status(); if status.arb_lost() { @@ -555,7 +555,7 @@ impl I2cMaster { fn write_blocking_generic( &mut self, - init_cmd: I2cCmd, + init_cmd: I2cCommand, addr: I2cAddress, output: &[u8], end_condition: WriteCompletionCondition, @@ -631,7 +631,7 @@ impl I2cMaster { read: &mut [u8], ) -> Result<(), Error> { self.write_blocking_generic( - I2cCmd::Start, + I2cCommand::Start, address, write, WriteCompletionCondition::Waiting, diff --git a/src/i2c/regs.rs b/src/i2c/regs.rs index 5707d6d..93a7412 100644 --- a/src/i2c/regs.rs +++ b/src/i2c/regs.rs @@ -93,7 +93,7 @@ pub enum I2cSpeed { } #[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))] -pub struct ClkScale { +pub struct ClockScale { /// Clock divide value. Reset value: 0x18. #[bits(0..=7, rw)] div: u8, @@ -313,11 +313,11 @@ pub struct TimingConfig { t_buf: u4, } -pub struct ClkTimeoutLimit(pub arbitrary_int::UInt); +pub struct ClockTimeoutLimit(pub arbitrary_int::UInt); -impl ClkTimeoutLimit { +impl ClockTimeoutLimit { pub fn new(value: u20) -> Self { - ClkTimeoutLimit(arbitrary_int::UInt::::new(value.value())) + ClockTimeoutLimit(arbitrary_int::UInt::::new(value.value())) } pub fn value(&self) -> u20 { self.0 @@ -591,7 +591,7 @@ pub mod slave { #[repr(C)] pub struct I2c { control: Control, - clkscale: ClkScale, + clkscale: ClockScale, words: Words, address: Address, data: Data, @@ -617,7 +617,7 @@ pub struct I2c { #[mmio(Write)] fifo_clear: FifoClear, timing_config: TimingConfig, - clk_timeout_limit: ClkTimeoutLimit, + clk_timeout_limit: ClockTimeoutLimit, _reserved_0: [u32; 0x2D], diff --git a/src/ioconfig/mod.rs b/src/ioconfig/mod.rs index d5b7d8e..b368ea1 100644 --- a/src/ioconfig/mod.rs +++ b/src/ioconfig/mod.rs @@ -1,3 +1,3 @@ -pub use regs::{FilterClkSel, FilterType}; +pub use regs::{FilterClockSelect, FilterType}; pub mod regs; diff --git a/src/ioconfig/regs.rs b/src/ioconfig/regs.rs index 75dd82e..6798c31 100644 --- a/src/ioconfig/regs.rs +++ b/src/ioconfig/regs.rs @@ -1,6 +1,6 @@ use core::marker::PhantomData; -use crate::{NUM_PORT_A, NUM_PORT_B, gpio::PinId}; +use crate::{NUM_PORT_A, NUM_PORT_B, gpio::DynPinId}; #[cfg(feature = "vor4x")] use crate::{NUM_PORT_DEFAULT, NUM_PORT_G}; @@ -24,7 +24,7 @@ pub enum FilterType { #[derive(Debug, PartialEq, Eq)] #[bitbybit::bitenum(u3, exhaustive = true)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum FilterClkSel { +pub enum FilterClockSelect { SysClk = 0, Clk1 = 1, Clk2 = 2, @@ -46,7 +46,7 @@ pub enum Pull { #[derive(Debug, Eq, PartialEq)] #[bitbybit::bitenum(u2, exhaustive = true)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum FunSel { +pub enum FunctionSelect { Sel0 = 0b00, Sel1 = 0b01, Sel2 = 0b10, @@ -58,7 +58,7 @@ pub struct Config { #[bit(16, rw)] io_disable: bool, #[bits(13..=14, rw)] - funsel: FunSel, + funsel: FunctionSelect, #[bit(12, rw)] pull_when_output_active: bool, #[bit(11, rw)] @@ -75,7 +75,7 @@ pub struct Config { #[bit(6, rw)] invert_input: bool, #[bits(3..=5, rw)] - filter_clk_sel: FilterClkSel, + filter_clk_sel: FilterClockSelect, #[bits(0..=2, rw)] filter_type: Option, } @@ -136,7 +136,7 @@ impl IoConfig { } impl MmioIoConfig<'_> { - pub fn read_pin_config(&self, id: PinId) -> Config { + pub fn read_pin_config(&self, id: DynPinId) -> Config { let offset = id.offset(); match id.port() { crate::Port::A => unsafe { self.read_port_a_unchecked(offset) }, @@ -154,12 +154,12 @@ impl MmioIoConfig<'_> { } } - pub fn modify_pin_config Config>(&mut self, id: PinId, f: F) { + pub fn modify_pin_config Config>(&mut self, id: DynPinId, f: F) { let config = self.read_pin_config(id); self.write_pin_config(id, f(config)) } - pub fn write_pin_config(&mut self, id: PinId, config: Config) { + pub fn write_pin_config(&mut self, id: DynPinId, config: Config) { let offset = id.offset(); match id.port() { crate::Port::A => unsafe { self.write_port_a_unchecked(offset, config) }, diff --git a/src/lib.rs b/src/lib.rs index c3514d0..f0ccf26 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,3 +1,4 @@ +//! Shared HAL code for Vorago VA108xx and VA416xx microcontrollers. #![no_std] #[cfg(feature = "vor4x")] pub mod clock; @@ -21,7 +22,7 @@ pub use sysconfig::{ #[cfg(not(feature = "_family-selected"))] compile_error!("no Vorago CPU family was select. Choices: vor1x or vor4x"); -pub use ioconfig::regs::FunSel; +pub use ioconfig::regs::FunctionSelect; #[cfg(feature = "vor1x")] use va108xx as pac; #[cfg(feature = "vor4x")] diff --git a/src/pins.rs b/src/pins.rs index c947706..3269348 100644 --- a/src/pins.rs +++ b/src/pins.rs @@ -1,6 +1,6 @@ use crate::sysconfig::reset_peripheral_for_cycles; -pub use crate::gpio::{Pin, PinId, PinIdProvider, Port}; +pub use crate::gpio::{DynPinId, Port}; use crate::PeripheralSelect; use crate::sealed::Sealed; @@ -9,8 +9,45 @@ use va108xx as pac; #[cfg(feature = "vor4x")] use va416xx as pac; -pub trait PinMarker: Sealed { - const ID: PinId; +/// Trait implemented by data structures associated with pin identification. +pub trait PinId { + const ID: crate::gpio::ll::DynPinId; +} + +pub trait AnyPin: Sealed { + const ID: DynPinId; +} + +/// Primary Pin structure for the physical pins exposed by Vorago MCUs. +/// +/// This pin structure is only used for resource management and does not do anything on its +/// own. +pub struct Pin { + phantom: core::marker::PhantomData, +} + +impl AnyPin for Pin { + const ID: DynPinId = Id::ID; +} + +impl Pin { + #[allow(clippy::new_without_default)] + #[doc(hidden)] + pub const fn __new() -> Self { + Self { + phantom: core::marker::PhantomData, + } + } + + /// Create a new pin instance. + /// + /// # Safety + /// + /// This circumvents ownership rules of the HAL and allows creating multiple instances + /// of the same pin. + pub const unsafe fn steal() -> Self { + Self::__new() + } } macro_rules! pin_id { @@ -22,18 +59,14 @@ macro_rules! pin_id { pub enum $Id {} impl $crate::sealed::Sealed for $Id {} - impl PinIdProvider for $Id { - const ID: PinId = PinId::new_unchecked($Port, $num); - } - - impl PinMarker for Pin<$Id> { - const ID: PinId = $Id::ID; + impl PinId for $Id { + const ID: DynPinId = DynPinId::new_unchecked($Port, $num); } } }; } -impl Sealed for Pin {} +impl Sealed for Pin {} pin_id!(Pa0, Port::A, 0); pin_id!(Pa1, Port::A, 1); diff --git a/src/pwm.rs b/src/pwm.rs index 408024b..9184d73 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -7,7 +7,7 @@ use crate::timer::regs::{EnableControl, StatusSelect}; use crate::{PeripheralSelect, enable_peripheral_clock}; use crate::time::Hertz; -use crate::timer::{self, TimId, TimMarker, TimPin}; +use crate::timer::{self, TimId, TimInstance, TimPin}; const DUTY_MAX: u16 = u16::MAX; @@ -46,7 +46,7 @@ pub struct PwmPin { impl PwmPin { /// Create a new PWM pin - pub fn new( + pub fn new( _pin: Pin, _tim: Tim, #[cfg(feature = "vor1x")] sys_clk: Hertz, diff --git a/src/spi/mod.rs b/src/spi/mod.rs index 16dc12b..e0bdcf2 100644 --- a/src/spi/mod.rs +++ b/src/spi/mod.rs @@ -1,12 +1,10 @@ -use crate::FunSel; -use crate::gpio::{IoPeriphPin, PinId}; -use crate::{ - PeripheralSelect, enable_peripheral_clock, pins::PinMarker, sealed::Sealed, time::Hertz, -}; +use crate::FunctionSelect; +use crate::gpio::{DynPinId, IoPeriphPin}; +use crate::{PeripheralSelect, enable_peripheral_clock, pins::AnyPin, sealed::Sealed, time::Hertz}; use core::{convert::Infallible, fmt::Debug, marker::PhantomData}; use embedded_hal::spi::{MODE_0, Mode}; -use regs::{ClkPrescaler, Data, FifoClear, WordSize}; +use regs::{ClockPrescaler, Data, FifoClear, WordSize}; #[cfg(feature = "vor1x")] use va108xx as pac; #[cfg(feature = "vor4x")] @@ -16,7 +14,7 @@ pub use regs::{Bank, HwChipSelectId}; pub mod regs; -pub fn configure_pin_as_hw_cs_pin(_pin: P) -> HwChipSelectId { +pub fn configure_pin_as_hw_cs_pin(_pin: P) -> HwChipSelectId { IoPeriphPin::new(P::ID, P::FUN_SEL, None); P::CS_ID } @@ -25,25 +23,25 @@ pub fn configure_pin_as_hw_cs_pin(_pin: P) -> HwChi // Pins and traits. //================================================================================================== -pub trait PinSck: PinMarker { +pub trait PinSck: AnyPin { const SPI_ID: Bank; - const FUN_SEL: FunSel; + const FUN_SEL: FunctionSelect; } -pub trait PinMosi: PinMarker { +pub trait PinMosi: AnyPin { const SPI_ID: Bank; - const FUN_SEL: FunSel; + const FUN_SEL: FunctionSelect; } -pub trait PinMiso: PinMarker { +pub trait PinMiso: AnyPin { const SPI_ID: Bank; - const FUN_SEL: FunSel; + const FUN_SEL: FunctionSelect; } pub trait HwCsProvider { - const PIN_ID: PinId; + const PIN_ID: DynPinId; const SPI_ID: Bank; - const FUN_SEL: FunSel; + const FUN_SEL: FunctionSelect; const CS_ID: HwChipSelectId; } @@ -77,9 +75,9 @@ mod macros { impl crate::sealed::Sealed for $name {} impl HwCsProvider for $name { - const PIN_ID: PinId = <$pin_id as PinIdProvider>::ID; + const PIN_ID: DynPinId = <$pin_id as PinId>::ID; const SPI_ID: Bank = $spi_id; - const FUN_SEL: FunSel = $fun_sel; + const FUN_SEL: FunctionSelect = $fun_sel; const CS_ID: HwChipSelectId = $cs_id; } }; @@ -90,9 +88,9 @@ mod macros { ($SpiId:path, $(($Px:ident, $FunSel:path, $HwCsIdent:path)$(,)?)+) => { $( impl HwCsProvider for Pin<$Px> { - const PIN_ID: PinId = $Px::ID; + const PIN_ID: DynPinId = $Px::ID; const SPI_ID: Bank = $SpiId; - const FUN_SEL: FunSel = $FunSel; + const FUN_SEL: FunctionSelect = $FunSel; const CS_ID: HwChipSelectId = $HwCsIdent; } )+ @@ -119,7 +117,7 @@ pub const DEFAULT_CLK_DIV: u16 = 2; /// Common trait implemented by all PAC peripheral access structures. The register block /// format is the same for all SPI blocks. -pub trait SpiMarker: Sealed { +pub trait SpiInstance: Sealed { const ID: Bank; const PERIPH_SEL: PeripheralSelect; } @@ -129,7 +127,7 @@ pub type Spi0 = pac::Spia; #[cfg(feature = "vor4x")] pub type Spi0 = pac::Spi0; -impl SpiMarker for Spi0 { +impl SpiInstance for Spi0 { const ID: Bank = Bank::Spi0; const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi0; } @@ -140,7 +138,7 @@ pub type Spi1 = pac::Spib; #[cfg(feature = "vor4x")] pub type Spi1 = pac::Spi1; -impl SpiMarker for Spi1 { +impl SpiInstance for Spi1 { const ID: Bank = Bank::Spi1; const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi1; } @@ -151,14 +149,14 @@ pub type Spi2 = pac::Spic; #[cfg(feature = "vor4x")] pub type Spi2 = pac::Spi2; -impl SpiMarker for Spi2 { +impl SpiInstance for Spi2 { const ID: Bank = Bank::Spi2; const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi2; } impl Sealed for Spi2 {} #[cfg(feature = "vor4x")] -impl SpiMarker for pac::Spi3 { +impl SpiInstance for pac::Spi3 { const ID: Bank = Bank::Spi3; const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi3; } @@ -173,7 +171,7 @@ pub trait TransferConfigProvider { fn sod(&mut self, sod: bool); fn blockmode(&mut self, blockmode: bool); fn mode(&mut self, mode: Mode); - fn clk_cfg(&mut self, clk_cfg: SpiClkConfig); + fn clk_cfg(&mut self, clk_cfg: SpiClockConfig); fn hw_cs_id(&self) -> u8; } @@ -182,7 +180,7 @@ pub trait TransferConfigProvider { #[derive(Copy, Clone, Debug)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct TransferConfig { - pub clk_cfg: Option, + pub clk_cfg: Option, pub mode: Option, pub sod: bool, /// If this is enabled, all data in the FIFO is transmitted in a single frame unless @@ -197,7 +195,7 @@ pub struct TransferConfig { impl TransferConfig { pub fn new_with_hw_cs( - clk_cfg: Option, + clk_cfg: Option, mode: Option, blockmode: bool, bmstall: bool, @@ -219,7 +217,7 @@ impl TransferConfig { #[derive(Debug, Copy, Clone)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct SpiConfig { - clk: SpiClkConfig, + clk: SpiClockConfig, // SPI mode configuration pub init_mode: Mode, /// If this is enabled, all data in the FIFO is transmitted in a single frame unless @@ -244,7 +242,7 @@ impl Default for SpiConfig { blockmode: true, bmstall: true, // Default value is definitely valid. - clk: SpiClkConfig::from_div(DEFAULT_CLK_DIV).unwrap(), + clk: SpiClockConfig::from_div(DEFAULT_CLK_DIV).unwrap(), slave_output_disable: Default::default(), loopback_mode: Default::default(), master_delayer_capture: Default::default(), @@ -273,7 +271,7 @@ impl SpiConfig { self } - pub fn clk_cfg(mut self, clk_cfg: SpiClkConfig) -> Self { + pub fn clk_cfg(mut self, clk_cfg: SpiClockConfig) -> Self { self.clk = clk_cfg; self } @@ -290,13 +288,13 @@ impl SpiConfig { /// Configuration trait for the Word Size /// used by the SPI peripheral -pub trait WordProvider: Copy + Default + Into + TryFrom + 'static { +pub trait SpiWord: Copy + Default + Into + TryFrom + 'static { const MASK: u32; const WORD_SIZE: regs::WordSize; fn word_reg() -> u8; } -impl WordProvider for u8 { +impl SpiWord for u8 { const MASK: u32 = 0xff; const WORD_SIZE: regs::WordSize = regs::WordSize::EightBits; fn word_reg() -> u8 { @@ -304,7 +302,7 @@ impl WordProvider for u8 { } } -impl WordProvider for u16 { +impl SpiWord for u16 { const MASK: u32 = 0xffff; const WORD_SIZE: regs::WordSize = regs::WordSize::SixteenBits; fn word_reg() -> u8 { @@ -358,12 +356,12 @@ pub fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) { #[derive(Debug, Copy, Clone, PartialEq, Eq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub struct SpiClkConfig { +pub struct SpiClockConfig { prescale_val: u8, scrdv: u8, } -impl SpiClkConfig { +impl SpiClockConfig { pub fn prescale_val(&self) -> u8 { self.prescale_val } @@ -372,7 +370,7 @@ impl SpiClkConfig { } } -impl SpiClkConfig { +impl SpiClockConfig { pub fn new(prescale_val: u8, scrdv: u8) -> Self { Self { prescale_val, @@ -380,7 +378,7 @@ impl SpiClkConfig { } } - pub fn from_div(div: u16) -> Result { + pub fn from_div(div: u16) -> Result { spi_clk_config_from_div(div) } @@ -402,7 +400,7 @@ impl SpiClkConfig { #[derive(Debug, thiserror::Error)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum SpiClkConfigError { +pub enum SpiClockConfigError { #[error("division by zero")] DivIsZero, #[error("divide value is not even")] @@ -412,12 +410,12 @@ pub enum SpiClkConfigError { } #[inline] -pub fn spi_clk_config_from_div(mut div: u16) -> Result { +pub fn spi_clk_config_from_div(mut div: u16) -> Result { if div == 0 { - return Err(SpiClkConfigError::DivIsZero); + return Err(SpiClockConfigError::DivIsZero); } if div % 2 != 0 { - return Err(SpiClkConfigError::DivideValueNotEven); + return Err(SpiClockConfigError::DivideValueNotEven); } let mut prescale_val = 0; @@ -430,14 +428,14 @@ pub fn spi_clk_config_from_div(mut div: u16) -> Result u8::MAX as u16 + 1 { - return Err(SpiClkConfigError::ScrdvValueTooLarge); + return Err(SpiClockConfigError::ScrdvValueTooLarge); } - Ok(SpiClkConfig { + Ok(SpiClockConfig { prescale_val: prescale_val as u8, scrdv: (div - 1) as u8, }) @@ -486,7 +484,7 @@ pub struct Spi { word: PhantomData, } -impl Spi +impl Spi where >::Error: core::fmt::Debug, { @@ -496,7 +494,7 @@ where /// /// * `spi` - SPI bus to use /// * `spi_cfg` - Configuration specific to the SPI bus - pub fn new_for_rom( + pub fn new_for_rom( spi: SpiI, spi_cfg: SpiConfig, ) -> Result { @@ -519,7 +517,7 @@ where /// * `pins` - Pins to be used for SPI transactions. These pins are consumed /// to ensure the pins can not be used for other purposes anymore /// * `spi_cfg` - Configuration specific to the SPI bus - pub fn new( + pub fn new( spi: SpiI, _pins: (Sck, Miso, Mosi), spi_cfg: SpiConfig, @@ -533,7 +531,7 @@ where Ok(Self::new_generic(spi, spi_cfg)) } - pub fn new_generic(_spi: SpiI, spi_cfg: SpiConfig) -> Self { + pub fn new_generic(_spi: SpiI, spi_cfg: SpiConfig) -> Self { enable_peripheral_clock(SpiI::PERIPH_SEL); let mut regs = regs::Spi::new_mmio(SpiI::ID); let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(spi_cfg.init_mode); @@ -559,7 +557,7 @@ where .with_lbm(spi_cfg.loopback_mode) .build(), ); - regs.write_clkprescale(ClkPrescaler::new(spi_cfg.clk.prescale_val)); + regs.write_clkprescale(ClockPrescaler::new(spi_cfg.clk.prescale_val)); regs.write_fifo_clear( FifoClear::builder() .with_tx_fifo(true) @@ -584,13 +582,13 @@ where } #[inline] - pub fn cfg_clock(&mut self, cfg: SpiClkConfig) { + pub fn cfg_clock(&mut self, cfg: SpiClockConfig) { self.regs.modify_ctrl0(|mut value| { value.set_scrdv(cfg.scrdv); value }); self.regs - .write_clkprescale(regs::ClkPrescaler::new(cfg.prescale_val)); + .write_clkprescale(regs::ClockPrescaler::new(cfg.prescale_val)); } pub fn set_fill_word(&mut self, fill_word: Word) { @@ -598,7 +596,7 @@ where } #[inline] - pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError> { + pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClockConfigError> { let val = spi_clk_config_from_div(div)?; self.cfg_clock(val); Ok(()) @@ -772,9 +770,9 @@ where } } -impl SpiLowLevel for Spi +impl SpiLowLevel for Spi where - >::Error: core::fmt::Debug, + >::Error: core::fmt::Debug, { #[inline(always)] fn write_fifo(&mut self, data: u32) -> nb::Result<(), Infallible> { @@ -804,11 +802,11 @@ where } } -impl embedded_hal::spi::ErrorType for Spi { +impl embedded_hal::spi::ErrorType for Spi { type Error = Infallible; } -impl embedded_hal::spi::SpiBus for Spi +impl embedded_hal::spi::SpiBus for Spi where >::Error: core::fmt::Debug, { diff --git a/src/spi/pins_vor1x.rs b/src/spi/pins_vor1x.rs index 15f0bea..6f564bf 100644 --- a/src/spi/pins_vor1x.rs +++ b/src/spi/pins_vor1x.rs @@ -1,6 +1,6 @@ use super::{HwCsProvider, PinMiso, PinMosi, PinSck}; -use crate::FunSel; -use crate::gpio::{PinId, PinIdProvider}; +use crate::FunctionSelect; +use crate::gpio::{DynPinId, PinId}; use crate::pins::{ Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, Pa16, Pa17, Pa18, Pa19, Pa20, Pa21, Pa22, Pa23, Pa24, Pa25, @@ -14,65 +14,65 @@ use super::{Bank, HwChipSelectId}; impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi0; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi0; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi0; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } hw_cs_pins!( Bank::Spi0, - (Pb0, FunSel::Sel2, HwChipSelectId::Id1), - (Pb1, FunSel::Sel2, HwChipSelectId::Id2), - (Pb2, FunSel::Sel2, HwChipSelectId::Id3), - (Pb3, FunSel::Sel2, HwChipSelectId::Id4), - (Pb4, FunSel::Sel2, HwChipSelectId::Id5), - (Pb5, FunSel::Sel2, HwChipSelectId::Id6), - (Pb6, FunSel::Sel2, HwChipSelectId::Id0), - (Pa24, FunSel::Sel1, HwChipSelectId::Id4), - (Pa25, FunSel::Sel1, HwChipSelectId::Id3), - (Pa26, FunSel::Sel1, HwChipSelectId::Id2), - (Pa27, FunSel::Sel1, HwChipSelectId::Id1), - (Pa28, FunSel::Sel1, HwChipSelectId::Id0), + (Pb0, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pb1, FunctionSelect::Sel2, HwChipSelectId::Id2), + (Pb2, FunctionSelect::Sel2, HwChipSelectId::Id3), + (Pb3, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pb4, FunctionSelect::Sel2, HwChipSelectId::Id5), + (Pb5, FunctionSelect::Sel2, HwChipSelectId::Id6), + (Pb6, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pa24, FunctionSelect::Sel1, HwChipSelectId::Id4), + (Pa25, FunctionSelect::Sel1, HwChipSelectId::Id3), + (Pa26, FunctionSelect::Sel1, HwChipSelectId::Id2), + (Pa27, FunctionSelect::Sel1, HwChipSelectId::Id1), + (Pa28, FunctionSelect::Sel1, HwChipSelectId::Id0), ); hw_cs_multi_pin!( PinPb0SpiaHwCsId1, Pb0, Bank::Spi0, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id1 ); hw_cs_multi_pin!( PinPb1SpiaHwCsId2, Pb1, Bank::Spi0, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id2 ); hw_cs_multi_pin!( PinPb2SpiaHwCsId3, Pb2, Bank::Spi0, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id3 ); @@ -80,21 +80,21 @@ hw_cs_multi_pin!( PinPa21SpiaHwCsId7, Pa21, Bank::Spi0, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id7 ); hw_cs_multi_pin!( PinPa22SpiaHwCsId6, Pa22, Bank::Spi0, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id6 ); hw_cs_multi_pin!( PinPa23SpiaHwCsId5, Pa23, Bank::Spi0, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id5 ); @@ -102,15 +102,15 @@ hw_cs_multi_pin!( impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } pub type SpiBPortASck = Pin; @@ -119,69 +119,69 @@ pub type SpiBPortAMiso = Pin; impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } // TODO: Need to deal with these duplications.. hw_cs_pins!( Bank::Spi1, - (Pb16, FunSel::Sel1, HwChipSelectId::Id0), - (Pb15, FunSel::Sel1, HwChipSelectId::Id1), - (Pb14, FunSel::Sel1, HwChipSelectId::Id2), - (Pb13, FunSel::Sel1, HwChipSelectId::Id3), - (Pa17, FunSel::Sel2, HwChipSelectId::Id0), - (Pa16, FunSel::Sel2, HwChipSelectId::Id1), - (Pa15, FunSel::Sel2, HwChipSelectId::Id2), - (Pa14, FunSel::Sel2, HwChipSelectId::Id3), - (Pa13, FunSel::Sel2, HwChipSelectId::Id4), - (Pa12, FunSel::Sel2, HwChipSelectId::Id5), - (Pa11, FunSel::Sel2, HwChipSelectId::Id6), - (Pa10, FunSel::Sel2, HwChipSelectId::Id7), - (Pa23, FunSel::Sel2, HwChipSelectId::Id5), - (Pa22, FunSel::Sel2, HwChipSelectId::Id6), - (Pa21, FunSel::Sel2, HwChipSelectId::Id7), + (Pb16, FunctionSelect::Sel1, HwChipSelectId::Id0), + (Pb15, FunctionSelect::Sel1, HwChipSelectId::Id1), + (Pb14, FunctionSelect::Sel1, HwChipSelectId::Id2), + (Pb13, FunctionSelect::Sel1, HwChipSelectId::Id3), + (Pa17, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pa16, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pa15, FunctionSelect::Sel2, HwChipSelectId::Id2), + (Pa14, FunctionSelect::Sel2, HwChipSelectId::Id3), + (Pa13, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pa12, FunctionSelect::Sel2, HwChipSelectId::Id5), + (Pa11, FunctionSelect::Sel2, HwChipSelectId::Id6), + (Pa10, FunctionSelect::Sel2, HwChipSelectId::Id7), + (Pa23, FunctionSelect::Sel2, HwChipSelectId::Id5), + (Pa22, FunctionSelect::Sel2, HwChipSelectId::Id6), + (Pa21, FunctionSelect::Sel2, HwChipSelectId::Id7), ); hw_cs_multi_pin!( PinPb0SpibHwCsId2, Pb0, Bank::Spi1, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id2 ); hw_cs_multi_pin!( PinPb1SpibHwCsId1, Pb1, Bank::Spi1, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id1 ); hw_cs_multi_pin!( PinPb2SpibHwCsId0, Pb2, Bank::Spi1, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id0 ); @@ -189,21 +189,21 @@ hw_cs_multi_pin!( PinPb10SpibHwCsId6, Pb10, Bank::Spi1, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id6 ); hw_cs_multi_pin!( PinPb11SpibHwCsId5, Pb11, Bank::Spi1, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id5 ); hw_cs_multi_pin!( PinPb12SpibHwCsId4, Pb12, Bank::Spi1, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id4 ); @@ -211,21 +211,21 @@ hw_cs_multi_pin!( PinPb10SpibHwCsId2, Pb10, Bank::Spi1, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id2 ); hw_cs_multi_pin!( PinPb11SpibHwCsId1, Pb11, Bank::Spi1, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id1 ); hw_cs_multi_pin!( PinPb12SpibHwCsId0, Pb12, Bank::Spi1, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id0 ); @@ -233,21 +233,21 @@ hw_cs_multi_pin!( PinPa21SpibHwCsId7, Pa21, Bank::Spi1, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id7 ); hw_cs_multi_pin!( PinPa22SpibHwCsId6, Pa22, Bank::Spi1, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id6 ); hw_cs_multi_pin!( PinPa23SpibHwCsId5, Pa23, Bank::Spi1, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id5 ); @@ -255,35 +255,35 @@ hw_cs_multi_pin!( hw_cs_pins!( Bank::Spi2, - (Pb9, FunSel::Sel3, HwChipSelectId::Id1), - (Pb8, FunSel::Sel3, HwChipSelectId::Id2), - (Pb7, FunSel::Sel3, HwChipSelectId::Id3), - (Pb23, FunSel::Sel3, HwChipSelectId::Id2), - (Pb22, FunSel::Sel3, HwChipSelectId::Id1), - (Pa20, FunSel::Sel1, HwChipSelectId::Id1), - (Pa19, FunSel::Sel1, HwChipSelectId::Id2), - (Pb18, FunSel::Sel1, HwChipSelectId::Id3), + (Pb9, FunctionSelect::Sel3, HwChipSelectId::Id1), + (Pb8, FunctionSelect::Sel3, HwChipSelectId::Id2), + (Pb7, FunctionSelect::Sel3, HwChipSelectId::Id3), + (Pb23, FunctionSelect::Sel3, HwChipSelectId::Id2), + (Pb22, FunctionSelect::Sel3, HwChipSelectId::Id1), + (Pa20, FunctionSelect::Sel1, HwChipSelectId::Id1), + (Pa19, FunctionSelect::Sel1, HwChipSelectId::Id2), + (Pb18, FunctionSelect::Sel1, HwChipSelectId::Id3), ); hw_cs_multi_pin!( PinPa21SpicHwCsId3, Pa21, Bank::Spi2, - FunSel::Sel3, + FunctionSelect::Sel3, HwChipSelectId::Id3 ); hw_cs_multi_pin!( PinPa22SpicHwCsId2, Pa22, Bank::Spi2, - FunSel::Sel3, + FunctionSelect::Sel3, HwChipSelectId::Id2 ); hw_cs_multi_pin!( PinPa23SpicHwCsId1, Pa23, Bank::Spi2, - FunSel::Sel3, + FunctionSelect::Sel3, HwChipSelectId::Id1 ); @@ -291,13 +291,13 @@ hw_cs_multi_pin!( PinPa20SpicHwCsId1, Pa20, Bank::Spi2, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id1 ); hw_cs_multi_pin!( PinPa20SpicHwCsId4, Pa20, Bank::Spi2, - FunSel::Sel3, + FunctionSelect::Sel3, HwChipSelectId::Id4 ); diff --git a/src/spi/pins_vor4x.rs b/src/spi/pins_vor4x.rs index 4c8a9df..c6323d9 100644 --- a/src/spi/pins_vor4x.rs +++ b/src/spi/pins_vor4x.rs @@ -1,6 +1,6 @@ use crate::{ - FunSel, - gpio::{Pin, PinId, PinIdProvider}, + FunctionSelect, + gpio::{DynPinId, Pin, PinId}, pins::{ Pa0, Pa1, Pa2, Pa3, Pa4, Pa5, Pa6, Pa7, Pa8, Pa9, Pb0, Pb1, Pb2, Pb3, Pb4, Pb12, Pb13, Pb14, Pb15, Pc0, Pc1, Pc7, Pc8, Pc9, Pc10, Pc11, Pe5, Pe6, Pe7, Pe8, Pe9, Pe12, Pe13, Pe14, @@ -17,122 +17,125 @@ use super::{Bank, HwChipSelectId, HwCsProvider, PinMiso, PinMosi, PinSck}; impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } hw_cs_pins!( Bank::Spi0, - (Pb14, FunSel::Sel1, HwChipSelectId::Id0), - (Pb13, FunSel::Sel1, HwChipSelectId::Id1), - (Pb12, FunSel::Sel1, HwChipSelectId::Id2), + (Pb14, FunctionSelect::Sel1, HwChipSelectId::Id0), + (Pb13, FunctionSelect::Sel1, HwChipSelectId::Id1), + (Pb12, FunctionSelect::Sel1, HwChipSelectId::Id2), ); #[cfg(not(feature = "va41628"))] -hw_cs_pins!(Bank::Spi0, (Pb11, FunSel::Sel1, HwChipSelectId::Id3)); +hw_cs_pins!( + Bank::Spi0, + (Pb11, FunctionSelect::Sel1, HwChipSelectId::Id3) +); // SPI1 #[cfg(not(feature = "va41628"))] impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } #[cfg(not(feature = "va41628"))] impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } #[cfg(not(feature = "va41628"))] impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } #[cfg(not(feature = "va41628"))] impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } #[cfg(not(feature = "va41628"))] impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } #[cfg(not(feature = "va41628"))] impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } hw_cs_pins!( Bank::Spi1, - (Pb4, FunSel::Sel3, HwChipSelectId::Id3), - (Pb3, FunSel::Sel3, HwChipSelectId::Id4), - (Pb2, FunSel::Sel3, HwChipSelectId::Id5), - (Pb1, FunSel::Sel3, HwChipSelectId::Id6), - (Pb0, FunSel::Sel3, HwChipSelectId::Id7), - (Pc8, FunSel::Sel2, HwChipSelectId::Id0), - (Pc7, FunSel::Sel2, HwChipSelectId::Id1), - (Pe12, FunSel::Sel2, HwChipSelectId::Id0), - (Pe9, FunSel::Sel2, HwChipSelectId::Id3), - (Pe8, FunSel::Sel2, HwChipSelectId::Id4), - (Pe7, FunSel::Sel3, HwChipSelectId::Id5), - (Pe6, FunSel::Sel3, HwChipSelectId::Id6), - (Pe5, FunSel::Sel3, HwChipSelectId::Id7), - (Pg2, FunSel::Sel2, HwChipSelectId::Id0), + (Pb4, FunctionSelect::Sel3, HwChipSelectId::Id3), + (Pb3, FunctionSelect::Sel3, HwChipSelectId::Id4), + (Pb2, FunctionSelect::Sel3, HwChipSelectId::Id5), + (Pb1, FunctionSelect::Sel3, HwChipSelectId::Id6), + (Pb0, FunctionSelect::Sel3, HwChipSelectId::Id7), + (Pc8, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pc7, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pe12, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pe9, FunctionSelect::Sel2, HwChipSelectId::Id3), + (Pe8, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pe7, FunctionSelect::Sel3, HwChipSelectId::Id5), + (Pe6, FunctionSelect::Sel3, HwChipSelectId::Id6), + (Pe5, FunctionSelect::Sel3, HwChipSelectId::Id7), + (Pg2, FunctionSelect::Sel2, HwChipSelectId::Id0), ); #[cfg(not(feature = "va41628"))] hw_cs_pins!( Bank::Spi1, - (Pb7, FunSel::Sel3, HwChipSelectId::Id0), - (Pb6, FunSel::Sel3, HwChipSelectId::Id1), - (Pb5, FunSel::Sel3, HwChipSelectId::Id2), - (Pe11, FunSel::Sel2, HwChipSelectId::Id1), - (Pe10, FunSel::Sel2, HwChipSelectId::Id2), + (Pb7, FunctionSelect::Sel3, HwChipSelectId::Id0), + (Pb6, FunctionSelect::Sel3, HwChipSelectId::Id1), + (Pb5, FunctionSelect::Sel3, HwChipSelectId::Id2), + (Pe11, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pe10, FunctionSelect::Sel2, HwChipSelectId::Id2), ); #[cfg(not(feature = "va41628"))] @@ -140,7 +143,7 @@ hw_cs_multi_pin!( PinPf2Spi1HwCsId0, Pf2, Bank::Spi2, - FunSel::Sel1, + FunctionSelect::Sel1, HwChipSelectId::Id0 ); @@ -148,51 +151,51 @@ hw_cs_multi_pin!( impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi2; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi2; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi2; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } #[cfg(not(feature = "va41628"))] impl PinSck for Pin { const SPI_ID: Bank = Bank::Spi2; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } #[cfg(not(feature = "va41628"))] impl PinMosi for Pin { const SPI_ID: Bank = Bank::Spi2; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } #[cfg(not(feature = "va41628"))] impl PinMiso for Pin { const SPI_ID: Bank = Bank::Spi2; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } hw_cs_pins!( Bank::Spi1, - (Pa4, FunSel::Sel2, HwChipSelectId::Id0), - (Pa3, FunSel::Sel2, HwChipSelectId::Id1), - (Pa2, FunSel::Sel2, HwChipSelectId::Id2), - (Pa1, FunSel::Sel2, HwChipSelectId::Id3), - (Pa0, FunSel::Sel2, HwChipSelectId::Id4), - (Pa8, FunSel::Sel2, HwChipSelectId::Id5), - (Pa9, FunSel::Sel2, HwChipSelectId::Id6), - (Pf0, FunSel::Sel2, HwChipSelectId::Id4), - (Pf1, FunSel::Sel2, HwChipSelectId::Id3), + (Pa4, FunctionSelect::Sel2, HwChipSelectId::Id0), + (Pa3, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pa2, FunctionSelect::Sel2, HwChipSelectId::Id2), + (Pa1, FunctionSelect::Sel2, HwChipSelectId::Id3), + (Pa0, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pa8, FunctionSelect::Sel2, HwChipSelectId::Id5), + (Pa9, FunctionSelect::Sel2, HwChipSelectId::Id6), + (Pf0, FunctionSelect::Sel2, HwChipSelectId::Id4), + (Pf1, FunctionSelect::Sel2, HwChipSelectId::Id3), ); #[cfg(not(feature = "va41628"))] hw_cs_pins!( Bank::Spi1, - (Pf3, FunSel::Sel2, HwChipSelectId::Id1), - (Pf4, FunSel::Sel2, HwChipSelectId::Id0), + (Pf3, FunctionSelect::Sel2, HwChipSelectId::Id1), + (Pf4, FunctionSelect::Sel2, HwChipSelectId::Id0), ); #[cfg(not(feature = "va41628"))] @@ -200,6 +203,6 @@ hw_cs_multi_pin!( PinPf2Spi2HwCsId2, Pf2, Bank::Spi2, - FunSel::Sel2, + FunctionSelect::Sel2, HwChipSelectId::Id2 ); diff --git a/src/spi/regs.rs b/src/spi/regs.rs index 667ad30..99d7d50 100644 --- a/src/spi/regs.rs +++ b/src/spi/regs.rs @@ -146,11 +146,11 @@ pub struct Status { /// are used as clock divisor values, and uneven values are truncated to the next even value. /// A value of 0 acts as a 1 for the divisor value. #[derive(Debug, Copy, Clone, PartialEq, Eq)] -pub struct ClkPrescaler(arbitrary_int::UInt); +pub struct ClockPrescaler(arbitrary_int::UInt); -impl ClkPrescaler { +impl ClockPrescaler { pub const fn new(value: u8) -> Self { - ClkPrescaler(arbitrary_int::UInt::::new(value as u32)) + ClockPrescaler(arbitrary_int::UInt::::new(value as u32)) } pub const fn value(&self) -> u8 { self.0.value() as u8 @@ -220,7 +220,7 @@ pub struct Spi { data: Data, #[mmio(PureRead)] status: Status, - clkprescale: ClkPrescaler, + clkprescale: ClockPrescaler, irq_enb: InterruptControl, /// Raw interrupt status. #[mmio(PureRead)] diff --git a/src/timer/mod.rs b/src/timer/mod.rs index af89408..d378b8c 100644 --- a/src/timer/mod.rs +++ b/src/timer/mod.rs @@ -9,7 +9,7 @@ use crate::sysconfig::enable_peripheral_clock; pub use regs::{CascadeSource, InvalidTimerIndex, TimId}; use crate::{enable_nvic_interrupt, sealed::Sealed, time::Hertz}; -use crate::{gpio::PinId, ioconfig::regs::FunSel, pins::PinMarker}; +use crate::{gpio::DynPinId, ioconfig::regs::FunctionSelect, pins::AnyPin}; use fugit::RateExtU32; #[cfg(feature = "vor1x")] @@ -69,13 +69,13 @@ pub enum CascadeSelect { // Valid TIM and PIN combinations //================================================================================================== -pub trait TimPin: PinMarker { - const PIN_ID: PinId; - const FUN_SEL: FunSel; +pub trait TimPin: AnyPin { + const PIN_ID: DynPinId; + const FUN_SEL: FunctionSelect; const TIM_ID: TimId; } -pub trait TimMarker: Sealed { +pub trait TimInstance: Sealed { // TIM ID ranging from 0 to 23 for 24 TIM peripherals const ID: TimId; #[cfg(feature = "vor4x")] @@ -93,14 +93,14 @@ pub trait TimMarker: Sealed { macro_rules! tim_marker { ($TIMX:path, $ID:expr) => { - impl TimMarker for $TIMX { + impl TimInstance for $TIMX { const ID: TimId = TimId::new_unchecked($ID); } impl Sealed for $TIMX {} }; ($TIMX:path, $ID:expr, $IrqId:ident) => { - impl TimMarker for $TIMX { + impl TimInstance for $TIMX { const ID: TimId = TimId::new_unchecked($ID); const IRQ: va416xx::Interrupt = va416xx::Interrupt::$IrqId; } @@ -163,7 +163,7 @@ cfg_if::cfg_if! { } } -pub trait ValidTimAndPin: Sealed {} +pub trait ValidTimAndPin: Sealed {} #[macro_use] mod macros { @@ -171,10 +171,10 @@ mod macros { ($Px:ident, $FunSel:path, $ID:expr) => { impl TimPin for Pin<$Px> where - $Px: PinIdProvider, + $Px: PinId, { - const PIN_ID: PinId = $Px::ID; - const FUN_SEL: FunSel = $FunSel; + const PIN_ID: DynPinId = $Px::ID; + const FUN_SEL: FunctionSelect = $FunSel; const TIM_ID: TimId = TimId::new_unchecked($ID); } }; @@ -207,7 +207,7 @@ impl CountdownTimer { /// [Self::enable_interrupt] and [Self::enable] API to set up and configure the countdown /// timer. #[cfg(feature = "vor1x")] - pub fn new(_tim: Tim, sys_clk: Hertz) -> Self { + pub fn new(_tim: Tim, sys_clk: Hertz) -> Self { enable_tim_clk(Tim::ID); assert_tim_reset_for_cycles(Tim::ID, 2); CountdownTimer { @@ -226,7 +226,7 @@ impl CountdownTimer { /// [Self::enable_interrupt] and [Self::enable] API to set up and configure the countdown /// timer. #[cfg(feature = "vor4x")] - pub fn new(_tim: Tim, clks: &crate::clock::Clocks) -> Self { + pub fn new(_tim: Tim, clks: &crate::clock::Clocks) -> Self { enable_tim_clk(Tim::ID); assert_tim_reset_for_cycles(Tim::ID, 2); CountdownTimer { diff --git a/src/timer/pins_vor1x.rs b/src/timer/pins_vor1x.rs index 3d4a480..abd22b3 100644 --- a/src/timer/pins_vor1x.rs +++ b/src/timer/pins_vor1x.rs @@ -1,56 +1,56 @@ use super::{TimId, TimPin}; -use crate::FunSel; +use crate::FunctionSelect; use crate::pins::{ - Pa0, Pa1, Pa2, Pa3, Pa4, Pa5, Pa6, Pa7, Pa8, Pa9, Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, Pa24, - Pa25, Pa26, Pa27, Pa28, Pa29, Pa30, Pa31, Pb0, Pb1, Pb2, Pb3, Pb4, Pb5, Pb6, Pb10, Pb11, Pb12, - Pb13, Pb14, Pb15, Pb16, Pb17, Pb18, Pb19, Pb20, Pb21, Pb22, Pb23, Pin, PinId, PinIdProvider, + DynPinId, Pa0, Pa1, Pa2, Pa3, Pa4, Pa5, Pa6, Pa7, Pa8, Pa9, Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, + Pa24, Pa25, Pa26, Pa27, Pa28, Pa29, Pa30, Pa31, Pb0, Pb1, Pb2, Pb3, Pb4, Pb5, Pb6, Pb10, Pb11, + Pb12, Pb13, Pb14, Pb15, Pb16, Pb17, Pb18, Pb19, Pb20, Pb21, Pb22, Pb23, Pin, PinId, }; -pin_and_tim!(Pa0, FunSel::Sel1, 0); -pin_and_tim!(Pa1, FunSel::Sel1, 1); -pin_and_tim!(Pa2, FunSel::Sel1, 2); -pin_and_tim!(Pa3, FunSel::Sel1, 3); -pin_and_tim!(Pa4, FunSel::Sel1, 4); -pin_and_tim!(Pa5, FunSel::Sel1, 5); -pin_and_tim!(Pa6, FunSel::Sel1, 6); -pin_and_tim!(Pa7, FunSel::Sel1, 7); -pin_and_tim!(Pa8, FunSel::Sel1, 8); -pin_and_tim!(Pa9, FunSel::Sel1, 9); -pin_and_tim!(Pa10, FunSel::Sel1, 10); -pin_and_tim!(Pa11, FunSel::Sel1, 11); -pin_and_tim!(Pa12, FunSel::Sel1, 12); -pin_and_tim!(Pa13, FunSel::Sel1, 13); -pin_and_tim!(Pa14, FunSel::Sel1, 14); -pin_and_tim!(Pa15, FunSel::Sel1, 15); +pin_and_tim!(Pa0, FunctionSelect::Sel1, 0); +pin_and_tim!(Pa1, FunctionSelect::Sel1, 1); +pin_and_tim!(Pa2, FunctionSelect::Sel1, 2); +pin_and_tim!(Pa3, FunctionSelect::Sel1, 3); +pin_and_tim!(Pa4, FunctionSelect::Sel1, 4); +pin_and_tim!(Pa5, FunctionSelect::Sel1, 5); +pin_and_tim!(Pa6, FunctionSelect::Sel1, 6); +pin_and_tim!(Pa7, FunctionSelect::Sel1, 7); +pin_and_tim!(Pa8, FunctionSelect::Sel1, 8); +pin_and_tim!(Pa9, FunctionSelect::Sel1, 9); +pin_and_tim!(Pa10, FunctionSelect::Sel1, 10); +pin_and_tim!(Pa11, FunctionSelect::Sel1, 11); +pin_and_tim!(Pa12, FunctionSelect::Sel1, 12); +pin_and_tim!(Pa13, FunctionSelect::Sel1, 13); +pin_and_tim!(Pa14, FunctionSelect::Sel1, 14); +pin_and_tim!(Pa15, FunctionSelect::Sel1, 15); -pin_and_tim!(Pa24, FunSel::Sel2, 16); -pin_and_tim!(Pa25, FunSel::Sel2, 17); -pin_and_tim!(Pa26, FunSel::Sel2, 18); -pin_and_tim!(Pa27, FunSel::Sel2, 19); -pin_and_tim!(Pa28, FunSel::Sel2, 20); -pin_and_tim!(Pa29, FunSel::Sel2, 21); -pin_and_tim!(Pa30, FunSel::Sel2, 22); -pin_and_tim!(Pa31, FunSel::Sel2, 23); +pin_and_tim!(Pa24, FunctionSelect::Sel2, 16); +pin_and_tim!(Pa25, FunctionSelect::Sel2, 17); +pin_and_tim!(Pa26, FunctionSelect::Sel2, 18); +pin_and_tim!(Pa27, FunctionSelect::Sel2, 19); +pin_and_tim!(Pa28, FunctionSelect::Sel2, 20); +pin_and_tim!(Pa29, FunctionSelect::Sel2, 21); +pin_and_tim!(Pa30, FunctionSelect::Sel2, 22); +pin_and_tim!(Pa31, FunctionSelect::Sel2, 23); -pin_and_tim!(Pb0, FunSel::Sel3, 0); -pin_and_tim!(Pb1, FunSel::Sel3, 1); -pin_and_tim!(Pb2, FunSel::Sel3, 2); -pin_and_tim!(Pb3, FunSel::Sel3, 3); -pin_and_tim!(Pb4, FunSel::Sel3, 4); -pin_and_tim!(Pb5, FunSel::Sel3, 5); -pin_and_tim!(Pb6, FunSel::Sel3, 6); +pin_and_tim!(Pb0, FunctionSelect::Sel3, 0); +pin_and_tim!(Pb1, FunctionSelect::Sel3, 1); +pin_and_tim!(Pb2, FunctionSelect::Sel3, 2); +pin_and_tim!(Pb3, FunctionSelect::Sel3, 3); +pin_and_tim!(Pb4, FunctionSelect::Sel3, 4); +pin_and_tim!(Pb5, FunctionSelect::Sel3, 5); +pin_and_tim!(Pb6, FunctionSelect::Sel3, 6); -pin_and_tim!(Pb10, FunSel::Sel3, 10); -pin_and_tim!(Pb11, FunSel::Sel3, 11); -pin_and_tim!(Pb12, FunSel::Sel3, 12); -pin_and_tim!(Pb13, FunSel::Sel3, 13); -pin_and_tim!(Pb14, FunSel::Sel3, 14); -pin_and_tim!(Pb15, FunSel::Sel3, 15); -pin_and_tim!(Pb16, FunSel::Sel3, 16); -pin_and_tim!(Pb17, FunSel::Sel3, 17); -pin_and_tim!(Pb18, FunSel::Sel3, 18); -pin_and_tim!(Pb19, FunSel::Sel3, 19); -pin_and_tim!(Pb20, FunSel::Sel3, 20); -pin_and_tim!(Pb21, FunSel::Sel3, 21); -pin_and_tim!(Pb22, FunSel::Sel3, 22); -pin_and_tim!(Pb23, FunSel::Sel3, 23); +pin_and_tim!(Pb10, FunctionSelect::Sel3, 10); +pin_and_tim!(Pb11, FunctionSelect::Sel3, 11); +pin_and_tim!(Pb12, FunctionSelect::Sel3, 12); +pin_and_tim!(Pb13, FunctionSelect::Sel3, 13); +pin_and_tim!(Pb14, FunctionSelect::Sel3, 14); +pin_and_tim!(Pb15, FunctionSelect::Sel3, 15); +pin_and_tim!(Pb16, FunctionSelect::Sel3, 16); +pin_and_tim!(Pb17, FunctionSelect::Sel3, 17); +pin_and_tim!(Pb18, FunctionSelect::Sel3, 18); +pin_and_tim!(Pb19, FunctionSelect::Sel3, 19); +pin_and_tim!(Pb20, FunctionSelect::Sel3, 20); +pin_and_tim!(Pb21, FunctionSelect::Sel3, 21); +pin_and_tim!(Pb22, FunctionSelect::Sel3, 22); +pin_and_tim!(Pb23, FunctionSelect::Sel3, 23); diff --git a/src/timer/pins_vor4x.rs b/src/timer/pins_vor4x.rs index 6ab1856..7ac72bf 100644 --- a/src/timer/pins_vor4x.rs +++ b/src/timer/pins_vor4x.rs @@ -1,9 +1,9 @@ -use super::{FunSel, TimId, TimPin}; +use super::{FunctionSelect, TimId, TimPin}; use crate::pins::{ - Pa0, Pa1, Pa2, Pa3, Pa4, Pa5, Pa6, Pa7, Pa8, Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, Pb0, Pb1, Pb2, - Pb3, Pb4, Pb12, Pb13, Pb14, Pb15, Pc0, Pc1, Pd10, Pd11, Pd12, Pd13, Pd14, Pd15, Pe0, Pe1, Pe2, - Pe3, Pe4, Pe5, Pe6, Pe7, Pe8, Pe9, Pe12, Pe13, Pe14, Pe15, Pf0, Pf1, Pf9, Pf11, Pf12, Pf13, - Pf14, Pf15, Pg0, Pg1, Pg2, Pg3, Pg6, Pin, PinId, PinIdProvider, + DynPinId, Pa0, Pa1, Pa2, Pa3, Pa4, Pa5, Pa6, Pa7, Pa8, Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, Pb0, + Pb1, Pb2, Pb3, Pb4, Pb12, Pb13, Pb14, Pb15, Pc0, Pc1, Pd10, Pd11, Pd12, Pd13, Pd14, Pd15, Pe0, + Pe1, Pe2, Pe3, Pe4, Pe5, Pe6, Pe7, Pe8, Pe9, Pe12, Pe13, Pe14, Pe15, Pf0, Pf1, Pf9, Pf11, Pf12, + Pf13, Pf14, Pf15, Pg0, Pg1, Pg2, Pg3, Pg6, Pin, PinId, }; #[cfg(not(feature = "va41628"))] use crate::pins::{ @@ -11,122 +11,122 @@ use crate::pins::{ Pe11, Pf2, Pf3, Pf4, Pf5, Pf6, Pf7, Pf8, Pf10, }; -pin_and_tim!(Pa0, FunSel::Sel1, 0); -pin_and_tim!(Pa1, FunSel::Sel1, 1); -pin_and_tim!(Pa2, FunSel::Sel1, 2); -pin_and_tim!(Pa3, FunSel::Sel1, 3); -pin_and_tim!(Pa4, FunSel::Sel1, 4); -pin_and_tim!(Pa5, FunSel::Sel1, 5); -pin_and_tim!(Pa6, FunSel::Sel1, 6); -pin_and_tim!(Pa7, FunSel::Sel1, 7); -pin_and_tim!(Pa8, FunSel::Sel3, 8); -pin_and_tim!(Pa10, FunSel::Sel2, 23); -pin_and_tim!(Pa11, FunSel::Sel2, 22); -pin_and_tim!(Pa12, FunSel::Sel2, 21); -pin_and_tim!(Pa13, FunSel::Sel2, 20); -pin_and_tim!(Pa14, FunSel::Sel2, 19); -pin_and_tim!(Pa15, FunSel::Sel2, 18); +pin_and_tim!(Pa0, FunctionSelect::Sel1, 0); +pin_and_tim!(Pa1, FunctionSelect::Sel1, 1); +pin_and_tim!(Pa2, FunctionSelect::Sel1, 2); +pin_and_tim!(Pa3, FunctionSelect::Sel1, 3); +pin_and_tim!(Pa4, FunctionSelect::Sel1, 4); +pin_and_tim!(Pa5, FunctionSelect::Sel1, 5); +pin_and_tim!(Pa6, FunctionSelect::Sel1, 6); +pin_and_tim!(Pa7, FunctionSelect::Sel1, 7); +pin_and_tim!(Pa8, FunctionSelect::Sel3, 8); +pin_and_tim!(Pa10, FunctionSelect::Sel2, 23); +pin_and_tim!(Pa11, FunctionSelect::Sel2, 22); +pin_and_tim!(Pa12, FunctionSelect::Sel2, 21); +pin_and_tim!(Pa13, FunctionSelect::Sel2, 20); +pin_and_tim!(Pa14, FunctionSelect::Sel2, 19); +pin_and_tim!(Pa15, FunctionSelect::Sel2, 18); -pin_and_tim!(Pb0, FunSel::Sel2, 17); -pin_and_tim!(Pb1, FunSel::Sel2, 16); -pin_and_tim!(Pb2, FunSel::Sel2, 15); -pin_and_tim!(Pb3, FunSel::Sel2, 14); -pin_and_tim!(Pb4, FunSel::Sel2, 13); +pin_and_tim!(Pb0, FunctionSelect::Sel2, 17); +pin_and_tim!(Pb1, FunctionSelect::Sel2, 16); +pin_and_tim!(Pb2, FunctionSelect::Sel2, 15); +pin_and_tim!(Pb3, FunctionSelect::Sel2, 14); +pin_and_tim!(Pb4, FunctionSelect::Sel2, 13); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pb5, FunSel::Sel2, 12); +pin_and_tim!(Pb5, FunctionSelect::Sel2, 12); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pb6, FunSel::Sel2, 11); +pin_and_tim!(Pb6, FunctionSelect::Sel2, 11); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pb7, FunSel::Sel2, 10); +pin_and_tim!(Pb7, FunctionSelect::Sel2, 10); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pb8, FunSel::Sel2, 9); +pin_and_tim!(Pb8, FunctionSelect::Sel2, 9); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pb9, FunSel::Sel2, 8); +pin_and_tim!(Pb9, FunctionSelect::Sel2, 8); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pb10, FunSel::Sel2, 7); +pin_and_tim!(Pb10, FunctionSelect::Sel2, 7); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pb11, FunSel::Sel2, 6); -pin_and_tim!(Pb12, FunSel::Sel2, 5); -pin_and_tim!(Pb13, FunSel::Sel2, 4); -pin_and_tim!(Pb14, FunSel::Sel2, 3); -pin_and_tim!(Pb15, FunSel::Sel2, 2); +pin_and_tim!(Pb11, FunctionSelect::Sel2, 6); +pin_and_tim!(Pb12, FunctionSelect::Sel2, 5); +pin_and_tim!(Pb13, FunctionSelect::Sel2, 4); +pin_and_tim!(Pb14, FunctionSelect::Sel2, 3); +pin_and_tim!(Pb15, FunctionSelect::Sel2, 2); -pin_and_tim!(Pc0, FunSel::Sel2, 1); -pin_and_tim!(Pc1, FunSel::Sel2, 0); +pin_and_tim!(Pc0, FunctionSelect::Sel2, 1); +pin_and_tim!(Pc1, FunctionSelect::Sel2, 0); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd0, FunSel::Sel2, 0); +pin_and_tim!(Pd0, FunctionSelect::Sel2, 0); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd1, FunSel::Sel2, 1); +pin_and_tim!(Pd1, FunctionSelect::Sel2, 1); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd2, FunSel::Sel2, 2); +pin_and_tim!(Pd2, FunctionSelect::Sel2, 2); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd3, FunSel::Sel2, 3); +pin_and_tim!(Pd3, FunctionSelect::Sel2, 3); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd4, FunSel::Sel2, 4); +pin_and_tim!(Pd4, FunctionSelect::Sel2, 4); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd5, FunSel::Sel2, 5); +pin_and_tim!(Pd5, FunctionSelect::Sel2, 5); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd6, FunSel::Sel2, 6); +pin_and_tim!(Pd6, FunctionSelect::Sel2, 6); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd7, FunSel::Sel2, 7); +pin_and_tim!(Pd7, FunctionSelect::Sel2, 7); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd8, FunSel::Sel2, 8); +pin_and_tim!(Pd8, FunctionSelect::Sel2, 8); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pd9, FunSel::Sel2, 9); -pin_and_tim!(Pd10, FunSel::Sel2, 10); -pin_and_tim!(Pd11, FunSel::Sel2, 11); -pin_and_tim!(Pd12, FunSel::Sel2, 12); -pin_and_tim!(Pd13, FunSel::Sel2, 13); -pin_and_tim!(Pd14, FunSel::Sel2, 14); -pin_and_tim!(Pd15, FunSel::Sel2, 15); +pin_and_tim!(Pd9, FunctionSelect::Sel2, 9); +pin_and_tim!(Pd10, FunctionSelect::Sel2, 10); +pin_and_tim!(Pd11, FunctionSelect::Sel2, 11); +pin_and_tim!(Pd12, FunctionSelect::Sel2, 12); +pin_and_tim!(Pd13, FunctionSelect::Sel2, 13); +pin_and_tim!(Pd14, FunctionSelect::Sel2, 14); +pin_and_tim!(Pd15, FunctionSelect::Sel2, 15); -pin_and_tim!(Pe0, FunSel::Sel2, 16); -pin_and_tim!(Pe1, FunSel::Sel2, 17); -pin_and_tim!(Pe2, FunSel::Sel2, 18); -pin_and_tim!(Pe3, FunSel::Sel2, 19); -pin_and_tim!(Pe4, FunSel::Sel2, 20); -pin_and_tim!(Pe5, FunSel::Sel2, 21); -pin_and_tim!(Pe6, FunSel::Sel2, 22); -pin_and_tim!(Pe7, FunSel::Sel2, 23); -pin_and_tim!(Pe8, FunSel::Sel3, 16); -pin_and_tim!(Pe9, FunSel::Sel3, 17); +pin_and_tim!(Pe0, FunctionSelect::Sel2, 16); +pin_and_tim!(Pe1, FunctionSelect::Sel2, 17); +pin_and_tim!(Pe2, FunctionSelect::Sel2, 18); +pin_and_tim!(Pe3, FunctionSelect::Sel2, 19); +pin_and_tim!(Pe4, FunctionSelect::Sel2, 20); +pin_and_tim!(Pe5, FunctionSelect::Sel2, 21); +pin_and_tim!(Pe6, FunctionSelect::Sel2, 22); +pin_and_tim!(Pe7, FunctionSelect::Sel2, 23); +pin_and_tim!(Pe8, FunctionSelect::Sel3, 16); +pin_and_tim!(Pe9, FunctionSelect::Sel3, 17); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pe10, FunSel::Sel3, 18); +pin_and_tim!(Pe10, FunctionSelect::Sel3, 18); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pe11, FunSel::Sel3, 19); -pin_and_tim!(Pe12, FunSel::Sel3, 20); -pin_and_tim!(Pe13, FunSel::Sel3, 21); -pin_and_tim!(Pe14, FunSel::Sel3, 22); -pin_and_tim!(Pe15, FunSel::Sel3, 23); +pin_and_tim!(Pe11, FunctionSelect::Sel3, 19); +pin_and_tim!(Pe12, FunctionSelect::Sel3, 20); +pin_and_tim!(Pe13, FunctionSelect::Sel3, 21); +pin_and_tim!(Pe14, FunctionSelect::Sel3, 22); +pin_and_tim!(Pe15, FunctionSelect::Sel3, 23); -pin_and_tim!(Pf0, FunSel::Sel3, 0); -pin_and_tim!(Pf1, FunSel::Sel3, 1); +pin_and_tim!(Pf0, FunctionSelect::Sel3, 0); +pin_and_tim!(Pf1, FunctionSelect::Sel3, 1); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pf2, FunSel::Sel3, 2); +pin_and_tim!(Pf2, FunctionSelect::Sel3, 2); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pf3, FunSel::Sel3, 3); +pin_and_tim!(Pf3, FunctionSelect::Sel3, 3); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pf4, FunSel::Sel3, 4); +pin_and_tim!(Pf4, FunctionSelect::Sel3, 4); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pf5, FunSel::Sel3, 5); +pin_and_tim!(Pf5, FunctionSelect::Sel3, 5); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pf6, FunSel::Sel3, 6); +pin_and_tim!(Pf6, FunctionSelect::Sel3, 6); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pf7, FunSel::Sel3, 7); +pin_and_tim!(Pf7, FunctionSelect::Sel3, 7); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pf8, FunSel::Sel3, 8); -pin_and_tim!(Pf9, FunSel::Sel3, 9); +pin_and_tim!(Pf8, FunctionSelect::Sel3, 8); +pin_and_tim!(Pf9, FunctionSelect::Sel3, 9); #[cfg(not(feature = "va41628"))] -pin_and_tim!(Pf10, FunSel::Sel3, 10); -pin_and_tim!(Pf11, FunSel::Sel3, 11); -pin_and_tim!(Pf12, FunSel::Sel3, 12); -pin_and_tim!(Pf13, FunSel::Sel2, 19); -pin_and_tim!(Pf14, FunSel::Sel2, 20); -pin_and_tim!(Pf15, FunSel::Sel2, 21); +pin_and_tim!(Pf10, FunctionSelect::Sel3, 10); +pin_and_tim!(Pf11, FunctionSelect::Sel3, 11); +pin_and_tim!(Pf12, FunctionSelect::Sel3, 12); +pin_and_tim!(Pf13, FunctionSelect::Sel2, 19); +pin_and_tim!(Pf14, FunctionSelect::Sel2, 20); +pin_and_tim!(Pf15, FunctionSelect::Sel2, 21); -pin_and_tim!(Pg0, FunSel::Sel2, 22); -pin_and_tim!(Pg1, FunSel::Sel2, 23); -pin_and_tim!(Pg2, FunSel::Sel1, 9); -pin_and_tim!(Pg3, FunSel::Sel1, 10); -pin_and_tim!(Pg6, FunSel::Sel1, 12); +pin_and_tim!(Pg0, FunctionSelect::Sel2, 22); +pin_and_tim!(Pg1, FunctionSelect::Sel2, 23); +pin_and_tim!(Pg2, FunctionSelect::Sel1, 9); +pin_and_tim!(Pg3, FunctionSelect::Sel1, 10); +pin_and_tim!(Pg6, FunctionSelect::Sel1, 12); diff --git a/src/uart/mod.rs b/src/uart/mod.rs index 362cee1..1a03761 100644 --- a/src/uart/mod.rs +++ b/src/uart/mod.rs @@ -16,10 +16,10 @@ use core::convert::Infallible; pub mod regs; #[cfg(feature = "vor1x")] use crate::InterruptConfig; -use crate::{FunSel, gpio::IoPeriphPin, pins::PinMarker, sealed::Sealed}; +use crate::{FunctionSelect, gpio::IoPeriphPin, pins::AnyPin, sealed::Sealed}; use arbitrary_int::{prelude::*, u6, u18}; use fugit::RateExtU32; -use regs::{ClkScale, Control, Data, Enable, FifoClear, InterruptClear, MmioUart}; +use regs::{ClockScale, Control, Data, Enable, FifoClear, InterruptClear, MmioUart}; use crate::{PeripheralSelect, enable_nvic_interrupt, enable_peripheral_clock, time::Hertz}; use embedded_hal_nb::serial::Read; @@ -47,13 +47,13 @@ pub use rx_asynch::*; // Type-Level support //================================================================================================== -pub trait TxPin: PinMarker { +pub trait TxPin: AnyPin { const BANK: Bank; - const FUN_SEL: FunSel; + const FUN_SEL: FunctionSelect; } -pub trait RxPin: PinMarker { +pub trait RxPin: AnyPin { const BANK: Bank; - const FUN_SEL: FunSel; + const FUN_SEL: FunctionSelect; } //================================================================================================== @@ -180,33 +180,33 @@ impl From for Config { #[derive(Debug, Copy, Clone)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub struct IrqContextTimeoutOrMaxSize { +pub struct InterruptContextTimeoutOrMaxSize { rx_idx: usize, - mode: IrqReceptionMode, + mode: InterruptReceptionMode, pub max_len: usize, } -impl IrqContextTimeoutOrMaxSize { +impl InterruptContextTimeoutOrMaxSize { pub fn new(max_len: usize) -> Self { - IrqContextTimeoutOrMaxSize { + InterruptContextTimeoutOrMaxSize { rx_idx: 0, max_len, - mode: IrqReceptionMode::Idle, + mode: InterruptReceptionMode::Idle, } } } -impl IrqContextTimeoutOrMaxSize { +impl InterruptContextTimeoutOrMaxSize { pub fn reset(&mut self) { self.rx_idx = 0; - self.mode = IrqReceptionMode::Idle; + self.mode = InterruptReceptionMode::Idle; } } /// This struct is used to return the default IRQ handler result to the user #[derive(Debug, Default)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub struct IrqResult { +pub struct InterruptResult { pub bytes_read: usize, pub errors: Option, } @@ -214,16 +214,16 @@ pub struct IrqResult { /// This struct is used to return the default IRQ handler result to the user #[derive(Debug, Default)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub struct IrqResultMaxSizeOrTimeout { +pub struct InterruptResultMaxSizeOrTimeout { complete: bool, timeout: bool, pub errors: Option, pub bytes_read: usize, } -impl IrqResultMaxSizeOrTimeout { +impl InterruptResultMaxSizeOrTimeout { pub fn new() -> Self { - IrqResultMaxSizeOrTimeout { + InterruptResultMaxSizeOrTimeout { complete: false, timeout: false, errors: None, @@ -231,7 +231,7 @@ impl IrqResultMaxSizeOrTimeout { } } } -impl IrqResultMaxSizeOrTimeout { +impl InterruptResultMaxSizeOrTimeout { #[inline] pub fn has_errors(&self) -> bool { self.errors.is_some() @@ -265,7 +265,7 @@ impl IrqResultMaxSizeOrTimeout { #[derive(Debug, PartialEq, Copy, Clone)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] -enum IrqReceptionMode { +enum InterruptReceptionMode { Idle, Pending, } @@ -319,7 +319,7 @@ pub struct BufferTooShortError { // UART peripheral wrapper //================================================================================================== -pub trait UartPeripheralMarker: Sealed { +pub trait UartInstance: Sealed { const ID: Bank; const PERIPH_SEL: PeripheralSelect; } @@ -329,7 +329,7 @@ pub type Uart0 = pac::Uarta; #[cfg(feature = "vor4x")] pub type Uart0 = pac::Uart0; -impl UartPeripheralMarker for Uart0 { +impl UartInstance for Uart0 { const ID: Bank = Bank::Uart0; const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart0; } @@ -340,14 +340,14 @@ pub type Uart1 = pac::Uartb; #[cfg(feature = "vor4x")] pub type Uart1 = pac::Uart1; -impl UartPeripheralMarker for Uart1 { +impl UartInstance for Uart1 { const ID: Bank = Bank::Uart1; const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart1; } impl Sealed for Uart1 {} #[cfg(feature = "vor4x")] -impl UartPeripheralMarker for pac::Uart2 { +impl UartInstance for pac::Uart2 { const ID: Bank = Bank::Uart2; const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart2; } @@ -373,22 +373,22 @@ impl Uart { cfg_if::cfg_if! { if #[cfg(feature = "vor1x")] { /// Calls [Self::new] with the interrupt configuration to some valid value. - pub fn new_with_interrupt( - uart: UartI, - tx_pin: TxPinI, - rx_pin: RxPinI, + pub fn new_with_interrupt( + uart: UartPeriph, + tx_pin: Tx, + rx_pin: Rx, sys_clk: Hertz, config: Config, irq_cfg: InterruptConfig, - ) -> Result { + ) -> Result { Self::new(uart, tx_pin, rx_pin, sys_clk, config, Some(irq_cfg)) } /// Calls [Self::new] with the interrupt configuration to [None]. - pub fn new_without_interrupt( - uart: UartI, - tx_pin: TxPinI, - rx_pin: RxPinI, + pub fn new_without_interrupt( + uart: UartPeriph, + tx_pin: Tx, + rx_pin: Rx, sys_clk: Hertz, config: Config, ) -> Result { @@ -407,10 +407,10 @@ impl Uart { /// - `irq_cfg`: Optional interrupt configuration. This should be a valid value if the plan /// is to use TX or RX functionality relying on interrupts. If only the blocking API without /// any interrupt support is used, this can be [None]. - pub fn new( - uart: UartI, - tx_pin: TxPinI, - rx_pin: RxPinI, + pub fn new( + uart: UartPeriph, + tx_pin: Tx, + rx_pin: Rx, sys_clk: Hertz, config: Config, opt_irq_cfg: Option, @@ -426,10 +426,10 @@ impl Uart { /// - `uart`: The concrete UART peripheral instance. /// - `pins`: UART TX and RX pin tuple. /// - `config`: UART specific configuration parameters like baudrate. - pub fn new( + pub fn new( uart: UartI, - tx_pin: TxPinI, - rx_pin: RxPinI, + tx_pin: Tx, + rx_pin: Rx, clks: &Clocks, config: Config, ) -> Result { @@ -448,10 +448,10 @@ impl Uart { /// - `uart`: The concrete UART peripheral instance. /// - `pins`: UART TX and RX pin tuple. /// - `config`: UART specific configuration parameters like baudrate. - pub fn new_with_ref_clk( - uart: UartI, - tx_pin: TxPinI, - rx_pin: RxPinI, + pub fn new_with_ref_clk( + uart: Uart, + tx_pin: Tx, + rx_pin: Rx, ref_clk: Hertz, config: Config, ) -> Result { @@ -460,7 +460,7 @@ impl Uart { } } - fn new_internal( + fn new_internal( _uart: UartI, _pins: (TxPinI, RxPinI), ref_clk: Hertz, @@ -489,7 +489,7 @@ impl Uart { let x = ref_clk.raw() as f32 / (config.baudrate.raw() * baud_multiplier) as f32; let integer_part = x as u32; reg_block.write_clkscale( - ClkScale::builder() + ClockScale::builder() .with_int(u18::new(integer_part)) .with_frac(u6::new(frac as u8)) .build(), @@ -545,7 +545,7 @@ impl Uart { } #[inline] - pub fn perid(&self) -> u32 { + pub fn peripheral_id(&self) -> u32 { self.tx.perid() } @@ -1095,12 +1095,12 @@ impl RxWithInterrupt { /// of a packet. pub fn read_fixed_len_or_timeout_based_using_irq( &mut self, - context: &mut IrqContextTimeoutOrMaxSize, + context: &mut InterruptContextTimeoutOrMaxSize, ) -> Result<(), TransferPendingError> { - if context.mode != IrqReceptionMode::Idle { + if context.mode != InterruptReceptionMode::Idle { return Err(TransferPendingError); } - context.mode = IrqReceptionMode::Pending; + context.mode = InterruptReceptionMode::Pending; context.rx_idx = 0; self.start(); Ok(()) @@ -1131,9 +1131,9 @@ impl RxWithInterrupt { /// /// This function will not disable the RX interrupts, so you don't need to call any other /// API after calling this function to continue emptying the FIFO. RX errors are handled - /// as partial errors and are returned as part of the [IrqResult]. - pub fn on_interrupt(&mut self, buf: &mut [u8; 16]) -> IrqResult { - let mut result = IrqResult::default(); + /// as partial errors and are returned as part of the [InterruptResult]. + pub fn on_interrupt(&mut self, buf: &mut [u8; 16]) -> InterruptResult { + let mut result = InterruptResult::default(); let irq_status = self.0.regs.read_irq_status(); let irq_enabled = self.0.regs.read_irq_enabled(); @@ -1182,23 +1182,23 @@ impl RxWithInterrupt { /// /// If either the maximum number of packets have been read or a timeout occured, the transfer /// will be deemed completed. The state information of the transfer is tracked in the - /// [IrqContextTimeoutOrMaxSize] structure. + /// [InterruptContextTimeoutOrMaxSize] structure. /// /// If passed buffer is equal to or larger than the specified maximum length, an /// [BufferTooShortError] will be returned. Other RX errors are treated as partial errors - /// and returned inside the [IrqResultMaxSizeOrTimeout] structure. + /// and returned inside the [InterruptResultMaxSizeOrTimeout] structure. pub fn on_interrupt_max_size_or_timeout_based( &mut self, - context: &mut IrqContextTimeoutOrMaxSize, + context: &mut InterruptContextTimeoutOrMaxSize, buf: &mut [u8], - ) -> Result { + ) -> Result { if buf.len() < context.max_len { return Err(BufferTooShortError { found: buf.len(), expected: context.max_len, }); } - let mut result = IrqResultMaxSizeOrTimeout::default(); + let mut result = InterruptResultMaxSizeOrTimeout::default(); let irq_status = self.0.regs.read_irq_status(); let rx_enabled = self.0.regs.read_enable().rx(); @@ -1283,14 +1283,14 @@ impl RxWithInterrupt { fn irq_completion_handler_max_size_timeout( &mut self, - res: &mut IrqResultMaxSizeOrTimeout, - context: &mut IrqContextTimeoutOrMaxSize, + res: &mut InterruptResultMaxSizeOrTimeout, + context: &mut InterruptContextTimeoutOrMaxSize, ) { self.disable_interrupts(); self.0.disable(); res.bytes_read = context.rx_idx; res.complete = true; - context.mode = IrqReceptionMode::Idle; + context.mode = InterruptReceptionMode::Idle; context.rx_idx = 0; } diff --git a/src/uart/pins_vor1x.rs b/src/uart/pins_vor1x.rs index c7c0a95..bd165b6 100644 --- a/src/uart/pins_vor1x.rs +++ b/src/uart/pins_vor1x.rs @@ -1,7 +1,7 @@ // UART A pins use crate::{ - FunSel, + FunctionSelect, pins::{ Pa2, Pa3, Pa8, Pa9, Pa16, Pa17, Pa18, Pa19, Pa26, Pa27, Pa30, Pa31, Pb6, Pb7, Pb8, Pb9, Pb18, Pb19, Pb20, Pb21, Pb22, Pb23, Pin, @@ -12,101 +12,101 @@ use super::{Bank, RxPin, TxPin}; impl TxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl RxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl TxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl RxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl TxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl RxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl TxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl RxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl TxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl RxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } // UART B pins impl TxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl RxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl TxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl RxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl TxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl RxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl TxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl RxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl TxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl RxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl TxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl RxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } diff --git a/src/uart/pins_vor4x.rs b/src/uart/pins_vor4x.rs index 3710534..a72e6c9 100644 --- a/src/uart/pins_vor4x.rs +++ b/src/uart/pins_vor4x.rs @@ -1,7 +1,7 @@ #[cfg(not(feature = "va41628"))] use crate::pins::{Pc15, Pf8}; use crate::{ - FunSel, + FunctionSelect, gpio::Pin, pins::{Pa2, Pa3, Pb14, Pb15, Pc4, Pc5, Pc14, Pd11, Pd12, Pe2, Pe3, Pf9, Pf12, Pf13, Pg0, Pg1}, }; @@ -12,87 +12,87 @@ use super::{Bank, RxPin, TxPin}; impl TxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl RxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl TxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl RxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } impl TxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl RxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl TxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl RxPin for Pin { const BANK: Bank = Bank::Uart0; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } // UART 1 pins impl TxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl RxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl TxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl RxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel3; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel3; } impl TxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl RxPin for Pin { const BANK: Bank = Bank::Uart1; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } // UART 2 pins impl TxPin for Pin { const BANK: Bank = Bank::Uart2; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } #[cfg(not(feature = "va41628"))] impl RxPin for Pin { const BANK: Bank = Bank::Uart2; - const FUN_SEL: FunSel = FunSel::Sel2; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel2; } #[cfg(not(feature = "va41628"))] impl TxPin for Pin { const BANK: Bank = Bank::Uart2; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } impl RxPin for Pin { const BANK: Bank = Bank::Uart2; - const FUN_SEL: FunSel = FunSel::Sel1; + const FUN_SEL: FunctionSelect = FunctionSelect::Sel1; } diff --git a/src/uart/regs.rs b/src/uart/regs.rs index 07c822d..06fc903 100644 --- a/src/uart/regs.rs +++ b/src/uart/regs.rs @@ -117,7 +117,7 @@ pub struct Control { } #[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))] -pub struct ClkScale { +pub struct ClockScale { #[bits(6..=23, rw)] int: u18, #[bits(0..=5, rw)] @@ -263,7 +263,7 @@ pub struct Uart { data: Data, enable: Enable, ctrl: Control, - clkscale: ClkScale, + clkscale: ClockScale, #[mmio(PureRead)] rx_status: RxStatus, #[mmio(PureRead)] -- 2.43.0