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274 lines
7.2 KiB
Rust
274 lines
7.2 KiB
Rust
use core::marker::PhantomData;
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pub use crate::shared::{FifoClear, TriggerLevel};
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cfg_if::cfg_if! {
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if #[cfg(feature = "vor1x")] {
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/// SPI A base address
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pub const BASE_ADDR_0: usize = 0x4005_0000;
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/// SPI B base address
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pub const BASE_ADDR_1: usize = 0x4005_1000;
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/// SPI C base address
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pub const BASE_ADDR_2: usize = 0x4005_2000;
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} else if #[cfg(feature = "vor4x")] {
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/// SPI 0 base address
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pub const BASE_ADDR_0: usize = 0x4001_5000;
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/// SPI 1 base address
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pub const BASE_ADDR_1: usize = 0x4001_5400;
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/// SPI 2 base address
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pub const BASE_ADDR_2: usize = 0x4001_5800;
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/// SPI 3 base address
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pub const BASE_ADDR_3: usize = 0x4001_5C00;
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}
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}
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#[derive(Debug, PartialEq, Eq, Clone, Copy)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Bank {
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Spi0,
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Spi1,
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Spi2,
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#[cfg(feature = "vor4x")]
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Spi3,
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}
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impl Bank {
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/// Unsafely steal the SPI peripheral block for the given port.
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///
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/// # Safety
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///
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/// Circumvents ownership and safety guarantees by the HAL.
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pub unsafe fn steal_regs(&self) -> MmioSpi<'static> {
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Spi::new_mmio(*self)
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}
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}
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#[bitbybit::bitenum(u4)]
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum WordSize {
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OneBit = 0x00,
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FourBits = 0x03,
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EightBits = 0x07,
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SixteenBits = 0x0f,
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}
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#[derive(Debug, PartialEq, Eq)]
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#[bitbybit::bitenum(u3, exhaustive = true)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum HwChipSelectId {
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Id0 = 0,
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Id1 = 1,
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Id2 = 2,
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Id3 = 3,
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Id4 = 4,
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Id5 = 5,
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Id6 = 6,
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Id7 = 7,
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}
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#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))]
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pub struct Control0 {
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#[bits(8..=15, rw)]
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scrdv: u8,
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#[bit(7, rw)]
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sph: bool,
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#[bit(6, rw)]
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spo: bool,
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#[bits(0..=3, rw)]
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word_size: Option<WordSize>,
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}
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#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))]
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pub struct Control1 {
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#[bit(11, rw)]
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mtxpause: bool,
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#[bit(10, rw)]
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mdlycap: bool,
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#[bit(9, rw)]
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bm_stall: bool,
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#[bit(8, rw)]
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bm_start: bool,
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#[bit(7, rw)]
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blockmode: bool,
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#[bits(4..=6, rw)]
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ss: HwChipSelectId,
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#[bit(3, rw)]
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sod: bool,
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#[bit(2, rw)]
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slave_mode: bool,
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#[bit(1, rw)]
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enable: bool,
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#[bit(0, rw)]
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lbm: bool,
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct Data {
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/// Only used for BLOCKMODE. For received data, this bit indicated that the data was the first
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/// word after the chip select went active. For transmitted data, setting this bit to 1
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/// will end an SPI frame (deassert CS) after the specified data word.
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#[bit(31, rw)]
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bm_start_stop: bool,
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/// Only used for BLOCKMODE. Setting this bit to 1 along with the BMSTOP bit will end an SPI
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/// frame without any additional data to be transmitted. If BMSTOP is not set, this bit is
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/// ignored.
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#[bit(30, rw)]
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bm_skipdata: bool,
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#[bits(0..=15, rw)]
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data: u16,
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}
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#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
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pub struct Status {
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/// TX FIFO below the trigger level.
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#[bit(7, r)]
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tx_trigger: bool,
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/// RX FIFO above or equals the trigger level.
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#[bit(6, r)]
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rx_trigger: bool,
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#[bit(5, r)]
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rx_data_first: bool,
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#[bit(4, r)]
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busy: bool,
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#[bit(3, r)]
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rx_full: bool,
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#[bit(2, r)]
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rx_not_empty: bool,
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#[bit(1, r)]
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tx_not_full: bool,
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#[bit(0, r)]
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tx_empty: bool,
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}
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/// Clock divisor value. Bit 0 is ignored and always 0. This means that only the even values
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/// are used as clock divisor values, and uneven values are truncated to the next even value.
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/// A value of 0 acts as a 1 for the divisor value.
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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pub struct ClkPrescaler(arbitrary_int::UInt<u32, 8>);
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impl ClkPrescaler {
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pub const fn new(value: u8) -> Self {
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ClkPrescaler(arbitrary_int::UInt::<u32, 8>::new(value as u32))
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}
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pub const fn value(&self) -> u8 {
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self.0.value() as u8
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}
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}
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#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
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pub struct InterruptControl {
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/// TX FIFO count <= TX FIFO trigger level.
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#[bit(3, rw)]
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tx: bool,
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/// RX FIFO count >= RX FIFO trigger level.
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#[bit(2, rw)]
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rx: bool,
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/// Occurs when the RX FIFO has not been read within 32 clock ticks of the SPICLKx2 clock
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/// within the RX FIFO not being empty. Clearing the RX interrupt or reading data from the
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/// FIFO resets the timeout counter.
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#[bit(1, rw)]
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rx_timeout: bool,
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#[bit(0, rw)]
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rx_overrun: bool,
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}
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#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
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pub struct InterruptStatus {
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/// TX FIFO count <= TX FIFO trigger level.
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#[bit(3, r)]
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tx: bool,
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/// RX FIFO count >= RX FIFO trigger level.
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#[bit(2, r)]
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rx: bool,
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/// Occurs when the RX FIFO has not been read within 32 clock ticks of the SPICLKx2 clock
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/// within the RX FIFO not being empty. Clearing the RX interrupt or reading data from the
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/// FIFO resets the timeout counter.
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#[bit(1, r)]
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rx_timeout: bool,
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#[bit(0, r)]
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rx_overrun: bool,
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct InterruptClear {
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/// Clearing the RX interrupt or reading data from the FIFO resets the timeout counter.
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#[bit(1, w)]
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rx_timeout: bool,
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#[bit(0, w)]
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rx_overrun: bool,
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}
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#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
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pub struct State {
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#[bits(0..=7, r)]
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rx_state: u8,
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#[bits(8..=15, r)]
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rx_fifo: u8,
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#[bits(24..=31, r)]
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tx_fifo: u8,
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}
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#[derive(derive_mmio::Mmio)]
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#[mmio(no_ctors)]
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#[repr(C)]
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pub struct Spi {
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ctrl0: Control0,
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ctrl1: Control1,
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data: Data,
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#[mmio(PureRead)]
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status: Status,
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clkprescale: ClkPrescaler,
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irq_enb: InterruptControl,
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/// Raw interrupt status.
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#[mmio(PureRead)]
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irq_raw: InterruptStatus,
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/// Enabled interrupt status.
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#[mmio(PureRead)]
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irq_status: InterruptStatus,
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#[mmio(Write)]
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irq_clear: InterruptClear,
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rx_fifo_trigger: TriggerLevel,
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tx_fifo_trigger: TriggerLevel,
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#[mmio(Write)]
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fifo_clear: FifoClear,
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#[mmio(PureRead)]
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state: u32,
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#[cfg(feature = "vor1x")]
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_reserved: [u32; 0x3F2],
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#[cfg(feature = "vor4x")]
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_reserved: [u32; 0xF2],
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/// Vorago 1x: 0x0113_07E1. Vorago 4x: 0x0213_07E9.
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#[mmio(PureRead)]
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perid: u32,
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}
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cfg_if::cfg_if! {
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if #[cfg(feature = "vor1x")] {
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static_assertions::const_assert_eq!(core::mem::size_of::<Spi>(), 0x1000);
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} else if #[cfg(feature = "vor4x")] {
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static_assertions::const_assert_eq!(core::mem::size_of::<Spi>(), 0x400);
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}
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}
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impl Spi {
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fn new_mmio_at(base: usize) -> MmioSpi<'static> {
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MmioSpi {
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ptr: base as *mut _,
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phantom: PhantomData,
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}
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}
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pub fn new_mmio(bank: Bank) -> MmioSpi<'static> {
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match bank {
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Bank::Spi0 => Self::new_mmio_at(BASE_ADDR_0),
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Bank::Spi1 => Self::new_mmio_at(BASE_ADDR_1),
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Bank::Spi2 => Self::new_mmio_at(BASE_ADDR_2),
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#[cfg(feature = "vor4x")]
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Bank::Spi3 => Self::new_mmio_at(BASE_ADDR_2),
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}
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}
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}
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