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585 lines
19 KiB
Rust
585 lines
19 KiB
Rust
pub use embedded_hal::digital::PinState;
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use crate::ioconfig::FilterClockSelect;
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use crate::ioconfig::FilterType;
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#[cfg(feature = "vor1x")]
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use crate::{PeripheralSelect, sysconfig::enable_peripheral_clock};
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pub use crate::InvalidOffsetError;
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pub use crate::Port;
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pub use crate::ioconfig::regs::Pull;
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use crate::ioconfig::regs::{FunctionSelect, IoConfig, MmioIoConfig};
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use crate::pins::PinId;
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use super::Pin;
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum InterruptEdge {
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HighToLow,
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LowToHigh,
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BothEdges,
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}
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum InterruptLevel {
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Low = 0,
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High = 1,
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}
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/// Pin identifier for all physical pins exposed by Vorago MCUs.
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#[derive(Debug, PartialEq, Eq, Clone, Copy)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct DynPinId {
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port: Port,
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/// Offset within the port.
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offset: u8,
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}
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#[derive(Debug, thiserror::Error)]
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#[cfg(feature = "vor4x")]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[error("port G does not support interrupts")]
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pub struct PortDoesNotSupportInterrupts;
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impl DynPinId {
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/// Unchecked constructor which panics on invalid offsets.
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pub const fn new_unchecked(port: Port, offset: usize) -> Self {
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if offset >= port.max_offset() {
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panic!("Pin ID construction: offset is out of range");
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}
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DynPinId {
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port,
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offset: offset as u8,
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}
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}
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pub const fn new(port: Port, offset: usize) -> Result<Self, InvalidOffsetError> {
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if offset >= port.max_offset() {
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return Err(InvalidOffsetError { offset, port });
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}
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Ok(DynPinId {
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port,
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offset: offset as u8,
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})
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}
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pub const fn port(&self) -> Port {
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self.port
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}
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pub const fn offset(&self) -> usize {
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self.offset as usize
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}
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/// This function panics if the port is [Port::G].
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#[cfg(feature = "vor4x")]
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pub fn irq(&self) -> Result<va416xx::Interrupt, PortDoesNotSupportInterrupts> {
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if self.port() == Port::G {
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return Err(PortDoesNotSupportInterrupts);
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}
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Ok(self.irq_unchecked())
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}
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/// This function panics if the port is [Port::G].
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#[cfg(feature = "vor4x")]
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pub const fn irq_unchecked(&self) -> va416xx::Interrupt {
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match self.port() {
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Port::A => match self.offset() {
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0 => va416xx::Interrupt::PORTA0,
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1 => va416xx::Interrupt::PORTA1,
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2 => va416xx::Interrupt::PORTA2,
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3 => va416xx::Interrupt::PORTA3,
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4 => va416xx::Interrupt::PORTA4,
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5 => va416xx::Interrupt::PORTA5,
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6 => va416xx::Interrupt::PORTA6,
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7 => va416xx::Interrupt::PORTA7,
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8 => va416xx::Interrupt::PORTA8,
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9 => va416xx::Interrupt::PORTA9,
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10 => va416xx::Interrupt::PORTA10,
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11 => va416xx::Interrupt::PORTA11,
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12 => va416xx::Interrupt::PORTA12,
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13 => va416xx::Interrupt::PORTA13,
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14 => va416xx::Interrupt::PORTA14,
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15 => va416xx::Interrupt::PORTA15,
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_ => unreachable!(),
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},
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Port::B => match self.offset() {
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0 => va416xx::Interrupt::PORTB0,
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1 => va416xx::Interrupt::PORTB1,
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2 => va416xx::Interrupt::PORTB2,
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3 => va416xx::Interrupt::PORTB3,
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4 => va416xx::Interrupt::PORTB4,
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5 => va416xx::Interrupt::PORTB5,
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6 => va416xx::Interrupt::PORTB6,
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7 => va416xx::Interrupt::PORTB7,
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8 => va416xx::Interrupt::PORTB8,
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9 => va416xx::Interrupt::PORTB9,
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10 => va416xx::Interrupt::PORTB10,
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11 => va416xx::Interrupt::PORTB11,
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12 => va416xx::Interrupt::PORTB12,
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13 => va416xx::Interrupt::PORTB13,
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14 => va416xx::Interrupt::PORTB14,
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15 => va416xx::Interrupt::PORTB15,
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_ => unreachable!(),
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},
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Port::C => match self.offset() {
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0 => va416xx::Interrupt::PORTC0,
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1 => va416xx::Interrupt::PORTC1,
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2 => va416xx::Interrupt::PORTC2,
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3 => va416xx::Interrupt::PORTC3,
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4 => va416xx::Interrupt::PORTC4,
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5 => va416xx::Interrupt::PORTC5,
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6 => va416xx::Interrupt::PORTC6,
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7 => va416xx::Interrupt::PORTC7,
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8 => va416xx::Interrupt::PORTC8,
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9 => va416xx::Interrupt::PORTC9,
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10 => va416xx::Interrupt::PORTC10,
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11 => va416xx::Interrupt::PORTC11,
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12 => va416xx::Interrupt::PORTC12,
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13 => va416xx::Interrupt::PORTC13,
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14 => va416xx::Interrupt::PORTC14,
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15 => va416xx::Interrupt::PORTC15,
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_ => unreachable!(),
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},
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Port::D => match self.offset() {
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0 => va416xx::Interrupt::PORTD0,
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1 => va416xx::Interrupt::PORTD1,
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2 => va416xx::Interrupt::PORTD2,
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3 => va416xx::Interrupt::PORTD3,
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4 => va416xx::Interrupt::PORTD4,
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5 => va416xx::Interrupt::PORTD5,
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6 => va416xx::Interrupt::PORTD6,
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7 => va416xx::Interrupt::PORTD7,
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8 => va416xx::Interrupt::PORTD8,
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9 => va416xx::Interrupt::PORTD9,
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10 => va416xx::Interrupt::PORTD10,
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11 => va416xx::Interrupt::PORTD11,
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12 => va416xx::Interrupt::PORTD12,
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13 => va416xx::Interrupt::PORTD13,
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14 => va416xx::Interrupt::PORTD14,
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15 => va416xx::Interrupt::PORTD15,
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_ => unreachable!(),
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},
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Port::E => match self.offset() {
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0 => va416xx::Interrupt::PORTE0,
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1 => va416xx::Interrupt::PORTE1,
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2 => va416xx::Interrupt::PORTE2,
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3 => va416xx::Interrupt::PORTE3,
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4 => va416xx::Interrupt::PORTE4,
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5 => va416xx::Interrupt::PORTE5,
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6 => va416xx::Interrupt::PORTE6,
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7 => va416xx::Interrupt::PORTE7,
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8 => va416xx::Interrupt::PORTE8,
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9 => va416xx::Interrupt::PORTE9,
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10 => va416xx::Interrupt::PORTE10,
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11 => va416xx::Interrupt::PORTE11,
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12 => va416xx::Interrupt::PORTE12,
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13 => va416xx::Interrupt::PORTE13,
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14 => va416xx::Interrupt::PORTE14,
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15 => va416xx::Interrupt::PORTE15,
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_ => unreachable!(),
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},
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Port::F => match self.offset() {
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0 => va416xx::Interrupt::PORTF0,
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1 => va416xx::Interrupt::PORTF1,
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2 => va416xx::Interrupt::PORTF2,
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3 => va416xx::Interrupt::PORTF3,
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4 => va416xx::Interrupt::PORTF4,
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5 => va416xx::Interrupt::PORTF5,
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6 => va416xx::Interrupt::PORTF6,
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7 => va416xx::Interrupt::PORTF7,
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8 => va416xx::Interrupt::PORTF8,
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9 => va416xx::Interrupt::PORTF9,
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10 => va416xx::Interrupt::PORTF10,
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11 => va416xx::Interrupt::PORTF11,
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12 => va416xx::Interrupt::PORTF12,
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13 => va416xx::Interrupt::PORTF13,
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14 => va416xx::Interrupt::PORTF14,
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15 => va416xx::Interrupt::PORTF15,
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_ => unreachable!(),
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},
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Port::G => panic!("port G does not have interrupts"),
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}
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}
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}
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/// Low-level driver structure for GPIO pins.
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pub struct LowLevelGpio {
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gpio: super::regs::MmioGpio<'static>,
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ioconfig: MmioIoConfig<'static>,
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id: DynPinId,
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}
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impl core::fmt::Debug for LowLevelGpio {
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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f.debug_struct("LowLevelGpio")
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.field("gpio", &self.gpio.port())
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.field("id", &self.id)
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.finish()
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}
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}
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impl LowLevelGpio {
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/// Create a new low-level GPIO pin instance from a given [Pin].
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///
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/// Can be used for performing resource management of the [Pin]s.
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pub fn new_with_pin<I: PinId>(_pin: Pin<I>) -> Self {
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Self::new(I::ID)
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}
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/// Create a new low-level GPIO pin instance using only the [PinId].
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pub fn new(id: DynPinId) -> Self {
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LowLevelGpio {
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gpio: super::regs::Gpio::new_mmio(id.port),
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ioconfig: IoConfig::new_mmio(),
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id,
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}
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}
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#[inline]
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pub fn id(&self) -> DynPinId {
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self.id
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}
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#[inline]
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pub fn port(&self) -> Port {
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self.id.port()
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}
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#[inline]
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pub fn offset(&self) -> usize {
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self.id.offset()
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}
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pub fn configure_as_input_floating(&mut self) {
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self.ioconfig.modify_pin_config(self.id, |mut config| {
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config.set_funsel(FunctionSelect::Sel0);
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config.set_io_disable(false);
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config.set_invert_input(false);
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config.set_open_drain(false);
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config.set_pull_enable(false);
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config.set_pull_when_output_active(false);
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config.set_invert_output(false);
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config.set_input_enable_when_output(false);
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config
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});
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self.gpio.modify_dir(|mut dir| {
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dir &= !(1 << self.id.offset());
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dir
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});
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}
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pub fn configure_as_input_with_pull(&mut self, pull: Pull) {
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self.ioconfig.modify_pin_config(self.id, |mut config| {
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config.set_funsel(FunctionSelect::Sel0);
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config.set_io_disable(false);
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config.set_invert_input(false);
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config.set_open_drain(false);
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config.set_pull_enable(true);
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config.set_pull_dir(pull);
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config.set_pull_when_output_active(false);
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config.set_invert_output(false);
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config.set_input_enable_when_output(false);
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config
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});
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self.gpio.modify_dir(|mut dir| {
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dir &= !(1 << self.id.offset());
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dir
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});
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}
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pub fn configure_as_output_push_pull(&mut self, init_level: PinState) {
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self.ioconfig.modify_pin_config(self.id, |mut config| {
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config.set_funsel(FunctionSelect::Sel0);
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config.set_io_disable(false);
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config.set_invert_input(false);
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config.set_open_drain(false);
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config.set_pull_enable(false);
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config.set_pull_when_output_active(false);
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config.set_invert_output(false);
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config.set_input_enable_when_output(true);
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config
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});
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match init_level {
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PinState::Low => self.gpio.write_clr_out(self.mask_32()),
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PinState::High => self.gpio.write_set_out(self.mask_32()),
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}
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self.gpio.modify_dir(|mut dir| {
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dir |= 1 << self.id.offset();
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dir
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});
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}
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pub fn configure_as_output_open_drain(&mut self, init_level: PinState) {
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self.ioconfig.modify_pin_config(self.id, |mut config| {
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config.set_funsel(FunctionSelect::Sel0);
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config.set_io_disable(false);
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config.set_invert_input(false);
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config.set_open_drain(true);
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config.set_pull_enable(true);
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config.set_pull_dir(Pull::Up);
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config.set_pull_when_output_active(false);
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config.set_invert_output(false);
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config.set_input_enable_when_output(true);
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config
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});
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let mask32 = self.mask_32();
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match init_level {
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PinState::Low => self.gpio.write_clr_out(mask32),
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PinState::High => self.gpio.write_set_out(mask32),
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}
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self.gpio.modify_dir(|mut dir| {
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dir |= mask32;
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dir
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});
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}
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pub fn configure_as_peripheral_pin(&mut self, fun_sel: FunctionSelect, pull: Option<Pull>) {
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self.ioconfig.modify_pin_config(self.id, |mut config| {
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config.set_funsel(fun_sel);
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config.set_io_disable(false);
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config.set_invert_input(false);
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config.set_open_drain(false);
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config.set_pull_enable(pull.is_some());
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config.set_pull_dir(pull.unwrap_or(Pull::Up));
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config.set_invert_output(false);
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config
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});
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}
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#[inline]
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pub fn is_high(&self) -> bool {
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(self.gpio.read_data_in() >> self.offset()) & 1 == 1
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}
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#[inline]
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pub fn is_low(&self) -> bool {
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!self.is_high()
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}
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#[inline]
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pub fn set_high(&mut self) {
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self.gpio.write_set_out(self.mask_32());
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}
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#[inline]
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pub fn set_low(&mut self) {
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self.gpio.write_clr_out(self.mask_32());
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}
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#[inline]
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pub fn is_set_high(&self) -> bool {
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(self.gpio.read_data_out() >> self.offset()) & 1 == 1
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}
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#[inline]
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pub fn is_set_low(&self) -> bool {
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!self.is_set_high()
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}
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#[inline]
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pub fn toggle(&mut self) {
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self.gpio.write_tog_out(self.mask_32());
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}
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#[cfg(feature = "vor1x")]
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pub fn enable_interrupt(&mut self, irq_cfg: crate::InterruptConfig) {
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if irq_cfg.route {
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self.configure_irqsel(irq_cfg.id);
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}
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if irq_cfg.enable_in_nvic {
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unsafe { crate::enable_nvic_interrupt(irq_cfg.id) };
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}
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self.gpio.modify_irq_enable(|mut value| {
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value |= 1 << self.id.offset;
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value
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});
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}
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#[cfg(feature = "vor4x")]
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pub fn enable_interrupt(
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&mut self,
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enable_in_nvic: bool,
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) -> Result<(), PortDoesNotSupportInterrupts> {
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if enable_in_nvic {
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unsafe { crate::enable_nvic_interrupt(self.id().irq_unchecked()) };
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}
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self.gpio.modify_irq_enable(|mut value| {
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value |= 1 << self.id.offset;
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value
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});
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Ok(())
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}
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#[cfg(feature = "vor1x")]
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pub fn disable_interrupt(&mut self, reset_irqsel: bool) {
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if reset_irqsel {
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self.reset_irqsel();
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}
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// We only manipulate our own bit.
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self.gpio.modify_irq_enable(|mut value| {
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value &= !(1 << self.id.offset);
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value
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});
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}
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#[cfg(feature = "vor4x")]
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pub fn disable_interrupt(&mut self) {
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self.gpio.modify_irq_enable(|mut value| {
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value &= !(1 << self.id.offset);
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value
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});
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}
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/// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure
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/// When using edge mode, it is possible to generate interrupts on both edges as well
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#[inline]
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pub fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
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let mask32 = self.mask_32();
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self.gpio.modify_irq_sen(|mut value| {
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value &= !mask32;
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value
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});
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match edge_type {
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InterruptEdge::HighToLow => {
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self.gpio.modify_irq_evt(|mut value| {
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value &= !mask32;
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value
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});
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}
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InterruptEdge::LowToHigh => {
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self.gpio.modify_irq_evt(|mut value| {
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value |= mask32;
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value
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});
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}
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InterruptEdge::BothEdges => {
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self.gpio.modify_irq_edge(|mut value| {
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value |= mask32;
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value
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});
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}
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}
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}
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/// Configure which edge or level type triggers an interrupt
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#[inline]
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pub fn configure_level_interrupt(&mut self, level: InterruptLevel) {
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let mask32 = self.mask_32();
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self.gpio.modify_irq_sen(|mut value| {
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value |= mask32;
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value
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});
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if level == InterruptLevel::Low {
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self.gpio.modify_irq_evt(|mut value| {
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value &= !mask32;
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value
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});
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} else {
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self.gpio.modify_irq_evt(|mut value| {
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value |= mask32;
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value
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});
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}
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}
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/// Only useful for input pins
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#[inline]
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pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClockSelect) {
|
|
self.ioconfig.modify_pin_config(self.id, |mut config| {
|
|
config.set_filter_type(filter);
|
|
config.set_filter_clk_sel(clksel);
|
|
config
|
|
});
|
|
}
|
|
|
|
/// Only useful for output pins.
|
|
#[inline]
|
|
pub fn configure_pulse_mode(&mut self, enable: bool, default_state: PinState) {
|
|
self.gpio.modify_pulse(|mut value| {
|
|
if enable {
|
|
value |= 1 << self.id.offset;
|
|
} else {
|
|
value &= !(1 << self.id.offset);
|
|
}
|
|
value
|
|
});
|
|
self.gpio.modify_pulsebase(|mut value| {
|
|
if default_state == PinState::High {
|
|
value |= 1 << self.id.offset;
|
|
} else {
|
|
value &= !(1 << self.id.offset);
|
|
}
|
|
value
|
|
});
|
|
}
|
|
|
|
/// Only useful for output pins
|
|
#[inline]
|
|
pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) {
|
|
self.gpio.modify_delay1(|mut value| {
|
|
if delay_1 {
|
|
value |= 1 << self.id.offset;
|
|
} else {
|
|
value &= !(1 << self.id.offset);
|
|
}
|
|
value
|
|
});
|
|
self.gpio.modify_delay2(|mut value| {
|
|
if delay_2 {
|
|
value |= 1 << self.id.offset;
|
|
} else {
|
|
value &= !(1 << self.id.offset);
|
|
}
|
|
value
|
|
});
|
|
}
|
|
|
|
#[cfg(feature = "vor1x")]
|
|
/// Configure the IRQSEL peripheral for this particular pin with the given interrupt ID.
|
|
pub fn configure_irqsel(&mut self, id: va108xx::Interrupt) {
|
|
let irqsel = unsafe { va108xx::Irqsel::steal() };
|
|
enable_peripheral_clock(PeripheralSelect::Irqsel);
|
|
match self.id().port() {
|
|
// Set the correct interrupt number in the IRQSEL register
|
|
super::Port::A => {
|
|
irqsel
|
|
.porta(self.id().offset())
|
|
.write(|w| unsafe { w.bits(id as u32) });
|
|
}
|
|
super::Port::B => {
|
|
irqsel
|
|
.portb(self.id().offset())
|
|
.write(|w| unsafe { w.bits(id as u32) });
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "vor1x")]
|
|
/// Reset the IRQSEL peripheral value for this particular pin.
|
|
pub fn reset_irqsel(&mut self) {
|
|
let irqsel = unsafe { va108xx::Irqsel::steal() };
|
|
enable_peripheral_clock(PeripheralSelect::Irqsel);
|
|
match self.id().port() {
|
|
// Set the correct interrupt number in the IRQSEL register
|
|
super::Port::A => {
|
|
irqsel
|
|
.porta(self.id().offset())
|
|
.write(|w| unsafe { w.bits(u32::MAX) });
|
|
}
|
|
super::Port::B => {
|
|
irqsel
|
|
.portb(self.id().offset())
|
|
.write(|w| unsafe { w.bits(u32::MAX) });
|
|
}
|
|
}
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub const fn mask_32(&self) -> u32 {
|
|
1 << self.id.offset()
|
|
}
|
|
}
|