diff --git a/Cargo.toml b/Cargo.toml
index 8bc810b..8098c5e 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -7,6 +7,6 @@ members = [
   "zynq7000-embassy",
   "examples/simple",
   "examples/embassy",
-  "examples/zedboard",
+  "examples/zedboard", "zynq-mmu",
 ]
 exclude = ["experiments"]
diff --git a/examples/embassy/src/bin/dht22-open-drain-pins.rs b/examples/embassy/src/bin/dht22-open-drain-pins.rs
index e81c99c..a366783 100644
--- a/examples/embassy/src/bin/dht22-open-drain-pins.rs
+++ b/examples/embassy/src/bin/dht22-open-drain-pins.rs
@@ -10,13 +10,13 @@ use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
 use embedded_io::Write;
 use log::{error, info, warn};
 use zynq7000_hal::{
+    BootMode,
     clocks::Clocks,
     gic::{GicConfigurator, GicInterruptHelper, Interrupt},
-    gpio::{mio, Flex, Output, PinState},
+    gpio::{Flex, Output, PinState, mio},
     gtc::Gtc,
     time::Hertz,
     uart::{ClkConfigRaw, Uart, UartConfig},
-    BootMode,
 };
 
 use zynq7000::PsPeripherals;
diff --git a/memory.x b/memory.x
index 8a65966..d1dc467 100644
--- a/memory.x
+++ b/memory.x
@@ -1,8 +1,23 @@
 
 MEMORY
 {
-  /* Zedboard: 512 MB DDR3. Only use 256 MB for now, should be plenty for a bare-metal app. */
-  CODE(rx) : ORIGIN = 0x00100000, LENGTH = 256M
+  /* Zedboard: 512 MB DDR3. Only use 63 MB for now, should be plenty for a bare-metal app.
+  Leave 1 MB of memory which will be configured as uncached device memory by the MPU. This is
+  recommended for something like DMA descriptors. */
+  CODE(rx) : ORIGIN = 0x00100000, LENGTH = 63M
+  UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
 }
 
 REGION_ALIAS("DATA", CODE);
+
+SECTIONS
+{
+  /* Uncached memory */
+  uncached (NOLOAD) : ALIGN(4) {
+    . = ALIGN(4);
+    _sbss_uncached = .;
+    *(.bss.uncached .bss.uncached.*);
+    . = ALIGN(4);
+    _ebss_uncached = .;
+  } > UNCACHED
+}
diff --git a/zynq-mmu/Cargo.toml b/zynq-mmu/Cargo.toml
new file mode 100644
index 0000000..af28d2a
--- /dev/null
+++ b/zynq-mmu/Cargo.toml
@@ -0,0 +1,9 @@
+[package]
+name = "zynq-mmu"
+description = "Zynq MMU structures"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+cortex-ar = { version = "0.2", path = "../../cortex-ar/cortex-ar" }
+thiserror = { version = "2", default-features = false }
diff --git a/zynq-mmu/src/lib.rs b/zynq-mmu/src/lib.rs
new file mode 100644
index 0000000..7953fb6
--- /dev/null
+++ b/zynq-mmu/src/lib.rs
@@ -0,0 +1,51 @@
+//! The MMU structures live inside a dedicated shared crate so it can be used by both the Zynq
+//! runtime crate and teh HAL crate.
+#![no_std]
+
+use cortex_ar::{
+    asm::{dsb, isb},
+    cache::clean_and_invalidate_l1_cache,
+    mmu::SectionAttributes,
+    register::{BpIAll, TlbIAll},
+};
+
+pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
+
+#[derive(Debug, PartialEq, Eq, thiserror::Error)]
+#[error("address is not aligned to 1MB boundary")]
+pub struct AddrNotAlignedToOneMb;
+
+#[repr(C, align(16384))]
+pub struct L1Table(pub [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
+
+impl L1Table {
+    #[inline(always)]
+    pub const fn as_ptr(&self) -> *const u32 {
+        self.0.as_ptr()
+    }
+
+    #[inline(always)]
+    pub const fn as_mut_ptr(&mut self) -> *mut u32 {
+        self.0.as_mut_ptr()
+    }
+
+    pub fn update(
+        &mut self,
+        addr: u32,
+        section_attrs: SectionAttributes,
+    ) -> Result<(), AddrNotAlignedToOneMb> {
+        if addr & 0x000F_FFFF != 0 {
+            return Err(AddrNotAlignedToOneMb);
+        }
+        let index = addr as usize / 0x10_0000;
+        self.0[index] = (self.0[index] & 0xFFF0_0000) | section_attrs.as_raw_bits();
+
+        clean_and_invalidate_l1_cache();
+        TlbIAll::write();
+        BpIAll::write();
+        dsb();
+        isb();
+
+        Ok(())
+    }
+}
diff --git a/zynq7000-hal/Cargo.toml b/zynq7000-hal/Cargo.toml
index fda74ba..58efac8 100644
--- a/zynq7000-hal/Cargo.toml
+++ b/zynq7000-hal/Cargo.toml
@@ -13,7 +13,9 @@ categories = ["embedded", "no-std", "hardware-support"]
 [dependencies]
 cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main" }
 zynq7000 = { path = "../zynq7000" }
+zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
 
+bitbybit = "1.3"
 arbitrary-int = "1.3"
 thiserror = { version = "2", default-features = false }
 num_enum = { version = "0.7", default-features = false }
diff --git a/zynq7000-hal/src/eth/ll.rs b/zynq7000-hal/src/eth/ll.rs
new file mode 100644
index 0000000..c0e20e3
--- /dev/null
+++ b/zynq7000-hal/src/eth/ll.rs
@@ -0,0 +1,212 @@
+use arbitrary_int::{Number, u6};
+use zynq7000::{
+    eth::{InterruptControl, NetworkControl, RxStatus, TxStatus},
+    slcr::reset::EthernetReset,
+};
+
+use crate::{enable_amba_peripheral_clock, slcr::Slcr, time::Hertz};
+
+use super::{EthernetId, PsEthernet as _};
+
+pub struct EthernetLowLevel {
+    id: EthernetId,
+    pub regs: zynq7000::eth::MmioEthernet<'static>,
+}
+
+#[derive(Debug, Clone, Copy)]
+pub struct ClkConfig {
+    pub src_sel: zynq7000::slcr::clocks::SrcSelIo,
+    pub use_emio_tx_clk: bool,
+    pub divisor_0: u6,
+    pub divisor_1: u6,
+    /// Enable the clock.
+    pub enable: bool,
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum Speed {
+    Mbps10,
+    Mbps100,
+    Mbps1000,
+}
+
+impl Speed {
+    pub const fn rgmii_clk_rate(&self) -> Hertz {
+        match self {
+            Speed::Mbps10 => Hertz::from_raw(2_500_000),
+            Speed::Mbps100 => Hertz::from_raw(25_000_000),
+            Speed::Mbps1000 => Hertz::from_raw(125_000_000),
+        }
+    }
+}
+
+impl ClkConfig {
+    pub const fn new(divisor_0: u6, divisor_1: u6) -> Self {
+        Self {
+            src_sel: zynq7000::slcr::clocks::SrcSelIo::IoPll,
+            use_emio_tx_clk: false,
+            divisor_0,
+            divisor_1,
+            enable: true,
+        }
+    }
+
+    /// Calculate the best clock configuration (divisors) for the given reference clock
+    /// and desired target speed when using a RGMII interface.
+    ///
+    /// Usually, the reference clock will be the IO clock.
+    ///
+    /// Returns a tuple where the first entry is the calcualted clock configuration
+    /// and the second entry is the difference between calculated clock speed for the divisors
+    /// and the target speed. Ideally, this difference should be 0.
+    pub fn calculate_for_rgmii(ref_clk: Hertz, target_speed: Speed) -> (Self, u32) {
+        let mut smallest_diff = u32::MAX;
+        let target_speed = target_speed.rgmii_clk_rate();
+        let mut best_div_0 = u6::new(0);
+        let mut best_div_1 = u6::new(0);
+        for div_0 in 0..=u6::MAX.as_usize() {
+            for div_1 in 0..=u6::MAX.as_usize() {
+                let clk_rate = ref_clk.raw() / div_0 as u32 / div_1 as u32;
+                let diff = (target_speed.raw() as i64 - clk_rate as i64).unsigned_abs() as u32;
+                if diff < smallest_diff {
+                    smallest_diff = diff;
+                    best_div_0 = u6::new(div_0 as u8);
+                    best_div_1 = u6::new(div_1 as u8);
+                }
+                // We found a perfect match. No need to continue.
+                if diff == 0 {
+                    break;
+                }
+            }
+        }
+        (Self::new(best_div_0, best_div_1), smallest_diff)
+    }
+}
+
+/// Ethernet low-level interface.
+impl EthernetLowLevel {
+    /// Creates a new instance of the Ethernet low-level interface.
+    #[inline]
+    pub fn new(regs: zynq7000::eth::MmioEthernet<'static>) -> Option<Self> {
+        regs.id()?;
+        Some(EthernetLowLevel {
+            id: regs.id().unwrap(),
+            regs,
+        })
+    }
+
+    /// Create a low-level instance for the given [EthernetId].
+    ///
+    /// # Safety
+    ///
+    /// Circumvents ownership and safety guarantees of the HAL.
+    #[inline]
+    pub const unsafe fn steal(id: EthernetId) -> Self {
+        Self {
+            id,
+            regs: unsafe {
+                match id {
+                    EthernetId::Eth0 => zynq7000::eth::Ethernet::new_mmio_fixed_0(),
+                    EthernetId::Eth1 => zynq7000::eth::Ethernet::new_mmio_fixed_1(),
+                }
+            },
+        }
+    }
+
+    pub fn reset(&mut self, cycles: usize) {
+        let assert_reset = match self.id {
+            EthernetId::Eth0 => EthernetReset::builder()
+                .with_gem1_ref_rst(false)
+                .with_gem0_ref_rst(true)
+                .with_gem1_rx_rst(false)
+                .with_gem0_rx_rst(true)
+                .with_gem1_cpu1x_rst(false)
+                .with_gem0_cpu1x_rst(true)
+                .build(),
+            EthernetId::Eth1 => EthernetReset::builder()
+                .with_gem1_ref_rst(true)
+                .with_gem0_ref_rst(false)
+                .with_gem1_rx_rst(true)
+                .with_gem0_rx_rst(false)
+                .with_gem1_cpu1x_rst(true)
+                .with_gem0_cpu1x_rst(false)
+                .build(),
+        };
+        unsafe {
+            Slcr::with(|regs| {
+                regs.reset_ctrl().write_eth(assert_reset);
+                for _ in 0..cycles {
+                    cortex_ar::asm::nop();
+                }
+                regs.reset_ctrl().write_eth(EthernetReset::DEFAULT);
+            });
+        }
+    }
+
+    #[inline]
+    pub fn enable_peripheral_clock(&mut self) {
+        let periph_sel = match self.id {
+            EthernetId::Eth0 => crate::PeripheralSelect::Gem0,
+            EthernetId::Eth1 => crate::PeripheralSelect::Gem1,
+        };
+        enable_amba_peripheral_clock(periph_sel);
+    }
+
+    #[inline]
+    pub fn configure_clock(&mut self, cfg: ClkConfig) {
+        unsafe {
+            Slcr::with(|regs| {
+                regs.clk_ctrl().modify_gem_0_clk_ctrl(|mut val| {
+                    val.set_srcsel(cfg.src_sel);
+                    val.set_divisor_0(cfg.divisor_0);
+                    val.set_divisor_1(cfg.divisor_1);
+                    val.set_use_emio_tx_clk(cfg.use_emio_tx_clk);
+                    val.set_clk_act(cfg.enable);
+                    val
+                });
+            })
+        }
+    }
+
+    #[inline]
+    pub fn set_promiscous_mode(&mut self, enable: bool) {
+        self.regs.modify_net_cfg(|mut val| {
+            val.set_copy_all_frames(enable);
+            val
+        });
+    }
+
+    #[inline]
+    pub fn set_rx_buf_descriptor_base_address(&mut self, addr: u32) {
+        // self.regs.
+        // TODO
+    }
+
+    #[inline]
+    pub fn set_tx_buf_descriptor_base_address(&mut self, addr: u32) {
+        // self.regs.
+        // TODO
+    }
+
+    /// Performs initialization according to TRM p.541.
+    ///
+    /// These steps do not include any resets or clock configuration.
+    pub fn initialize(&mut self) {
+        let mut ctrl_val = NetworkControl::new_with_raw_value(0);
+        self.regs.write_net_ctrl(ctrl_val);
+        // Now clear statistics.
+        ctrl_val.set_clear_statistics(true);
+        self.regs.write_net_ctrl(ctrl_val);
+        self.regs.write_tx_status(TxStatus::new_clear_all());
+        self.regs.write_rx_status(RxStatus::new_clear_all());
+        self.regs
+            .write_interrupt_disable(InterruptControl::new_clear_all());
+        self.regs.write_rx_buf_queue_base_addr(0);
+        self.regs.write_tx_buf_queue_base_addr(0);
+    }
+
+    #[inline]
+    pub const fn id(&self) -> EthernetId {
+        self.id
+    }
+}
diff --git a/zynq7000-hal/src/eth/mdio.rs b/zynq7000-hal/src/eth/mdio.rs
new file mode 100644
index 0000000..bcb1df6
--- /dev/null
+++ b/zynq7000-hal/src/eth/mdio.rs
@@ -0,0 +1,65 @@
+use arbitrary_int::{u2, u5};
+use zynq7000::eth::{MdcClkDiv, PhyMaintenance};
+
+use super::{EthernetId, ll::EthernetLowLevel};
+
+pub struct Mdio {
+    regs: zynq7000::eth::MmioEthernet<'static>,
+    clause22: bool,
+}
+
+impl Mdio {
+    pub fn new(ll: &EthernetLowLevel, clause22: bool) -> Self {
+        Self {
+            regs: unsafe { ll.regs.clone() },
+            clause22,
+        }
+    }
+
+    /// # Safety
+    ///
+    /// Circumvents ownership and safety guarantees of the HAL.
+    pub unsafe fn steal(eth_id: EthernetId, clause22: bool) -> Self {
+        Self {
+            regs: unsafe { eth_id.steal_regs() },
+            clause22,
+        }
+    }
+
+    #[inline]
+    pub fn configure_clock_div(&mut self, clk_div: MdcClkDiv) {
+        self.regs.modify_net_cfg(|mut val| {
+            val.set_mdc_clk_div(clk_div);
+            val
+        });
+    }
+
+    pub fn read_blocking(&mut self, phy_addr: u5, reg_addr: u5) -> u16 {
+        self.regs.write_phy_maintenance(
+            PhyMaintenance::builder()
+                .with_clause_22(self.clause22)
+                .with_op(zynq7000::eth::PhyOperation::Read)
+                .with_phy_addr(phy_addr)
+                .with_reg_addr(reg_addr)
+                .with_must_be_0b10(u2::new(0b10))
+                .with_data(0x0000)
+                .build(),
+        );
+        while !self.regs.read_net_status().phy_mgmt_idle() {}
+        self.regs.read_phy_maintenance().data()
+    }
+
+    pub fn write_blocking(&mut self, phy_addr: u5, reg_addr: u5, data: u16) {
+        self.regs.write_phy_maintenance(
+            PhyMaintenance::builder()
+                .with_clause_22(self.clause22)
+                .with_op(zynq7000::eth::PhyOperation::Write)
+                .with_phy_addr(phy_addr)
+                .with_reg_addr(reg_addr)
+                .with_must_be_0b10(u2::new(0b10))
+                .with_data(data)
+                .build(),
+        );
+        while !self.regs.read_net_status().phy_mgmt_idle() {}
+    }
+}
diff --git a/zynq7000-hal/src/eth/mod.rs b/zynq7000-hal/src/eth/mod.rs
new file mode 100644
index 0000000..fd2cf46
--- /dev/null
+++ b/zynq7000-hal/src/eth/mod.rs
@@ -0,0 +1,444 @@
+use arbitrary_int::{u2, u3};
+pub use zynq7000::eth::MdcClkDiv;
+use zynq7000::eth::{
+    BurstLength, DmaRxBufSize, GEM_0_BASE_ADDR, GEM_1_BASE_ADDR, MmioEthernet, NetworkConfig,
+    SpeedMode,
+};
+
+pub use ll::{ClkConfig, EthernetLowLevel};
+
+pub mod ll;
+pub mod mdio;
+pub mod rx_descr;
+pub mod tx_descr;
+
+const MTU: usize = 1536;
+
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+use crate::gpio::mio::{
+    Mio16, Mio17, Mio18, Mio19, Mio20, Mio21, Mio22, Mio23, Mio24, Mio25, Mio26, Mio27,
+};
+use crate::gpio::{
+    IoPeriphPin,
+    mio::{
+        Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, Mio52,
+        Mio53, MioPinMarker, MuxConf, Pin,
+    },
+};
+
+pub const MUX_CONF_PHY: MuxConf = MuxConf::new_with_l0();
+pub const MUX_CONF_MDIO: MuxConf = MuxConf::new_with_l3(u3::new(0b100));
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum EthernetId {
+    Eth0 = 0,
+    Eth1 = 1,
+}
+
+impl EthernetId {
+    /// Steal the ethernet register block for the given ethernet ID.
+    ///
+    /// # Safety
+    ///
+    /// Circumvents ownership and safety guarantees of the HAL.
+    pub const unsafe fn steal_regs(&self) -> zynq7000::eth::MmioEthernet<'static> {
+        unsafe {
+            match self {
+                EthernetId::Eth0 => zynq7000::eth::Ethernet::new_mmio_fixed_0(),
+                EthernetId::Eth1 => zynq7000::eth::Ethernet::new_mmio_fixed_1(),
+            }
+        }
+    }
+}
+
+pub trait PsEthernet {
+    fn reg_block(&self) -> MmioEthernet<'static>;
+    fn id(&self) -> Option<EthernetId>;
+}
+
+impl PsEthernet for MmioEthernet<'static> {
+    #[inline]
+    fn reg_block(&self) -> MmioEthernet<'static> {
+        unsafe { self.clone() }
+    }
+
+    #[inline]
+    fn id(&self) -> Option<EthernetId> {
+        let base_addr = unsafe { self.ptr() } as usize;
+        if base_addr == GEM_0_BASE_ADDR {
+            return Some(EthernetId::Eth0);
+        } else if base_addr == GEM_1_BASE_ADDR {
+            return Some(EthernetId::Eth1);
+        }
+        None
+    }
+}
+
+pub trait TxClk: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait TxCtrl: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait TxData0: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait TxData1: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait TxData2: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait TxData3: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait RxClk: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait RxCtrl: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait RxData0: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait RxData1: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait RxData2: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+pub trait RxData3: MioPinMarker {
+    const ETH_ID: EthernetId;
+}
+
+pub trait MdClk: MioPinMarker {}
+pub trait MdIo: MioPinMarker {}
+
+impl MdClk for Pin<Mio52> {}
+impl MdIo for Pin<Mio53> {}
+
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl TxClk for Pin<Mio16> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl TxCtrl for Pin<Mio21> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl TxData0 for Pin<Mio17> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl TxData1 for Pin<Mio18> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl TxData2 for Pin<Mio19> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl TxData3 for Pin<Mio20> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl RxClk for Pin<Mio22> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl RxCtrl for Pin<Mio27> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl RxData0 for Pin<Mio23> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl RxData1 for Pin<Mio24> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl RxData2 for Pin<Mio25> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+#[cfg(not(feature = "7z010-7z007s-clg225"))]
+impl RxData3 for Pin<Mio26> {
+    const ETH_ID: EthernetId = EthernetId::Eth0;
+}
+
+impl TxClk for Pin<Mio28> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl TxCtrl for Pin<Mio33> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl TxData0 for Pin<Mio29> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl TxData1 for Pin<Mio30> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl TxData2 for Pin<Mio31> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl TxData3 for Pin<Mio32> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl RxClk for Pin<Mio34> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl RxCtrl for Pin<Mio39> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl RxData0 for Pin<Mio35> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl RxData1 for Pin<Mio36> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl RxData2 for Pin<Mio37> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+impl RxData3 for Pin<Mio38> {
+    const ETH_ID: EthernetId = EthernetId::Eth1;
+}
+
+#[derive(Debug, Clone, Copy)]
+pub struct EthernetConfig {
+    pub clk_config: ClkConfig,
+    pub mdc_clk_div: MdcClkDiv,
+    pub mac_address: [u8; 6],
+}
+
+impl EthernetConfig {
+    pub fn new(clk_config: ClkConfig, mdc_clk_div: MdcClkDiv, mac_address: [u8; 6]) -> Self {
+        Self {
+            clk_config,
+            mdc_clk_div,
+            mac_address,
+        }
+    }
+}
+
+pub struct Ethernet {
+    ll: ll::EthernetLowLevel,
+    mdio: mdio::Mdio,
+}
+
+impl Ethernet {
+    #[allow(clippy::too_many_arguments)]
+    pub fn new_with_mio<
+        TxClkPin: TxClk,
+        TxCtrlPin: TxCtrl,
+        TxData0Pin: TxData0,
+        TxData1Pin: TxData1,
+        TxData2Pin: TxData2,
+        TxData3Pin: TxData3,
+        RxClkPin: RxClk,
+        RxCtrlPin: RxCtrl,
+        RxData0Pin: RxData0,
+        RxData1Pin: RxData1,
+        RxData2Pin: RxData2,
+        RxData3Pin: RxData3,
+        MdClkPin: MdClk,
+        MdIoPin: MdIo,
+    >(
+        mut ll: ll::EthernetLowLevel,
+        config: EthernetConfig,
+        tx_clk: TxClkPin,
+        tx_ctrl: TxCtrlPin,
+        tx_data: (TxData0Pin, TxData1Pin, TxData2Pin, TxData3Pin),
+        rx_clk: RxClkPin,
+        rx_ctrl: RxCtrlPin,
+        rx_data: (RxData0Pin, RxData1Pin, RxData2Pin, RxData3Pin),
+        md_pins: Option<(MdClkPin, MdIoPin)>,
+    ) -> Self {
+        Self::common_init(&mut ll, config.mac_address);
+        let tx_mio_config = zynq7000::slcr::mio::Config::builder()
+            .with_disable_hstl_rcvr(true)
+            .with_pullup(true)
+            .with_io_type(zynq7000::slcr::mio::IoType::Hstl)
+            .with_speed(zynq7000::slcr::mio::Speed::FastCmosEdge)
+            .with_l3_sel(MUX_CONF_PHY.l3_sel())
+            .with_l2_sel(MUX_CONF_PHY.l2_sel())
+            .with_l1_sel(MUX_CONF_PHY.l1_sel())
+            .with_l0_sel(MUX_CONF_PHY.l0_sel())
+            .with_tri_enable(false)
+            .build();
+        let rx_mio_config = zynq7000::slcr::mio::Config::builder()
+            .with_disable_hstl_rcvr(false)
+            .with_pullup(true)
+            .with_io_type(zynq7000::slcr::mio::IoType::Hstl)
+            .with_speed(zynq7000::slcr::mio::Speed::FastCmosEdge)
+            .with_l3_sel(MUX_CONF_PHY.l3_sel())
+            .with_l2_sel(MUX_CONF_PHY.l2_sel())
+            .with_l1_sel(MUX_CONF_PHY.l1_sel())
+            .with_l0_sel(MUX_CONF_PHY.l0_sel())
+            // Disable output driver.
+            .with_tri_enable(true)
+            .build();
+        unsafe {
+            crate::slcr::Slcr::with(|slcr_mut| {
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    tx_clk,
+                    slcr_mut,
+                    tx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    tx_ctrl,
+                    slcr_mut,
+                    tx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    tx_data.0,
+                    slcr_mut,
+                    tx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    tx_data.1,
+                    slcr_mut,
+                    tx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    tx_data.2,
+                    slcr_mut,
+                    tx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    tx_data.3,
+                    slcr_mut,
+                    tx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    rx_clk,
+                    slcr_mut,
+                    rx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    rx_ctrl,
+                    slcr_mut,
+                    rx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    rx_data.0,
+                    slcr_mut,
+                    rx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    rx_data.1,
+                    slcr_mut,
+                    rx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    rx_data.2,
+                    slcr_mut,
+                    rx_mio_config,
+                );
+                IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                    rx_data.3,
+                    slcr_mut,
+                    rx_mio_config,
+                );
+                if let Some((md_clk, md_io)) = md_pins {
+                    let md_mio_config = zynq7000::slcr::mio::Config::builder()
+                        .with_disable_hstl_rcvr(false)
+                        .with_pullup(true)
+                        .with_io_type(zynq7000::slcr::mio::IoType::LvCmos18)
+                        .with_speed(zynq7000::slcr::mio::Speed::SlowCmosEdge)
+                        .with_l3_sel(MUX_CONF_MDIO.l3_sel())
+                        .with_l2_sel(MUX_CONF_MDIO.l2_sel())
+                        .with_l1_sel(MUX_CONF_MDIO.l1_sel())
+                        .with_l0_sel(MUX_CONF_MDIO.l0_sel())
+                        .with_tri_enable(false)
+                        .build();
+                    IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                        md_clk,
+                        slcr_mut,
+                        md_mio_config,
+                    );
+                    IoPeriphPin::new_with_full_config_and_unlocked_slcr(
+                        md_io,
+                        slcr_mut,
+                        md_mio_config,
+                    );
+                }
+                // Enable VREF internal generator, which is required for HSTL pin mode.
+                slcr_mut.gpiob().modify_ctrl(|mut ctrl| {
+                    ctrl.set_vref_en(true);
+                    ctrl
+                });
+            });
+        }
+        ll.configure_clock(config.clk_config);
+        let mut mdio = mdio::Mdio::new(&ll, true);
+        mdio.configure_clock_div(config.mdc_clk_div);
+        Ethernet { ll, mdio }
+    }
+
+    pub fn new(mut ll: EthernetLowLevel, config: EthernetConfig) -> Self {
+        Self::common_init(&mut ll, config.mac_address);
+        ll.configure_clock(config.clk_config);
+        let mut mdio = mdio::Mdio::new(&ll, true);
+        mdio.configure_clock_div(config.mdc_clk_div);
+        Ethernet { ll, mdio }
+    }
+
+    fn common_init(ll: &mut EthernetLowLevel, mac_address: [u8; 6]) {
+        ll.enable_peripheral_clock();
+        ll.reset(3);
+        ll.initialize();
+        // By default, only modify critical network control bits to retain user configuration
+        // like the MDC clock divisor.
+        ll.regs.modify_net_cfg(|mut net_cfg| {
+            net_cfg.set_full_duplex(true);
+            net_cfg.set_gigabit_enable(true);
+            net_cfg.set_speed_mode(SpeedMode::High100Mbps);
+            net_cfg
+        });
+        let macaddr_msbs = (u32::from(mac_address[5]) << 8) | u32::from(mac_address[4]);
+        let macaddr_lsbs = (u32::from(mac_address[3]) << 24)
+            | (u32::from(mac_address[2]) << 16)
+            | (u32::from(mac_address[1]) << 8)
+            | u32::from(mac_address[0]);
+        // Writing to the lower address portion disables the address match, writing to the higher
+        // portion enables it again. Address matching is disabled on reset, so we do not need
+        // to disable the other addresses here.
+        ll.regs.write_addr1_low(macaddr_lsbs);
+        ll.regs.write_addr1_high(macaddr_msbs);
+        // TODO
+        ll.regs.modify_dma_cfg(|mut val| {
+            val.set_rx_packet_buf_size_sel(u2::new(0b11));
+            val.set_tx_packet_buf_size_sel(true);
+            val.set_burst_length(BurstLength::Incr16.reg_value());
+            // Configure 1536 bytes receive buffer size. This is sufficient for regular Ethernet
+            // frames.
+            val.set_dma_rx_ahb_buf_size_sel(DmaRxBufSize::new((MTU >> 6) as u8).unwrap());
+            val.set_endian_swap_mgmt_descriptor(zynq7000::eth::AhbEndianess::Little);
+            val
+        });
+    }
+
+    #[inline]
+    pub fn ll(&mut self) -> &mut EthernetLowLevel {
+        &mut self.ll
+    }
+
+    #[inline]
+    pub fn regs(&mut self) -> &MmioEthernet<'static> {
+        &self.ll.regs
+    }
+
+    #[inline]
+    pub fn regs_mut(&mut self) -> &mut MmioEthernet<'static> {
+        &mut self.ll.regs
+    }
+}
+
+mod shared {
+    #[bitbybit::bitenum(u1, exhaustive = true)]
+    #[derive(Debug, PartialEq, Eq)]
+    pub enum Ownership {
+        Hardware = 0,
+        Software = 1,
+    }
+}
diff --git a/zynq7000-hal/src/eth/rx_descr.rs b/zynq7000-hal/src/eth/rx_descr.rs
new file mode 100644
index 0000000..b7a4d52
--- /dev/null
+++ b/zynq7000-hal/src/eth/rx_descr.rs
@@ -0,0 +1,122 @@
+//! RX buffer descriptor module.
+pub use super::shared::Ownership;
+use arbitrary_int::{u2, u3, u13, u30};
+
+/// RX buffer descriptor.
+///
+/// The user should declare an array of this structure inside uncached memory.
+///
+/// These descriptors are shared between software and hardware and contain information
+/// related to frame reception.
+#[repr(C)]
+pub struct Descriptor {
+    /// The first word of the descriptor.
+    pub word0: Word0,
+    /// The second word of the descriptor.
+    pub word1: Word1,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug, PartialEq, Eq)]
+pub struct Word0 {
+    /// The full reception address with the last two bits cleared.
+    #[bits(2..=31, rw)]
+    addr_upper_30_bits: u30,
+    #[bit(1, rw)]
+    wrap: bool,
+    #[bit(0, rw)]
+    ownership: Ownership,
+}
+
+/// This control word contains the status bits.
+///
+/// If the end of frame bit (15) is not set, the only valid status information is the start of
+/// frame bit.
+#[bitbybit::bitfield(u32)]
+#[derive(Debug, PartialEq, Eq)]
+pub struct Word1 {
+    #[bit(31, r)]
+    broadcast_detect: bool,
+    #[bit(30, r)]
+    multicast_hash: bool,
+    #[bit(29, r)]
+    unicast_hash: bool,
+    #[bit(27, r)]
+    specific_addr_match: bool,
+    /// Specifies which of the 4 specific address registers was matched.
+    #[bits(25..=26, r)]
+    specific_addr_match_info: u2,
+    #[bit(24, r)]
+    type_id_match_or_snap_info: bool,
+    #[bits(22..=23, r)]
+    type_id_match_info_or_chksum_status: u2,
+    #[bit(21, r)]
+    vlan_tag_detected: bool,
+    #[bit(20, r)]
+    priority_tag_detected: bool,
+    #[bits(17..=19, r)]
+    vlan_prio: u3,
+    #[bit(16, r)]
+    cfi_bit: bool,
+    /// If this bit is not set, the only other valid status bit is the start of frame bit.
+    #[bit(15, r)]
+    end_of_frame: bool,
+    #[bit(14, r)]
+    start_of_frame: bool,
+    /// Relevant when FCS errors are not ignored.
+    /// 0: Frame has good FCS, 1: Frame has bad FCS, but was copied to memory as the ignore FCS
+    /// functionality was enabled.
+    #[bit(13, r)]
+    fcs_status: bool,
+    #[bits(0..=12, r)]
+    rx_len: u13,
+}
+
+impl Descriptor {
+    #[inline]
+    pub fn set_ownership(&mut self, ownership: Ownership) {
+        self.word0.set_ownership(ownership);
+    }
+
+    #[inline]
+    pub fn set_wrap_bit(&mut self) {
+        self.word0.set_wrap(true);
+    }
+
+    #[inline]
+    pub fn write_rx_addr(&mut self, addr: u32) {
+        self.word0.set_addr_upper_30_bits(u30::new(addr >> 2));
+    }
+}
+
+pub struct DescriptorListRef<'a>(&'a [Descriptor]);
+
+impl DescriptorListRef<'_> {
+    #[inline]
+    pub fn new(descriptor: &[Descriptor]) -> Self {
+        Self(descriptor)
+    }
+
+    #[inline]
+    pub fn base_ptr(&self) -> *const Descriptor {
+        self.0.as_ptr()
+    }
+
+    #[inline]
+    pub fn base_addr(&self) -> u32 {
+        self.base_ptr() as u32
+    }
+
+    pub fn init(&mut self) {
+        for desc in self.0.iter_mut() {
+            desc.set_ownership(Ownership::Hardware);
+        }
+        self.0.last().unwrap().set_wrap_bit();
+    }
+
+    pub fn set_rx_buf_addresses<const S: usize>(&mut self, buf: &[[u8; S]]) {
+        for (desc, buf) in self.0.iter_mut().zip(buf.iter()) {
+            desc.write_rx_addr(buf.as_ptr() as u32);
+        }
+    }
+}
diff --git a/zynq7000-hal/src/eth/tx_descr.rs b/zynq7000-hal/src/eth/tx_descr.rs
new file mode 100644
index 0000000..fa2915c
--- /dev/null
+++ b/zynq7000-hal/src/eth/tx_descr.rs
@@ -0,0 +1,103 @@
+use arbitrary_int::u14;
+
+pub use super::shared::Ownership;
+
+/// TX buffer descriptor.
+///
+/// The user should declare an array of this structure inside uncached memory.
+///
+/// These descriptors are shared between software and hardware and contain information
+/// related to frame reception.
+#[repr(C)]
+pub struct Descriptor {
+    /// The first word of the descriptor which is the byte address of the buffer.
+    pub word0: u32,
+    /// The second word of the descriptor.
+    pub word1: Word1,
+}
+
+#[bitbybit::bitenum(u3, exhaustive = true)]
+#[derive(Debug, PartialEq, Eq)]
+pub enum TransmitChecksumGenerationStatus {
+    NoError = 0b000,
+    VlanError = 0b001,
+    SnapError = 0b010,
+    IpError = 0b011,
+    NotVlanOrSnapOrIp = 0b100,
+    NonSupportedPacketFragmentation = 0b101,
+    PacketNotTcpUdp = 0b110,
+    PrematureEndOfFrame = 0b111,
+}
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug, PartialEq, Eq)]
+pub struct Word1 {
+    #[bit(31, rw)]
+    ownership: Ownership,
+    #[bit(30, rw)]
+    wrap: bool,
+    #[bit(29, rw)]
+    retry_limit_exceeded: bool,
+    #[bit(27, rw)]
+    transmit_frame_corruption_ahb_error: bool,
+    #[bit(26, rw)]
+    late_collision: bool,
+    #[bits(20..=22, rw)]
+    checksum_status: TransmitChecksumGenerationStatus,
+    #[bit(16, rw)]
+    no_crc_generation: bool,
+    #[bit(15, rw)]
+    last_buffer: bool,
+    #[bits(0..=13, rw)]
+    tx_len: u14,
+}
+
+impl Descriptor {
+    #[inline]
+    pub fn set_ownership(&mut self, ownership: Ownership) {
+        self.word1.set_ownership(ownership);
+    }
+
+    /// Set the wrap bit, which should be done for the last descriptor in the descriptor list.
+    #[inline]
+    pub fn set_wrap_bit(&mut self) {
+        self.word1.set_wrap(true);
+    }
+
+    /// Set the information for a transfer.
+    pub fn set_tx_transfer_info(
+        &mut self,
+        tx_len: u14,
+        last_buffer: bool,
+        no_crc_generation: bool,
+    ) {
+        self.word1.set_tx_len(tx_len);
+        self.word1.set_last_buffer(last_buffer);
+        self.word1.set_no_crc_generation(no_crc_generation);
+    }
+}
+
+pub struct DescriptorListRef<'a>(&'a [Descriptor]);
+
+impl DescriptorListRef {
+    pub fn new(descriptor: &[Descriptor]) -> Self {
+        Self(descriptor)
+    }
+
+    #[inline]
+    pub fn base_ptr(&self) -> *const Descriptor {
+        self.0.as_ptr()
+    }
+
+    #[inline]
+    pub fn base_addr(&self) -> u32 {
+        self.base_ptr() as u32
+    }
+
+    pub fn init(&mut self) {
+        for desc in self.0.iter_mut() {
+            desc.set_ownership(Ownership::Hardware);
+        }
+        self.0.last().unwrap().set_wrap_bit();
+    }
+}
diff --git a/zynq7000-hal/src/gpio/ll.rs b/zynq7000-hal/src/gpio/ll.rs
index a05681d..9313681 100644
--- a/zynq7000-hal/src/gpio/ll.rs
+++ b/zynq7000-hal/src/gpio/ll.rs
@@ -4,7 +4,7 @@ use zynq7000::gpio::{Gpio, MaskedOutput, MmioGpio};
 
 use crate::slcr::Slcr;
 
-use super::{mio::MuxConf, PinIsOutputOnly};
+use super::{PinIsOutputOnly, mio::MuxConf};
 
 #[derive(Debug, Clone, Copy)]
 pub enum PinOffset {
@@ -148,6 +148,23 @@ impl LowLevelGpio {
         self.reconfigure_slcr_mio_cfg(false, pullup, Some(mux_conf));
     }
 
+    pub fn set_mio_pin_config(&mut self, config: zynq7000::slcr::mio::Config) {
+        let raw_offset = self.offset.offset();
+        // Safety: We only modify the MIO config of the pin.
+        let mut slcr_wrapper = unsafe { Slcr::steal() };
+        slcr_wrapper.modify(|mut_slcr| mut_slcr.write_mio_pins(raw_offset, config).unwrap());
+    }
+
+    /// Set the MIO pin configuration with an unlocked SLCR.
+    pub fn set_mio_pin_config_with_unlocked_slcr(
+        &mut self,
+        slcr: &mut zynq7000::slcr::MmioSlcr<'static>,
+        config: zynq7000::slcr::mio::Config,
+    ) {
+        let raw_offset = self.offset.offset();
+        slcr.write_mio_pins(raw_offset, config).unwrap();
+    }
+
     #[inline]
     pub fn is_low(&self) -> bool {
         let (offset, in_reg) = self.get_data_in_reg_and_local_offset();
diff --git a/zynq7000-hal/src/gpio/mio.rs b/zynq7000-hal/src/gpio/mio.rs
index 3ce38f2..ca6fc59 100644
--- a/zynq7000-hal/src/gpio/mio.rs
+++ b/zynq7000-hal/src/gpio/mio.rs
@@ -31,6 +31,10 @@ impl MuxConf {
         Self { l3, l2, l1, l0 }
     }
 
+    pub const fn new_with_l0() -> Self {
+        Self::new(true, false, u2::new(0b00), u3::new(0b000))
+    }
+
     pub const fn new_with_l3(l3: u3) -> Self {
         Self::new(false, false, u2::new(0b00), l3)
     }
diff --git a/zynq7000-hal/src/gpio/mod.rs b/zynq7000-hal/src/gpio/mod.rs
index 60cc5d1..29afee9 100644
--- a/zynq7000-hal/src/gpio/mod.rs
+++ b/zynq7000-hal/src/gpio/mod.rs
@@ -172,7 +172,8 @@ impl Flex {
 
     pub fn configure_as_output_open_drain(&mut self, level: PinState, with_internal_pullup: bool) {
         self.mode = PinMode::OutputOpenDrain;
-        self.ll.configure_as_output_open_drain(level, with_internal_pullup);
+        self.ll
+            .configure_as_output_open_drain(level, with_internal_pullup);
     }
 
     /// If the pin is configured as an input pin, this function does nothing.
@@ -383,6 +384,8 @@ pub struct IoPeriphPin {
 }
 
 impl IoPeriphPin {
+    /// Constructor for IO peripheral pins where only the multiplexer and pullup configuration
+    /// need to be changed.
     pub fn new(pin: impl MioPinMarker, mux_conf: MuxConf, pullup: Option<bool>) -> Self {
         let mut low_level = LowLevelGpio::new(PinOffset::Mio(pin.offset()));
         low_level.configure_as_io_periph_pin(mux_conf, pullup);
@@ -391,6 +394,43 @@ impl IoPeriphPin {
             mux_conf,
         }
     }
+
+    /// Constructor to fully configure an IO peripheral pin with a specific MIO pin configuration.
+    pub fn new_with_full_config(
+        pin: impl MioPinMarker,
+        config: zynq7000::slcr::mio::Config,
+    ) -> Self {
+        let mut low_level = LowLevelGpio::new(PinOffset::Mio(pin.offset()));
+        low_level.set_mio_pin_config(config);
+        Self {
+            pin: low_level,
+            mux_conf: MuxConf::new(
+                config.l0_sel(),
+                config.l1_sel(),
+                config.l2_sel(),
+                config.l3_sel(),
+            ),
+        }
+    }
+
+    /// Constructor to fully configure an IO peripheral pin with a specific MIO pin configuration.
+    pub fn new_with_full_config_and_unlocked_slcr(
+        pin: impl MioPinMarker,
+        slcr: &mut zynq7000::slcr::MmioSlcr<'static>,
+        config: zynq7000::slcr::mio::Config,
+    ) -> Self {
+        let mut low_level = LowLevelGpio::new(PinOffset::Mio(pin.offset()));
+        low_level.set_mio_pin_config_with_unlocked_slcr(slcr, config);
+        Self {
+            pin: low_level,
+            mux_conf: MuxConf::new(
+                config.l0_sel(),
+                config.l1_sel(),
+                config.l2_sel(),
+                config.l3_sel(),
+            ),
+        }
+    }
 }
 
 impl IoPinProvider for IoPeriphPin {
diff --git a/zynq7000-hal/src/lib.rs b/zynq7000-hal/src/lib.rs
index 9ef1931..ee54b3c 100644
--- a/zynq7000-hal/src/lib.rs
+++ b/zynq7000-hal/src/lib.rs
@@ -13,11 +13,13 @@ use slcr::Slcr;
 use zynq7000::slcr::LevelShifterReg;
 
 pub mod clocks;
+pub mod eth;
 pub mod gic;
 pub mod gpio;
 pub mod gtc;
 pub mod i2c;
 pub mod log;
+pub mod mmu;
 pub mod prelude;
 pub mod slcr;
 pub mod spi;
diff --git a/zynq7000-hal/src/mmu.rs b/zynq7000-hal/src/mmu.rs
new file mode 100644
index 0000000..11662ea
--- /dev/null
+++ b/zynq7000-hal/src/mmu.rs
@@ -0,0 +1,16 @@
+use zynq_mmu::L1Table;
+
+pub struct Mmu(&'static mut L1Table);
+
+impl Mmu {
+    #[inline]
+    pub const fn new(table: &'static mut L1Table) -> Self {
+        Mmu(table)
+    }
+
+    pub fn update_l1_table(&mut self, f: impl FnOnce(&mut L1Table)) {
+        // TODO: Disable MMU
+        f(self.0);
+        // DSB, ISB? enable MMU again.
+    }
+}
diff --git a/zynq7000-hal/src/slcr.rs b/zynq7000-hal/src/slcr.rs
index 778e1f4..1c710ea 100644
--- a/zynq7000-hal/src/slcr.rs
+++ b/zynq7000-hal/src/slcr.rs
@@ -14,7 +14,7 @@ impl Slcr {
     /// This method unsafely steals the SLCR MMIO block and then calls a user provided function
     /// with the [SLCR MMIO][MmioSlcr] block as an input argument. It is the user's responsibility
     /// that the SLCR is not used concurrently in a way which leads to data races.
-    pub unsafe fn with<F: FnMut(&mut MmioSlcr)>(mut f: F) {
+    pub unsafe fn with<F: FnOnce(&mut MmioSlcr<'static>)>(f: F) {
         let mut slcr = unsafe { zynq7000::slcr::Slcr::new_mmio_fixed() };
         slcr.write_unlock(UNLOCK_KEY);
         f(&mut slcr);
diff --git a/zynq7000-rt/Cargo.toml b/zynq7000-rt/Cargo.toml
index 50ca596..df88cb9 100644
--- a/zynq7000-rt/Cargo.toml
+++ b/zynq7000-rt/Cargo.toml
@@ -11,8 +11,9 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-cortex-a-rt = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main", optional = true, features = ["vfp-dp"] }
-cortex-ar = { git = "https://github.com/rust-embedded/cortex-ar", branch = "main" }
+cortex-a-rt = { version = "0.1", optional = true, features = ["vfp-dp"] }
+cortex-ar = "0.2"
+zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
 
 [features]
 default = ["rt"]
diff --git a/zynq7000-rt/src/bin/table-gen.rs b/zynq7000-rt/src/bin/table-gen.rs
index b8a440b..92b58db 100644
--- a/zynq7000-rt/src/bin/table-gen.rs
+++ b/zynq7000-rt/src/bin/table-gen.rs
@@ -4,6 +4,17 @@ use std::process::Command;
 use zynq7000_rt::mmu::ONE_MB;
 pub use zynq7000_rt::mmu::segments::*;
 
+macro_rules! write_l1_section {
+    ($writer:expr, $offset:expr, $attr:expr) => {
+        writeln!(
+            $writer,
+            "L1Section::new({:#010x}, {}).raw_value(),",
+            $offset, $attr
+        )
+        .unwrap();
+    };
+}
+
 fn main() {
     let file_path = "src/mmu_table.rs";
     let file = File::create(file_path).expect("Failed to create file");
@@ -35,6 +46,7 @@ fn main() {
             + OCM_MAPPED_HIGH,
         4096
     );
+
     let mut buf_writer = std::io::BufWriter::new(file);
     writeln!(
         buf_writer,
@@ -63,44 +75,24 @@ fn main() {
         "// First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000)"
     )
     .unwrap();
-    writeln!(
-        buf_writer,
-        "L1Section::new({}, {}).raw_value(),",
-        offset, attr_ddr
-    )
-    .unwrap();
+    write_l1_section!(buf_writer, offset, attr_ddr);
 
     offset += ONE_MB;
     writeln!(buf_writer, "// DDR memory (0x00100000 - 0x4000_0000)").unwrap();
     for _ in 0..DDR_FULL_ACCESSIBLE {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_ddr
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_ddr);
         offset += ONE_MB;
     }
 
     writeln!(buf_writer, "// FPGA slave 0 (0x4000_0000 - 0x8000_0000)").unwrap();
     for _ in 0..FPGA_SLAVE {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_fpga_slaves
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_fpga_slaves);
         offset += ONE_MB;
     }
 
     writeln!(buf_writer, "// FPGA slave 1 (0x8000_0000 - 0xC000_0000)").unwrap();
     for _ in 0..FPGA_SLAVE {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_fpga_slaves
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_fpga_slaves);
         offset += ONE_MB;
     }
 
@@ -110,12 +102,7 @@ fn main() {
     )
     .unwrap();
     for _ in 0..UNASSIGNED_0 {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_unassigned
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_unassigned);
         offset += ONE_MB;
     }
 
@@ -125,12 +112,7 @@ fn main() {
     )
     .unwrap();
     for _ in 0..IO_PERIPHS {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_shared_dev
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_shared_dev);
         offset += ONE_MB;
     }
 
@@ -140,45 +122,25 @@ fn main() {
     )
     .unwrap();
     for _ in 0..UNASSIGNED_1 {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_unassigned
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_unassigned);
         offset += ONE_MB;
     }
 
     writeln!(buf_writer, "// NAND (0xE100_0000 - 0xE200_0000)").unwrap();
     for _ in 0..NAND {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_shared_dev
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_shared_dev);
         offset += ONE_MB;
     }
 
     writeln!(buf_writer, "// NOR (0xE200_0000 - 0xE400_0000)").unwrap();
     for _ in 0..NOR {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_shared_dev
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_shared_dev);
         offset += ONE_MB;
     }
 
     writeln!(buf_writer, "// SRAM (0xE400_0000 - 0xE600_0000)").unwrap();
     for _ in 0..SRAM {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_sram
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_sram);
         offset += ONE_MB;
     }
 
@@ -188,12 +150,7 @@ fn main() {
     )
     .unwrap();
     for _ in 0..SEGMENTS_UNASSIGNED_2 {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_unassigned
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_unassigned);
         offset += ONE_MB;
     }
 
@@ -203,12 +160,7 @@ fn main() {
     )
     .unwrap();
     for _ in 0..AMBA_APB {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_shared_dev
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_shared_dev);
         offset += ONE_MB;
     }
 
@@ -218,23 +170,13 @@ fn main() {
     )
     .unwrap();
     for _ in 0..UNASSIGNED_3 {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_unassigned
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_unassigned);
         offset += ONE_MB;
     }
 
     writeln!(buf_writer, "// QSPI XIP (0xFC00_0000 - 0xFE00_0000)").unwrap();
     for _ in 0..QSPI_XIP {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_qspi
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_qspi);
         offset += ONE_MB;
     }
 
@@ -244,24 +186,14 @@ fn main() {
     )
     .unwrap();
     for _ in 0..UNASSIGNED_4 {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_unassigned
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_unassigned);
         offset += ONE_MB;
     }
 
     writeln!(buf_writer, "// OCM High (0xFFF0_0000 - 0xFFFF_FFFF)").unwrap();
     let mut offset_u64 = offset as u64;
     for _ in 0..OCM_MAPPED_HIGH {
-        writeln!(
-            buf_writer,
-            "L1Section::new({}, {}).raw_value(),",
-            offset, attr_ocm_high
-        )
-        .unwrap();
+        write_l1_section!(buf_writer, offset, attr_ocm_high);
 
         offset_u64 += ONE_MB as u64;
     }
diff --git a/zynq7000-rt/src/mmu.rs b/zynq7000-rt/src/mmu.rs
index fc1925a..3b54b30 100644
--- a/zynq7000-rt/src/mmu.rs
+++ b/zynq7000-rt/src/mmu.rs
@@ -162,12 +162,6 @@ pub mod section_attrs {
     };
 }
 
-pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
-
-#[repr(C, align(16384))]
-#[cfg(feature = "rt")]
-pub struct L1Table(pub(crate) [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
-
 /// Load the MMU translation table base address into the MMU.
 ///
 /// # Safety
diff --git a/zynq7000-rt/src/mmu_table.rs b/zynq7000-rt/src/mmu_table.rs
index cf791d6..86cf1b3 100644
--- a/zynq7000-rt/src/mmu_table.rs
+++ b/zynq7000-rt/src/mmu_table.rs
@@ -1,4121 +1,4122 @@
 //! This file was auto-generated by table-gen.rs
-use crate::mmu::{L1Table, section_attrs};
+use crate::mmu::section_attrs;
 use cortex_ar::mmu::L1Section;
+use zynq_mmu::L1Table;
 
 /// MMU Level 1 Page table.
 ///
 /// 4096 entries, each covering 1MB of the address space.
 pub const MMU_L1_PAGE_TABLE: L1Table = L1Table([
     // First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000)
-    L1Section::new(0, section_attrs::DDR).raw_value(),
+    L1Section::new(0x00000000, section_attrs::DDR).raw_value(),
     // DDR memory (0x00100000 - 0x4000_0000)
-    L1Section::new(1048576, section_attrs::DDR).raw_value(),
-    L1Section::new(2097152, section_attrs::DDR).raw_value(),
-    L1Section::new(3145728, section_attrs::DDR).raw_value(),
-    L1Section::new(4194304, section_attrs::DDR).raw_value(),
-    L1Section::new(5242880, section_attrs::DDR).raw_value(),
-    L1Section::new(6291456, section_attrs::DDR).raw_value(),
-    L1Section::new(7340032, section_attrs::DDR).raw_value(),
-    L1Section::new(8388608, section_attrs::DDR).raw_value(),
-    L1Section::new(9437184, section_attrs::DDR).raw_value(),
-    L1Section::new(10485760, section_attrs::DDR).raw_value(),
-    L1Section::new(11534336, section_attrs::DDR).raw_value(),
-    L1Section::new(12582912, section_attrs::DDR).raw_value(),
-    L1Section::new(13631488, section_attrs::DDR).raw_value(),
-    L1Section::new(14680064, section_attrs::DDR).raw_value(),
-    L1Section::new(15728640, section_attrs::DDR).raw_value(),
-    L1Section::new(16777216, section_attrs::DDR).raw_value(),
-    L1Section::new(17825792, section_attrs::DDR).raw_value(),
-    L1Section::new(18874368, section_attrs::DDR).raw_value(),
-    L1Section::new(19922944, section_attrs::DDR).raw_value(),
-    L1Section::new(20971520, section_attrs::DDR).raw_value(),
-    L1Section::new(22020096, section_attrs::DDR).raw_value(),
-    L1Section::new(23068672, section_attrs::DDR).raw_value(),
-    L1Section::new(24117248, section_attrs::DDR).raw_value(),
-    L1Section::new(25165824, section_attrs::DDR).raw_value(),
-    L1Section::new(26214400, section_attrs::DDR).raw_value(),
-    L1Section::new(27262976, section_attrs::DDR).raw_value(),
-    L1Section::new(28311552, section_attrs::DDR).raw_value(),
-    L1Section::new(29360128, section_attrs::DDR).raw_value(),
-    L1Section::new(30408704, section_attrs::DDR).raw_value(),
-    L1Section::new(31457280, section_attrs::DDR).raw_value(),
-    L1Section::new(32505856, section_attrs::DDR).raw_value(),
-    L1Section::new(33554432, section_attrs::DDR).raw_value(),
-    L1Section::new(34603008, section_attrs::DDR).raw_value(),
-    L1Section::new(35651584, section_attrs::DDR).raw_value(),
-    L1Section::new(36700160, section_attrs::DDR).raw_value(),
-    L1Section::new(37748736, section_attrs::DDR).raw_value(),
-    L1Section::new(38797312, section_attrs::DDR).raw_value(),
-    L1Section::new(39845888, section_attrs::DDR).raw_value(),
-    L1Section::new(40894464, section_attrs::DDR).raw_value(),
-    L1Section::new(41943040, section_attrs::DDR).raw_value(),
-    L1Section::new(42991616, section_attrs::DDR).raw_value(),
-    L1Section::new(44040192, section_attrs::DDR).raw_value(),
-    L1Section::new(45088768, section_attrs::DDR).raw_value(),
-    L1Section::new(46137344, section_attrs::DDR).raw_value(),
-    L1Section::new(47185920, section_attrs::DDR).raw_value(),
-    L1Section::new(48234496, section_attrs::DDR).raw_value(),
-    L1Section::new(49283072, section_attrs::DDR).raw_value(),
-    L1Section::new(50331648, section_attrs::DDR).raw_value(),
-    L1Section::new(51380224, section_attrs::DDR).raw_value(),
-    L1Section::new(52428800, section_attrs::DDR).raw_value(),
-    L1Section::new(53477376, section_attrs::DDR).raw_value(),
-    L1Section::new(54525952, section_attrs::DDR).raw_value(),
-    L1Section::new(55574528, section_attrs::DDR).raw_value(),
-    L1Section::new(56623104, section_attrs::DDR).raw_value(),
-    L1Section::new(57671680, section_attrs::DDR).raw_value(),
-    L1Section::new(58720256, section_attrs::DDR).raw_value(),
-    L1Section::new(59768832, section_attrs::DDR).raw_value(),
-    L1Section::new(60817408, section_attrs::DDR).raw_value(),
-    L1Section::new(61865984, section_attrs::DDR).raw_value(),
-    L1Section::new(62914560, section_attrs::DDR).raw_value(),
-    L1Section::new(63963136, section_attrs::DDR).raw_value(),
-    L1Section::new(65011712, section_attrs::DDR).raw_value(),
-    L1Section::new(66060288, section_attrs::DDR).raw_value(),
-    L1Section::new(67108864, section_attrs::DDR).raw_value(),
-    L1Section::new(68157440, section_attrs::DDR).raw_value(),
-    L1Section::new(69206016, section_attrs::DDR).raw_value(),
-    L1Section::new(70254592, section_attrs::DDR).raw_value(),
-    L1Section::new(71303168, section_attrs::DDR).raw_value(),
-    L1Section::new(72351744, section_attrs::DDR).raw_value(),
-    L1Section::new(73400320, section_attrs::DDR).raw_value(),
-    L1Section::new(74448896, section_attrs::DDR).raw_value(),
-    L1Section::new(75497472, section_attrs::DDR).raw_value(),
-    L1Section::new(76546048, section_attrs::DDR).raw_value(),
-    L1Section::new(77594624, section_attrs::DDR).raw_value(),
-    L1Section::new(78643200, section_attrs::DDR).raw_value(),
-    L1Section::new(79691776, section_attrs::DDR).raw_value(),
-    L1Section::new(80740352, section_attrs::DDR).raw_value(),
-    L1Section::new(81788928, section_attrs::DDR).raw_value(),
-    L1Section::new(82837504, section_attrs::DDR).raw_value(),
-    L1Section::new(83886080, section_attrs::DDR).raw_value(),
-    L1Section::new(84934656, section_attrs::DDR).raw_value(),
-    L1Section::new(85983232, section_attrs::DDR).raw_value(),
-    L1Section::new(87031808, section_attrs::DDR).raw_value(),
-    L1Section::new(88080384, section_attrs::DDR).raw_value(),
-    L1Section::new(89128960, section_attrs::DDR).raw_value(),
-    L1Section::new(90177536, section_attrs::DDR).raw_value(),
-    L1Section::new(91226112, section_attrs::DDR).raw_value(),
-    L1Section::new(92274688, section_attrs::DDR).raw_value(),
-    L1Section::new(93323264, section_attrs::DDR).raw_value(),
-    L1Section::new(94371840, section_attrs::DDR).raw_value(),
-    L1Section::new(95420416, section_attrs::DDR).raw_value(),
-    L1Section::new(96468992, section_attrs::DDR).raw_value(),
-    L1Section::new(97517568, section_attrs::DDR).raw_value(),
-    L1Section::new(98566144, section_attrs::DDR).raw_value(),
-    L1Section::new(99614720, section_attrs::DDR).raw_value(),
-    L1Section::new(100663296, section_attrs::DDR).raw_value(),
-    L1Section::new(101711872, section_attrs::DDR).raw_value(),
-    L1Section::new(102760448, section_attrs::DDR).raw_value(),
-    L1Section::new(103809024, section_attrs::DDR).raw_value(),
-    L1Section::new(104857600, section_attrs::DDR).raw_value(),
-    L1Section::new(105906176, section_attrs::DDR).raw_value(),
-    L1Section::new(106954752, section_attrs::DDR).raw_value(),
-    L1Section::new(108003328, section_attrs::DDR).raw_value(),
-    L1Section::new(109051904, section_attrs::DDR).raw_value(),
-    L1Section::new(110100480, section_attrs::DDR).raw_value(),
-    L1Section::new(111149056, section_attrs::DDR).raw_value(),
-    L1Section::new(112197632, section_attrs::DDR).raw_value(),
-    L1Section::new(113246208, section_attrs::DDR).raw_value(),
-    L1Section::new(114294784, section_attrs::DDR).raw_value(),
-    L1Section::new(115343360, section_attrs::DDR).raw_value(),
-    L1Section::new(116391936, section_attrs::DDR).raw_value(),
-    L1Section::new(117440512, section_attrs::DDR).raw_value(),
-    L1Section::new(118489088, section_attrs::DDR).raw_value(),
-    L1Section::new(119537664, section_attrs::DDR).raw_value(),
-    L1Section::new(120586240, section_attrs::DDR).raw_value(),
-    L1Section::new(121634816, section_attrs::DDR).raw_value(),
-    L1Section::new(122683392, section_attrs::DDR).raw_value(),
-    L1Section::new(123731968, section_attrs::DDR).raw_value(),
-    L1Section::new(124780544, section_attrs::DDR).raw_value(),
-    L1Section::new(125829120, section_attrs::DDR).raw_value(),
-    L1Section::new(126877696, section_attrs::DDR).raw_value(),
-    L1Section::new(127926272, section_attrs::DDR).raw_value(),
-    L1Section::new(128974848, section_attrs::DDR).raw_value(),
-    L1Section::new(130023424, section_attrs::DDR).raw_value(),
-    L1Section::new(131072000, section_attrs::DDR).raw_value(),
-    L1Section::new(132120576, section_attrs::DDR).raw_value(),
-    L1Section::new(133169152, section_attrs::DDR).raw_value(),
-    L1Section::new(134217728, section_attrs::DDR).raw_value(),
-    L1Section::new(135266304, section_attrs::DDR).raw_value(),
-    L1Section::new(136314880, section_attrs::DDR).raw_value(),
-    L1Section::new(137363456, section_attrs::DDR).raw_value(),
-    L1Section::new(138412032, section_attrs::DDR).raw_value(),
-    L1Section::new(139460608, section_attrs::DDR).raw_value(),
-    L1Section::new(140509184, section_attrs::DDR).raw_value(),
-    L1Section::new(141557760, section_attrs::DDR).raw_value(),
-    L1Section::new(142606336, section_attrs::DDR).raw_value(),
-    L1Section::new(143654912, section_attrs::DDR).raw_value(),
-    L1Section::new(144703488, section_attrs::DDR).raw_value(),
-    L1Section::new(145752064, section_attrs::DDR).raw_value(),
-    L1Section::new(146800640, section_attrs::DDR).raw_value(),
-    L1Section::new(147849216, section_attrs::DDR).raw_value(),
-    L1Section::new(148897792, section_attrs::DDR).raw_value(),
-    L1Section::new(149946368, section_attrs::DDR).raw_value(),
-    L1Section::new(150994944, section_attrs::DDR).raw_value(),
-    L1Section::new(152043520, section_attrs::DDR).raw_value(),
-    L1Section::new(153092096, section_attrs::DDR).raw_value(),
-    L1Section::new(154140672, section_attrs::DDR).raw_value(),
-    L1Section::new(155189248, section_attrs::DDR).raw_value(),
-    L1Section::new(156237824, section_attrs::DDR).raw_value(),
-    L1Section::new(157286400, section_attrs::DDR).raw_value(),
-    L1Section::new(158334976, section_attrs::DDR).raw_value(),
-    L1Section::new(159383552, section_attrs::DDR).raw_value(),
-    L1Section::new(160432128, section_attrs::DDR).raw_value(),
-    L1Section::new(161480704, section_attrs::DDR).raw_value(),
-    L1Section::new(162529280, section_attrs::DDR).raw_value(),
-    L1Section::new(163577856, section_attrs::DDR).raw_value(),
-    L1Section::new(164626432, section_attrs::DDR).raw_value(),
-    L1Section::new(165675008, section_attrs::DDR).raw_value(),
-    L1Section::new(166723584, section_attrs::DDR).raw_value(),
-    L1Section::new(167772160, section_attrs::DDR).raw_value(),
-    L1Section::new(168820736, section_attrs::DDR).raw_value(),
-    L1Section::new(169869312, section_attrs::DDR).raw_value(),
-    L1Section::new(170917888, section_attrs::DDR).raw_value(),
-    L1Section::new(171966464, section_attrs::DDR).raw_value(),
-    L1Section::new(173015040, section_attrs::DDR).raw_value(),
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+    L1Section::new(0x04e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x04f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x05f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x06f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x07f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x08f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x09f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0a900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0aa00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ab00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ac00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ad00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ae00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0af00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0b900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ba00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0bb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0bc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0bd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0be00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0bf00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0c900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ca00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0cb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0cc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0cd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ce00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0cf00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0d900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0da00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0db00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0dc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0dd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0de00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0df00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0e900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ea00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0eb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ec00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ed00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ee00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ef00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0f900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0fa00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0fb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0fc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0fd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0fe00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x0ff00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x10f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x11f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x12f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x13f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x14f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x15f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x16f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x17f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x18f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x19f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1a900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1aa00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ab00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ac00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ad00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ae00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1af00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1b900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ba00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1bb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1bc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1bd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1be00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1bf00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1c900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ca00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1cb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1cc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1cd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ce00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1cf00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1d900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1da00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1db00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1dc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1dd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1de00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1df00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1e900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ea00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1eb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ec00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ed00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ee00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ef00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1f900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1fa00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1fb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1fc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1fd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1fe00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x1ff00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x20f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x21f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x22f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x23f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x24f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x25f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x26f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x27f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x28f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x29f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2a900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2aa00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ab00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ac00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ad00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ae00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2af00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2b900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ba00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2bb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2bc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2bd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2be00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2bf00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2c900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ca00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2cb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2cc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2cd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ce00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2cf00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2d900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2da00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2db00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2dc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2dd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2de00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2df00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2e900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ea00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2eb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ec00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ed00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ee00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ef00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2f900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2fa00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2fb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2fc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2fd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2fe00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x2ff00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x30f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x31f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x32f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x33f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x34f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x35f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x36f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x37f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x38f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39a00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39b00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39c00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39d00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39e00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x39f00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3a900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3aa00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ab00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ac00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ad00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ae00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3af00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3b900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ba00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3bb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3bc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3bd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3be00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3bf00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3c900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ca00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3cb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3cc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3cd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ce00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3cf00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3d900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3da00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3db00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3dc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3dd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3de00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3df00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3e900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ea00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3eb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ec00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ed00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ee00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ef00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f000000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f100000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f200000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f300000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f400000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f500000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f600000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f700000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f800000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3f900000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3fa00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3fb00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3fc00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3fd00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3fe00000, section_attrs::DDR).raw_value(),
+    L1Section::new(0x3ff00000, section_attrs::DDR).raw_value(),
     // FPGA slave 0 (0x4000_0000 - 0x8000_0000)
-    L1Section::new(1073741824, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1074790400, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1075838976, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1076887552, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1077936128, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1078984704, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1080033280, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1081081856, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1082130432, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1083179008, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1084227584, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1085276160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1086324736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1087373312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1088421888, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1089470464, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1090519040, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1091567616, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1092616192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1093664768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1094713344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1095761920, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1096810496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1097859072, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1098907648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1099956224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1101004800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1102053376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1103101952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1104150528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1105199104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1106247680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1107296256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1108344832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1109393408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1110441984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1111490560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1112539136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1113587712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1114636288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1115684864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1116733440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1117782016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1118830592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1119879168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1120927744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1121976320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1123024896, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1124073472, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1125122048, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1126170624, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1127219200, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1128267776, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1129316352, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1130364928, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1131413504, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1132462080, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1133510656, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1134559232, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1135607808, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1136656384, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1137704960, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1138753536, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1139802112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1140850688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1141899264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1142947840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1143996416, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1145044992, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1146093568, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1147142144, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1148190720, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1149239296, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1150287872, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1151336448, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1152385024, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1153433600, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1154482176, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1155530752, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1156579328, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1157627904, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1158676480, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1159725056, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1160773632, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1161822208, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1162870784, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1163919360, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1164967936, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1166016512, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1167065088, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1168113664, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1169162240, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1170210816, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1171259392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1172307968, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1173356544, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1174405120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1175453696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1176502272, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1177550848, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1178599424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1179648000, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1180696576, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1181745152, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1182793728, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1183842304, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1184890880, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1185939456, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1186988032, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1188036608, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1189085184, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1190133760, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1191182336, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1192230912, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1193279488, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1194328064, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1195376640, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1196425216, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1197473792, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1198522368, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1199570944, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1200619520, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1201668096, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1202716672, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1203765248, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1204813824, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1205862400, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1206910976, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1207959552, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1209008128, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1210056704, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1211105280, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1212153856, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1213202432, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1214251008, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1215299584, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1216348160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1217396736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1218445312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1219493888, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1220542464, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1221591040, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1222639616, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1223688192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1224736768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1225785344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1226833920, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1227882496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1228931072, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1229979648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1231028224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1232076800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1233125376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1234173952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1235222528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1236271104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1237319680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1238368256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1239416832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1240465408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1241513984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1242562560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1243611136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1244659712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1245708288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1246756864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1247805440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1248854016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1249902592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1250951168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1251999744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1253048320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1254096896, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1255145472, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1256194048, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1257242624, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1258291200, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1259339776, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1260388352, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1261436928, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1262485504, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1263534080, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1264582656, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1265631232, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1266679808, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1267728384, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1268776960, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1269825536, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1270874112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1271922688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1272971264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1274019840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1275068416, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1276116992, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1277165568, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1278214144, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1279262720, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1280311296, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1281359872, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1282408448, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1283457024, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1284505600, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1285554176, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1286602752, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1287651328, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1288699904, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1289748480, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1290797056, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1291845632, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1292894208, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1293942784, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1294991360, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1296039936, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1297088512, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1298137088, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1299185664, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1300234240, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1301282816, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1302331392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1303379968, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1304428544, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1305477120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1306525696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1307574272, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1308622848, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1309671424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1310720000, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1311768576, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1312817152, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1313865728, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1314914304, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1315962880, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1317011456, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1318060032, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1319108608, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1320157184, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1321205760, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1322254336, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1323302912, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1324351488, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1325400064, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1326448640, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1327497216, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1328545792, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1329594368, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1330642944, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1331691520, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1332740096, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1333788672, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1334837248, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1335885824, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1336934400, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1337982976, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1339031552, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1340080128, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1341128704, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1342177280, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1343225856, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1344274432, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1345323008, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1346371584, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1347420160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1348468736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1349517312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1350565888, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1351614464, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1352663040, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1353711616, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1354760192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1355808768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1356857344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1357905920, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1358954496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1360003072, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1361051648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1362100224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1363148800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1364197376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1365245952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1366294528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1367343104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1368391680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1369440256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1370488832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1371537408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1372585984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1373634560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1374683136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1375731712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1376780288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1377828864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1378877440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1379926016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1380974592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1382023168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1383071744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1384120320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1385168896, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1386217472, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1387266048, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1388314624, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1389363200, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1390411776, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1391460352, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1392508928, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1393557504, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1394606080, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1395654656, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1396703232, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1397751808, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1398800384, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1399848960, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1400897536, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1401946112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1402994688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1404043264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1405091840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1406140416, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1407188992, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1408237568, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1409286144, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1410334720, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1411383296, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1412431872, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1413480448, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1414529024, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1415577600, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1416626176, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1417674752, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1418723328, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1419771904, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1420820480, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1421869056, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1422917632, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1423966208, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1425014784, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1426063360, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1427111936, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1428160512, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1429209088, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1430257664, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1431306240, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1432354816, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1433403392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1434451968, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1435500544, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1436549120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1437597696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1438646272, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1439694848, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1440743424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1441792000, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1442840576, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1443889152, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1444937728, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1445986304, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1447034880, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1448083456, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1449132032, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1450180608, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1451229184, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1452277760, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1453326336, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1455423488, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1456472064, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1457520640, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1458569216, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1459617792, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1460666368, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1461714944, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1462763520, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1463812096, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1464860672, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1465909248, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1468006400, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1471152128, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1472200704, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1473249280, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1474297856, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1476395008, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1477443584, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1478492160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1479540736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1480589312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1481637888, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1483735040, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1485832192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1486880768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1487929344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1488977920, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1490026496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1491075072, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1492123648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1493172224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1494220800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1495269376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1496317952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1497366528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1498415104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1499463680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1500512256, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1502609408, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1530920960, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1533018112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1534066688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1535115264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1536163840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1537212416, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1547698176, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1551892480, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1559232512, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1561329664, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1564475392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1565523968, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1567621120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1568669696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1569718272, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1571815424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1572864000, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1577058304, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1578106880, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1579155456, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1580204032, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1581252608, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1582301184, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1583349760, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1584398336, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1585446912, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1586495488, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1587544064, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1588592640, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1589641216, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1590689792, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1591738368, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1592786944, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1593835520, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1594884096, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1595932672, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1596981248, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1598029824, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1599078400, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1600126976, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1601175552, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1602224128, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1603272704, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1604321280, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1605369856, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1606418432, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1607467008, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1608515584, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1609564160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1610612736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1611661312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1612709888, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1613758464, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1614807040, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1615855616, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1616904192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1617952768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1619001344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1620049920, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1621098496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1622147072, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1623195648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1624244224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1625292800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1626341376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1627389952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1628438528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1629487104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1630535680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1631584256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1632632832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1633681408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1634729984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1635778560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1636827136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1637875712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1638924288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1639972864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1641021440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1642070016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1643118592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1644167168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1645215744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1646264320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1647312896, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1648361472, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1649410048, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1650458624, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1651507200, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1652555776, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1653604352, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1654652928, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1655701504, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1656750080, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1657798656, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1658847232, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1659895808, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1660944384, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1661992960, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1663041536, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1664090112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1665138688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1666187264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1667235840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1668284416, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1669332992, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1670381568, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1671430144, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1672478720, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1673527296, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1674575872, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1675624448, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1676673024, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1677721600, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1678770176, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1679818752, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1680867328, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1681915904, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1682964480, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1684013056, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1685061632, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1686110208, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1687158784, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1688207360, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1689255936, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1690304512, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1691353088, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1692401664, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1693450240, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1694498816, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1695547392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1696595968, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1698693120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1699741696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1700790272, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1701838848, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1702887424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1703936000, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1706033152, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1707081728, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1708130304, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1715470336, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1718616064, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1719664640, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1720713216, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(1721761792, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(1724907520, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2124414976, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2125463552, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2126512128, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2127560704, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2128609280, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2129657856, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2130706432, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2131755008, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2132803584, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2133852160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2134900736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2135949312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2136997888, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2138046464, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2139095040, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2140143616, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2141192192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2142240768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2143289344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2144337920, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2145386496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2146435072, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x40f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x41f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x42f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x43f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x44f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x45f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x46f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x47f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x48f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x49f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4a900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4aa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ab00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ac00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ad00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ae00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4af00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4b900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ba00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4bb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4bc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4bd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4be00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4bf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4c900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ca00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4cb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4cc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4cd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ce00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4cf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4d900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4da00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4db00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4dc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4dd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4de00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4df00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4e900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ea00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4eb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ec00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ed00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ee00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ef00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4f900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4fa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4fb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4fc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4fd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4fe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x4ff00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x50f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x51f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x52f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x53f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x54f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x55f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x56f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x57f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x58f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x59f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5a900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5aa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ab00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ac00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ad00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ae00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5af00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5b900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ba00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5bb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5bc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5bd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5be00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5bf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5c900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ca00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5cb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5cc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5cd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ce00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5cf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5d900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5da00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5db00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5dc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5dd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5de00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5df00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5e900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ea00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5eb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ec00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ed00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ee00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ef00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5f900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5fa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5fb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5fc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5fd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5fe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x5ff00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x60f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x61f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x62f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x63f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x64f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x65f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x66f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x67f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x68f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x69f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6a900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6aa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ab00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ac00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ad00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ae00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6af00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6b900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ba00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6bb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6bc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6bd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6be00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6bf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6c900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ca00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6cb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6cc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6cd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ce00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6cf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6d900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6da00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6db00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6dc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6dd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6de00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6df00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6e900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ea00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6eb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ec00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ed00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ee00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ef00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6f900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6fa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6fb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6fc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6fd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6fe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x6ff00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x70f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x71f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x72f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x73f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x74f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x75f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x76f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x77f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x78f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x79f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7a900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7aa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ab00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ac00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ad00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ae00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7af00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7b900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ba00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7bb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7bc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7bd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7be00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7bf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7c900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ca00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7cb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7cc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7cd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ce00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7cf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7d900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7da00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7db00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7dc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7dd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7de00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7df00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7e900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ea00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7eb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ec00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ed00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ee00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ef00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7f900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7fa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7fb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7fc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7fd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7fe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x7ff00000, section_attrs::FPGA_SLAVES).raw_value(),
     // FPGA slave 1 (0x8000_0000 - 0xC000_0000)
-    L1Section::new(2147483648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2148532224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2149580800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2150629376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2151677952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2152726528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2153775104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2154823680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2155872256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2156920832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2157969408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2159017984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2160066560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2161115136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2162163712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2163212288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2164260864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2165309440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2166358016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2167406592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2168455168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2169503744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2170552320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2171600896, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2172649472, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2173698048, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2174746624, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2175795200, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2176843776, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2177892352, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2178940928, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2179989504, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2181038080, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2182086656, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2183135232, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2184183808, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2185232384, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2186280960, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2187329536, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2188378112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2189426688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2190475264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2191523840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2192572416, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2193620992, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2194669568, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2195718144, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2196766720, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2197815296, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2198863872, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2199912448, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2200961024, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2202009600, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2203058176, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2204106752, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2205155328, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2206203904, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2207252480, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2208301056, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2209349632, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2210398208, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2211446784, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2212495360, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2213543936, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2214592512, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2215641088, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2216689664, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2217738240, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2218786816, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2219835392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2220883968, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2221932544, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2222981120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2224029696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2225078272, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2226126848, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2227175424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2228224000, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2229272576, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2230321152, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2231369728, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2232418304, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2233466880, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2234515456, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2235564032, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2236612608, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2237661184, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2238709760, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2239758336, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2240806912, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2241855488, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2242904064, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2243952640, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2245001216, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2246049792, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2247098368, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2248146944, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2249195520, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2250244096, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2251292672, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2252341248, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2253389824, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2254438400, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2255486976, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2256535552, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2257584128, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2258632704, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2259681280, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2260729856, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2261778432, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2262827008, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2263875584, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2264924160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2265972736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2267021312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2268069888, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2269118464, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2270167040, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2271215616, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2272264192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2273312768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2274361344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2275409920, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2276458496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2277507072, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2278555648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2279604224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2280652800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2281701376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2282749952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2283798528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2284847104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2285895680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2286944256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2287992832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2289041408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2290089984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2291138560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2292187136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2293235712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2294284288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2295332864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2296381440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2297430016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2298478592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2299527168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2300575744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2301624320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2302672896, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2303721472, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2304770048, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2305818624, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2306867200, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2307915776, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2308964352, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2310012928, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2311061504, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2312110080, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2313158656, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2314207232, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2315255808, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2316304384, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2317352960, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2318401536, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2319450112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2320498688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2321547264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2322595840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2323644416, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2324692992, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2325741568, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2326790144, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2327838720, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2328887296, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2329935872, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2330984448, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2332033024, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2333081600, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2334130176, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2335178752, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2336227328, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2337275904, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2338324480, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2339373056, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2340421632, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2341470208, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2342518784, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2343567360, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2344615936, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2345664512, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2346713088, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2347761664, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2348810240, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2349858816, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2350907392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2351955968, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2353004544, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2354053120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2355101696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2356150272, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2357198848, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2358247424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2359296000, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2360344576, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2361393152, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2362441728, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2363490304, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2364538880, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2365587456, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2366636032, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2367684608, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2368733184, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2369781760, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2370830336, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2371878912, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2372927488, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2373976064, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2375024640, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2376073216, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2377121792, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2378170368, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2379218944, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2380267520, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2381316096, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2382364672, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2383413248, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2384461824, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2385510400, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2386558976, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2387607552, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2388656128, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2389704704, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2390753280, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2391801856, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2392850432, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2393899008, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2394947584, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2395996160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2397044736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2398093312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2399141888, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2400190464, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2401239040, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2402287616, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2403336192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2404384768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2405433344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2406481920, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2407530496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2408579072, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2409627648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2410676224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2411724800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2412773376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2413821952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2414870528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2415919104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2416967680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2418016256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2419064832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2420113408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2421161984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2422210560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2423259136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2424307712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2425356288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2426404864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2427453440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2428502016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2429550592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2430599168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2431647744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2432696320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2433744896, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2434793472, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2435842048, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2436890624, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2437939200, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2438987776, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2440036352, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2441084928, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2442133504, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2443182080, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2444230656, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2445279232, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2446327808, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2447376384, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2448424960, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2449473536, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2450522112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2451570688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2452619264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2453667840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2454716416, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2455764992, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2456813568, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2457862144, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2458910720, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2459959296, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2461007872, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2462056448, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2463105024, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2464153600, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2465202176, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2466250752, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2467299328, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2468347904, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2469396480, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2470445056, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2471493632, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2472542208, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2473590784, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2474639360, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2475687936, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2476736512, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2477785088, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2478833664, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2479882240, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2480930816, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2481979392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2483027968, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2484076544, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2485125120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2486173696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2487222272, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2488270848, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2489319424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2490368000, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2491416576, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2492465152, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2493513728, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2494562304, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2495610880, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2496659456, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2497708032, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2498756608, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2499805184, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2500853760, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2501902336, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2502950912, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2503999488, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2506096640, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2508193792, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2510290944, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2511339520, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2514485248, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2515533824, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2516582400, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2523922432, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2524971008, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2527068160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2528116736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2529165312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2530213888, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2532311040, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2659188736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2660237312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2661285888, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2662334464, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2663383040, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2664431616, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2665480192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2666528768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2667577344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2668625920, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2669674496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2670723072, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2671771648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2672820224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2673868800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2674917376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2675965952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2677014528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2678063104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2679111680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2680160256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2681208832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2682257408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2683305984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2684354560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2685403136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2686451712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2687500288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2688548864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2689597440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2690646016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2691694592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2692743168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2693791744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2694840320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2695888896, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2696937472, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2697986048, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2699034624, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2700083200, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2701131776, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2702180352, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2703228928, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2704277504, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2705326080, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2706374656, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2707423232, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2708471808, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2709520384, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2710568960, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2711617536, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2712666112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2713714688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2714763264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2715811840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2716860416, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2717908992, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2718957568, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2720006144, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2721054720, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2722103296, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2723151872, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2724200448, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2725249024, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2726297600, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2727346176, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2728394752, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2729443328, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2730491904, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2731540480, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2732589056, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2733637632, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2734686208, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2735734784, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2736783360, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2737831936, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2738880512, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2739929088, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2740977664, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2742026240, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2743074816, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2744123392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2745171968, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2746220544, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2747269120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2748317696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2749366272, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2750414848, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2751463424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2752512000, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2753560576, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2754609152, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2755657728, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2756706304, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2757754880, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2758803456, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2759852032, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2760900608, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2761949184, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2762997760, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2764046336, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2765094912, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2766143488, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2767192064, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2768240640, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2769289216, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2770337792, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2771386368, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2772434944, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2773483520, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2774532096, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2775580672, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2776629248, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2777677824, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2778726400, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2779774976, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2780823552, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2781872128, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2782920704, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2783969280, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2785017856, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2786066432, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2787115008, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2788163584, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2789212160, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2790260736, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2791309312, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2792357888, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2795503616, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2796552192, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2797600768, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2798649344, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2799697920, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2804940800, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(2931818496, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2932867072, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2933915648, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2934964224, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2936012800, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2937061376, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2938109952, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2939158528, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2940207104, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2941255680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2942304256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2943352832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2944401408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2945449984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2946498560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2947547136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2948595712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2949644288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2950692864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2951741440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2952790016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2953838592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2954887168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2955935744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2956984320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2958032896, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2959081472, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2960130048, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2961178624, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2962227200, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2963275776, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2964324352, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2965372928, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2966421504, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2967470080, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2968518656, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2969567232, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2970615808, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2971664384, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2972712960, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2973761536, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2974810112, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2975858688, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2976907264, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2977955840, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2979004416, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2980052992, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2981101568, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2982150144, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2983198720, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2984247296, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2985295872, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2986344448, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2987393024, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2988441600, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2989490176, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2990538752, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2991587328, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2992635904, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2993684480, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2994733056, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2995781632, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2996830208, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2997878784, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2998927360, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(2999975936, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3001024512, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3002073088, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3003121664, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3004170240, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3005218816, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3006267392, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3007315968, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3008364544, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3009413120, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3010461696, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3011510272, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3012558848, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3013607424, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3014656000, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3015704576, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3016753152, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3017801728, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3018850304, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3019898880, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3020947456, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3021996032, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3023044608, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3024093184, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3025141760, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3026190336, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3027238912, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3028287488, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3029336064, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3030384640, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(3032481792, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3033530368, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3034578944, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3035627520, section_attrs::FPGA_SLAVES).raw_value(),
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-    L1Section::new(3203399680, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3204448256, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3205496832, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3206545408, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3207593984, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3208642560, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3209691136, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3210739712, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3211788288, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3212836864, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3213885440, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3214934016, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3215982592, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3217031168, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3218079744, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3219128320, section_attrs::FPGA_SLAVES).raw_value(),
-    L1Section::new(3220176896, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x80f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x81f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x82f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x83f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x84f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x85f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x86f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x87f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x88f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x89f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8a900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8aa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ab00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ac00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ad00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ae00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8af00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8b900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ba00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8bb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8bc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8bd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8be00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8bf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8c900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ca00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8cb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8cc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8cd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ce00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8cf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8d900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8da00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8db00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8dc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8dd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8de00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8df00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8e900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ea00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8eb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ec00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ed00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ee00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ef00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8f900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8fa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8fb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8fc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8fd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8fe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x8ff00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x90f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x91f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x92f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x93f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x94f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x95f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x96f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x97f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x98f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x99f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9a900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9aa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ab00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ac00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ad00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ae00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9af00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9b900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ba00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9bb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9bc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9bd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9be00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9bf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9c900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ca00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9cb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9cc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9cd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ce00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9cf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9d900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9da00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9db00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9dc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9dd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9de00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9df00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9e900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ea00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9eb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ec00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ed00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ee00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ef00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9f900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9fa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9fb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9fc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9fd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9fe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0x9ff00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa0f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa1f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa2f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa3f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa4f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa5f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa6f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa7f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa8f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xa9f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaa900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaaa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaab00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaac00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaad00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaae00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaaf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xab900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaba00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xabb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xabc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xabd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xabe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xabf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xac900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaca00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xacb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xacc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xacd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xace00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xacf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xad900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xada00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xadb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xadc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xadd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xade00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xadf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xae900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaea00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaeb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaec00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaed00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaee00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaef00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaf900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xafa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xafb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xafc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xafd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xafe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xaff00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb0f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb1f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb2f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb3f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb4f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb5f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb6f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb7f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb8f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9a00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9b00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9c00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9d00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9e00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xb9f00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xba900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbaa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbab00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbac00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbad00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbae00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbaf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbb900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbba00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbbb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbbc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbbd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbbe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbbf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbc900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbca00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbcb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbcc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbcd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbce00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbcf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbd900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbda00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbdb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbdc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbdd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbde00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbdf00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbe900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbea00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbeb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbec00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbed00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbee00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbef00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf000000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf100000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf200000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf300000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf400000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf500000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf600000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf700000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf800000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbf900000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbfa00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbfb00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbfc00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbfd00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbfe00000, section_attrs::FPGA_SLAVES).raw_value(),
+    L1Section::new(0xbff00000, section_attrs::FPGA_SLAVES).raw_value(),
     // Unassigned/Reserved (0xC000_0000 - 0xE000_0000)
-    L1Section::new(3221225472, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3222274048, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3223322624, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3224371200, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3225419776, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3226468352, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3227516928, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3228565504, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3229614080, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3230662656, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3231711232, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3232759808, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3233808384, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3234856960, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3235905536, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3236954112, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3238002688, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3239051264, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3240099840, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3241148416, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3242196992, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3243245568, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3244294144, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3245342720, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3246391296, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3247439872, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3248488448, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3249537024, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3250585600, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3251634176, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3252682752, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3253731328, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3254779904, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3255828480, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3256877056, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3257925632, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3258974208, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3260022784, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3261071360, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3262119936, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3263168512, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3264217088, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3265265664, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3266314240, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3267362816, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3268411392, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3269459968, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3270508544, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3271557120, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3272605696, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3273654272, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3274702848, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3275751424, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3276800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3277848576, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3278897152, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3279945728, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3280994304, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3282042880, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3283091456, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3284140032, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3285188608, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3286237184, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3287285760, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3288334336, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3289382912, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3290431488, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3291480064, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3292528640, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3293577216, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3294625792, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3295674368, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3296722944, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3297771520, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3298820096, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3299868672, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3300917248, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3301965824, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3303014400, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3304062976, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3305111552, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3306160128, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3307208704, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3308257280, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3309305856, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3310354432, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3311403008, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3312451584, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3313500160, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3314548736, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3315597312, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3316645888, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3317694464, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3318743040, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3319791616, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3320840192, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3321888768, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3322937344, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3323985920, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3325034496, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3326083072, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3327131648, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3328180224, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3329228800, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3330277376, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3331325952, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3332374528, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3333423104, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3334471680, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3335520256, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3336568832, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3337617408, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3338665984, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3339714560, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3340763136, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3341811712, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3342860288, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3343908864, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3344957440, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3346006016, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3347054592, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3348103168, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3349151744, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3350200320, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3351248896, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3352297472, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3353346048, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3354394624, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3355443200, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3356491776, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3357540352, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3358588928, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3359637504, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3360686080, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3361734656, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3362783232, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3363831808, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3364880384, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3365928960, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3366977536, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3368026112, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3369074688, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3370123264, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3371171840, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3372220416, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3373268992, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3374317568, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3375366144, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3376414720, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3377463296, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3378511872, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3379560448, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3380609024, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3381657600, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3382706176, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3383754752, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3384803328, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3385851904, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3386900480, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3387949056, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3388997632, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3390046208, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3391094784, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3392143360, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3393191936, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3394240512, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3395289088, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3396337664, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3397386240, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3398434816, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3399483392, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3400531968, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3401580544, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3402629120, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3403677696, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3404726272, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3405774848, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3406823424, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3407872000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3408920576, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3409969152, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3411017728, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3412066304, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3413114880, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3414163456, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3415212032, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3416260608, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3417309184, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3418357760, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3419406336, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3420454912, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3421503488, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3422552064, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3423600640, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3424649216, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3425697792, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3426746368, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3427794944, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3428843520, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3429892096, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3430940672, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3431989248, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3433037824, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3434086400, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3435134976, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3436183552, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3437232128, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3438280704, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3439329280, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3440377856, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3441426432, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3442475008, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3443523584, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3444572160, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3445620736, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3446669312, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3447717888, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3448766464, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3449815040, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3450863616, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3451912192, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3452960768, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3454009344, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3455057920, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3456106496, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3457155072, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3458203648, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3459252224, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3460300800, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3461349376, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3462397952, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3463446528, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3464495104, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3465543680, section_attrs::UNASSIGNED_RESERVED).raw_value(),
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-    L1Section::new(3727687680, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3728736256, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3729784832, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3730833408, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3731881984, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3732930560, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3733979136, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3735027712, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3736076288, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3737124864, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3738173440, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3739222016, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3740270592, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3741319168, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3742367744, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3743416320, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3744464896, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3745513472, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3746562048, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3747610624, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3748659200, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3749707776, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3750756352, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3751804928, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3752853504, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3753902080, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3754950656, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3755999232, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3757047808, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc0f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc1f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc2f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc3f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc4f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc5f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc6f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc7f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc8f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xc9f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xca900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcaa00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcab00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcac00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcad00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcae00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcaf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcb900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcba00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcbb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcbc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcbd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcbe00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcbf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcc900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcca00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xccb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xccc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xccd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcce00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xccf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcd900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcda00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcdb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcdc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcdd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcde00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcdf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xce900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcea00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xceb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcec00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xced00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcee00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcef00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcf900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcfa00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcfb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcfc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcfd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcfe00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xcff00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd0f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd1f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd2f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd3f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd4f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd5f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd6f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd7f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd8f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xd9f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xda900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdaa00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdab00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdac00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdad00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdae00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdaf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdb900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdba00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdbb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdbc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdbd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdbe00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdbf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdc900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdca00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdcb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdcc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdcd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdce00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdcf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdd900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdda00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xddb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xddc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xddd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdde00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xddf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xde900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdea00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdeb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdec00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xded00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdee00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdef00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdf900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdfa00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdfb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdfc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdfd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdfe00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xdff00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
     // Segments IO peripherals (0xE000_0000 - 0xE030_0000)
-    L1Section::new(3758096384, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3759144960, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3760193536, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe0000000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe0100000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe0200000, section_attrs::SHAREABLE_DEVICE).raw_value(),
     // Unassigned/Reserved (0xE030_0000 - 0xE100_0000)
-    L1Section::new(3761242112, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3762290688, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3763339264, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3764387840, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3765436416, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3766484992, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3767533568, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3768582144, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3769630720, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3770679296, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3771727872, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3772776448, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3773825024, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe0f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
     // NAND (0xE100_0000 - 0xE200_0000)
-    L1Section::new(3774873600, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3775922176, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3776970752, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3778019328, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3779067904, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3780116480, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3781165056, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3782213632, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3783262208, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3784310784, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3785359360, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3786407936, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3787456512, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3788505088, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3789553664, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3790602240, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1000000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1100000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1200000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1300000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1400000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1500000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1600000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1700000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1800000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1900000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1a00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1b00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1c00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1d00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1e00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe1f00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
     // NOR (0xE200_0000 - 0xE400_0000)
-    L1Section::new(3791650816, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3792699392, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3793747968, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3794796544, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3795845120, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3796893696, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3797942272, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3798990848, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3800039424, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3801088000, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3802136576, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3803185152, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3804233728, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3805282304, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3806330880, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3807379456, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3808428032, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3809476608, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3810525184, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3811573760, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3812622336, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3813670912, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3814719488, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3815768064, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3816816640, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3817865216, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3818913792, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3819962368, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3821010944, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3822059520, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3823108096, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(3824156672, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2000000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2100000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2200000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2300000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2400000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2500000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2600000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2700000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2800000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2900000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2a00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2b00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2c00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2d00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2e00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe2f00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3000000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3100000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3200000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3300000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3400000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3500000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3600000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3700000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3800000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3900000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3a00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3b00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3c00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3d00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3e00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xe3f00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
     // SRAM (0xE400_0000 - 0xE600_0000)
-    L1Section::new(3825205248, section_attrs::SRAM).raw_value(),
-    L1Section::new(3826253824, section_attrs::SRAM).raw_value(),
-    L1Section::new(3827302400, section_attrs::SRAM).raw_value(),
-    L1Section::new(3828350976, section_attrs::SRAM).raw_value(),
-    L1Section::new(3829399552, section_attrs::SRAM).raw_value(),
-    L1Section::new(3830448128, section_attrs::SRAM).raw_value(),
-    L1Section::new(3831496704, section_attrs::SRAM).raw_value(),
-    L1Section::new(3832545280, section_attrs::SRAM).raw_value(),
-    L1Section::new(3833593856, section_attrs::SRAM).raw_value(),
-    L1Section::new(3834642432, section_attrs::SRAM).raw_value(),
-    L1Section::new(3835691008, section_attrs::SRAM).raw_value(),
-    L1Section::new(3836739584, section_attrs::SRAM).raw_value(),
-    L1Section::new(3837788160, section_attrs::SRAM).raw_value(),
-    L1Section::new(3838836736, section_attrs::SRAM).raw_value(),
-    L1Section::new(3839885312, section_attrs::SRAM).raw_value(),
-    L1Section::new(3840933888, section_attrs::SRAM).raw_value(),
-    L1Section::new(3841982464, section_attrs::SRAM).raw_value(),
-    L1Section::new(3843031040, section_attrs::SRAM).raw_value(),
-    L1Section::new(3844079616, section_attrs::SRAM).raw_value(),
-    L1Section::new(3845128192, section_attrs::SRAM).raw_value(),
-    L1Section::new(3846176768, section_attrs::SRAM).raw_value(),
-    L1Section::new(3847225344, section_attrs::SRAM).raw_value(),
-    L1Section::new(3848273920, section_attrs::SRAM).raw_value(),
-    L1Section::new(3849322496, section_attrs::SRAM).raw_value(),
-    L1Section::new(3850371072, section_attrs::SRAM).raw_value(),
-    L1Section::new(3851419648, section_attrs::SRAM).raw_value(),
-    L1Section::new(3852468224, section_attrs::SRAM).raw_value(),
-    L1Section::new(3853516800, section_attrs::SRAM).raw_value(),
-    L1Section::new(3854565376, section_attrs::SRAM).raw_value(),
-    L1Section::new(3855613952, section_attrs::SRAM).raw_value(),
-    L1Section::new(3856662528, section_attrs::SRAM).raw_value(),
-    L1Section::new(3857711104, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4000000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4100000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4200000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4300000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4400000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4500000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4600000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4700000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4800000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4900000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4a00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4b00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4c00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4d00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4e00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe4f00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5000000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5100000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5200000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5300000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5400000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5500000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5600000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5700000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5800000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5900000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5a00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5b00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5c00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5d00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5e00000, section_attrs::SRAM).raw_value(),
+    L1Section::new(0xe5f00000, section_attrs::SRAM).raw_value(),
     // Unassigned/Reserved (0xE600_0000 - 0xF800_0000)
-    L1Section::new(3858759680, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3859808256, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3860856832, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3861905408, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3862953984, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3864002560, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3865051136, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3866099712, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3867148288, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3868196864, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3869245440, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3870294016, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3871342592, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3872391168, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3873439744, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3874488320, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3875536896, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3876585472, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3877634048, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3878682624, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3879731200, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3880779776, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3881828352, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3882876928, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3883925504, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3884974080, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3886022656, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3887071232, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3888119808, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3889168384, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3890216960, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3891265536, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3892314112, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3893362688, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3894411264, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3895459840, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(3896508416, section_attrs::UNASSIGNED_RESERVED).raw_value(),
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-    L1Section::new(4158652416, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4159700992, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe6f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe7f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe8f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xe9f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xea900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeaa00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeab00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeac00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xead00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeae00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeaf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeb900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeba00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xebb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xebc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xebd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xebe00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xebf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xec900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeca00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xecb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xecc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xecd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xece00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xecf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xed900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeda00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xedb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xedc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xedd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xede00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xedf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xee900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeea00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeeb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeec00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeed00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeee00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeef00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xef900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xefa00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xefb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xefc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xefd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xefe00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xeff00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf0f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf1f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf2f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf3f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf4f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf5f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf6f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf7f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
     // AMBA APB peripherals (0xF800_0000 - 0xF900_0000)
-    L1Section::new(4160749568, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4161798144, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4162846720, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4163895296, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4164943872, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4165992448, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4167041024, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4168089600, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4169138176, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4170186752, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4171235328, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4172283904, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4173332480, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4174381056, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4175429632, section_attrs::SHAREABLE_DEVICE).raw_value(),
-    L1Section::new(4176478208, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8000000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8100000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8200000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8300000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8400000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8500000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8600000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8700000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8800000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8900000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8a00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8b00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8c00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8d00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8e00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
+    L1Section::new(0xf8f00000, section_attrs::SHAREABLE_DEVICE).raw_value(),
     // Unassigned/Reserved (0xF900_0000 - 0xFC00_0000)
-    L1Section::new(4177526784, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4178575360, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4179623936, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4180672512, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4181721088, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4182769664, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4183818240, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4184866816, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4185915392, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4186963968, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4188012544, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4189061120, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4190109696, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4191158272, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4192206848, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4193255424, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4194304000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4195352576, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4196401152, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4197449728, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4198498304, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4199546880, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4200595456, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4201644032, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4202692608, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4203741184, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4204789760, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4205838336, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4206886912, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4207935488, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4208984064, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4210032640, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4211081216, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4212129792, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4213178368, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4214226944, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4215275520, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4216324096, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4217372672, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4218421248, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4219469824, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4220518400, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4221566976, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4222615552, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4223664128, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4224712704, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4225761280, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4226809856, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9a00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9b00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9c00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9d00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9e00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xf9f00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfa900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfaa00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfab00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfac00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfad00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfae00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfaf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfb900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfba00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfbb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfbc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfbd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfbe00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfbf00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
     // QSPI XIP (0xFC00_0000 - 0xFE00_0000)
-    L1Section::new(4227858432, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4228907008, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4229955584, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4231004160, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4232052736, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4233101312, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4234149888, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4235198464, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4236247040, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4237295616, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4238344192, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4239392768, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4240441344, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4241489920, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4242538496, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4243587072, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4244635648, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4245684224, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4246732800, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4247781376, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4248829952, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4249878528, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4250927104, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4251975680, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4253024256, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4254072832, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4255121408, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4256169984, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4257218560, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4258267136, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4259315712, section_attrs::QSPI_XIP).raw_value(),
-    L1Section::new(4260364288, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc000000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc100000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc200000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc300000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc400000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc500000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc600000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc700000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc800000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfc900000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfca00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfcb00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfcc00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfcd00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfce00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfcf00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd000000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd100000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd200000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd300000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd400000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd500000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd600000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd700000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd800000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfd900000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfda00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfdb00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfdc00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfdd00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfde00000, section_attrs::QSPI_XIP).raw_value(),
+    L1Section::new(0xfdf00000, section_attrs::QSPI_XIP).raw_value(),
     // Unassiged/Reserved (0xFE00_0000 - 0xFFF0_0000)
-    L1Section::new(4261412864, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4262461440, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4263510016, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4264558592, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4265607168, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4266655744, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4267704320, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4268752896, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4269801472, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4270850048, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4271898624, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4272947200, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4273995776, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4275044352, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4276092928, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4277141504, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4278190080, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4279238656, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4280287232, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4281335808, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4282384384, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4283432960, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4284481536, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4285530112, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4286578688, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4287627264, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4288675840, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4289724416, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4290772992, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4291821568, section_attrs::UNASSIGNED_RESERVED).raw_value(),
-    L1Section::new(4292870144, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfe900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfea00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfeb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfec00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfed00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfee00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xfef00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff000000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff100000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff200000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff300000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff400000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff500000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff600000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff700000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff800000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xff900000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xffa00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xffb00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xffc00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xffd00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
+    L1Section::new(0xffe00000, section_attrs::UNASSIGNED_RESERVED).raw_value(),
     // OCM High (0xFFF0_0000 - 0xFFFF_FFFF)
-    L1Section::new(4293918720, section_attrs::OCM_MAPPED_HIGH).raw_value(),
+    L1Section::new(0xfff00000, section_attrs::OCM_MAPPED_HIGH).raw_value(),
 ]);
diff --git a/zynq7000/src/eth.rs b/zynq7000/src/eth.rs
new file mode 100644
index 0000000..b1c17e3
--- /dev/null
+++ b/zynq7000/src/eth.rs
@@ -0,0 +1,599 @@
+use arbitrary_int::{u2, u5};
+
+pub const GEM_0_BASE_ADDR: usize = 0xE000_B000;
+pub const GEM_1_BASE_ADDR: usize = 0xE000_C000;
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct NetworkControl {
+    #[bit(18, w)]
+    flush_next_rx_dpram_pkt: bool,
+    #[bit(17, w)]
+    tx_pfc_pri_pause_frame: bool,
+    #[bit(16, w)]
+    enable_pfc_pri_pause_rx: bool,
+    #[bit(12, w)]
+    zero_pause_tx: bool,
+    #[bit(11, w)]
+    pause_tx: bool,
+    #[bit(10, w)]
+    stop_tx: bool,
+    #[bit(9, w)]
+    start_tx: bool,
+    #[bit(8, rw)]
+    back_pressure: bool,
+    #[bit(7, rw)]
+    statistics_write_enable: bool,
+    #[bit(6, w)]
+    increment_statistics: bool,
+    #[bit(5, w)]
+    clear_statistics: bool,
+    #[bit(4, rw)]
+    management_port_enable: bool,
+    #[bit(3, rw)]
+    tx_enable: bool,
+    #[bit(2, rw)]
+    rx_enable: bool,
+    #[bit(1, rw)]
+    loopback_local: bool,
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug, PartialEq, Eq)]
+pub enum SpeedMode {
+    Low10Mbps = 0,
+    High100Mbps = 1,
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug, PartialEq, Eq)]
+pub enum PcsSelect {
+    GmiiMii = 0,
+    Tbi = 1,
+}
+
+#[bitbybit::bitenum(u3, exhaustive = true)]
+#[derive(Debug, PartialEq, Eq)]
+pub enum MdcClkDiv {
+    Div8 = 0,
+    Div16 = 1,
+    Div32 = 2,
+    Div48 = 3,
+    Div64 = 4,
+    Div96 = 5,
+    Div128 = 6,
+    Div224 = 7,
+}
+
+impl MdcClkDiv {
+    pub fn divisor(&self) -> usize {
+        match self {
+            MdcClkDiv::Div8 => 8,
+            MdcClkDiv::Div16 => 16,
+            MdcClkDiv::Div32 => 32,
+            MdcClkDiv::Div48 => 48,
+            MdcClkDiv::Div64 => 64,
+            MdcClkDiv::Div96 => 96,
+            MdcClkDiv::Div128 => 128,
+            MdcClkDiv::Div224 => 224,
+        }
+    }
+}
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug)]
+pub struct NetworkConfig {
+    #[bit(30, rw)]
+    ignore_ipg_rx_error: bool,
+    #[bit(29, rw)]
+    allow_bad_preamble: bool,
+    #[bit(28, rw)]
+    ipg_stretch_enable: bool,
+    #[bit(27, rw)]
+    sgmii_enable: bool,
+    #[bit(26, rw)]
+    ignore_rx_fcs: bool,
+    #[bit(25, rw)]
+    half_duplex_rx_enable: bool,
+    #[bit(24, rw)]
+    rx_checksum_enable: bool,
+    #[bit(23, rw)]
+    disable_copy_pause_frames: bool,
+    /// Zynq defines this as 0b00 for 32-bit AMBA AHB data bus width.
+    #[bits(21..=22, r)]
+    dbus_width: u2,
+    #[bits(18..=20, rw)]
+    mdc_clk_div: MdcClkDiv,
+    #[bit(17, rw)]
+    fcs_removal: bool,
+    #[bit(16, rw)]
+    length_field_error_discard: bool,
+    #[bits(14..=15, rw)]
+    rx_buf_offset: u2,
+    #[bit(13, rw)]
+    pause_enable: bool,
+    #[bit(12, rw)]
+    retry_test_enable: bool,
+    #[bit(11, rw)]
+    pcs_select: PcsSelect,
+    #[bit(10, rw)]
+    gigabit_enable: bool,
+    #[bit(9, rw)]
+    ext_addr_match_enable: bool,
+    #[bit(8, rw)]
+    rx_enable_1536: bool,
+    #[bit(7, rw)]
+    unicast_hash_enable: bool,
+    #[bit(6, rw)]
+    multicast_hash_enable: bool,
+    #[bit(5, rw)]
+    no_broadcast: bool,
+    #[bit(4, rw)]
+    copy_all_frames: bool,
+    #[bit(2, rw)]
+    discard_non_vlan: bool,
+    #[bit(1, rw)]
+    full_duplex: bool,
+    #[bit(0, rw)]
+    speed_mode: SpeedMode,
+}
+
+/// PHY management status information.
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct NetworkStatus {
+    #[bit(6, r)]
+    pfc_pri_pause_neg: bool,
+    #[bit(5, r)]
+    pcs_autoneg_pause_tx_res: bool,
+    #[bit(4, r)]
+    pcs_autoneg_pause_rx_res: bool,
+    #[bit(3, r)]
+    pcs_autoneg_dup_res: bool,
+    #[bit(2, r)]
+    phy_mgmt_idle: bool,
+    #[bit(1, r)]
+    mdio_in: bool,
+    #[bit(0, r)]
+    pcs_link_state: bool,
+}
+
+#[derive(Default, Debug, Clone, Copy, PartialEq, Eq)]
+pub enum BurstLength {
+    Single,
+    #[default]
+    Incr4,
+    Incr8,
+    Incr16,
+}
+
+impl BurstLength {
+    pub const fn reg_value(&self) -> u5 {
+        u5::new(match self {
+            BurstLength::Single => 0b1,
+            BurstLength::Incr4 => 0b100,
+            BurstLength::Incr8 => 0b1000,
+            BurstLength::Incr16 => 0b10000,
+        })
+    }
+}
+
+#[bitbybit::bitenum(u1, exhaustive = true)]
+#[derive(Debug, PartialEq, Eq)]
+pub enum AhbEndianess {
+    Little = 0,
+    Big = 1,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+pub struct DmaRxBufSize(u8);
+
+impl DmaRxBufSize {
+    pub const fn new_with_raw_value(size: u8) -> Self {
+        Self(size)
+    }
+
+    pub const fn new(size: u8) -> Option<Self> {
+        if size == 0 {
+            return None;
+        }
+        Some(Self(size))
+    }
+
+    pub const fn raw_value(&self) -> u8 {
+        self.0
+    }
+
+    pub const fn size_in_bytes(&self) -> usize {
+        self.0 as usize * 64
+    }
+
+    pub const fn reg_value(&self) -> u8 {
+        self.0
+    }
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct DmaConfig {
+    #[bit(24, rw)]
+    discard_when_ahb_full: bool,
+    /// DMA receive buffer size in AHB system memory.
+    #[bits(16..=23, rw)]
+    dma_rx_ahb_buf_size_sel: DmaRxBufSize,
+    #[bit(11, rw)]
+    chksum_offload_enable: bool,
+    /// Select size for packet buffer SRAM. Should be set to 1 to use the full configurable address
+    /// space of 4 kB for the packet buffer.
+    #[bit(10, rw)]
+    tx_packet_buf_size_sel: bool,
+    /// Select size for packet buffer SRAM. Should be set to 0b11 to use the full configurable
+    /// address space of 8 kB for the packet buffer.
+    #[bits(8..=9, rw)]
+    rx_packet_buf_size_sel: u2,
+    /// Default value is 0x1 (big endian)
+    #[bit(7, rw)]
+    endian_swap_packet_data: AhbEndianess,
+    // Default value is 0x0 (little endian)
+    #[bit(6, rw)]
+    endian_swap_mgmt_descriptor: AhbEndianess,
+    #[bits(0..=4, rw)]
+    burst_length: u5,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct TxStatus {
+    #[bit(8, rw)]
+    hresp_not_ok: bool,
+    #[bit(7, rw)]
+    late_collision: bool,
+    #[bit(6, rw)]
+    tx_underrun: bool,
+    #[bit(5, rw)]
+    tx_complete: bool,
+    #[bit(4, rw)]
+    tx_frame_corruption_ahb_error: bool,
+    #[bit(3, r)]
+    tx_go: bool,
+    #[bit(2, rw)]
+    retry_limit_reached: bool,
+    #[bit(1, rw)]
+    collision: bool,
+    #[bit(0, rw)]
+    read_when_used: bool,
+}
+
+impl TxStatus {
+    pub fn new_clear_all() -> Self {
+        Self::new_with_raw_value(0xFF)
+    }
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct RxStatus {
+    #[bit(3, rw)]
+    hresp_not_ok: bool,
+    #[bit(2, rw)]
+    rx_overrun: bool,
+    #[bit(1, rw)]
+    frame_received: bool,
+    #[bit(0, rw)]
+    buf_not_available: bool,
+}
+
+impl RxStatus {
+    pub fn new_clear_all() -> Self {
+        Self::new_with_raw_value(0xF)
+    }
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct InterruptStatus {
+    #[bit(26, rw)]
+    tsu_sec_incr: bool,
+    /// Marked N/A in datasheet.
+    #[bit(17, rw)]
+    partner_pg_rx: bool,
+    /// Marked N/A in datasheet.
+    #[bit(16, rw)]
+    auto_negotiation_complete: bool,
+    #[bit(15, rw)]
+    external_interrupt: bool,
+    #[bit(14, rw)]
+    pause_transmitted: bool,
+    #[bit(13, rw)]
+    pause_time_zero: bool,
+    #[bit(12, rw)]
+    pause_with_non_zero_quantum: bool,
+    #[bit(11, rw)]
+    hresp_not_ok: bool,
+    #[bit(10, rw)]
+    rx_overrun: bool,
+    /// Marked N/A in datasheet.
+    #[bit(9, rw)]
+    link_changed: bool,
+    #[bit(7, r)]
+    tx_complete: bool,
+    /// Cleared on read.
+    #[bit(6, r)]
+    tx_frame_corruption_ahb_error: bool,
+    #[bit(5, rw)]
+    retry_limit_reached: bool,
+    #[bit(3, rw)]
+    tx_descr_read_when_used: bool,
+    #[bit(2, rw)]
+    rx_descr_read_when_used: bool,
+    #[bit(1, rw)]
+    frame_received: bool,
+    #[bit(0, rw)]
+    mgmt_frame_sent: bool,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct InterruptControl {
+    #[bit(26, w)]
+    tsu_sec_incr: bool,
+    /// Marked N/A in datasheet.
+    #[bit(17, w)]
+    partner_pg_rx: bool,
+    /// Marked N/A in datasheet.
+    #[bit(16, w)]
+    auto_negotiation_complete: bool,
+    #[bit(15, w)]
+    external_interrupt: bool,
+    #[bit(14, w)]
+    pause_transmitted: bool,
+    #[bit(13, w)]
+    pause_time_zero: bool,
+    #[bit(12, w)]
+    pause_with_non_zero_quantum: bool,
+    #[bit(11, w)]
+    hresp_not_ok: bool,
+    #[bit(10, w)]
+    rx_overrun: bool,
+    /// Marked N/A in datasheet.
+    #[bit(9, w)]
+    link_changed: bool,
+    #[bit(7, w)]
+    tx_complete: bool,
+    /// Cleared on read.
+    #[bit(6, w)]
+    tx_frame_corruption_ahb_error: bool,
+    #[bit(5, w)]
+    retry_limit_reached: bool,
+    #[bit(3, w)]
+    tx_descr_read_when_used: bool,
+    #[bit(2, w)]
+    rx_descr_read_when_used: bool,
+    #[bit(1, w)]
+    frame_received: bool,
+    #[bit(0, w)]
+    mgmt_frame_sent: bool,
+}
+
+impl InterruptControl {
+    pub fn new_clear_all() -> Self {
+        Self::new_with_raw_value(0xFFFF_FFFF)
+    }
+}
+
+#[bitbybit::bitenum(u2, exhaustive = false)]
+pub enum PhyOperation {
+    Read = 0b10,
+    Write = 0b01,
+}
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug)]
+pub struct PhyMaintenance {
+    /// Must be 1 for Clause 22 operations.
+    #[bit(30, rw)]
+    clause_22: bool,
+    #[bits(28..=29, rw)]
+    op: Option<PhyOperation>,
+    #[bits(23..=27, rw)]
+    phy_addr: u5,
+    #[bits(18..=22, rw)]
+    reg_addr: u5,
+    #[bits(16..=17, rw)]
+    must_be_0b10: u2,
+    #[bits(0..=15, rw)]
+    data: u16,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct PauseQuantum {
+    #[bits(0..=15, rw)]
+    value: u16,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct MatchRegister {
+    #[bit(31, rw)]
+    copy_enable: bool,
+    #[bits(0..=15, rw)]
+    type_id: u16,
+}
+
+/// Gigabit Ethernet Controller (GEM) registers for Zynq-7000
+#[derive(derive_mmio::Mmio)]
+#[repr(C)]
+pub struct Ethernet {
+    net_ctrl: NetworkControl,
+    net_cfg: NetworkConfig,
+    #[mmio(PureRead)]
+    net_status: NetworkStatus,
+    _reserved0: u32,
+    dma_cfg: DmaConfig,
+    tx_status: TxStatus,
+    rx_buf_queue_base_addr: u32,
+    tx_buf_queue_base_addr: u32,
+    rx_status: RxStatus,
+    interrupt_status: InterruptStatus,
+    interrupt_enable: InterruptControl,
+    interrupt_disable: InterruptControl,
+    interrupt_mask: InterruptStatus,
+    phy_maintenance: PhyMaintenance,
+    #[mmio(PureRead)]
+    rx_pause_quantum: PauseQuantum,
+    tx_pause_quantum: PauseQuantum,
+    _reserved1: [u32; 0x10],
+    hash_low: u32,
+    hash_high: u32,
+    addr1_low: u32,
+    addr1_high: u32,
+    addr2_low: u32,
+    addr2_high: u32,
+    addr3_low: u32,
+    addr3_high: u32,
+    addr4_low: u32,
+    addr4_high: u32,
+    match_reg: [MatchRegister; 4],
+    wake_on_lan: u32,
+    ipg_stretch: u32,
+    stacked_vlan: u32,
+    tx_pfc: u32,
+    addr1_mask_low: u32,
+    addr1_mask_high: u32,
+    _reserved2: [u32; 0x0B],
+    /// Should be 0x20118.
+    #[mmio(PureRead)]
+    module_id: u32,
+    #[mmio(inner)]
+    statistics: Statistics,
+    _reserved3: [u32; 0x34],
+    #[mmio(PureRead)]
+    design_cfg_2: u32,
+    #[mmio(PureRead)]
+    design_cfg_3: u32,
+    #[mmio(PureRead)]
+    design_cfg_4: u32,
+    #[mmio(PureRead)]
+    design_cfg_5: u32,
+}
+
+static_assertions::const_assert_eq!(core::mem::size_of::<Ethernet>(), 0x294);
+
+/// GEM statistics registers
+#[derive(derive_mmio::Mmio)]
+#[repr(C)]
+pub struct Statistics {
+    #[mmio(PureRead)]
+    tx_octets_low: u32,
+    #[mmio(PureRead)]
+    tx_octets_high: u32,
+    #[mmio(PureRead)]
+    tx_count: u32,
+    #[mmio(PureRead)]
+    tx_broadcast: u32,
+    #[mmio(PureRead)]
+    tx_multicast: u32,
+    #[mmio(PureRead)]
+    tx_pause: u32,
+    #[mmio(PureRead)]
+    tx_64_bits: u32,
+    #[mmio(PureRead)]
+    tx_65_to_127_bits: u32,
+    #[mmio(PureRead)]
+    tx_128_to_255_bits: u32,
+    #[mmio(PureRead)]
+    tx_256_to_511_bits: u32,
+    #[mmio(PureRead)]
+    tx_512_to_1023_bits: u32,
+    #[mmio(PureRead)]
+    tx_1024_to_1518_bits: u32,
+    _reserved0: u32,
+    #[mmio(PureRead)]
+    tx_underruns: u32,
+    #[mmio(PureRead)]
+    single_collision_frames: u32,
+    #[mmio(PureRead)]
+    multi_collision_frames: u32,
+    #[mmio(PureRead)]
+    excessive_collisions: u32,
+    #[mmio(PureRead)]
+    late_collisions: u32,
+    #[mmio(PureRead)]
+    deferred_tx: u32,
+    #[mmio(PureRead)]
+    carrier_sense_errors: u32,
+    #[mmio(PureRead)]
+    rx_octets_low: u32,
+    #[mmio(PureRead)]
+    rx_octets_high: u32,
+    #[mmio(PureRead)]
+    rx_count: u32,
+    #[mmio(PureRead)]
+    rx_broadcast: u32,
+    #[mmio(PureRead)]
+    rx_multicast: u32,
+    #[mmio(PureRead)]
+    rx_pause: u32,
+    #[mmio(PureRead)]
+    rx_64_bits: u32,
+    #[mmio(PureRead)]
+    rx_65_to_127_bits: u32,
+    #[mmio(PureRead)]
+    rx_128_to_255_bits: u32,
+    #[mmio(PureRead)]
+    rx_256_to_511_bits: u32,
+    #[mmio(PureRead)]
+    rx_512_to_1023_bits: u32,
+    #[mmio(PureRead)]
+    rx_1024_to_1518_bits: u32,
+    _reserved1: u32,
+    #[mmio(PureRead)]
+    rx_undersize: u32,
+    #[mmio(PureRead)]
+    rx_oversize: u32,
+    #[mmio(PureRead)]
+    rx_jabber: u32,
+    #[mmio(PureRead)]
+    rx_frame_check_sequence_errors: u32,
+    #[mmio(PureRead)]
+    rx_length_field_errors: u32,
+    #[mmio(PureRead)]
+    rx_symbol_errors: u32,
+    #[mmio(PureRead)]
+    rx_alignment_errors: u32,
+    #[mmio(PureRead)]
+    rx_resource_errors: u32,
+    #[mmio(PureRead)]
+    rx_overrun_errors: u32,
+    #[mmio(PureRead)]
+    rx_ip_header_checksum_errors: u32,
+    #[mmio(PureRead)]
+    rx_tcp_checksum_errors: u32,
+    #[mmio(PureRead)]
+    rx_udp_checksum_errors: u32,
+}
+
+impl Ethernet {
+    /// Create a new Gigabit Ethernet MMIO instance for GEM 0 at address [GEM_0_BASE_ADDR].
+    ///
+    /// # Safety
+    ///
+    /// This API can be used to potentially create a driver to the same peripheral structure
+    /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
+    /// interfere with each other.
+    pub const unsafe fn new_mmio_fixed_0() -> MmioEthernet<'static> {
+        unsafe { Self::new_mmio_at(GEM_0_BASE_ADDR) }
+    }
+
+    /// Create a new Gigabit Ethernet MMIO instance for GEM 1 at address [GEM_1_BASE_ADDR].
+    ///
+    /// # Safety
+    ///
+    /// This API can be used to potentially create a driver to the same peripheral structure
+    /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
+    /// interfere with each other.
+    pub const unsafe fn new_mmio_fixed_1() -> MmioEthernet<'static> {
+        unsafe { Self::new_mmio_at(GEM_1_BASE_ADDR) }
+    }
+}
diff --git a/zynq7000/src/lib.rs b/zynq7000/src/lib.rs
index 5ad2a15..d9a2538 100644
--- a/zynq7000/src/lib.rs
+++ b/zynq7000/src/lib.rs
@@ -15,6 +15,7 @@ extern crate std;
 
 pub const MPCORE_BASE_ADDR: usize = 0xF8F0_0000;
 
+pub mod eth;
 pub mod gic;
 pub mod gpio;
 pub mod gtc;
diff --git a/zynq7000/src/slcr/mio.rs b/zynq7000/src/slcr/mio.rs
index 7236019..f37ec10 100644
--- a/zynq7000/src/slcr/mio.rs
+++ b/zynq7000/src/slcr/mio.rs
@@ -17,7 +17,7 @@ pub enum IoType {
     Hstl = 0b100,
 }
 
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, default = 0x0)]
 #[derive(Debug)]
 pub struct Config {
     #[bit(13, rw)]
diff --git a/zynq7000/src/slcr/mod.rs b/zynq7000/src/slcr/mod.rs
index c6b648e..d6d9bab 100644
--- a/zynq7000/src/slcr/mod.rs
+++ b/zynq7000/src/slcr/mod.rs
@@ -1,7 +1,7 @@
 //! System Level Control Registers (slcr)
 //!
 //! Writing any of these registers required unlocking the SLCR first.
-use arbitrary_int::u4;
+use arbitrary_int::{u3, u4};
 pub use clocks::{ClockControl, MmioClockControl};
 pub use reset::{MmioResetControl, ResetControl};
 
@@ -50,10 +50,27 @@ impl DdrIoB {
 
 static_assertions::const_assert_eq!(core::mem::size_of::<DdrIoB>(), 0x38);
 
+#[bitbybit::bitenum(u3, exhaustive = false)]
+pub enum VrefSel {
+    Disabled = 0b000,
+    Vref0_9V = 0b001,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug)]
+pub struct GpiobControl {
+    #[bit(11, rw)]
+    vref_sw_en: bool,
+    #[bits(4..=6, rw)]
+    vref_sel: Option<VrefSel>,
+    #[bit(0, rw)]
+    vref_en: bool,
+}
+
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct GpiobCtrl {
-    ctrl: u32,
+pub struct GpiobRegisters {
+    ctrl: GpiobControl,
     cfg_cmos18: u32,
     cfg_cmos25: u32,
     cfg_cmos33: u32,
@@ -62,7 +79,7 @@ pub struct GpiobCtrl {
     drvr_bias_ctrl: u32,
 }
 
-impl GpiobCtrl {
+impl GpiobRegisters {
     /// Create a new handle to this peripheral.
     ///
     /// Writing to this register requires unlocking the SLCR registers first.
@@ -71,12 +88,13 @@ impl GpiobCtrl {
     ///
     /// If you create multiple instances of this handle at the same time, you are responsible for
     /// ensuring that there are no read-modify-write races on any of the registers.
-    pub unsafe fn new_mmio_fixed() -> MmioGpiobCtrl<'static> {
+    pub unsafe fn new_mmio_fixed() -> MmioGpiobRegisters<'static> {
         unsafe { Self::new_mmio_at(SLCR_BASE_ADDR + GPIOB_OFFSET) }
     }
 }
 
 #[bitbybit::bitfield(u32)]
+#[derive(Debug)]
 pub struct BootModeRegister {
     #[bit(4, r)]
     pll_bypass: bool,
@@ -183,7 +201,7 @@ pub struct Slcr {
     _gap18: [u32; 0x09],
 
     #[mmio(inner)]
-    gpiob: GpiobCtrl,
+    gpiob: GpiobRegisters,
 
     #[mmio(inner)]
     ddriob: DdrIoB,
diff --git a/zynq7000/src/slcr/reset.rs b/zynq7000/src/slcr/reset.rs
index d427994..286ed23 100644
--- a/zynq7000/src/slcr/reset.rs
+++ b/zynq7000/src/slcr/reset.rs
@@ -35,6 +35,23 @@ pub struct GpioClockReset {
     gpio_cpu1x_rst: bool,
 }
 
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug)]
+pub struct EthernetReset {
+    #[bit(5, rw)]
+    gem1_ref_rst: bool,
+    #[bit(4, rw)]
+    gem0_ref_rst: bool,
+    #[bit(3, rw)]
+    gem1_rx_rst: bool,
+    #[bit(2, rw)]
+    gem0_rx_rst: bool,
+    #[bit(1, rw)]
+    gem1_cpu1x_rst: bool,
+    #[bit(0, rw)]
+    gem0_cpu1x_rst: bool,
+}
+
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct ResetControl {
@@ -45,7 +62,7 @@ pub struct ResetControl {
     topsw: u32,
     dmac: u32,
     usb: u32,
-    gem: u32,
+    eth: EthernetReset,
     sdio: DualRefAndClockReset,
     spi: DualRefAndClockReset,
     can: DualClockReset,