diff --git a/Cargo.lock b/Cargo.lock index 6b77be0..656ed59 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -88,11 +88,11 @@ name = "zedboard-blinky-rs" version = "0.1.0" dependencies = [ "cortex-r-a", - "zynq-rt", + "zynq7000-rt", ] [[package]] -name = "zynq-rt" +name = "zynq7000-rt" version = "0.1.0" dependencies = [ "cortex-a-rt", diff --git a/Cargo.toml b/Cargo.toml index f25b7e7..d266929 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,5 +1,5 @@ [workspace] -members = ["zynq-rt"] +members = ["zynq7000-rt"] [package] name = "zedboard-blinky-rs" @@ -8,4 +8,4 @@ edition = "2021" [dependencies] cortex-r-a = { path = "../cortex-r-a/cortex-r-a" } -zynq-rt = { path = "zynq-rt" } +zynq7000-rt = { path = "zynq7000-rt" } diff --git a/src/main.rs b/src/main.rs index f20001d..c413e57 100644 --- a/src/main.rs +++ b/src/main.rs @@ -3,11 +3,14 @@ use core::panic::PanicInfo; use cortex_r_a::asm::nop; -use zynq_rt as _; +use zynq7000_rt as _; /// Entry point (not called like a normal main function) #[no_mangle] -pub extern "C" fn kmain() -> ! { +pub extern "C" fn boot_core(cpu_id: u32) -> ! { + if cpu_id != 0 { + panic!("unexpected CPU ID {}", cpu_id); + } main(); } diff --git a/zynq-rt/src/bin/main.rs b/zynq-rt/src/bin/main.rs deleted file mode 100644 index e69de29..0000000 diff --git a/zynq-rt/src/lib.rs b/zynq-rt/src/lib.rs deleted file mode 100644 index 9122417..0000000 --- a/zynq-rt/src/lib.rs +++ /dev/null @@ -1,61 +0,0 @@ -#![no_std] - -#[cfg(feature="rt")] -pub mod rt; -pub mod mmu; -mod mmu_table; - -/* -* - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the irq stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x12 /* IRQ mode */ - msr cpsr, r2 - ldr r13,=IRQ_stack /* IRQ stack pointer */ - bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ - msr spsr_fsxc,r2 - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the supervisor stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x13 /* supervisor mode */ - msr cpsr, r2 - ldr r13,=SPV_stack /* Supervisor stack pointer */ - bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ - msr spsr_fsxc,r2 - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the Abort stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x17 /* Abort mode */ - msr cpsr, r2 - ldr r13,=Abort_stack /* Abort stack pointer */ - bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ - msr spsr_fsxc,r2 - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the FIQ stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x11 /* FIQ mode */ - msr cpsr, r2 - ldr r13,=FIQ_stack /* FIQ stack pointer */ - bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ - msr spsr_fsxc,r2 - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the Undefine stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x1b /* Undefine mode */ - msr cpsr, r2 - ldr r13,=Undef_stack /* Undefine stack pointer */ - bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */ - msr spsr_fsxc,r2 - - mrs r0, cpsr /* get the current PSR */ - mvn r1, #0x1f /* set up the system stack pointer */ - and r2, r1, r0 - orr r2, r2, #0x1F /* SYS mode */ - msr cpsr, r2 - ldr r13,=SYS_stack /* SYS stack pointer */ -*/ diff --git a/zynq-rt/Cargo.lock b/zynq7000-rt/Cargo.lock similarity index 100% rename from zynq-rt/Cargo.lock rename to zynq7000-rt/Cargo.lock diff --git a/zynq-rt/Cargo.toml b/zynq7000-rt/Cargo.toml similarity index 83% rename from zynq-rt/Cargo.toml rename to zynq7000-rt/Cargo.toml index 1586184..67a1275 100644 --- a/zynq-rt/Cargo.toml +++ b/zynq7000-rt/Cargo.toml @@ -1,13 +1,12 @@ [package] -name = "zynq-rt" +name = "zynq7000-rt" version = "0.1.0" edition = "2024" [dependencies] -cortex-a-rt = { path = "../../cortex-r-a/cortex-a-rt", optional = true } +cortex-a-rt = { path = "../../cortex-r-a/cortex-a-rt", optional = true, features = ["vfp-dp"] } cortex-r-a = { path = "../../cortex-r-a/cortex-r-a", optional = true } [features] default = ["rt"] rt = ["dep:cortex-a-rt", "dep:cortex-r-a"] - diff --git a/zynq-rt/src/bin/table-gen.rs b/zynq7000-rt/src/bin/table-gen.rs similarity index 100% rename from zynq-rt/src/bin/table-gen.rs rename to zynq7000-rt/src/bin/table-gen.rs diff --git a/zynq7000-rt/src/lib.rs b/zynq7000-rt/src/lib.rs new file mode 100644 index 0000000..976ed43 --- /dev/null +++ b/zynq7000-rt/src/lib.rs @@ -0,0 +1,10 @@ +//! Rust bare metal run-time support for the AMD Zynq 7000 SoCs +//! +//! This includes basic low-level startup code similar to the bare-metal boot routines +//! [provided by Xilinx](https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/cortexa9/gcc). +#![no_std] + +#[cfg(feature="rt")] +pub mod rt; +pub mod mmu; +mod mmu_table; diff --git a/zynq-rt/src/mmu.rs b/zynq7000-rt/src/mmu.rs similarity index 99% rename from zynq-rt/src/mmu.rs rename to zynq7000-rt/src/mmu.rs index 782d321..f3ad257 100644 --- a/zynq-rt/src/mmu.rs +++ b/zynq7000-rt/src/mmu.rs @@ -23,7 +23,6 @@ //! of 1 MB, it is not possible to define separate regions for them. For region //! 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB //! granual size, it is not possible to define separate region for it. -use core::arch::asm; use crate::mmu_table::MMU_L1_PAGE_TABLE; diff --git a/zynq-rt/src/mmu_table.rs b/zynq7000-rt/src/mmu_table.rs similarity index 100% rename from zynq-rt/src/mmu_table.rs rename to zynq7000-rt/src/mmu_table.rs diff --git a/zynq-rt/src/rt.rs b/zynq7000-rt/src/rt.rs similarity index 95% rename from zynq-rt/src/rt.rs rename to zynq7000-rt/src/rt.rs index df61a81..f49f383 100644 --- a/zynq-rt/src/rt.rs +++ b/zynq7000-rt/src/rt.rs @@ -1,3 +1,8 @@ +//! Start-up code for Zynq 7000 +//! +//! The bootup routine was kepts as similar to the one +//! [provided by Xilinx](https://github.com/Xilinx/embeddedsw/blob/master/lib/bsp/standalone/src/arm/cortexa9/gcc/boot.S) +//! as possible. The boot routine includes stack, MMU, cache and .bss/.data section initialization. use cortex_a_rt as _; use cortex_r_a::register::{cpsr::ProcessorMode, Cpsr}; @@ -56,7 +61,7 @@ _start: beq check_efuse b initialize -// Zynq specific code. It is recommended to restet CPU1 according to page 160 of the datasheet +// Zynq specific code. It is recommended to reset CPU1 according to page 160 of the datasheet check_efuse: ldr r0,=EFUSEStatus ldr r1,[r0] /* Read eFuse setting */ @@ -256,7 +261,9 @@ Sync: msr cpsr_xsf, r0 // Jump to application - bl kmain + // Load CPU ID 0, which will be used as a function argument to the boot_core function. + ldr r0, #0x0 + bl boot_core // In case the application returns, loop forever b . .size _start, . - _start