From 4590dfbc88bee5259c6ccada9bb56fa4d3d58236 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Thu, 19 Feb 2026 13:20:48 +0100 Subject: [PATCH] use div-ceil for QSPI clock calc --- firmware/zynq7000-hal/src/qspi/mod.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/firmware/zynq7000-hal/src/qspi/mod.rs b/firmware/zynq7000-hal/src/qspi/mod.rs index d360897..7a1c0a0 100644 --- a/firmware/zynq7000-hal/src/qspi/mod.rs +++ b/firmware/zynq7000-hal/src/qspi/mod.rs @@ -261,7 +261,7 @@ impl ClockConfig { if qspi_ref_clk < clocks.arm_clocks().cpu_1x_clk() { return Err(ClockCalculationError::RefClockSmallerThanCpu1xClock); } - let qspi_baud_rate_div = qspi_ref_clk / target_qspi_interface_clock; + let qspi_baud_rate_div = qspi_ref_clk.raw().div_ceil(target_qspi_interface_clock.raw()); let baud_rate_div = match qspi_baud_rate_div { 0..=2 => BaudRateDivisor::_2, 3..=4 => BaudRateDivisor::_4,