From 5044425a9a0a2ab0d548ee15c12c75c037db29bd Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Wed, 19 Feb 2025 11:00:04 +0100 Subject: [PATCH] init commit --- .cargo/config.toml | 13 +++ .gitignore | 1 + Cargo.lock | 7 ++ Cargo.toml | 6 + link.x | 281 +++++++++++++++++++++++++++++++++++++++++++++ memory.x | 9 ++ src/main.rs | 16 +++ 7 files changed, 333 insertions(+) create mode 100644 .cargo/config.toml create mode 100644 .gitignore create mode 100644 Cargo.lock create mode 100644 Cargo.toml create mode 100644 link.x create mode 100644 memory.x create mode 100644 src/main.rs diff --git a/.cargo/config.toml b/.cargo/config.toml new file mode 100644 index 0000000..8ad96ae --- /dev/null +++ b/.cargo/config.toml @@ -0,0 +1,13 @@ +[target.armv7a-none-eabihf] +rustflags = [ + "-Ctarget-cpu=cortex-a9", + "-Ctarget-feature=+vfp3", + "-Clink-arg=-Tlink.x", +] + +[build] +target = "armv7a-none-eabihf" + +# Tier 3 target, so no pre-compiled artifacts included. +[unstable] +build-std = ["core", "alloc"] diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..ea8c4bf --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +/target diff --git a/Cargo.lock b/Cargo.lock new file mode 100644 index 0000000..9e73e66 --- /dev/null +++ b/Cargo.lock @@ -0,0 +1,7 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. +version = 4 + +[[package]] +name = "zedboard-blinky-rs" +version = "0.1.0" diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..124790e --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,6 @@ +[package] +name = "zedboard-blinky-rs" +version = "0.1.0" +edition = "2021" + +[dependencies] diff --git a/link.x b/link.x new file mode 100644 index 0000000..fbe0263 --- /dev/null +++ b/link.x @@ -0,0 +1,281 @@ +/****************************************************************************** +* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +PROVIDE(_STACK_SIZE = 2048) +PROVIDE(_HEAP_SIZE = 2048) + +PROVIDE(_ABORT_STACK_SIZE = 1024) +PROVIDE(_SUPERVISOR_STACK_SIZE = 2048) +PROVIDE(_IRQ_STACK_SIZE = 1024) +PROVIDE(_FIQ_STACK_SIZE = 1024) +PROVIDE(_UNDEF_STACK_SIZE = 1024) + +INCLUDE memory.x + +/* Specify the default entry point to the program */ + +ENTRY(_vector_table) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.vfp11_veneer) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) + *(.note.gnu.build-id) +} > @DDR@ + +.init : { + KEEP (*(.init)) +} > @DDR@ + +.fini : { + KEEP (*(.fini)) +} > @DDR@ + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > @DDR@ + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > @DDR@ + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > @DDR@ + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > @DDR@ + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + __data_end = .; +} > @DDR@ + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > @DDR@ + +.got : { + *(.got) +} > @DDR@ + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > @DDR@ + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > @DDR@ + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > @DDR@ + +.eh_frame : { + *(.eh_frame) +} > @DDR@ + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > @DDR@ + +.gcc_except_table : { + *(.gcc_except_table) +} > @DDR@ + +.mmu_tbl (ALIGN(16384)) : { + __mmu_tbl_start = .; + *(.mmu_tbl) + __mmu_tbl_end = .; +} > @DDR@ + +.ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; +} > @DDR@ + +.preinit_array : { + __preinit_array_start = .; + KEEP (*(SORT(.preinit_array.*))) + KEEP (*(.preinit_array)) + __preinit_array_end = .; +} > @DDR@ + +.init_array : { + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; +} > @DDR@ + +.fini_array : { + __fini_array_start = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; +} > @DDR@ + +.drvcfg_sec : { + . = ALIGN(8); + __drvcfgsecdata_start = .; + KEEP (*(.drvcfg_sec)) + __drvcfgsecdata_end = .; + __drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start; +} > @DDR@ + +.ARM.attributes : { + __ARM.attributes_start = .; + *(.ARM.attributes) + __ARM.attributes_end = .; +} > @DDR@ + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > @DDR@ + +.sbss (NOLOAD) : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + __sbss_end = .; +} > @DDR@ + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > @DDR@ + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > @DDR@ + +.bss (NOLOAD) : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end = .; +} > @DDR@ + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(16); + _heap = .; + HeapBase = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; + HeapLimit = .; +} > @DDR@ + +.stack (NOLOAD) : { + . = ALIGN(16); + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(16); + _stack = .; + __stack = _stack; + . = ALIGN(16); + _irq_stack_end = .; + . += _IRQ_STACK_SIZE; + . = ALIGN(16); + __irq_stack = .; + _supervisor_stack_end = .; + . += _SUPERVISOR_STACK_SIZE; + . = ALIGN(16); + __supervisor_stack = .; + _abort_stack_end = .; + . += _ABORT_STACK_SIZE; + . = ALIGN(16); + __abort_stack = .; + _fiq_stack_end = .; + . += _FIQ_STACK_SIZE; + . = ALIGN(16); + __fiq_stack = .; + _undef_stack_end = .; + . += _UNDEF_STACK_SIZE; + . = ALIGN(16); + __undef_stack = .; +} > @DDR@ + +end = .; +} diff --git a/memory.x b/memory.x new file mode 100644 index 0000000..f300371 --- /dev/null +++ b/memory.x @@ -0,0 +1,9 @@ + +MEMORY +{ + /* Zedboard: 512 MB DDR3. */ + DDR(rx) : ORIGIN = 0x00100000, LENGTH = 512M +} + +_STACK_SIZE = 8M +_HEAP_SIZE = 64M diff --git a/src/main.rs b/src/main.rs new file mode 100644 index 0000000..7f6ec6f --- /dev/null +++ b/src/main.rs @@ -0,0 +1,16 @@ +#![no_std] +#![no_main] + +use core::panic::PanicInfo; + +/// Entry point (not called like a normal main function) +#[no_mangle] +pub extern "C" fn _start() -> ! { + loop {} +} + +/// Panic handler +#[panic_handler] +fn panic(_info: &PanicInfo) -> ! { + loop {} +}