update for cortex-ar API update
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@@ -6,7 +6,7 @@ edition = "2024"
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[dependencies]
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[dependencies]
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thiserror = { version = "2", default-features = false }
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thiserror = { version = "2", default-features = false }
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cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar", optional = true }
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cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar" }
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[features]
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[features]
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default = ["cortex-ar"]
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tools = []
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@@ -3,8 +3,8 @@
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#![no_std]
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#![no_std]
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use core::cell::UnsafeCell;
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use core::cell::UnsafeCell;
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use cortex_ar::mmu::L1Section;
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#[cfg(feature = "cortex-ar")]
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#[cfg(not(feature = "tools"))]
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use cortex_ar::{
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use cortex_ar::{
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asm::{dsb, isb},
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asm::{dsb, isb},
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cache::clean_and_invalidate_l1_data_cache,
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cache::clean_and_invalidate_l1_data_cache,
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@@ -23,20 +23,20 @@ pub struct AddrNotAlignedToOneMb;
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/// You can use [L1Table] to create a static global L1 table, which can be shared and updated
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/// You can use [L1Table] to create a static global L1 table, which can be shared and updated
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/// without requiring a static mutable global.
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/// without requiring a static mutable global.
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#[repr(C, align(16384))]
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#[repr(C, align(16384))]
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pub struct L1TableRaw(pub [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
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pub struct L1TableRaw(pub [L1Section; NUM_L1_PAGE_TABLE_ENTRIES]);
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impl L1TableRaw {
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impl L1TableRaw {
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#[inline(always)]
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#[inline(always)]
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pub const fn as_ptr(&self) -> *const u32 {
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pub const fn as_ptr(&self) -> *const u32 {
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self.0.as_ptr()
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self.0.as_ptr() as *const _
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}
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}
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#[inline(always)]
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#[inline(always)]
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pub const fn as_mut_ptr(&mut self) -> *mut u32 {
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pub const fn as_mut_ptr(&mut self) -> *mut u32 {
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self.0.as_mut_ptr()
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self.0.as_mut_ptr() as *mut _
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}
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}
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#[cfg(feature = "cortex-ar")]
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#[cfg(not(feature = "tools"))]
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pub fn update(
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pub fn update(
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&mut self,
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&mut self,
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addr: u32,
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addr: u32,
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@@ -46,7 +46,7 @@ impl L1TableRaw {
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return Err(AddrNotAlignedToOneMb);
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return Err(AddrNotAlignedToOneMb);
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}
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}
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let index = addr as usize / 0x10_0000;
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let index = addr as usize / 0x10_0000;
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self.0[index] = (self.0[index] & 0xFFF0_0000) | section_attrs.raw();
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self.0[index].set_section_attrs(section_attrs);
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// The Zynq 7000 has a 32 kB 4-way associative cache with a line length of 32 bytes.
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// The Zynq 7000 has a 32 kB 4-way associative cache with a line length of 32 bytes.
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// 4-way associative cache: A == 2
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// 4-way associative cache: A == 2
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@@ -74,7 +74,7 @@ unsafe impl Sync for L1Table {}
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impl L1Table {
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impl L1Table {
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#[inline]
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#[inline]
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pub const fn new(l1_table: [u32; NUM_L1_PAGE_TABLE_ENTRIES]) -> L1Table {
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pub const fn new(l1_table: [L1Section; NUM_L1_PAGE_TABLE_ENTRIES]) -> L1Table {
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L1Table(UnsafeCell::new(L1TableRaw(l1_table)))
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L1Table(UnsafeCell::new(L1TableRaw(l1_table)))
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}
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}
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}
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}
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@@ -89,7 +89,7 @@ impl<'a> L1TableWrapper<'a> {
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}
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}
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impl L1TableWrapper<'_> {
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impl L1TableWrapper<'_> {
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#[cfg(feature = "cortex-ar")]
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#[cfg(not(feature = "tools"))]
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pub fn update(
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pub fn update(
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&mut self,
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&mut self,
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addr: u32,
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addr: u32,
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@@ -15,11 +15,11 @@ cortex-a-rt = { version = "0.1", optional = true, features = ["vfp-dp"] }
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# cortex-ar = "0.2"
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# cortex-ar = "0.2"
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cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar" }
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cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar" }
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arbitrary-int = "1.3"
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arbitrary-int = "1.3"
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zynq-mmu = { path = "../zynq-mmu", version = "0.1.0", default-features = false }
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zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
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[features]
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[features]
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default = ["rt", "zynq-mmu/cortex-ar"]
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default = ["rt"]
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tools = []
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tools = ["zynq-mmu/tools"]
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rt = ["dep:cortex-a-rt"]
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rt = ["dep:cortex-a-rt"]
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[[bin]]
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[[bin]]
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@@ -8,7 +8,7 @@ macro_rules! write_l1_section {
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($writer:expr, $offset:expr, $attr:expr) => {
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($writer:expr, $offset:expr, $attr:expr) => {
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writeln!(
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writeln!(
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$writer,
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$writer,
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"L1Section::new({:#010x}, {}).raw_value(),",
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"L1Section::new_with_addr_and_attrs({:#010x}, {}),",
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$offset, $attr
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$offset, $attr
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)
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)
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.unwrap();
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.unwrap();
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