update for cortex-ar API update
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This commit is contained in:
2025-07-16 18:29:24 +02:00
parent 602b8915e4
commit 699564d3ee
5 changed files with 4111 additions and 4111 deletions

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@@ -6,7 +6,7 @@ edition = "2024"
[dependencies] [dependencies]
thiserror = { version = "2", default-features = false } thiserror = { version = "2", default-features = false }
cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar", optional = true } cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar" }
[features] [features]
default = ["cortex-ar"] tools = []

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@@ -3,8 +3,8 @@
#![no_std] #![no_std]
use core::cell::UnsafeCell; use core::cell::UnsafeCell;
use cortex_ar::mmu::L1Section;
#[cfg(feature = "cortex-ar")] #[cfg(not(feature = "tools"))]
use cortex_ar::{ use cortex_ar::{
asm::{dsb, isb}, asm::{dsb, isb},
cache::clean_and_invalidate_l1_data_cache, cache::clean_and_invalidate_l1_data_cache,
@@ -23,20 +23,20 @@ pub struct AddrNotAlignedToOneMb;
/// You can use [L1Table] to create a static global L1 table, which can be shared and updated /// You can use [L1Table] to create a static global L1 table, which can be shared and updated
/// without requiring a static mutable global. /// without requiring a static mutable global.
#[repr(C, align(16384))] #[repr(C, align(16384))]
pub struct L1TableRaw(pub [u32; NUM_L1_PAGE_TABLE_ENTRIES]); pub struct L1TableRaw(pub [L1Section; NUM_L1_PAGE_TABLE_ENTRIES]);
impl L1TableRaw { impl L1TableRaw {
#[inline(always)] #[inline(always)]
pub const fn as_ptr(&self) -> *const u32 { pub const fn as_ptr(&self) -> *const u32 {
self.0.as_ptr() self.0.as_ptr() as *const _
} }
#[inline(always)] #[inline(always)]
pub const fn as_mut_ptr(&mut self) -> *mut u32 { pub const fn as_mut_ptr(&mut self) -> *mut u32 {
self.0.as_mut_ptr() self.0.as_mut_ptr() as *mut _
} }
#[cfg(feature = "cortex-ar")] #[cfg(not(feature = "tools"))]
pub fn update( pub fn update(
&mut self, &mut self,
addr: u32, addr: u32,
@@ -46,7 +46,7 @@ impl L1TableRaw {
return Err(AddrNotAlignedToOneMb); return Err(AddrNotAlignedToOneMb);
} }
let index = addr as usize / 0x10_0000; let index = addr as usize / 0x10_0000;
self.0[index] = (self.0[index] & 0xFFF0_0000) | section_attrs.raw(); self.0[index].set_section_attrs(section_attrs);
// The Zynq 7000 has a 32 kB 4-way associative cache with a line length of 32 bytes. // The Zynq 7000 has a 32 kB 4-way associative cache with a line length of 32 bytes.
// 4-way associative cache: A == 2 // 4-way associative cache: A == 2
@@ -74,7 +74,7 @@ unsafe impl Sync for L1Table {}
impl L1Table { impl L1Table {
#[inline] #[inline]
pub const fn new(l1_table: [u32; NUM_L1_PAGE_TABLE_ENTRIES]) -> L1Table { pub const fn new(l1_table: [L1Section; NUM_L1_PAGE_TABLE_ENTRIES]) -> L1Table {
L1Table(UnsafeCell::new(L1TableRaw(l1_table))) L1Table(UnsafeCell::new(L1TableRaw(l1_table)))
} }
} }
@@ -89,7 +89,7 @@ impl<'a> L1TableWrapper<'a> {
} }
impl L1TableWrapper<'_> { impl L1TableWrapper<'_> {
#[cfg(feature = "cortex-ar")] #[cfg(not(feature = "tools"))]
pub fn update( pub fn update(
&mut self, &mut self,
addr: u32, addr: u32,

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@@ -15,11 +15,11 @@ cortex-a-rt = { version = "0.1", optional = true, features = ["vfp-dp"] }
# cortex-ar = "0.2" # cortex-ar = "0.2"
cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar" } cortex-ar = { version = "0.2", path = "../../../Rust/cortex-ar/cortex-ar" }
arbitrary-int = "1.3" arbitrary-int = "1.3"
zynq-mmu = { path = "../zynq-mmu", version = "0.1.0", default-features = false } zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
[features] [features]
default = ["rt", "zynq-mmu/cortex-ar"] default = ["rt"]
tools = [] tools = ["zynq-mmu/tools"]
rt = ["dep:cortex-a-rt"] rt = ["dep:cortex-a-rt"]
[[bin]] [[bin]]

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@@ -8,7 +8,7 @@ macro_rules! write_l1_section {
($writer:expr, $offset:expr, $attr:expr) => { ($writer:expr, $offset:expr, $attr:expr) => {
writeln!( writeln!(
$writer, $writer,
"L1Section::new({:#010x}, {}).raw_value(),", "L1Section::new_with_addr_and_attrs({:#010x}, {}),",
$offset, $attr $offset, $attr
) )
.unwrap(); .unwrap();

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