From 884bc29146f5838244057f1e3f8867fc14ea53e0 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Wed, 26 Feb 2025 13:26:35 +0100 Subject: [PATCH] start derive_mmio experiments --- Cargo.lock | 65 +- Cargo.toml | 2 +- zynq-examples/Cargo.toml | 2 +- zynq7000-rt/Cargo.toml | 4 +- zynq7000-rt/regen-table.sh | 2 + zynq7000-rt/src/bin/table-gen.rs | 34 +- zynq7000-rt/src/mmu.rs | 2 +- zynq7000-rt/src/mmu_table.rs | 8134 ++++++++++++++-------------- zynq7000/Cargo.toml | 8 +- zynq7000/{ => bak}/device.x | 0 zynq7000/{ => bak}/example.svd | 0 zynq7000/{ => bak}/example.svd.tmp | 0 zynq7000/{ => bak}/gen-helper.sh | 0 zynq7000/build.rs | 15 +- zynq7000/src/generic.rs | 730 --- zynq7000/src/generic/raw.rs | 95 - zynq7000/src/lib.rs | 237 +- zynq7000/src/timer0.rs | 110 - zynq7000/src/timer0/count.rs | 28 - zynq7000/src/timer0/cr.rs | 1225 ----- zynq7000/src/timer0/int.rs | 173 - zynq7000/src/timer0/match_.rs | 28 - zynq7000/src/timer0/prescale_rd.rs | 19 - zynq7000/src/timer0/prescale_wr.rs | 24 - zynq7000/src/timer0/reload.rs | 29 - zynq7000/src/timer0/sr.rs | 365 -- 26 files changed, 4158 insertions(+), 7173 deletions(-) create mode 100755 zynq7000-rt/regen-table.sh rename zynq7000/{ => bak}/device.x (100%) rename zynq7000/{ => bak}/example.svd (100%) rename zynq7000/{ => bak}/example.svd.tmp (100%) rename zynq7000/{ => bak}/gen-helper.sh (100%) delete mode 100644 zynq7000/src/generic.rs delete mode 100644 zynq7000/src/generic/raw.rs delete mode 100644 zynq7000/src/timer0.rs delete mode 100644 zynq7000/src/timer0/count.rs delete mode 100644 zynq7000/src/timer0/cr.rs delete mode 100644 zynq7000/src/timer0/int.rs delete mode 100644 zynq7000/src/timer0/match_.rs delete mode 100644 zynq7000/src/timer0/prescale_rd.rs delete mode 100644 zynq7000/src/timer0/prescale_wr.rs delete mode 100644 zynq7000/src/timer0/reload.rs delete mode 100644 zynq7000/src/timer0/sr.rs diff --git a/Cargo.lock b/Cargo.lock index 186c36c..357ff32 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -29,12 +29,12 @@ name = "cortex-a-rt" version = "0.1.0" dependencies = [ "arm-targets", - "cortex-r-a", + "cortex-ar", "semihosting", ] [[package]] -name = "cortex-r-a" +name = "cortex-ar" version = "0.1.0" dependencies = [ "arbitrary-int", @@ -42,6 +42,50 @@ dependencies = [ "bitbybit", ] +[[package]] +name = "derive-mmio" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "290d102578147eb74f297190842998dff79a70c1c242886e6c01f0b2194f8afc" +dependencies = [ + "derive-mmio-macro", +] + +[[package]] +name = "derive-mmio-macro" +version = "0.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7a42cb29e2388869429bcd293f8fd37218e98cce4bb8381b10993de0ddab4928" +dependencies = [ + "proc-macro-error2", + "proc-macro2", + "quote", + "rustversion", + "syn", +] + +[[package]] +name = "proc-macro-error-attr2" +version = "2.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "96de42df36bb9bba5542fe9f1a054b8cc87e172759a1868aa05c1f3acc89dfc5" +dependencies = [ + "proc-macro2", + "quote", +] + +[[package]] +name = "proc-macro-error2" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "11ec05c52be0a07b08061f7dd003e7d7092e0472bc731b4af7bb1ef876109802" +dependencies = [ + "proc-macro-error-attr2", + "proc-macro2", + "quote", + "syn", +] + [[package]] name = "proc-macro2" version = "1.0.93" @@ -60,6 +104,12 @@ dependencies = [ "proc-macro2", ] +[[package]] +name = "rustversion" +version = "1.0.19" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f7c45b9784283f1b2e7fb61b42047c2fd678ef0960d4f6f1eba131594cc369d4" + [[package]] name = "semihosting" version = "0.1.19" @@ -87,14 +137,21 @@ checksum = "00e2473a93778eb0bad35909dff6a10d28e63f792f16ed15e404fca9d5eeedbe" name = "zynq-examples" version = "0.1.0" dependencies = [ - "cortex-r-a", + "cortex-ar", "zynq7000-rt", ] +[[package]] +name = "zynq7000" +version = "0.1.0" +dependencies = [ + "derive-mmio", +] + [[package]] name = "zynq7000-rt" version = "0.1.0" dependencies = [ "cortex-a-rt", - "cortex-r-a", + "cortex-ar", ] diff --git a/Cargo.toml b/Cargo.toml index 7e8d7fc..7206954 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,7 +1,7 @@ [workspace] resolver = "3" members = [ - # "zynq7000", + "zynq7000", "zynq7000-rt", "zynq-examples" ] diff --git a/zynq-examples/Cargo.toml b/zynq-examples/Cargo.toml index c384900..3576101 100644 --- a/zynq-examples/Cargo.toml +++ b/zynq-examples/Cargo.toml @@ -11,5 +11,5 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"] categories = ["embedded", "no-std", "hardware-support"] [dependencies] -cortex-r-a = { path = "../../cortex-r-a/cortex-r-a" } +cortex-ar = { path = "../../cortex-ar/cortex-ar" } zynq7000-rt = { path = "../zynq7000-rt" } diff --git a/zynq7000-rt/Cargo.toml b/zynq7000-rt/Cargo.toml index d423d5e..88ead71 100644 --- a/zynq7000-rt/Cargo.toml +++ b/zynq7000-rt/Cargo.toml @@ -11,8 +11,8 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"] categories = ["embedded", "no-std", "hardware-support"] [dependencies] -cortex-a-rt = { path = "../../cortex-r-a/cortex-a-rt", optional = true, features = ["vfp-dp"] } -cortex-r-a = { path = "../../cortex-r-a/cortex-r-a" } +cortex-a-rt = { path = "../../cortex-ar/cortex-a-rt", optional = true, features = ["vfp-dp"] } +cortex-ar = { path = "../../cortex-ar/cortex-ar" } [features] default = ["rt"] diff --git a/zynq7000-rt/regen-table.sh b/zynq7000-rt/regen-table.sh new file mode 100755 index 0000000..4efe896 --- /dev/null +++ b/zynq7000-rt/regen-table.sh @@ -0,0 +1,2 @@ +#!/bin/bash +cargo +stable run --target $(rustc -vV | grep host | cut -d ' ' -f2) --bin table-gen --no-default-features --features tools diff --git a/zynq7000-rt/src/bin/table-gen.rs b/zynq7000-rt/src/bin/table-gen.rs index 643a577..bbcfbd1 100644 --- a/zynq7000-rt/src/bin/table-gen.rs +++ b/zynq7000-rt/src/bin/table-gen.rs @@ -38,10 +38,10 @@ fn main() { let mut buf_writer = std::io::BufWriter::new(file); writeln!( buf_writer, - "//! This file is auto-generated by table-gen.rs. Do not edit it!" + "//! This file was auto-generated by table-gen.rs" ) .unwrap(); - writeln!(buf_writer, "use cortex_r_a::mmu::L1Section;").unwrap(); + writeln!(buf_writer, "use cortex_ar::mmu::L1Section;").unwrap(); writeln!(buf_writer, "use crate::mmu::{{section_attrs, L1Table}};").unwrap(); writeln!(buf_writer, "").unwrap(); @@ -63,12 +63,12 @@ fn main() { "// First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000)" ) .unwrap(); - writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_ddr).unwrap(); + writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap(); offset += ONE_MB; writeln!(buf_writer, "// DDR memory (0x00100000 - 0x4000_0000)").unwrap(); for _ in 0..DDR_FULL_ACCESSIBLE { - writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_ddr).unwrap(); + writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap(); offset += ONE_MB; } @@ -76,7 +76,7 @@ fn main() { for _ in 0..FPGA_SLAVE { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_fpga_slaves ) .unwrap(); @@ -87,7 +87,7 @@ fn main() { for _ in 0..FPGA_SLAVE { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_fpga_slaves ) .unwrap(); @@ -102,7 +102,7 @@ fn main() { for _ in 0..UNASSIGNED_0 { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_unassigned ) .unwrap(); @@ -117,7 +117,7 @@ fn main() { for _ in 0..IO_PERIPHS { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_shared_dev ) .unwrap(); @@ -132,7 +132,7 @@ fn main() { for _ in 0..UNASSIGNED_1 { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_unassigned ) .unwrap(); @@ -143,7 +143,7 @@ fn main() { for _ in 0..NAND { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_shared_dev ) .unwrap(); @@ -154,7 +154,7 @@ fn main() { for _ in 0..NOR { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_shared_dev ) .unwrap(); @@ -175,7 +175,7 @@ fn main() { for _ in 0..SEGMENTS_UNASSIGNED_2 { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_unassigned ) .unwrap(); @@ -190,7 +190,7 @@ fn main() { for _ in 0..AMBA_APB { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_shared_dev ) .unwrap(); @@ -205,7 +205,7 @@ fn main() { for _ in 0..UNASSIGNED_3 { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_unassigned ) .unwrap(); @@ -214,7 +214,7 @@ fn main() { writeln!(buf_writer, "// QSPI XIP (0xFC00_0000 - 0xFE00_0000)").unwrap(); for _ in 0..QSPI_XIP { - writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_qspi).unwrap(); + writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_qspi).unwrap(); offset += ONE_MB; } @@ -226,7 +226,7 @@ fn main() { for _ in 0..UNASSIGNED_4 { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_unassigned ) .unwrap(); @@ -238,7 +238,7 @@ fn main() { for _ in 0..OCM_MAPPED_HIGH { writeln!( buf_writer, - "L1Section::new({}, {}).0,", + "L1Section::new({}, {}).raw_value(),", offset, attr_ocm_high ) .unwrap(); diff --git a/zynq7000-rt/src/mmu.rs b/zynq7000-rt/src/mmu.rs index 492db51..fc1925a 100644 --- a/zynq7000-rt/src/mmu.rs +++ b/zynq7000-rt/src/mmu.rs @@ -84,7 +84,7 @@ pub mod segments { } pub mod section_attrs { - use cortex_r_a::mmu::{ + use cortex_ar::mmu::{ AccessPermissions, CacheableMemoryAttribute, MemoryRegionAttributes, SectionAttributes, }; diff --git a/zynq7000-rt/src/mmu_table.rs b/zynq7000-rt/src/mmu_table.rs index 1c93920..b6e6776 100644 --- a/zynq7000-rt/src/mmu_table.rs +++ b/zynq7000-rt/src/mmu_table.rs @@ -1,3668 +1,3668 @@ -//! This file is auto-generated by table-gen.rs. Do not edit it! -use crate::mmu::{L1Table, section_attrs}; -use cortex_r_a::mmu::L1Section; +//! This file was auto-generated by table-gen.rs +use crate::mmu::{section_attrs, L1Table}; +use cortex_ar::mmu::L1Section; /// MMU Level 1 Page table. /// /// 4096 entries, each covering 1MB of the address space. pub const MMU_L1_PAGE_TABLE: L1Table = L1Table([ // First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000) - L1Section::new(0, section_attrs::DDR).0, + L1Section::new(0, section_attrs::DDR).raw_value(), // DDR memory (0x00100000 - 0x4000_0000) - L1Section::new(1048576, section_attrs::DDR).0, - L1Section::new(2097152, section_attrs::DDR).0, - L1Section::new(3145728, section_attrs::DDR).0, - L1Section::new(4194304, section_attrs::DDR).0, - L1Section::new(5242880, section_attrs::DDR).0, - L1Section::new(6291456, section_attrs::DDR).0, - L1Section::new(7340032, section_attrs::DDR).0, - L1Section::new(8388608, section_attrs::DDR).0, - L1Section::new(9437184, section_attrs::DDR).0, - L1Section::new(10485760, section_attrs::DDR).0, - L1Section::new(11534336, section_attrs::DDR).0, - L1Section::new(12582912, section_attrs::DDR).0, - L1Section::new(13631488, section_attrs::DDR).0, - L1Section::new(14680064, section_attrs::DDR).0, - L1Section::new(15728640, section_attrs::DDR).0, - L1Section::new(16777216, section_attrs::DDR).0, - L1Section::new(17825792, section_attrs::DDR).0, - L1Section::new(18874368, section_attrs::DDR).0, - L1Section::new(19922944, section_attrs::DDR).0, - L1Section::new(20971520, section_attrs::DDR).0, - L1Section::new(22020096, section_attrs::DDR).0, - L1Section::new(23068672, section_attrs::DDR).0, - L1Section::new(24117248, section_attrs::DDR).0, - L1Section::new(25165824, section_attrs::DDR).0, - L1Section::new(26214400, section_attrs::DDR).0, - L1Section::new(27262976, section_attrs::DDR).0, - L1Section::new(28311552, section_attrs::DDR).0, - L1Section::new(29360128, section_attrs::DDR).0, - L1Section::new(30408704, section_attrs::DDR).0, - L1Section::new(31457280, section_attrs::DDR).0, - L1Section::new(32505856, section_attrs::DDR).0, - L1Section::new(33554432, section_attrs::DDR).0, - L1Section::new(34603008, section_attrs::DDR).0, - L1Section::new(35651584, section_attrs::DDR).0, - L1Section::new(36700160, section_attrs::DDR).0, - L1Section::new(37748736, section_attrs::DDR).0, - L1Section::new(38797312, section_attrs::DDR).0, - L1Section::new(39845888, section_attrs::DDR).0, - L1Section::new(40894464, section_attrs::DDR).0, - L1Section::new(41943040, section_attrs::DDR).0, - L1Section::new(42991616, section_attrs::DDR).0, - L1Section::new(44040192, section_attrs::DDR).0, - L1Section::new(45088768, section_attrs::DDR).0, - L1Section::new(46137344, section_attrs::DDR).0, - L1Section::new(47185920, section_attrs::DDR).0, - L1Section::new(48234496, section_attrs::DDR).0, - L1Section::new(49283072, section_attrs::DDR).0, - L1Section::new(50331648, section_attrs::DDR).0, - L1Section::new(51380224, section_attrs::DDR).0, - L1Section::new(52428800, section_attrs::DDR).0, - L1Section::new(53477376, section_attrs::DDR).0, - L1Section::new(54525952, section_attrs::DDR).0, - L1Section::new(55574528, section_attrs::DDR).0, - L1Section::new(56623104, section_attrs::DDR).0, - L1Section::new(57671680, section_attrs::DDR).0, - L1Section::new(58720256, section_attrs::DDR).0, - L1Section::new(59768832, section_attrs::DDR).0, - L1Section::new(60817408, section_attrs::DDR).0, - L1Section::new(61865984, section_attrs::DDR).0, - L1Section::new(62914560, section_attrs::DDR).0, - L1Section::new(63963136, section_attrs::DDR).0, - L1Section::new(65011712, section_attrs::DDR).0, - L1Section::new(66060288, section_attrs::DDR).0, - L1Section::new(67108864, section_attrs::DDR).0, - L1Section::new(68157440, section_attrs::DDR).0, - L1Section::new(69206016, section_attrs::DDR).0, - L1Section::new(70254592, section_attrs::DDR).0, - L1Section::new(71303168, section_attrs::DDR).0, - L1Section::new(72351744, section_attrs::DDR).0, - L1Section::new(73400320, section_attrs::DDR).0, - L1Section::new(74448896, section_attrs::DDR).0, - L1Section::new(75497472, section_attrs::DDR).0, - L1Section::new(76546048, section_attrs::DDR).0, - L1Section::new(77594624, section_attrs::DDR).0, - L1Section::new(78643200, section_attrs::DDR).0, - L1Section::new(79691776, section_attrs::DDR).0, - L1Section::new(80740352, section_attrs::DDR).0, - L1Section::new(81788928, section_attrs::DDR).0, - L1Section::new(82837504, section_attrs::DDR).0, - L1Section::new(83886080, section_attrs::DDR).0, - L1Section::new(84934656, section_attrs::DDR).0, - L1Section::new(85983232, section_attrs::DDR).0, - L1Section::new(87031808, section_attrs::DDR).0, - L1Section::new(88080384, section_attrs::DDR).0, - L1Section::new(89128960, section_attrs::DDR).0, - L1Section::new(90177536, section_attrs::DDR).0, - L1Section::new(91226112, section_attrs::DDR).0, - L1Section::new(92274688, section_attrs::DDR).0, - L1Section::new(93323264, section_attrs::DDR).0, - L1Section::new(94371840, section_attrs::DDR).0, - L1Section::new(95420416, section_attrs::DDR).0, - L1Section::new(96468992, section_attrs::DDR).0, - L1Section::new(97517568, section_attrs::DDR).0, - L1Section::new(98566144, section_attrs::DDR).0, - L1Section::new(99614720, section_attrs::DDR).0, - L1Section::new(100663296, section_attrs::DDR).0, - L1Section::new(101711872, section_attrs::DDR).0, - L1Section::new(102760448, section_attrs::DDR).0, - L1Section::new(103809024, section_attrs::DDR).0, - L1Section::new(104857600, section_attrs::DDR).0, - L1Section::new(105906176, section_attrs::DDR).0, - L1Section::new(106954752, section_attrs::DDR).0, - L1Section::new(108003328, section_attrs::DDR).0, - L1Section::new(109051904, section_attrs::DDR).0, - L1Section::new(110100480, section_attrs::DDR).0, - L1Section::new(111149056, section_attrs::DDR).0, - L1Section::new(112197632, section_attrs::DDR).0, - L1Section::new(113246208, section_attrs::DDR).0, - L1Section::new(114294784, section_attrs::DDR).0, - L1Section::new(115343360, section_attrs::DDR).0, - L1Section::new(116391936, section_attrs::DDR).0, - L1Section::new(117440512, section_attrs::DDR).0, - L1Section::new(118489088, section_attrs::DDR).0, - L1Section::new(119537664, section_attrs::DDR).0, - L1Section::new(120586240, section_attrs::DDR).0, - L1Section::new(121634816, section_attrs::DDR).0, - L1Section::new(122683392, section_attrs::DDR).0, - L1Section::new(123731968, section_attrs::DDR).0, - L1Section::new(124780544, section_attrs::DDR).0, - L1Section::new(125829120, section_attrs::DDR).0, - L1Section::new(126877696, section_attrs::DDR).0, - L1Section::new(127926272, section_attrs::DDR).0, - L1Section::new(128974848, section_attrs::DDR).0, - L1Section::new(130023424, section_attrs::DDR).0, - L1Section::new(131072000, section_attrs::DDR).0, - L1Section::new(132120576, section_attrs::DDR).0, - L1Section::new(133169152, section_attrs::DDR).0, - L1Section::new(134217728, section_attrs::DDR).0, - L1Section::new(135266304, section_attrs::DDR).0, - L1Section::new(136314880, section_attrs::DDR).0, - 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L1Section::new(828375040, section_attrs::DDR).raw_value(), + L1Section::new(829423616, section_attrs::DDR).raw_value(), + L1Section::new(830472192, section_attrs::DDR).raw_value(), + L1Section::new(831520768, section_attrs::DDR).raw_value(), + L1Section::new(832569344, section_attrs::DDR).raw_value(), + L1Section::new(833617920, section_attrs::DDR).raw_value(), + L1Section::new(834666496, section_attrs::DDR).raw_value(), + L1Section::new(835715072, section_attrs::DDR).raw_value(), + L1Section::new(836763648, section_attrs::DDR).raw_value(), + L1Section::new(837812224, section_attrs::DDR).raw_value(), + L1Section::new(838860800, section_attrs::DDR).raw_value(), + L1Section::new(839909376, section_attrs::DDR).raw_value(), + L1Section::new(840957952, section_attrs::DDR).raw_value(), + L1Section::new(842006528, section_attrs::DDR).raw_value(), + L1Section::new(843055104, section_attrs::DDR).raw_value(), + L1Section::new(844103680, section_attrs::DDR).raw_value(), + L1Section::new(845152256, section_attrs::DDR).raw_value(), + L1Section::new(846200832, section_attrs::DDR).raw_value(), + L1Section::new(847249408, section_attrs::DDR).raw_value(), + L1Section::new(848297984, section_attrs::DDR).raw_value(), + L1Section::new(849346560, section_attrs::DDR).raw_value(), + L1Section::new(850395136, section_attrs::DDR).raw_value(), + L1Section::new(851443712, section_attrs::DDR).raw_value(), + L1Section::new(852492288, section_attrs::DDR).raw_value(), + L1Section::new(853540864, section_attrs::DDR).raw_value(), + L1Section::new(854589440, section_attrs::DDR).raw_value(), + L1Section::new(855638016, section_attrs::DDR).raw_value(), + L1Section::new(856686592, section_attrs::DDR).raw_value(), + L1Section::new(857735168, section_attrs::DDR).raw_value(), + L1Section::new(858783744, section_attrs::DDR).raw_value(), + L1Section::new(859832320, section_attrs::DDR).raw_value(), + L1Section::new(860880896, section_attrs::DDR).raw_value(), + L1Section::new(861929472, section_attrs::DDR).raw_value(), + L1Section::new(862978048, section_attrs::DDR).raw_value(), + L1Section::new(864026624, section_attrs::DDR).raw_value(), + L1Section::new(865075200, section_attrs::DDR).raw_value(), + L1Section::new(866123776, section_attrs::DDR).raw_value(), + L1Section::new(867172352, section_attrs::DDR).raw_value(), + L1Section::new(868220928, section_attrs::DDR).raw_value(), + L1Section::new(869269504, section_attrs::DDR).raw_value(), + L1Section::new(870318080, section_attrs::DDR).raw_value(), + L1Section::new(871366656, section_attrs::DDR).raw_value(), + L1Section::new(872415232, section_attrs::DDR).raw_value(), + L1Section::new(873463808, section_attrs::DDR).raw_value(), + L1Section::new(874512384, section_attrs::DDR).raw_value(), + L1Section::new(875560960, section_attrs::DDR).raw_value(), + L1Section::new(876609536, section_attrs::DDR).raw_value(), + L1Section::new(877658112, section_attrs::DDR).raw_value(), + L1Section::new(878706688, section_attrs::DDR).raw_value(), + L1Section::new(879755264, section_attrs::DDR).raw_value(), + L1Section::new(880803840, section_attrs::DDR).raw_value(), + L1Section::new(881852416, section_attrs::DDR).raw_value(), + L1Section::new(882900992, section_attrs::DDR).raw_value(), + L1Section::new(883949568, section_attrs::DDR).raw_value(), + L1Section::new(884998144, section_attrs::DDR).raw_value(), + L1Section::new(886046720, section_attrs::DDR).raw_value(), + L1Section::new(887095296, section_attrs::DDR).raw_value(), + L1Section::new(888143872, section_attrs::DDR).raw_value(), + L1Section::new(889192448, section_attrs::DDR).raw_value(), + L1Section::new(890241024, section_attrs::DDR).raw_value(), + L1Section::new(891289600, section_attrs::DDR).raw_value(), + L1Section::new(892338176, section_attrs::DDR).raw_value(), + L1Section::new(893386752, section_attrs::DDR).raw_value(), + L1Section::new(894435328, section_attrs::DDR).raw_value(), + L1Section::new(895483904, section_attrs::DDR).raw_value(), + L1Section::new(896532480, section_attrs::DDR).raw_value(), + L1Section::new(897581056, section_attrs::DDR).raw_value(), + L1Section::new(898629632, section_attrs::DDR).raw_value(), + L1Section::new(899678208, section_attrs::DDR).raw_value(), + L1Section::new(900726784, section_attrs::DDR).raw_value(), + L1Section::new(901775360, section_attrs::DDR).raw_value(), + L1Section::new(902823936, section_attrs::DDR).raw_value(), + L1Section::new(903872512, section_attrs::DDR).raw_value(), + L1Section::new(904921088, section_attrs::DDR).raw_value(), + L1Section::new(905969664, section_attrs::DDR).raw_value(), + L1Section::new(907018240, section_attrs::DDR).raw_value(), + L1Section::new(908066816, section_attrs::DDR).raw_value(), + L1Section::new(909115392, section_attrs::DDR).raw_value(), + L1Section::new(910163968, section_attrs::DDR).raw_value(), + L1Section::new(911212544, section_attrs::DDR).raw_value(), + L1Section::new(912261120, section_attrs::DDR).raw_value(), + L1Section::new(913309696, section_attrs::DDR).raw_value(), + L1Section::new(914358272, section_attrs::DDR).raw_value(), + L1Section::new(915406848, section_attrs::DDR).raw_value(), + L1Section::new(916455424, section_attrs::DDR).raw_value(), + L1Section::new(917504000, section_attrs::DDR).raw_value(), + L1Section::new(918552576, section_attrs::DDR).raw_value(), + L1Section::new(919601152, section_attrs::DDR).raw_value(), + L1Section::new(920649728, section_attrs::DDR).raw_value(), + L1Section::new(921698304, section_attrs::DDR).raw_value(), + L1Section::new(922746880, section_attrs::DDR).raw_value(), + L1Section::new(923795456, section_attrs::DDR).raw_value(), + L1Section::new(924844032, section_attrs::DDR).raw_value(), + L1Section::new(925892608, section_attrs::DDR).raw_value(), + L1Section::new(926941184, section_attrs::DDR).raw_value(), + L1Section::new(927989760, section_attrs::DDR).raw_value(), + L1Section::new(929038336, section_attrs::DDR).raw_value(), + L1Section::new(930086912, section_attrs::DDR).raw_value(), + L1Section::new(931135488, section_attrs::DDR).raw_value(), + L1Section::new(932184064, section_attrs::DDR).raw_value(), + L1Section::new(933232640, section_attrs::DDR).raw_value(), + L1Section::new(934281216, section_attrs::DDR).raw_value(), + L1Section::new(935329792, section_attrs::DDR).raw_value(), + L1Section::new(936378368, section_attrs::DDR).raw_value(), + L1Section::new(937426944, section_attrs::DDR).raw_value(), + L1Section::new(938475520, section_attrs::DDR).raw_value(), + L1Section::new(939524096, section_attrs::DDR).raw_value(), + L1Section::new(940572672, section_attrs::DDR).raw_value(), + L1Section::new(941621248, section_attrs::DDR).raw_value(), + L1Section::new(942669824, section_attrs::DDR).raw_value(), + L1Section::new(943718400, section_attrs::DDR).raw_value(), + L1Section::new(944766976, section_attrs::DDR).raw_value(), + L1Section::new(945815552, section_attrs::DDR).raw_value(), + L1Section::new(946864128, section_attrs::DDR).raw_value(), + L1Section::new(947912704, section_attrs::DDR).raw_value(), + L1Section::new(948961280, section_attrs::DDR).raw_value(), + L1Section::new(950009856, section_attrs::DDR).raw_value(), + L1Section::new(951058432, section_attrs::DDR).raw_value(), + L1Section::new(952107008, section_attrs::DDR).raw_value(), + L1Section::new(953155584, section_attrs::DDR).raw_value(), + L1Section::new(954204160, section_attrs::DDR).raw_value(), + L1Section::new(955252736, section_attrs::DDR).raw_value(), + L1Section::new(956301312, section_attrs::DDR).raw_value(), + L1Section::new(957349888, section_attrs::DDR).raw_value(), + L1Section::new(958398464, section_attrs::DDR).raw_value(), + L1Section::new(959447040, section_attrs::DDR).raw_value(), + L1Section::new(960495616, section_attrs::DDR).raw_value(), + L1Section::new(961544192, section_attrs::DDR).raw_value(), + L1Section::new(962592768, section_attrs::DDR).raw_value(), + L1Section::new(963641344, section_attrs::DDR).raw_value(), + L1Section::new(964689920, section_attrs::DDR).raw_value(), + L1Section::new(965738496, section_attrs::DDR).raw_value(), + L1Section::new(966787072, section_attrs::DDR).raw_value(), + L1Section::new(967835648, section_attrs::DDR).raw_value(), + L1Section::new(968884224, section_attrs::DDR).raw_value(), + L1Section::new(969932800, section_attrs::DDR).raw_value(), + L1Section::new(970981376, section_attrs::DDR).raw_value(), + L1Section::new(972029952, section_attrs::DDR).raw_value(), + L1Section::new(973078528, section_attrs::DDR).raw_value(), + L1Section::new(974127104, section_attrs::DDR).raw_value(), + L1Section::new(975175680, section_attrs::DDR).raw_value(), + L1Section::new(976224256, section_attrs::DDR).raw_value(), + L1Section::new(977272832, section_attrs::DDR).raw_value(), + L1Section::new(978321408, section_attrs::DDR).raw_value(), + L1Section::new(979369984, section_attrs::DDR).raw_value(), + L1Section::new(980418560, section_attrs::DDR).raw_value(), + L1Section::new(981467136, section_attrs::DDR).raw_value(), + L1Section::new(982515712, section_attrs::DDR).raw_value(), + L1Section::new(983564288, section_attrs::DDR).raw_value(), + L1Section::new(984612864, section_attrs::DDR).raw_value(), + L1Section::new(985661440, section_attrs::DDR).raw_value(), + L1Section::new(986710016, section_attrs::DDR).raw_value(), + L1Section::new(987758592, section_attrs::DDR).raw_value(), + L1Section::new(988807168, section_attrs::DDR).raw_value(), + L1Section::new(989855744, section_attrs::DDR).raw_value(), + L1Section::new(990904320, section_attrs::DDR).raw_value(), + L1Section::new(991952896, section_attrs::DDR).raw_value(), + L1Section::new(993001472, section_attrs::DDR).raw_value(), + L1Section::new(994050048, section_attrs::DDR).raw_value(), + L1Section::new(995098624, section_attrs::DDR).raw_value(), + L1Section::new(996147200, section_attrs::DDR).raw_value(), + L1Section::new(997195776, section_attrs::DDR).raw_value(), + L1Section::new(998244352, section_attrs::DDR).raw_value(), + L1Section::new(999292928, section_attrs::DDR).raw_value(), + L1Section::new(1000341504, section_attrs::DDR).raw_value(), + L1Section::new(1001390080, section_attrs::DDR).raw_value(), + L1Section::new(1002438656, section_attrs::DDR).raw_value(), + L1Section::new(1003487232, section_attrs::DDR).raw_value(), + L1Section::new(1004535808, section_attrs::DDR).raw_value(), + L1Section::new(1005584384, section_attrs::DDR).raw_value(), + L1Section::new(1006632960, section_attrs::DDR).raw_value(), + L1Section::new(1007681536, section_attrs::DDR).raw_value(), + L1Section::new(1008730112, section_attrs::DDR).raw_value(), + L1Section::new(1009778688, section_attrs::DDR).raw_value(), + L1Section::new(1010827264, section_attrs::DDR).raw_value(), + L1Section::new(1011875840, section_attrs::DDR).raw_value(), + L1Section::new(1012924416, section_attrs::DDR).raw_value(), + L1Section::new(1013972992, section_attrs::DDR).raw_value(), + L1Section::new(1015021568, section_attrs::DDR).raw_value(), + L1Section::new(1016070144, section_attrs::DDR).raw_value(), + L1Section::new(1017118720, section_attrs::DDR).raw_value(), + L1Section::new(1018167296, section_attrs::DDR).raw_value(), + L1Section::new(1019215872, section_attrs::DDR).raw_value(), + L1Section::new(1020264448, section_attrs::DDR).raw_value(), + L1Section::new(1021313024, section_attrs::DDR).raw_value(), + L1Section::new(1022361600, section_attrs::DDR).raw_value(), + L1Section::new(1023410176, section_attrs::DDR).raw_value(), + L1Section::new(1024458752, section_attrs::DDR).raw_value(), + L1Section::new(1025507328, section_attrs::DDR).raw_value(), + L1Section::new(1026555904, section_attrs::DDR).raw_value(), + L1Section::new(1027604480, section_attrs::DDR).raw_value(), + L1Section::new(1028653056, section_attrs::DDR).raw_value(), + L1Section::new(1029701632, section_attrs::DDR).raw_value(), + L1Section::new(1030750208, section_attrs::DDR).raw_value(), + L1Section::new(1031798784, section_attrs::DDR).raw_value(), + L1Section::new(1032847360, section_attrs::DDR).raw_value(), + L1Section::new(1033895936, section_attrs::DDR).raw_value(), + L1Section::new(1034944512, section_attrs::DDR).raw_value(), + L1Section::new(1035993088, section_attrs::DDR).raw_value(), + L1Section::new(1037041664, section_attrs::DDR).raw_value(), + L1Section::new(1038090240, section_attrs::DDR).raw_value(), + L1Section::new(1039138816, section_attrs::DDR).raw_value(), + L1Section::new(1040187392, section_attrs::DDR).raw_value(), + L1Section::new(1041235968, section_attrs::DDR).raw_value(), + L1Section::new(1042284544, section_attrs::DDR).raw_value(), + L1Section::new(1043333120, section_attrs::DDR).raw_value(), + L1Section::new(1044381696, section_attrs::DDR).raw_value(), + L1Section::new(1045430272, section_attrs::DDR).raw_value(), + L1Section::new(1046478848, section_attrs::DDR).raw_value(), + L1Section::new(1047527424, section_attrs::DDR).raw_value(), + L1Section::new(1048576000, section_attrs::DDR).raw_value(), + L1Section::new(1049624576, section_attrs::DDR).raw_value(), + L1Section::new(1050673152, section_attrs::DDR).raw_value(), + L1Section::new(1051721728, section_attrs::DDR).raw_value(), + L1Section::new(1052770304, section_attrs::DDR).raw_value(), + L1Section::new(1053818880, section_attrs::DDR).raw_value(), + L1Section::new(1054867456, section_attrs::DDR).raw_value(), + L1Section::new(1055916032, section_attrs::DDR).raw_value(), + L1Section::new(1056964608, section_attrs::DDR).raw_value(), + L1Section::new(1058013184, section_attrs::DDR).raw_value(), + L1Section::new(1059061760, section_attrs::DDR).raw_value(), + L1Section::new(1060110336, section_attrs::DDR).raw_value(), + L1Section::new(1061158912, section_attrs::DDR).raw_value(), + L1Section::new(1062207488, section_attrs::DDR).raw_value(), + L1Section::new(1063256064, section_attrs::DDR).raw_value(), + L1Section::new(1064304640, section_attrs::DDR).raw_value(), + L1Section::new(1065353216, section_attrs::DDR).raw_value(), + L1Section::new(1066401792, section_attrs::DDR).raw_value(), + L1Section::new(1067450368, section_attrs::DDR).raw_value(), + L1Section::new(1068498944, section_attrs::DDR).raw_value(), + L1Section::new(1069547520, section_attrs::DDR).raw_value(), + L1Section::new(1070596096, section_attrs::DDR).raw_value(), + L1Section::new(1071644672, section_attrs::DDR).raw_value(), + L1Section::new(1072693248, section_attrs::DDR).raw_value(), // FPGA slave 0 (0x4000_0000 - 0x8000_0000) - L1Section::new(1073741824, section_attrs::FPGA_SLAVES).0, - L1Section::new(1074790400, section_attrs::FPGA_SLAVES).0, - L1Section::new(1075838976, section_attrs::FPGA_SLAVES).0, - L1Section::new(1076887552, section_attrs::FPGA_SLAVES).0, - L1Section::new(1077936128, section_attrs::FPGA_SLAVES).0, - L1Section::new(1078984704, section_attrs::FPGA_SLAVES).0, - L1Section::new(1080033280, section_attrs::FPGA_SLAVES).0, - L1Section::new(1081081856, section_attrs::FPGA_SLAVES).0, - L1Section::new(1082130432, section_attrs::FPGA_SLAVES).0, - L1Section::new(1083179008, section_attrs::FPGA_SLAVES).0, - L1Section::new(1084227584, section_attrs::FPGA_SLAVES).0, - L1Section::new(1085276160, section_attrs::FPGA_SLAVES).0, - L1Section::new(1086324736, section_attrs::FPGA_SLAVES).0, - L1Section::new(1087373312, section_attrs::FPGA_SLAVES).0, - L1Section::new(1088421888, section_attrs::FPGA_SLAVES).0, - L1Section::new(1089470464, section_attrs::FPGA_SLAVES).0, - L1Section::new(1090519040, section_attrs::FPGA_SLAVES).0, - L1Section::new(1091567616, section_attrs::FPGA_SLAVES).0, - L1Section::new(1092616192, section_attrs::FPGA_SLAVES).0, - L1Section::new(1093664768, section_attrs::FPGA_SLAVES).0, - L1Section::new(1094713344, section_attrs::FPGA_SLAVES).0, - L1Section::new(1095761920, section_attrs::FPGA_SLAVES).0, - L1Section::new(1096810496, section_attrs::FPGA_SLAVES).0, - L1Section::new(1097859072, section_attrs::FPGA_SLAVES).0, - L1Section::new(1098907648, section_attrs::FPGA_SLAVES).0, - L1Section::new(1099956224, section_attrs::FPGA_SLAVES).0, - L1Section::new(1101004800, section_attrs::FPGA_SLAVES).0, - L1Section::new(1102053376, section_attrs::FPGA_SLAVES).0, - L1Section::new(1103101952, section_attrs::FPGA_SLAVES).0, - L1Section::new(1104150528, section_attrs::FPGA_SLAVES).0, - L1Section::new(1105199104, section_attrs::FPGA_SLAVES).0, - L1Section::new(1106247680, section_attrs::FPGA_SLAVES).0, - L1Section::new(1107296256, section_attrs::FPGA_SLAVES).0, - L1Section::new(1108344832, section_attrs::FPGA_SLAVES).0, - L1Section::new(1109393408, section_attrs::FPGA_SLAVES).0, - L1Section::new(1110441984, section_attrs::FPGA_SLAVES).0, - L1Section::new(1111490560, section_attrs::FPGA_SLAVES).0, - L1Section::new(1112539136, section_attrs::FPGA_SLAVES).0, - L1Section::new(1113587712, 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L1Section::new(1180696576, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1181745152, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1182793728, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1183842304, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1184890880, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1185939456, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1186988032, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1188036608, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1189085184, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1190133760, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1191182336, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1192230912, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1193279488, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1194328064, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1195376640, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1196425216, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1197473792, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1198522368, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1199570944, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1200619520, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1201668096, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1202716672, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1203765248, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1204813824, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1205862400, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1206910976, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1207959552, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1209008128, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1210056704, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1211105280, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1212153856, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1213202432, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1214251008, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1215299584, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1216348160, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1217396736, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1218445312, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1219493888, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1220542464, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1221591040, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1222639616, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1223688192, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1224736768, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1225785344, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1226833920, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1227882496, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1228931072, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1229979648, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1231028224, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1232076800, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1233125376, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1234173952, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1235222528, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1236271104, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1237319680, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1238368256, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1239416832, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1240465408, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1241513984, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1242562560, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1243611136, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1244659712, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1245708288, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1246756864, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1247805440, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1248854016, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1249902592, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1250951168, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1251999744, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1253048320, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1254096896, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1255145472, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1256194048, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1257242624, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1258291200, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1259339776, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1260388352, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1261436928, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1262485504, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1263534080, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1264582656, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1265631232, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1266679808, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1267728384, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1268776960, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1269825536, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1270874112, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1271922688, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1272971264, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1274019840, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1275068416, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1276116992, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1277165568, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1278214144, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1279262720, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1280311296, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1281359872, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1282408448, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1283457024, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1284505600, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1285554176, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1286602752, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1287651328, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1288699904, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1289748480, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1290797056, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1291845632, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1292894208, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1293942784, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1294991360, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1296039936, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1297088512, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1298137088, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1299185664, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1300234240, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1301282816, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1302331392, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1303379968, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1304428544, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1305477120, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1306525696, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1307574272, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1308622848, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1309671424, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1310720000, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1311768576, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1312817152, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1313865728, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1314914304, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1315962880, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1317011456, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1318060032, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1319108608, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1320157184, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1321205760, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1322254336, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1323302912, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1324351488, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1325400064, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1326448640, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1327497216, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1328545792, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1329594368, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1330642944, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1331691520, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1332740096, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1333788672, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1334837248, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1335885824, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1336934400, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1337982976, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1339031552, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1340080128, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1341128704, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1342177280, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1343225856, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1344274432, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1345323008, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1346371584, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1347420160, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1348468736, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1349517312, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1350565888, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1351614464, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1352663040, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1353711616, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1354760192, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1355808768, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1356857344, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1357905920, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1358954496, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1360003072, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1361051648, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1362100224, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1363148800, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1364197376, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1365245952, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1366294528, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1367343104, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1368391680, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1369440256, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1370488832, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1371537408, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1372585984, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1373634560, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1374683136, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1375731712, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1376780288, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1377828864, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1378877440, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1379926016, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1380974592, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1382023168, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1383071744, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1384120320, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1385168896, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1386217472, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1387266048, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1388314624, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1389363200, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1390411776, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1391460352, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1392508928, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1393557504, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1394606080, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1395654656, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1396703232, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1397751808, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1398800384, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1399848960, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1400897536, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1401946112, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1402994688, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1404043264, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1405091840, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1406140416, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1407188992, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1408237568, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1409286144, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1410334720, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1411383296, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1412431872, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1413480448, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1414529024, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1415577600, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1416626176, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1417674752, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1418723328, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1419771904, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1420820480, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1421869056, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1422917632, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1423966208, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1425014784, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1426063360, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1427111936, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1428160512, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1429209088, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1430257664, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1431306240, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1432354816, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1433403392, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1434451968, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1435500544, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1436549120, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1437597696, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1438646272, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1439694848, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1440743424, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1441792000, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1442840576, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1443889152, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1444937728, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1445986304, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1447034880, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1448083456, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1449132032, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1450180608, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1451229184, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1452277760, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1453326336, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1454374912, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1455423488, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1456472064, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1457520640, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1458569216, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1459617792, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1460666368, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1461714944, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1462763520, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1463812096, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1464860672, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1465909248, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1466957824, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1468006400, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1469054976, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1470103552, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1471152128, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1472200704, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1473249280, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1474297856, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1475346432, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1476395008, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1477443584, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1478492160, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1479540736, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1480589312, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1481637888, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1482686464, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1483735040, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1484783616, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1485832192, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1486880768, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1487929344, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1488977920, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1490026496, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1491075072, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1492123648, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1493172224, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1494220800, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1495269376, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1496317952, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1497366528, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1498415104, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1499463680, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1500512256, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1501560832, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1502609408, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1503657984, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1504706560, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1505755136, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1506803712, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1507852288, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1508900864, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1509949440, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1510998016, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1512046592, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1513095168, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1514143744, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1515192320, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1516240896, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1517289472, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1518338048, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1519386624, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1520435200, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1521483776, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1522532352, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1523580928, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1524629504, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1525678080, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1526726656, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1527775232, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1528823808, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1529872384, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1530920960, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1531969536, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1533018112, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1534066688, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1535115264, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1536163840, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1537212416, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1538260992, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1539309568, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1540358144, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1541406720, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1542455296, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1543503872, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1544552448, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1545601024, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1546649600, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1547698176, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1548746752, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1549795328, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1550843904, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1551892480, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1552941056, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1553989632, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1555038208, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1556086784, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1557135360, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1558183936, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1559232512, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1560281088, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1561329664, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1562378240, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1563426816, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1564475392, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1565523968, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1566572544, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1567621120, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1568669696, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1569718272, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1570766848, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1571815424, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1572864000, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1573912576, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1574961152, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1576009728, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1577058304, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1578106880, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1579155456, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1580204032, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1581252608, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1582301184, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1583349760, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1584398336, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1585446912, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1586495488, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1587544064, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1588592640, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1589641216, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1590689792, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1591738368, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1592786944, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1593835520, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1594884096, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1595932672, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1596981248, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1598029824, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1599078400, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1600126976, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1601175552, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1602224128, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1603272704, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1604321280, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1605369856, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1606418432, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1607467008, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1608515584, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1609564160, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1610612736, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1611661312, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1612709888, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1613758464, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1614807040, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1615855616, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1616904192, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1617952768, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1619001344, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1620049920, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1621098496, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1622147072, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1623195648, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1624244224, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1625292800, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1626341376, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1627389952, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1628438528, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1629487104, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1630535680, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1631584256, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1632632832, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1633681408, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1634729984, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1635778560, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1636827136, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1637875712, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1638924288, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1639972864, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1641021440, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1642070016, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1643118592, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1644167168, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1645215744, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1646264320, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1647312896, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1648361472, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1649410048, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1650458624, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1651507200, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1652555776, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1653604352, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1654652928, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1655701504, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1656750080, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1657798656, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1658847232, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1659895808, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1660944384, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1661992960, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1663041536, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1664090112, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1665138688, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1666187264, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1667235840, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1668284416, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1669332992, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1670381568, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1671430144, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1672478720, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1673527296, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1674575872, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1675624448, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1676673024, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1677721600, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1678770176, section_attrs::FPGA_SLAVES).raw_value(), + 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L1Section::new(1958739968, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1959788544, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1960837120, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1961885696, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1962934272, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1963982848, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1965031424, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1966080000, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1967128576, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1968177152, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1969225728, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1970274304, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1971322880, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1972371456, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1973420032, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1974468608, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1975517184, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1976565760, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1977614336, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1978662912, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1979711488, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1980760064, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1981808640, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1982857216, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1983905792, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1984954368, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1986002944, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1987051520, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1988100096, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1989148672, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1990197248, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1991245824, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1992294400, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1993342976, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1994391552, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1995440128, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1996488704, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1997537280, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1998585856, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(1999634432, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2000683008, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2001731584, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2002780160, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2003828736, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2004877312, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2005925888, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2006974464, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2008023040, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2009071616, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2010120192, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2011168768, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2012217344, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2013265920, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2014314496, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2015363072, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2016411648, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2017460224, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2018508800, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2019557376, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2020605952, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2021654528, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2022703104, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2023751680, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2024800256, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2025848832, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2026897408, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2027945984, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2028994560, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2030043136, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2031091712, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2032140288, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2033188864, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2034237440, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2035286016, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2036334592, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2037383168, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2038431744, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2039480320, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2040528896, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2041577472, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2042626048, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2043674624, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2044723200, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2045771776, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2046820352, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2047868928, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2048917504, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2049966080, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2051014656, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2052063232, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2053111808, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2054160384, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2055208960, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2056257536, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2057306112, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2058354688, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2059403264, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2060451840, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2061500416, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2062548992, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2063597568, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2064646144, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2065694720, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2066743296, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2067791872, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2068840448, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2069889024, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2070937600, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2071986176, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2073034752, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2074083328, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2075131904, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2076180480, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2077229056, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2078277632, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2079326208, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2080374784, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2081423360, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2082471936, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2083520512, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2084569088, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2085617664, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2086666240, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2087714816, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2088763392, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2089811968, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2090860544, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2091909120, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2092957696, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2094006272, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2095054848, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2096103424, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2097152000, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2098200576, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2099249152, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2100297728, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2101346304, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2102394880, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2103443456, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2104492032, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2105540608, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2106589184, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2107637760, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2108686336, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2109734912, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2110783488, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2111832064, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2112880640, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2113929216, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2114977792, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2116026368, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2117074944, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2118123520, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2119172096, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2120220672, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2121269248, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2122317824, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2123366400, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2124414976, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2125463552, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2126512128, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2127560704, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2128609280, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2129657856, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2130706432, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2131755008, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2132803584, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2133852160, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2134900736, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2135949312, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2136997888, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2138046464, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2139095040, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2140143616, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2141192192, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2142240768, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2143289344, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2144337920, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2145386496, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(2146435072, section_attrs::FPGA_SLAVES).raw_value(), // FPGA slave 1 (0x8000_0000 - 0xC000_0000) - L1Section::new(2147483648, section_attrs::FPGA_SLAVES).0, - L1Section::new(2148532224, section_attrs::FPGA_SLAVES).0, - L1Section::new(2149580800, section_attrs::FPGA_SLAVES).0, - L1Section::new(2150629376, section_attrs::FPGA_SLAVES).0, - L1Section::new(2151677952, section_attrs::FPGA_SLAVES).0, - L1Section::new(2152726528, section_attrs::FPGA_SLAVES).0, - L1Section::new(2153775104, section_attrs::FPGA_SLAVES).0, - L1Section::new(2154823680, section_attrs::FPGA_SLAVES).0, - L1Section::new(2155872256, section_attrs::FPGA_SLAVES).0, - L1Section::new(2156920832, section_attrs::FPGA_SLAVES).0, - L1Section::new(2157969408, section_attrs::FPGA_SLAVES).0, - L1Section::new(2159017984, section_attrs::FPGA_SLAVES).0, - L1Section::new(2160066560, section_attrs::FPGA_SLAVES).0, - L1Section::new(2161115136, section_attrs::FPGA_SLAVES).0, - L1Section::new(2162163712, section_attrs::FPGA_SLAVES).0, - L1Section::new(2163212288, section_attrs::FPGA_SLAVES).0, - L1Section::new(2164260864, section_attrs::FPGA_SLAVES).0, - L1Section::new(2165309440, section_attrs::FPGA_SLAVES).0, - L1Section::new(2166358016, section_attrs::FPGA_SLAVES).0, - L1Section::new(2167406592, section_attrs::FPGA_SLAVES).0, - L1Section::new(2168455168, section_attrs::FPGA_SLAVES).0, - L1Section::new(2169503744, section_attrs::FPGA_SLAVES).0, - L1Section::new(2170552320, section_attrs::FPGA_SLAVES).0, - L1Section::new(2171600896, section_attrs::FPGA_SLAVES).0, - L1Section::new(2172649472, section_attrs::FPGA_SLAVES).0, - L1Section::new(2173698048, section_attrs::FPGA_SLAVES).0, - L1Section::new(2174746624, section_attrs::FPGA_SLAVES).0, - L1Section::new(2175795200, section_attrs::FPGA_SLAVES).0, - L1Section::new(2176843776, section_attrs::FPGA_SLAVES).0, - L1Section::new(2177892352, section_attrs::FPGA_SLAVES).0, - L1Section::new(2178940928, section_attrs::FPGA_SLAVES).0, - L1Section::new(2179989504, section_attrs::FPGA_SLAVES).0, - L1Section::new(2181038080, section_attrs::FPGA_SLAVES).0, - L1Section::new(2182086656, section_attrs::FPGA_SLAVES).0, - L1Section::new(2183135232, section_attrs::FPGA_SLAVES).0, - L1Section::new(2184183808, section_attrs::FPGA_SLAVES).0, - L1Section::new(2185232384, section_attrs::FPGA_SLAVES).0, - L1Section::new(2186280960, section_attrs::FPGA_SLAVES).0, - L1Section::new(2187329536, section_attrs::FPGA_SLAVES).0, - L1Section::new(2188378112, section_attrs::FPGA_SLAVES).0, - L1Section::new(2189426688, section_attrs::FPGA_SLAVES).0, - L1Section::new(2190475264, section_attrs::FPGA_SLAVES).0, - L1Section::new(2191523840, section_attrs::FPGA_SLAVES).0, - L1Section::new(2192572416, section_attrs::FPGA_SLAVES).0, - L1Section::new(2193620992, section_attrs::FPGA_SLAVES).0, - L1Section::new(2194669568, section_attrs::FPGA_SLAVES).0, - L1Section::new(2195718144, section_attrs::FPGA_SLAVES).0, - L1Section::new(2196766720, section_attrs::FPGA_SLAVES).0, - L1Section::new(2197815296, section_attrs::FPGA_SLAVES).0, - L1Section::new(2198863872, section_attrs::FPGA_SLAVES).0, - L1Section::new(2199912448, section_attrs::FPGA_SLAVES).0, - L1Section::new(2200961024, section_attrs::FPGA_SLAVES).0, - L1Section::new(2202009600, section_attrs::FPGA_SLAVES).0, - L1Section::new(2203058176, section_attrs::FPGA_SLAVES).0, - L1Section::new(2204106752, section_attrs::FPGA_SLAVES).0, - L1Section::new(2205155328, section_attrs::FPGA_SLAVES).0, - L1Section::new(2206203904, section_attrs::FPGA_SLAVES).0, - L1Section::new(2207252480, section_attrs::FPGA_SLAVES).0, - L1Section::new(2208301056, section_attrs::FPGA_SLAVES).0, - L1Section::new(2209349632, section_attrs::FPGA_SLAVES).0, - L1Section::new(2210398208, section_attrs::FPGA_SLAVES).0, - L1Section::new(2211446784, section_attrs::FPGA_SLAVES).0, - L1Section::new(2212495360, section_attrs::FPGA_SLAVES).0, - L1Section::new(2213543936, section_attrs::FPGA_SLAVES).0, - L1Section::new(2214592512, section_attrs::FPGA_SLAVES).0, - L1Section::new(2215641088, section_attrs::FPGA_SLAVES).0, - L1Section::new(2216689664, section_attrs::FPGA_SLAVES).0, - L1Section::new(2217738240, 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section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3073376256, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3074424832, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3075473408, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3076521984, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3077570560, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3078619136, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3079667712, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3080716288, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3081764864, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3082813440, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3083862016, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3084910592, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3085959168, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3087007744, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3088056320, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3089104896, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3090153472, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3091202048, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3092250624, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3093299200, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3094347776, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3095396352, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3096444928, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3097493504, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3098542080, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3099590656, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3100639232, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3101687808, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3102736384, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3103784960, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3104833536, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3105882112, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3106930688, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3107979264, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3109027840, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3110076416, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3111124992, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3112173568, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3113222144, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3114270720, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3115319296, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3116367872, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3117416448, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3118465024, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3119513600, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3120562176, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3121610752, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3122659328, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3123707904, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3124756480, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3125805056, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3126853632, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3127902208, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3128950784, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3129999360, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3131047936, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3132096512, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3133145088, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3134193664, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3135242240, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3136290816, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3137339392, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3138387968, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3139436544, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3140485120, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3141533696, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3142582272, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3143630848, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3144679424, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3145728000, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3146776576, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3147825152, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3148873728, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3149922304, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3150970880, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3152019456, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3153068032, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3154116608, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3155165184, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3156213760, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3157262336, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3158310912, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3159359488, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3160408064, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3161456640, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3162505216, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3163553792, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3164602368, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3165650944, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3166699520, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3167748096, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3168796672, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3169845248, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3170893824, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3171942400, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3172990976, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3174039552, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3175088128, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3176136704, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3177185280, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3178233856, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3179282432, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3180331008, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3181379584, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3182428160, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3183476736, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3184525312, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3185573888, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3186622464, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3187671040, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3188719616, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3189768192, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3190816768, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3191865344, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3192913920, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3193962496, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3195011072, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3196059648, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3197108224, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3198156800, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3199205376, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3200253952, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3201302528, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3202351104, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3203399680, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3204448256, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3205496832, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3206545408, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3207593984, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3208642560, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3209691136, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3210739712, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3211788288, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3212836864, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3213885440, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3214934016, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3215982592, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3217031168, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3218079744, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3219128320, section_attrs::FPGA_SLAVES).raw_value(), + L1Section::new(3220176896, section_attrs::FPGA_SLAVES).raw_value(), // Unassigned/Reserved (0xC000_0000 - 0xE000_0000) - L1Section::new(3221225472, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3222274048, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3223322624, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3224371200, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3225419776, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3226468352, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3227516928, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3228565504, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3229614080, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3230662656, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3231711232, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3232759808, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3233808384, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3234856960, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3235905536, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3236954112, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3238002688, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3239051264, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3240099840, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3241148416, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3242196992, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3243245568, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3244294144, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3245342720, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3246391296, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3247439872, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3248488448, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3249537024, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3250585600, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3251634176, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3252682752, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3253731328, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3254779904, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3255828480, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3256877056, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3257925632, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3258974208, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3260022784, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3261071360, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3262119936, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3263168512, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3264217088, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3265265664, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3266314240, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3267362816, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3268411392, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3269459968, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3270508544, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3271557120, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3272605696, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3273654272, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3274702848, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3275751424, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3276800000, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3277848576, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3278897152, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3279945728, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3280994304, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3282042880, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3283091456, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3284140032, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3285188608, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3286237184, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3287285760, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3288334336, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3289382912, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3290431488, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3291480064, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3292528640, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3293577216, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3294625792, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3295674368, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3296722944, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3297771520, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3298820096, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3299868672, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3300917248, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3301965824, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3303014400, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3304062976, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3305111552, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3306160128, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3307208704, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3308257280, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3309305856, 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L1Section::new(3319791616, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3320840192, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3321888768, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3322937344, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3323985920, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3325034496, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3326083072, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3327131648, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3328180224, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3329228800, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3330277376, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3331325952, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3332374528, 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L1Section::new(3346006016, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3347054592, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3348103168, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3349151744, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3350200320, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3351248896, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3352297472, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3353346048, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3354394624, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3355443200, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3356491776, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3357540352, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3358588928, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3359637504, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3360686080, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3361734656, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3362783232, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3363831808, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3364880384, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3365928960, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3366977536, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3368026112, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3369074688, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3370123264, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3371171840, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3372220416, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3373268992, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3374317568, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3375366144, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3376414720, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3377463296, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3378511872, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3379560448, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3380609024, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3381657600, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3382706176, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3383754752, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3384803328, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3385851904, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3386900480, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3387949056, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3388997632, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3390046208, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3391094784, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3392143360, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3393191936, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3394240512, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3395289088, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3396337664, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3397386240, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3398434816, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3399483392, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3400531968, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3401580544, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3402629120, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3403677696, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3404726272, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3405774848, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3406823424, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3407872000, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3408920576, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3409969152, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3411017728, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3412066304, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3413114880, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3414163456, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3415212032, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3416260608, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3417309184, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3418357760, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3419406336, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3420454912, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3421503488, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3422552064, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3423600640, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3424649216, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3425697792, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3426746368, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3427794944, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3428843520, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3429892096, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3430940672, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3431989248, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3433037824, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3434086400, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3435134976, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3436183552, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3437232128, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3438280704, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3439329280, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3440377856, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3441426432, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3442475008, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3443523584, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3444572160, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3445620736, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3446669312, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3447717888, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3448766464, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3449815040, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3450863616, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3451912192, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3452960768, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3454009344, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3455057920, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3456106496, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3457155072, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3458203648, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3459252224, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3460300800, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3461349376, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3462397952, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3463446528, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3464495104, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3465543680, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3466592256, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3467640832, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3468689408, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3469737984, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3470786560, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3471835136, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3472883712, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3473932288, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3474980864, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3476029440, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3477078016, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3478126592, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3479175168, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3480223744, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3481272320, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3482320896, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3483369472, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3484418048, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3485466624, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3486515200, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3487563776, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3488612352, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3489660928, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3490709504, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3491758080, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3492806656, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3493855232, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3494903808, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3495952384, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3497000960, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3498049536, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3499098112, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3500146688, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3501195264, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3502243840, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3503292416, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3504340992, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3505389568, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3506438144, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3507486720, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3508535296, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3509583872, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3510632448, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3511681024, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3512729600, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3513778176, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3514826752, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3515875328, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3516923904, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3517972480, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3519021056, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3520069632, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3521118208, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3522166784, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3523215360, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3524263936, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3525312512, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3526361088, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3527409664, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3528458240, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3529506816, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3530555392, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3531603968, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3532652544, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3533701120, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3534749696, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3535798272, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3536846848, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3537895424, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3538944000, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3539992576, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3541041152, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3542089728, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3543138304, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3544186880, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3545235456, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3546284032, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3547332608, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3548381184, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3549429760, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3550478336, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3551526912, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3552575488, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3553624064, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3554672640, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3555721216, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3556769792, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3557818368, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3558866944, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3559915520, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3560964096, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3562012672, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3563061248, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3564109824, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3565158400, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3566206976, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3567255552, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3568304128, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3569352704, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3570401280, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3571449856, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3572498432, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3573547008, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3574595584, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3575644160, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3576692736, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3577741312, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3578789888, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3579838464, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3580887040, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3581935616, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3582984192, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3584032768, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3585081344, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3586129920, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3587178496, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3588227072, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3589275648, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3590324224, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3591372800, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3592421376, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3593469952, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3594518528, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3595567104, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3596615680, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3597664256, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3598712832, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3599761408, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3600809984, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3601858560, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3602907136, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3603955712, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3605004288, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3606052864, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3607101440, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3608150016, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3609198592, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3610247168, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3611295744, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3612344320, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3613392896, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3614441472, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3615490048, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3616538624, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3617587200, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3618635776, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3619684352, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3620732928, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3621781504, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3622830080, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3623878656, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3624927232, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3625975808, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3627024384, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3628072960, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3629121536, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3630170112, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3631218688, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3632267264, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3633315840, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3634364416, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3635412992, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3636461568, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3637510144, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3638558720, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3639607296, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3640655872, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3641704448, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3642753024, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3643801600, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3644850176, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3645898752, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3646947328, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3647995904, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3649044480, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3650093056, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3651141632, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3652190208, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3653238784, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3654287360, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3655335936, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3656384512, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3657433088, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3658481664, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3659530240, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3660578816, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3661627392, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3662675968, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3663724544, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3664773120, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3665821696, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3666870272, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3667918848, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3668967424, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3670016000, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3671064576, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3672113152, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3673161728, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3674210304, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3675258880, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3676307456, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3677356032, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3678404608, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3679453184, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3680501760, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3681550336, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3682598912, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3683647488, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3684696064, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3685744640, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3686793216, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3687841792, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3688890368, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3689938944, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3690987520, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3692036096, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3693084672, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3694133248, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3695181824, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3696230400, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3697278976, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3698327552, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3699376128, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3700424704, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3701473280, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3702521856, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3703570432, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3704619008, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3705667584, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3706716160, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3707764736, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3708813312, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3709861888, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3710910464, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3711959040, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3713007616, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3714056192, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3715104768, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3716153344, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3717201920, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3718250496, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3719299072, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3720347648, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3721396224, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3722444800, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3723493376, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3724541952, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3725590528, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3726639104, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3727687680, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3728736256, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3729784832, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3730833408, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3731881984, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3732930560, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3733979136, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3735027712, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3736076288, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3737124864, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3738173440, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3739222016, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3740270592, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3741319168, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3742367744, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3743416320, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3744464896, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3745513472, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3746562048, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3747610624, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3748659200, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3749707776, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3750756352, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3751804928, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3752853504, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3753902080, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3754950656, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3755999232, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3757047808, section_attrs::UNASSIGNED_RESERVED).raw_value(), // Segments IO peripherals (0xE000_0000 - 0xE030_0000) - L1Section::new(3758096384, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3759144960, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3760193536, section_attrs::SHAREABLE_DEVICE).0, + L1Section::new(3758096384, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3759144960, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3760193536, section_attrs::SHAREABLE_DEVICE).raw_value(), // Unassigned/Reserved (0xE030_0000 - 0xE100_0000) - L1Section::new(3761242112, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3762290688, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3763339264, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3764387840, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3765436416, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3766484992, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3767533568, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3768582144, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3769630720, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3770679296, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3771727872, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3772776448, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3773825024, section_attrs::UNASSIGNED_RESERVED).0, + L1Section::new(3761242112, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3762290688, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3763339264, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3764387840, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3765436416, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3766484992, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3767533568, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3768582144, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3769630720, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3770679296, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3771727872, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3772776448, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3773825024, section_attrs::UNASSIGNED_RESERVED).raw_value(), // NAND (0xE100_0000 - 0xE200_0000) - L1Section::new(3774873600, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3775922176, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3776970752, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3778019328, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3779067904, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3780116480, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3781165056, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3782213632, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3783262208, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3784310784, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3785359360, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3786407936, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3787456512, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3788505088, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3789553664, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3790602240, section_attrs::SHAREABLE_DEVICE).0, + L1Section::new(3774873600, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3775922176, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3776970752, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3778019328, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3779067904, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3780116480, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3781165056, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3782213632, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3783262208, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3784310784, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3785359360, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3786407936, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3787456512, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3788505088, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3789553664, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3790602240, section_attrs::SHAREABLE_DEVICE).raw_value(), // NOR (0xE200_0000 - 0xE400_0000) - L1Section::new(3791650816, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3792699392, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3793747968, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3794796544, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3795845120, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3796893696, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3797942272, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3798990848, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3800039424, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3801088000, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3802136576, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3803185152, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3804233728, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3805282304, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3806330880, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3807379456, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3808428032, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3809476608, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3810525184, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3811573760, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3812622336, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3813670912, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3814719488, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3815768064, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3816816640, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3817865216, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3818913792, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3819962368, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3821010944, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3822059520, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3823108096, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(3824156672, section_attrs::SHAREABLE_DEVICE).0, + L1Section::new(3791650816, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3792699392, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3793747968, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3794796544, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3795845120, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3796893696, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3797942272, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3798990848, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3800039424, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3801088000, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3802136576, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3803185152, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3804233728, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3805282304, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3806330880, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3807379456, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3808428032, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3809476608, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3810525184, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3811573760, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3812622336, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3813670912, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3814719488, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3815768064, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3816816640, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3817865216, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3818913792, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3819962368, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3821010944, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3822059520, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3823108096, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(3824156672, section_attrs::SHAREABLE_DEVICE).raw_value(), // SRAM (0xE400_0000 - 0xE600_0000) L1Section::new(3825205248, section_attrs::SRAM).0, L1Section::new(3826253824, section_attrs::SRAM).0, @@ -3697,425 +3697,425 @@ pub const MMU_L1_PAGE_TABLE: L1Table = L1Table([ L1Section::new(3856662528, section_attrs::SRAM).0, L1Section::new(3857711104, section_attrs::SRAM).0, // Unassigned/Reserved (0xE600_0000 - 0xF800_0000) - L1Section::new(3858759680, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3859808256, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3860856832, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3861905408, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3862953984, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3864002560, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3865051136, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3866099712, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3867148288, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3868196864, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3869245440, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3870294016, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3871342592, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3872391168, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3873439744, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3874488320, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3875536896, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3876585472, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3877634048, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3878682624, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3879731200, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3880779776, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3881828352, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3882876928, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3883925504, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3884974080, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3886022656, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3887071232, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3888119808, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3889168384, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3890216960, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3891265536, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3892314112, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3893362688, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3894411264, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3895459840, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3896508416, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3897556992, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3898605568, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3899654144, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3900702720, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3901751296, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3902799872, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3903848448, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3904897024, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3905945600, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3906994176, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3908042752, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3909091328, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3910139904, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3911188480, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3912237056, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3913285632, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3914334208, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3915382784, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3916431360, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3917479936, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3918528512, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3919577088, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3920625664, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3921674240, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3922722816, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3923771392, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3924819968, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3925868544, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3926917120, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3927965696, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3929014272, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3930062848, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3931111424, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3932160000, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3933208576, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3934257152, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3935305728, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3936354304, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3937402880, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3938451456, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3939500032, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3940548608, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3941597184, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3942645760, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3943694336, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3944742912, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3945791488, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3946840064, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3947888640, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3948937216, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3949985792, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3951034368, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3952082944, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3953131520, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3954180096, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3955228672, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3956277248, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3957325824, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3958374400, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3959422976, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3960471552, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3961520128, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3962568704, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3963617280, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3964665856, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3965714432, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3966763008, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3967811584, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3968860160, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3969908736, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3970957312, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3972005888, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3973054464, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3974103040, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3975151616, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3976200192, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3977248768, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3978297344, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3979345920, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3980394496, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3981443072, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3982491648, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3983540224, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3984588800, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3985637376, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3986685952, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3987734528, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3988783104, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3989831680, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3990880256, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3991928832, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3992977408, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3994025984, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3995074560, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3996123136, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3997171712, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3998220288, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(3999268864, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4000317440, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4001366016, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4002414592, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4003463168, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4004511744, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4005560320, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4006608896, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4007657472, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4008706048, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4009754624, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4010803200, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4011851776, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4012900352, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4013948928, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4014997504, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4016046080, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4017094656, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4018143232, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4019191808, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4020240384, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4021288960, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4022337536, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4023386112, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4024434688, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4025483264, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4026531840, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4027580416, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4028628992, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4029677568, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4030726144, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4031774720, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4032823296, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4033871872, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4034920448, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4035969024, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4037017600, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4038066176, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4039114752, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4040163328, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4041211904, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4042260480, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4043309056, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4044357632, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4045406208, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4046454784, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4047503360, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4048551936, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4049600512, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4050649088, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4051697664, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4052746240, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4053794816, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4054843392, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4055891968, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4056940544, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4057989120, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4059037696, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4060086272, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4061134848, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4062183424, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4063232000, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4064280576, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4065329152, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4066377728, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4067426304, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4068474880, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4069523456, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4070572032, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4071620608, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4072669184, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4073717760, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4074766336, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4075814912, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4076863488, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4077912064, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4078960640, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4080009216, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4081057792, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4082106368, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4083154944, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4084203520, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4085252096, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4086300672, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4087349248, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4088397824, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4089446400, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4090494976, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4091543552, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4092592128, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4093640704, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4094689280, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4095737856, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4096786432, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4097835008, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4098883584, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4099932160, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4100980736, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4102029312, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4103077888, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4104126464, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4105175040, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4106223616, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4107272192, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4108320768, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4109369344, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4110417920, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4111466496, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4112515072, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4113563648, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4114612224, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4115660800, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4116709376, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4117757952, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4118806528, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4119855104, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4120903680, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4121952256, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4123000832, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4124049408, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4125097984, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4126146560, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4127195136, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4128243712, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4129292288, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4130340864, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4131389440, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4132438016, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4133486592, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4134535168, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4135583744, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4136632320, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4137680896, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4138729472, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4139778048, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4140826624, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4141875200, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4142923776, section_attrs::UNASSIGNED_RESERVED).0, - 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section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4159700992, section_attrs::UNASSIGNED_RESERVED).0, + L1Section::new(3858759680, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3859808256, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3860856832, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3861905408, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3862953984, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3864002560, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3865051136, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3866099712, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3867148288, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3868196864, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3869245440, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3870294016, 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L1Section::new(3883925504, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3884974080, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3886022656, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3887071232, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3888119808, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3889168384, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3890216960, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3891265536, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3892314112, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3893362688, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3894411264, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3895459840, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3896508416, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3897556992, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3898605568, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3899654144, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3900702720, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3901751296, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3902799872, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3903848448, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3904897024, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3905945600, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3906994176, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3908042752, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3909091328, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3910139904, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3911188480, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3912237056, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3913285632, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3914334208, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3915382784, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3916431360, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3917479936, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3918528512, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3919577088, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3920625664, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3921674240, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3922722816, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3923771392, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3924819968, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3925868544, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3926917120, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3927965696, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3929014272, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3930062848, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3931111424, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3932160000, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3933208576, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3934257152, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3935305728, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3936354304, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3937402880, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3938451456, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3939500032, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3940548608, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3941597184, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3942645760, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3943694336, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3944742912, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3945791488, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3946840064, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3947888640, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3948937216, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3949985792, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3951034368, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3952082944, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3953131520, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3954180096, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3955228672, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3956277248, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3957325824, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3958374400, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3959422976, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3960471552, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3961520128, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3962568704, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3963617280, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3964665856, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3965714432, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3966763008, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3967811584, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3968860160, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3969908736, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3970957312, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3972005888, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3973054464, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3974103040, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3975151616, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3976200192, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3977248768, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3978297344, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3979345920, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3980394496, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3981443072, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3982491648, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3983540224, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3984588800, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3985637376, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3986685952, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3987734528, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3988783104, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3989831680, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3990880256, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3991928832, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3992977408, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3994025984, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3995074560, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3996123136, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3997171712, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3998220288, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(3999268864, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4000317440, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4001366016, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4002414592, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4003463168, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4004511744, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4005560320, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4006608896, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4007657472, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4008706048, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4009754624, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4010803200, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4011851776, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4012900352, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4013948928, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4014997504, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4016046080, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4017094656, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4018143232, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4019191808, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4020240384, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4021288960, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4022337536, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4023386112, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4024434688, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4025483264, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4026531840, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4027580416, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4028628992, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4029677568, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4030726144, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4031774720, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4032823296, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4033871872, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4034920448, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4035969024, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4037017600, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4038066176, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4039114752, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4040163328, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4041211904, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4042260480, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4043309056, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4044357632, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4045406208, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4046454784, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4047503360, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4048551936, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4049600512, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4050649088, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4051697664, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4052746240, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4053794816, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4054843392, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4055891968, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4056940544, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4057989120, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4059037696, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4060086272, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4061134848, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4062183424, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4063232000, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4064280576, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4065329152, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4066377728, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4067426304, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4068474880, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4069523456, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4070572032, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4071620608, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4072669184, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4073717760, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4074766336, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4075814912, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4076863488, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4077912064, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4078960640, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4080009216, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4081057792, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4082106368, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4083154944, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4084203520, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4085252096, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4086300672, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4087349248, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4088397824, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4089446400, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4090494976, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4091543552, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4092592128, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4093640704, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4094689280, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4095737856, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4096786432, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4097835008, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4098883584, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4099932160, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4100980736, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4102029312, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4103077888, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4104126464, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4105175040, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4106223616, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4107272192, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4108320768, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4109369344, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4110417920, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4111466496, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4112515072, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4113563648, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4114612224, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4115660800, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4116709376, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4117757952, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4118806528, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4119855104, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4120903680, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4121952256, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4123000832, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4124049408, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4125097984, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4126146560, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4127195136, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4128243712, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4129292288, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4130340864, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4131389440, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4132438016, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4133486592, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4134535168, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4135583744, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4136632320, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4137680896, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4138729472, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4139778048, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4140826624, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4141875200, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4142923776, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4143972352, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4145020928, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4146069504, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4147118080, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4148166656, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4149215232, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4150263808, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4151312384, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4152360960, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4153409536, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4154458112, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4155506688, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4156555264, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4157603840, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4158652416, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4159700992, section_attrs::UNASSIGNED_RESERVED).raw_value(), // AMBA APB peripherals (0xF800_0000 - 0xF900_0000) - L1Section::new(4160749568, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4161798144, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4162846720, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4163895296, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4164943872, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4165992448, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4167041024, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4168089600, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4169138176, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4170186752, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4171235328, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4172283904, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4173332480, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4174381056, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4175429632, section_attrs::SHAREABLE_DEVICE).0, - L1Section::new(4176478208, section_attrs::SHAREABLE_DEVICE).0, + L1Section::new(4160749568, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4161798144, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4162846720, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4163895296, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4164943872, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4165992448, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4167041024, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4168089600, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4169138176, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4170186752, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4171235328, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4172283904, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4173332480, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4174381056, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4175429632, section_attrs::SHAREABLE_DEVICE).raw_value(), + L1Section::new(4176478208, section_attrs::SHAREABLE_DEVICE).raw_value(), // Unassigned/Reserved (0xF900_0000 - 0xFC00_0000) - L1Section::new(4177526784, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4178575360, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4179623936, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4180672512, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4181721088, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4182769664, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4183818240, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4184866816, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4185915392, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4186963968, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4188012544, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4189061120, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4190109696, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4191158272, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4192206848, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4193255424, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4194304000, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4195352576, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4196401152, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4197449728, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4198498304, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4199546880, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4200595456, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4201644032, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4202692608, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4203741184, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4204789760, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4205838336, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4206886912, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4207935488, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4208984064, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4210032640, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4211081216, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4212129792, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4213178368, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4214226944, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4215275520, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4216324096, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4217372672, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4218421248, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4219469824, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4220518400, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4221566976, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4222615552, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4223664128, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4224712704, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4225761280, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4226809856, section_attrs::UNASSIGNED_RESERVED).0, + L1Section::new(4177526784, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4178575360, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4179623936, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4180672512, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4181721088, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4182769664, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4183818240, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4184866816, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4185915392, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4186963968, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4188012544, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4189061120, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4190109696, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4191158272, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4192206848, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4193255424, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4194304000, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4195352576, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4196401152, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4197449728, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4198498304, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4199546880, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4200595456, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4201644032, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4202692608, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4203741184, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4204789760, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4205838336, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4206886912, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4207935488, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4208984064, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4210032640, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4211081216, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4212129792, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4213178368, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4214226944, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4215275520, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4216324096, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4217372672, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4218421248, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4219469824, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4220518400, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4221566976, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4222615552, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4223664128, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4224712704, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4225761280, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4226809856, section_attrs::UNASSIGNED_RESERVED).raw_value(), // QSPI XIP (0xFC00_0000 - 0xFE00_0000) - L1Section::new(4227858432, section_attrs::QSPI_XIP).0, - L1Section::new(4228907008, section_attrs::QSPI_XIP).0, - L1Section::new(4229955584, section_attrs::QSPI_XIP).0, - L1Section::new(4231004160, section_attrs::QSPI_XIP).0, - L1Section::new(4232052736, section_attrs::QSPI_XIP).0, - L1Section::new(4233101312, section_attrs::QSPI_XIP).0, - L1Section::new(4234149888, section_attrs::QSPI_XIP).0, - L1Section::new(4235198464, section_attrs::QSPI_XIP).0, - L1Section::new(4236247040, section_attrs::QSPI_XIP).0, - L1Section::new(4237295616, section_attrs::QSPI_XIP).0, - L1Section::new(4238344192, section_attrs::QSPI_XIP).0, - L1Section::new(4239392768, section_attrs::QSPI_XIP).0, - L1Section::new(4240441344, section_attrs::QSPI_XIP).0, - L1Section::new(4241489920, section_attrs::QSPI_XIP).0, - L1Section::new(4242538496, section_attrs::QSPI_XIP).0, - L1Section::new(4243587072, section_attrs::QSPI_XIP).0, - L1Section::new(4244635648, section_attrs::QSPI_XIP).0, - L1Section::new(4245684224, section_attrs::QSPI_XIP).0, - L1Section::new(4246732800, section_attrs::QSPI_XIP).0, - L1Section::new(4247781376, section_attrs::QSPI_XIP).0, - L1Section::new(4248829952, section_attrs::QSPI_XIP).0, - L1Section::new(4249878528, section_attrs::QSPI_XIP).0, - L1Section::new(4250927104, section_attrs::QSPI_XIP).0, - L1Section::new(4251975680, section_attrs::QSPI_XIP).0, - L1Section::new(4253024256, section_attrs::QSPI_XIP).0, - L1Section::new(4254072832, section_attrs::QSPI_XIP).0, - L1Section::new(4255121408, section_attrs::QSPI_XIP).0, - L1Section::new(4256169984, section_attrs::QSPI_XIP).0, - L1Section::new(4257218560, section_attrs::QSPI_XIP).0, - L1Section::new(4258267136, section_attrs::QSPI_XIP).0, - L1Section::new(4259315712, section_attrs::QSPI_XIP).0, - L1Section::new(4260364288, section_attrs::QSPI_XIP).0, + L1Section::new(4227858432, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4228907008, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4229955584, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4231004160, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4232052736, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4233101312, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4234149888, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4235198464, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4236247040, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4237295616, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4238344192, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4239392768, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4240441344, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4241489920, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4242538496, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4243587072, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4244635648, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4245684224, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4246732800, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4247781376, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4248829952, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4249878528, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4250927104, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4251975680, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4253024256, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4254072832, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4255121408, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4256169984, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4257218560, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4258267136, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4259315712, section_attrs::QSPI_XIP).raw_value(), + L1Section::new(4260364288, section_attrs::QSPI_XIP).raw_value(), // Unassiged/Reserved (0xFE00_0000 - 0xFFF0_0000) - L1Section::new(4261412864, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4262461440, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4263510016, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4264558592, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4265607168, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4266655744, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4267704320, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4268752896, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4269801472, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4270850048, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4271898624, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4272947200, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4273995776, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4275044352, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4276092928, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4277141504, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4278190080, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4279238656, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4280287232, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4281335808, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4282384384, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4283432960, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4284481536, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4285530112, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4286578688, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4287627264, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4288675840, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4289724416, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4290772992, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4291821568, section_attrs::UNASSIGNED_RESERVED).0, - L1Section::new(4292870144, section_attrs::UNASSIGNED_RESERVED).0, + L1Section::new(4261412864, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4262461440, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4263510016, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4264558592, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4265607168, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4266655744, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4267704320, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4268752896, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4269801472, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4270850048, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4271898624, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4272947200, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4273995776, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4275044352, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4276092928, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4277141504, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4278190080, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4279238656, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4280287232, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4281335808, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4282384384, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4283432960, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4284481536, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4285530112, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4286578688, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4287627264, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4288675840, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4289724416, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4290772992, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4291821568, section_attrs::UNASSIGNED_RESERVED).raw_value(), + L1Section::new(4292870144, section_attrs::UNASSIGNED_RESERVED).raw_value(), // OCM High (0xFFF0_0000 - 0xFFFF_FFFF) - L1Section::new(4293918720, section_attrs::OCM_MAPPED_HIGH).0, + L1Section::new(4293918720, section_attrs::OCM_MAPPED_HIGH).raw_value(), ]); diff --git a/zynq7000/Cargo.toml b/zynq7000/Cargo.toml index c9603b6..7f96f7f 100644 --- a/zynq7000/Cargo.toml +++ b/zynq7000/Cargo.toml @@ -11,10 +11,10 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"] categories = ["embedded", "no-std", "hardware-support"] [dependencies] -# cortex-ra -vcell = "0.1.3" -defmt = { version = "0.3", optional = true } -critical-section = { version = "1", optional = true } +derive-mmio = "0.2" +# cortex-r +# defmt = { version = "0.3", optional = true } +# critical-section = { version = "1", optional = true } [features] # Adds Debug implementation diff --git a/zynq7000/device.x b/zynq7000/bak/device.x similarity index 100% rename from zynq7000/device.x rename to zynq7000/bak/device.x diff --git a/zynq7000/example.svd b/zynq7000/bak/example.svd similarity index 100% rename from zynq7000/example.svd rename to zynq7000/bak/example.svd diff --git a/zynq7000/example.svd.tmp b/zynq7000/bak/example.svd.tmp similarity index 100% rename from zynq7000/example.svd.tmp rename to zynq7000/bak/example.svd.tmp diff --git a/zynq7000/gen-helper.sh b/zynq7000/bak/gen-helper.sh similarity index 100% rename from zynq7000/gen-helper.sh rename to zynq7000/bak/gen-helper.sh diff --git a/zynq7000/build.rs b/zynq7000/build.rs index d0781ac..d12f788 100644 --- a/zynq7000/build.rs +++ b/zynq7000/build.rs @@ -1,17 +1,4 @@ -#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; + fn main() { - if env::var_os("CARGO_FEATURE_RT").is_some() { - let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); - File::create(out.join("device.x")) - .unwrap() - .write_all(include_bytes!("device.x")) - .unwrap(); - println!("cargo:rustc-link-search={}", out.display()); - println!("cargo:rerun-if-changed=device.x"); - } println!("cargo:rerun-if-changed=build.rs"); } diff --git a/zynq7000/src/generic.rs b/zynq7000/src/generic.rs deleted file mode 100644 index 59eec56..0000000 --- a/zynq7000/src/generic.rs +++ /dev/null @@ -1,730 +0,0 @@ -use core::marker; -#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] -pub trait RawReg: - Copy - + Default - + From - + core::ops::BitOr - + core::ops::BitAnd - + core::ops::BitOrAssign - + core::ops::BitAndAssign - + core::ops::Not - + core::ops::Shl -{ - #[doc = " Mask for bits of width `WI`"] - fn mask() -> Self; - #[doc = " Mask for bits of width 1"] - fn one() -> Self; -} -macro_rules! raw_reg { - ($ U : ty , $ size : literal , $ mask : ident) => { - impl RawReg for $U { - #[inline(always)] - fn mask() -> Self { - $mask::() - } - #[inline(always)] - fn one() -> Self { - 1 - } - } - const fn $mask() -> $U { - <$U>::MAX >> ($size - WI) - } - impl FieldSpec for $U { - type Ux = $U; - } - }; -} -raw_reg!(u8, 8, mask_u8); -raw_reg!(u16, 16, mask_u16); -raw_reg!(u32, 32, mask_u32); -raw_reg!(u64, 64, mask_u64); -#[doc = " Raw register type"] -pub trait RegisterSpec { - #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] - type Ux: RawReg; -} -#[doc = " Raw field type"] -pub trait FieldSpec: Sized { - #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] - type Ux: Copy + core::fmt::Debug + PartialEq + From; -} -#[doc = " Marker for fields with fixed values"] -pub trait IsEnum: FieldSpec {} -#[doc = " Trait implemented by readable registers to enable the `read` method."] -#[doc = ""] -#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] -pub trait Readable: RegisterSpec {} -#[doc = " Trait implemented by writeable registers."] -#[doc = ""] -#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] -#[doc = ""] -#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] -pub trait Writable: RegisterSpec { - #[doc = " Is it safe to write any bits to register"] - type Safety; - #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] - const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; - #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] - const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; -} -#[doc = " Reset value of the register."] -#[doc = ""] -#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] -#[doc = " register by using the `reset` method."] -pub trait Resettable: RegisterSpec { - #[doc = " Reset value of the register."] - const RESET_VALUE: Self::Ux; - #[doc = " Reset value of the register."] - #[inline(always)] - fn reset_value() -> Self::Ux { - Self::RESET_VALUE - } -} -#[doc(hidden)] -pub mod raw; -#[doc = " Register reader."] -#[doc = ""] -#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] -#[doc = " method."] -pub type R = raw::R; -impl R { - #[doc = " Reads raw bits from register."] - #[inline(always)] - pub const fn bits(&self) -> REG::Ux { - self.bits - } -} -impl PartialEq for R -where - REG::Ux: PartialEq, - FI: Copy, - REG::Ux: From, -{ - #[inline(always)] - fn eq(&self, other: &FI) -> bool { - self.bits.eq(®::Ux::from(*other)) - } -} -#[doc = " Register writer."] -#[doc = ""] -#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] -pub type W = raw::W; -impl W { - #[doc = " Writes raw bits to the register."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { - self.bits = bits; - self - } -} -impl W -where - REG: Writable, -{ - #[doc = " Writes raw bits to the register."] - #[inline(always)] - pub fn set(&mut self, bits: REG::Ux) -> &mut Self { - self.bits = bits; - self - } -} -#[doc = " Field reader."] -#[doc = ""] -#[doc = " Result of the `read` methods of fields."] -pub type FieldReader = raw::FieldReader; -#[doc = " Bit-wise field reader"] -pub type BitReader = raw::BitReader; -impl FieldReader { - #[doc = " Reads raw bits from field."] - #[inline(always)] - pub const fn bits(&self) -> FI::Ux { - self.bits - } -} -impl core::fmt::Debug for FieldReader { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.bits, f) - } -} -impl PartialEq for FieldReader -where - FI: FieldSpec + Copy, -{ - #[inline(always)] - fn eq(&self, other: &FI) -> bool { - self.bits.eq(&FI::Ux::from(*other)) - } -} -impl PartialEq for BitReader -where - FI: Copy, - bool: From, -{ - #[inline(always)] - fn eq(&self, other: &FI) -> bool { - self.bits.eq(&bool::from(*other)) - } -} -impl BitReader { - #[doc = " Value of the field as raw bits."] - #[inline(always)] - pub const fn bit(&self) -> bool { - self.bits - } - #[doc = " Returns `true` if the bit is clear (0)."] - #[inline(always)] - pub const fn bit_is_clear(&self) -> bool { - !self.bit() - } - #[doc = " Returns `true` if the bit is set (1)."] - #[inline(always)] - pub const fn bit_is_set(&self) -> bool { - self.bit() - } -} -impl core::fmt::Debug for BitReader { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.bits, f) - } -} -#[doc = " Marker for register/field writers which can take any value of specified width"] -pub struct Safe; -#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] -pub struct Unsafe; -#[doc = " Marker for field writers are safe to write in specified inclusive range"] -pub struct Range; -#[doc = " Marker for field writers are safe to write in specified inclusive range"] -pub struct RangeFrom; -#[doc = " Marker for field writers are safe to write in specified inclusive range"] -pub struct RangeTo; -#[doc = " Write field Proxy"] -pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> = - raw::FieldWriter<'a, REG, WI, FI, Safety>; -impl FieldWriter<'_, REG, WI, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - #[doc = " Field width"] - pub const WIDTH: u8 = WI; - #[doc = " Field width"] - #[inline(always)] - pub const fn width(&self) -> u8 { - WI - } - #[doc = " Field offset"] - #[inline(always)] - pub const fn offset(&self) -> u8 { - self.o - } -} -impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { - self.w.bits &= !(REG::Ux::mask::() << self.o); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; - self.w - } -} -impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn set(self, value: FI::Ux) -> &'a mut W { - unsafe { self.bits(value) } - } -} -impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64> - FieldWriter<'a, REG, WI, FI, Range> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, - u64: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn set(self, value: FI::Ux) -> &'a mut W { - { - let value = u64::from(value); - assert!(value >= MIN && value <= MAX); - } - unsafe { self.bits(value) } - } -} -impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, - u64: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn set(self, value: FI::Ux) -> &'a mut W { - { - let value = u64::from(value); - assert!(value >= MIN); - } - unsafe { self.bits(value) } - } -} -impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, - REG::Ux: From, - u64: From, -{ - #[doc = " Writes raw bits to the field"] - #[inline(always)] - pub fn set(self, value: FI::Ux) -> &'a mut W { - { - let value = u64::from(value); - assert!(value <= MAX); - } - unsafe { self.bits(value) } - } -} -impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: IsEnum, - REG::Ux: From, -{ - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - unsafe { self.bits(FI::Ux::from(variant)) } - } -} -macro_rules! bit_proxy { - ($ writer : ident , $ mwv : ident) => { - #[doc(hidden)] - pub struct $mwv; - #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; - impl<'a, REG, FI> $writer<'a, REG, FI> - where - REG: Writable + RegisterSpec, - bool: From, - { - #[doc = " Field width"] - pub const WIDTH: u8 = 1; - #[doc = " Field width"] - #[inline(always)] - pub const fn width(&self) -> u8 { - Self::WIDTH - } - #[doc = " Field offset"] - #[inline(always)] - pub const fn offset(&self) -> u8 { - self.o - } - #[doc = " Writes bit to the field"] - #[inline(always)] - pub fn bit(self, value: bool) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o; - self.w - } - #[doc = " Writes `variant` to the field"] - #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut W { - self.bit(bool::from(variant)) - } - } - }; -} -bit_proxy!(BitWriter, BitM); -bit_proxy!(BitWriter1S, Bit1S); -bit_proxy!(BitWriter0C, Bit0C); -bit_proxy!(BitWriter1C, Bit1C); -bit_proxy!(BitWriter0S, Bit0S); -bit_proxy!(BitWriter1T, Bit1T); -bit_proxy!(BitWriter0T, Bit0T); -impl<'a, REG, FI> BitWriter<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Sets the field bit"] - #[inline(always)] - pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << self.o; - self.w - } - #[doc = " Clears the field bit"] - #[inline(always)] - pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w - } -} -impl<'a, REG, FI> BitWriter1S<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Sets the field bit"] - #[inline(always)] - pub fn set_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << self.o; - self.w - } -} -impl<'a, REG, FI> BitWriter0C<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Clears the field bit"] - #[inline(always)] - pub fn clear_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w - } -} -impl<'a, REG, FI> BitWriter1C<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Clears the field bit by passing one"] - #[inline(always)] - pub fn clear_bit_by_one(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << self.o; - self.w - } -} -impl<'a, REG, FI> BitWriter0S<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Sets the field bit by passing zero"] - #[inline(always)] - pub fn set_bit_by_zero(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w - } -} -impl<'a, REG, FI> BitWriter1T<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Toggle the field bit by passing one"] - #[inline(always)] - pub fn toggle_bit(self) -> &'a mut W { - self.w.bits |= REG::Ux::one() << self.o; - self.w - } -} -impl<'a, REG, FI> BitWriter0T<'a, REG, FI> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = "Toggle the field bit by passing zero"] - #[inline(always)] - pub fn toggle_bit(self) -> &'a mut W { - self.w.bits &= !(REG::Ux::one() << self.o); - self.w - } -} -#[doc = " This structure provides volatile access to registers."] -#[repr(transparent)] -pub struct Reg { - register: vcell::VolatileCell, - _marker: marker::PhantomData, -} -unsafe impl Send for Reg where REG::Ux: Send {} -impl Reg { - #[doc = " Returns the underlying memory address of register."] - #[doc = ""] - #[doc = " ```ignore"] - #[doc = " let reg_ptr = periph.reg.as_ptr();"] - #[doc = " ```"] - #[inline(always)] - pub fn as_ptr(&self) -> *mut REG::Ux { - self.register.as_ptr() - } -} -impl Reg { - #[doc = " Reads the contents of a `Readable` register."] - #[doc = ""] - #[doc = " You can read the raw contents of a register by using `bits`:"] - #[doc = " ```ignore"] - #[doc = " let bits = periph.reg.read().bits();"] - #[doc = " ```"] - #[doc = " or get the content of a particular field of a register:"] - #[doc = " ```ignore"] - #[doc = " let reader = periph.reg.read();"] - #[doc = " let bits = reader.field1().bits();"] - #[doc = " let flag = reader.field2().bit_is_set();"] - #[doc = " ```"] - #[inline(always)] - pub fn read(&self) -> R { - R { - bits: self.register.get(), - _reg: marker::PhantomData, - } - } -} -impl Reg { - #[doc = " Writes the reset value to `Writable` register."] - #[doc = ""] - #[doc = " Resets the register to its initial state."] - #[inline(always)] - pub fn reset(&self) { - self.register.set(REG::RESET_VALUE) - } - #[doc = " Writes bits to a `Writable` register."] - #[doc = ""] - #[doc = " You can write raw bits into a register:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] - #[doc = " ```"] - #[doc = " or write only the fields you need:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write(|w| w"] - #[doc = " .field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT)"] - #[doc = " );"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write(|w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT)"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " In the latter case, other fields will be set to their reset value."] - #[inline(always)] - pub fn write(&self, f: F) -> REG::Ux - where - F: FnOnce(&mut W) -> &mut W, - { - let value = f(&mut W { - bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP - | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }) - .bits; - self.register.set(value); - value - } - #[doc = " Writes bits to a `Writable` register and produce a value."] - #[doc = ""] - #[doc = " You can write raw bits into a register:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"] - #[doc = " ```"] - #[doc = " or write only the fields you need:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write_and(|w| {"] - #[doc = " w.field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT);"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.write_and(|w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT);"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " In the latter case, other fields will be set to their reset value."] - #[doc = ""] - #[doc = " Values can be returned from the closure:"] - #[doc = " ```ignore"] - #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"] - #[doc = " ```"] - #[inline(always)] - pub fn from_write(&self, f: F) -> T - where - F: FnOnce(&mut W) -> T, - { - let mut writer = W { - bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP - | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }; - let result = f(&mut writer); - self.register.set(writer.bits); - result - } -} -impl Reg { - #[doc = " Writes 0 to a `Writable` register."] - #[doc = ""] - #[doc = " Similar to `write`, but unused bits will contain 0."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Unsafe to use with registers which don't allow to write 0."] - #[inline(always)] - pub unsafe fn write_with_zero(&self, f: F) -> REG::Ux - where - F: FnOnce(&mut W) -> &mut W, - { - let value = f(&mut W { - bits: REG::Ux::default(), - _reg: marker::PhantomData, - }) - .bits; - self.register.set(value); - value - } - #[doc = " Writes 0 to a `Writable` register and produces a value."] - #[doc = ""] - #[doc = " Similar to `write`, but unused bits will contain 0."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Unsafe to use with registers which don't allow to write 0."] - #[inline(always)] - pub unsafe fn from_write_with_zero(&self, f: F) -> T - where - F: FnOnce(&mut W) -> T, - { - let mut writer = W { - bits: REG::Ux::default(), - _reg: marker::PhantomData, - }; - let result = f(&mut writer); - self.register.set(writer.bits); - result - } -} -impl Reg { - #[doc = " Modifies the contents of the register by reading and then writing it."] - #[doc = ""] - #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] - #[doc = " r.bits() | 3"] - #[doc = " ) });"] - #[doc = " ```"] - #[doc = " or"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| w"] - #[doc = " .field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT)"] - #[doc = " );"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT)"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " Other fields will have the value they had before the call to `modify`."] - #[inline(always)] - pub fn modify(&self, f: F) -> REG::Ux - where - for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, - { - let bits = self.register.get(); - let value = f( - &R { - bits, - _reg: marker::PhantomData, - }, - &mut W { - bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }, - ) - .bits; - self.register.set(value); - value - } - #[doc = " Modifies the contents of the register by reading and then writing it"] - #[doc = " and produces a value."] - #[doc = ""] - #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] - #[doc = " ```ignore"] - #[doc = " let bits = periph.reg.modify(|r, w| {"] - #[doc = " let new_bits = r.bits() | 3;"] - #[doc = " unsafe {"] - #[doc = " w.bits(new_bits);"] - #[doc = " }"] - #[doc = ""] - #[doc = " new_bits"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " or"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| {"] - #[doc = " w.field1().bits(newfield1bits)"] - #[doc = " .field2().set_bit()"] - #[doc = " .field3().variant(VARIANT);"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " or an alternative way of saying the same:"] - #[doc = " ```ignore"] - #[doc = " periph.reg.modify(|_, w| {"] - #[doc = " w.field1().bits(newfield1bits);"] - #[doc = " w.field2().set_bit();"] - #[doc = " w.field3().variant(VARIANT);"] - #[doc = " });"] - #[doc = " ```"] - #[doc = " Other fields will have the value they had before the call to `modify`."] - #[inline(always)] - pub fn from_modify(&self, f: F) -> T - where - for<'w> F: FnOnce(&R, &'w mut W) -> T, - { - let bits = self.register.get(); - let mut writer = W { - bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, - _reg: marker::PhantomData, - }; - let result = f( - &R { - bits, - _reg: marker::PhantomData, - }, - &mut writer, - ); - self.register.set(writer.bits); - result - } -} -impl core::fmt::Debug for crate::generic::Reg -where - R: core::fmt::Debug, -{ - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - core::fmt::Debug::fmt(&self.read(), f) - } -} diff --git a/zynq7000/src/generic/raw.rs b/zynq7000/src/generic/raw.rs deleted file mode 100644 index 6a53dfe..0000000 --- a/zynq7000/src/generic/raw.rs +++ /dev/null @@ -1,95 +0,0 @@ -use super::{BitM, FieldSpec, RegisterSpec, Unsafe, Writable, marker}; -pub struct R { - pub(crate) bits: REG::Ux, - pub(super) _reg: marker::PhantomData, -} -pub struct W { - #[doc = "Writable bits"] - pub(crate) bits: REG::Ux, - pub(super) _reg: marker::PhantomData, -} -pub struct FieldReader -where - FI: FieldSpec, -{ - pub(crate) bits: FI::Ux, - _reg: marker::PhantomData, -} -impl FieldReader { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) const fn new(bits: FI::Ux) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -pub struct BitReader { - pub(crate) bits: bool, - _reg: marker::PhantomData, -} -impl BitReader { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) const fn new(bits: bool) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -#[must_use = "after creating `FieldWriter` you need to call field value setting method"] -pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - pub(crate) w: &'a mut W, - pub(crate) o: u8, - _field: marker::PhantomData<(FI, Safety)>, -} -impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut W, o: u8) -> Self { - Self { - w, - o, - _field: marker::PhantomData, - } - } -} -#[must_use = "after creating `BitWriter` you need to call bit setting method"] -pub struct BitWriter<'a, REG, FI = bool, M = BitM> -where - REG: Writable + RegisterSpec, - bool: From, -{ - pub(crate) w: &'a mut W, - pub(crate) o: u8, - _field: marker::PhantomData<(FI, M)>, -} -impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut W, o: u8) -> Self { - Self { - w, - o, - _field: marker::PhantomData, - } - } -} diff --git a/zynq7000/src/lib.rs b/zynq7000/src/lib.rs index 9b5b0e5..5fdf5d1 100644 --- a/zynq7000/src/lib.rs +++ b/zynq7000/src/lib.rs @@ -1,237 +1,2 @@ -#![doc = "Peripheral access API for ARM_EXAMPLE microcontrollers (generated using svd2rust v0.35.0 (e10f920 2025-02-12))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] -svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.35.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] -#![allow(non_camel_case_types)] -#![allow(non_snake_case)] +//! Rust peripheral acess crate to the AMD Zynq 7000 SoCs #![no_std] -use core::marker::PhantomData; -use core::ops::Deref; -#[doc = r"Number available in the NVIC for configuring priority"] -pub const NVIC_PRIO_BITS: u8 = 3; -#[cfg(feature = "rt")] -pub use self::Interrupt as interrupt; -#[cfg(feature = "rt")] -pub use cortex_m_rt::interrupt; -#[allow(unused_imports)] -use generic::*; -#[doc = r"Common register and bit access and modify traits"] -pub mod generic; -#[cfg(feature = "rt")] -extern "C" { - fn TIMER0(); - fn TIMER1(); - fn TIMER2(); -} -#[doc(hidden)] -#[repr(C)] -pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, -} -#[cfg(feature = "rt")] -#[doc(hidden)] -#[link_section = ".vector_table.interrupts"] -#[no_mangle] -pub static __INTERRUPTS: [Vector; 7] = [ - Vector { _handler: TIMER0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: TIMER1 }, - Vector { _reserved: 0 }, - Vector { _handler: TIMER2 }, -]; -#[doc = r"Enumeration of all the interrupts."] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Interrupt { - #[doc = "0 - Timer 0 interrupt"] - TIMER0 = 0, - #[doc = "4 - Timer 1 interrupt"] - TIMER1 = 4, - #[doc = "6 - Timer 2 interrupt"] - TIMER2 = 6, -} -unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } -} -#[doc = "32 Timer / Counter, counting up or down from different sources"] -pub struct Timer0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for Timer0 {} -impl Timer0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const timer0::RegisterBlock = 0x4001_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const timer0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for Timer0 { - type Target = timer0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for Timer0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Timer0").finish() - } -} -#[doc = "32 Timer / Counter, counting up or down from different sources"] -pub mod timer0; -#[doc = "32 Timer / Counter, counting up or down from different sources"] -pub struct Timer1 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for Timer1 {} -impl Timer1 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const timer0::RegisterBlock = 0x4001_0100 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const timer0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for Timer1 { - type Target = timer0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for Timer1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Timer1").finish() - } -} -#[doc = "32 Timer / Counter, counting up or down from different sources"] -pub use self::timer0 as timer1; -#[doc = "32 Timer / Counter, counting up or down from different sources"] -pub struct Timer2 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for Timer2 {} -impl Timer2 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const timer0::RegisterBlock = 0x4001_0200 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const timer0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for Timer2 { - type Target = timer0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for Timer2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("Timer2").finish() - } -} -#[doc = "32 Timer / Counter, counting up or down from different sources"] -pub use self::timer0 as timer2; -#[no_mangle] -static mut DEVICE_PERIPHERALS: bool = false; -#[doc = r" All the peripherals."] -#[allow(non_snake_case)] -pub struct Peripherals { - #[doc = "TIMER0"] - pub timer0: Timer0, - #[doc = "TIMER1"] - pub timer1: Timer1, - #[doc = "TIMER2"] - pub timer2: Timer2, -} -impl Peripherals { - #[doc = r" Returns all the peripherals *once*."] - #[cfg(feature = "critical-section")] - #[inline] - pub fn take() -> Option { - critical_section::with(|_| { - if unsafe { DEVICE_PERIPHERALS } { - return None; - } - Some(unsafe { Peripherals::steal() }) - }) - } - #[doc = r" Unchecked version of `Peripherals::take`."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Each of the returned peripherals must be used at most once."] - #[inline] - pub unsafe fn steal() -> Self { - DEVICE_PERIPHERALS = true; - Peripherals { - timer0: Timer0::steal(), - timer1: Timer1::steal(), - timer2: Timer2::steal(), - } - } -} diff --git a/zynq7000/src/timer0.rs b/zynq7000/src/timer0.rs deleted file mode 100644 index 548fbd5..0000000 --- a/zynq7000/src/timer0.rs +++ /dev/null @@ -1,110 +0,0 @@ -#[repr(C)] -#[doc = "Register block"] -pub struct RegisterBlock { - cr: Cr, - sr: Sr, - _reserved2: [u8; 0x0a], - int: Int, - _reserved3: [u8; 0x0e], - count: Count, - match_: Match, - _reserved_5_prescale: [u8; 0x04], - _reserved6: [u8; 0x24], - reload: [Reload; 4], -} -impl RegisterBlock { - #[doc = "0x00 - Control Register"] - #[inline(always)] - pub const fn cr(&self) -> &Cr { - &self.cr - } - #[doc = "0x04 - Status Register"] - #[inline(always)] - pub const fn sr(&self) -> &Sr { - &self.sr - } - #[doc = "0x10 - Interrupt Register"] - #[inline(always)] - pub const fn int(&self) -> &Int { - &self.int - } - #[doc = "0x20 - The Counter Register reflects the actual Value of the Timer/Counter"] - #[inline(always)] - pub const fn count(&self) -> &Count { - &self.count - } - #[doc = "0x24 - The Match Register stores the compare Value for the MATCH condition"] - #[inline(always)] - pub const fn match_(&self) -> &Match { - &self.match_ - } - #[doc = "0x28 - The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value"] - #[inline(always)] - pub const fn prescale_wr(&self) -> &PrescaleWr { - unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } - } - #[doc = "0x28 - The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value"] - #[inline(always)] - pub const fn prescale_rd(&self) -> &PrescaleRd { - unsafe { &*core::ptr::from_ref(self).cast::().add(40).cast() } - } - #[doc = "0x50..0x60 - The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met."] - #[inline(always)] - pub const fn reload(&self, n: usize) -> &Reload { - &self.reload[n] - } - #[doc = "Iterator for array of:"] - #[doc = "0x50..0x60 - The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met."] - #[inline(always)] - pub fn reload_iter(&self) -> impl Iterator { - self.reload.iter() - } -} -#[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] -module"] -#[doc(alias = "CR")] -pub type Cr = crate::Reg; -#[doc = "Control Register"] -pub mod cr; -#[doc = "SR (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] -module"] -#[doc(alias = "SR")] -pub type Sr = crate::Reg; -#[doc = "Status Register"] -pub mod sr; -#[doc = "INT (rw) register accessor: Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int`] -module"] -#[doc(alias = "INT")] -pub type Int = crate::Reg; -#[doc = "Interrupt Register"] -pub mod int; -#[doc = "COUNT (rw) register accessor: The Counter Register reflects the actual Value of the Timer/Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@count`] -module"] -#[doc(alias = "COUNT")] -pub type Count = crate::Reg; -#[doc = "The Counter Register reflects the actual Value of the Timer/Counter"] -pub mod count; -#[doc = "MATCH (rw) register accessor: The Match Register stores the compare Value for the MATCH condition\n\nYou can [`read`](crate::Reg::read) this register and get [`match_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@match_`] -module"] -#[doc(alias = "MATCH")] -pub type Match = crate::Reg; -#[doc = "The Match Register stores the compare Value for the MATCH condition"] -pub mod match_; -#[doc = "PRESCALE_RD (r) register accessor: The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value\n\nYou can [`read`](crate::Reg::read) this register and get [`prescale_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prescale_rd`] -module"] -#[doc(alias = "PRESCALE_RD")] -pub type PrescaleRd = crate::Reg; -#[doc = "The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value"] -pub mod prescale_rd; -#[doc = "PRESCALE_WR (w) register accessor: The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prescale_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prescale_wr`] -module"] -#[doc(alias = "PRESCALE_WR")] -pub type PrescaleWr = crate::Reg; -#[doc = "The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value"] -pub mod prescale_wr; -#[doc = "RELOAD (rw) register accessor: The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reload`] -module"] -#[doc(alias = "RELOAD")] -pub type Reload = crate::Reg; -#[doc = "The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met."] -pub mod reload; diff --git a/zynq7000/src/timer0/count.rs b/zynq7000/src/timer0/count.rs deleted file mode 100644 index bfac5e8..0000000 --- a/zynq7000/src/timer0/count.rs +++ /dev/null @@ -1,28 +0,0 @@ -#[doc = "Register `COUNT` reader"] -pub type R = crate::R; -#[doc = "Register `COUNT` writer"] -pub type W = crate::W; -#[cfg(feature = "debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl W {} -#[doc = "The Counter Register reflects the actual Value of the Timer/Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CountSpec; -impl crate::RegisterSpec for CountSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`count::R`](R) reader structure"] -impl crate::Readable for CountSpec {} -#[doc = "`write(|w| ..)` method takes [`count::W`](W) writer structure"] -impl crate::Writable for CountSpec { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets COUNT to value 0"] -impl crate::Resettable for CountSpec { - const RESET_VALUE: u32 = 0; -} diff --git a/zynq7000/src/timer0/cr.rs b/zynq7000/src/timer0/cr.rs deleted file mode 100644 index 03f7b15..0000000 --- a/zynq7000/src/timer0/cr.rs +++ /dev/null @@ -1,1225 +0,0 @@ -#[doc = "Register `CR` reader"] -pub type R = crate::R; -#[doc = "Register `CR` writer"] -pub type W = crate::W; -#[doc = "Enable\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum En { - #[doc = "0: Timer is disabled and does not operate"] - Disable = 0, - #[doc = "1: Timer is enabled and can operate"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EN` reader - Enable"] -pub type EnR = crate::BitReader; -impl EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> En { - match self.bits { - false => En::Disable, - true => En::Enable, - } - } - #[doc = "Timer is disabled and does not operate"] - #[inline(always)] - pub fn is_disable(&self) -> bool { - *self == En::Disable - } - #[doc = "Timer is enabled and can operate"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == En::Enable - } -} -#[doc = "Field `EN` writer - Enable"] -pub type EnW<'a, REG> = crate::BitWriter<'a, REG, En>; -impl<'a, REG> EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Timer is disabled and does not operate"] - #[inline(always)] - pub fn disable(self) -> &'a mut crate::W { - self.variant(En::Disable) - } - #[doc = "Timer is enabled and can operate"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(En::Enable) - } -} -#[doc = "Reset Timer\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rst { - #[doc = "0: Write as ZERO if necessary"] - NoAction = 0, - #[doc = "1: Reset the Timer"] - ResetTimer = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RST` writer - Reset Timer"] -pub type RstW<'a, REG> = crate::BitWriter<'a, REG, Rst>; -impl<'a, REG> RstW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Write as ZERO if necessary"] - #[inline(always)] - pub fn no_action(self) -> &'a mut crate::W { - self.variant(Rst::NoAction) - } - #[doc = "Reset the Timer"] - #[inline(always)] - pub fn reset_timer(self) -> &'a mut crate::W { - self.variant(Rst::ResetTimer) - } -} -#[doc = "Counting direction\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cnt { - #[doc = "0: Timer Counts UO and wraps, if no STOP condition is set"] - CountUp = 0, - #[doc = "1: Timer Counts DOWN and wraps, if no STOP condition is set"] - CountDown = 1, - #[doc = "2: Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set"] - Toggle = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cnt) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cnt { - type Ux = u8; -} -impl crate::IsEnum for Cnt {} -#[doc = "Field `CNT` reader - Counting direction"] -pub type CntR = crate::FieldReader; -impl CntR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cnt::CountUp), - 1 => Some(Cnt::CountDown), - 2 => Some(Cnt::Toggle), - _ => None, - } - } - #[doc = "Timer Counts UO and wraps, if no STOP condition is set"] - #[inline(always)] - pub fn is_count_up(&self) -> bool { - *self == Cnt::CountUp - } - #[doc = "Timer Counts DOWN and wraps, if no STOP condition is set"] - #[inline(always)] - pub fn is_count_down(&self) -> bool { - *self == Cnt::CountDown - } - #[doc = "Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set"] - #[inline(always)] - pub fn is_toggle(&self) -> bool { - *self == Cnt::Toggle - } -} -#[doc = "Field `CNT` writer - Counting direction"] -pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cnt>; -impl<'a, REG> CntW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Timer Counts UO and wraps, if no STOP condition is set"] - #[inline(always)] - pub fn count_up(self) -> &'a mut crate::W { - self.variant(Cnt::CountUp) - } - #[doc = "Timer Counts DOWN and wraps, if no STOP condition is set"] - #[inline(always)] - pub fn count_down(self) -> &'a mut crate::W { - self.variant(Cnt::CountDown) - } - #[doc = "Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set"] - #[inline(always)] - pub fn toggle(self) -> &'a mut crate::W { - self.variant(Cnt::Toggle) - } -} -#[doc = "Operation Mode\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mode { - #[doc = "0: Timer runs continously"] - Continous = 0, - #[doc = "1: Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops"] - SingleZeroMax = 1, - #[doc = "2: Timer counts to the Value of MATCH Register and stops"] - SingleMatch = 2, - #[doc = "3: Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues"] - ReloadZeroMax = 3, - #[doc = "4: Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues"] - ReloadMatch = 4, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mode { - type Ux = u8; -} -impl crate::IsEnum for Mode {} -#[doc = "Field `MODE` reader - Operation Mode"] -pub type ModeR = crate::FieldReader; -impl ModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mode::Continous), - 1 => Some(Mode::SingleZeroMax), - 2 => Some(Mode::SingleMatch), - 3 => Some(Mode::ReloadZeroMax), - 4 => Some(Mode::ReloadMatch), - _ => None, - } - } - #[doc = "Timer runs continously"] - #[inline(always)] - pub fn is_continous(&self) -> bool { - *self == Mode::Continous - } - #[doc = "Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops"] - #[inline(always)] - pub fn is_single_zero_max(&self) -> bool { - *self == Mode::SingleZeroMax - } - #[doc = "Timer counts to the Value of MATCH Register and stops"] - #[inline(always)] - pub fn is_single_match(&self) -> bool { - *self == Mode::SingleMatch - } - #[doc = "Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues"] - #[inline(always)] - pub fn is_reload_zero_max(&self) -> bool { - *self == Mode::ReloadZeroMax - } - #[doc = "Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues"] - #[inline(always)] - pub fn is_reload_match(&self) -> bool { - *self == Mode::ReloadMatch - } -} -#[doc = "Field `MODE` writer - Operation Mode"] -pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mode>; -impl<'a, REG> ModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Timer runs continously"] - #[inline(always)] - pub fn continous(self) -> &'a mut crate::W { - self.variant(Mode::Continous) - } - #[doc = "Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops"] - #[inline(always)] - pub fn single_zero_max(self) -> &'a mut crate::W { - self.variant(Mode::SingleZeroMax) - } - #[doc = "Timer counts to the Value of MATCH Register and stops"] - #[inline(always)] - pub fn single_match(self) -> &'a mut crate::W { - self.variant(Mode::SingleMatch) - } - #[doc = "Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues"] - #[inline(always)] - pub fn reload_zero_max(self) -> &'a mut crate::W { - self.variant(Mode::ReloadZeroMax) - } - #[doc = "Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues"] - #[inline(always)] - pub fn reload_match(self) -> &'a mut crate::W { - self.variant(Mode::ReloadMatch) - } -} -#[doc = "Use Prescaler\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Psc { - #[doc = "0: Prescaler is not used"] - Disabled = 0, - #[doc = "1: Prescaler is used as divider"] - Enabled = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Psc) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `PSC` reader - Use Prescaler"] -pub type PscR = crate::BitReader; -impl PscR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Psc { - match self.bits { - false => Psc::Disabled, - true => Psc::Enabled, - } - } - #[doc = "Prescaler is not used"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == Psc::Disabled - } - #[doc = "Prescaler is used as divider"] - #[inline(always)] - pub fn is_enabled(&self) -> bool { - *self == Psc::Enabled - } -} -#[doc = "Field `PSC` writer - Use Prescaler"] -pub type PscW<'a, REG> = crate::BitWriter<'a, REG, Psc>; -impl<'a, REG> PscW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Prescaler is not used"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(Psc::Disabled) - } - #[doc = "Prescaler is used as divider"] - #[inline(always)] - pub fn enabled(self) -> &'a mut crate::W { - self.variant(Psc::Enabled) - } -} -#[doc = "Timer / Counter Source Divider\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Cntsrc { - #[doc = "0: Capture Source is used directly"] - CapSrc = 0, - #[doc = "1: Capture Source is divided by 2"] - CapSrcDiv2 = 1, - #[doc = "2: Capture Source is divided by 4"] - CapSrcDiv4 = 2, - #[doc = "3: Capture Source is divided by 8"] - CapSrcDiv8 = 3, - #[doc = "4: Capture Source is divided by 16"] - CapSrcDiv16 = 4, - #[doc = "5: Capture Source is divided by 32"] - CapSrcDiv32 = 5, - #[doc = "6: Capture Source is divided by 64"] - CapSrcDiv64 = 6, - #[doc = "7: Capture Source is divided by 128"] - CapSrcDiv128 = 7, - #[doc = "8: Capture Source is divided by 256"] - CapSrcDiv256 = 8, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Cntsrc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Cntsrc { - type Ux = u8; -} -impl crate::IsEnum for Cntsrc {} -#[doc = "Field `CNTSRC` reader - Timer / Counter Source Divider"] -pub type CntsrcR = crate::FieldReader; -impl CntsrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Cntsrc::CapSrc), - 1 => Some(Cntsrc::CapSrcDiv2), - 2 => Some(Cntsrc::CapSrcDiv4), - 3 => Some(Cntsrc::CapSrcDiv8), - 4 => Some(Cntsrc::CapSrcDiv16), - 5 => Some(Cntsrc::CapSrcDiv32), - 6 => Some(Cntsrc::CapSrcDiv64), - 7 => Some(Cntsrc::CapSrcDiv128), - 8 => Some(Cntsrc::CapSrcDiv256), - _ => None, - } - } - #[doc = "Capture Source is used directly"] - #[inline(always)] - pub fn is_cap_src(&self) -> bool { - *self == Cntsrc::CapSrc - } - #[doc = "Capture Source is divided by 2"] - #[inline(always)] - pub fn is_cap_src_div2(&self) -> bool { - *self == Cntsrc::CapSrcDiv2 - } - #[doc = "Capture Source is divided by 4"] - #[inline(always)] - pub fn is_cap_src_div4(&self) -> bool { - *self == Cntsrc::CapSrcDiv4 - } - #[doc = "Capture Source is divided by 8"] - #[inline(always)] - pub fn is_cap_src_div8(&self) -> bool { - *self == Cntsrc::CapSrcDiv8 - } - #[doc = "Capture Source is divided by 16"] - #[inline(always)] - pub fn is_cap_src_div16(&self) -> bool { - *self == Cntsrc::CapSrcDiv16 - } - #[doc = "Capture Source is divided by 32"] - #[inline(always)] - pub fn is_cap_src_div32(&self) -> bool { - *self == Cntsrc::CapSrcDiv32 - } - #[doc = "Capture Source is divided by 64"] - #[inline(always)] - pub fn is_cap_src_div64(&self) -> bool { - *self == Cntsrc::CapSrcDiv64 - } - #[doc = "Capture Source is divided by 128"] - #[inline(always)] - pub fn is_cap_src_div128(&self) -> bool { - *self == Cntsrc::CapSrcDiv128 - } - #[doc = "Capture Source is divided by 256"] - #[inline(always)] - pub fn is_cap_src_div256(&self) -> bool { - *self == Cntsrc::CapSrcDiv256 - } -} -#[doc = "Field `CNTSRC` writer - Timer / Counter Source Divider"] -pub type CntsrcW<'a, REG> = crate::FieldWriter<'a, REG, 4, Cntsrc>; -impl<'a, REG> CntsrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Capture Source is used directly"] - #[inline(always)] - pub fn cap_src(self) -> &'a mut crate::W { - self.variant(Cntsrc::CapSrc) - } - #[doc = "Capture Source is divided by 2"] - #[inline(always)] - pub fn cap_src_div2(self) -> &'a mut crate::W { - self.variant(Cntsrc::CapSrcDiv2) - } - #[doc = "Capture Source is divided by 4"] - #[inline(always)] - pub fn cap_src_div4(self) -> &'a mut crate::W { - self.variant(Cntsrc::CapSrcDiv4) - } - #[doc = "Capture Source is divided by 8"] - #[inline(always)] - pub fn cap_src_div8(self) -> &'a mut crate::W { - self.variant(Cntsrc::CapSrcDiv8) - } - #[doc = "Capture Source is divided by 16"] - #[inline(always)] - pub fn cap_src_div16(self) -> &'a mut crate::W { - self.variant(Cntsrc::CapSrcDiv16) - } - #[doc = "Capture Source is divided by 32"] - #[inline(always)] - pub fn cap_src_div32(self) -> &'a mut crate::W { - self.variant(Cntsrc::CapSrcDiv32) - } - #[doc = "Capture Source is divided by 64"] - #[inline(always)] - pub fn cap_src_div64(self) -> &'a mut crate::W { - self.variant(Cntsrc::CapSrcDiv64) - } - #[doc = "Capture Source is divided by 128"] - #[inline(always)] - pub fn cap_src_div128(self) -> &'a mut crate::W { - self.variant(Cntsrc::CapSrcDiv128) - } - #[doc = "Capture Source is divided by 256"] - #[inline(always)] - pub fn cap_src_div256(self) -> &'a mut crate::W { - self.variant(Cntsrc::CapSrcDiv256) - } -} -#[doc = "Timer / Counter Capture Source\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Capsrc { - #[doc = "0: Core Clock"] - Cclk = 0, - #[doc = "1: GPIO A, PIN 0"] - Gpioa0 = 1, - #[doc = "2: GPIO A, PIN 1"] - Gpioa1 = 2, - #[doc = "3: GPIO A, PIN 2"] - Gpioa2 = 3, - #[doc = "4: GPIO A, PIN 3"] - Gpioa3 = 4, - #[doc = "5: GPIO A, PIN 4"] - Gpioa4 = 5, - #[doc = "6: GPIO A, PIN 5"] - Gpioa5 = 6, - #[doc = "7: GPIO A, PIN 6"] - Gpioa6 = 7, - #[doc = "8: GPIO A, PIN 7"] - Gpioa7 = 8, - #[doc = "9: GPIO B, PIN 0"] - Gpiob0 = 9, - #[doc = "10: GPIO B, PIN 1"] - Gpiob1 = 10, - #[doc = "11: GPIO B, PIN 2"] - Gpiob2 = 11, - #[doc = "12: GPIO B, PIN 3"] - Gpiob3 = 12, - #[doc = "13: GPIO C, PIN 0"] - Gpioc0 = 13, - #[doc = "14: GPIO C, PIN 1"] - Gpioc5 = 14, - #[doc = "15: GPIO C, PIN 2"] - Gpioc6 = 15, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Capsrc) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Capsrc { - type Ux = u8; -} -impl crate::IsEnum for Capsrc {} -#[doc = "Field `CAPSRC` reader - Timer / Counter Capture Source"] -pub type CapsrcR = crate::FieldReader; -impl CapsrcR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Capsrc { - match self.bits { - 0 => Capsrc::Cclk, - 1 => Capsrc::Gpioa0, - 2 => Capsrc::Gpioa1, - 3 => Capsrc::Gpioa2, - 4 => Capsrc::Gpioa3, - 5 => Capsrc::Gpioa4, - 6 => Capsrc::Gpioa5, - 7 => Capsrc::Gpioa6, - 8 => Capsrc::Gpioa7, - 9 => Capsrc::Gpiob0, - 10 => Capsrc::Gpiob1, - 11 => Capsrc::Gpiob2, - 12 => Capsrc::Gpiob3, - 13 => Capsrc::Gpioc0, - 14 => Capsrc::Gpioc5, - 15 => Capsrc::Gpioc6, - _ => unreachable!(), - } - } - #[doc = "Core Clock"] - #[inline(always)] - pub fn is_cclk(&self) -> bool { - *self == Capsrc::Cclk - } - #[doc = "GPIO A, PIN 0"] - #[inline(always)] - pub fn is_gpioa_0(&self) -> bool { - *self == Capsrc::Gpioa0 - } - #[doc = "GPIO A, PIN 1"] - #[inline(always)] - pub fn is_gpioa_1(&self) -> bool { - *self == Capsrc::Gpioa1 - } - #[doc = "GPIO A, PIN 2"] - #[inline(always)] - pub fn is_gpioa_2(&self) -> bool { - *self == Capsrc::Gpioa2 - } - #[doc = "GPIO A, PIN 3"] - #[inline(always)] - pub fn is_gpioa_3(&self) -> bool { - *self == Capsrc::Gpioa3 - } - #[doc = "GPIO A, PIN 4"] - #[inline(always)] - pub fn is_gpioa_4(&self) -> bool { - *self == Capsrc::Gpioa4 - } - #[doc = "GPIO A, PIN 5"] - #[inline(always)] - pub fn is_gpioa_5(&self) -> bool { - *self == Capsrc::Gpioa5 - } - #[doc = "GPIO A, PIN 6"] - #[inline(always)] - pub fn is_gpioa_6(&self) -> bool { - *self == Capsrc::Gpioa6 - } - #[doc = "GPIO A, PIN 7"] - #[inline(always)] - pub fn is_gpioa_7(&self) -> bool { - *self == Capsrc::Gpioa7 - } - #[doc = "GPIO B, PIN 0"] - #[inline(always)] - pub fn is_gpiob_0(&self) -> bool { - *self == Capsrc::Gpiob0 - } - #[doc = "GPIO B, PIN 1"] - #[inline(always)] - pub fn is_gpiob_1(&self) -> bool { - *self == Capsrc::Gpiob1 - } - #[doc = "GPIO B, PIN 2"] - #[inline(always)] - pub fn is_gpiob_2(&self) -> bool { - *self == Capsrc::Gpiob2 - } - #[doc = "GPIO B, PIN 3"] - #[inline(always)] - pub fn is_gpiob_3(&self) -> bool { - *self == Capsrc::Gpiob3 - } - #[doc = "GPIO C, PIN 0"] - #[inline(always)] - pub fn is_gpioc_0(&self) -> bool { - *self == Capsrc::Gpioc0 - } - #[doc = "GPIO C, PIN 1"] - #[inline(always)] - pub fn is_gpioc_5(&self) -> bool { - *self == Capsrc::Gpioc5 - } - #[doc = "GPIO C, PIN 2"] - #[inline(always)] - pub fn is_gpioc_6(&self) -> bool { - *self == Capsrc::Gpioc6 - } -} -#[doc = "Field `CAPSRC` writer - Timer / Counter Capture Source"] -pub type CapsrcW<'a, REG> = crate::FieldWriter<'a, REG, 4, Capsrc, crate::Safe>; -impl<'a, REG> CapsrcW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Core Clock"] - #[inline(always)] - pub fn cclk(self) -> &'a mut crate::W { - self.variant(Capsrc::Cclk) - } - #[doc = "GPIO A, PIN 0"] - #[inline(always)] - pub fn gpioa_0(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioa0) - } - #[doc = "GPIO A, PIN 1"] - #[inline(always)] - pub fn gpioa_1(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioa1) - } - #[doc = "GPIO A, PIN 2"] - #[inline(always)] - pub fn gpioa_2(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioa2) - } - #[doc = "GPIO A, PIN 3"] - #[inline(always)] - pub fn gpioa_3(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioa3) - } - #[doc = "GPIO A, PIN 4"] - #[inline(always)] - pub fn gpioa_4(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioa4) - } - #[doc = "GPIO A, PIN 5"] - #[inline(always)] - pub fn gpioa_5(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioa5) - } - #[doc = "GPIO A, PIN 6"] - #[inline(always)] - pub fn gpioa_6(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioa6) - } - #[doc = "GPIO A, PIN 7"] - #[inline(always)] - pub fn gpioa_7(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioa7) - } - #[doc = "GPIO B, PIN 0"] - #[inline(always)] - pub fn gpiob_0(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpiob0) - } - #[doc = "GPIO B, PIN 1"] - #[inline(always)] - pub fn gpiob_1(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpiob1) - } - #[doc = "GPIO B, PIN 2"] - #[inline(always)] - pub fn gpiob_2(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpiob2) - } - #[doc = "GPIO B, PIN 3"] - #[inline(always)] - pub fn gpiob_3(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpiob3) - } - #[doc = "GPIO C, PIN 0"] - #[inline(always)] - pub fn gpioc_0(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioc0) - } - #[doc = "GPIO C, PIN 1"] - #[inline(always)] - pub fn gpioc_5(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioc5) - } - #[doc = "GPIO C, PIN 2"] - #[inline(always)] - pub fn gpioc_6(self) -> &'a mut crate::W { - self.variant(Capsrc::Gpioc6) - } -} -#[doc = "Capture Edge, select which Edge should result in a counter increment or decrement\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Capedge { - #[doc = "0: Only rising edges result in a counter increment or decrement"] - Rising = 0, - #[doc = "1: Only falling edges result in a counter increment or decrement"] - Falling = 1, - #[doc = "2: Rising and falling edges result in a counter increment or decrement"] - Both = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Capedge) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Capedge { - type Ux = u8; -} -impl crate::IsEnum for Capedge {} -#[doc = "Field `CAPEDGE` reader - Capture Edge, select which Edge should result in a counter increment or decrement"] -pub type CapedgeR = crate::FieldReader; -impl CapedgeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Capedge::Rising), - 1 => Some(Capedge::Falling), - 2 => Some(Capedge::Both), - _ => None, - } - } - #[doc = "Only rising edges result in a counter increment or decrement"] - #[inline(always)] - pub fn is_rising(&self) -> bool { - *self == Capedge::Rising - } - #[doc = "Only falling edges result in a counter increment or decrement"] - #[inline(always)] - pub fn is_falling(&self) -> bool { - *self == Capedge::Falling - } - #[doc = "Rising and falling edges result in a counter increment or decrement"] - #[inline(always)] - pub fn is_both(&self) -> bool { - *self == Capedge::Both - } -} -#[doc = "Field `CAPEDGE` writer - Capture Edge, select which Edge should result in a counter increment or decrement"] -pub type CapedgeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Capedge>; -impl<'a, REG> CapedgeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Only rising edges result in a counter increment or decrement"] - #[inline(always)] - pub fn rising(self) -> &'a mut crate::W { - self.variant(Capedge::Rising) - } - #[doc = "Only falling edges result in a counter increment or decrement"] - #[inline(always)] - pub fn falling(self) -> &'a mut crate::W { - self.variant(Capedge::Falling) - } - #[doc = "Rising and falling edges result in a counter increment or decrement"] - #[inline(always)] - pub fn both(self) -> &'a mut crate::W { - self.variant(Capedge::Both) - } -} -#[doc = "Triggers an other Peripheral\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Trgext { - #[doc = "0: No Trigger is emitted"] - None = 0, - #[doc = "1: DMA Controller 1 is triggered, dependant on MODE"] - Dma1 = 1, - #[doc = "2: DMA Controller 2 is triggered, dependant on MODE"] - Dma2 = 2, - #[doc = "3: UART is triggered, dependant on MODE"] - Uart = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Trgext) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Trgext { - type Ux = u8; -} -impl crate::IsEnum for Trgext {} -#[doc = "Field `TRGEXT` reader - Triggers an other Peripheral"] -pub type TrgextR = crate::FieldReader; -impl TrgextR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Trgext { - match self.bits { - 0 => Trgext::None, - 1 => Trgext::Dma1, - 2 => Trgext::Dma2, - 3 => Trgext::Uart, - _ => unreachable!(), - } - } - #[doc = "No Trigger is emitted"] - #[inline(always)] - pub fn is_none(&self) -> bool { - *self == Trgext::None - } - #[doc = "DMA Controller 1 is triggered, dependant on MODE"] - #[inline(always)] - pub fn is_dma1(&self) -> bool { - *self == Trgext::Dma1 - } - #[doc = "DMA Controller 2 is triggered, dependant on MODE"] - #[inline(always)] - pub fn is_dma2(&self) -> bool { - *self == Trgext::Dma2 - } - #[doc = "UART is triggered, dependant on MODE"] - #[inline(always)] - pub fn is_uart(&self) -> bool { - *self == Trgext::Uart - } -} -#[doc = "Field `TRGEXT` writer - Triggers an other Peripheral"] -pub type TrgextW<'a, REG> = crate::FieldWriter<'a, REG, 2, Trgext, crate::Safe>; -impl<'a, REG> TrgextW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "No Trigger is emitted"] - #[inline(always)] - pub fn none(self) -> &'a mut crate::W { - self.variant(Trgext::None) - } - #[doc = "DMA Controller 1 is triggered, dependant on MODE"] - #[inline(always)] - pub fn dma1(self) -> &'a mut crate::W { - self.variant(Trgext::Dma1) - } - #[doc = "DMA Controller 2 is triggered, dependant on MODE"] - #[inline(always)] - pub fn dma2(self) -> &'a mut crate::W { - self.variant(Trgext::Dma2) - } - #[doc = "UART is triggered, dependant on MODE"] - #[inline(always)] - pub fn uart(self) -> &'a mut crate::W { - self.variant(Trgext::Uart) - } -} -#[doc = "Select RELOAD Register n to reload Timer on condition\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Reload { - #[doc = "0: Selects Reload Register number 0"] - Reload0 = 0, - #[doc = "1: Selects Reload Register number 1"] - Reload1 = 1, - #[doc = "2: Selects Reload Register number 2"] - Reload2 = 2, - #[doc = "3: Selects Reload Register number 3"] - Reload3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Reload) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Reload { - type Ux = u8; -} -impl crate::IsEnum for Reload {} -#[doc = "Field `RELOAD` reader - Select RELOAD Register n to reload Timer on condition"] -pub type ReloadR = crate::FieldReader; -impl ReloadR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reload { - match self.bits { - 0 => Reload::Reload0, - 1 => Reload::Reload1, - 2 => Reload::Reload2, - 3 => Reload::Reload3, - _ => unreachable!(), - } - } - #[doc = "Selects Reload Register number 0"] - #[inline(always)] - pub fn is_reload0(&self) -> bool { - *self == Reload::Reload0 - } - #[doc = "Selects Reload Register number 1"] - #[inline(always)] - pub fn is_reload1(&self) -> bool { - *self == Reload::Reload1 - } - #[doc = "Selects Reload Register number 2"] - #[inline(always)] - pub fn is_reload2(&self) -> bool { - *self == Reload::Reload2 - } - #[doc = "Selects Reload Register number 3"] - #[inline(always)] - pub fn is_reload3(&self) -> bool { - *self == Reload::Reload3 - } -} -#[doc = "Field `RELOAD` writer - Select RELOAD Register n to reload Timer on condition"] -pub type ReloadW<'a, REG> = crate::FieldWriter<'a, REG, 2, Reload, crate::Safe>; -impl<'a, REG> ReloadW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Selects Reload Register number 0"] - #[inline(always)] - pub fn reload0(self) -> &'a mut crate::W { - self.variant(Reload::Reload0) - } - #[doc = "Selects Reload Register number 1"] - #[inline(always)] - pub fn reload1(self) -> &'a mut crate::W { - self.variant(Reload::Reload1) - } - #[doc = "Selects Reload Register number 2"] - #[inline(always)] - pub fn reload2(self) -> &'a mut crate::W { - self.variant(Reload::Reload2) - } - #[doc = "Selects Reload Register number 3"] - #[inline(always)] - pub fn reload3(self) -> &'a mut crate::W { - self.variant(Reload::Reload3) - } -} -#[doc = "Selects, if Reload Register number is incremented, decremented or not modified\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Idr { - #[doc = "0: Reload Register number does not change automatically"] - Keep = 0, - #[doc = "1: Reload Register number is incremented on each match"] - Increment = 1, - #[doc = "2: Reload Register number is decremented on each match"] - Decrement = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Idr) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Idr { - type Ux = u8; -} -impl crate::IsEnum for Idr {} -#[doc = "Field `IDR` reader - Selects, if Reload Register number is incremented, decremented or not modified"] -pub type IdrR = crate::FieldReader; -impl IdrR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Idr::Keep), - 1 => Some(Idr::Increment), - 2 => Some(Idr::Decrement), - _ => None, - } - } - #[doc = "Reload Register number does not change automatically"] - #[inline(always)] - pub fn is_keep(&self) -> bool { - *self == Idr::Keep - } - #[doc = "Reload Register number is incremented on each match"] - #[inline(always)] - pub fn is_increment(&self) -> bool { - *self == Idr::Increment - } - #[doc = "Reload Register number is decremented on each match"] - #[inline(always)] - pub fn is_decrement(&self) -> bool { - *self == Idr::Decrement - } -} -#[doc = "Field `IDR` writer - Selects, if Reload Register number is incremented, decremented or not modified"] -pub type IdrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Idr>; -impl<'a, REG> IdrW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Reload Register number does not change automatically"] - #[inline(always)] - pub fn keep(self) -> &'a mut crate::W { - self.variant(Idr::Keep) - } - #[doc = "Reload Register number is incremented on each match"] - #[inline(always)] - pub fn increment(self) -> &'a mut crate::W { - self.variant(Idr::Increment) - } - #[doc = "Reload Register number is decremented on each match"] - #[inline(always)] - pub fn decrement(self) -> &'a mut crate::W { - self.variant(Idr::Decrement) - } -} -#[doc = "Starts and Stops the Timer / Counter\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum S { - #[doc = "0: Timer / Counter is stopped"] - Stop = 0, - #[doc = "1: Timer / Counter is started"] - Start = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: S) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `S` reader - Starts and Stops the Timer / Counter"] -pub type SR = crate::BitReader; -impl SR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> S { - match self.bits { - false => S::Stop, - true => S::Start, - } - } - #[doc = "Timer / Counter is stopped"] - #[inline(always)] - pub fn is_stop(&self) -> bool { - *self == S::Stop - } - #[doc = "Timer / Counter is started"] - #[inline(always)] - pub fn is_start(&self) -> bool { - *self == S::Start - } -} -#[doc = "Field `S` writer - Starts and Stops the Timer / Counter"] -pub type SW<'a, REG> = crate::BitWriter<'a, REG, S>; -impl<'a, REG> SW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Timer / Counter is stopped"] - #[inline(always)] - pub fn stop(self) -> &'a mut crate::W { - self.variant(S::Stop) - } - #[doc = "Timer / Counter is started"] - #[inline(always)] - pub fn start(self) -> &'a mut crate::W { - self.variant(S::Start) - } -} -impl R { - #[doc = "Bit 0 - Enable"] - #[inline(always)] - pub fn en(&self) -> EnR { - EnR::new((self.bits & 1) != 0) - } - #[doc = "Bits 2:3 - Counting direction"] - #[inline(always)] - pub fn cnt(&self) -> CntR { - CntR::new(((self.bits >> 2) & 3) as u8) - } - #[doc = "Bits 4:6 - Operation Mode"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new(((self.bits >> 4) & 7) as u8) - } - #[doc = "Bit 7 - Use Prescaler"] - #[inline(always)] - pub fn psc(&self) -> PscR { - PscR::new(((self.bits >> 7) & 1) != 0) - } - #[doc = "Bits 8:11 - Timer / Counter Source Divider"] - #[inline(always)] - pub fn cntsrc(&self) -> CntsrcR { - CntsrcR::new(((self.bits >> 8) & 0x0f) as u8) - } - #[doc = "Bits 12:15 - Timer / Counter Capture Source"] - #[inline(always)] - pub fn capsrc(&self) -> CapsrcR { - CapsrcR::new(((self.bits >> 12) & 0x0f) as u8) - } - #[doc = "Bits 16:17 - Capture Edge, select which Edge should result in a counter increment or decrement"] - #[inline(always)] - pub fn capedge(&self) -> CapedgeR { - CapedgeR::new(((self.bits >> 16) & 3) as u8) - } - #[doc = "Bits 20:21 - Triggers an other Peripheral"] - #[inline(always)] - pub fn trgext(&self) -> TrgextR { - TrgextR::new(((self.bits >> 20) & 3) as u8) - } - #[doc = "Bits 24:25 - Select RELOAD Register n to reload Timer on condition"] - #[inline(always)] - pub fn reload(&self) -> ReloadR { - ReloadR::new(((self.bits >> 24) & 3) as u8) - } - #[doc = "Bits 26:27 - Selects, if Reload Register number is incremented, decremented or not modified"] - #[inline(always)] - pub fn idr(&self) -> IdrR { - IdrR::new(((self.bits >> 26) & 3) as u8) - } - #[doc = "Bit 31 - Starts and Stops the Timer / Counter"] - #[inline(always)] - pub fn s(&self) -> SR { - SR::new(((self.bits >> 31) & 1) != 0) - } -} -impl W { - #[doc = "Bit 0 - Enable"] - #[inline(always)] - pub fn en(&mut self) -> EnW { - EnW::new(self, 0) - } - #[doc = "Bit 1 - Reset Timer"] - #[inline(always)] - pub fn rst(&mut self) -> RstW { - RstW::new(self, 1) - } - #[doc = "Bits 2:3 - Counting direction"] - #[inline(always)] - pub fn cnt(&mut self) -> CntW { - CntW::new(self, 2) - } - #[doc = "Bits 4:6 - Operation Mode"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 4) - } - #[doc = "Bit 7 - Use Prescaler"] - #[inline(always)] - pub fn psc(&mut self) -> PscW { - PscW::new(self, 7) - } - #[doc = "Bits 8:11 - Timer / Counter Source Divider"] - #[inline(always)] - pub fn cntsrc(&mut self) -> CntsrcW { - CntsrcW::new(self, 8) - } - #[doc = "Bits 12:15 - Timer / Counter Capture Source"] - #[inline(always)] - pub fn capsrc(&mut self) -> CapsrcW { - CapsrcW::new(self, 12) - } - #[doc = "Bits 16:17 - Capture Edge, select which Edge should result in a counter increment or decrement"] - #[inline(always)] - pub fn capedge(&mut self) -> CapedgeW { - CapedgeW::new(self, 16) - } - #[doc = "Bits 20:21 - Triggers an other Peripheral"] - #[inline(always)] - pub fn trgext(&mut self) -> TrgextW { - TrgextW::new(self, 20) - } - #[doc = "Bits 24:25 - Select RELOAD Register n to reload Timer on condition"] - #[inline(always)] - pub fn reload(&mut self) -> ReloadW { - ReloadW::new(self, 24) - } - #[doc = "Bits 26:27 - Selects, if Reload Register number is incremented, decremented or not modified"] - #[inline(always)] - pub fn idr(&mut self) -> IdrW { - IdrW::new(self, 26) - } - #[doc = "Bit 31 - Starts and Stops the Timer / Counter"] - #[inline(always)] - pub fn s(&mut self) -> SW { - SW::new(self, 31) - } -} -#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct CrSpec; -impl crate::RegisterSpec for CrSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`cr::R`](R) reader structure"] -impl crate::Readable for CrSpec {} -#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] -impl crate::Writable for CrSpec { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets CR to value 0"] -impl crate::Resettable for CrSpec { - const RESET_VALUE: u32 = 0; -} diff --git a/zynq7000/src/timer0/int.rs b/zynq7000/src/timer0/int.rs deleted file mode 100644 index 8310e3a..0000000 --- a/zynq7000/src/timer0/int.rs +++ /dev/null @@ -1,173 +0,0 @@ -#[doc = "Register `INT` reader"] -pub type R = crate::R; -#[doc = "Register `INT` writer"] -pub type W = crate::W; -#[doc = "Interrupt Enable\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum En { - #[doc = "0: Timer does not generate Interrupts"] - Disabled = 0, - #[doc = "1: Timer triggers the TIMERn Interrupt"] - Enable = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: En) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `EN` reader - Interrupt Enable"] -pub type EnR = crate::BitReader; -impl EnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> En { - match self.bits { - false => En::Disabled, - true => En::Enable, - } - } - #[doc = "Timer does not generate Interrupts"] - #[inline(always)] - pub fn is_disabled(&self) -> bool { - *self == En::Disabled - } - #[doc = "Timer triggers the TIMERn Interrupt"] - #[inline(always)] - pub fn is_enable(&self) -> bool { - *self == En::Enable - } -} -#[doc = "Field `EN` writer - Interrupt Enable"] -pub type EnW<'a, REG> = crate::BitWriter<'a, REG, En>; -impl<'a, REG> EnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "Timer does not generate Interrupts"] - #[inline(always)] - pub fn disabled(self) -> &'a mut crate::W { - self.variant(En::Disabled) - } - #[doc = "Timer triggers the TIMERn Interrupt"] - #[inline(always)] - pub fn enable(self) -> &'a mut crate::W { - self.variant(En::Enable) - } -} -#[doc = "Interrupt Mode, selects on which condition the Timer should generate an Interrupt\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Mode { - #[doc = "0: Timer generates an Interrupt when the MATCH condition is hit"] - Match = 0, - #[doc = "1: Timer generates an Interrupt when it underflows"] - Underflow = 1, - #[doc = "2: Timer generates an Interrupt when it overflows"] - Overflow = 2, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Mode) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Mode { - type Ux = u8; -} -impl crate::IsEnum for Mode {} -#[doc = "Field `MODE` reader - Interrupt Mode, selects on which condition the Timer should generate an Interrupt"] -pub type ModeR = crate::FieldReader; -impl ModeR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Option { - match self.bits { - 0 => Some(Mode::Match), - 1 => Some(Mode::Underflow), - 2 => Some(Mode::Overflow), - _ => None, - } - } - #[doc = "Timer generates an Interrupt when the MATCH condition is hit"] - #[inline(always)] - pub fn is_match(&self) -> bool { - *self == Mode::Match - } - #[doc = "Timer generates an Interrupt when it underflows"] - #[inline(always)] - pub fn is_underflow(&self) -> bool { - *self == Mode::Underflow - } - #[doc = "Timer generates an Interrupt when it overflows"] - #[inline(always)] - pub fn is_overflow(&self) -> bool { - *self == Mode::Overflow - } -} -#[doc = "Field `MODE` writer - Interrupt Mode, selects on which condition the Timer should generate an Interrupt"] -pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mode>; -impl<'a, REG> ModeW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, - REG::Ux: From, -{ - #[doc = "Timer generates an Interrupt when the MATCH condition is hit"] - #[inline(always)] - pub fn match_(self) -> &'a mut crate::W { - self.variant(Mode::Match) - } - #[doc = "Timer generates an Interrupt when it underflows"] - #[inline(always)] - pub fn underflow(self) -> &'a mut crate::W { - self.variant(Mode::Underflow) - } - #[doc = "Timer generates an Interrupt when it overflows"] - #[inline(always)] - pub fn overflow(self) -> &'a mut crate::W { - self.variant(Mode::Overflow) - } -} -impl R { - #[doc = "Bit 0 - Interrupt Enable"] - #[inline(always)] - pub fn en(&self) -> EnR { - EnR::new((self.bits & 1) != 0) - } - #[doc = "Bits 4:6 - Interrupt Mode, selects on which condition the Timer should generate an Interrupt"] - #[inline(always)] - pub fn mode(&self) -> ModeR { - ModeR::new(((self.bits >> 4) & 7) as u8) - } -} -impl W { - #[doc = "Bit 0 - Interrupt Enable"] - #[inline(always)] - pub fn en(&mut self) -> EnW { - EnW::new(self, 0) - } - #[doc = "Bits 4:6 - Interrupt Mode, selects on which condition the Timer should generate an Interrupt"] - #[inline(always)] - pub fn mode(&mut self) -> ModeW { - ModeW::new(self, 4) - } -} -#[doc = "Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct IntSpec; -impl crate::RegisterSpec for IntSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`int::R`](R) reader structure"] -impl crate::Readable for IntSpec {} -#[doc = "`write(|w| ..)` method takes [`int::W`](W) writer structure"] -impl crate::Writable for IntSpec { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; -} -#[doc = "`reset()` method sets INT to value 0"] -impl crate::Resettable for IntSpec { - const RESET_VALUE: u16 = 0; -} diff --git a/zynq7000/src/timer0/match_.rs b/zynq7000/src/timer0/match_.rs deleted file mode 100644 index 5229f94..0000000 --- a/zynq7000/src/timer0/match_.rs +++ /dev/null @@ -1,28 +0,0 @@ -#[doc = "Register `MATCH` reader"] -pub type R = crate::R; -#[doc = "Register `MATCH` writer"] -pub type W = crate::W; -#[cfg(feature = "debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl W {} -#[doc = "The Match Register stores the compare Value for the MATCH condition\n\nYou can [`read`](crate::Reg::read) this register and get [`match_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct MatchSpec; -impl crate::RegisterSpec for MatchSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`match_::R`](R) reader structure"] -impl crate::Readable for MatchSpec {} -#[doc = "`write(|w| ..)` method takes [`match_::W`](W) writer structure"] -impl crate::Writable for MatchSpec { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets MATCH to value 0"] -impl crate::Resettable for MatchSpec { - const RESET_VALUE: u32 = 0; -} diff --git a/zynq7000/src/timer0/prescale_rd.rs b/zynq7000/src/timer0/prescale_rd.rs deleted file mode 100644 index ac52cf4..0000000 --- a/zynq7000/src/timer0/prescale_rd.rs +++ /dev/null @@ -1,19 +0,0 @@ -#[doc = "Register `PRESCALE_RD` reader"] -pub type R = crate::R; -#[cfg(feature = "debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -#[doc = "The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value\n\nYou can [`read`](crate::Reg::read) this register and get [`prescale_rd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PrescaleRdSpec; -impl crate::RegisterSpec for PrescaleRdSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`prescale_rd::R`](R) reader structure"] -impl crate::Readable for PrescaleRdSpec {} -#[doc = "`reset()` method sets PRESCALE_RD to value 0"] -impl crate::Resettable for PrescaleRdSpec { - const RESET_VALUE: u32 = 0; -} diff --git a/zynq7000/src/timer0/prescale_wr.rs b/zynq7000/src/timer0/prescale_wr.rs deleted file mode 100644 index 1c284ff..0000000 --- a/zynq7000/src/timer0/prescale_wr.rs +++ /dev/null @@ -1,24 +0,0 @@ -#[doc = "Register `PRESCALE_WR` writer"] -pub type W = crate::W; -#[cfg(feature = "debug")] -impl core::fmt::Debug for crate::generic::Reg { - fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { - write!(f, "(not readable)") - } -} -impl W {} -#[doc = "The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prescale_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PrescaleWrSpec; -impl crate::RegisterSpec for PrescaleWrSpec { - type Ux = u32; -} -#[doc = "`write(|w| ..)` method takes [`prescale_wr::W`](W) writer structure"] -impl crate::Writable for PrescaleWrSpec { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets PRESCALE_WR to value 0"] -impl crate::Resettable for PrescaleWrSpec { - const RESET_VALUE: u32 = 0; -} diff --git a/zynq7000/src/timer0/reload.rs b/zynq7000/src/timer0/reload.rs deleted file mode 100644 index 7f35638..0000000 --- a/zynq7000/src/timer0/reload.rs +++ /dev/null @@ -1,29 +0,0 @@ -#[doc = "Register `RELOAD[%s]` reader"] -pub type R = crate::R; -#[doc = "Register `RELOAD[%s]` writer"] -pub type W = crate::W; -#[cfg(feature = "debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - write!(f, "{}", self.bits()) - } -} -impl W {} -#[doc = "The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct ReloadSpec; -impl crate::RegisterSpec for ReloadSpec { - type Ux = u32; -} -#[doc = "`read()` method returns [`reload::R`](R) reader structure"] -impl crate::Readable for ReloadSpec {} -#[doc = "`write(|w| ..)` method takes [`reload::W`](W) writer structure"] -impl crate::Writable for ReloadSpec { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; -} -#[doc = "`reset()` method sets RELOAD[%s] -to value 0"] -impl crate::Resettable for ReloadSpec { - const RESET_VALUE: u32 = 0; -} diff --git a/zynq7000/src/timer0/sr.rs b/zynq7000/src/timer0/sr.rs deleted file mode 100644 index 6c19ac6..0000000 --- a/zynq7000/src/timer0/sr.rs +++ /dev/null @@ -1,365 +0,0 @@ -#[doc = "Register `SR` reader"] -pub type R = crate::R; -#[doc = "Register `SR` writer"] -pub type W = crate::W; -#[doc = "Shows if Timer is running or not\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Run { - #[doc = "0: Timer is not running"] - Stopped = 0, - #[doc = "1: Timer is running"] - Running = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Run) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RUN` reader - Shows if Timer is running or not"] -pub type RunR = crate::BitReader; -impl RunR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Run { - match self.bits { - false => Run::Stopped, - true => Run::Running, - } - } - #[doc = "Timer is not running"] - #[inline(always)] - pub fn is_stopped(&self) -> bool { - *self == Run::Stopped - } - #[doc = "Timer is running"] - #[inline(always)] - pub fn is_running(&self) -> bool { - *self == Run::Running - } -} -#[doc = "Shows if the MATCH was hit\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Match { - #[doc = "0: The MATCH condition was not hit"] - NoMatch = 0, - #[doc = "1: The MATCH condition was hit"] - MatchHit = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Match) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `MATCH` reader - Shows if the MATCH was hit"] -pub type MatchR = crate::BitReader; -impl MatchR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Match { - match self.bits { - false => Match::NoMatch, - true => Match::MatchHit, - } - } - #[doc = "The MATCH condition was not hit"] - #[inline(always)] - pub fn is_no_match(&self) -> bool { - *self == Match::NoMatch - } - #[doc = "The MATCH condition was hit"] - #[inline(always)] - pub fn is_match_hit(&self) -> bool { - *self == Match::MatchHit - } -} -#[doc = "Field `MATCH` writer - Shows if the MATCH was hit"] -pub type MatchW<'a, REG> = crate::BitWriter<'a, REG, Match>; -impl<'a, REG> MatchW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "The MATCH condition was not hit"] - #[inline(always)] - pub fn no_match(self) -> &'a mut crate::W { - self.variant(Match::NoMatch) - } - #[doc = "The MATCH condition was hit"] - #[inline(always)] - pub fn match_hit(self) -> &'a mut crate::W { - self.variant(Match::MatchHit) - } -} -#[doc = "Shows if an underflow occured. This flag is sticky\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Un { - #[doc = "0: No underflow occured since last clear"] - NoUnderflow = 0, - #[doc = "1: A minimum of one underflow occured since last clear"] - Underflow = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Un) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `UN` reader - Shows if an underflow occured. This flag is sticky"] -pub type UnR = crate::BitReader; -impl UnR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Un { - match self.bits { - false => Un::NoUnderflow, - true => Un::Underflow, - } - } - #[doc = "No underflow occured since last clear"] - #[inline(always)] - pub fn is_no_underflow(&self) -> bool { - *self == Un::NoUnderflow - } - #[doc = "A minimum of one underflow occured since last clear"] - #[inline(always)] - pub fn is_underflow(&self) -> bool { - *self == Un::Underflow - } -} -#[doc = "Field `UN` writer - Shows if an underflow occured. This flag is sticky"] -pub type UnW<'a, REG> = crate::BitWriter<'a, REG, Un>; -impl<'a, REG> UnW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No underflow occured since last clear"] - #[inline(always)] - pub fn no_underflow(self) -> &'a mut crate::W { - self.variant(Un::NoUnderflow) - } - #[doc = "A minimum of one underflow occured since last clear"] - #[inline(always)] - pub fn underflow(self) -> &'a mut crate::W { - self.variant(Un::Underflow) - } -} -#[doc = "Shows if an overflow occured. This flag is sticky\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Ov { - #[doc = "0: No overflow occured since last clear"] - NoOverflow = 0, - #[doc = "1: A minimum of one overflow occured since last clear"] - OverflowOccured = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Ov) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `OV` reader - Shows if an overflow occured. This flag is sticky"] -pub type OvR = crate::BitReader; -impl OvR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Ov { - match self.bits { - false => Ov::NoOverflow, - true => Ov::OverflowOccured, - } - } - #[doc = "No overflow occured since last clear"] - #[inline(always)] - pub fn is_no_overflow(&self) -> bool { - *self == Ov::NoOverflow - } - #[doc = "A minimum of one overflow occured since last clear"] - #[inline(always)] - pub fn is_overflow_occured(&self) -> bool { - *self == Ov::OverflowOccured - } -} -#[doc = "Field `OV` writer - Shows if an overflow occured. This flag is sticky"] -pub type OvW<'a, REG> = crate::BitWriter<'a, REG, Ov>; -impl<'a, REG> OvW<'a, REG> -where - REG: crate::Writable + crate::RegisterSpec, -{ - #[doc = "No overflow occured since last clear"] - #[inline(always)] - pub fn no_overflow(self) -> &'a mut crate::W { - self.variant(Ov::NoOverflow) - } - #[doc = "A minimum of one overflow occured since last clear"] - #[inline(always)] - pub fn overflow_occured(self) -> &'a mut crate::W { - self.variant(Ov::OverflowOccured) - } -} -#[doc = "Shows if Timer is in RESET state\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -pub enum Rst { - #[doc = "0: Timer is not in RESET state and can operate"] - Ready = 0, - #[doc = "1: Timer is in RESET state and can not operate"] - InReset = 1, -} -impl From for bool { - #[inline(always)] - fn from(variant: Rst) -> Self { - variant as u8 != 0 - } -} -#[doc = "Field `RST` reader - Shows if Timer is in RESET state"] -pub type RstR = crate::BitReader; -impl RstR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Rst { - match self.bits { - false => Rst::Ready, - true => Rst::InReset, - } - } - #[doc = "Timer is not in RESET state and can operate"] - #[inline(always)] - pub fn is_ready(&self) -> bool { - *self == Rst::Ready - } - #[doc = "Timer is in RESET state and can not operate"] - #[inline(always)] - pub fn is_in_reset(&self) -> bool { - *self == Rst::InReset - } -} -#[doc = "Shows the currently active RELOAD Register\n\nValue on reset: 0"] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -#[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u8)] -pub enum Reload { - #[doc = "0: Reload Register number 0 is active"] - Reload0 = 0, - #[doc = "1: Reload Register number 1 is active"] - Reload1 = 1, - #[doc = "2: Reload Register number 2 is active"] - Reload2 = 2, - #[doc = "3: Reload Register number 3 is active"] - Reload3 = 3, -} -impl From for u8 { - #[inline(always)] - fn from(variant: Reload) -> Self { - variant as _ - } -} -impl crate::FieldSpec for Reload { - type Ux = u8; -} -impl crate::IsEnum for Reload {} -#[doc = "Field `RELOAD` reader - Shows the currently active RELOAD Register"] -pub type ReloadR = crate::FieldReader; -impl ReloadR { - #[doc = "Get enumerated values variant"] - #[inline(always)] - pub const fn variant(&self) -> Reload { - match self.bits { - 0 => Reload::Reload0, - 1 => Reload::Reload1, - 2 => Reload::Reload2, - 3 => Reload::Reload3, - _ => unreachable!(), - } - } - #[doc = "Reload Register number 0 is active"] - #[inline(always)] - pub fn is_reload0(&self) -> bool { - *self == Reload::Reload0 - } - #[doc = "Reload Register number 1 is active"] - #[inline(always)] - pub fn is_reload1(&self) -> bool { - *self == Reload::Reload1 - } - #[doc = "Reload Register number 2 is active"] - #[inline(always)] - pub fn is_reload2(&self) -> bool { - *self == Reload::Reload2 - } - #[doc = "Reload Register number 3 is active"] - #[inline(always)] - pub fn is_reload3(&self) -> bool { - *self == Reload::Reload3 - } -} -impl R { - #[doc = "Bit 0 - Shows if Timer is running or not"] - #[inline(always)] - pub fn run(&self) -> RunR { - RunR::new((self.bits & 1) != 0) - } - #[doc = "Bit 8 - Shows if the MATCH was hit"] - #[inline(always)] - pub fn match_(&self) -> MatchR { - MatchR::new(((self.bits >> 8) & 1) != 0) - } - #[doc = "Bit 9 - Shows if an underflow occured. This flag is sticky"] - #[inline(always)] - pub fn un(&self) -> UnR { - UnR::new(((self.bits >> 9) & 1) != 0) - } - #[doc = "Bit 10 - Shows if an overflow occured. This flag is sticky"] - #[inline(always)] - pub fn ov(&self) -> OvR { - OvR::new(((self.bits >> 10) & 1) != 0) - } - #[doc = "Bit 12 - Shows if Timer is in RESET state"] - #[inline(always)] - pub fn rst(&self) -> RstR { - RstR::new(((self.bits >> 12) & 1) != 0) - } - #[doc = "Bits 14:15 - Shows the currently active RELOAD Register"] - #[inline(always)] - pub fn reload(&self) -> ReloadR { - ReloadR::new(((self.bits >> 14) & 3) as u8) - } -} -impl W { - #[doc = "Bit 8 - Shows if the MATCH was hit"] - #[inline(always)] - pub fn match_(&mut self) -> MatchW { - MatchW::new(self, 8) - } - #[doc = "Bit 9 - Shows if an underflow occured. This flag is sticky"] - #[inline(always)] - pub fn un(&mut self) -> UnW { - UnW::new(self, 9) - } - #[doc = "Bit 10 - Shows if an overflow occured. This flag is sticky"] - #[inline(always)] - pub fn ov(&mut self) -> OvW { - OvW::new(self, 10) - } -} -#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct SrSpec; -impl crate::RegisterSpec for SrSpec { - type Ux = u16; -} -#[doc = "`read()` method returns [`sr::R`](R) reader structure"] -impl crate::Readable for SrSpec {} -#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] -impl crate::Writable for SrSpec { - type Safety = crate::Unsafe; - const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; -} -#[doc = "`reset()` method sets SR to value 0"] -impl crate::Resettable for SrSpec { - const RESET_VALUE: u16 = 0; -}