From 924ca98fc6c35624e28712242a421696b6a40db6 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Thu, 31 Jul 2025 18:47:05 +0200 Subject: [PATCH] de-abbreviate some stuff --- examples/zedboard/src/bin/ethernet.rs | 4 ++-- examples/zedboard/src/bin/l3gd20h-i2c-mio.rs | 4 ++-- examples/zedboard/src/bin/l3gd20h-spi-mio.rs | 4 ++-- examples/zedboard/src/bin/uart-blocking.rs | 4 ++-- examples/zedboard/src/bin/uart-non-blocking.rs | 4 ++-- examples/zedboard/src/main.rs | 4 ++-- zynq7000-hal/src/gic.rs | 6 +++--- zynq7000-hal/src/l2_cache.rs | 16 ++++++++-------- zynq7000-hal/src/lib.rs | 2 +- 9 files changed, 24 insertions(+), 24 deletions(-) diff --git a/examples/zedboard/src/bin/ethernet.rs b/examples/zedboard/src/bin/ethernet.rs index 8338ea8..68df12a 100644 --- a/examples/zedboard/src/bin/ethernet.rs +++ b/examples/zedboard/src/bin/ethernet.rs @@ -40,7 +40,7 @@ use zedboard::{ use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, eth::{ AlignedBuffer, ClkDivCollection, EthernetConfig, EthernetLowLevel, embassy_net::InterruptResult, @@ -213,7 +213,7 @@ async fn main(spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Configure the uncached memory region using the MMU. mmu_l1_table_mut() diff --git a/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs b/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs index 0c0630e..496acfc 100644 --- a/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs +++ b/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs @@ -20,7 +20,7 @@ use log::{error, info}; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -52,7 +52,7 @@ async fn main(_spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); diff --git a/examples/zedboard/src/bin/l3gd20h-spi-mio.rs b/examples/zedboard/src/bin/l3gd20h-spi-mio.rs index 3b0677d..95cf6ac 100644 --- a/examples/zedboard/src/bin/l3gd20h-spi-mio.rs +++ b/examples/zedboard/src/bin/l3gd20h-spi-mio.rs @@ -20,7 +20,7 @@ use log::{error, info}; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -55,7 +55,7 @@ async fn main(spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let mut clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); diff --git a/examples/zedboard/src/bin/uart-blocking.rs b/examples/zedboard/src/bin/uart-blocking.rs index e909e85..1b511bc 100644 --- a/examples/zedboard/src/bin/uart-blocking.rs +++ b/examples/zedboard/src/bin/uart-blocking.rs @@ -15,7 +15,7 @@ use zedboard::PS_CLOCK_FREQUENCY; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -105,7 +105,7 @@ async fn main(_spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); // Set up the global interrupt controller. diff --git a/examples/zedboard/src/bin/uart-non-blocking.rs b/examples/zedboard/src/bin/uart-non-blocking.rs index 1c43fc1..fbfb48d 100644 --- a/examples/zedboard/src/bin/uart-non-blocking.rs +++ b/examples/zedboard/src/bin/uart-non-blocking.rs @@ -41,7 +41,7 @@ use log::{error, info, warn}; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -170,7 +170,7 @@ async fn main(spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); diff --git a/examples/zedboard/src/main.rs b/examples/zedboard/src/main.rs index 4ca0870..02f4565 100644 --- a/examples/zedboard/src/main.rs +++ b/examples/zedboard/src/main.rs @@ -12,7 +12,7 @@ use zedboard::PS_CLOCK_FREQUENCY; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -41,7 +41,7 @@ async fn main(_spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); diff --git a/zynq7000-hal/src/gic.rs b/zynq7000-hal/src/gic.rs index 7b71d02..d38d912 100644 --- a/zynq7000-hal/src/gic.rs +++ b/zynq7000-hal/src/gic.rs @@ -10,7 +10,7 @@ use arbitrary_int::Number; use cortex_ar::interrupt; use zynq7000::gic::{ - Dcr, GicCpuInterface, GicDistributor, Icr, InterruptSignalRegister, MmioGicCpuInterface, MmioGicDistributor, PriorityReg, + Dcr, GicCpuInterface, GicDistributor, InterfaceCtrl, InterruptSignalRegister, MmioGicCpuInterface, MmioGicDistributor, PriorityReg, }; const SPURIOUS_INTERRUPT_ID: u32 = 1023; @@ -442,7 +442,7 @@ impl GicConfigurator { /// to call [Self::enable_interrupts] for interrupts to work. pub fn enable(&mut self) { self.update_ctrl_regs( - Icr::builder() + InterfaceCtrl::builder() .with_sbpr(false) .with_fiq_en(false) .with_ack_ctrl(false) @@ -476,7 +476,7 @@ impl GicConfigurator { /// Update the control registers which control the safety configuration and which also enable /// the GIC. - pub fn update_ctrl_regs(&mut self, icr: Icr, dcr: Dcr) { + pub fn update_ctrl_regs(&mut self, icr: InterfaceCtrl, dcr: Dcr) { self.gicc.write_icr(icr); self.gicd.write_dcr(dcr); } diff --git a/zynq7000-hal/src/l2_cache.rs b/zynq7000-hal/src/l2_cache.rs index 813493d..2dedc92 100644 --- a/zynq7000-hal/src/l2_cache.rs +++ b/zynq7000-hal/src/l2_cache.rs @@ -1,15 +1,15 @@ use core::sync::atomic::compiler_fence; use arbitrary_int::{u2, u3}; -pub use zynq7000::l2_cache::LatencyConfig; +pub use zynq7000::l2_cache::LatencyCfg; use zynq7000::l2_cache::{ - Associativity, AuxControl, Ctrl, InterruptControl, MmioL2Cache, ReplacementPolicy, WaySize, + Associativity, AuxCtrl, Ctrl, InterruptCtrl, MmioL2Cache, ReplacementPolicy, WaySize, }; use crate::slcr::Slcr; /// This is the default configuration used by Xilinx/AMD. -pub const AUX_CTRL_DEFAULT: AuxControl = AuxControl::builder() +pub const AUX_CTRL_DEFAULT: AuxCtrl = AuxCtrl::builder() .with_early_bresp_enable(true) .with_isntruction_prefetch_enable(true) .with_data_prefetch_enable(true) @@ -30,14 +30,14 @@ pub const AUX_CTRL_DEFAULT: AuxControl = AuxControl::builder() .build(); /// Xilinx/AMD default configuration. 2 cycles for setup, write and read. -pub const DEFAULT_TAG_RAM_LATENCY: LatencyConfig = LatencyConfig::builder() +pub const DEFAULT_TAG_RAM_LATENCY: LatencyCfg = LatencyCfg::builder() .with_write_access_latency(u3::new(0b001)) .with_read_access_latency(u3::new(0b001)) .with_setup_latency(u3::new(0b001)) .build(); /// Xilinx/AMD default configuration. 2 cycles for setup and write, 3 cycles for read. -pub const DEFAULT_DATA_RAM_LATENCY: LatencyConfig = LatencyConfig::builder() +pub const DEFAULT_DATA_RAM_LATENCY: LatencyCfg = LatencyCfg::builder() .with_write_access_latency(u3::new(0b001)) .with_read_access_latency(u3::new(0b010)) .with_setup_latency(u3::new(0b001)) @@ -57,8 +57,8 @@ pub fn init_with_defaults(l2c_mmio: &mut MmioL2Cache<'static>) { /// the runtime initialization provided by Xilinx/AMD. pub fn init( l2c_mmio: &mut MmioL2Cache<'static>, - tag_ram_latency: LatencyConfig, - data_ram_latency: LatencyConfig, + tag_ram_latency: LatencyCfg, + data_ram_latency: LatencyCfg, ) { l2c_mmio.write_control(Ctrl::new_disabled()); l2c_mmio.write_aux_control(AUX_CTRL_DEFAULT); @@ -71,7 +71,7 @@ pub fn init( compiler_fence(core::sync::atomic::Ordering::SeqCst); let pending = l2c_mmio.read_interrupt_raw_status(); - l2c_mmio.write_interrupt_clear(InterruptControl::new_with_raw_value(pending.raw_value())); + l2c_mmio.write_interrupt_clear(InterruptCtrl::new_with_raw_value(pending.raw_value())); unsafe { Slcr::with(|slcr| { slcr.write_magic_l2c_register(SLCR_L2C_CONFIG_MAGIC_VALUE); diff --git a/zynq7000-hal/src/lib.rs b/zynq7000-hal/src/lib.rs index 620d5f0..65dad86 100644 --- a/zynq7000-hal/src/lib.rs +++ b/zynq7000-hal/src/lib.rs @@ -104,7 +104,7 @@ impl BootMode { /// system (PS). /// /// The Zynq-7000 TRM p.32 specifies more information about this register and how to use it. -pub fn cfg_level_shifter(config: zynq7000::slcr::LevelShifterCfg) { +pub fn configure_level_shifter(config: zynq7000::slcr::LevelShifterCfg) { // Safety: We only manipulate the level shift registers. unsafe { Slcr::with(|slcr_unlocked| {