replaced cortex-ar and cortex-a-rt by aarch32-rt and aarch32-cpu

zynq/zynq7000-hal/src/ddr/ll.rs

@@ -163,10 +163,7 @@ pub unsafe fn calibrate_iob_impedance(
             val
         });
         if poll_for_done {
-            while !slcr.ddriob().read_dci_status().done() {
-                // Wait for the DDR IOB impedance calibration to complete.
-                cortex_ar::asm::nop();
-            }
+            while !slcr.ddriob().read_dci_status().done() {}
         }
     });
 }

zynq/zynq7000-hal/src/ddr/mod.rs

@@ -89,7 +89,7 @@ pub fn configure_ddr_for_ddr3(
     let ddriob_shared = slcr.regs().ddriob_shared();
     // Wait for DDR IOB impedance calibration to complete first.
     while !ddriob_shared.read_dci_status().done() {
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
     }
     log::debug!("DDR IOB impedance calib done");
 
@@ -103,7 +103,7 @@ pub fn configure_ddr_for_ddr3(
         != zynq7000::ddrc::regs::OperatingMode::NormalOperation
     {
         // Wait for the soft reset to complete.
-        cortex_ar::asm::nop();
+        aarch32_cpu::asm::nop();
     }
 }