diff --git a/examples/simple/src/main.rs b/examples/simple/src/main.rs
index 2042471..4512126 100644
--- a/examples/simple/src/main.rs
+++ b/examples/simple/src/main.rs
@@ -8,7 +8,7 @@ use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
 use zynq7000::PsPeripherals;
 use zynq7000_hal::{
     clocks::Clocks,
-    gpio::{mio, Output, PinState},
+    gpio::{Output, PinState, mio},
     l2_cache,
     priv_tim::CpuPrivateTimer,
     time::Hertz,
@@ -31,7 +31,6 @@ pub enum Lib {
     Hal,
 }
 
-
 /// Entry point (not called like a normal main function)
 #[unsafe(no_mangle)]
 pub extern "C" fn boot_core(cpu_id: u32) -> ! {
diff --git a/zynq7000-hal/src/lib.rs b/zynq7000-hal/src/lib.rs
index c9d6fed..f92a800 100644
--- a/zynq7000-hal/src/lib.rs
+++ b/zynq7000-hal/src/lib.rs
@@ -18,6 +18,7 @@ use zynq7000::{
     slcr::{BootModeRegister, BootPllConfig, LevelShifterRegister},
 };
 
+pub mod boot_image;
 pub mod cache;
 pub mod clocks;
 pub mod ddr;
@@ -29,14 +30,13 @@ pub mod i2c;
 pub mod l2_cache;
 pub mod log;
 pub mod prelude;
+pub mod priv_tim;
 pub mod qspi;
 pub mod slcr;
 pub mod spi;
 pub mod time;
 pub mod ttc;
 pub mod uart;
-pub mod priv_tim;
-pub mod boot_image;
 
 /// This enumeration encodes the various boot sources.
 #[derive(Debug, Copy, Clone)]
diff --git a/zynq7000-hal/src/qspi/mod.rs b/zynq7000-hal/src/qspi/mod.rs
index e2fced9..f5cd6f7 100644
--- a/zynq7000-hal/src/qspi/mod.rs
+++ b/zynq7000-hal/src/qspi/mod.rs
@@ -1,4 +1,4 @@
-use arbitrary_int::{u2, u3, u6, Number};
+use arbitrary_int::{Number, u2, u3, u6};
 use zynq7000::{
     qspi::{
         BaudRateDivisor, Config, InstructionCode, LinearQspiConfig, LoopbackMasterClockDelay,
@@ -12,19 +12,19 @@ use zynq7000::{
 };
 
 use crate::{
+    PeriphSelect,
     clocks::Clocks,
     enable_amba_peripheral_clock,
     gpio::{
+        IoPeriphPin,
         mio::{
-            Mio0, Mio1, Mio10, Mio11, Mio12, Mio13, Mio2, Mio3, Mio4, Mio5, Mio6, Mio8, Mio9,
+            Mio0, Mio1, Mio2, Mio3, Mio4, Mio5, Mio6, Mio8, Mio9, Mio10, Mio11, Mio12, Mio13,
             MioPinMarker, MuxConfig, Pin,
         },
-        IoPeriphPin,
     },
     slcr::Slcr,
     spi_mode_const_to_cpol_cpha,
     time::Hertz,
-    PeriphSelect,
 };
 
 pub(crate) mod lqspi_configs;
diff --git a/zynq7000/src/lib.rs b/zynq7000/src/lib.rs
index 5174be9..ee52340 100644
--- a/zynq7000/src/lib.rs
+++ b/zynq7000/src/lib.rs
@@ -22,10 +22,10 @@ pub mod eth;
 pub mod gic;
 pub mod gpio;
 pub mod gtc;
-pub mod priv_tim;
 pub mod i2c;
 pub mod l2_cache;
 pub mod mpcore;
+pub mod priv_tim;
 pub mod qspi;
 pub mod slcr;
 pub mod spi;
diff --git a/zynq7000/src/priv_tim.rs b/zynq7000/src/priv_tim.rs
index 7dc4c12..dc6b1a0 100644
--- a/zynq7000/src/priv_tim.rs
+++ b/zynq7000/src/priv_tim.rs
@@ -30,7 +30,6 @@ pub struct CpuPrivateTimer {
     interrupt_status: InterruptStatus,
 }
 
-
 impl CpuPrivateTimer {
     /// Create a new CPU Private Timer MMIO instance at the fixed base address.
     ///