diff --git a/zedboard-fpga-design/src/zedboard-bd.tcl b/zedboard-fpga-design/src/zedboard-bd.tcl index 98b854d..c5d9e47 100644 --- a/zedboard-fpga-design/src/zedboard-bd.tcl +++ b/zedboard-fpga-design/src/zedboard-bd.tcl @@ -140,9 +140,10 @@ xilinx.com:ip:processing_system7:5.5\ xilinx.com:ip:axi_uartlite:2.0\ xilinx.com:ip:proc_sys_reset:5.0\ xilinx.com:ip:axi_uart16550:2.0\ -xilinx.com:ip:xlconcat:2.1\ -xilinx.com:ip:xlslice:1.0\ -xilinx.com:ip:xlconstant:1.1\ +xilinx.com:inline_hdl:ilslice:1.0\ +xilinx.com:inline_hdl:ilconcat:1.0\ +xilinx.com:inline_hdl:ilconstant:1.0\ +xilinx.com:ip:smartconnect:1.0\ " set list_ips_missing "" @@ -243,6 +244,8 @@ proc create_root_design { parentCell } { set UART_txd [ create_bd_port -dir O UART_txd ] set UART_rxd [ create_bd_port -dir I UART_rxd ] set TTC0_WAVEOUT [ create_bd_port -dir O TTC0_WAVEOUT ] + set OLED_SCLK [ create_bd_port -dir O OLED_SCLK ] + set OLED_SDIN [ create_bd_port -dir O OLED_SDIN ] # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] @@ -260,7 +263,7 @@ proc create_root_design { parentCell } { CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ - CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ @@ -287,6 +290,8 @@ proc create_root_design { parentCell } { CONFIG.PCW_ENET_RESET_ENABLE {1} \ CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ CONFIG.PCW_EN_EMIO_GPIO {1} \ + CONFIG.PCW_EN_EMIO_SPI0 {0} \ + CONFIG.PCW_EN_EMIO_SPI1 {1} \ CONFIG.PCW_EN_EMIO_TTC0 {1} \ CONFIG.PCW_EN_EMIO_TTC1 {0} \ CONFIG.PCW_EN_EMIO_UART0 {1} \ @@ -295,6 +300,8 @@ proc create_root_design { parentCell } { CONFIG.PCW_EN_GPIO {1} \ CONFIG.PCW_EN_QSPI {1} \ CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SPI0 {0} \ + CONFIG.PCW_EN_SPI1 {1} \ CONFIG.PCW_EN_TTC0 {1} \ CONFIG.PCW_EN_TTC1 {0} \ CONFIG.PCW_EN_UART0 {1} \ @@ -489,6 +496,11 @@ proc create_root_design { parentCell } { CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \ + CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI1_SPI1_IO {EMIO} \ + CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ + CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \ CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \ CONFIG.PCW_TTC0_TTC0_IO {EMIO} \ CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \ @@ -502,14 +514,14 @@ proc create_root_design { parentCell } { CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ - CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.176} \ - CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.159} \ - CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.162} \ - CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.187} \ - CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.073} \ - CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.034} \ - CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.03} \ - CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.082} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.410} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.411} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.341} \ + CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.358} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.025} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.028} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ + CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.061} \ CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} \ CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ @@ -534,11 +546,6 @@ proc create_root_design { parentCell } { ] $axi_uartlite_0 - # Create instance: ps7_0_axi_periph, and set properties - set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] - set_property CONFIG.NUM_MI {2} $ps7_0_axi_periph - - # Create instance: rst_ps7_0_100M, and set properties set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ] @@ -550,71 +557,6 @@ proc create_root_design { parentCell } { ] $axi_uart16550_0 - # Create instance: IRQ_F2P, and set properties - set IRQ_F2P [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 IRQ_F2P ] - - # Create instance: LEDS, and set properties - set LEDS [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 LEDS ] - set_property -dict [list \ - CONFIG.DIN_FROM {7} \ - CONFIG.DIN_WIDTH {16} \ - ] $LEDS - - - # Create instance: EMIO_O_0, and set properties - set EMIO_O_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 EMIO_O_0 ] - set_property -dict [list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DIN_WIDTH {64} \ - ] $EMIO_O_0 - - - # Create instance: EMIO_O_1, and set properties - set EMIO_O_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 EMIO_O_1 ] - set_property -dict [list \ - CONFIG.DIN_FROM {47} \ - CONFIG.DIN_TO {32} \ - CONFIG.DIN_WIDTH {64} \ - ] $EMIO_O_1 - - - # Create instance: EMIO_I, and set properties - set EMIO_I [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 EMIO_I ] - set_property -dict [list \ - CONFIG.IN0_WIDTH {16} \ - CONFIG.IN1_WIDTH {16} \ - CONFIG.IN2_WIDTH {16} \ - CONFIG.IN3_WIDTH {16} \ - CONFIG.NUM_PORTS {4} \ - ] $EMIO_I - - - # Create instance: EMIO_I_0, and set properties - set EMIO_I_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 EMIO_I_0 ] - set_property -dict [list \ - CONFIG.IN0_WIDTH {8} \ - CONFIG.IN1_WIDTH {5} \ - CONFIG.IN2_WIDTH {3} \ - CONFIG.NUM_PORTS {3} \ - ] $EMIO_I_0 - - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {3} \ - ] $xlconstant_0 - - - # Create instance: EMIO_I_1, and set properties - set EMIO_I_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 EMIO_I_1 ] - set_property -dict [list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {16} \ - ] $EMIO_I_1 - - # Create instance: uart_mux_0, and set properties set block_name uart_mux set block_cell_name uart_mux_0 @@ -626,8 +568,45 @@ proc create_root_design { parentCell } { return 1 } + # Create instance: EMIO_O_0, and set properties + set EMIO_O_0 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilslice:1.0 EMIO_O_0 ] + set_property -dict [list \ + CONFIG.DIN_FROM {15} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {64} \ + ] $EMIO_O_0 + + + # Create instance: EMIO_O_1, and set properties + set EMIO_O_1 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilslice:1.0 EMIO_O_1 ] + set_property -dict [list \ + CONFIG.DIN_FROM {47} \ + CONFIG.DIN_TO {32} \ + CONFIG.DIN_WIDTH {64} \ + ] $EMIO_O_1 + + + # Create instance: EMIO_I, and set properties + set EMIO_I [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilconcat:1.0 EMIO_I ] + set_property -dict [list \ + CONFIG.IN0_WIDTH {16} \ + CONFIG.IN1_WIDTH {16} \ + CONFIG.IN2_WIDTH {16} \ + CONFIG.IN3_WIDTH {16} \ + CONFIG.NUM_PORTS {4} \ + ] $EMIO_I + + + # Create instance: EMIO_I_1, and set properties + set EMIO_I_1 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilconstant:1.0 EMIO_I_1 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {16} \ + ] $EMIO_I_1 + + # Create instance: UART_MUX, and set properties - set UART_MUX [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 UART_MUX ] + set UART_MUX [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilslice:1.0 UART_MUX ] set_property -dict [list \ CONFIG.DIN_FROM {10} \ CONFIG.DIN_TO {8} \ @@ -635,56 +614,125 @@ proc create_root_design { parentCell } { ] $UART_MUX - # Create instance: xlconstant_1, and set properties - set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + # Create instance: LEDS, and set properties + set LEDS [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilslice:1.0 LEDS ] + set_property -dict [list \ + CONFIG.DIN_FROM {7} \ + CONFIG.DIN_WIDTH {16} \ + ] $LEDS + + + # Create instance: EMIO_I_0, and set properties + set EMIO_I_0 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilconcat:1.0 EMIO_I_0 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH {8} \ + CONFIG.IN1_WIDTH {5} \ + CONFIG.IN2_WIDTH {3} \ + CONFIG.NUM_PORTS {3} \ + ] $EMIO_I_0 + + + # Create instance: ilconstant_0, and set properties + set ilconstant_0 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilconstant:1.0 ilconstant_0 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {3} \ + ] $ilconstant_0 + + + # Create instance: ilconstant_1, and set properties + set ilconstant_1 [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilconstant:1.0 ilconstant_1 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [list \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_0 + + + # Create instance: IRQ_F2P, and set properties + set IRQ_F2P [ create_bd_cell -type inline_hdl -vlnv xilinx.com:inline_hdl:ilconcat:1.0 IRQ_F2P ] # Create interface connections connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] - connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] - connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins axi_uartlite_0/S_AXI] - connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins axi_uart16550_0/S_AXI] + connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins axi_uartlite_0/S_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins axi_uart16550_0/S_AXI] # Create port connections - connect_bd_net -net EMIO_O_1_Dout [get_bd_pins EMIO_O_1/Dout] [get_bd_pins EMIO_I/In2] - connect_bd_net -net In0_0_1 [get_bd_ports SWITCHES] [get_bd_pins EMIO_I_0/In0] - connect_bd_net -net In1_0_1 [get_bd_ports BTTNS] [get_bd_pins EMIO_I_0/In1] - connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_pins axi_uart16550_0/ip2intc_irpt] [get_bd_pins IRQ_F2P/In1] - connect_bd_net -net axi_uart16550_0_sout [get_bd_pins axi_uart16550_0/sout] [get_bd_pins uart_mux_0/uart_2_tx] - connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins IRQ_F2P/In0] - connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins uart_mux_0/uart_1_tx] - connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins uart_mux_0/sys_clk] - connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] - connect_bd_net -net processing_system7_0_GPIO_O [get_bd_pins processing_system7_0/GPIO_O] [get_bd_pins EMIO_O_0/Din] [get_bd_pins EMIO_O_1/Din] - connect_bd_net -net processing_system7_0_TTC0_WAVE0_OUT [get_bd_pins processing_system7_0/TTC0_WAVE0_OUT] [get_bd_ports TTC0_WAVEOUT] - connect_bd_net -net processing_system7_0_UART0_TX [get_bd_pins processing_system7_0/UART0_TX] [get_bd_pins uart_mux_0/uart_0_tx] - connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] - connect_bd_net -net rx_in_0_1 [get_bd_ports UART_rxd] [get_bd_pins uart_mux_0/rx_in] - connect_bd_net -net uart_mux_0_tx_out [get_bd_pins uart_mux_0/tx_out] [get_bd_ports UART_txd] - connect_bd_net -net uart_mux_0_uart_0_rx [get_bd_pins uart_mux_0/uart_0_rx] [get_bd_pins processing_system7_0/UART0_RX] - connect_bd_net -net uart_mux_0_uart_1_rx [get_bd_pins uart_mux_0/uart_1_rx] [get_bd_pins axi_uartlite_0/rx] - connect_bd_net -net uart_mux_0_uart_2_rx [get_bd_pins uart_mux_0/uart_2_rx] [get_bd_pins axi_uart16550_0/sin] - connect_bd_net -net xlconcat_0_dout [get_bd_pins IRQ_F2P/dout] [get_bd_pins processing_system7_0/IRQ_F2P] - connect_bd_net -net xlconcat_1_dout [get_bd_pins EMIO_I/dout] [get_bd_pins processing_system7_0/GPIO_I] - connect_bd_net -net xlconcat_1_dout1 [get_bd_pins EMIO_I_0/dout] [get_bd_pins EMIO_I/In1] - connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] [get_bd_pins EMIO_I_0/In2] - connect_bd_net -net xlconstant_1_dout [get_bd_pins EMIO_I_1/dout] [get_bd_pins EMIO_I/In3] - connect_bd_net -net xlconstant_1_dout1 [get_bd_pins xlconstant_1/dout] [get_bd_pins axi_uart16550_0/rin] [get_bd_pins axi_uart16550_0/dsrn] [get_bd_pins axi_uart16550_0/ctsn] [get_bd_pins axi_uart16550_0/dcdn] - connect_bd_net -net xlslice_0_Dout [get_bd_pins LEDS/Dout] [get_bd_ports LEDS] - connect_bd_net -net xlslice_0_Dout1 [get_bd_pins UART_MUX/Dout] [get_bd_pins uart_mux_0/sel] - connect_bd_net -net xlslice_1_Dout [get_bd_pins EMIO_O_0/Dout] [get_bd_pins LEDS/Din] [get_bd_pins EMIO_I/In0] [get_bd_pins UART_MUX/Din] - - # Set DDR properties specified in the datasheet. - set_property -dict [list \ - CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.410} \ - CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.411} \ - CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.341} \ - CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.358} \ - CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.025} \ - CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.028} \ - CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ - CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.061} \ - ] [get_bd_cells processing_system7_0] + connect_bd_net -net BTTNS_1 [get_bd_ports BTTNS] \ + [get_bd_pins EMIO_I_0/In1] + connect_bd_net -net EMIO_I_1_dout [get_bd_pins EMIO_I_1/dout] \ + [get_bd_pins EMIO_I/In3] + connect_bd_net -net EMIO_O_1_Dout [get_bd_pins EMIO_O_1/Dout] \ + [get_bd_pins EMIO_I/In2] + connect_bd_net -net SWITCHES_1 [get_bd_ports SWITCHES] \ + [get_bd_pins EMIO_I_0/In0] + connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_pins axi_uart16550_0/ip2intc_irpt] \ + [get_bd_pins IRQ_F2P/In1] + connect_bd_net -net axi_uart16550_0_sout [get_bd_pins axi_uart16550_0/sout] \ + [get_bd_pins uart_mux_0/uart_2_tx] + connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] \ + [get_bd_pins IRQ_F2P/In0] + connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] \ + [get_bd_pins uart_mux_0/uart_1_tx] + connect_bd_net -net ilconcat_0_dout [get_bd_pins EMIO_I/dout] \ + [get_bd_pins processing_system7_0/GPIO_I] + connect_bd_net -net ilconcat_0_dout1 [get_bd_pins EMIO_I_0/dout] \ + [get_bd_pins EMIO_I/In1] + connect_bd_net -net ilconcat_0_dout2 [get_bd_pins IRQ_F2P/dout] \ + [get_bd_pins processing_system7_0/IRQ_F2P] + connect_bd_net -net ilconstant_0_dout [get_bd_pins ilconstant_0/dout] \ + [get_bd_pins EMIO_I_0/In2] + connect_bd_net -net ilslice_0_Dout [get_bd_pins UART_MUX/Dout] \ + [get_bd_pins uart_mux_0/sel] + connect_bd_net -net ilslice_0_Dout1 [get_bd_pins LEDS/Dout] \ + [get_bd_ports LEDS] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] \ + [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] \ + [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] \ + [get_bd_pins axi_uartlite_0/s_axi_aclk] \ + [get_bd_pins axi_uart16550_0/s_axi_aclk] \ + [get_bd_pins uart_mux_0/sys_clk] \ + [get_bd_pins smartconnect_0/aclk] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] \ + [get_bd_pins rst_ps7_0_100M/ext_reset_in] + connect_bd_net -net processing_system7_0_GPIO_O [get_bd_pins processing_system7_0/GPIO_O] \ + [get_bd_pins EMIO_O_0/Din] \ + [get_bd_pins EMIO_O_1/Din] + connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_pins processing_system7_0/SPI1_MOSI_O] \ + [get_bd_ports OLED_SDIN] + connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_pins processing_system7_0/SPI1_SCLK_O] \ + [get_bd_ports OLED_SCLK] + connect_bd_net -net processing_system7_0_TTC0_WAVE0_OUT [get_bd_pins processing_system7_0/TTC0_WAVE0_OUT] \ + [get_bd_ports TTC0_WAVEOUT] + connect_bd_net -net processing_system7_0_UART0_TX [get_bd_pins processing_system7_0/UART0_TX] \ + [get_bd_pins uart_mux_0/uart_0_tx] + connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] \ + [get_bd_pins axi_uartlite_0/s_axi_aresetn] \ + [get_bd_pins axi_uart16550_0/s_axi_aresetn] \ + [get_bd_pins smartconnect_0/aresetn] + connect_bd_net -net rx_in_0_1 [get_bd_ports UART_rxd] \ + [get_bd_pins uart_mux_0/rx_in] + connect_bd_net -net uart_mux_0_tx_out [get_bd_pins uart_mux_0/tx_out] \ + [get_bd_ports UART_txd] + connect_bd_net -net uart_mux_0_uart_0_rx [get_bd_pins uart_mux_0/uart_0_rx] \ + [get_bd_pins processing_system7_0/UART0_RX] + connect_bd_net -net uart_mux_0_uart_1_rx [get_bd_pins uart_mux_0/uart_1_rx] \ + [get_bd_pins axi_uartlite_0/rx] + connect_bd_net -net uart_mux_0_uart_2_rx [get_bd_pins uart_mux_0/uart_2_rx] \ + [get_bd_pins axi_uart16550_0/sin] + connect_bd_net -net xlconstant_1_dout1 [get_bd_pins ilconstant_1/dout] \ + [get_bd_pins axi_uart16550_0/rin] \ + [get_bd_pins axi_uart16550_0/dsrn] \ + [get_bd_pins axi_uart16550_0/ctsn] \ + [get_bd_pins axi_uart16550_0/dcdn] + connect_bd_net -net xlslice_1_Dout [get_bd_pins EMIO_O_0/Dout] \ + [get_bd_pins EMIO_I/In0] \ + [get_bd_pins UART_MUX/Din] \ + [get_bd_pins LEDS/Din] # Create address segments assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force @@ -694,7 +742,6 @@ proc create_root_design { parentCell } { # Restore current instance current_bd_instance $oldCurInst - validate_bd_design save_bd_design } # End of create_root_design() @@ -707,3 +754,5 @@ proc create_root_design { parentCell } { create_root_design "" +common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." + diff --git a/zedboard-fpga-design/src/zedboard.xdc b/zedboard-fpga-design/src/zedboard.xdc index 001e72e..d01c99c 100644 --- a/zedboard-fpga-design/src/zedboard.xdc +++ b/zedboard-fpga-design/src/zedboard.xdc @@ -70,6 +70,12 @@ set_property IOSTANDARD LVCMOS33 [get_ports UART_rxd] set_property PACKAGE_PIN AA11 [get_ports UART_txd] set_property IOSTANDARD LVCMOS33 [get_ports UART_txd] +# OLED SPI +set_property PACKAGE_PIN AB12 [get_ports OLED_SCLK] +set_property IOSTANDARD LVCMOS33 [get_ports OLED_SCLK] +set_property PACKAGE_PIN AA12 [get_ports OLED_SDIN] +set_property IOSTANDARD LVCMOS33 [get_ports OLED_SDIN] + # TTC0 Wave Out set_property PACKAGE_PIN W12 [get_ports {TTC0_WAVEOUT}] set_property IOSTANDARD LVCMOS33 [get_ports {TTC0_WAVEOUT}] \ No newline at end of file