rename register blocks

zynq/zynq7000/src/ddrc.rs

@@ -728,7 +728,7 @@ use regs::*;
 /// DDR controller register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct DdrController {
+pub struct Registers {
     ddrc_ctrl: DdrcControl,
     two_rank_cfg: TwoRankConfig,
     hpr_queue_ctrl: LprHprQueueControl,
@@ -871,9 +871,9 @@ pub struct DdrController {
     lpddr_ctrl_3: LpddrControl3,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<DdrController>(), 0x2B8);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x2B8);
 
-impl DdrController {
+impl Registers {
     /// Create a new DDR MMIO instance for the DDR controller at address [DDRC_BASE_ADDR].
     ///
     /// # Safety
@@ -881,7 +881,7 @@ impl DdrController {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed() -> MmioDdrController<'static> {
+    pub const unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(DDRC_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/devcfg.rs

@@ -260,7 +260,7 @@ pub struct Status {
 /// Device configuration register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct DevCfg {
+pub struct Registers {
     control: Control,
     lock: Lock,
     config: Config,
@@ -284,12 +284,12 @@ pub struct DevCfg {
 
     // Included here but not exposed to avoid providing multiple references to the same peripheral.
     // Exposed in [crate::xadc].
-    _xadc: crate::xadc::XAdc,
+    _xadc: crate::xadc::Registers,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<DevCfg>(), 0x11C);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x11C);
 
-impl DevCfg {
+impl Registers {
     /// Create a new DevCfg MMIO instance for for device configuration peripheral at address
     /// [DEVCFG_BASE_ADDR].
     ///
@@ -298,7 +298,7 @@ impl DevCfg {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub unsafe fn new_mmio_fixed() -> MmioDevCfg<'static> {
+    pub unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(DEVCFG_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/eth.rs

@@ -421,7 +421,7 @@ pub struct MatchRegister {
 /// Gigabit Ethernet Controller (GEM) register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct Ethernet {
+pub struct Registers {
     net_ctrl: NetworkControl,
     net_cfg: NetworkConfig,
     #[mmio(PureRead)]
@@ -475,7 +475,7 @@ pub struct Ethernet {
     design_cfg_5: u32,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<Ethernet>(), 0x294);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x294);
 
 /// Ethernet statistics registers
 #[derive(derive_mmio::Mmio)]
@@ -571,7 +571,7 @@ pub struct Statistics {
     rx_udp_checksum_errors: u32,
 }
 
-impl Ethernet {
+impl Registers {
     /// Create a new Gigabit Ethernet MMIO instance for GEM 0 at address [GEM_0_BASE_ADDR].
     ///
     /// # Safety
@@ -579,7 +579,7 @@ impl Ethernet {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_0() -> MmioEthernet<'static> {
+    pub const unsafe fn new_mmio_fixed_0() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(GEM_0_BASE_ADDR) }
     }
 
@@ -590,7 +590,7 @@ impl Ethernet {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_1() -> MmioEthernet<'static> {
+    pub const unsafe fn new_mmio_fixed_1() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(GEM_1_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/gic.rs

@@ -43,7 +43,7 @@ pub type Typer = TypeRegister;
 /// GIC Distributor registers.
 #[derive(derive_mmio::Mmio)]
 #[repr(C, align(8))]
-pub struct GicDistributor {
+pub struct GicDistributorRegisters {
     /// Distributor Control Register
     pub dcr: DistributorControlRegister,
     /// Interrupt Controller Type Register
@@ -109,9 +109,9 @@ pub struct GicDistributor {
     pub cidr: [u32; 4],
 }
 
-const_assert_eq!(core::mem::size_of::<GicDistributor>(), 0x1000);
+const_assert_eq!(core::mem::size_of::<GicDistributorRegisters>(), 0x1000);
 
-impl GicDistributor {
+impl GicDistributorRegisters {
     /// Create a new Global Interrupt Controller Distributor MMIO instance at the fixed address of
     /// the processing system.
     ///
@@ -121,7 +121,7 @@ impl GicDistributor {
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
     #[inline]
-    pub const unsafe fn new_mmio_fixed() -> MmioGicDistributor<'static> {
+    pub const unsafe fn new_mmio_fixed() -> MmioGicDistributorRegisters<'static> {
         unsafe { Self::new_mmio_at(GICD_BASE_ADDR) }
     }
 }
@@ -160,7 +160,7 @@ pub struct InterruptSignalRegister {
 /// GIC CPU interface registers.
 #[derive(derive_mmio::Mmio)]
 #[repr(C, align(8))]
-pub struct GicCpuInterface {
+pub struct GicCpuInterfaceRegisters {
     /// CPU Interface Control Register (ICR).
     pub icr: InterfaceControl,
     /// Interrupt Priority Mask Register.
@@ -183,9 +183,9 @@ pub struct GicCpuInterface {
     pub iidr: u32,
 }
 
-const_assert_eq!(core::mem::size_of::<GicCpuInterface>(), 0x100);
+const_assert_eq!(core::mem::size_of::<GicCpuInterfaceRegisters>(), 0x100);
 
-impl GicCpuInterface {
+impl GicCpuInterfaceRegisters {
     /// Create a new Global Interrupt Controller CPU MMIO instance at the fixed address of the
     /// processing system.
     ///
@@ -195,7 +195,7 @@ impl GicCpuInterface {
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
     #[inline]
-    pub const unsafe fn new_mmio_fixed() -> MmioGicCpuInterface<'static> {
+    pub const unsafe fn new_mmio_fixed() -> MmioGicCpuInterfaceRegisters<'static> {
         unsafe { Self::new_mmio_at(GICC_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/gpio.rs

@@ -10,7 +10,7 @@ pub struct MaskedOutput {
 
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct BankControl {
+pub struct BankControlRegisters {
     /// Direction mode
     dirm: u32,
     /// Output enable
@@ -38,7 +38,7 @@ pub struct BankControl {
 /// GPIO register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct Gpio {
+pub struct Registers {
     /// Maskable output data (GPIO bank 0, MIO, lower 16 bits)
     masked_out_0_lsw: MaskedOutput,
     /// Maskable output data (GPIO bank 0, MIO, upper 16 bits)
@@ -85,27 +85,27 @@ pub struct Gpio {
     _reserved_2: [u32; 101],
 
     #[mmio(Inner)]
-    bank_0: BankControl,
+    bank_0: BankControlRegisters,
 
     _reserved_3: [u32; 7],
 
     #[mmio(Inner)]
-    bank_1: BankControl,
+    bank_1: BankControlRegisters,
 
     _reserved_4: [u32; 7],
 
     #[mmio(Inner)]
-    bank_2: BankControl,
+    bank_2: BankControlRegisters,
 
     _reserved_5: [u32; 7],
 
     #[mmio(Inner)]
-    bank_3: BankControl,
+    bank_3: BankControlRegisters,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x2E8);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x2E8);
 
-impl Gpio {
+impl Registers {
     /// Create a new XGPIOPS GPIO MMIO instance.
     ///
     /// # Safety
@@ -113,9 +113,9 @@ impl Gpio {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed() -> MmioGpio<'static> {
-        MmioGpio {
-            ptr: 0xE000A000 as *mut Gpio,
+    pub const unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
+        MmioRegisters {
+            ptr: 0xE000A000 as *mut Registers,
             phantom: core::marker::PhantomData,
         }
     }

zynq/zynq7000/src/gtc.rs

@@ -25,7 +25,7 @@ pub struct InterruptStatus {
 /// Global timer counter register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct GlobalTimerCounter {
+pub struct Registers {
     /// Count register 0, lower 32 bits
     count_lower: u32,
     /// Count register 1, upper 32 bits
@@ -43,9 +43,9 @@ pub struct GlobalTimerCounter {
     auto_increment: u32,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<GlobalTimerCounter>(), 0x1C);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x1C);
 
-impl GlobalTimerCounter {
+impl Registers {
     /// Create a new GTC MMIO instance at the fixed base address.
     ///
     /// # Safety
@@ -54,7 +54,7 @@ impl GlobalTimerCounter {
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
     #[inline]
-    pub const unsafe fn new_mmio_fixed() -> MmioGlobalTimerCounter<'static> {
-        unsafe { GlobalTimerCounter::new_mmio_at(GTC_BASE_ADDR) }
+    pub const unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
+        unsafe { Registers::new_mmio_at(GTC_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/i2c.rs

@@ -159,7 +159,7 @@ pub struct TransferSize {
 /// I2C register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct I2c {
+pub struct Registers {
     cr: Control,
     #[mmio(PureRead)]
     sr: Status,
@@ -179,9 +179,9 @@ pub struct I2c {
     idr: InterruptControl,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<I2c>(), 0x2C);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x2C);
 
-impl I2c {
+impl Registers {
     /// Create a new I2C MMIO instance for I2C0 at address [I2C_0_BASE_ADDR].
     ///
     /// # Safety
@@ -189,7 +189,7 @@ impl I2c {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_0() -> MmioI2c<'static> {
+    pub const unsafe fn new_mmio_fixed_0() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(I2C_0_BASE_ADDR) }
     }
 
@@ -200,7 +200,7 @@ impl I2c {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_1() -> MmioI2c<'static> {
+    pub const unsafe fn new_mmio_fixed_1() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(I2C_1_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/l2_cache.rs

@@ -187,7 +187,7 @@ pub struct InterruptControl {
 /// L2 Cache register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct L2Cache {
+pub struct Registers {
     #[mmio(PureRead)]
     cache_id: CacheId,
     #[mmio(PureRead)]
@@ -273,9 +273,9 @@ pub struct L2Cache {
     power_control: u32,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<L2Cache>(), 0xF84);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0xF84);
 
-impl L2Cache {
+impl Registers {
     /// Create a new L2C MMIO instance for for L2 Cache at address [L2C_BASE_ADDR].
     ///
     /// # Safety
@@ -283,7 +283,7 @@ impl L2Cache {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed() -> MmioL2Cache<'static> {
+    pub const unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(L2C_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/lib.rs

@@ -43,26 +43,26 @@ static PERIPHERALS_TAKEN: AtomicBool = AtomicBool::new(false);
 /// The [`svd2rust` documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api)
 /// provides some more information about this.
 pub struct Peripherals {
-    pub gicc: gic::MmioGicCpuInterface<'static>,
-    pub gicd: gic::MmioGicDistributor<'static>,
-    pub l2c: l2_cache::MmioL2Cache<'static>,
-    pub ddrc: ddrc::MmioDdrController<'static>,
-    pub uart_0: uart::MmioUart<'static>,
-    pub uart_1: uart::MmioUart<'static>,
-    pub spi_0: spi::MmioSpi<'static>,
-    pub spi_1: spi::MmioSpi<'static>,
-    pub i2c_0: i2c::MmioI2c<'static>,
-    pub i2c_1: i2c::MmioI2c<'static>,
-    pub gtc: gtc::MmioGlobalTimerCounter<'static>,
-    pub gpio: gpio::MmioGpio<'static>,
-    pub slcr: slcr::MmioSlcr<'static>,
-    pub ttc_0: ttc::MmioTtc<'static>,
-    pub ttc_1: ttc::MmioTtc<'static>,
-    pub eth_0: eth::MmioEthernet<'static>,
-    pub eth_1: eth::MmioEthernet<'static>,
-    pub qspi: qspi::MmioQspi<'static>,
-    pub devcfg: devcfg::MmioDevCfg<'static>,
-    pub xadc: xadc::MmioXAdc<'static>,
+    pub gicc: gic::MmioGicCpuInterfaceRegisters<'static>,
+    pub gicd: gic::MmioGicDistributorRegisters<'static>,
+    pub l2c: l2_cache::MmioRegisters<'static>,
+    pub ddrc: ddrc::MmioRegisters<'static>,
+    pub uart_0: uart::MmioRegisters<'static>,
+    pub uart_1: uart::MmioRegisters<'static>,
+    pub spi_0: spi::MmioRegisters<'static>,
+    pub spi_1: spi::MmioRegisters<'static>,
+    pub i2c_0: i2c::MmioRegisters<'static>,
+    pub i2c_1: i2c::MmioRegisters<'static>,
+    pub gtc: gtc::MmioRegisters<'static>,
+    pub gpio: gpio::MmioRegisters<'static>,
+    pub slcr: slcr::MmioRegisters<'static>,
+    pub ttc_0: ttc::MmioRegisters<'static>,
+    pub ttc_1: ttc::MmioRegisters<'static>,
+    pub eth_0: eth::MmioRegisters<'static>,
+    pub eth_1: eth::MmioRegisters<'static>,
+    pub qspi: qspi::MmioRegisters<'static>,
+    pub devcfg: devcfg::MmioRegisters<'static>,
+    pub xadc: xadc::MmioRegisters<'static>,
 }
 
 impl Peripherals {
@@ -83,26 +83,26 @@ impl Peripherals {
     pub unsafe fn steal() -> Self {
         unsafe {
             Self {
-                gicc: gic::GicCpuInterface::new_mmio_fixed(),
-                gicd: gic::GicDistributor::new_mmio_fixed(),
-                l2c: l2_cache::L2Cache::new_mmio_fixed(),
-                ddrc: ddrc::DdrController::new_mmio_fixed(),
-                uart_0: uart::Uart::new_mmio_fixed_0(),
-                uart_1: uart::Uart::new_mmio_fixed_1(),
-                gtc: gtc::GlobalTimerCounter::new_mmio_fixed(),
-                gpio: gpio::Gpio::new_mmio_fixed(),
-                slcr: slcr::Slcr::new_mmio_fixed(),
-                spi_0: spi::Spi::new_mmio_fixed_0(),
-                spi_1: spi::Spi::new_mmio_fixed_1(),
-                i2c_0: i2c::I2c::new_mmio_fixed_0(),
-                i2c_1: i2c::I2c::new_mmio_fixed_1(),
-                ttc_0: ttc::Ttc::new_mmio_fixed_0(),
-                ttc_1: ttc::Ttc::new_mmio_fixed_1(),
-                eth_0: eth::Ethernet::new_mmio_fixed_0(),
-                eth_1: eth::Ethernet::new_mmio_fixed_1(),
-                qspi: qspi::Qspi::new_mmio_fixed(),
-                devcfg: devcfg::DevCfg::new_mmio_fixed(),
-                xadc: xadc::XAdc::new_mmio_fixed(),
+                gicc: gic::GicCpuInterfaceRegisters::new_mmio_fixed(),
+                gicd: gic::GicDistributorRegisters::new_mmio_fixed(),
+                l2c: l2_cache::Registers::new_mmio_fixed(),
+                ddrc: ddrc::Registers::new_mmio_fixed(),
+                uart_0: uart::Registers::new_mmio_fixed_0(),
+                uart_1: uart::Registers::new_mmio_fixed_1(),
+                gtc: gtc::Registers::new_mmio_fixed(),
+                gpio: gpio::Registers::new_mmio_fixed(),
+                slcr: slcr::Registers::new_mmio_fixed(),
+                spi_0: spi::Registers::new_mmio_fixed_0(),
+                spi_1: spi::Registers::new_mmio_fixed_1(),
+                i2c_0: i2c::Registers::new_mmio_fixed_0(),
+                i2c_1: i2c::Registers::new_mmio_fixed_1(),
+                ttc_0: ttc::Registers::new_mmio_fixed_0(),
+                ttc_1: ttc::Registers::new_mmio_fixed_1(),
+                eth_0: eth::Registers::new_mmio_fixed_0(),
+                eth_1: eth::Registers::new_mmio_fixed_1(),
+                qspi: qspi::Registers::new_mmio_fixed(),
+                devcfg: devcfg::Registers::new_mmio_fixed(),
+                xadc: xadc::Registers::new_mmio_fixed(),
             }
         }
     }

zynq/zynq7000/src/mpcore.rs

@@ -4,8 +4,11 @@
 use static_assertions::const_assert_eq;
 
 use crate::{
-    gic::{GicCpuInterface, GicDistributor, MmioGicCpuInterface, MmioGicDistributor},
-    gtc::{GlobalTimerCounter, MmioGlobalTimerCounter},
+    gic::{
+        GicCpuInterfaceRegisters, GicDistributorRegisters, MmioGicCpuInterfaceRegisters,
+        MmioGicDistributorRegisters,
+    },
+    gtc::{MmioRegisters, Registers},
 };
 
 pub const MPCORE_BASE_ADDR: usize = 0xF8F0_0000;
@@ -54,10 +57,10 @@ pub struct MpCore {
     _reserved_0: [u32; 0x2A],
 
     #[mmio(Inner)]
-    gicc: GicCpuInterface,
+    gicc: GicCpuInterfaceRegisters,
 
     #[mmio(Inner)]
-    gt: GlobalTimerCounter,
+    gt: Registers,
 
     _reserved_1: [u32; 0xF9],
 
@@ -78,7 +81,7 @@ pub struct MpCore {
     _reserved_3: [u32; 0x272],
 
     #[mmio(Inner)]
-    gicd: GicDistributor,
+    gicd: GicDistributorRegisters,
 }
 
 const_assert_eq!(core::mem::size_of::<MpCore>(), 0x2000);

zynq/zynq7000/src/priv_tim.rs

@@ -24,14 +24,14 @@ pub struct InterruptStatus {
 /// CPU private timer register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct CpuPrivateTimer {
+pub struct Registers {
     reload: u32,
     counter: u32,
     control: Control,
     interrupt_status: InterruptStatus,
 }
 
-impl CpuPrivateTimer {
+impl Registers {
     /// Create a new CPU Private Timer MMIO instance at the fixed base address.
     ///
     /// # Safety
@@ -43,7 +43,7 @@ impl CpuPrivateTimer {
     /// It should also be noted that the calls to this MMIO structure are private for each CPU
     /// core, which might lead to unexpected results when using this in a SMP system.
     #[inline]
-    pub const unsafe fn new_mmio_fixed() -> MmioCpuPrivateTimer<'static> {
-        unsafe { CpuPrivateTimer::new_mmio_at(CPU_PRIV_TIM_BASE_ADDR) }
+    pub const unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
+        unsafe { Registers::new_mmio_at(CPU_PRIV_TIM_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/qspi.rs

@@ -223,7 +223,7 @@ pub struct LinearQspiStatus {
 /// QSPI register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct Qspi {
+pub struct Registers {
     config: Config,
     interrupt_status: InterruptStatus,
     #[mmio(Write)]
@@ -265,9 +265,9 @@ pub struct Qspi {
     module_id: u32,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<Qspi>(), 0x100);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x100);
 
-impl Qspi {
+impl Registers {
     /// Create a new QSPI MMIO instance for for QSPI controller at address [QSPI_BASE_ADDR].
     ///
     /// # Safety
@@ -275,7 +275,7 @@ impl Qspi {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed() -> MmioQspi<'static> {
+    pub const unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(QSPI_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/slcr/clocks.rs

@@ -110,14 +110,14 @@ pub struct FpgaClockControl {
 
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct FpgaClockControlBlock {
+pub struct FpgaClockControlRegisters {
     ctrl: FpgaClockControl,
     thr_ctrl: u32,
     thr_cnt: u32,
     thr_status: u32,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<FpgaClockControlBlock>(), 0x10);
+static_assertions::const_assert_eq!(core::mem::size_of::<FpgaClockControlRegisters>(), 0x10);
 
 #[bitbybit::bitenum(u2, exhaustive = true)]
 #[derive(Debug)]
@@ -359,7 +359,7 @@ pub struct AperClockControl {
 
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct ClockControl {
+pub struct ClockControlRegisters {
     arm_pll_ctrl: PllControl,
     ddr_pll_ctrl: PllControl,
     io_pll_ctrl: PllControl,
@@ -391,18 +391,18 @@ pub struct ClockControl {
     pcap_clk_ctrl: SingleCommonPeriphIoClockControl,
     topsw_clk_ctrl: u32,
     #[mmio(Inner)]
-    fpga_0_clk_ctrl: FpgaClockControlBlock,
+    fpga_0_clk_ctrl: FpgaClockControlRegisters,
     #[mmio(Inner)]
-    fpga_1_clk_ctrl: FpgaClockControlBlock,
+    fpga_1_clk_ctrl: FpgaClockControlRegisters,
     #[mmio(Inner)]
-    fpga_2_clk_ctrl: FpgaClockControlBlock,
+    fpga_2_clk_ctrl: FpgaClockControlRegisters,
     #[mmio(Inner)]
-    fpga_3_clk_ctrl: FpgaClockControlBlock,
+    fpga_3_clk_ctrl: FpgaClockControlRegisters,
     _gap1: [u32; 5],
     clk_621_true: ClockRatioSelectReg,
 }
 
-impl ClockControl {
+impl ClockControlRegisters {
     /// Create a new handle to this peripheral.
     ///
     /// Writing to this register requires unlocking the SLCR registers first.
@@ -411,9 +411,9 @@ impl ClockControl {
     ///
     /// If you create multiple instances of this handle at the same time, you are responsible for
     /// ensuring that there are no read-modify-write races on any of the registers.
-    pub unsafe fn new_mmio_fixed() -> MmioClockControl<'static> {
+    pub unsafe fn new_mmio_fixed() -> MmioClockControlRegisters<'static> {
         unsafe { Self::new_mmio_at(SLCR_BASE_ADDR + CLOCK_CONTROL_OFFSET) }
     }
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<ClockControl>(), 0xC8);
+static_assertions::const_assert_eq!(core::mem::size_of::<ClockControlRegisters>(), 0xC8);

zynq/zynq7000/src/slcr/ddriob.rs

@@ -106,7 +106,7 @@ pub struct DdriobConfig {
 
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct DdrIoB {
+pub struct DdrIobRegisters {
     ddriob_addr0: DdriobConfig,
     ddriob_addr1: DdriobConfig,
     ddriob_data0: DdriobConfig,
@@ -123,7 +123,7 @@ pub struct DdrIoB {
     dci_status: DciStatus,
 }
 
-impl DdrIoB {
+impl DdrIobRegisters {
     /// Create a new handle to this peripheral.
     ///
     /// Writing to this register requires unlocking the SLCR registers first.
@@ -132,9 +132,9 @@ impl DdrIoB {
     ///
     /// If you create multiple instances of this handle at the same time, you are responsible for
     /// ensuring that there are no read-modify-write races on any of the registers.
-    pub unsafe fn new_mmio_fixed() -> MmioDdrIoB<'static> {
+    pub unsafe fn new_mmio_fixed() -> MmioDdrIobRegisters<'static> {
         unsafe { Self::new_mmio_at(super::SLCR_BASE_ADDR + super::DDRIOB_OFFSET) }
     }
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<DdrIoB>(), 0x38);
+static_assertions::const_assert_eq!(core::mem::size_of::<DdrIobRegisters>(), 0x38);

zynq/zynq7000/src/slcr/mod.rs

@@ -2,7 +2,7 @@
 //!
 //! Writing any of these registers required unlocking the SLCR first.
 use arbitrary_int::u4;
-pub use clocks::{ClockControl, MmioClockControl};
+pub use clocks::{ClockControlRegisters, MmioClockControlRegisters};
 pub use reset::{MmioResetControl, ResetControl};
 
 const SLCR_BASE_ADDR: usize = 0xF8000000;
@@ -94,7 +94,7 @@ pub struct LevelShifterRegister {
 /// System Level Control Registers access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct Slcr {
+pub struct Registers {
     /// Secure configuration lock.
     scl: u32,
     /// SLCR write protection lock
@@ -107,7 +107,7 @@ pub struct Slcr {
     _gap0: [u32; 0x3C],
 
     #[mmio(Inner)]
-    clk_ctrl: ClockControl,
+    clk_ctrl: ClockControlRegisters,
 
     _gap1: [u32; 0x0E],
 
@@ -180,12 +180,12 @@ pub struct Slcr {
     gpiob: GpiobRegisters,
 
     #[mmio(Inner)]
-    ddriob: ddriob::DdrIoB,
+    ddriob: ddriob::DdrIobRegisters,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<Slcr>(), 0xB78);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0xB78);
 
-impl Slcr {
+impl Registers {
     /// Create a new handle to this peripheral.
     ///
     /// Writing to this register requires unlocking the SLCR registers first.
@@ -194,7 +194,7 @@ impl Slcr {
     ///
     /// If you create multiple instances of this handle at the same time, you are responsible for
     /// ensuring that there are no read-modify-write races on any of the registers.
-    pub unsafe fn new_mmio_fixed() -> MmioSlcr<'static> {
+    pub unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(SLCR_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/spi.rs

@@ -35,7 +35,6 @@ impl BaudDivSel {
 
 // TODO: Use bitbybit debug support as soon as it was added.
 #[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
 pub struct Config {
     #[bit(17, rw)]
     modefail_gen_en: bool,
@@ -181,7 +180,7 @@ pub struct DelayControl {
 /// SPI register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct Spi {
+pub struct Registers {
     cr: Config,
     #[mmio(PureRead, Write)]
     isr: InterruptStatus,
@@ -209,9 +208,9 @@ pub struct Spi {
     mod_id: u32,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<Spi>(), 0x100);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x100);
 
-impl Spi {
+impl Registers {
     /// Create a new SPI MMIO instance for SPI0 at address [SPI_0_BASE_ADDR].
     ///
     /// # Safety
@@ -219,7 +218,7 @@ impl Spi {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_0() -> MmioSpi<'static> {
+    pub const unsafe fn new_mmio_fixed_0() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(SPI_0_BASE_ADDR) }
     }
 
@@ -230,7 +229,7 @@ impl Spi {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_1() -> MmioSpi<'static> {
+    pub const unsafe fn new_mmio_fixed_1() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(SPI_1_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/ttc.rs

@@ -145,7 +145,7 @@ pub struct EventCount {
 /// Triple-timer counter register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct Ttc {
+pub struct Registers {
     clk_cntr: [ClockControl; 3],
     cnt_ctrl: [CounterControl; 3],
     #[mmio(PureRead)]
@@ -162,9 +162,9 @@ pub struct Ttc {
     event_reg: [EventCount; 3],
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<Ttc>(), 0x84);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x84);
 
-impl Ttc {
+impl Registers {
     /// Create a new TTC MMIO instance for TTC0 at address [TTC_0_BASE_ADDR].
     ///
     /// # Safety
@@ -172,7 +172,7 @@ impl Ttc {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_0() -> MmioTtc<'static> {
+    pub const unsafe fn new_mmio_fixed_0() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(TTC_0_BASE_ADDR) }
     }
 
@@ -183,7 +183,7 @@ impl Ttc {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_1() -> MmioTtc<'static> {
+    pub const unsafe fn new_mmio_fixed_1() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(TTC_1_BASE_ADDR) }
     }
 }

zynq/zynq7000/src/uart.rs

@@ -281,7 +281,7 @@ impl InterruptStatus {
 /// UART register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct Uart {
+pub struct Registers {
     /// Control Register
     cr: Control,
     /// Mode register
@@ -325,9 +325,9 @@ pub struct Uart {
     tx_fifo_trigger: FifoTrigger,
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<Uart>(), 0x48);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x48);
 
-impl Uart {
+impl Registers {
     /// Create a new UART MMIO instance for uart0 at address 0xE000_0000.
     ///
     /// # Safety
@@ -335,7 +335,7 @@ impl Uart {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_0() -> MmioUart<'static> {
+    pub const unsafe fn new_mmio_fixed_0() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(UART_0_BASE) }
     }
 
@@ -346,7 +346,7 @@ impl Uart {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub const unsafe fn new_mmio_fixed_1() -> MmioUart<'static> {
+    pub const unsafe fn new_mmio_fixed_1() -> MmioRegisters<'static> {
         unsafe { Self::new_mmio_at(UART_1_BASE) }
     }
 }

zynq/zynq7000/src/xadc.rs

@@ -3,7 +3,7 @@ pub const XADC_BASE_ADDR: usize = 0xF8007100;
 /// XADC register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
-pub struct XAdc {
+pub struct Registers {
     config: u32,
     interrupt_status: u32,
     interrupt_mask: u32,
@@ -13,7 +13,7 @@ pub struct XAdc {
     misc_control: u32,
 }
 
-impl XAdc {
+impl Registers {
     /// Create a new XADC MMIO instance for for device configuration peripheral at address
     /// [XADC_BASE_ADDR].
     ///
@@ -22,9 +22,9 @@ impl XAdc {
     /// This API can be used to potentially create a driver to the same peripheral structure
     /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
     /// interfere with each other.
-    pub unsafe fn new_mmio_fixed() -> MmioXAdc<'static> {
-        unsafe { XAdc::new_mmio_at(XADC_BASE_ADDR) }
+    pub unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
+        unsafe { Registers::new_mmio_at(XADC_BASE_ADDR) }
     }
 }
 
-static_assertions::const_assert_eq!(core::mem::size_of::<XAdc>(), 0x1C);
+static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x1C);