first SDIO test
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This commit is contained in:
Robin Mueller
2025-11-28 18:02:37 +01:00
parent e4eac4b9ac
commit e559572d69
3 changed files with 24 additions and 17 deletions

View File

@@ -13,13 +13,13 @@ use zynq7000_hal::gpio::Input;
use zynq7000_hal::prelude::*;
use zynq7000_hal::{
BootMode, clocks, gic, gpio, gtc,
sdio::{Sdio, SdioClockConfig, SdioLowLevel},
sdio::{Sdio, SdioClockConfig},
uart,
};
use zynq7000_rt as _;
const INIT_STRING: &str = "-- Zynq 7000 Zedboard GPIO blinky example --\n\r";
const INIT_STRING: &str = "-- Zynq 7000 Zedboard SDIO example --\n\r";
/// Entry point (not called like a normal main function)
#[unsafe(no_mangle)]
@@ -42,7 +42,7 @@ async fn main(_spawner: Spawner) -> ! {
// Clock was already initialized by PS7 Init TCL script or FSBL, we just read it.
let clocks = clocks::Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap();
let mut gpio_pins = gpio::GpioPins::new(periphs.gpio);
let gpio_pins = gpio::GpioPins::new(periphs.gpio);
// Set up global timer counter and embassy time driver.
let gtc = gtc::GlobalTimerCounter::new(periphs.gtc, clocks.arm_clocks());
@@ -69,7 +69,7 @@ async fn main(_spawner: Spawner) -> ! {
};
let sdio_clock_config =
SdioClockConfig::calculate_for_io_clock(clocks.io_clocks(), 100.MHz(), 10.MHz());
SdioClockConfig::calculate_for_io_clock(clocks.io_clocks(), 100.MHz(), 10.MHz()).unwrap();
let sdio = Sdio::new_for_sdio_0(
periphs.sdio_0,
sdio_clock_config,
@@ -85,7 +85,10 @@ async fn main(_spawner: Spawner) -> ! {
.unwrap();
let card_detect = Input::new_for_mio(gpio_pins.mio.mio47).unwrap();
let write_protect = Input::new_for_mio(gpio_pins.mio.mio46).unwrap();
info!("Card detect state: {:?}", card_detect.is_high());
// The card detect being active low makes sense according to the Zedboard docs. Not sure
// about write-protect though.. It seems that write protect on means that the
// the pin is pulled high.
info!("Card detect state: {:?}", card_detect.is_low());
info!("Write protect state: {:?}", write_protect.is_high());
let capabilities = sdio.ll().capabilities();

View File

@@ -470,7 +470,7 @@ impl Ethernet {
});
});
}
ll.configure_peripheral_clock(config.clk_config_1000_mbps, true);
ll.configure_clock(config.clk_config_1000_mbps, true);
let mut mdio = mdio::Mdio::new(&ll, true);
mdio.configure_clock_div(config.mdc_clk_div);
ll.regs.modify_net_ctrl(|mut val| {
@@ -491,7 +491,7 @@ impl Ethernet {
pub fn new(mut ll: EthernetLowLevel, config: EthernetConfig) -> Self {
Self::common_init(&mut ll, config.mac_address);
ll.configure_peripheral_clock(config.clk_config_1000_mbps, true);
ll.configure_clock(config.clk_config_1000_mbps, true);
let mut mdio = mdio::Mdio::new(&ll, true);
mdio.configure_clock_div(config.mdc_clk_div);
Ethernet {

View File

@@ -10,7 +10,7 @@ use crate::gpio::mio::{
Mio41, Mio42, Mio43, Mio44, Mio45, Mio46, Mio47, Mio50, Mio51,
};
use crate::{
clocks::{Clocks, IoClocks},
clocks::IoClocks,
gpio::{
IoPeriphPin,
mio::{
@@ -22,6 +22,10 @@ use crate::{
time::Hertz,
};
#[derive(Debug, thiserror::Error)]
#[error("invalid peripheral instance")]
pub struct InvalidPeripheralError;
pub const MUX_CONF: MuxConfig = MuxConfig::new_with_l3(u3::new(0b100));
pub trait Sdio0ClockPin: MioPin {}
@@ -354,12 +358,12 @@ impl Sdio {
clock_pin: Sdio0Clock,
command_pin: Sdio0Command,
data_pins: (Sdio0Data0, Sdio0Data1, Sdio0Data2, Sdio0Data3),
) -> Option<Self> {
let id = regs.id()?;
if id != SdioId::Sdio1 {
return None;
) -> Result<Self, InvalidPeripheralError> {
let id = regs.id().ok_or(InvalidPeripheralError)?;
if id != SdioId::Sdio0 {
return Err(InvalidPeripheralError);
}
Some(Self::new(
Ok(Self::new(
regs,
clock_config,
clock_pin,
@@ -381,12 +385,12 @@ impl Sdio {
clock_pin: Sdio1Clock,
command_pin: Sdio1Command,
data_pins: (Sdio1Data0, Sdio1Data1, Sdio1Data2, Sdio1Data3),
) -> Option<Self> {
let id = regs.id()?;
) -> Result<Self, InvalidPeripheralError> {
let id = regs.id().ok_or(InvalidPeripheralError)?;
if id != SdioId::Sdio1 {
return None;
return Err(InvalidPeripheralError);
}
Some(Self::new(
Ok(Self::new(
regs,
clock_config,
clock_pin,