From bd5bbe2a422032804fa851d0fc2faa52f3651bde Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Thu, 31 Jul 2025 18:37:05 +0200 Subject: [PATCH 1/2] major renaming --- .../embassy/src/bin/dht22-open-drain-pins.rs | 4 +- .../embassy/src/bin/logger-non-blocking.rs | 4 +- examples/embassy/src/bin/pwm.rs | 4 +- examples/embassy/src/main.rs | 4 +- examples/simple/src/bin/gtc-ticks.rs | 4 +- examples/simple/src/bin/logger.rs | 4 +- examples/zedboard/src/bin/ethernet.rs | 10 +-- examples/zedboard/src/bin/l3gd20h-i2c-mio.rs | 10 +-- examples/zedboard/src/bin/l3gd20h-spi-mio.rs | 12 +-- examples/zedboard/src/bin/uart-blocking.rs | 10 +-- .../zedboard/src/bin/uart-non-blocking.rs | 10 +-- examples/zedboard/src/main.rs | 10 +-- zynq7000-embassy/src/lib.rs | 12 +-- zynq7000-hal/src/clocks.rs | 16 ++-- zynq7000-hal/src/eth/ll.rs | 22 ++--- zynq7000-hal/src/eth/mod.rs | 12 +-- zynq7000-hal/src/gic.rs | 18 ++-- zynq7000-hal/src/gpio/ll.rs | 16 ++-- zynq7000-hal/src/gpio/mio.rs | 6 +- zynq7000-hal/src/gpio/mod.rs | 22 ++--- zynq7000-hal/src/gtc.rs | 16 ++-- zynq7000-hal/src/i2c.rs | 30 +++---- zynq7000-hal/src/l2_cache.rs | 6 +- zynq7000-hal/src/lib.rs | 90 +++++++++---------- zynq7000-hal/src/spi/mod.rs | 28 +++--- zynq7000-hal/src/time.rs | 3 + zynq7000-hal/src/ttc.rs | 14 +-- zynq7000-hal/src/uart/mod.rs | 22 ++--- zynq7000/src/eth.rs | 20 ++--- zynq7000/src/gic.rs | 34 +++---- zynq7000/src/gtc.rs | 10 +-- zynq7000/src/i2c.rs | 8 +- zynq7000/src/l2_cache.rs | 24 ++--- zynq7000/src/lib.rs | 12 +-- zynq7000/src/mpcore.rs | 10 +-- zynq7000/src/slcr/clocks.rs | 24 ++--- zynq7000/src/slcr/mod.rs | 12 +-- zynq7000/src/slcr/reset.rs | 22 ++--- zynq7000/src/spi.rs | 24 ++--- zynq7000/src/ttc.rs | 4 +- 40 files changed, 313 insertions(+), 310 deletions(-) diff --git a/examples/embassy/src/bin/dht22-open-drain-pins.rs b/examples/embassy/src/bin/dht22-open-drain-pins.rs index 0e7711d..d60453f 100644 --- a/examples/embassy/src/bin/dht22-open-drain-pins.rs +++ b/examples/embassy/src/bin/dht22-open-drain-pins.rs @@ -14,7 +14,7 @@ use zynq7000_hal::{ clocks::Clocks, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{Flex, Output, PinState, mio}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, time::Hertz, uart::{ClkConfigRaw, Uart, UartConfig}, @@ -60,7 +60,7 @@ async fn main(_spawner: Spawner) -> ! { let mio_pins = mio::Pins::new(dp.gpio); // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); // Set up the UART, we are logging with it. diff --git a/examples/embassy/src/bin/logger-non-blocking.rs b/examples/embassy/src/bin/logger-non-blocking.rs index 145e66d..23223c1 100644 --- a/examples/embassy/src/bin/logger-non-blocking.rs +++ b/examples/embassy/src/bin/logger-non-blocking.rs @@ -15,7 +15,7 @@ use zynq7000_hal::{ clocks::Clocks, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{Output, PinState, mio}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, time::Hertz, uart::{ClkConfigRaw, TxAsync, Uart, UartConfig, on_interrupt_tx}, @@ -52,7 +52,7 @@ async fn main(spawner: Spawner) -> ! { gic.enable_interrupts(); } // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); let mio_pins = mio::Pins::new(dp.gpio); diff --git a/examples/embassy/src/bin/pwm.rs b/examples/embassy/src/bin/pwm.rs index 0d2c4bd..5180b09 100644 --- a/examples/embassy/src/bin/pwm.rs +++ b/examples/embassy/src/bin/pwm.rs @@ -20,7 +20,7 @@ use zynq7000_hal::{ clocks::Clocks, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{Output, PinState, mio}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, time::Hertz, uart::{ClkConfigRaw, Uart, UartConfig}, @@ -60,7 +60,7 @@ async fn main(_spawner: Spawner) -> ! { let mio_pins = mio::Pins::new(dp.gpio); // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); // Unwrap is okay, the address is definitely valid. diff --git a/examples/embassy/src/main.rs b/examples/embassy/src/main.rs index 31fc883..300f677 100644 --- a/examples/embassy/src/main.rs +++ b/examples/embassy/src/main.rs @@ -13,7 +13,7 @@ use zynq7000_hal::{ clocks::Clocks, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{Output, PinState, mio}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, time::Hertz, uart::{ClkConfigRaw, Uart, UartConfig}, @@ -53,7 +53,7 @@ async fn main(_spawner: Spawner) -> ! { let mio_pins = mio::Pins::new(dp.gpio); // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); // Set up the UART, we are logging with it. diff --git a/examples/simple/src/bin/gtc-ticks.rs b/examples/simple/src/bin/gtc-ticks.rs index 7fe7a35..6fee69a 100644 --- a/examples/simple/src/bin/gtc-ticks.rs +++ b/examples/simple/src/bin/gtc-ticks.rs @@ -11,7 +11,7 @@ use zynq7000_hal::{ clocks::Clocks, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{Output, PinState, mio}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, prelude::*, time::Hertz, @@ -52,7 +52,7 @@ pub fn main() -> ! { let uart_clk_config = ClkConfigRaw::new_autocalc_with_error(clocks.io_clocks(), 115200) .unwrap() .0; - let mut gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let mut gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); let ticks = gtc.frequency_to_ticks(1000.Hz()); gtc.set_auto_increment_value(ticks); gtc.set_comparator(gtc.read_timer() + ticks as u64); diff --git a/examples/simple/src/bin/logger.rs b/examples/simple/src/bin/logger.rs index 579bcb7..fdc04c4 100644 --- a/examples/simple/src/bin/logger.rs +++ b/examples/simple/src/bin/logger.rs @@ -12,7 +12,7 @@ use zynq7000_hal::{ clocks::Clocks, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{Output, PinState, mio}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, prelude::*, time::Hertz, @@ -53,7 +53,7 @@ pub fn main() -> ! { let uart_clk_config = ClkConfigRaw::new_autocalc_with_error(clocks.io_clocks(), 115200) .unwrap() .0; - let mut gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let mut gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); let ticks = gtc.frequency_to_ticks(1000.Hz()); gtc.set_auto_increment_value(ticks); gtc.set_comparator(gtc.read_timer() + ticks as u64); diff --git a/examples/zedboard/src/bin/ethernet.rs b/examples/zedboard/src/bin/ethernet.rs index 6a468c8..8338ea8 100644 --- a/examples/zedboard/src/bin/ethernet.rs +++ b/examples/zedboard/src/bin/ethernet.rs @@ -40,19 +40,19 @@ use zedboard::{ use zynq7000_hal::{ BootMode, clocks::Clocks, - configure_level_shifter, + cfg_level_shifter, eth::{ AlignedBuffer, ClkDivCollection, EthernetConfig, EthernetLowLevel, embassy_net::InterruptResult, }, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, uart::{ClkConfigRaw, Uart, UartConfig}, }; -use zynq7000::{PsPeripherals, slcr::LevelShifterConfig}; +use zynq7000::{PsPeripherals, slcr::LevelShifterCfg}; use zynq7000_rt::{self as _, mmu::section_attrs::SHAREABLE_DEVICE, mmu_l1_table_mut}; const USE_DHCP: bool = true; @@ -213,7 +213,7 @@ async fn main(spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - configure_level_shifter(LevelShifterConfig::EnableAll); + cfg_level_shifter(LevelShifterCfg::EnableAll); // Configure the uncached memory region using the MMU. mmu_l1_table_mut() @@ -233,7 +233,7 @@ async fn main(spawner: Spawner) -> ! { let gpio_pins = GpioPins::new(dp.gpio); // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); // Set up the UART, we are logging with it. diff --git a/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs b/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs index 1a6ec09..0c0630e 100644 --- a/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs +++ b/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs @@ -20,16 +20,16 @@ use log::{error, info}; use zynq7000_hal::{ BootMode, clocks::Clocks, - configure_level_shifter, + cfg_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, - gtc::Gtc, + gtc::GlobalTimerCounter, i2c, l2_cache, time::Hertz, uart, }; -use zynq7000::{PsPeripherals, slcr::LevelShifterConfig}; +use zynq7000::{PsPeripherals, slcr::LevelShifterCfg}; use zynq7000_rt as _; // Define the clock frequency as a constant @@ -52,7 +52,7 @@ async fn main(_spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - configure_level_shifter(LevelShifterConfig::EnableAll); + cfg_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); @@ -69,7 +69,7 @@ async fn main(_spawner: Spawner) -> ! { let mut gpio_pins = GpioPins::new(dp.gpio); // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); // Set up the UART, we are logging with it. diff --git a/examples/zedboard/src/bin/l3gd20h-spi-mio.rs b/examples/zedboard/src/bin/l3gd20h-spi-mio.rs index d7b38b9..3b0677d 100644 --- a/examples/zedboard/src/bin/l3gd20h-spi-mio.rs +++ b/examples/zedboard/src/bin/l3gd20h-spi-mio.rs @@ -20,17 +20,17 @@ use log::{error, info}; use zynq7000_hal::{ BootMode, clocks::Clocks, - configure_level_shifter, + cfg_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, spi::{self, SpiAsync, SpiId, SpiWithHwCs, SpiWithHwCsAsync, on_interrupt}, time::Hertz, uart::{self, TxAsync, on_interrupt_tx}, }; -use zynq7000::{PsPeripherals, slcr::LevelShifterConfig, spi::DelayControl}; +use zynq7000::{PsPeripherals, slcr::LevelShifterCfg, spi::DelayControl}; use zynq7000_rt as _; // Define the clock frequency as a constant @@ -55,7 +55,7 @@ async fn main(spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - configure_level_shifter(LevelShifterConfig::EnableAll); + cfg_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let mut clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); @@ -79,7 +79,7 @@ async fn main(spawner: Spawner) -> ! { let mut gpio_pins = GpioPins::new(dp.gpio); // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); // Set up the UART, we are logging with it. @@ -114,7 +114,7 @@ async fn main(spawner: Spawner) -> ! { clocks.io_clocks(), spi::Config::new( // 10 MHz maximum rating of the sensor. - zynq7000::spi::BaudDivSelect::By64, + zynq7000::spi::BaudDivSel::By64, //l3gd20::MODE, embedded_hal::spi::MODE_3, spi::SlaveSelectConfig::AutoWithAutoStart, diff --git a/examples/zedboard/src/bin/uart-blocking.rs b/examples/zedboard/src/bin/uart-blocking.rs index 617cfae..e909e85 100644 --- a/examples/zedboard/src/bin/uart-blocking.rs +++ b/examples/zedboard/src/bin/uart-blocking.rs @@ -15,15 +15,15 @@ use zedboard::PS_CLOCK_FREQUENCY; use zynq7000_hal::{ BootMode, clocks::Clocks, - configure_level_shifter, + cfg_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, uart::{ClkConfigRaw, Uart, UartConfig}, }; -use zynq7000::{PsPeripherals, slcr::LevelShifterConfig}; +use zynq7000::{PsPeripherals, slcr::LevelShifterCfg}; use zynq7000_rt as _; const INIT_STRING: &str = "-- Zynq 7000 Zedboard blocking UART example --\n\r"; @@ -105,7 +105,7 @@ async fn main(_spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - configure_level_shifter(LevelShifterConfig::EnableAll); + cfg_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); // Set up the global interrupt controller. @@ -119,7 +119,7 @@ async fn main(_spawner: Spawner) -> ! { let mut gpio_pins = GpioPins::new(dp.gpio); // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); // Set up the UART, we are logging with it. diff --git a/examples/zedboard/src/bin/uart-non-blocking.rs b/examples/zedboard/src/bin/uart-non-blocking.rs index a2b712e..1c43fc1 100644 --- a/examples/zedboard/src/bin/uart-non-blocking.rs +++ b/examples/zedboard/src/bin/uart-non-blocking.rs @@ -41,10 +41,10 @@ use log::{error, info, warn}; use zynq7000_hal::{ BootMode, clocks::Clocks, - configure_level_shifter, + cfg_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, time::Hertz, uart::{ClkConfigRaw, Uart, UartConfig}, @@ -62,7 +62,7 @@ const INIT_STRING: &str = "-- Zynq 7000 Zedboard non-blocking UART example --\n\ #[global_allocator] static HEAP: Heap = Heap::empty(); -use zynq7000::{PsPeripherals, slcr::LevelShifterConfig}; +use zynq7000::{PsPeripherals, slcr::LevelShifterCfg}; use zynq7000_rt as _; // Define the clock frequency as a constant @@ -170,7 +170,7 @@ async fn main(spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - configure_level_shifter(LevelShifterConfig::EnableAll); + cfg_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); @@ -190,7 +190,7 @@ async fn main(spawner: Spawner) -> ! { let mut gpio_pins = GpioPins::new(dp.gpio); // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); // Set up the UART, we are logging with it. diff --git a/examples/zedboard/src/main.rs b/examples/zedboard/src/main.rs index b6aaa33..4ca0870 100644 --- a/examples/zedboard/src/main.rs +++ b/examples/zedboard/src/main.rs @@ -12,15 +12,15 @@ use zedboard::PS_CLOCK_FREQUENCY; use zynq7000_hal::{ BootMode, clocks::Clocks, - configure_level_shifter, + cfg_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, - gtc::Gtc, + gtc::GlobalTimerCounter, l2_cache, uart::{ClkConfigRaw, Uart, UartConfig}, }; -use zynq7000::{PsPeripherals, slcr::LevelShifterConfig}; +use zynq7000::{PsPeripherals, slcr::LevelShifterCfg}; use zynq7000_rt as _; const INIT_STRING: &str = "-- Zynq 7000 Zedboard GPIO blinky example --\n\r"; @@ -41,7 +41,7 @@ async fn main(_spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - configure_level_shifter(LevelShifterConfig::EnableAll); + cfg_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); @@ -56,7 +56,7 @@ async fn main(_spawner: Spawner) -> ! { let mut gpio_pins = GpioPins::new(dp.gpio); // Set up global timer counter and embassy time driver. - let gtc = Gtc::new(dp.gtc, clocks.arm_clocks()); + let gtc = GlobalTimerCounter::new(dp.gtc, clocks.arm_clocks()); zynq7000_embassy::init(clocks.arm_clocks(), gtc); // Set up the UART, we are logging with it. diff --git a/zynq7000-embassy/src/lib.rs b/zynq7000-embassy/src/lib.rs index b480376..34dd714 100644 --- a/zynq7000-embassy/src/lib.rs +++ b/zynq7000-embassy/src/lib.rs @@ -6,7 +6,7 @@ use embassy_time_driver::{Driver, TICK_HZ, time_driver_impl}; use embassy_time_queue_utils::Queue; use once_cell::sync::OnceCell; -use zynq7000_hal::{clocks::ArmClocks, gtc::Gtc, time::Hertz}; +use zynq7000_hal::{clocks::ArmClocks, gtc::GlobalTimerCounter, time::Hertz}; static SCALE: OnceCell = OnceCell::new(); static CPU_3X2X_CLK: OnceCell = OnceCell::new(); @@ -28,7 +28,7 @@ unsafe impl Send for AlarmState {} /// This is the initialization method for the embassy time driver. /// /// It should be called ONCE at system initialization. -pub fn init(arm_clocks: &ArmClocks, gtc: Gtc) { +pub fn init(arm_clocks: &ArmClocks, gtc: GlobalTimerCounter) { if SCALE.get().is_some() || CPU_3X2X_CLK.get().is_some() { return; } @@ -46,7 +46,7 @@ pub unsafe fn on_interrupt() { } pub struct GtcTimerDriver { - gtc: Mutex>, + gtc: Mutex>, // Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled. alarms: Mutex, queue: Mutex>, @@ -58,7 +58,7 @@ impl GtcTimerDriver { /// # Safety /// /// This has to be called ONCE at system initialization. - pub unsafe fn init(&'static self, arm_clock: &ArmClocks, mut gtc: Gtc) { + pub unsafe fn init(&'static self, arm_clock: &ArmClocks, mut gtc: GlobalTimerCounter) { CPU_3X2X_CLK.set(arm_clock.cpu_3x2x_clk()).unwrap(); SCALE .set(arm_clock.cpu_3x2x_clk().raw() as u64 / TICK_HZ) @@ -148,7 +148,7 @@ impl Driver for GtcTimerDriver { } // This is okay, we only read the GTC and do not re-configure it, avoids the // need for a lock. - let gtc = unsafe { Gtc::steal_fixed(Some(*CPU_3X2X_CLK.get().unwrap())) }; + let gtc = unsafe { GlobalTimerCounter::steal_fixed(Some(*CPU_3X2X_CLK.get().unwrap())) }; gtc.read_timer() / SCALE.get().unwrap() } @@ -170,7 +170,7 @@ impl Driver for GtcTimerDriver { time_driver_impl!( // We assume ownership of the GTC, so it is okay to steal here. static GTC_TIME_DRIVER: GtcTimerDriver = GtcTimerDriver { - gtc: Mutex::new(RefCell::new(unsafe { Gtc::steal_fixed(None)})), + gtc: Mutex::new(RefCell::new(unsafe { GlobalTimerCounter::steal_fixed(None)})), alarms: Mutex::new(AlarmState::new()), queue: Mutex::new(RefCell::new(Queue::new())), }); diff --git a/zynq7000-hal/src/clocks.rs b/zynq7000-hal/src/clocks.rs index 3a6feb2..4a48983 100644 --- a/zynq7000-hal/src/clocks.rs +++ b/zynq7000-hal/src/clocks.rs @@ -4,7 +4,7 @@ use arbitrary_int::Number; use zynq7000::slcr::{ ClockControl, clocks::{ - ClockRatioSelect, DualCommonPeriphIoClkCtrl, FpgaClkControl, GigEthClkCtrl, + ClkRatioSelect, DualCommonPeriphIoClkCtrl, FpgaClkCtrl, GigEthClkCtrl, SingleCommonPeriphIoClkCtrl, }, }; @@ -228,14 +228,14 @@ impl Clocks { } let arm_clk_divided = arm_base_clk / arm_clk_ctrl.divisor().as_u32(); let arm_clks = match clk_sel.sel() { - ClockRatioSelect::FourToTwoToOne => ArmClocks { + ClkRatioSelect::FourToTwoToOne => ArmClocks { ref_clk: arm_pll_out, cpu_1x_clk: arm_clk_divided / 4, cpu_2x_clk: arm_clk_divided / 2, cpu_3x2x_clk: arm_clk_divided / 2, cpu_6x4x_clk: arm_clk_divided, }, - ClockRatioSelect::SixToTwoToOne => ArmClocks { + ClkRatioSelect::SixToTwoToOne => ArmClocks { ref_clk: arm_pll_out, cpu_1x_clk: arm_clk_divided / 6, cpu_2x_clk: arm_clk_divided / 3, @@ -340,7 +340,7 @@ impl Clocks { | zynq7000::slcr::clocks::SrcSelTpiu::EmioTraceClkAlt1 | zynq7000::slcr::clocks::SrcSelTpiu::EmioTraceClkAlt2 => None, }; - let calculate_fpga_clk = |fpga_clk_ctrl: FpgaClkControl| -> Result { + let calculate_fpga_clk = |fpga_clk_ctrl: FpgaClkCtrl| -> Result { if fpga_clk_ctrl.divisor_0().as_u32() == 0 || fpga_clk_ctrl.divisor_1().as_u32() == 0 { return Err(ClockReadError::DivisorZero(DivisorZero( ClockModuleId::Fpga, @@ -387,10 +387,10 @@ impl Clocks { // TODO: There should be a mut and a non-mut getter for an inner block. We only do pure // reads with the inner block here. pl: [ - calculate_fpga_clk(clk_regs.fpga_0_clk_ctrl().read_clk_ctrl())?, - calculate_fpga_clk(clk_regs.fpga_1_clk_ctrl().read_clk_ctrl())?, - calculate_fpga_clk(clk_regs.fpga_2_clk_ctrl().read_clk_ctrl())?, - calculate_fpga_clk(clk_regs.fpga_3_clk_ctrl().read_clk_ctrl())?, + calculate_fpga_clk(clk_regs.fpga_0_clk_ctrl().read_ctrl())?, + calculate_fpga_clk(clk_regs.fpga_1_clk_ctrl().read_ctrl())?, + calculate_fpga_clk(clk_regs.fpga_2_clk_ctrl().read_ctrl())?, + calculate_fpga_clk(clk_regs.fpga_3_clk_ctrl().read_ctrl())?, ], }) } diff --git a/zynq7000-hal/src/eth/ll.rs b/zynq7000-hal/src/eth/ll.rs index 8c59638..889ca4a 100644 --- a/zynq7000-hal/src/eth/ll.rs +++ b/zynq7000-hal/src/eth/ll.rs @@ -1,10 +1,10 @@ use arbitrary_int::{Number, u6}; use zynq7000::{ - eth::{InterruptControl, NetworkControl, RxStatus, TxStatus}, - slcr::reset::EthernetReset, + eth::{InterruptCtrl, NetworkCtrl, RxStatus, TxStatus}, + slcr::reset::EthernetRst, }; -use crate::{clocks::IoClocks, enable_amba_peripheral_clock, slcr::Slcr, time::Hertz}; +use crate::{clocks::IoClocks, enable_amba_periph_clk, slcr::Slcr, time::Hertz}; use super::{EthernetId, PsEthernet as _}; @@ -204,7 +204,7 @@ impl EthernetLowLevel { pub fn reset(&mut self, cycles: usize) { let assert_reset = match self.id { - EthernetId::Eth0 => EthernetReset::builder() + EthernetId::Eth0 => EthernetRst::builder() .with_gem1_ref_rst(false) .with_gem0_ref_rst(true) .with_gem1_rx_rst(false) @@ -212,7 +212,7 @@ impl EthernetLowLevel { .with_gem1_cpu1x_rst(false) .with_gem0_cpu1x_rst(true) .build(), - EthernetId::Eth1 => EthernetReset::builder() + EthernetId::Eth1 => EthernetRst::builder() .with_gem1_ref_rst(true) .with_gem0_ref_rst(false) .with_gem1_rx_rst(true) @@ -227,7 +227,7 @@ impl EthernetLowLevel { for _ in 0..cycles { cortex_ar::asm::nop(); } - regs.reset_ctrl().write_eth(EthernetReset::DEFAULT); + regs.reset_ctrl().write_eth(EthernetRst::DEFAULT); }); } } @@ -235,10 +235,10 @@ impl EthernetLowLevel { #[inline] pub fn enable_peripheral_clock(&mut self) { let periph_sel = match self.id { - EthernetId::Eth0 => crate::PeripheralSelect::Gem0, - EthernetId::Eth1 => crate::PeripheralSelect::Gem1, + EthernetId::Eth0 => crate::PeriphSelect::Gem0, + EthernetId::Eth1 => crate::PeriphSelect::Gem1, }; - enable_amba_peripheral_clock(periph_sel); + enable_amba_periph_clk(periph_sel); } /// Completely configures the clock based on the provided [ClkConfig]. @@ -362,7 +362,7 @@ impl EthernetLowLevel { /// /// These steps do not include any resets or clock configuration. pub fn initialize(&mut self, reset_rx_tx_queue_base_addr: bool) { - let mut ctrl_val = NetworkControl::new_with_raw_value(0); + let mut ctrl_val = NetworkCtrl::new_with_raw_value(0); self.regs.write_net_ctrl(ctrl_val); // Now clear statistics. ctrl_val.set_clear_statistics(true); @@ -370,7 +370,7 @@ impl EthernetLowLevel { self.regs.write_tx_status(TxStatus::new_clear_all()); self.regs.write_rx_status(RxStatus::new_clear_all()); self.regs - .write_interrupt_disable(InterruptControl::new_clear_all()); + .write_interrupt_disable(InterruptCtrl::new_clear_all()); if reset_rx_tx_queue_base_addr { self.regs.write_rx_buf_queue_base_addr(0); self.regs.write_tx_buf_queue_base_addr(0); diff --git a/zynq7000-hal/src/eth/mod.rs b/zynq7000-hal/src/eth/mod.rs index e54644c..88f9501 100644 --- a/zynq7000-hal/src/eth/mod.rs +++ b/zynq7000-hal/src/eth/mod.rs @@ -1,7 +1,7 @@ use arbitrary_int::{u2, u3}; pub use zynq7000::eth::MdcClkDiv; use zynq7000::eth::{ - BurstLength, DmaRxBufSize, GEM_0_BASE_ADDR, GEM_1_BASE_ADDR, InterruptControl, InterruptStatus, + BurstLength, DmaRxBufSize, GEM_0_BASE_ADDR, GEM_1_BASE_ADDR, InterruptCtrl, InterruptStatus, MmioEthernet, RxStatus, TxStatus, }; @@ -32,14 +32,14 @@ use crate::{ IoPeriphPin, mio::{ Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, - Mio52, Mio53, MioPinMarker, MuxConf, Pin, + Mio52, Mio53, MioPinMarker, MuxCfg, Pin, }, }, time::Hertz, }; -pub const MUX_CONF_PHY: MuxConf = MuxConf::new_with_l0(); -pub const MUX_CONF_MDIO: MuxConf = MuxConf::new_with_l3(u3::new(0b100)); +pub const MUX_CONF_PHY: MuxCfg = MuxCfg::new_with_l0(); +pub const MUX_CONF_MDIO: MuxCfg = MuxCfg::new_with_l3(u3::new(0b100)); #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum EthernetId { @@ -284,7 +284,7 @@ pub struct Ethernet { current_clk_divs: ClkDivisors, } -const IRQ_CONTROL: InterruptControl = InterruptControl::builder() +const IRQ_CONTROL: InterruptCtrl = InterruptCtrl::builder() .with_tsu_sec_incr(false) .with_partner_pg_rx(false) .with_auto_negotiation_complete(false) @@ -721,7 +721,7 @@ pub(crate) fn on_interrupt( let mut clear = InterruptStatus::new_with_raw_value(0); let mut tx_status_clear = TxStatus::new_with_raw_value(0); let mut rx_status_clear = RxStatus::new_with_raw_value(0); - let mut disable = InterruptControl::new_with_raw_value(0); + let mut disable = InterruptCtrl::new_with_raw_value(0); let mut result = InterruptResult::default(); if status.frame_sent() { diff --git a/zynq7000-hal/src/gic.rs b/zynq7000-hal/src/gic.rs index 516d09c..7b71d02 100644 --- a/zynq7000-hal/src/gic.rs +++ b/zynq7000-hal/src/gic.rs @@ -10,7 +10,7 @@ use arbitrary_int::Number; use cortex_ar::interrupt; use zynq7000::gic::{ - Dcr, Gicc, Gicd, Icr, InterruptSignalRegister, MmioGicc, MmioGicd, PriorityRegister, + Dcr, GicCpuInterface, GicDistributor, Icr, InterruptSignalRegister, MmioGicCpuInterface, MmioGicDistributor, PriorityReg, }; const SPURIOUS_INTERRUPT_ID: u32 = 1023; @@ -223,15 +223,15 @@ pub struct InvalidSgiInterruptId(pub usize); /// For the handling of the interrupts, you can use the [GicInterruptHelper] which assumes a /// properly configured GIC. pub struct GicConfigurator { - pub gicc: MmioGicc<'static>, - pub gicd: MmioGicd<'static>, + pub gicc: MmioGicCpuInterface<'static>, + pub gicd: MmioGicDistributor<'static>, } impl GicConfigurator { /// Create a new GIC controller instance and calls [Self::initialize] to perform /// strongly recommended initialization routines for the GIC. #[inline] - pub fn new_with_init(gicc: MmioGicc<'static>, gicd: MmioGicd<'static>) -> Self { + pub fn new_with_init(gicc: MmioGicCpuInterface<'static>, gicd: MmioGicDistributor<'static>) -> Self { let mut gic = GicConfigurator { gicc, gicd }; gic.initialize(); gic @@ -247,8 +247,8 @@ impl GicConfigurator { #[inline] pub unsafe fn steal() -> Self { GicConfigurator { - gicc: unsafe { Gicc::new_mmio_fixed() }, - gicd: unsafe { Gicd::new_mmio_fixed() }, + gicc: unsafe { GicCpuInterface::new_mmio_fixed() }, + gicd: unsafe { GicDistributor::new_mmio_fixed() }, } } @@ -280,7 +280,7 @@ impl GicConfigurator { /// 8-bit bitfield. See p.83 of the ARM GICv1 architecture specification. pub fn set_priority_mask(&mut self, mask: u8) { self.gicc - .write_pmr(PriorityRegister::new_with_raw_value(mask as u32)); + .write_pmr(PriorityReg::new_with_raw_value(mask as u32)); } /// Set the sensitivity of a the Programmable Logic SPI interrupts. @@ -484,12 +484,12 @@ impl GicConfigurator { /// Helper structure which should only be used inside the interrupt handler once the GIC has /// been configured with the [GicConfigurator]. -pub struct GicInterruptHelper(MmioGicc<'static>); +pub struct GicInterruptHelper(MmioGicCpuInterface<'static>); impl GicInterruptHelper { /// Create the interrupt helper with the fixed GICC MMIO instance. pub const fn new() -> Self { - GicInterruptHelper(unsafe { Gicc::new_mmio_fixed() }) + GicInterruptHelper(unsafe { GicCpuInterface::new_mmio_fixed() }) } /// Acknowledges an interrupt by reading the IAR register and returning the interrupt context diff --git a/zynq7000-hal/src/gpio/ll.rs b/zynq7000-hal/src/gpio/ll.rs index 9313681..bc16688 100644 --- a/zynq7000-hal/src/gpio/ll.rs +++ b/zynq7000-hal/src/gpio/ll.rs @@ -4,7 +4,7 @@ use zynq7000::gpio::{Gpio, MaskedOutput, MmioGpio}; use crate::slcr::Slcr; -use super::{PinIsOutputOnly, mio::MuxConf}; +use super::{PinIsOutputOnly, mio::MuxCfg}; #[derive(Debug, Clone, Copy)] pub enum PinOffset { @@ -68,7 +68,7 @@ impl LowLevelGpio { let (offset, dirm, outen) = self.get_dirm_outen_regs_and_local_offset(); if self.offset.is_mio() { // Tri-state bit must be 0 for the output driver to work. - self.reconfigure_slcr_mio_cfg(false, None, Some(MuxConf::new_for_gpio())); + self.reconfigure_slcr_mio_cfg(false, None, Some(MuxCfg::new_for_gpio())); } let mut curr_dirm = unsafe { core::ptr::read_volatile(dirm) }; curr_dirm |= 1 << offset; @@ -100,7 +100,7 @@ impl LowLevelGpio { self.reconfigure_slcr_mio_cfg( false, Some(with_internal_pullup), - Some(MuxConf::new_for_gpio()), + Some(MuxCfg::new_for_gpio()), ); } let mut curr_dirm = unsafe { core::ptr::read_volatile(dirm) }; @@ -124,7 +124,7 @@ impl LowLevelGpio { if offset_raw == 7 || offset_raw == 8 { return Err(PinIsOutputOnly); } - self.reconfigure_slcr_mio_cfg(true, Some(false), Some(MuxConf::new_for_gpio())); + self.reconfigure_slcr_mio_cfg(true, Some(false), Some(MuxCfg::new_for_gpio())); } self.configure_input_pin(); Ok(()) @@ -137,14 +137,14 @@ impl LowLevelGpio { if offset_raw == 7 || offset_raw == 8 { return Err(PinIsOutputOnly); } - self.reconfigure_slcr_mio_cfg(true, Some(true), Some(MuxConf::new_for_gpio())); + self.reconfigure_slcr_mio_cfg(true, Some(true), Some(MuxCfg::new_for_gpio())); } self.configure_input_pin(); Ok(()) } /// Convert the pin into an IO peripheral pin. - pub fn configure_as_io_periph_pin(&mut self, mux_conf: MuxConf, pullup: Option) { + pub fn configure_as_io_periph_pin(&mut self, mux_conf: MuxCfg, pullup: Option) { self.reconfigure_slcr_mio_cfg(false, pullup, Some(mux_conf)); } @@ -233,7 +233,7 @@ impl LowLevelGpio { &mut self, tristate: bool, pullup: Option, - mux_conf: Option, + mux_conf: Option, ) { let raw_offset = self.offset.offset(); // Safety: We only modify the MIO config of the pin. @@ -243,7 +243,7 @@ impl LowLevelGpio { // re-configuration which might also be potentially unsafe at run-time. let mio_cfg = slcr_wrapper.regs().read_mio_pins(raw_offset).unwrap(); if (pullup.is_some() && mio_cfg.pullup() != pullup.unwrap()) - || (mux_conf.is_some() && MuxConf::from(mio_cfg) != mux_conf.unwrap()) + || (mux_conf.is_some() && MuxCfg::from(mio_cfg) != mux_conf.unwrap()) || tristate != mio_cfg.tri_enable() { slcr_wrapper.modify(|mut_slcr| { diff --git a/zynq7000-hal/src/gpio/mio.rs b/zynq7000-hal/src/gpio/mio.rs index 74185ff..aff66ad 100644 --- a/zynq7000-hal/src/gpio/mio.rs +++ b/zynq7000-hal/src/gpio/mio.rs @@ -7,14 +7,14 @@ use arbitrary_int::{u2, u3}; use zynq7000::gpio::MmioGpio; #[derive(Debug, Copy, Clone, PartialEq, Eq)] -pub struct MuxConf { +pub struct MuxCfg { l3: u3, l2: u2, l1: bool, l0: bool, } -impl From for MuxConf { +impl From for MuxCfg { fn from(value: zynq7000::slcr::mio::Config) -> Self { Self::new( value.l0_sel(), @@ -25,7 +25,7 @@ impl From for MuxConf { } } -impl MuxConf { +impl MuxCfg { #[inline] pub const fn new(l0: bool, l1: bool, l2: u2, l3: u3) -> Self { Self { l3, l2, l1, l0 } diff --git a/zynq7000-hal/src/gpio/mod.rs b/zynq7000-hal/src/gpio/mod.rs index 29afee9..a5091e9 100644 --- a/zynq7000-hal/src/gpio/mod.rs +++ b/zynq7000-hal/src/gpio/mod.rs @@ -14,12 +14,12 @@ pub mod mio; use core::convert::Infallible; use ll::PinOffset; -use mio::{MioPinMarker, MuxConf}; +use mio::{MioPinMarker, MuxCfg}; use crate::gpio::ll::LowLevelGpio; -use crate::{enable_amba_peripheral_clock, slcr::Slcr}; +use crate::{enable_amba_periph_clk, slcr::Slcr}; pub use embedded_hal::digital::PinState; -use zynq7000::{gpio::MmioGpio, slcr::reset::GpioClockReset}; +use zynq7000::{gpio::MmioGpio, slcr::reset::GpioClkRst}; #[derive(Debug, thiserror::Error)] #[error("MIO pins 7 and 8 can only be output pins")] @@ -33,7 +33,7 @@ pub struct GpioPins { impl GpioPins { pub fn new(gpio: MmioGpio) -> Self { - enable_amba_peripheral_clock(crate::PeripheralSelect::Gpio); + enable_amba_periph_clk(crate::PeriphSelect::Gpio); Self { mio: mio::Pins::new(unsafe { gpio.clone() }), emio: emio::Pins::new(gpio), @@ -47,11 +47,11 @@ pub fn reset() { unsafe { Slcr::with(|regs| { regs.reset_ctrl() - .write_gpio(GpioClockReset::builder().with_gpio_cpu1x_rst(true).build()); + .write_gpio(GpioClkRst::builder().with_gpio_cpu1x_rst(true).build()); // Keep it in reset for one cycle.. not sure if this is necessary. cortex_ar::asm::nop(); regs.reset_ctrl() - .write_gpio(GpioClockReset::builder().with_gpio_cpu1x_rst(false).build()); + .write_gpio(GpioClkRst::builder().with_gpio_cpu1x_rst(false).build()); }); } } @@ -66,7 +66,7 @@ pub enum PinMode { InputFloating, InputPullUp, /// MIO-only peripheral pin configuration - MioIoPeriph(MuxConf), + MioIoPeriph(MuxCfg), } #[derive(Debug, thiserror::Error)] @@ -380,13 +380,13 @@ impl embedded_hal::digital::InputPin for Input { /// IO peripheral pin. pub struct IoPeriphPin { pin: LowLevelGpio, - mux_conf: MuxConf, + mux_conf: MuxCfg, } impl IoPeriphPin { /// Constructor for IO peripheral pins where only the multiplexer and pullup configuration /// need to be changed. - pub fn new(pin: impl MioPinMarker, mux_conf: MuxConf, pullup: Option) -> Self { + pub fn new(pin: impl MioPinMarker, mux_conf: MuxCfg, pullup: Option) -> Self { let mut low_level = LowLevelGpio::new(PinOffset::Mio(pin.offset())); low_level.configure_as_io_periph_pin(mux_conf, pullup); Self { @@ -404,7 +404,7 @@ impl IoPeriphPin { low_level.set_mio_pin_config(config); Self { pin: low_level, - mux_conf: MuxConf::new( + mux_conf: MuxCfg::new( config.l0_sel(), config.l1_sel(), config.l2_sel(), @@ -423,7 +423,7 @@ impl IoPeriphPin { low_level.set_mio_pin_config_with_unlocked_slcr(slcr, config); Self { pin: low_level, - mux_conf: MuxConf::new( + mux_conf: MuxCfg::new( config.l0_sel(), config.l1_sel(), config.l2_sel(), diff --git a/zynq7000-hal/src/gtc.rs b/zynq7000-hal/src/gtc.rs index 782c45a..272957f 100644 --- a/zynq7000-hal/src/gtc.rs +++ b/zynq7000-hal/src/gtc.rs @@ -4,7 +4,7 @@ //! //! - [GTC ticks example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/gtc-ticks.rs) //! - [Embassy Timer Driver](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq7000-embassy/src/lib.rs) -use zynq7000::gtc::MmioGtc; +use zynq7000::gtc::MmioGlobalTimerCounter; use crate::{clocks::ArmClocks, time::Hertz}; @@ -13,21 +13,21 @@ use crate::{clocks::ArmClocks, time::Hertz}; /// This structure also allows an optional clock member, which is required for the /// [frequency_to_ticks] function and the [embedded_hal::delay::DelayNs] implementation /// to work. -pub struct Gtc { - regs: MmioGtc<'static>, +pub struct GlobalTimerCounter { + regs: MmioGlobalTimerCounter<'static>, cpu_3x2x_clock: Option, } -unsafe impl Send for Gtc {} +unsafe impl Send for GlobalTimerCounter {} pub const fn frequency_to_ticks(clock: Hertz, frequency: Hertz) -> u32 { clock.raw().div_ceil(frequency.raw()) } -impl Gtc { +impl GlobalTimerCounter { /// Create a peripheral driver from a MMIO GTC block. #[inline] - pub const fn new(_regs: MmioGtc<'static>, clocks: &ArmClocks) -> Self { + pub const fn new(_regs: MmioGlobalTimerCounter<'static>, clocks: &ArmClocks) -> Self { unsafe { Self::steal_fixed(Some(clocks.cpu_3x2x_clk())) } } @@ -42,7 +42,7 @@ impl Gtc { #[inline] pub const unsafe fn steal_fixed(cpu_3x2x_clk: Option) -> Self { Self { - regs: unsafe { zynq7000::gtc::Gtc::new_mmio_fixed() }, + regs: unsafe { zynq7000::gtc::GlobalTimerCounter::new_mmio_fixed() }, cpu_3x2x_clock: cpu_3x2x_clk, } } @@ -157,7 +157,7 @@ impl Gtc { } /// GTC can be used for blocking delays. -impl embedded_hal::delay::DelayNs for Gtc { +impl embedded_hal::delay::DelayNs for GlobalTimerCounter { fn delay_ns(&mut self, ns: u32) { if self.cpu_3x2x_clock.is_none() { return; diff --git a/zynq7000-hal/src/i2c.rs b/zynq7000-hal/src/i2c.rs index 139a927..17034bb 100644 --- a/zynq7000-hal/src/i2c.rs +++ b/zynq7000-hal/src/i2c.rs @@ -1,8 +1,8 @@ use arbitrary_int::{u2, u3, u6}; use embedded_hal::i2c::NoAcknowledgeSource; use zynq7000::{ - i2c::{Control, I2C_0_BASE_ADDR, I2C_1_BASE_ADDR, InterruptStatus, MmioI2c, TransferSize}, - slcr::reset::DualClockReset, + i2c::{Ctrl, I2C_0_BASE_ADDR, I2C_1_BASE_ADDR, InterruptStatus, MmioI2c, TransferSize}, + slcr::reset::DualClkRst, }; #[cfg(not(feature = "7z010-7z007s-clg225"))] @@ -11,20 +11,20 @@ use crate::gpio::mio::{ Mio41, Mio42, Mio43, Mio44, Mio45, Mio46, Mio47, Mio50, Mio51, }; use crate::{ - enable_amba_peripheral_clock, + enable_amba_periph_clk, gpio::{ IoPeriphPin, mio::{ Mio10, Mio11, Mio12, Mio13, Mio14, Mio15, Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, Mio48, Mio49, Mio52, Mio53, MioPinMarker, - MuxConf, Pin, + MuxCfg, Pin, }, }, slcr::Slcr, time::Hertz, }; -pub const I2C_MUX_CONF: MuxConf = MuxConf::new_with_l3(u3::new(0b010)); +pub const I2C_MUX_CONF: MuxCfg = MuxCfg::new_with_l3(u3::new(0b010)); pub const FIFO_DEPTH: usize = 16; /// Maximum read size in one read operation. pub const MAX_READ_SIZE: usize = 255; @@ -345,13 +345,13 @@ impl I2c { pub fn new_generic(id: I2cId, mut regs: MmioI2c<'static>, clk_cfg: ClockConfig) -> Self { let periph_sel = match id { - I2cId::I2c0 => crate::PeripheralSelect::I2c0, - I2cId::I2c1 => crate::PeripheralSelect::I2c1, + I2cId::I2c0 => crate::PeriphSelect::I2c0, + I2cId::I2c1 => crate::PeriphSelect::I2c1, }; - enable_amba_peripheral_clock(periph_sel); + enable_amba_periph_clk(periph_sel); //reset(id); regs.write_cr( - Control::builder() + Ctrl::builder() .with_div_a(u2::new(clk_cfg.div_a())) .with_div_b(u6::new(clk_cfg.div_b())) .with_clear_fifo(true) @@ -360,7 +360,7 @@ impl I2c { .with_acken(false) .with_addressing(true) .with_mode(zynq7000::i2c::Mode::Master) - .with_dir(zynq7000::i2c::Direction::Transmitter) + .with_dir(zynq7000::i2c::Dir::Transmitter) .build(), ); Self { regs } @@ -399,7 +399,7 @@ impl I2c { cr.set_acken(true); cr.set_mode(zynq7000::i2c::Mode::Master); cr.set_clear_fifo(true); - cr.set_dir(zynq7000::i2c::Direction::Transmitter); + cr.set_dir(zynq7000::i2c::Dir::Transmitter); if !generate_stop { cr.set_hold_bus(true); } @@ -498,7 +498,7 @@ impl I2c { cr.set_acken(true); cr.set_mode(zynq7000::i2c::Mode::Master); cr.set_clear_fifo(true); - cr.set_dir(zynq7000::i2c::Direction::Receiver); + cr.set_dir(zynq7000::i2c::Dir::Receiver); if data.len() > FIFO_DEPTH { cr.set_hold_bus(true); } @@ -640,11 +640,11 @@ impl embedded_hal::i2c::I2c for I2c { #[inline] pub fn reset(id: I2cId) { let assert_reset = match id { - I2cId::I2c0 => DualClockReset::builder() + I2cId::I2c0 => DualClkRst::builder() .with_periph1_cpu1x_rst(false) .with_periph0_cpu1x_rst(true) .build(), - I2cId::I2c1 => DualClockReset::builder() + I2cId::I2c1 => DualClkRst::builder() .with_periph1_cpu1x_rst(true) .with_periph0_cpu1x_rst(false) .build(), @@ -657,7 +657,7 @@ pub fn reset(id: I2cId) { for _ in 0..3 { cortex_ar::asm::nop(); } - regs.reset_ctrl().write_i2c(DualClockReset::DEFAULT); + regs.reset_ctrl().write_i2c(DualClkRst::DEFAULT); }); } } diff --git a/zynq7000-hal/src/l2_cache.rs b/zynq7000-hal/src/l2_cache.rs index 5a6c4a0..813493d 100644 --- a/zynq7000-hal/src/l2_cache.rs +++ b/zynq7000-hal/src/l2_cache.rs @@ -3,7 +3,7 @@ use core::sync::atomic::compiler_fence; use arbitrary_int::{u2, u3}; pub use zynq7000::l2_cache::LatencyConfig; use zynq7000::l2_cache::{ - Associativity, AuxControl, Control, InterruptControl, MmioL2Cache, ReplacementPolicy, WaySize, + Associativity, AuxControl, Ctrl, InterruptControl, MmioL2Cache, ReplacementPolicy, WaySize, }; use crate::slcr::Slcr; @@ -60,7 +60,7 @@ pub fn init( tag_ram_latency: LatencyConfig, data_ram_latency: LatencyConfig, ) { - l2c_mmio.write_control(Control::new_disabled()); + l2c_mmio.write_control(Ctrl::new_disabled()); l2c_mmio.write_aux_control(AUX_CTRL_DEFAULT); l2c_mmio.write_tag_ram_latency(tag_ram_latency); l2c_mmio.write_data_ram_latency(data_ram_latency); @@ -77,5 +77,5 @@ pub fn init( slcr.write_magic_l2c_register(SLCR_L2C_CONFIG_MAGIC_VALUE); }); } - l2c_mmio.write_control(Control::new_enabled()); + l2c_mmio.write_control(Ctrl::new_enabled()); } diff --git a/zynq7000-hal/src/lib.rs b/zynq7000-hal/src/lib.rs index 7d0f45b..620d5f0 100644 --- a/zynq7000-hal/src/lib.rs +++ b/zynq7000-hal/src/lib.rs @@ -40,7 +40,7 @@ pub enum BootDevice { } #[derive(Debug, Copy, Clone)] -pub enum BootPllConfig { +pub enum BootPllCfg { Enabled, Bypassed, } @@ -48,7 +48,7 @@ pub enum BootPllConfig { #[derive(Debug)] pub struct BootMode { boot_mode: Option, - pll_config: BootPllConfig, + pll_config: BootPllCfg, } impl BootMode { @@ -82,9 +82,9 @@ impl BootMode { _ => None, }; let pll_config = if (raw_register >> 4) & 0b1 == 0 { - BootPllConfig::Enabled + BootPllCfg::Enabled } else { - BootPllConfig::Bypassed + BootPllCfg::Bypassed }; Self { boot_mode, @@ -95,7 +95,7 @@ impl BootMode { self.boot_mode } - pub const fn pll_enable(&self) -> BootPllConfig { + pub const fn pll_enable(&self) -> BootPllCfg { self.pll_config } } @@ -104,7 +104,7 @@ impl BootMode { /// system (PS). /// /// The Zynq-7000 TRM p.32 specifies more information about this register and how to use it. -pub fn configure_level_shifter(config: zynq7000::slcr::LevelShifterConfig) { +pub fn cfg_level_shifter(config: zynq7000::slcr::LevelShifterCfg) { // Safety: We only manipulate the level shift registers. unsafe { Slcr::with(|slcr_unlocked| { @@ -114,7 +114,7 @@ pub fn configure_level_shifter(config: zynq7000::slcr::LevelShifterConfig) { } #[derive(Debug, PartialEq, Eq, Clone, Copy)] -pub enum PeripheralSelect { +pub enum PeriphSelect { Smc = 24, Lqspi = 23, Gpio = 22, @@ -138,29 +138,29 @@ pub enum PeripheralSelect { /// Enable the AMBA peripheral clock, which is required to read the registers of a peripheral /// block. #[inline] -pub fn enable_amba_peripheral_clock(select: PeripheralSelect) { +pub fn enable_amba_periph_clk(select: PeriphSelect) { unsafe { Slcr::with(|regs| { regs.clk_ctrl().modify_aper_clk_ctrl(|mut val| { match select { - PeripheralSelect::Smc => val.set_smc_1x_clk_act(true), - PeripheralSelect::Lqspi => val.set_lqspi_1x_clk_act(true), - PeripheralSelect::Gpio => val.set_gpio_1x_clk_act(true), - PeripheralSelect::Uart1 => val.set_uart_1_1x_clk_act(true), - PeripheralSelect::Uart0 => val.set_uart_0_1x_clk_act(true), - PeripheralSelect::I2c1 => val.set_i2c_1_1x_clk_act(true), - PeripheralSelect::I2c0 => val.set_i2c_0_1x_clk_act(true), - PeripheralSelect::Can1 => val.set_can_1_1x_clk_act(true), - PeripheralSelect::Can0 => val.set_can_0_1x_clk_act(true), - PeripheralSelect::Spi1 => val.set_spi_1_1x_clk_act(true), - PeripheralSelect::Spi0 => val.set_spi_1_1x_clk_act(true), - PeripheralSelect::Sdio1 => val.set_sdio_1_1x_clk_act(true), - PeripheralSelect::Sdio0 => val.set_sdio_0_1x_clk_act(true), - PeripheralSelect::Gem1 => val.set_gem_1_1x_clk_act(true), - PeripheralSelect::Gem0 => val.set_gem_0_1x_clk_act(true), - PeripheralSelect::Usb1 => val.set_usb_1_cpu_1x_clk_act(true), - PeripheralSelect::Usb0 => val.set_usb_0_cpu_1x_clk_act(true), - PeripheralSelect::Dma => val.set_dma_cpu_2x_clk_act(true), + PeriphSelect::Smc => val.set_smc_1x_clk_act(true), + PeriphSelect::Lqspi => val.set_lqspi_1x_clk_act(true), + PeriphSelect::Gpio => val.set_gpio_1x_clk_act(true), + PeriphSelect::Uart1 => val.set_uart_1_1x_clk_act(true), + PeriphSelect::Uart0 => val.set_uart_0_1x_clk_act(true), + PeriphSelect::I2c1 => val.set_i2c_1_1x_clk_act(true), + PeriphSelect::I2c0 => val.set_i2c_0_1x_clk_act(true), + PeriphSelect::Can1 => val.set_can_1_1x_clk_act(true), + PeriphSelect::Can0 => val.set_can_0_1x_clk_act(true), + PeriphSelect::Spi1 => val.set_spi_1_1x_clk_act(true), + PeriphSelect::Spi0 => val.set_spi_1_1x_clk_act(true), + PeriphSelect::Sdio1 => val.set_sdio_1_1x_clk_act(true), + PeriphSelect::Sdio0 => val.set_sdio_0_1x_clk_act(true), + PeriphSelect::Gem1 => val.set_gem_1_1x_clk_act(true), + PeriphSelect::Gem0 => val.set_gem_0_1x_clk_act(true), + PeriphSelect::Usb1 => val.set_usb_1_cpu_1x_clk_act(true), + PeriphSelect::Usb0 => val.set_usb_0_cpu_1x_clk_act(true), + PeriphSelect::Dma => val.set_dma_cpu_2x_clk_act(true), } val }) @@ -171,29 +171,29 @@ pub fn enable_amba_peripheral_clock(select: PeripheralSelect) { /// Disable the AMBA peripheral clock, which is required to read the registers of a peripheral /// block. #[inline] -pub fn disable_amba_peripheral_clock(select: PeripheralSelect) { +pub fn disable_amba_periph_clk(select: PeriphSelect) { unsafe { Slcr::with(|regs| { regs.clk_ctrl().modify_aper_clk_ctrl(|mut val| { match select { - PeripheralSelect::Smc => val.set_smc_1x_clk_act(false), - PeripheralSelect::Lqspi => val.set_lqspi_1x_clk_act(false), - PeripheralSelect::Gpio => val.set_gpio_1x_clk_act(false), - PeripheralSelect::Uart1 => val.set_uart_1_1x_clk_act(false), - PeripheralSelect::Uart0 => val.set_uart_0_1x_clk_act(false), - PeripheralSelect::I2c1 => val.set_i2c_1_1x_clk_act(false), - PeripheralSelect::I2c0 => val.set_i2c_0_1x_clk_act(false), - PeripheralSelect::Can1 => val.set_can_1_1x_clk_act(false), - PeripheralSelect::Can0 => val.set_can_0_1x_clk_act(false), - PeripheralSelect::Spi1 => val.set_spi_1_1x_clk_act(false), - PeripheralSelect::Spi0 => val.set_spi_1_1x_clk_act(false), - PeripheralSelect::Sdio1 => val.set_sdio_1_1x_clk_act(false), - PeripheralSelect::Sdio0 => val.set_sdio_0_1x_clk_act(false), - PeripheralSelect::Gem1 => val.set_gem_1_1x_clk_act(false), - PeripheralSelect::Gem0 => val.set_gem_0_1x_clk_act(false), - PeripheralSelect::Usb1 => val.set_usb_1_cpu_1x_clk_act(false), - PeripheralSelect::Usb0 => val.set_usb_0_cpu_1x_clk_act(false), - PeripheralSelect::Dma => val.set_dma_cpu_2x_clk_act(false), + PeriphSelect::Smc => val.set_smc_1x_clk_act(false), + PeriphSelect::Lqspi => val.set_lqspi_1x_clk_act(false), + PeriphSelect::Gpio => val.set_gpio_1x_clk_act(false), + PeriphSelect::Uart1 => val.set_uart_1_1x_clk_act(false), + PeriphSelect::Uart0 => val.set_uart_0_1x_clk_act(false), + PeriphSelect::I2c1 => val.set_i2c_1_1x_clk_act(false), + PeriphSelect::I2c0 => val.set_i2c_0_1x_clk_act(false), + PeriphSelect::Can1 => val.set_can_1_1x_clk_act(false), + PeriphSelect::Can0 => val.set_can_0_1x_clk_act(false), + PeriphSelect::Spi1 => val.set_spi_1_1x_clk_act(false), + PeriphSelect::Spi0 => val.set_spi_1_1x_clk_act(false), + PeriphSelect::Sdio1 => val.set_sdio_1_1x_clk_act(false), + PeriphSelect::Sdio0 => val.set_sdio_0_1x_clk_act(false), + PeriphSelect::Gem1 => val.set_gem_1_1x_clk_act(false), + PeriphSelect::Gem0 => val.set_gem_0_1x_clk_act(false), + PeriphSelect::Usb1 => val.set_usb_1_cpu_1x_clk_act(false), + PeriphSelect::Usb0 => val.set_usb_0_cpu_1x_clk_act(false), + PeriphSelect::Dma => val.set_dma_cpu_2x_clk_act(false), } val }) diff --git a/zynq7000-hal/src/spi/mod.rs b/zynq7000-hal/src/spi/mod.rs index 62449d1..cb59564 100644 --- a/zynq7000-hal/src/spi/mod.rs +++ b/zynq7000-hal/src/spi/mod.rs @@ -2,11 +2,11 @@ use core::convert::Infallible; use crate::clocks::Clocks; -use crate::enable_amba_peripheral_clock; +use crate::enable_amba_periph_clk; use crate::gpio::IoPeriphPin; use crate::gpio::mio::{ Mio10, Mio11, Mio12, Mio13, Mio14, Mio15, Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, - Mio35, Mio36, Mio37, Mio38, Mio39, MioPinMarker, MuxConf, Pin, + Mio35, Mio36, Mio37, Mio38, Mio39, MioPinMarker, MuxCfg, Pin, }; #[cfg(not(feature = "7z010-7z007s-clg225"))] use crate::gpio::mio::{ @@ -19,9 +19,9 @@ use arbitrary_int::{Number, u3, u4, u6}; use embedded_hal::delay::DelayNs; pub use embedded_hal::spi::Mode; use embedded_hal::spi::{MODE_0, MODE_1, MODE_2, MODE_3, SpiBus as _}; -use zynq7000::slcr::reset::DualRefAndClockReset; +use zynq7000::slcr::reset::DualRefAndClkRst; use zynq7000::spi::{ - BaudDivSelect, DelayControl, FifoWrite, InterruptControl, InterruptMask, InterruptStatus, + BaudDivSel, DelayControl, FifoWrite, InterruptControl, InterruptMask, InterruptStatus, MmioSpi, SPI_0_BASE_ADDR, SPI_1_BASE_ADDR, }; @@ -81,7 +81,7 @@ pub trait SsPin: MioPinMarker { const GROUP: usize; } -pub const SPI_MUX_CONF: MuxConf = MuxConf::new_with_l3(u3::new(0b101)); +pub const SPI_MUX_CONF: MuxCfg = MuxCfg::new_with_l3(u3::new(0b101)); // SPI0, choice 1 #[cfg(not(feature = "7z010-7z007s-clg225"))] @@ -364,14 +364,14 @@ pub enum SlaveSelectConfig { #[derive(Debug, Copy, Clone)] pub struct Config { - baud_div: BaudDivSelect, + baud_div: BaudDivSel, init_mode: Mode, ss_config: SlaveSelectConfig, with_ext_decoding: bool, } impl Config { - pub fn new(baud_div: BaudDivSelect, init_mode: Mode, ss_config: SlaveSelectConfig) -> Self { + pub fn new(baud_div: BaudDivSel, init_mode: Mode, ss_config: SlaveSelectConfig) -> Self { Self { baud_div, init_mode, @@ -493,7 +493,7 @@ impl SpiLowLevel { }; self.regs.write_cr( - zynq7000::spi::Config::builder() + zynq7000::spi::Cfg::builder() .with_modefail_gen_en(false) .with_manual_start(false) .with_manual_start_enable(man_start) @@ -819,10 +819,10 @@ impl Spi { config: Config, ) -> Self { let periph_sel = match id { - SpiId::Spi0 => crate::PeripheralSelect::Spi0, - SpiId::Spi1 => crate::PeripheralSelect::Spi1, + SpiId::Spi0 => crate::PeriphSelect::Spi0, + SpiId::Spi1 => crate::PeriphSelect::Spi1, }; - enable_amba_peripheral_clock(periph_sel); + enable_amba_periph_clk(periph_sel); let sclk = clocks.spi_clk() / config.baud_div.div_value() as u32; let mut spi = Self { inner: SpiLowLevel { regs, id }, @@ -1106,13 +1106,13 @@ impl embedded_hal::spi::SpiDevice for SpiWithHwCs { #[inline] pub fn reset(id: SpiId) { let assert_reset = match id { - SpiId::Spi0 => DualRefAndClockReset::builder() + SpiId::Spi0 => DualRefAndClkRst::builder() .with_periph1_ref_rst(false) .with_periph0_ref_rst(true) .with_periph1_cpu1x_rst(false) .with_periph0_cpu1x_rst(true) .build(), - SpiId::Spi1 => DualRefAndClockReset::builder() + SpiId::Spi1 => DualRefAndClkRst::builder() .with_periph1_ref_rst(true) .with_periph0_ref_rst(false) .with_periph1_cpu1x_rst(true) @@ -1127,7 +1127,7 @@ pub fn reset(id: SpiId) { for _ in 0..3 { cortex_ar::asm::nop(); } - regs.reset_ctrl().write_spi(DualRefAndClockReset::DEFAULT); + regs.reset_ctrl().write_spi(DualRefAndClkRst::DEFAULT); }); } } diff --git a/zynq7000-hal/src/time.rs b/zynq7000-hal/src/time.rs index 9808028..a61724c 100644 --- a/zynq7000-hal/src/time.rs +++ b/zynq7000-hal/src/time.rs @@ -4,12 +4,15 @@ /// Hertz pub type Hertz = fugit::HertzU32; +pub type Hz = Hertz; /// KiloHertz pub type KiloHertz = fugit::KilohertzU32; +pub type KHz = KiloHertz; /// MegaHertz pub type MegaHertz = fugit::MegahertzU32; +pub type MHz = MegaHertz; // Period based diff --git a/zynq7000-hal/src/ttc.rs b/zynq7000-hal/src/ttc.rs index d5139e7..f259b9e 100644 --- a/zynq7000-hal/src/ttc.rs +++ b/zynq7000-hal/src/ttc.rs @@ -13,7 +13,7 @@ use crate::{ clocks::ArmClocks, gpio::{ IoPeriphPin, - mio::{Mio28, Mio29, Mio30, Mio31, MioPinMarker, MuxConf, Pin}, + mio::{Mio28, Mio29, Mio30, Mio31, MioPinMarker, MuxCfg, Pin}, }, time::Hertz, }; @@ -55,7 +55,7 @@ impl PsTtc for MmioTtc<'static> { } } -pub const TTC_MUX_CONF: MuxConf = MuxConf::new_with_l3(u3::new(0b110)); +pub const TTC_MUX_CONF: MuxCfg = MuxCfg::new_with_l3(u3::new(0b110)); pub trait ClockInPin: MioPinMarker { const ID: TtcId; @@ -172,7 +172,7 @@ impl TtcChannel { #[derive(Debug, thiserror::Error)] #[error("invalid TTC pin configuration")] -pub struct InvalidTtcPinConfigError(pub MuxConf); +pub struct InvalidTtcPinConfigError(pub MuxCfg); #[derive(Debug, thiserror::Error)] #[error("frequency is zero")] @@ -186,7 +186,7 @@ pub enum TtcConstructionError { FrequencyIsZero(#[from] FrequencyIsZeroError), } -pub fn calculate_prescaler_reg_and_interval_ticks( +pub fn calc_prescaler_reg_and_interval_ticks( mut ref_clk: Hertz, freq: Hertz, ) -> (Option, u16) { @@ -246,7 +246,7 @@ impl Pwm { if freq.raw() == 0 { return Err(FrequencyIsZeroError); } - let (prescaler_reg, tick_val) = calculate_prescaler_reg_and_interval_ticks(ref_clk, freq); + let (prescaler_reg, tick_val) = calc_prescaler_reg_and_interval_ticks(ref_clk, freq); let id = channel.id() as usize; let mut pwm = Self { channel, ref_clk }; pwm.set_up_and_configure_pwm(id, prescaler_reg, tick_val); @@ -262,7 +262,7 @@ impl Pwm { } let id = self.channel.id() as usize; let (prescaler_reg, tick_val) = - calculate_prescaler_reg_and_interval_ticks(self.ref_clk, freq); + calc_prescaler_reg_and_interval_ticks(self.ref_clk, freq); self.set_up_and_configure_pwm(id, prescaler_reg, tick_val); Ok(()) } @@ -320,7 +320,7 @@ impl Pwm { .regs .write_clk_cntr( id, - zynq7000::ttc::ClockControl::builder() + zynq7000::ttc::ClkCtrl::builder() .with_ext_clk_edge(false) .with_clk_src(zynq7000::ttc::ClockSource::Pclk) .with_prescaler(prescaler_reg.unwrap_or(u4::new(0))) diff --git a/zynq7000-hal/src/uart/mod.rs b/zynq7000-hal/src/uart/mod.rs index fb71cb2..2ba63d2 100644 --- a/zynq7000-hal/src/uart/mod.rs +++ b/zynq7000-hal/src/uart/mod.rs @@ -6,7 +6,7 @@ use core::convert::Infallible; use arbitrary_int::u3; use libm::round; use zynq7000::{ - slcr::reset::DualRefAndClockReset, + slcr::reset::DualRefAndClkRst, uart::{ BaudRateDiv, Baudgen, ChMode, ClkSel, FifoTrigger, InterruptControl, MmioUart, Mode, UART_0_BASE, UART_1_BASE, @@ -14,13 +14,13 @@ use zynq7000::{ }; use crate::{ - enable_amba_peripheral_clock, + enable_amba_periph_clk, gpio::{ IoPeriphPin, mio::{ Mio8, Mio9, Mio10, Mio11, Mio12, Mio13, Mio14, Mio15, Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, Mio48, Mio49, Mio52, Mio53, - MioPinMarker, MuxConf, Pin, + MioPinMarker, MuxCfg, Pin, }, }, slcr::Slcr, @@ -45,7 +45,7 @@ pub use rx::*; pub const FIFO_DEPTH: usize = 64; pub const DEFAULT_RX_TRIGGER_LEVEL: u8 = 32; -pub const UART_MUX_CONF: MuxConf = MuxConf::new_with_l3(u3::new(0b111)); +pub const UART_MUX_CONF: MuxCfg = MuxCfg::new_with_l3(u3::new(0b111)); #[derive(Debug, Copy, Clone, PartialEq, Eq)] pub enum UartId { @@ -436,7 +436,7 @@ pub enum UartConstructionError { #[error("missmatch between pins index and passed index")] IdxMissmatch, #[error("invalid pin mux conf for UART")] - InvalidMuxConf(MuxConf), + InvalidMuxConf(MuxCfg), } impl Uart { @@ -491,10 +491,10 @@ impl Uart { cfg: UartConfig, ) -> Uart { let periph_sel = match uart_id { - UartId::Uart0 => crate::PeripheralSelect::Uart0, - UartId::Uart1 => crate::PeripheralSelect::Uart1, + UartId::Uart0 => crate::PeriphSelect::Uart0, + UartId::Uart1 => crate::PeriphSelect::Uart1, }; - enable_amba_peripheral_clock(periph_sel); + enable_amba_periph_clk(periph_sel); reset(uart_id); reg_block.modify_cr(|mut v| { v.set_tx_dis(true); @@ -644,13 +644,13 @@ impl embedded_io::Read for Uart { #[inline] pub fn reset(id: UartId) { let assert_reset = match id { - UartId::Uart0 => DualRefAndClockReset::builder() + UartId::Uart0 => DualRefAndClkRst::builder() .with_periph1_ref_rst(false) .with_periph0_ref_rst(true) .with_periph1_cpu1x_rst(false) .with_periph0_cpu1x_rst(true) .build(), - UartId::Uart1 => DualRefAndClockReset::builder() + UartId::Uart1 => DualRefAndClkRst::builder() .with_periph1_ref_rst(true) .with_periph0_ref_rst(false) .with_periph1_cpu1x_rst(true) @@ -662,7 +662,7 @@ pub fn reset(id: UartId) { regs.reset_ctrl().write_uart(assert_reset); // Keep it in reset for one cycle.. not sure if this is necessary. cortex_ar::asm::nop(); - regs.reset_ctrl().write_uart(DualRefAndClockReset::DEFAULT); + regs.reset_ctrl().write_uart(DualRefAndClkRst::DEFAULT); }); } } diff --git a/zynq7000/src/eth.rs b/zynq7000/src/eth.rs index a60fcf2..ce6ee8e 100644 --- a/zynq7000/src/eth.rs +++ b/zynq7000/src/eth.rs @@ -6,7 +6,7 @@ pub const GEM_1_BASE_ADDR: usize = 0xE000_C000; #[bitbybit::bitfield(u32)] #[derive(Debug)] -pub struct NetworkControl { +pub struct NetworkCtrl { #[bit(18, w)] flush_next_rx_dpram_pkt: bool, #[bit(17, w)] @@ -84,7 +84,7 @@ impl MdcClkDiv { #[bitbybit::bitfield(u32, default = 0x0)] #[derive(Debug)] -pub struct NetworkConfig { +pub struct NetworkCfg { #[bit(30, rw)] ignore_ipg_rx_error: bool, #[bit(29, rw)] @@ -217,7 +217,7 @@ impl DmaRxBufSize { #[bitbybit::bitfield(u32)] #[derive(Debug)] -pub struct DmaConfig { +pub struct DmaCfg { #[bit(24, rw)] discard_when_ahb_full: bool, /// DMA receive buffer size in AHB system memory. @@ -340,7 +340,7 @@ pub struct InterruptStatus { #[bitbybit::bitfield(u32, default = 0x00)] #[derive(Debug)] -pub struct InterruptControl { +pub struct InterruptCtrl { #[bit(26, w)] tsu_sec_incr: bool, /// Marked N/A in datasheet. Probably because external PHYs are used. @@ -380,7 +380,7 @@ pub struct InterruptControl { mgmt_frame_sent: bool, } -impl InterruptControl { +impl InterruptCtrl { pub fn new_clear_all() -> Self { Self::new_with_raw_value(0xFFFF_FFFF) } @@ -430,19 +430,19 @@ pub struct MatchRegister { #[derive(derive_mmio::Mmio)] #[repr(C)] pub struct Ethernet { - net_ctrl: NetworkControl, - net_cfg: NetworkConfig, + net_ctrl: NetworkCtrl, + net_cfg: NetworkCfg, #[mmio(PureRead)] net_status: NetworkStatus, _reserved0: u32, - dma_cfg: DmaConfig, + dma_cfg: DmaCfg, tx_status: TxStatus, rx_buf_queue_base_addr: u32, tx_buf_queue_base_addr: u32, rx_status: RxStatus, interrupt_status: InterruptStatus, - interrupt_enable: InterruptControl, - interrupt_disable: InterruptControl, + interrupt_enable: InterruptCtrl, + interrupt_disable: InterruptCtrl, interrupt_mask: InterruptStatus, phy_maintenance: PhyMaintenance, #[mmio(PureRead)] diff --git a/zynq7000/src/gic.rs b/zynq7000/src/gic.rs index 2d85c88..d364e61 100644 --- a/zynq7000/src/gic.rs +++ b/zynq7000/src/gic.rs @@ -14,7 +14,7 @@ pub struct Dcr { /// Read only bit. This register only returns fixed constants. #[bitbybit::bitfield(u32)] -pub struct TypeRegister { +pub struct TypeReg { #[bits(11..=15, r)] lspi: u5, #[bit(10, r)] @@ -25,7 +25,7 @@ pub struct TypeRegister { it_lines_number: u5, } -impl TypeRegister { +impl TypeReg { pub const SECURITY_EXTNS_BIT: bool = true; /// 31 LSPIs. pub const NUM_LSPI: usize = 0x1f; @@ -38,12 +38,12 @@ impl TypeRegister { pub const NUM_OF_INTERRUPTS: usize = 96; } -pub type Typer = TypeRegister; +pub type Typer = TypeReg; /// GIC Distributor registers. #[derive(derive_mmio::Mmio)] #[repr(C, align(8))] -pub struct Gicd { +pub struct GicDistributor { /// Distributor Control Register pub dcr: Dcr, /// Interrupt Controller Type Register @@ -109,9 +109,9 @@ pub struct Gicd { pub cidr: [u32; 4], } -const_assert_eq!(core::mem::size_of::(), 0x1000); +const_assert_eq!(core::mem::size_of::(), 0x1000); -impl Gicd { +impl GicDistributor { /// Create a new Global Interrupt Controller Distributor MMIO instance at the fixed address of /// the processing system. /// @@ -121,14 +121,14 @@ impl Gicd { /// from multiple threads. The user must ensure that concurrent accesses are safe and do not /// interfere with each other. #[inline] - pub const unsafe fn new_mmio_fixed() -> MmioGicd<'static> { + pub const unsafe fn new_mmio_fixed() -> MmioGicDistributor<'static> { unsafe { Self::new_mmio_at(GICD_BASE_ADDR) } } } /// CPU interface control register. #[bitbybit::bitfield(u32, default = 0x0)] -pub struct Icr { +pub struct InterfaceCtrl { #[bit(4, rw)] sbpr: bool, #[bit(3, rw)] @@ -143,7 +143,7 @@ pub struct Icr { /// Priority Mask Register #[bitbybit::bitfield(u32)] -pub struct PriorityRegister { +pub struct PriorityReg { #[bits(0..=7, rw)] priority: u8, } @@ -161,11 +161,11 @@ pub struct InterruptSignalRegister { /// GIC CPU interface registers. #[derive(derive_mmio::Mmio)] #[repr(C, align(8))] -pub struct Gicc { - /// CPU Interface Control Register. - pub icr: Icr, +pub struct GicCpuInterface { + /// CPU Interface Control Register (ICR). + pub icr: InterfaceCtrl, /// Interrupt Priority Mask Register. - pub pmr: PriorityRegister, + pub pmr: PriorityReg, /// Binary Point Register. pub bpr: u32, /// Interrupt Acknowledge Register. @@ -173,7 +173,7 @@ pub struct Gicc { /// End of Interrupt Register. pub eoir: InterruptSignalRegister, /// Running Priority Register. - pub rpr: PriorityRegister, + pub rpr: PriorityReg, /// Highest Pending Interrupt Register. pub hpir: InterruptSignalRegister, /// Aliased Binary Point Register @@ -184,9 +184,9 @@ pub struct Gicc { pub iidr: u32, } -const_assert_eq!(core::mem::size_of::(), 0x100); +const_assert_eq!(core::mem::size_of::(), 0x100); -impl Gicc { +impl GicCpuInterface { /// Create a new Global Interrupt Controller CPU MMIO instance at the fixed address of the /// processing system. /// @@ -196,7 +196,7 @@ impl Gicc { /// from multiple threads. The user must ensure that concurrent accesses are safe and do not /// interfere with each other. #[inline] - pub const unsafe fn new_mmio_fixed() -> MmioGicc<'static> { + pub const unsafe fn new_mmio_fixed() -> MmioGicCpuInterface<'static> { unsafe { Self::new_mmio_at(GICC_BASE_ADDR) } } } diff --git a/zynq7000/src/gtc.rs b/zynq7000/src/gtc.rs index 845c80e..94b16ab 100644 --- a/zynq7000/src/gtc.rs +++ b/zynq7000/src/gtc.rs @@ -25,7 +25,7 @@ pub struct InterruptStatus { /// Global timer counter. #[derive(derive_mmio::Mmio)] #[repr(C)] -pub struct Gtc { +pub struct GlobalTimerCounter { /// Count register 0, lower 32 bits count_lower: u32, /// Count register 1, upper 32 bits @@ -43,9 +43,9 @@ pub struct Gtc { auto_increment: u32, } -static_assertions::const_assert_eq!(core::mem::size_of::(), 0x1C); +static_assertions::const_assert_eq!(core::mem::size_of::(), 0x1C); -impl Gtc { +impl GlobalTimerCounter { /// Create a new GTC MMIO instance at the fixed base address. /// /// # Safety @@ -54,7 +54,7 @@ impl Gtc { /// from multiple threads. The user must ensure that concurrent accesses are safe and do not /// interfere with each other. #[inline] - pub const unsafe fn new_mmio_fixed() -> MmioGtc<'static> { - unsafe { Gtc::new_mmio_at(GTC_BASE_ADDR) } + pub const unsafe fn new_mmio_fixed() -> MmioGlobalTimerCounter<'static> { + unsafe { GlobalTimerCounter::new_mmio_at(GTC_BASE_ADDR) } } } diff --git a/zynq7000/src/i2c.rs b/zynq7000/src/i2c.rs index d01c6fd..eff1b08 100644 --- a/zynq7000/src/i2c.rs +++ b/zynq7000/src/i2c.rs @@ -6,7 +6,7 @@ pub const I2C_1_BASE_ADDR: usize = 0xE000_5000; #[bitbybit::bitenum(u1, exhaustive = true)] #[derive(Debug)] -pub enum Direction { +pub enum Dir { Receiver = 0b1, Transmitter = 0b0, } @@ -19,7 +19,7 @@ pub enum Mode { } #[bitbybit::bitfield(u32, default = 0x0)] -pub struct Control { +pub struct Ctrl { /// Divides the input PCLK frequency by this value + 1 #[bits(14..=15, rw)] div_a: u2, @@ -44,7 +44,7 @@ pub struct Control { #[bit(1, rw)] mode: Mode, #[bit(0, rw)] - dir: Direction, + dir: Dir, } #[bitbybit::bitfield(u32)] @@ -159,7 +159,7 @@ pub struct TransferSize { #[derive(derive_mmio::Mmio)] #[repr(C)] pub struct I2c { - cr: Control, + cr: Ctrl, #[mmio(PureRead)] sr: Status, addr: Addr, diff --git a/zynq7000/src/l2_cache.rs b/zynq7000/src/l2_cache.rs index 68036d9..28dae2b 100644 --- a/zynq7000/src/l2_cache.rs +++ b/zynq7000/src/l2_cache.rs @@ -18,7 +18,7 @@ pub struct CacheSync { #[bitbybit::bitfield(u32, default = 0x0)] #[derive(Debug)] -pub struct DebugControl { +pub struct DebugCtrl { #[bit(2, rw)] spniden: bool, #[bit(1, rw)] @@ -41,9 +41,9 @@ pub struct CacheId { } #[repr(transparent)] -pub struct Control(u32); +pub struct Ctrl(u32); -impl Control { +impl Ctrl { pub fn new_enabled() -> Self { Self(0x1) } @@ -87,7 +87,7 @@ pub enum Associativity { } #[bitbybit::bitfield(u32, default = 0x0)] -pub struct AuxControl { +pub struct AuxCtrl { #[bit(30, rw)] early_bresp_enable: bool, #[bit(29, rw)] @@ -127,7 +127,7 @@ pub struct AuxControl { #[bitbybit::bitfield(u32, default = 0x0)] #[derive(Debug, PartialEq, Eq)] -pub struct LatencyConfig { +pub struct LatencyCfg { /// Latency is the numerical value + 1 cycles. #[bits(8..=10, rw)] write_access_latency: u3, @@ -165,7 +165,7 @@ pub struct InterruptStatus { #[bitbybit::bitfield(u32, default = 0x0)] #[derive(Debug)] -pub struct InterruptControl { +pub struct InterruptCtrl { #[bit(8, w)] dec_error_l3: bool, #[bit(7, w)] @@ -197,10 +197,10 @@ pub struct L2Cache { _reserved: [u32; 0x3E], - control: Control, - aux_control: AuxControl, - tag_ram_latency: LatencyConfig, - data_ram_latency: LatencyConfig, + control: Ctrl, + aux_control: AuxCtrl, + tag_ram_latency: LatencyCfg, + data_ram_latency: LatencyCfg, _reserved2: [u32; 0x3C], @@ -215,7 +215,7 @@ pub struct L2Cache { #[mmio(PureRead)] interrupt_raw_status: InterruptStatus, #[mmio(Write)] - interrupt_clear: InterruptControl, + interrupt_clear: InterruptCtrl, _reserved3: [u32; 0x143], @@ -264,7 +264,7 @@ pub struct L2Cache { _reserved13: [u32; 0xCE], - debug_control: DebugControl, + debug_control: DebugCtrl, _reserved14: [u32; 0x7], diff --git a/zynq7000/src/lib.rs b/zynq7000/src/lib.rs index a9df228..9dec569 100644 --- a/zynq7000/src/lib.rs +++ b/zynq7000/src/lib.rs @@ -37,8 +37,8 @@ static PERIPHERALS_TAKEN: AtomicBool = AtomicBool::new(false); /// The [`svd2rust` documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api) /// provides some more information about this. pub struct PsPeripherals { - pub gicc: gic::MmioGicc<'static>, - pub gicd: gic::MmioGicd<'static>, + pub gicc: gic::MmioGicCpuInterface<'static>, + pub gicd: gic::MmioGicDistributor<'static>, pub l2c: l2_cache::MmioL2Cache<'static>, pub uart_0: uart::MmioUart<'static>, pub uart_1: uart::MmioUart<'static>, @@ -46,7 +46,7 @@ pub struct PsPeripherals { pub spi_1: spi::MmioSpi<'static>, pub i2c_0: i2c::MmioI2c<'static>, pub i2c_1: i2c::MmioI2c<'static>, - pub gtc: gtc::MmioGtc<'static>, + pub gtc: gtc::MmioGlobalTimerCounter<'static>, pub gpio: gpio::MmioGpio<'static>, pub slcr: slcr::MmioSlcr<'static>, pub ttc_0: ttc::MmioTtc<'static>, @@ -73,12 +73,12 @@ impl PsPeripherals { pub unsafe fn steal() -> Self { unsafe { Self { - gicc: gic::Gicc::new_mmio_fixed(), - gicd: gic::Gicd::new_mmio_fixed(), + gicc: gic::GicCpuInterface::new_mmio_fixed(), + gicd: gic::GicDistributor::new_mmio_fixed(), l2c: l2_cache::L2Cache::new_mmio_fixed(), uart_0: uart::Uart::new_mmio_fixed_0(), uart_1: uart::Uart::new_mmio_fixed_1(), - gtc: gtc::Gtc::new_mmio_fixed(), + gtc: gtc::GlobalTimerCounter::new_mmio_fixed(), gpio: gpio::Gpio::new_mmio_fixed(), slcr: slcr::Slcr::new_mmio_fixed(), spi_0: spi::Spi::new_mmio_fixed_0(), diff --git a/zynq7000/src/mpcore.rs b/zynq7000/src/mpcore.rs index ef5ea67..97897bc 100644 --- a/zynq7000/src/mpcore.rs +++ b/zynq7000/src/mpcore.rs @@ -4,8 +4,8 @@ use static_assertions::const_assert_eq; use crate::{ - gic::{Gicc, Gicd, MmioGicc, MmioGicd}, - gtc::{Gtc, MmioGtc}, + gic::{GicCpuInterface, GicDistributor, MmioGicCpuInterface, MmioGicDistributor}, + gtc::{GlobalTimerCounter, MmioGlobalTimerCounter}, }; pub const MPCORE_BASE_ADDR: usize = 0xF8F0_0000; @@ -53,10 +53,10 @@ pub struct Mpcore { _reserved_0: [u32; 0x2A], #[mmio(Inner)] - gicc: Gicc, + gicc: GicCpuInterface, #[mmio(Inner)] - gt: Gtc, + gt: GlobalTimerCounter, _reserved_1: [u32; 0xF9], @@ -77,7 +77,7 @@ pub struct Mpcore { _reserved_3: [u32; 0x272], #[mmio(Inner)] - gicd: Gicd, + gicd: GicDistributor, } const_assert_eq!(core::mem::size_of::(), 0x2000); diff --git a/zynq7000/src/slcr/clocks.rs b/zynq7000/src/slcr/clocks.rs index bc1e8cb..019e3c6 100644 --- a/zynq7000/src/slcr/clocks.rs +++ b/zynq7000/src/slcr/clocks.rs @@ -73,7 +73,7 @@ pub struct PllStatus { #[bitbybit::bitfield(u32)] #[derive(Debug)] -pub struct FpgaClkControl { +pub struct FpgaClkCtrl { // Reset value 0x1 #[bits(20..=25, rw)] divisor_1: u6, @@ -86,14 +86,14 @@ pub struct FpgaClkControl { #[derive(derive_mmio::Mmio)] #[repr(C)] -pub struct FpgaClkBlock { - clk_ctrl: FpgaClkControl, +pub struct FpgaClkCtrlBlock { + ctrl: FpgaClkCtrl, thr_ctrl: u32, thr_cnt: u32, thr_status: u32, } -static_assertions::const_assert_eq!(core::mem::size_of::(), 0x10); +static_assertions::const_assert_eq!(core::mem::size_of::(), 0x10); #[bitbybit::bitenum(u2, exhaustive = true)] #[derive(Debug)] @@ -156,15 +156,15 @@ pub struct DciClkCtrl { #[bitbybit::bitfield(u32)] #[derive(Debug)] -pub struct ClockRatioSelectReg { +pub struct ClkRatioSelectReg { /// Reset value: 0x1 (6:2:1 clock) #[bit(0, rw)] - sel: ClockRatioSelect, + sel: ClkRatioSelect, } #[bitbybit::bitenum(u1, exhaustive = true)] #[derive(Debug)] -pub enum ClockRatioSelect { +pub enum ClkRatioSelect { /// 4:2:1 clock ratio, which is an abbreviation for 4:2:2:1. FourToTwoToOne = 0b0, /// 6:2:1 clock ratio, which is an abbreviation for 6:3:2:1. @@ -372,15 +372,15 @@ pub struct ClockControl { pcap_clk_ctrl: SingleCommonPeriphIoClkCtrl, topsw_clk_ctrl: u32, #[mmio(Inner)] - fpga_0_clk_ctrl: FpgaClkBlock, + fpga_0_clk_ctrl: FpgaClkCtrlBlock, #[mmio(Inner)] - fpga_1_clk_ctrl: FpgaClkBlock, + fpga_1_clk_ctrl: FpgaClkCtrlBlock, #[mmio(Inner)] - fpga_2_clk_ctrl: FpgaClkBlock, + fpga_2_clk_ctrl: FpgaClkCtrlBlock, #[mmio(Inner)] - fpga_3_clk_ctrl: FpgaClkBlock, + fpga_3_clk_ctrl: FpgaClkCtrlBlock, _gap1: [u32; 5], - clk_621_true: ClockRatioSelectReg, + clk_621_true: ClkRatioSelectReg, } impl ClockControl { diff --git a/zynq7000/src/slcr/mod.rs b/zynq7000/src/slcr/mod.rs index 4c72b09..81416bf 100644 --- a/zynq7000/src/slcr/mod.rs +++ b/zynq7000/src/slcr/mod.rs @@ -58,7 +58,7 @@ pub enum VrefSel { #[bitbybit::bitfield(u32)] #[derive(Debug)] -pub struct GpiobControl { +pub struct GpiobCtrl { #[bit(11, rw)] vref_sw_en: bool, #[bits(4..=6, rw)] @@ -70,7 +70,7 @@ pub struct GpiobControl { #[derive(derive_mmio::Mmio)] #[repr(C)] pub struct GpiobRegisters { - ctrl: GpiobControl, + ctrl: GpiobCtrl, cfg_cmos18: u32, cfg_cmos25: u32, cfg_cmos33: u32, @@ -95,7 +95,7 @@ impl GpiobRegisters { #[bitbybit::bitfield(u32)] #[derive(Debug)] -pub struct BootModeRegister { +pub struct BootModeReg { #[bit(4, r)] pll_bypass: bool, #[bits(0..=3, r)] @@ -104,7 +104,7 @@ pub struct BootModeRegister { #[bitbybit::bitenum(u4)] #[derive(Debug, PartialEq, Eq)] -pub enum LevelShifterConfig { +pub enum LevelShifterCfg { DisableAll = 0x00, EnablePsToPl = 0xA, EnableAll = 0xF, @@ -113,7 +113,7 @@ pub enum LevelShifterConfig { #[bitbybit::bitfield(u32)] pub struct LevelShifterReg { #[bits(0..=3, rw)] - user_lvl_shftr_en: Option, + user_lvl_shftr_en: Option, } /// System Level Control Registers @@ -142,7 +142,7 @@ pub struct Slcr { _gap2: [u32; 0x02], reboot_status: u32, - boot_mode: BootModeRegister, + boot_mode: BootModeReg, _gap3: [u32; 0x28], diff --git a/zynq7000/src/slcr/reset.rs b/zynq7000/src/slcr/reset.rs index 286ed23..bc23b07 100644 --- a/zynq7000/src/slcr/reset.rs +++ b/zynq7000/src/slcr/reset.rs @@ -2,7 +2,7 @@ use super::{RESET_BLOCK_OFFSET, SLCR_BASE_ADDR}; #[bitbybit::bitfield(u32, default = 0x0)] #[derive(Debug)] -pub struct DualClockReset { +pub struct DualClkRst { /// Peripheral 1 AMBA software reset. #[bit(1, rw)] periph1_cpu1x_rst: bool, @@ -13,7 +13,7 @@ pub struct DualClockReset { #[bitbybit::bitfield(u32, default = 0x0)] #[derive(Debug)] -pub struct DualRefAndClockReset { +pub struct DualRefAndClkRst { /// Periperal 1 Reference software reset. #[bit(3, rw)] periph1_ref_rst: bool, @@ -30,14 +30,14 @@ pub struct DualRefAndClockReset { #[bitbybit::bitfield(u32, default = 0x0)] #[derive(Debug)] -pub struct GpioClockReset { +pub struct GpioClkRst { #[bit(0, rw)] gpio_cpu1x_rst: bool, } #[bitbybit::bitfield(u32, default = 0x0)] #[derive(Debug)] -pub struct EthernetReset { +pub struct EthernetRst { #[bit(5, rw)] gem1_ref_rst: bool, #[bit(4, rw)] @@ -62,13 +62,13 @@ pub struct ResetControl { topsw: u32, dmac: u32, usb: u32, - eth: EthernetReset, - sdio: DualRefAndClockReset, - spi: DualRefAndClockReset, - can: DualClockReset, - i2c: DualClockReset, - uart: DualRefAndClockReset, - gpio: GpioClockReset, + eth: EthernetRst, + sdio: DualRefAndClkRst, + spi: DualRefAndClkRst, + can: DualClkRst, + i2c: DualClkRst, + uart: DualRefAndClkRst, + gpio: GpioClkRst, lqspi: u32, smc: u32, ocm: u32, diff --git a/zynq7000/src/spi.rs b/zynq7000/src/spi.rs index b732b07..079467b 100644 --- a/zynq7000/src/spi.rs +++ b/zynq7000/src/spi.rs @@ -7,7 +7,7 @@ pub const SPI_1_BASE_ADDR: usize = 0xE000_7000; /// The SPI reference block will be divided by a divisor value. #[bitbybit::bitenum(u3)] #[derive(Debug, PartialEq, Eq)] -pub enum BaudDivSelect { +pub enum BaudDivSel { By4 = 0b001, By8 = 0b010, By16 = 0b011, @@ -17,23 +17,23 @@ pub enum BaudDivSelect { By256 = 0b111, } -impl BaudDivSelect { +impl BaudDivSel { pub const fn div_value(&self) -> usize { match self { - BaudDivSelect::By4 => 4, - BaudDivSelect::By8 => 8, - BaudDivSelect::By16 => 16, - BaudDivSelect::By32 => 32, - BaudDivSelect::By64 => 64, - BaudDivSelect::By128 => 128, - BaudDivSelect::By256 => 256, + BaudDivSel::By4 => 4, + BaudDivSel::By8 => 8, + BaudDivSel::By16 => 16, + BaudDivSel::By32 => 32, + BaudDivSel::By64 => 64, + BaudDivSel::By128 => 128, + BaudDivSel::By256 => 256, } } } #[bitbybit::bitfield(u32, default = 0x0)] #[derive(Debug)] -pub struct Config { +pub struct Cfg { #[bit(17, rw)] modefail_gen_en: bool, #[bit(16, w)] @@ -53,7 +53,7 @@ pub struct Config { #[bit(8, r)] ref_clk: bool, #[bits(3..=5, rw)] - baud_rate_div: Option, + baud_rate_div: Option, /// Clock phase. 1: The SPI clock is inactive outside the word. #[bit(2, rw)] cpha: bool, @@ -182,7 +182,7 @@ pub struct DelayControl { #[derive(derive_mmio::Mmio)] #[repr(C)] pub struct Spi { - cr: Config, + cr: Cfg, #[mmio(PureRead, Write)] isr: InterruptStatus, /// Interrupt Enable Register. diff --git a/zynq7000/src/ttc.rs b/zynq7000/src/ttc.rs index 76fe4d8..b0a9a07 100644 --- a/zynq7000/src/ttc.rs +++ b/zynq7000/src/ttc.rs @@ -14,7 +14,7 @@ pub enum ClockSource { } #[bitbybit::bitfield(u32, default = 0x0)] -pub struct ClockControl { +pub struct ClkCtrl { /// When this bit is set and the external clock is selected, the counter clocks on the /// negative edge of the external clock input. #[bit(6, rw)] @@ -146,7 +146,7 @@ pub struct EventCount { #[derive(derive_mmio::Mmio)] #[repr(C)] pub struct Ttc { - clk_cntr: [ClockControl; 3], + clk_cntr: [ClkCtrl; 3], cnt_ctrl: [CounterControl; 3], #[mmio(PureRead)] current_counter: [Counter; 3], From 924ca98fc6c35624e28712242a421696b6a40db6 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Thu, 31 Jul 2025 18:47:05 +0200 Subject: [PATCH 2/2] de-abbreviate some stuff --- examples/zedboard/src/bin/ethernet.rs | 4 ++-- examples/zedboard/src/bin/l3gd20h-i2c-mio.rs | 4 ++-- examples/zedboard/src/bin/l3gd20h-spi-mio.rs | 4 ++-- examples/zedboard/src/bin/uart-blocking.rs | 4 ++-- examples/zedboard/src/bin/uart-non-blocking.rs | 4 ++-- examples/zedboard/src/main.rs | 4 ++-- zynq7000-hal/src/gic.rs | 6 +++--- zynq7000-hal/src/l2_cache.rs | 16 ++++++++-------- zynq7000-hal/src/lib.rs | 2 +- 9 files changed, 24 insertions(+), 24 deletions(-) diff --git a/examples/zedboard/src/bin/ethernet.rs b/examples/zedboard/src/bin/ethernet.rs index 8338ea8..68df12a 100644 --- a/examples/zedboard/src/bin/ethernet.rs +++ b/examples/zedboard/src/bin/ethernet.rs @@ -40,7 +40,7 @@ use zedboard::{ use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, eth::{ AlignedBuffer, ClkDivCollection, EthernetConfig, EthernetLowLevel, embassy_net::InterruptResult, @@ -213,7 +213,7 @@ async fn main(spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Configure the uncached memory region using the MMU. mmu_l1_table_mut() diff --git a/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs b/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs index 0c0630e..496acfc 100644 --- a/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs +++ b/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs @@ -20,7 +20,7 @@ use log::{error, info}; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -52,7 +52,7 @@ async fn main(_spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); diff --git a/examples/zedboard/src/bin/l3gd20h-spi-mio.rs b/examples/zedboard/src/bin/l3gd20h-spi-mio.rs index 3b0677d..95cf6ac 100644 --- a/examples/zedboard/src/bin/l3gd20h-spi-mio.rs +++ b/examples/zedboard/src/bin/l3gd20h-spi-mio.rs @@ -20,7 +20,7 @@ use log::{error, info}; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -55,7 +55,7 @@ async fn main(spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let mut clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); diff --git a/examples/zedboard/src/bin/uart-blocking.rs b/examples/zedboard/src/bin/uart-blocking.rs index e909e85..1b511bc 100644 --- a/examples/zedboard/src/bin/uart-blocking.rs +++ b/examples/zedboard/src/bin/uart-blocking.rs @@ -15,7 +15,7 @@ use zedboard::PS_CLOCK_FREQUENCY; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -105,7 +105,7 @@ async fn main(_spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); // Set up the global interrupt controller. diff --git a/examples/zedboard/src/bin/uart-non-blocking.rs b/examples/zedboard/src/bin/uart-non-blocking.rs index 1c43fc1..fbfb48d 100644 --- a/examples/zedboard/src/bin/uart-non-blocking.rs +++ b/examples/zedboard/src/bin/uart-non-blocking.rs @@ -41,7 +41,7 @@ use log::{error, info, warn}; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -170,7 +170,7 @@ async fn main(spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); diff --git a/examples/zedboard/src/main.rs b/examples/zedboard/src/main.rs index 4ca0870..02f4565 100644 --- a/examples/zedboard/src/main.rs +++ b/examples/zedboard/src/main.rs @@ -12,7 +12,7 @@ use zedboard::PS_CLOCK_FREQUENCY; use zynq7000_hal::{ BootMode, clocks::Clocks, - cfg_level_shifter, + configure_level_shifter, gic::{GicConfigurator, GicInterruptHelper, Interrupt}, gpio::{GpioPins, Output, PinState}, gtc::GlobalTimerCounter, @@ -41,7 +41,7 @@ async fn main(_spawner: Spawner) -> ! { l2_cache::init_with_defaults(&mut dp.l2c); // Enable PS-PL level shifters. - cfg_level_shifter(LevelShifterCfg::EnableAll); + configure_level_shifter(LevelShifterCfg::EnableAll); // Clock was already initialized by PS7 Init TCL script or FSBL, we just read it. let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap(); diff --git a/zynq7000-hal/src/gic.rs b/zynq7000-hal/src/gic.rs index 7b71d02..d38d912 100644 --- a/zynq7000-hal/src/gic.rs +++ b/zynq7000-hal/src/gic.rs @@ -10,7 +10,7 @@ use arbitrary_int::Number; use cortex_ar::interrupt; use zynq7000::gic::{ - Dcr, GicCpuInterface, GicDistributor, Icr, InterruptSignalRegister, MmioGicCpuInterface, MmioGicDistributor, PriorityReg, + Dcr, GicCpuInterface, GicDistributor, InterfaceCtrl, InterruptSignalRegister, MmioGicCpuInterface, MmioGicDistributor, PriorityReg, }; const SPURIOUS_INTERRUPT_ID: u32 = 1023; @@ -442,7 +442,7 @@ impl GicConfigurator { /// to call [Self::enable_interrupts] for interrupts to work. pub fn enable(&mut self) { self.update_ctrl_regs( - Icr::builder() + InterfaceCtrl::builder() .with_sbpr(false) .with_fiq_en(false) .with_ack_ctrl(false) @@ -476,7 +476,7 @@ impl GicConfigurator { /// Update the control registers which control the safety configuration and which also enable /// the GIC. - pub fn update_ctrl_regs(&mut self, icr: Icr, dcr: Dcr) { + pub fn update_ctrl_regs(&mut self, icr: InterfaceCtrl, dcr: Dcr) { self.gicc.write_icr(icr); self.gicd.write_dcr(dcr); } diff --git a/zynq7000-hal/src/l2_cache.rs b/zynq7000-hal/src/l2_cache.rs index 813493d..2dedc92 100644 --- a/zynq7000-hal/src/l2_cache.rs +++ b/zynq7000-hal/src/l2_cache.rs @@ -1,15 +1,15 @@ use core::sync::atomic::compiler_fence; use arbitrary_int::{u2, u3}; -pub use zynq7000::l2_cache::LatencyConfig; +pub use zynq7000::l2_cache::LatencyCfg; use zynq7000::l2_cache::{ - Associativity, AuxControl, Ctrl, InterruptControl, MmioL2Cache, ReplacementPolicy, WaySize, + Associativity, AuxCtrl, Ctrl, InterruptCtrl, MmioL2Cache, ReplacementPolicy, WaySize, }; use crate::slcr::Slcr; /// This is the default configuration used by Xilinx/AMD. -pub const AUX_CTRL_DEFAULT: AuxControl = AuxControl::builder() +pub const AUX_CTRL_DEFAULT: AuxCtrl = AuxCtrl::builder() .with_early_bresp_enable(true) .with_isntruction_prefetch_enable(true) .with_data_prefetch_enable(true) @@ -30,14 +30,14 @@ pub const AUX_CTRL_DEFAULT: AuxControl = AuxControl::builder() .build(); /// Xilinx/AMD default configuration. 2 cycles for setup, write and read. -pub const DEFAULT_TAG_RAM_LATENCY: LatencyConfig = LatencyConfig::builder() +pub const DEFAULT_TAG_RAM_LATENCY: LatencyCfg = LatencyCfg::builder() .with_write_access_latency(u3::new(0b001)) .with_read_access_latency(u3::new(0b001)) .with_setup_latency(u3::new(0b001)) .build(); /// Xilinx/AMD default configuration. 2 cycles for setup and write, 3 cycles for read. -pub const DEFAULT_DATA_RAM_LATENCY: LatencyConfig = LatencyConfig::builder() +pub const DEFAULT_DATA_RAM_LATENCY: LatencyCfg = LatencyCfg::builder() .with_write_access_latency(u3::new(0b001)) .with_read_access_latency(u3::new(0b010)) .with_setup_latency(u3::new(0b001)) @@ -57,8 +57,8 @@ pub fn init_with_defaults(l2c_mmio: &mut MmioL2Cache<'static>) { /// the runtime initialization provided by Xilinx/AMD. pub fn init( l2c_mmio: &mut MmioL2Cache<'static>, - tag_ram_latency: LatencyConfig, - data_ram_latency: LatencyConfig, + tag_ram_latency: LatencyCfg, + data_ram_latency: LatencyCfg, ) { l2c_mmio.write_control(Ctrl::new_disabled()); l2c_mmio.write_aux_control(AUX_CTRL_DEFAULT); @@ -71,7 +71,7 @@ pub fn init( compiler_fence(core::sync::atomic::Ordering::SeqCst); let pending = l2c_mmio.read_interrupt_raw_status(); - l2c_mmio.write_interrupt_clear(InterruptControl::new_with_raw_value(pending.raw_value())); + l2c_mmio.write_interrupt_clear(InterruptCtrl::new_with_raw_value(pending.raw_value())); unsafe { Slcr::with(|slcr| { slcr.write_magic_l2c_register(SLCR_L2C_CONFIG_MAGIC_VALUE); diff --git a/zynq7000-hal/src/lib.rs b/zynq7000-hal/src/lib.rs index 620d5f0..65dad86 100644 --- a/zynq7000-hal/src/lib.rs +++ b/zynq7000-hal/src/lib.rs @@ -104,7 +104,7 @@ impl BootMode { /// system (PS). /// /// The Zynq-7000 TRM p.32 specifies more information about this register and how to use it. -pub fn cfg_level_shifter(config: zynq7000::slcr::LevelShifterCfg) { +pub fn configure_level_shifter(config: zynq7000::slcr::LevelShifterCfg) { // Safety: We only manipulate the level shift registers. unsafe { Slcr::with(|slcr_unlocked| {