diff --git a/examples/embassy/Cargo.toml b/examples/embassy/Cargo.toml
index 06bfe5d..e58dd47 100644
--- a/examples/embassy/Cargo.toml
+++ b/examples/embassy/Cargo.toml
@@ -30,7 +30,7 @@ embassy-executor = { git = "https://github.com/us-irs/embassy.git", branch = "co
   "executor-thread",
 ]}
 # TODO: Remove generic-queue-16 feature as soon as upstream executor is used again.
-embassy-time = { version = "0.4", features = ["tick-hz-1_000_000", "generic-queue-16"] }
+embassy-time = { version = "0.5", features = ["tick-hz-1_000_000", "generic-queue-16"] }
 
 [profile.release]
 codegen-units = 1
diff --git a/examples/zedboard/Cargo.toml b/examples/zedboard/Cargo.toml
index 796b26b..5e8a56b 100644
--- a/examples/zedboard/Cargo.toml
+++ b/examples/zedboard/Cargo.toml
@@ -35,7 +35,7 @@ embassy-executor = { git = "https://github.com/us-irs/embassy.git", branch = "co
   "executor-thread",
 ]}
 # TODO: Remove generic-queue-16 feature as soon as upstream executor is used again.
-embassy-time = { version = "0.4", features = ["tick-hz-1_000_000", "generic-queue-16"] }
+embassy-time = { version = "0.5", features = ["tick-hz-1_000_000", "generic-queue-16"] }
 embassy-net = { version = "0.7", features = ["dhcpv4", "packet-trace", "medium-ethernet", "icmp", "tcp", "udp"] }
 embassy-sync = { version = "0.7" }
 heapless = "0.8"
diff --git a/zynq7000-embassy/Cargo.toml b/zynq7000-embassy/Cargo.toml
index 6482803..8928c1c 100644
--- a/zynq7000-embassy/Cargo.toml
+++ b/zynq7000-embassy/Cargo.toml
@@ -18,4 +18,4 @@ zynq7000-hal = { path = "../zynq7000-hal" }
 # embassy-time-driver = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", version = "0.2" }
 # embassy-time-queue-utils = { git = "https://github.com/embassy-rs/embassy.git", branch = "main", version = "0.1" }
 embassy-time-driver = "0.2"
-embassy-time-queue-utils = "0.1"
+embassy-time-queue-utils = "0.3"
diff --git a/zynq7000-hal/src/eth/mod.rs b/zynq7000-hal/src/eth/mod.rs
index 0c95157..8ee46ca 100644
--- a/zynq7000-hal/src/eth/mod.rs
+++ b/zynq7000-hal/src/eth/mod.rs
@@ -32,7 +32,7 @@ use crate::{
         IoPeriphPin,
         mio::{
             Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39,
-            Mio52, Mio53, MioPinMarker, MuxConfig, Pin,
+            Mio52, Mio53, MioPin, MuxConfig, Pin,
         },
     },
     time::Hertz,
@@ -105,45 +105,45 @@ impl PsEthernet for MmioEthernet<'static> {
     }
 }
 
-pub trait TxClk: MioPinMarker {
+pub trait TxClk: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait TxCtrl: MioPinMarker {
+pub trait TxCtrl: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait TxData0: MioPinMarker {
+pub trait TxData0: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait TxData1: MioPinMarker {
+pub trait TxData1: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait TxData2: MioPinMarker {
+pub trait TxData2: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait TxData3: MioPinMarker {
+pub trait TxData3: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait RxClk: MioPinMarker {
+pub trait RxClk: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait RxCtrl: MioPinMarker {
+pub trait RxCtrl: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait RxData0: MioPinMarker {
+pub trait RxData0: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait RxData1: MioPinMarker {
+pub trait RxData1: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait RxData2: MioPinMarker {
+pub trait RxData2: MioPin {
     const ETH_ID: EthernetId;
 }
-pub trait RxData3: MioPinMarker {
+pub trait RxData3: MioPin {
     const ETH_ID: EthernetId;
 }
 
-pub trait MdClk: MioPinMarker {}
-pub trait MdIo: MioPinMarker {}
+pub trait MdClk: MioPin {}
+pub trait MdIo: MioPin {}
 
 impl MdClk for Pin<Mio52> {}
 impl MdIo for Pin<Mio53> {}
diff --git a/zynq7000-hal/src/gpio/mio.rs b/zynq7000-hal/src/gpio/mio.rs
index 7602f5c..0972b5e 100644
--- a/zynq7000-hal/src/gpio/mio.rs
+++ b/zynq7000-hal/src/gpio/mio.rs
@@ -174,7 +174,7 @@ pin_id!(Mio51, 51);
 pin_id!(Mio52, 52);
 pin_id!(Mio53, 53);
 
-pub trait MioPinMarker {
+pub trait MioPin {
     fn offset(&self) -> usize;
 }
 
@@ -374,7 +374,7 @@ impl Pins {
     }
 }
 
-impl<I: PinId> MioPinMarker for Pin<I> {
+impl<I: PinId> MioPin for Pin<I> {
     fn offset(&self) -> usize {
         I::OFFSET
     }
diff --git a/zynq7000-hal/src/gpio/mod.rs b/zynq7000-hal/src/gpio/mod.rs
index 9e11e3d..19b1171 100644
--- a/zynq7000-hal/src/gpio/mod.rs
+++ b/zynq7000-hal/src/gpio/mod.rs
@@ -14,7 +14,7 @@ pub mod mio;
 
 use core::convert::Infallible;
 use ll::PinOffset;
-use mio::{MioPinMarker, MuxConfig};
+use mio::{MioPin, MuxConfig};
 
 use crate::gpio::ll::LowLevelGpio;
 use crate::{enable_amba_periph_clk, slcr::Slcr};
@@ -386,7 +386,7 @@ pub struct IoPeriphPin {
 impl IoPeriphPin {
     /// Constructor for IO peripheral pins where only the multiplexer and pullup configuration
     /// need to be changed.
-    pub fn new(pin: impl MioPinMarker, mux_conf: MuxConfig, pullup: Option<bool>) -> Self {
+    pub fn new(pin: impl MioPin, mux_conf: MuxConfig, pullup: Option<bool>) -> Self {
         let mut low_level = LowLevelGpio::new(PinOffset::Mio(pin.offset()));
         low_level.configure_as_io_periph_pin(mux_conf, pullup);
         Self {
@@ -396,10 +396,7 @@ impl IoPeriphPin {
     }
 
     /// Constructor to fully configure an IO peripheral pin with a specific MIO pin configuration.
-    pub fn new_with_full_config(
-        pin: impl MioPinMarker,
-        config: zynq7000::slcr::mio::Config,
-    ) -> Self {
+    pub fn new_with_full_config(pin: impl MioPin, config: zynq7000::slcr::mio::Config) -> Self {
         let mut low_level = LowLevelGpio::new(PinOffset::Mio(pin.offset()));
         low_level.set_mio_pin_config(config);
         Self {
@@ -415,7 +412,7 @@ impl IoPeriphPin {
 
     /// Constructor to fully configure an IO peripheral pin with a specific MIO pin configuration.
     pub fn new_with_full_config_and_unlocked_slcr(
-        pin: impl MioPinMarker,
+        pin: impl MioPin,
         slcr: &mut zynq7000::slcr::MmioSlcr<'static>,
         config: zynq7000::slcr::mio::Config,
     ) -> Self {
diff --git a/zynq7000-hal/src/i2c.rs b/zynq7000-hal/src/i2c.rs
index 29bf5f5..b20d745 100644
--- a/zynq7000-hal/src/i2c.rs
+++ b/zynq7000-hal/src/i2c.rs
@@ -16,7 +16,7 @@ use crate::{
         IoPeriphPin,
         mio::{
             Mio10, Mio11, Mio12, Mio13, Mio14, Mio15, Mio28, Mio29, Mio30, Mio31, Mio32, Mio33,
-            Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, Mio48, Mio49, Mio52, Mio53, MioPinMarker,
+            Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, Mio48, Mio49, Mio52, Mio53, MioPin,
             MuxConfig, Pin,
         },
     },
@@ -58,11 +58,11 @@ impl PsI2c for MmioI2c<'static> {
     }
 }
 
-pub trait SdaPin: MioPinMarker {
+pub trait SdaPin: MioPin {
     const ID: I2cId;
 }
 
-pub trait SckPin: MioPinMarker {
+pub trait SckPin: MioPin {
     const ID: I2cId;
 }
 
diff --git a/zynq7000-hal/src/spi/mod.rs b/zynq7000-hal/src/spi/mod.rs
index 98f4f75..804286a 100644
--- a/zynq7000-hal/src/spi/mod.rs
+++ b/zynq7000-hal/src/spi/mod.rs
@@ -6,7 +6,7 @@ use crate::enable_amba_periph_clk;
 use crate::gpio::IoPeriphPin;
 use crate::gpio::mio::{
     Mio10, Mio11, Mio12, Mio13, Mio14, Mio15, Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34,
-    Mio35, Mio36, Mio37, Mio38, Mio39, MioPinMarker, MuxConfig, Pin,
+    Mio35, Mio36, Mio37, Mio38, Mio39, MioPin, MuxConfig, Pin,
 };
 #[cfg(not(feature = "7z010-7z007s-clg225"))]
 use crate::gpio::mio::{
@@ -60,22 +60,22 @@ impl PsSpi for MmioSpi<'static> {
     }
 }
 
-pub trait SckPin: MioPinMarker {
+pub trait SckPin: MioPin {
     const SPI: SpiId;
     const GROUP: usize;
 }
 
-pub trait MosiPin: MioPinMarker {
+pub trait MosiPin: MioPin {
     const SPI: SpiId;
     const GROUP: usize;
 }
 
-pub trait MisoPin: MioPinMarker {
+pub trait MisoPin: MioPin {
     const SPI: SpiId;
     const GROUP: usize;
 }
 
-pub trait SsPin: MioPinMarker {
+pub trait SsPin: MioPin {
     const IDX: usize;
     const SPI: SpiId;
     const GROUP: usize;
diff --git a/zynq7000-hal/src/ttc.rs b/zynq7000-hal/src/ttc.rs
index 1e032d4..30aab84 100644
--- a/zynq7000-hal/src/ttc.rs
+++ b/zynq7000-hal/src/ttc.rs
@@ -13,7 +13,7 @@ use crate::{
     clocks::ArmClocks,
     gpio::{
         IoPeriphPin,
-        mio::{Mio28, Mio29, Mio30, Mio31, MioPinMarker, MuxConfig, Pin},
+        mio::{Mio28, Mio29, Mio30, Mio31, MioPin, MuxConfig, Pin},
     },
     time::Hertz,
 };
@@ -57,11 +57,11 @@ impl PsTtc for MmioTtc<'static> {
 
 pub const TTC_MUX_CONF: MuxConfig = MuxConfig::new_with_l3(u3::new(0b110));
 
-pub trait ClockInPin: MioPinMarker {
+pub trait ClockInPin: MioPin {
     const ID: TtcId;
 }
 
-pub trait WaveOutPin: MioPinMarker {
+pub trait WaveOutPin: MioPin {
     const ID: TtcId;
 }
 
diff --git a/zynq7000-hal/src/uart/mod.rs b/zynq7000-hal/src/uart/mod.rs
index b3bfc32..d753a69 100644
--- a/zynq7000-hal/src/uart/mod.rs
+++ b/zynq7000-hal/src/uart/mod.rs
@@ -20,7 +20,7 @@ use crate::{
         mio::{
             Mio8, Mio9, Mio10, Mio11, Mio12, Mio13, Mio14, Mio15, Mio28, Mio29, Mio30, Mio31,
             Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, Mio48, Mio49, Mio52, Mio53,
-            MioPinMarker, MuxConfig, Pin,
+            MioPin, MuxConfig, Pin,
         },
     },
     slcr::Slcr,
@@ -89,10 +89,10 @@ impl UartId {
     }
 }
 
-pub trait RxPin: MioPinMarker {
+pub trait RxPin: MioPin {
     const UART_IDX: UartId;
 }
-pub trait TxPin: MioPinMarker {
+pub trait TxPin: MioPin {
     const UART_IDX: UartId;
 }