From 0206d15b2eacc4bf84453a780b31c54fe19ca248 Mon Sep 17 00:00:00 2001
From: Robin Mueller <robin.mueller.m@pm.me>
Date: Thu, 9 Oct 2025 00:58:35 +0200
Subject: [PATCH] smaller tweaks and docs API unification

---
 README.md                     | 3 ++-
 zynq/zynq7000-mmu/src/lib.rs  | 2 +-
 zynq/zynq7000/src/ddrc.rs     | 1 +
 zynq/zynq7000/src/devcfg.rs   | 1 +
 zynq/zynq7000/src/eth.rs      | 4 ++--
 zynq/zynq7000/src/gpio.rs     | 1 +
 zynq/zynq7000/src/gtc.rs      | 2 +-
 zynq/zynq7000/src/i2c.rs      | 1 +
 zynq/zynq7000/src/l2_cache.rs | 1 +
 zynq/zynq7000/src/mpcore.rs   | 1 +
 zynq/zynq7000/src/priv_tim.rs | 1 +
 zynq/zynq7000/src/qspi.rs     | 1 +
 zynq/zynq7000/src/slcr/mod.rs | 2 +-
 zynq/zynq7000/src/spi.rs      | 2 +-
 zynq/zynq7000/src/ttc.rs      | 2 +-
 zynq/zynq7000/src/uart.rs     | 1 +
 zynq/zynq7000/src/xadc.rs     | 1 +
 17 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/README.md b/README.md
index 3fd640a..bd3f935 100644
--- a/README.md
+++ b/README.md
@@ -111,7 +111,8 @@ target = "armv7a-none-eabihf"
 You can build the blinky example app using
 
 ```sh
-cargo build --example simple
+cd zynq
+cargo build --bin blinky
 ```
 
 
diff --git a/zynq/zynq7000-mmu/src/lib.rs b/zynq/zynq7000-mmu/src/lib.rs
index 6c59afb..c8dfec6 100644
--- a/zynq/zynq7000-mmu/src/lib.rs
+++ b/zynq/zynq7000-mmu/src/lib.rs
@@ -1,4 +1,4 @@
-//! # Zynq7000 Memory Management Unit (MMU) 
+//! # Zynq7000 Memory Management Unit (MMU)
 //!
 //! Dedicated shared crate for Zynq7000 MMU abstractions which can be used by Zynq
 //! runtime crates, PACs and HALs.
diff --git a/zynq/zynq7000/src/ddrc.rs b/zynq/zynq7000/src/ddrc.rs
index d1fe31c..9986316 100644
--- a/zynq/zynq7000/src/ddrc.rs
+++ b/zynq/zynq7000/src/ddrc.rs
@@ -725,6 +725,7 @@ pub mod regs {
 
 use regs::*;
 
+/// DDR controller register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct DdrController {
diff --git a/zynq/zynq7000/src/devcfg.rs b/zynq/zynq7000/src/devcfg.rs
index d7d67c1..e2d11bc 100644
--- a/zynq/zynq7000/src/devcfg.rs
+++ b/zynq/zynq7000/src/devcfg.rs
@@ -257,6 +257,7 @@ pub struct Status {
     efuse_jtag_disabled: bool,
 }
 
+/// Device configuration register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct DevCfg {
diff --git a/zynq/zynq7000/src/eth.rs b/zynq/zynq7000/src/eth.rs
index 38ab358..30991b2 100644
--- a/zynq/zynq7000/src/eth.rs
+++ b/zynq/zynq7000/src/eth.rs
@@ -418,7 +418,7 @@ pub struct MatchRegister {
     type_id: u16,
 }
 
-/// Gigabit Ethernet Controller (GEM) registers for Zynq-7000
+/// Gigabit Ethernet Controller (GEM) register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Ethernet {
@@ -477,7 +477,7 @@ pub struct Ethernet {
 
 static_assertions::const_assert_eq!(core::mem::size_of::<Ethernet>(), 0x294);
 
-/// GEM statistics registers
+/// Ethernet statistics registers
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Statistics {
diff --git a/zynq/zynq7000/src/gpio.rs b/zynq/zynq7000/src/gpio.rs
index 5decc98..68e299c 100644
--- a/zynq/zynq7000/src/gpio.rs
+++ b/zynq/zynq7000/src/gpio.rs
@@ -35,6 +35,7 @@ pub struct BankControl {
     int_any: u32,
 }
 
+/// GPIO register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Gpio {
diff --git a/zynq/zynq7000/src/gtc.rs b/zynq/zynq7000/src/gtc.rs
index 3e29b12..62f8086 100644
--- a/zynq/zynq7000/src/gtc.rs
+++ b/zynq/zynq7000/src/gtc.rs
@@ -22,7 +22,7 @@ pub struct InterruptStatus {
     event_flag: bool,
 }
 
-/// Global timer counter.
+/// Global timer counter register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct GlobalTimerCounter {
diff --git a/zynq/zynq7000/src/i2c.rs b/zynq/zynq7000/src/i2c.rs
index 8ea7663..723360b 100644
--- a/zynq/zynq7000/src/i2c.rs
+++ b/zynq/zynq7000/src/i2c.rs
@@ -156,6 +156,7 @@ pub struct TransferSize {
     size: u8,
 }
 
+/// I2C register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct I2c {
diff --git a/zynq/zynq7000/src/l2_cache.rs b/zynq/zynq7000/src/l2_cache.rs
index 46d090a..328b1c2 100644
--- a/zynq/zynq7000/src/l2_cache.rs
+++ b/zynq/zynq7000/src/l2_cache.rs
@@ -184,6 +184,7 @@ pub struct InterruptControl {
     event_counter_overflow_increment: bool,
 }
 
+/// L2 Cache register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct L2Cache {
diff --git a/zynq/zynq7000/src/mpcore.rs b/zynq/zynq7000/src/mpcore.rs
index 122ea08..92d9527 100644
--- a/zynq/zynq7000/src/mpcore.rs
+++ b/zynq/zynq7000/src/mpcore.rs
@@ -44,6 +44,7 @@ impl SnoopControlUnit {
 
 const_assert_eq!(core::mem::size_of::<SnoopControlUnit>(), 0x58);
 
+/// MP Core register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct MpCore {
diff --git a/zynq/zynq7000/src/priv_tim.rs b/zynq/zynq7000/src/priv_tim.rs
index cc86ede..cfbbb46 100644
--- a/zynq/zynq7000/src/priv_tim.rs
+++ b/zynq/zynq7000/src/priv_tim.rs
@@ -21,6 +21,7 @@ pub struct InterruptStatus {
     event_flag: bool,
 }
 
+/// CPU private timer register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct CpuPrivateTimer {
diff --git a/zynq/zynq7000/src/qspi.rs b/zynq/zynq7000/src/qspi.rs
index f032b17..c5d0cb4 100644
--- a/zynq/zynq7000/src/qspi.rs
+++ b/zynq/zynq7000/src/qspi.rs
@@ -220,6 +220,7 @@ pub struct LinearQspiStatus {
     axi_write_command_received: bool,
 }
 
+/// QSPI register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Qspi {
diff --git a/zynq/zynq7000/src/slcr/mod.rs b/zynq/zynq7000/src/slcr/mod.rs
index 5bbdc60..20a7db9 100644
--- a/zynq/zynq7000/src/slcr/mod.rs
+++ b/zynq/zynq7000/src/slcr/mod.rs
@@ -91,7 +91,7 @@ pub struct LevelShifterRegister {
     user_lvl_shftr_en: Option<LevelShifterConfig>,
 }
 
-/// System Level Control Registers
+/// System Level Control Registers access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Slcr {
diff --git a/zynq/zynq7000/src/spi.rs b/zynq/zynq7000/src/spi.rs
index dbb5ae4..ced47a9 100644
--- a/zynq/zynq7000/src/spi.rs
+++ b/zynq/zynq7000/src/spi.rs
@@ -178,7 +178,7 @@ pub struct DelayControl {
     cs_to_first_bit: u8,
 }
 
-/// Register block specification for both PS SPIs.
+/// SPI register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Spi {
diff --git a/zynq/zynq7000/src/ttc.rs b/zynq/zynq7000/src/ttc.rs
index 58a1cd5..cb5a8fb 100644
--- a/zynq/zynq7000/src/ttc.rs
+++ b/zynq/zynq7000/src/ttc.rs
@@ -142,7 +142,7 @@ pub struct EventCount {
     count: u16,
 }
 
-/// Triple-timer counter
+/// Triple-timer counter register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Ttc {
diff --git a/zynq/zynq7000/src/uart.rs b/zynq/zynq7000/src/uart.rs
index de94ff7..27fa845 100644
--- a/zynq/zynq7000/src/uart.rs
+++ b/zynq/zynq7000/src/uart.rs
@@ -278,6 +278,7 @@ impl InterruptStatus {
     }
 }
 
+/// UART register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Uart {
diff --git a/zynq/zynq7000/src/xadc.rs b/zynq/zynq7000/src/xadc.rs
index e80bf22..24dcb5e 100644
--- a/zynq/zynq7000/src/xadc.rs
+++ b/zynq/zynq7000/src/xadc.rs
@@ -1,5 +1,6 @@
 pub const XADC_BASE_ADDR: usize = 0xF8007100;
 
+/// XADC register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct XAdc {
-- 
2.43.0