diff --git a/.gitignore b/.gitignore index a2e6b44..8e6638e 100644 --- a/.gitignore +++ b/.gitignore @@ -1,7 +1,7 @@ target +xsct-output.log +app.map -/app.map -/xsct-output.log /.vscode /Cargo.lock /.cargo/config.toml diff --git a/zynq/zynq7000-hal/CHANGELOG.md b/zynq/zynq7000-hal/CHANGELOG.md index 7ffc55b..a519f72 100644 --- a/zynq/zynq7000-hal/CHANGELOG.md +++ b/zynq/zynq7000-hal/CHANGELOG.md @@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). # [unreleased] +# [v0.1.1] 2025-10-10 + +Documentation fixes. + # [v0.1.0] 2025-10-09 Initial release diff --git a/zynq/zynq7000-hal/Cargo.toml b/zynq/zynq7000-hal/Cargo.toml index 32a081d..1841a58 100644 --- a/zynq/zynq7000-hal/Cargo.toml +++ b/zynq/zynq7000-hal/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "zynq7000-hal" -version = "0.1.0" +version = "0.1.1" authors = ["Robin Mueller "] edition = "2024" description = "Hardware Abstraction Layer (HAL) for the Zynq7000 family of SoCs" @@ -52,4 +52,6 @@ approx = "0.5" [package.metadata.docs.rs] features = ["alloc"] +targets = ["armv7a-none-eabihf"] +cargo-args = ["-Z", "build-std=core"] rustdoc-args = ["--generate-link-to-definition"] diff --git a/zynq/zynq7000-mmu/CHANGELOG.md b/zynq/zynq7000-mmu/CHANGELOG.md index 932e63e..12cc3ee 100644 --- a/zynq/zynq7000-mmu/CHANGELOG.md +++ b/zynq/zynq7000-mmu/CHANGELOG.md @@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). # [unreleased] +# [v0.1.1] 2025-10-10 + +Documentation fixes. + # [v0.1.0] 2025-10-09 Initial release diff --git a/zynq/zynq7000-mmu/Cargo.toml b/zynq/zynq7000-mmu/Cargo.toml index 6536869..7b5c846 100644 --- a/zynq/zynq7000-mmu/Cargo.toml +++ b/zynq/zynq7000-mmu/Cargo.toml @@ -1,7 +1,7 @@ [package] name = "zynq7000-mmu" description = "Zynq7000 MMU structures" -version = "0.1.0" +version = "0.1.1" edition = "2024" license = "MIT OR Apache-2.0" homepage = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs" @@ -13,5 +13,13 @@ categories = ["embedded", "no-std", "hardware-support"] thiserror = { version = "2", default-features = false } cortex-ar = { version = "0.3" } +[build-dependencies] +arm-targets = { version = "0.3" } + [features] tools = [] + +[package.metadata.docs.rs] +targets = ["armv7a-none-eabihf"] +cargo-args = ["-Z", "build-std=core"] +rustdoc-args = ["--generate-link-to-definition"] diff --git a/zynq/zynq7000-mmu/README.md b/zynq/zynq7000-mmu/README.md index cc009ce..365d4d5 100644 --- a/zynq/zynq7000-mmu/README.md +++ b/zynq/zynq7000-mmu/README.md @@ -1,3 +1,7 @@ +[![Crates.io](https://img.shields.io/crates/v/zynq7000-mmu)](https://crates.io/crates/zynq7000-mmu) +[![docs.rs](https://img.shields.io/docsrs/zynq7000-mmu)](https://docs.rs/zynq7000-mmu) +[![ci](https://github.com/us-irs/zynq7000-rs/actions/workflows/ci.yml/badge.svg?branch=main)](https://github.com/us-irs/zynq7000-rs/actions/workflows/ci.yml) + Zynq7000 Memory Management Unit (MMU) library ========= diff --git a/zynq/zynq7000-mmu/build.rs b/zynq/zynq7000-mmu/build.rs new file mode 100644 index 0000000..c3ecdc6 --- /dev/null +++ b/zynq/zynq7000-mmu/build.rs @@ -0,0 +1,3 @@ +fn main() { + arm_targets::process(); +} diff --git a/zynq/zynq7000-mmu/src/lib.rs b/zynq/zynq7000-mmu/src/lib.rs index c8dfec6..a4056b4 100644 --- a/zynq/zynq7000-mmu/src/lib.rs +++ b/zynq/zynq7000-mmu/src/lib.rs @@ -7,7 +7,7 @@ use core::cell::UnsafeCell; use cortex_ar::mmu::L1Section; -#[cfg(not(feature = "tools"))] +#[cfg(all(not(feature = "tools"), arm_profile = "a"))] use cortex_ar::{ asm::{dsb, isb}, cache::clean_and_invalidate_l1_data_cache, @@ -39,7 +39,7 @@ impl L1TableRaw { self.0.as_mut_ptr() as *mut _ } - #[cfg(not(feature = "tools"))] + #[cfg(all(not(feature = "tools"), arm_profile = "a"))] pub fn update( &mut self, addr: u32, @@ -92,7 +92,7 @@ impl<'a> L1TableWrapper<'a> { } impl L1TableWrapper<'_> { - #[cfg(not(feature = "tools"))] + #[cfg(all(not(feature = "tools"), arm_profile = "a"))] pub fn update( &mut self, addr: u32, diff --git a/zynq/zynq7000-rt/Cargo.toml b/zynq/zynq7000-rt/Cargo.toml index 1f05ecf..27b61bd 100644 --- a/zynq/zynq7000-rt/Cargo.toml +++ b/zynq/zynq7000-rt/Cargo.toml @@ -16,9 +16,14 @@ cortex-ar = { version = "0.3" } arbitrary-int = "2" zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1" } +[build-dependencies] +arm-targets = { version = "0.3" } + [features] default = ["rt"] rt = ["dep:cortex-a-rt"] [package.metadata.docs.rs] +targets = ["armv7a-none-eabihf"] +cargo-args = ["-Z", "build-std=core"] rustdoc-args = ["--generate-link-to-definition"] diff --git a/zynq/zynq7000-rt/build.rs b/zynq/zynq7000-rt/build.rs new file mode 100644 index 0000000..c3ecdc6 --- /dev/null +++ b/zynq/zynq7000-rt/build.rs @@ -0,0 +1,3 @@ +fn main() { + arm_targets::process(); +} diff --git a/zynq/zynq7000-rt/src/lib.rs b/zynq/zynq7000-rt/src/lib.rs index b0efd60..55ad9eb 100644 --- a/zynq/zynq7000-rt/src/lib.rs +++ b/zynq/zynq7000-rt/src/lib.rs @@ -9,20 +9,20 @@ //! - Modification to the stack setup code, because a different linker script is used. #![no_std] #![cfg_attr(docsrs, feature(doc_cfg))] -#[cfg(feature = "rt")] +#[cfg(all(feature = "rt", arm_profile = "a"))] pub use cortex_a_rt::*; #[cfg(feature = "rt")] use zynq7000_mmu::L1TableWrapper; pub mod mmu; -#[cfg(feature = "rt")] +#[cfg(all(feature = "rt", arm_profile = "a"))] mod mmu_table; -#[cfg(feature = "rt")] +#[cfg(all(feature = "rt", arm_profile = "a"))] pub mod rt; /// Retrieves a mutable reference to the MMU L1 page table. -#[cfg(feature = "rt")] +#[cfg(all(feature = "rt", arm_profile = "a"))] pub fn mmu_l1_table_mut() -> L1TableWrapper<'static> { let mmu_table = mmu_table::MMU_L1_PAGE_TABLE.0.get(); // Safety: We retrieve a reference to the MMU page table singleton. diff --git a/zynq/zynq7000/Cargo.toml b/zynq/zynq7000/Cargo.toml index 9c60387..0b573af 100644 --- a/zynq/zynq7000/Cargo.toml +++ b/zynq/zynq7000/Cargo.toml @@ -23,4 +23,6 @@ once_cell = { version = "1", default-features = false, features = ["critical-sec approx = "0.5" [package.metadata.docs.rs] +targets = ["armv7a-none-eabihf"] +cargo-args = ["-Z", "build-std=core"] rustdoc-args = ["--generate-link-to-definition"]