diff --git a/zynq/zynq7000-hal/src/cache.rs b/zynq/zynq7000-hal/src/cache.rs
index 318b552..b6ffa7f 100644
--- a/zynq/zynq7000-hal/src/cache.rs
+++ b/zynq/zynq7000-hal/src/cache.rs
@@ -1,3 +1,7 @@
+//! # Cache management module
+//!
+//! A lot of cache maintenance operations for this SoC have to be performed on both the L1 and the
+//! L2 cache in the correct order. This module provides commonly required operations.
 use core::sync::atomic::compiler_fence;
 
 use cortex_ar::{
diff --git a/zynq/zynq7000-hal/src/clocks/mod.rs b/zynq/zynq7000-hal/src/clocks/mod.rs
index 74aeeff..7596824 100644
--- a/zynq/zynq7000-hal/src/clocks/mod.rs
+++ b/zynq/zynq7000-hal/src/clocks/mod.rs
@@ -1,4 +1,8 @@
-//! Clock module.
+//! # Clock module
+//!
+//! ## Examples
+//!
+//! - PLL initialization in [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
 use arbitrary_int::{prelude::*, u6};
 
 pub mod pll;
diff --git a/zynq/zynq7000-hal/src/ddr/mod.rs b/zynq/zynq7000-hal/src/ddr/mod.rs
index 825e648..f831968 100644
--- a/zynq/zynq7000-hal/src/ddr/mod.rs
+++ b/zynq/zynq7000-hal/src/ddr/mod.rs
@@ -1,3 +1,8 @@
+//! # DDR module
+//!
+//! ## Examples
+//!
+//! - [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
 use arbitrary_int::u6;
 use zynq7000::ddrc::MmioDdrController;
 
diff --git a/zynq/zynq7000-hal/src/devcfg.rs b/zynq/zynq7000-hal/src/devcfg.rs
index bbee0e6..5aee3d7 100644
--- a/zynq/zynq7000-hal/src/devcfg.rs
+++ b/zynq/zynq7000-hal/src/devcfg.rs
@@ -1,3 +1,4 @@
+//! # Device Configuration Module
 #[derive(Debug, thiserror::Error)]
 #[error("unaligned address: {0}")]
 pub struct UnalignedAddrError(usize);
diff --git a/zynq/zynq7000-hal/src/eth/mod.rs b/zynq/zynq7000-hal/src/eth/mod.rs
index 2565814..df194c6 100644
--- a/zynq/zynq7000-hal/src/eth/mod.rs
+++ b/zynq/zynq7000-hal/src/eth/mod.rs
@@ -1,3 +1,8 @@
+//! # Ethernet module
+//!
+//! ## Examples
+//!
+//! - [Zedboard Ethernet](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/ethernet.rs)
 use arbitrary_int::{u2, u3};
 pub use zynq7000::eth::MdcClockDivisor;
 use zynq7000::eth::{
diff --git a/zynq/zynq7000-hal/src/gic.rs b/zynq/zynq7000-hal/src/gic.rs
index 9b75816..12298fa 100644
--- a/zynq/zynq7000-hal/src/gic.rs
+++ b/zynq/zynq7000-hal/src/gic.rs
@@ -1,4 +1,4 @@
-//! Global Interrupt Controller (GIC) module.
+//! # Global Interrupt Controller (GIC) module
 //!
 //! The primary interface to configure and allow handling the interrupts are the
 //! [GicConfigurator] and the [GicInterruptHelper] structures.
@@ -191,9 +191,9 @@ pub struct InvalidSgiInterruptId(pub usize);
 ///
 /// The flow of using this controller is as follows:
 ///
-/// 1. Create the controller using [Self::new_with_init]. You can use the [zynq7000::PsPeripherals]
+/// 1. Create the controller using [Self::new_with_init]. You can use the [zynq7000::Peripherals]
 ///    structure or the [zynq7000::gic::GicCpuInterface::new_mmio] and [zynq7000::gic::GicDistributor::new_mmio]
-///    functions  to create the MMIO instances. The constructor configures all PL interrupts
+///    functions to retrieve the MMIO instances. The constructor configures all PL interrupts
 ///    sensivities to high-level sensitivity and configures all sensitivities which are expected
 ///    to have a certain value. It also sets the priority mask to 0xff by calling
 ///    [Self::set_priority_mask] to prevent masking of the interrupts.
diff --git a/zynq/zynq7000-hal/src/gpio/mod.rs b/zynq/zynq7000-hal/src/gpio/mod.rs
index 5b7702c..8728650 100644
--- a/zynq/zynq7000-hal/src/gpio/mod.rs
+++ b/zynq/zynq7000-hal/src/gpio/mod.rs
@@ -1,12 +1,12 @@
-//! GPIO support module for the Zynq7000 SoC.
+//! # GPIO module
 //!
 //! This module contains a MIO and EMIO pin resource managements singleton as well as abstractions
 //! to use these pins as GPIOs.
 //!
 //! # Examples
 //!
-//! - [Blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/main.rs)
-//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/logger.rs)
+//! - [Blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/main.rs)
+//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
 //!   which uses MIO pins for the UART.
 pub mod emio;
 pub mod ll;
diff --git a/zynq/zynq7000-hal/src/gtc.rs b/zynq/zynq7000-hal/src/gtc.rs
index a59989a..c4e1de5 100644
--- a/zynq/zynq7000-hal/src/gtc.rs
+++ b/zynq/zynq7000-hal/src/gtc.rs
@@ -1,9 +1,9 @@
-//! Global timer counter driver module.
+//! # Global timer counter driver module
 //!
-//! # Examples
+//! ## Examples
 //!
-//! - [GTC ticks example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/gtc-ticks.rs)
-//! - [Embassy Timer Driver](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq7000-embassy/src/lib.rs)
+//! - [GTC ticks example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/gtc-ticks.rs)
+//! - [Embassy Timer Driver](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zynq7000-embassy/src/lib.rs)
 use zynq7000::gtc::MmioGlobalTimerCounter;
 
 use crate::{clocks::ArmClocks, time::Hertz};
diff --git a/zynq/zynq7000-hal/src/i2c.rs b/zynq/zynq7000-hal/src/i2c.rs
index fa3185e..c35b41b 100644
--- a/zynq/zynq7000-hal/src/i2c.rs
+++ b/zynq/zynq7000-hal/src/i2c.rs
@@ -1,3 +1,4 @@
+//! # I2C module
 use arbitrary_int::{u2, u3, u6};
 use embedded_hal::i2c::NoAcknowledgeSource;
 use zynq7000::{
diff --git a/zynq/zynq7000-hal/src/l2_cache.rs b/zynq/zynq7000-hal/src/l2_cache.rs
index 5a6c4a0..f41ad3c 100644
--- a/zynq/zynq7000-hal/src/l2_cache.rs
+++ b/zynq/zynq7000-hal/src/l2_cache.rs
@@ -1,3 +1,4 @@
+//! # L2 cache module
 use core::sync::atomic::compiler_fence;
 
 use arbitrary_int::{u2, u3};
diff --git a/zynq/zynq7000-hal/src/lib.rs b/zynq/zynq7000-hal/src/lib.rs
index f21c1b1..e72afba 100644
--- a/zynq/zynq7000-hal/src/lib.rs
+++ b/zynq/zynq7000-hal/src/lib.rs
@@ -7,6 +7,11 @@
 //! raw PAC. This crate also implements traits specified by the
 //! [embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with
 //! various drivers in the embedded rust ecosystem.
+//!
+//! ## Examples
+//!
+//! All exaples can be found inside the [examples folder](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples)
+//! of the project
 #![no_std]
 #![cfg_attr(docsrs, feature(doc_cfg))]
 
diff --git a/zynq/zynq7000-hal/src/log.rs b/zynq/zynq7000-hal/src/log.rs
index 6593365..a62204c 100644
--- a/zynq/zynq7000-hal/src/log.rs
+++ b/zynq/zynq7000-hal/src/log.rs
@@ -1,4 +1,9 @@
-//! # Simple logging providers.
+//! # Simple logging providers
+//!
+//! ## Examples
+//!
+//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
+//!   which uses MIO pins for the UART.
 
 use core::sync::atomic::{AtomicBool, AtomicU8};
 
diff --git a/zynq/zynq7000-hal/src/priv_tim.rs b/zynq/zynq7000-hal/src/priv_tim.rs
index d5f8e08..02e883c 100644
--- a/zynq/zynq7000-hal/src/priv_tim.rs
+++ b/zynq/zynq7000-hal/src/priv_tim.rs
@@ -1,3 +1,8 @@
+//! # CPU private timer module
+//!
+//! ## Examples
+//!
+//! - Private timer as delay provider in [blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/blinky.rs)
 use core::{marker::PhantomData, sync::atomic::AtomicBool};
 
 use zynq7000::priv_tim::InterruptStatus;
diff --git a/zynq/zynq7000-hal/src/qspi/mod.rs b/zynq/zynq7000-hal/src/qspi/mod.rs
index c7c3528..e195dd3 100644
--- a/zynq/zynq7000-hal/src/qspi/mod.rs
+++ b/zynq/zynq7000-hal/src/qspi/mod.rs
@@ -1,3 +1,8 @@
+//! # QSPI module
+//!
+//! ## Examples
+//!
+//! - [Zedboard QSPI](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/qspi.rs)
 use core::ops::{Deref, DerefMut};
 
 use arbitrary_int::{prelude::*, u2, u3, u6};
diff --git a/zynq/zynq7000-hal/src/slcr.rs b/zynq/zynq7000-hal/src/slcr.rs
index 20cd90d..c4b5f45 100644
--- a/zynq/zynq7000-hal/src/slcr.rs
+++ b/zynq/zynq7000-hal/src/slcr.rs
@@ -1,4 +1,4 @@
-//! # System Level Control Register (SLCR) module.
+//! # System Level Control Register (SLCR) module
 use zynq7000::slcr::MmioSlcr;
 
 pub const LOCK_KEY: u32 = 0x767B;
diff --git a/zynq/zynq7000-hal/src/spi/mod.rs b/zynq/zynq7000-hal/src/spi/mod.rs
index faba759..80d6a2c 100644
--- a/zynq/zynq7000-hal/src/spi/mod.rs
+++ b/zynq/zynq7000-hal/src/spi/mod.rs
@@ -1,4 +1,8 @@
-//! PS SPI HAL driver.
+//! SPI module
+//!
+//! ## Examples
+//!
+//! - [L3GD20H SPI sensor](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/l3gd20h-spi-mio.rs)
 use core::convert::Infallible;
 
 use crate::clocks::Clocks;
diff --git a/zynq/zynq7000-hal/src/time.rs b/zynq/zynq7000-hal/src/time.rs
index a61724c..0cfcf6d 100644
--- a/zynq/zynq7000-hal/src/time.rs
+++ b/zynq/zynq7000-hal/src/time.rs
@@ -1,4 +1,4 @@
-//! Time units
+//! # Time units
 
 // Frequency based
 
diff --git a/zynq/zynq7000-hal/src/ttc.rs b/zynq/zynq7000-hal/src/ttc.rs
index 3375df9..ec0e435 100644
--- a/zynq/zynq7000-hal/src/ttc.rs
+++ b/zynq/zynq7000-hal/src/ttc.rs
@@ -1,6 +1,10 @@
-//! Triple-timer counter (TTC) high-level driver.
+//! # Triple-timer counter (TTC) high-level driver
 //!
 //! This module also contains support for PWM and output waveform generation.
+//!
+//! ## Examples
+//!
+//! - [PWM](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/embassy/src/bin/pwm.rs)
 
 use core::convert::Infallible;
 
diff --git a/zynq/zynq7000-hal/src/uart/mod.rs b/zynq/zynq7000-hal/src/uart/mod.rs
index ba9e99d..46a10bc 100644
--- a/zynq/zynq7000-hal/src/uart/mod.rs
+++ b/zynq/zynq7000-hal/src/uart/mod.rs
@@ -1,6 +1,12 @@
-//! # UART module.
+//! # UART module
 //!
 //! Support for the processing system UARTs.
+//!
+//! ## Examples
+//!
+//! - [Logger through UART](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
+//! - [Zedboard Blocking UART](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/uart-blocking.rs)
+//! - [Zedboard Non-Blocking UART](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/uart-non-blocking.rs)
 use core::convert::Infallible;
 
 use arbitrary_int::u3;