From dd97bc3177e6e9d8c18986a351b9dafabd0767a1 Mon Sep 17 00:00:00 2001
From: Jakob Meier <meierj@irs.uni-stuttgart.de>
Date: Fri, 6 Mar 2026 13:15:57 +0100
Subject: [PATCH] corrected bit positions of qspi reset register

---
 firmware/zynq7000/src/slcr/reset.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/firmware/zynq7000/src/slcr/reset.rs b/firmware/zynq7000/src/slcr/reset.rs
index 8275ad5..5bff33d 100644
--- a/firmware/zynq7000/src/slcr/reset.rs
+++ b/firmware/zynq7000/src/slcr/reset.rs
@@ -50,9 +50,9 @@ pub struct EthernetReset {
 
 #[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct QspiResetControl {
-    #[bit(2, rw)]
-    qspi_ref_reset: bool,
     #[bit(1, rw)]
+    qspi_ref_reset: bool,
+    #[bit(0, rw)]
     cpu_1x_reset: bool,
 }
 
-- 
2.43.0