diff --git a/firmware/zynq7000-hal/src/uart/rx.rs b/firmware/zynq7000-hal/src/uart/rx.rs
index 0ea352b..f1639f6 100644
--- a/firmware/zynq7000-hal/src/uart/rx.rs
+++ b/firmware/zynq7000-hal/src/uart/rx.rs
@@ -2,7 +2,7 @@
 use core::convert::Infallible;
 
 use arbitrary_int::prelude::*;
-use zynq7000::uart::{InterruptControl, InterruptStatus, MmioRegisters};
+use zynq7000::uart::{InterruptControl, InterruptStatus, MmioRegisters, FifoTrigger};
 
 use super::FIFO_DEPTH;
 
@@ -120,6 +120,13 @@ impl Rx {
         self.enable_interrupts();
     }
 
+    /// Sets the RX FIFO trigger level.
+    pub fn set_rx_fifo_trigger_level(&mut self, level: u8) {
+        self.regs.write_rx_fifo_trigger(FifoTrigger::new_with_raw_value(
+            level as u32,
+        ));
+    }
+
     /// Enables all interrupts relevant for the RX side of the UART.
     ///
     /// It is recommended to also clear all interrupts immediately after enabling them.